1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce_clocks.h" 27 #include "dm_services.h" 28 #include "reg_helper.h" 29 #include "fixed31_32.h" 30 #include "bios_parser_interface.h" 31 #include "dc.h" 32 #include "dmcu.h" 33 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 34 #include "dcn_calcs.h" 35 #endif 36 #include "core_types.h" 37 #include "dc_types.h" 38 #include "dal_asic_id.h" 39 40 #define TO_DCE_CLOCKS(clocks)\ 41 container_of(clocks, struct dce_dccg, base) 42 43 #define REG(reg) \ 44 (clk_dce->regs->reg) 45 46 #undef FN 47 #define FN(reg_name, field_name) \ 48 clk_dce->clk_shift->field_name, clk_dce->clk_mask->field_name 49 50 #define CTX \ 51 clk_dce->base.ctx 52 #define DC_LOGGER \ 53 clk->ctx->logger 54 55 /* Max clock values for each state indexed by "enum clocks_state": */ 56 static const struct state_dependent_clocks dce80_max_clks_by_state[] = { 57 /* ClocksStateInvalid - should not be used */ 58 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 59 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */ 60 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 61 /* ClocksStateLow */ 62 { .display_clk_khz = 352000, .pixel_clk_khz = 330000}, 63 /* ClocksStateNominal */ 64 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 }, 65 /* ClocksStatePerformance */ 66 { .display_clk_khz = 600000, .pixel_clk_khz = 400000 } }; 67 68 static const struct state_dependent_clocks dce110_max_clks_by_state[] = { 69 /*ClocksStateInvalid - should not be used*/ 70 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 71 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ 72 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, 73 /*ClocksStateLow*/ 74 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, 75 /*ClocksStateNominal*/ 76 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, 77 /*ClocksStatePerformance*/ 78 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; 79 80 static const struct state_dependent_clocks dce112_max_clks_by_state[] = { 81 /*ClocksStateInvalid - should not be used*/ 82 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 83 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ 84 { .display_clk_khz = 389189, .pixel_clk_khz = 346672 }, 85 /*ClocksStateLow*/ 86 { .display_clk_khz = 459000, .pixel_clk_khz = 400000 }, 87 /*ClocksStateNominal*/ 88 { .display_clk_khz = 667000, .pixel_clk_khz = 600000 }, 89 /*ClocksStatePerformance*/ 90 { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; 91 92 static const struct state_dependent_clocks dce120_max_clks_by_state[] = { 93 /*ClocksStateInvalid - should not be used*/ 94 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 95 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ 96 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 97 /*ClocksStateLow*/ 98 { .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, 99 /*ClocksStateNominal*/ 100 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, 101 /*ClocksStatePerformance*/ 102 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; 103 104 /* Starting DID for each range */ 105 enum dentist_base_divider_id { 106 DENTIST_BASE_DID_1 = 0x08, 107 DENTIST_BASE_DID_2 = 0x40, 108 DENTIST_BASE_DID_3 = 0x60, 109 DENTIST_BASE_DID_4 = 0x7e, 110 DENTIST_MAX_DID = 0x7f 111 }; 112 113 /* Starting point and step size for each divider range.*/ 114 enum dentist_divider_range { 115 DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */ 116 DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */ 117 DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */ 118 DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */ 119 DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */ 120 DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */ 121 DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */ 122 DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */ 123 DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4 124 }; 125 126 static int dentist_get_divider_from_did(int did) 127 { 128 if (did < DENTIST_BASE_DID_1) 129 did = DENTIST_BASE_DID_1; 130 if (did > DENTIST_MAX_DID) 131 did = DENTIST_MAX_DID; 132 133 if (did < DENTIST_BASE_DID_2) { 134 return DENTIST_DIVIDER_RANGE_1_START + DENTIST_DIVIDER_RANGE_1_STEP 135 * (did - DENTIST_BASE_DID_1); 136 } else if (did < DENTIST_BASE_DID_3) { 137 return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP 138 * (did - DENTIST_BASE_DID_2); 139 } else if (did < DENTIST_BASE_DID_4) { 140 return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP 141 * (did - DENTIST_BASE_DID_3); 142 } else { 143 return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP 144 * (did - DENTIST_BASE_DID_4); 145 } 146 } 147 148 /* SW will adjust DP REF Clock average value for all purposes 149 * (DP DTO / DP Audio DTO and DP GTC) 150 if clock is spread for all cases: 151 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW 152 calculations for DS_INCR/DS_MODULO (this is planned to be default case) 153 -if SS enabled on DP Ref clock and HW de-spreading enabled with HW 154 calculations (not planned to be used, but average clock should still 155 be valid) 156 -if SS enabled on DP Ref clock and HW de-spreading disabled 157 (should not be case with CIK) then SW should program all rates 158 generated according to average value (case as with previous ASICs) 159 */ 160 static int dccg_adjust_dp_ref_freq_for_ss(struct dce_dccg *clk_dce, int dp_ref_clk_khz) 161 { 162 if (clk_dce->ss_on_dprefclk && clk_dce->dprefclk_ss_divider != 0) { 163 struct fixed31_32 ss_percentage = dc_fixpt_div_int( 164 dc_fixpt_from_fraction(clk_dce->dprefclk_ss_percentage, 165 clk_dce->dprefclk_ss_divider), 200); 166 struct fixed31_32 adj_dp_ref_clk_khz; 167 168 ss_percentage = dc_fixpt_sub(dc_fixpt_one, ss_percentage); 169 adj_dp_ref_clk_khz = dc_fixpt_mul_int(ss_percentage, dp_ref_clk_khz); 170 dp_ref_clk_khz = dc_fixpt_floor(adj_dp_ref_clk_khz); 171 } 172 return dp_ref_clk_khz; 173 } 174 175 static int dce_get_dp_ref_freq_khz(struct dccg *clk) 176 { 177 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 178 int dprefclk_wdivider; 179 int dprefclk_src_sel; 180 int dp_ref_clk_khz = 600000; 181 int target_div; 182 183 /* ASSERT DP Reference Clock source is from DFS*/ 184 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); 185 ASSERT(dprefclk_src_sel == 0); 186 187 /* Read the mmDENTIST_DISPCLK_CNTL to get the currently 188 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/ 189 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); 190 191 /* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/ 192 target_div = dentist_get_divider_from_did(dprefclk_wdivider); 193 194 /* Calculate the current DFS clock, in kHz.*/ 195 dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR 196 * clk_dce->dentist_vco_freq_khz) / target_div; 197 198 return dccg_adjust_dp_ref_freq_for_ss(clk_dce, dp_ref_clk_khz); 199 } 200 201 static int dce12_get_dp_ref_freq_khz(struct dccg *clk) 202 { 203 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 204 205 return dccg_adjust_dp_ref_freq_for_ss(clk_dce, 600000); 206 } 207 208 static enum dm_pp_clocks_state dce_get_required_clocks_state( 209 struct dccg *clk, 210 struct dc_clocks *req_clocks) 211 { 212 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 213 int i; 214 enum dm_pp_clocks_state low_req_clk; 215 216 /* Iterate from highest supported to lowest valid state, and update 217 * lowest RequiredState with the lowest state that satisfies 218 * all required clocks 219 */ 220 for (i = clk->max_clks_state; i >= DM_PP_CLOCKS_STATE_ULTRA_LOW; i--) 221 if (req_clocks->dispclk_khz > 222 clk_dce->max_clks_by_state[i].display_clk_khz 223 || req_clocks->phyclk_khz > 224 clk_dce->max_clks_by_state[i].pixel_clk_khz) 225 break; 226 227 low_req_clk = i + 1; 228 if (low_req_clk > clk->max_clks_state) { 229 /* set max clock state for high phyclock, invalid on exceeding display clock */ 230 if (clk_dce->max_clks_by_state[clk->max_clks_state].display_clk_khz 231 < req_clocks->dispclk_khz) 232 low_req_clk = DM_PP_CLOCKS_STATE_INVALID; 233 else 234 low_req_clk = clk->max_clks_state; 235 } 236 237 return low_req_clk; 238 } 239 240 static int dce_set_clock( 241 struct dccg *clk, 242 int requested_clk_khz) 243 { 244 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 245 struct bp_pixel_clock_parameters pxl_clk_params = { 0 }; 246 struct dc_bios *bp = clk->ctx->dc_bios; 247 int actual_clock = requested_clk_khz; 248 249 /* Make sure requested clock isn't lower than minimum threshold*/ 250 if (requested_clk_khz > 0) 251 requested_clk_khz = max(requested_clk_khz, 252 clk_dce->dentist_vco_freq_khz / 64); 253 254 /* Prepare to program display clock*/ 255 pxl_clk_params.target_pixel_clock = requested_clk_khz; 256 pxl_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 257 258 bp->funcs->program_display_engine_pll(bp, &pxl_clk_params); 259 260 if (clk_dce->dfs_bypass_enabled) { 261 262 /* Cache the fixed display clock*/ 263 clk_dce->dfs_bypass_disp_clk = 264 pxl_clk_params.dfs_bypass_display_clock; 265 actual_clock = pxl_clk_params.dfs_bypass_display_clock; 266 } 267 268 /* from power down, we need mark the clock state as ClocksStateNominal 269 * from HWReset, so when resume we will call pplib voltage regulator.*/ 270 if (requested_clk_khz == 0) 271 clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; 272 return actual_clock; 273 } 274 275 static int dce_psr_set_clock( 276 struct dccg *clk, 277 int requested_clk_khz) 278 { 279 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 280 struct dc_context *ctx = clk_dce->base.ctx; 281 struct dc *core_dc = ctx->dc; 282 struct dmcu *dmcu = core_dc->res_pool->dmcu; 283 int actual_clk_khz = requested_clk_khz; 284 285 actual_clk_khz = dce_set_clock(clk, requested_clk_khz); 286 287 dmcu->funcs->set_psr_wait_loop(dmcu, actual_clk_khz / 1000 / 7); 288 return actual_clk_khz; 289 } 290 291 static int dce112_set_clock( 292 struct dccg *clk, 293 int requested_clk_khz) 294 { 295 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); 296 struct bp_set_dce_clock_parameters dce_clk_params; 297 struct dc_bios *bp = clk->ctx->dc_bios; 298 struct dc *core_dc = clk->ctx->dc; 299 struct dmcu *dmcu = core_dc->res_pool->dmcu; 300 int actual_clock = requested_clk_khz; 301 /* Prepare to program display clock*/ 302 memset(&dce_clk_params, 0, sizeof(dce_clk_params)); 303 304 /* Make sure requested clock isn't lower than minimum threshold*/ 305 if (requested_clk_khz > 0) 306 requested_clk_khz = max(requested_clk_khz, 307 clk_dce->dentist_vco_freq_khz / 62); 308 309 dce_clk_params.target_clock_frequency = requested_clk_khz; 310 dce_clk_params.pll_id = CLOCK_SOURCE_ID_DFS; 311 dce_clk_params.clock_type = DCECLOCK_TYPE_DISPLAY_CLOCK; 312 313 bp->funcs->set_dce_clock(bp, &dce_clk_params); 314 actual_clock = dce_clk_params.target_clock_frequency; 315 316 /* from power down, we need mark the clock state as ClocksStateNominal 317 * from HWReset, so when resume we will call pplib voltage regulator.*/ 318 if (requested_clk_khz == 0) 319 clk->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; 320 321 /*Program DP ref Clock*/ 322 /*VBIOS will determine DPREFCLK frequency, so we don't set it*/ 323 dce_clk_params.target_clock_frequency = 0; 324 dce_clk_params.clock_type = DCECLOCK_TYPE_DPREFCLK; 325 if (!ASICREV_IS_VEGA20_P(clk->ctx->asic_id.hw_internal_rev)) 326 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = 327 (dce_clk_params.pll_id == 328 CLOCK_SOURCE_COMBO_DISPLAY_PLL0); 329 else 330 dce_clk_params.flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK = false; 331 332 bp->funcs->set_dce_clock(bp, &dce_clk_params); 333 334 if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) { 335 if (clk_dce->dfs_bypass_disp_clk != actual_clock) 336 dmcu->funcs->set_psr_wait_loop(dmcu, 337 actual_clock / 1000 / 7); 338 } 339 340 clk_dce->dfs_bypass_disp_clk = actual_clock; 341 return actual_clock; 342 } 343 344 static void dce_clock_read_integrated_info(struct dce_dccg *clk_dce) 345 { 346 struct dc_debug_options *debug = &clk_dce->base.ctx->dc->debug; 347 struct dc_bios *bp = clk_dce->base.ctx->dc_bios; 348 struct integrated_info info = { { { 0 } } }; 349 struct dc_firmware_info fw_info = { { 0 } }; 350 int i; 351 352 if (bp->integrated_info) 353 info = *bp->integrated_info; 354 355 clk_dce->dentist_vco_freq_khz = info.dentist_vco_freq; 356 if (clk_dce->dentist_vco_freq_khz == 0) { 357 bp->funcs->get_firmware_info(bp, &fw_info); 358 clk_dce->dentist_vco_freq_khz = 359 fw_info.smu_gpu_pll_output_freq; 360 if (clk_dce->dentist_vco_freq_khz == 0) 361 clk_dce->dentist_vco_freq_khz = 3600000; 362 } 363 364 /*update the maximum display clock for each power state*/ 365 for (i = 0; i < NUMBER_OF_DISP_CLK_VOLTAGE; ++i) { 366 enum dm_pp_clocks_state clk_state = DM_PP_CLOCKS_STATE_INVALID; 367 368 switch (i) { 369 case 0: 370 clk_state = DM_PP_CLOCKS_STATE_ULTRA_LOW; 371 break; 372 373 case 1: 374 clk_state = DM_PP_CLOCKS_STATE_LOW; 375 break; 376 377 case 2: 378 clk_state = DM_PP_CLOCKS_STATE_NOMINAL; 379 break; 380 381 case 3: 382 clk_state = DM_PP_CLOCKS_STATE_PERFORMANCE; 383 break; 384 385 default: 386 clk_state = DM_PP_CLOCKS_STATE_INVALID; 387 break; 388 } 389 390 /*Do not allow bad VBIOS/SBIOS to override with invalid values, 391 * check for > 100MHz*/ 392 if (info.disp_clk_voltage[i].max_supported_clk >= 100000) 393 clk_dce->max_clks_by_state[clk_state].display_clk_khz = 394 info.disp_clk_voltage[i].max_supported_clk; 395 } 396 397 if (!debug->disable_dfs_bypass && bp->integrated_info) 398 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) 399 clk_dce->dfs_bypass_enabled = true; 400 } 401 402 static void dce_clock_read_ss_info(struct dce_dccg *clk_dce) 403 { 404 struct dc_bios *bp = clk_dce->base.ctx->dc_bios; 405 int ss_info_num = bp->funcs->get_ss_entry_number( 406 bp, AS_SIGNAL_TYPE_GPU_PLL); 407 408 if (ss_info_num) { 409 struct spread_spectrum_info info = { { 0 } }; 410 enum bp_result result = bp->funcs->get_spread_spectrum_info( 411 bp, AS_SIGNAL_TYPE_GPU_PLL, 0, &info); 412 413 /* Based on VBIOS, VBIOS will keep entry for GPU PLL SS 414 * even if SS not enabled and in that case 415 * SSInfo.spreadSpectrumPercentage !=0 would be sign 416 * that SS is enabled 417 */ 418 if (result == BP_RESULT_OK && 419 info.spread_spectrum_percentage != 0) { 420 clk_dce->ss_on_dprefclk = true; 421 clk_dce->dprefclk_ss_divider = info.spread_percentage_divider; 422 423 if (info.type.CENTER_MODE == 0) { 424 /* TODO: Currently for DP Reference clock we 425 * need only SS percentage for 426 * downspread */ 427 clk_dce->dprefclk_ss_percentage = 428 info.spread_spectrum_percentage; 429 } 430 431 return; 432 } 433 434 result = bp->funcs->get_spread_spectrum_info( 435 bp, AS_SIGNAL_TYPE_DISPLAY_PORT, 0, &info); 436 437 /* Based on VBIOS, VBIOS will keep entry for DPREFCLK SS 438 * even if SS not enabled and in that case 439 * SSInfo.spreadSpectrumPercentage !=0 would be sign 440 * that SS is enabled 441 */ 442 if (result == BP_RESULT_OK && 443 info.spread_spectrum_percentage != 0) { 444 clk_dce->ss_on_dprefclk = true; 445 clk_dce->dprefclk_ss_divider = info.spread_percentage_divider; 446 447 if (info.type.CENTER_MODE == 0) { 448 /* Currently for DP Reference clock we 449 * need only SS percentage for 450 * downspread */ 451 clk_dce->dprefclk_ss_percentage = 452 info.spread_spectrum_percentage; 453 } 454 } 455 } 456 } 457 458 static inline bool should_set_clock(bool safe_to_lower, int calc_clk, int cur_clk) 459 { 460 return ((safe_to_lower && calc_clk < cur_clk) || calc_clk > cur_clk); 461 } 462 463 static void dce12_update_clocks(struct dccg *dccg, 464 struct dc_clocks *new_clocks, 465 bool safe_to_lower) 466 { 467 struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; 468 469 /* TODO: Investigate why this is needed to fix display corruption. */ 470 new_clocks->dispclk_khz = new_clocks->dispclk_khz * 115 / 100; 471 472 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { 473 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; 474 clock_voltage_req.clocks_in_khz = new_clocks->dispclk_khz; 475 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); 476 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; 477 478 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); 479 } 480 481 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) { 482 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; 483 clock_voltage_req.clocks_in_khz = new_clocks->phyclk_khz; 484 dccg->clks.phyclk_khz = new_clocks->phyclk_khz; 485 486 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); 487 } 488 } 489 490 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 491 static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks) 492 { 493 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 494 bool dispclk_increase = new_clocks->dispclk_khz > dccg->clks.dispclk_khz; 495 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz; 496 bool cur_dpp_div = dccg->clks.dispclk_khz > dccg->clks.dppclk_khz; 497 498 /* increase clock, looking for div is 0 for current, request div is 1*/ 499 if (dispclk_increase) { 500 /* already divided by 2, no need to reach target clk with 2 steps*/ 501 if (cur_dpp_div) 502 return new_clocks->dispclk_khz; 503 504 /* request disp clk is lower than maximum supported dpp clk, 505 * no need to reach target clk with two steps. 506 */ 507 if (new_clocks->dispclk_khz <= disp_clk_threshold) 508 return new_clocks->dispclk_khz; 509 510 /* target dpp clk not request divided by 2, still within threshold */ 511 if (!request_dpp_div) 512 return new_clocks->dispclk_khz; 513 514 } else { 515 /* decrease clock, looking for current dppclk divided by 2, 516 * request dppclk not divided by 2. 517 */ 518 519 /* current dpp clk not divided by 2, no need to ramp*/ 520 if (!cur_dpp_div) 521 return new_clocks->dispclk_khz; 522 523 /* current disp clk is lower than current maximum dpp clk, 524 * no need to ramp 525 */ 526 if (dccg->clks.dispclk_khz <= disp_clk_threshold) 527 return new_clocks->dispclk_khz; 528 529 /* request dpp clk need to be divided by 2 */ 530 if (request_dpp_div) 531 return new_clocks->dispclk_khz; 532 } 533 534 return disp_clk_threshold; 535 } 536 537 static void dcn1_ramp_up_dispclk_with_dpp(struct dccg *dccg, struct dc_clocks *new_clocks) 538 { 539 struct dc *dc = dccg->ctx->dc; 540 int dispclk_to_dpp_threshold = dcn1_determine_dppclk_threshold(dccg, new_clocks); 541 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; 542 int i; 543 544 /* set disp clk to dpp clk threshold */ 545 dccg->funcs->set_dispclk(dccg, dispclk_to_dpp_threshold); 546 547 /* update request dpp clk division option */ 548 for (i = 0; i < dc->res_pool->pipe_count; i++) { 549 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; 550 551 if (!pipe_ctx->plane_state) 552 continue; 553 554 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control( 555 pipe_ctx->plane_res.dpp, 556 request_dpp_div, 557 true); 558 } 559 560 /* If target clk not same as dppclk threshold, set to target clock */ 561 if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz) 562 dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); 563 564 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; 565 dccg->clks.dppclk_khz = new_clocks->dppclk_khz; 566 dccg->clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz; 567 } 568 569 static void dcn1_update_clocks(struct dccg *dccg, 570 struct dc_clocks *new_clocks, 571 bool safe_to_lower) 572 { 573 struct dc *dc = dccg->ctx->dc; 574 struct pp_smu_display_requirement_rv *smu_req_cur = 575 &dc->res_pool->pp_smu_req; 576 struct pp_smu_display_requirement_rv smu_req = *smu_req_cur; 577 struct pp_smu_funcs_rv *pp_smu = dc->res_pool->pp_smu; 578 struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; 579 bool send_request_to_increase = false; 580 bool send_request_to_lower = false; 581 582 if (new_clocks->phyclk_khz) 583 smu_req.display_count = 1; 584 else 585 smu_req.display_count = 0; 586 587 if (new_clocks->dispclk_khz > dccg->clks.dispclk_khz 588 || new_clocks->phyclk_khz > dccg->clks.phyclk_khz 589 || new_clocks->fclk_khz > dccg->clks.fclk_khz 590 || new_clocks->dcfclk_khz > dccg->clks.dcfclk_khz) 591 send_request_to_increase = true; 592 593 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, dccg->clks.phyclk_khz)) { 594 dccg->clks.phyclk_khz = new_clocks->phyclk_khz; 595 596 send_request_to_lower = true; 597 } 598 599 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, dccg->clks.fclk_khz)) { 600 dccg->clks.fclk_khz = new_clocks->fclk_khz; 601 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_FCLK; 602 clock_voltage_req.clocks_in_khz = new_clocks->fclk_khz; 603 smu_req.hard_min_fclk_khz = new_clocks->fclk_khz; 604 605 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); 606 send_request_to_lower = true; 607 } 608 609 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, dccg->clks.dcfclk_khz)) { 610 dccg->clks.dcfclk_khz = new_clocks->dcfclk_khz; 611 smu_req.hard_min_dcefclk_khz = new_clocks->dcfclk_khz; 612 613 send_request_to_lower = true; 614 } 615 616 if (should_set_clock(safe_to_lower, 617 new_clocks->dcfclk_deep_sleep_khz, dccg->clks.dcfclk_deep_sleep_khz)) { 618 dccg->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz; 619 smu_req.min_deep_sleep_dcefclk_mhz = new_clocks->dcfclk_deep_sleep_khz; 620 621 send_request_to_lower = true; 622 } 623 624 /* make sure dcf clk is before dpp clk to 625 * make sure we have enough voltage to run dpp clk 626 */ 627 if (send_request_to_increase) { 628 /*use dcfclk to request voltage*/ 629 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 630 clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); 631 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); 632 if (pp_smu->set_display_requirement) 633 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); 634 } 635 636 /* dcn1 dppclk is tied to dispclk */ 637 /* program dispclk on = as a w/a for sleep resume clock ramping issues */ 638 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz) 639 || new_clocks->dispclk_khz == dccg->clks.dispclk_khz) { 640 dcn1_ramp_up_dispclk_with_dpp(dccg, new_clocks); 641 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; 642 643 send_request_to_lower = true; 644 } 645 646 if (!send_request_to_increase && send_request_to_lower) { 647 /*use dcfclk to request voltage*/ 648 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; 649 clock_voltage_req.clocks_in_khz = dcn_find_dcfclk_suits_all(dc, new_clocks); 650 dm_pp_apply_clock_for_voltage_request(dccg->ctx, &clock_voltage_req); 651 if (pp_smu->set_display_requirement) 652 pp_smu->set_display_requirement(&pp_smu->pp_smu, &smu_req); 653 } 654 655 656 *smu_req_cur = smu_req; 657 } 658 #endif 659 660 static void dce_update_clocks(struct dccg *dccg, 661 struct dc_clocks *new_clocks, 662 bool safe_to_lower) 663 { 664 struct dm_pp_power_level_change_request level_change_req; 665 666 level_change_req.power_level = dce_get_required_clocks_state(dccg, new_clocks); 667 /* get max clock state from PPLIB */ 668 if ((level_change_req.power_level < dccg->cur_min_clks_state && safe_to_lower) 669 || level_change_req.power_level > dccg->cur_min_clks_state) { 670 if (dm_pp_apply_power_level_change_request(dccg->ctx, &level_change_req)) 671 dccg->cur_min_clks_state = level_change_req.power_level; 672 } 673 674 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, dccg->clks.dispclk_khz)) { 675 new_clocks->dispclk_khz = dccg->funcs->set_dispclk(dccg, new_clocks->dispclk_khz); 676 dccg->clks.dispclk_khz = new_clocks->dispclk_khz; 677 } 678 } 679 680 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 681 static const struct display_clock_funcs dcn1_funcs = { 682 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 683 .set_dispclk = dce112_set_clock, 684 .update_clocks = dcn1_update_clocks 685 }; 686 #endif 687 688 static const struct display_clock_funcs dce120_funcs = { 689 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, 690 .set_dispclk = dce112_set_clock, 691 .update_clocks = dce12_update_clocks 692 }; 693 694 static const struct display_clock_funcs dce112_funcs = { 695 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, 696 .set_dispclk = dce112_set_clock, 697 .update_clocks = dce_update_clocks 698 }; 699 700 static const struct display_clock_funcs dce110_funcs = { 701 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, 702 .set_dispclk = dce_psr_set_clock, 703 .update_clocks = dce_update_clocks 704 }; 705 706 static const struct display_clock_funcs dce_funcs = { 707 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, 708 .set_dispclk = dce_set_clock, 709 .update_clocks = dce_update_clocks 710 }; 711 712 static void dce_dccg_construct( 713 struct dce_dccg *clk_dce, 714 struct dc_context *ctx, 715 const struct dccg_registers *regs, 716 const struct dccg_shift *clk_shift, 717 const struct dccg_mask *clk_mask) 718 { 719 struct dccg *base = &clk_dce->base; 720 721 base->ctx = ctx; 722 base->funcs = &dce_funcs; 723 724 clk_dce->regs = regs; 725 clk_dce->clk_shift = clk_shift; 726 clk_dce->clk_mask = clk_mask; 727 728 clk_dce->dfs_bypass_disp_clk = 0; 729 730 clk_dce->dprefclk_ss_percentage = 0; 731 clk_dce->dprefclk_ss_divider = 1000; 732 clk_dce->ss_on_dprefclk = false; 733 734 base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL; 735 base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID; 736 737 dce_clock_read_integrated_info(clk_dce); 738 dce_clock_read_ss_info(clk_dce); 739 } 740 741 struct dccg *dce_dccg_create( 742 struct dc_context *ctx, 743 const struct dccg_registers *regs, 744 const struct dccg_shift *clk_shift, 745 const struct dccg_mask *clk_mask) 746 { 747 struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); 748 749 if (clk_dce == NULL) { 750 BREAK_TO_DEBUGGER(); 751 return NULL; 752 } 753 754 memcpy(clk_dce->max_clks_by_state, 755 dce80_max_clks_by_state, 756 sizeof(dce80_max_clks_by_state)); 757 758 dce_dccg_construct( 759 clk_dce, ctx, regs, clk_shift, clk_mask); 760 761 return &clk_dce->base; 762 } 763 764 struct dccg *dce110_dccg_create( 765 struct dc_context *ctx, 766 const struct dccg_registers *regs, 767 const struct dccg_shift *clk_shift, 768 const struct dccg_mask *clk_mask) 769 { 770 struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); 771 772 if (clk_dce == NULL) { 773 BREAK_TO_DEBUGGER(); 774 return NULL; 775 } 776 777 memcpy(clk_dce->max_clks_by_state, 778 dce110_max_clks_by_state, 779 sizeof(dce110_max_clks_by_state)); 780 781 dce_dccg_construct( 782 clk_dce, ctx, regs, clk_shift, clk_mask); 783 784 clk_dce->base.funcs = &dce110_funcs; 785 786 return &clk_dce->base; 787 } 788 789 struct dccg *dce112_dccg_create( 790 struct dc_context *ctx, 791 const struct dccg_registers *regs, 792 const struct dccg_shift *clk_shift, 793 const struct dccg_mask *clk_mask) 794 { 795 struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); 796 797 if (clk_dce == NULL) { 798 BREAK_TO_DEBUGGER(); 799 return NULL; 800 } 801 802 memcpy(clk_dce->max_clks_by_state, 803 dce112_max_clks_by_state, 804 sizeof(dce112_max_clks_by_state)); 805 806 dce_dccg_construct( 807 clk_dce, ctx, regs, clk_shift, clk_mask); 808 809 clk_dce->base.funcs = &dce112_funcs; 810 811 return &clk_dce->base; 812 } 813 814 struct dccg *dce120_dccg_create(struct dc_context *ctx) 815 { 816 struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); 817 818 if (clk_dce == NULL) { 819 BREAK_TO_DEBUGGER(); 820 return NULL; 821 } 822 823 memcpy(clk_dce->max_clks_by_state, 824 dce120_max_clks_by_state, 825 sizeof(dce120_max_clks_by_state)); 826 827 dce_dccg_construct( 828 clk_dce, ctx, NULL, NULL, NULL); 829 830 clk_dce->base.funcs = &dce120_funcs; 831 832 return &clk_dce->base; 833 } 834 835 #ifdef CONFIG_DRM_AMD_DC_DCN1_0 836 struct dccg *dcn1_dccg_create(struct dc_context *ctx) 837 { 838 struct dc_debug_options *debug = &ctx->dc->debug; 839 struct dc_bios *bp = ctx->dc_bios; 840 struct dc_firmware_info fw_info = { { 0 } }; 841 struct dce_dccg *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); 842 843 if (clk_dce == NULL) { 844 BREAK_TO_DEBUGGER(); 845 return NULL; 846 } 847 848 clk_dce->base.ctx = ctx; 849 clk_dce->base.funcs = &dcn1_funcs; 850 851 clk_dce->dfs_bypass_disp_clk = 0; 852 853 clk_dce->dprefclk_ss_percentage = 0; 854 clk_dce->dprefclk_ss_divider = 1000; 855 clk_dce->ss_on_dprefclk = false; 856 857 if (bp->integrated_info) 858 clk_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq; 859 if (clk_dce->dentist_vco_freq_khz == 0) { 860 bp->funcs->get_firmware_info(bp, &fw_info); 861 clk_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq; 862 if (clk_dce->dentist_vco_freq_khz == 0) 863 clk_dce->dentist_vco_freq_khz = 3600000; 864 } 865 866 if (!debug->disable_dfs_bypass && bp->integrated_info) 867 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE) 868 clk_dce->dfs_bypass_enabled = true; 869 870 dce_clock_read_ss_info(clk_dce); 871 872 return &clk_dce->base; 873 } 874 #endif 875 876 void dce_dccg_destroy(struct dccg **dccg) 877 { 878 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(*dccg); 879 880 kfree(clk_dce); 881 *dccg = NULL; 882 } 883