1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dce_hwseq.h"
27*b843c749SSergey Zigachev #include "reg_helper.h"
28*b843c749SSergey Zigachev #include "hw_sequencer.h"
29*b843c749SSergey Zigachev #include "core_types.h"
30*b843c749SSergey Zigachev
31*b843c749SSergey Zigachev #define CTX \
32*b843c749SSergey Zigachev hws->ctx
33*b843c749SSergey Zigachev #define REG(reg)\
34*b843c749SSergey Zigachev hws->regs->reg
35*b843c749SSergey Zigachev
36*b843c749SSergey Zigachev #undef FN
37*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
38*b843c749SSergey Zigachev hws->shifts->field_name, hws->masks->field_name
39*b843c749SSergey Zigachev
dce_enable_fe_clock(struct dce_hwseq * hws,unsigned int fe_inst,bool enable)40*b843c749SSergey Zigachev void dce_enable_fe_clock(struct dce_hwseq *hws,
41*b843c749SSergey Zigachev unsigned int fe_inst, bool enable)
42*b843c749SSergey Zigachev {
43*b843c749SSergey Zigachev REG_UPDATE(DCFE_CLOCK_CONTROL[fe_inst],
44*b843c749SSergey Zigachev DCFE_CLOCK_ENABLE, enable);
45*b843c749SSergey Zigachev }
46*b843c749SSergey Zigachev
dce_pipe_control_lock(struct dc * dc,struct pipe_ctx * pipe,bool lock)47*b843c749SSergey Zigachev void dce_pipe_control_lock(struct dc *dc,
48*b843c749SSergey Zigachev struct pipe_ctx *pipe,
49*b843c749SSergey Zigachev bool lock)
50*b843c749SSergey Zigachev {
51*b843c749SSergey Zigachev uint32_t lock_val = lock ? 1 : 0;
52*b843c749SSergey Zigachev uint32_t dcp_grph, scl, blnd, update_lock_mode, val;
53*b843c749SSergey Zigachev struct dce_hwseq *hws = dc->hwseq;
54*b843c749SSergey Zigachev
55*b843c749SSergey Zigachev /* Not lock pipe when blank */
56*b843c749SSergey Zigachev if (lock && pipe->stream_res.tg->funcs->is_blanked &&
57*b843c749SSergey Zigachev pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg))
58*b843c749SSergey Zigachev return;
59*b843c749SSergey Zigachev
60*b843c749SSergey Zigachev val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst],
61*b843c749SSergey Zigachev BLND_DCP_GRPH_V_UPDATE_LOCK, &dcp_grph,
62*b843c749SSergey Zigachev BLND_SCL_V_UPDATE_LOCK, &scl,
63*b843c749SSergey Zigachev BLND_BLND_V_UPDATE_LOCK, &blnd,
64*b843c749SSergey Zigachev BLND_V_UPDATE_LOCK_MODE, &update_lock_mode);
65*b843c749SSergey Zigachev
66*b843c749SSergey Zigachev dcp_grph = lock_val;
67*b843c749SSergey Zigachev scl = lock_val;
68*b843c749SSergey Zigachev blnd = lock_val;
69*b843c749SSergey Zigachev update_lock_mode = lock_val;
70*b843c749SSergey Zigachev
71*b843c749SSergey Zigachev REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
72*b843c749SSergey Zigachev BLND_DCP_GRPH_V_UPDATE_LOCK, dcp_grph,
73*b843c749SSergey Zigachev BLND_SCL_V_UPDATE_LOCK, scl);
74*b843c749SSergey Zigachev
75*b843c749SSergey Zigachev if (hws->masks->BLND_BLND_V_UPDATE_LOCK != 0)
76*b843c749SSergey Zigachev REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val,
77*b843c749SSergey Zigachev BLND_BLND_V_UPDATE_LOCK, blnd,
78*b843c749SSergey Zigachev BLND_V_UPDATE_LOCK_MODE, update_lock_mode);
79*b843c749SSergey Zigachev
80*b843c749SSergey Zigachev if (hws->wa.blnd_crtc_trigger) {
81*b843c749SSergey Zigachev if (!lock) {
82*b843c749SSergey Zigachev uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]);
83*b843c749SSergey Zigachev REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value);
84*b843c749SSergey Zigachev }
85*b843c749SSergey Zigachev }
86*b843c749SSergey Zigachev }
87*b843c749SSergey Zigachev
dce_set_blender_mode(struct dce_hwseq * hws,unsigned int blnd_inst,enum blnd_mode mode)88*b843c749SSergey Zigachev void dce_set_blender_mode(struct dce_hwseq *hws,
89*b843c749SSergey Zigachev unsigned int blnd_inst,
90*b843c749SSergey Zigachev enum blnd_mode mode)
91*b843c749SSergey Zigachev {
92*b843c749SSergey Zigachev uint32_t feedthrough = 1;
93*b843c749SSergey Zigachev uint32_t blnd_mode = 0;
94*b843c749SSergey Zigachev uint32_t multiplied_mode = 0;
95*b843c749SSergey Zigachev uint32_t alpha_mode = 2;
96*b843c749SSergey Zigachev
97*b843c749SSergey Zigachev switch (mode) {
98*b843c749SSergey Zigachev case BLND_MODE_OTHER_PIPE:
99*b843c749SSergey Zigachev feedthrough = 0;
100*b843c749SSergey Zigachev blnd_mode = 1;
101*b843c749SSergey Zigachev alpha_mode = 0;
102*b843c749SSergey Zigachev break;
103*b843c749SSergey Zigachev case BLND_MODE_BLENDING:
104*b843c749SSergey Zigachev feedthrough = 0;
105*b843c749SSergey Zigachev blnd_mode = 2;
106*b843c749SSergey Zigachev alpha_mode = 0;
107*b843c749SSergey Zigachev multiplied_mode = 1;
108*b843c749SSergey Zigachev break;
109*b843c749SSergey Zigachev case BLND_MODE_CURRENT_PIPE:
110*b843c749SSergey Zigachev default:
111*b843c749SSergey Zigachev if (REG(BLND_CONTROL[blnd_inst]) == REG(BLNDV_CONTROL) ||
112*b843c749SSergey Zigachev blnd_inst == 0)
113*b843c749SSergey Zigachev feedthrough = 0;
114*b843c749SSergey Zigachev break;
115*b843c749SSergey Zigachev }
116*b843c749SSergey Zigachev
117*b843c749SSergey Zigachev REG_UPDATE(BLND_CONTROL[blnd_inst],
118*b843c749SSergey Zigachev BLND_MODE, blnd_mode);
119*b843c749SSergey Zigachev
120*b843c749SSergey Zigachev if (hws->masks->BLND_ALPHA_MODE != 0) {
121*b843c749SSergey Zigachev REG_UPDATE_3(BLND_CONTROL[blnd_inst],
122*b843c749SSergey Zigachev BLND_FEEDTHROUGH_EN, feedthrough,
123*b843c749SSergey Zigachev BLND_ALPHA_MODE, alpha_mode,
124*b843c749SSergey Zigachev BLND_MULTIPLIED_MODE, multiplied_mode);
125*b843c749SSergey Zigachev }
126*b843c749SSergey Zigachev }
127*b843c749SSergey Zigachev
128*b843c749SSergey Zigachev
dce_disable_sram_shut_down(struct dce_hwseq * hws)129*b843c749SSergey Zigachev static void dce_disable_sram_shut_down(struct dce_hwseq *hws)
130*b843c749SSergey Zigachev {
131*b843c749SSergey Zigachev if (REG(DC_MEM_GLOBAL_PWR_REQ_CNTL))
132*b843c749SSergey Zigachev REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL,
133*b843c749SSergey Zigachev DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
134*b843c749SSergey Zigachev }
135*b843c749SSergey Zigachev
dce_underlay_clock_enable(struct dce_hwseq * hws)136*b843c749SSergey Zigachev static void dce_underlay_clock_enable(struct dce_hwseq *hws)
137*b843c749SSergey Zigachev {
138*b843c749SSergey Zigachev /* todo: why do we need this at boot? is dce_enable_fe_clock enough? */
139*b843c749SSergey Zigachev if (REG(DCFEV_CLOCK_CONTROL))
140*b843c749SSergey Zigachev REG_UPDATE(DCFEV_CLOCK_CONTROL,
141*b843c749SSergey Zigachev DCFEV_CLOCK_ENABLE, 1);
142*b843c749SSergey Zigachev }
143*b843c749SSergey Zigachev
enable_hw_base_light_sleep(void)144*b843c749SSergey Zigachev static void enable_hw_base_light_sleep(void)
145*b843c749SSergey Zigachev {
146*b843c749SSergey Zigachev /* TODO: implement */
147*b843c749SSergey Zigachev }
148*b843c749SSergey Zigachev
disable_sw_manual_control_light_sleep(void)149*b843c749SSergey Zigachev static void disable_sw_manual_control_light_sleep(void)
150*b843c749SSergey Zigachev {
151*b843c749SSergey Zigachev /* TODO: implement */
152*b843c749SSergey Zigachev }
153*b843c749SSergey Zigachev
dce_clock_gating_power_up(struct dce_hwseq * hws,bool enable)154*b843c749SSergey Zigachev void dce_clock_gating_power_up(struct dce_hwseq *hws,
155*b843c749SSergey Zigachev bool enable)
156*b843c749SSergey Zigachev {
157*b843c749SSergey Zigachev if (enable) {
158*b843c749SSergey Zigachev enable_hw_base_light_sleep();
159*b843c749SSergey Zigachev disable_sw_manual_control_light_sleep();
160*b843c749SSergey Zigachev } else {
161*b843c749SSergey Zigachev dce_disable_sram_shut_down(hws);
162*b843c749SSergey Zigachev dce_underlay_clock_enable(hws);
163*b843c749SSergey Zigachev }
164*b843c749SSergey Zigachev }
165*b843c749SSergey Zigachev
dce_crtc_switch_to_clk_src(struct dce_hwseq * hws,struct clock_source * clk_src,unsigned int tg_inst)166*b843c749SSergey Zigachev void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws,
167*b843c749SSergey Zigachev struct clock_source *clk_src,
168*b843c749SSergey Zigachev unsigned int tg_inst)
169*b843c749SSergey Zigachev {
170*b843c749SSergey Zigachev if (clk_src->id == CLOCK_SOURCE_ID_DP_DTO || clk_src->dp_clk_src) {
171*b843c749SSergey Zigachev REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
172*b843c749SSergey Zigachev DP_DTO0_ENABLE, 1);
173*b843c749SSergey Zigachev
174*b843c749SSergey Zigachev } else if (clk_src->id >= CLOCK_SOURCE_COMBO_PHY_PLL0) {
175*b843c749SSergey Zigachev uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0;
176*b843c749SSergey Zigachev
177*b843c749SSergey Zigachev REG_UPDATE_2(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
178*b843c749SSergey Zigachev PHYPLL_PIXEL_RATE_SOURCE, rate_source,
179*b843c749SSergey Zigachev PIXEL_RATE_PLL_SOURCE, 0);
180*b843c749SSergey Zigachev
181*b843c749SSergey Zigachev REG_UPDATE(PIXEL_RATE_CNTL[tg_inst],
182*b843c749SSergey Zigachev DP_DTO0_ENABLE, 0);
183*b843c749SSergey Zigachev
184*b843c749SSergey Zigachev } else if (clk_src->id <= CLOCK_SOURCE_ID_PLL2) {
185*b843c749SSergey Zigachev uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
186*b843c749SSergey Zigachev
187*b843c749SSergey Zigachev REG_UPDATE_2(PIXEL_RATE_CNTL[tg_inst],
188*b843c749SSergey Zigachev PIXEL_RATE_SOURCE, rate_source,
189*b843c749SSergey Zigachev DP_DTO0_ENABLE, 0);
190*b843c749SSergey Zigachev
191*b843c749SSergey Zigachev if (REG(PHYPLL_PIXEL_RATE_CNTL[tg_inst]))
192*b843c749SSergey Zigachev REG_UPDATE(PHYPLL_PIXEL_RATE_CNTL[tg_inst],
193*b843c749SSergey Zigachev PIXEL_RATE_PLL_SOURCE, 1);
194*b843c749SSergey Zigachev } else {
195*b843c749SSergey Zigachev DC_ERR("Unknown clock source. clk_src id: %d, TG_inst: %d",
196*b843c749SSergey Zigachev clk_src->id, tg_inst);
197*b843c749SSergey Zigachev }
198*b843c749SSergey Zigachev }
199*b843c749SSergey Zigachev
200*b843c749SSergey Zigachev /* Only use LUT for 8 bit formats */
dce_use_lut(enum surface_pixel_format format)201*b843c749SSergey Zigachev bool dce_use_lut(enum surface_pixel_format format)
202*b843c749SSergey Zigachev {
203*b843c749SSergey Zigachev switch (format) {
204*b843c749SSergey Zigachev case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
205*b843c749SSergey Zigachev case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
206*b843c749SSergey Zigachev return true;
207*b843c749SSergey Zigachev default:
208*b843c749SSergey Zigachev return false;
209*b843c749SSergey Zigachev }
210*b843c749SSergey Zigachev }
211