1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev #ifndef __DCE_HWSEQ_H__ 26*b843c749SSergey Zigachev #define __DCE_HWSEQ_H__ 27*b843c749SSergey Zigachev 28*b843c749SSergey Zigachev #include "hw_sequencer.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define BL_REG_LIST()\ 31*b843c749SSergey Zigachev SR(LVTMA_PWRSEQ_CNTL), \ 32*b843c749SSergey Zigachev SR(LVTMA_PWRSEQ_STATE) 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev #define HWSEQ_DCEF_REG_LIST_DCE8() \ 35*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 36*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 37*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 38*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 39*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 40*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 41*b843c749SSergey Zigachev 42*b843c749SSergey Zigachev #define HWSEQ_DCEF_REG_LIST() \ 43*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 44*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 45*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 46*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 47*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 48*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 49*b843c749SSergey Zigachev SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev #define HWSEQ_BLND_REG_LIST() \ 52*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 53*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 54*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 55*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 56*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 57*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 58*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 0), \ 59*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 1), \ 60*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 2), \ 61*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 3), \ 62*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 4), \ 63*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 5) 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 0), \ 67*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 1), \ 68*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 2), \ 69*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 3), \ 70*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 4), \ 71*b843c749SSergey Zigachev SRII(PIXEL_RATE_CNTL, blk, 5) 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79*b843c749SSergey Zigachev SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev #define HWSEQ_DCE11_REG_LIST_BASE() \ 82*b843c749SSergey Zigachev SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 83*b843c749SSergey Zigachev SR(DCFEV_CLOCK_CONTROL), \ 84*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 85*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 86*b843c749SSergey Zigachev SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 87*b843c749SSergey Zigachev SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 88*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 89*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 90*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 0),\ 91*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 1),\ 92*b843c749SSergey Zigachev SR(BLNDV_CONTROL),\ 93*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 94*b843c749SSergey Zigachev BL_REG_LIST() 95*b843c749SSergey Zigachev 96*b843c749SSergey Zigachev #define HWSEQ_DCE8_REG_LIST() \ 97*b843c749SSergey Zigachev HWSEQ_DCEF_REG_LIST_DCE8(), \ 98*b843c749SSergey Zigachev HWSEQ_BLND_REG_LIST(), \ 99*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(CRTC),\ 100*b843c749SSergey Zigachev BL_REG_LIST() 101*b843c749SSergey Zigachev 102*b843c749SSergey Zigachev #define HWSEQ_DCE10_REG_LIST() \ 103*b843c749SSergey Zigachev HWSEQ_DCEF_REG_LIST(), \ 104*b843c749SSergey Zigachev HWSEQ_BLND_REG_LIST(), \ 105*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 106*b843c749SSergey Zigachev BL_REG_LIST() 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev #define HWSEQ_ST_REG_LIST() \ 109*b843c749SSergey Zigachev HWSEQ_DCE11_REG_LIST_BASE(), \ 110*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 111*b843c749SSergey Zigachev .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 112*b843c749SSergey Zigachev .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 113*b843c749SSergey Zigachev .BLND_CONTROL[2] = mmBLNDV_CONTROL 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev #define HWSEQ_CZ_REG_LIST() \ 116*b843c749SSergey Zigachev HWSEQ_DCE11_REG_LIST_BASE(), \ 117*b843c749SSergey Zigachev SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 118*b843c749SSergey Zigachev SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 119*b843c749SSergey Zigachev SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 120*b843c749SSergey Zigachev SRII(BLND_CONTROL, BLND, 2), \ 121*b843c749SSergey Zigachev .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 122*b843c749SSergey Zigachev .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 123*b843c749SSergey Zigachev .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 124*b843c749SSergey Zigachev .BLND_CONTROL[3] = mmBLNDV_CONTROL 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev #define HWSEQ_DCE120_REG_LIST() \ 127*b843c749SSergey Zigachev HWSEQ_DCE10_REG_LIST(), \ 128*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 129*b843c749SSergey Zigachev HWSEQ_PHYPLL_REG_LIST(CRTC), \ 130*b843c749SSergey Zigachev SR(DCHUB_FB_LOCATION),\ 131*b843c749SSergey Zigachev SR(DCHUB_AGP_BASE),\ 132*b843c749SSergey Zigachev SR(DCHUB_AGP_BOT),\ 133*b843c749SSergey Zigachev SR(DCHUB_AGP_TOP), \ 134*b843c749SSergey Zigachev BL_REG_LIST() 135*b843c749SSergey Zigachev 136*b843c749SSergey Zigachev #define HWSEQ_DCE112_REG_LIST() \ 137*b843c749SSergey Zigachev HWSEQ_DCE10_REG_LIST(), \ 138*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 139*b843c749SSergey Zigachev HWSEQ_PHYPLL_REG_LIST(CRTC), \ 140*b843c749SSergey Zigachev BL_REG_LIST() 141*b843c749SSergey Zigachev 142*b843c749SSergey Zigachev #define HWSEQ_DCN_REG_LIST()\ 143*b843c749SSergey Zigachev SR(REFCLK_CNTL), \ 144*b843c749SSergey Zigachev SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 145*b843c749SSergey Zigachev SR(DIO_MEM_PWR_CTRL), \ 146*b843c749SSergey Zigachev SR(DCCG_GATE_DISABLE_CNTL), \ 147*b843c749SSergey Zigachev SR(DCCG_GATE_DISABLE_CNTL2), \ 148*b843c749SSergey Zigachev SR(DCFCLK_CNTL),\ 149*b843c749SSergey Zigachev SR(DCFCLK_CNTL), \ 150*b843c749SSergey Zigachev SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 151*b843c749SSergey Zigachev /* todo: get these from GVM instead of reading registers ourselves */\ 152*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 153*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 154*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 155*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 156*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 157*b843c749SSergey Zigachev MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 158*b843c749SSergey Zigachev MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 159*b843c749SSergey Zigachev MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 160*b843c749SSergey Zigachev MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 161*b843c749SSergey Zigachev MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 162*b843c749SSergey Zigachev MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 163*b843c749SSergey Zigachev MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 164*b843c749SSergey Zigachev 165*b843c749SSergey Zigachev #define HWSEQ_DCN1_REG_LIST()\ 166*b843c749SSergey Zigachev HWSEQ_DCN_REG_LIST(), \ 167*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ 168*b843c749SSergey Zigachev HWSEQ_PHYPLL_REG_LIST(OTG), \ 169*b843c749SSergey Zigachev SR(DCHUBBUB_SDPIF_FB_BASE),\ 170*b843c749SSergey Zigachev SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 171*b843c749SSergey Zigachev SR(DCHUBBUB_SDPIF_AGP_BASE),\ 172*b843c749SSergey Zigachev SR(DCHUBBUB_SDPIF_AGP_BOT),\ 173*b843c749SSergey Zigachev SR(DCHUBBUB_SDPIF_AGP_TOP),\ 174*b843c749SSergey Zigachev SR(DOMAIN0_PG_CONFIG), \ 175*b843c749SSergey Zigachev SR(DOMAIN1_PG_CONFIG), \ 176*b843c749SSergey Zigachev SR(DOMAIN2_PG_CONFIG), \ 177*b843c749SSergey Zigachev SR(DOMAIN3_PG_CONFIG), \ 178*b843c749SSergey Zigachev SR(DOMAIN4_PG_CONFIG), \ 179*b843c749SSergey Zigachev SR(DOMAIN5_PG_CONFIG), \ 180*b843c749SSergey Zigachev SR(DOMAIN6_PG_CONFIG), \ 181*b843c749SSergey Zigachev SR(DOMAIN7_PG_CONFIG), \ 182*b843c749SSergey Zigachev SR(DOMAIN0_PG_STATUS), \ 183*b843c749SSergey Zigachev SR(DOMAIN1_PG_STATUS), \ 184*b843c749SSergey Zigachev SR(DOMAIN2_PG_STATUS), \ 185*b843c749SSergey Zigachev SR(DOMAIN3_PG_STATUS), \ 186*b843c749SSergey Zigachev SR(DOMAIN4_PG_STATUS), \ 187*b843c749SSergey Zigachev SR(DOMAIN5_PG_STATUS), \ 188*b843c749SSergey Zigachev SR(DOMAIN6_PG_STATUS), \ 189*b843c749SSergey Zigachev SR(DOMAIN7_PG_STATUS), \ 190*b843c749SSergey Zigachev SR(D1VGA_CONTROL), \ 191*b843c749SSergey Zigachev SR(D2VGA_CONTROL), \ 192*b843c749SSergey Zigachev SR(D3VGA_CONTROL), \ 193*b843c749SSergey Zigachev SR(D4VGA_CONTROL), \ 194*b843c749SSergey Zigachev SR(VGA_TEST_CONTROL), \ 195*b843c749SSergey Zigachev SR(DC_IP_REQUEST_CNTL), \ 196*b843c749SSergey Zigachev BL_REG_LIST() 197*b843c749SSergey Zigachev 198*b843c749SSergey Zigachev struct dce_hwseq_registers { 199*b843c749SSergey Zigachev 200*b843c749SSergey Zigachev /* Backlight registers */ 201*b843c749SSergey Zigachev uint32_t LVTMA_PWRSEQ_CNTL; 202*b843c749SSergey Zigachev uint32_t LVTMA_PWRSEQ_STATE; 203*b843c749SSergey Zigachev 204*b843c749SSergey Zigachev uint32_t DCFE_CLOCK_CONTROL[6]; 205*b843c749SSergey Zigachev uint32_t DCFEV_CLOCK_CONTROL; 206*b843c749SSergey Zigachev uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 207*b843c749SSergey Zigachev uint32_t BLND_V_UPDATE_LOCK[6]; 208*b843c749SSergey Zigachev uint32_t BLND_CONTROL[6]; 209*b843c749SSergey Zigachev uint32_t BLNDV_CONTROL; 210*b843c749SSergey Zigachev uint32_t CRTC_H_BLANK_START_END[6]; 211*b843c749SSergey Zigachev uint32_t PIXEL_RATE_CNTL[6]; 212*b843c749SSergey Zigachev uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 213*b843c749SSergey Zigachev /*DCHUB*/ 214*b843c749SSergey Zigachev uint32_t DCHUB_FB_LOCATION; 215*b843c749SSergey Zigachev uint32_t DCHUB_AGP_BASE; 216*b843c749SSergey Zigachev uint32_t DCHUB_AGP_BOT; 217*b843c749SSergey Zigachev uint32_t DCHUB_AGP_TOP; 218*b843c749SSergey Zigachev 219*b843c749SSergey Zigachev uint32_t REFCLK_CNTL; 220*b843c749SSergey Zigachev 221*b843c749SSergey Zigachev uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 222*b843c749SSergey Zigachev uint32_t DCHUBBUB_SDPIF_FB_BASE; 223*b843c749SSergey Zigachev uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 224*b843c749SSergey Zigachev uint32_t DCHUBBUB_SDPIF_AGP_BASE; 225*b843c749SSergey Zigachev uint32_t DCHUBBUB_SDPIF_AGP_BOT; 226*b843c749SSergey Zigachev uint32_t DCHUBBUB_SDPIF_AGP_TOP; 227*b843c749SSergey Zigachev uint32_t DC_IP_REQUEST_CNTL; 228*b843c749SSergey Zigachev uint32_t DOMAIN0_PG_CONFIG; 229*b843c749SSergey Zigachev uint32_t DOMAIN1_PG_CONFIG; 230*b843c749SSergey Zigachev uint32_t DOMAIN2_PG_CONFIG; 231*b843c749SSergey Zigachev uint32_t DOMAIN3_PG_CONFIG; 232*b843c749SSergey Zigachev uint32_t DOMAIN4_PG_CONFIG; 233*b843c749SSergey Zigachev uint32_t DOMAIN5_PG_CONFIG; 234*b843c749SSergey Zigachev uint32_t DOMAIN6_PG_CONFIG; 235*b843c749SSergey Zigachev uint32_t DOMAIN7_PG_CONFIG; 236*b843c749SSergey Zigachev uint32_t DOMAIN0_PG_STATUS; 237*b843c749SSergey Zigachev uint32_t DOMAIN1_PG_STATUS; 238*b843c749SSergey Zigachev uint32_t DOMAIN2_PG_STATUS; 239*b843c749SSergey Zigachev uint32_t DOMAIN3_PG_STATUS; 240*b843c749SSergey Zigachev uint32_t DOMAIN4_PG_STATUS; 241*b843c749SSergey Zigachev uint32_t DOMAIN5_PG_STATUS; 242*b843c749SSergey Zigachev uint32_t DOMAIN6_PG_STATUS; 243*b843c749SSergey Zigachev uint32_t DOMAIN7_PG_STATUS; 244*b843c749SSergey Zigachev uint32_t DIO_MEM_PWR_CTRL; 245*b843c749SSergey Zigachev uint32_t DCCG_GATE_DISABLE_CNTL; 246*b843c749SSergey Zigachev uint32_t DCCG_GATE_DISABLE_CNTL2; 247*b843c749SSergey Zigachev uint32_t DCFCLK_CNTL; 248*b843c749SSergey Zigachev uint32_t MICROSECOND_TIME_BASE_DIV; 249*b843c749SSergey Zigachev uint32_t MILLISECOND_TIME_BASE_DIV; 250*b843c749SSergey Zigachev uint32_t DISPCLK_FREQ_CHANGE_CNTL; 251*b843c749SSergey Zigachev uint32_t RBBMIF_TIMEOUT_DIS; 252*b843c749SSergey Zigachev uint32_t RBBMIF_TIMEOUT_DIS_2; 253*b843c749SSergey Zigachev uint32_t DCHUBBUB_CRC_CTRL; 254*b843c749SSergey Zigachev uint32_t DPP_TOP0_DPP_CRC_CTRL; 255*b843c749SSergey Zigachev uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 256*b843c749SSergey Zigachev uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 257*b843c749SSergey Zigachev uint32_t MPC_CRC_CTRL; 258*b843c749SSergey Zigachev uint32_t MPC_CRC_RESULT_GB; 259*b843c749SSergey Zigachev uint32_t MPC_CRC_RESULT_C; 260*b843c749SSergey Zigachev uint32_t MPC_CRC_RESULT_AR; 261*b843c749SSergey Zigachev uint32_t D1VGA_CONTROL; 262*b843c749SSergey Zigachev uint32_t D2VGA_CONTROL; 263*b843c749SSergey Zigachev uint32_t D3VGA_CONTROL; 264*b843c749SSergey Zigachev uint32_t D4VGA_CONTROL; 265*b843c749SSergey Zigachev uint32_t VGA_TEST_CONTROL; 266*b843c749SSergey Zigachev /* MMHUB registers. read only. temporary hack */ 267*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 268*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 269*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 270*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 271*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 272*b843c749SSergey Zigachev uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 273*b843c749SSergey Zigachev uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 274*b843c749SSergey Zigachev uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 275*b843c749SSergey Zigachev uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 276*b843c749SSergey Zigachev uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 277*b843c749SSergey Zigachev uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 278*b843c749SSergey Zigachev uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 279*b843c749SSergey Zigachev uint32_t AZALIA_AUDIO_DTO; 280*b843c749SSergey Zigachev uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 281*b843c749SSergey Zigachev }; 282*b843c749SSergey Zigachev /* set field name */ 283*b843c749SSergey Zigachev #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 284*b843c749SSergey Zigachev .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 285*b843c749SSergey Zigachev 286*b843c749SSergey Zigachev #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 287*b843c749SSergey Zigachev .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 288*b843c749SSergey Zigachev 289*b843c749SSergey Zigachev 290*b843c749SSergey Zigachev #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 291*b843c749SSergey Zigachev HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 292*b843c749SSergey Zigachev SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 293*b843c749SSergey Zigachev 294*b843c749SSergey Zigachev #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 295*b843c749SSergey Zigachev HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 296*b843c749SSergey Zigachev HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 297*b843c749SSergey Zigachev HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 298*b843c749SSergey Zigachev HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 299*b843c749SSergey Zigachev HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 300*b843c749SSergey Zigachev HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 301*b843c749SSergey Zigachev HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 302*b843c749SSergey Zigachev HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 303*b843c749SSergey Zigachev HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 304*b843c749SSergey Zigachev 305*b843c749SSergey Zigachev #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 306*b843c749SSergey Zigachev HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 307*b843c749SSergey Zigachev HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 310*b843c749SSergey Zigachev HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 311*b843c749SSergey Zigachev HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 312*b843c749SSergey Zigachev 313*b843c749SSergey Zigachev #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 314*b843c749SSergey Zigachev .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 315*b843c749SSergey Zigachev HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 316*b843c749SSergey Zigachev HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 317*b843c749SSergey Zigachev HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 318*b843c749SSergey Zigachev HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 319*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 320*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 321*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 322*b843c749SSergey Zigachev 323*b843c749SSergey Zigachev #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 324*b843c749SSergey Zigachev HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 325*b843c749SSergey Zigachev HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 326*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_), \ 327*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 328*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 329*b843c749SSergey Zigachev 330*b843c749SSergey Zigachev #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 331*b843c749SSergey Zigachev HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 332*b843c749SSergey Zigachev SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 333*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 334*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\ 335*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\ 336*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 337*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 340*b843c749SSergey Zigachev HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 341*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\ 342*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh),\ 343*b843c749SSergey Zigachev HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 344*b843c749SSergey Zigachev 345*b843c749SSergey Zigachev #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 346*b843c749SSergey Zigachev SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 347*b843c749SSergey Zigachev SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 348*b843c749SSergey Zigachev SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 349*b843c749SSergey Zigachev SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 350*b843c749SSergey Zigachev SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh), \ 351*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 352*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 353*b843c749SSergey Zigachev 354*b843c749SSergey Zigachev #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 355*b843c749SSergey Zigachev HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 356*b843c749SSergey Zigachev HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 357*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 358*b843c749SSergey Zigachev HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 359*b843c749SSergey Zigachev HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh), \ 360*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 361*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 364*b843c749SSergey Zigachev HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 365*b843c749SSergey Zigachev HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 366*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 367*b843c749SSergey Zigachev HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 368*b843c749SSergey Zigachev HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 369*b843c749SSergey Zigachev 370*b843c749SSergey Zigachev #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 371*b843c749SSergey Zigachev HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 372*b843c749SSergey Zigachev HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 373*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 374*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 375*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 376*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 377*b843c749SSergey Zigachev HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 378*b843c749SSergey Zigachev /* todo: get these from GVM instead of reading registers ourselves */\ 379*b843c749SSergey Zigachev HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 380*b843c749SSergey Zigachev HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 381*b843c749SSergey Zigachev HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 382*b843c749SSergey Zigachev HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 383*b843c749SSergey Zigachev HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 384*b843c749SSergey Zigachev HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 385*b843c749SSergey Zigachev HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 386*b843c749SSergey Zigachev HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 387*b843c749SSergey Zigachev HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 388*b843c749SSergey Zigachev HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 389*b843c749SSergey Zigachev HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 390*b843c749SSergey Zigachev HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 391*b843c749SSergey Zigachev HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 392*b843c749SSergey Zigachev HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 393*b843c749SSergey Zigachev HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 394*b843c749SSergey Zigachev HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 395*b843c749SSergey Zigachev HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 396*b843c749SSergey Zigachev HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 397*b843c749SSergey Zigachev HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 398*b843c749SSergey Zigachev HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 399*b843c749SSergey Zigachev HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 400*b843c749SSergey Zigachev HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 401*b843c749SSergey Zigachev HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 402*b843c749SSergey Zigachev HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 403*b843c749SSergey Zigachev HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 404*b843c749SSergey Zigachev HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 405*b843c749SSergey Zigachev HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 406*b843c749SSergey Zigachev HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 407*b843c749SSergey Zigachev HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 408*b843c749SSergey Zigachev HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 409*b843c749SSergey Zigachev HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 410*b843c749SSergey Zigachev HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 411*b843c749SSergey Zigachev HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 412*b843c749SSergey Zigachev HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 413*b843c749SSergey Zigachev HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 414*b843c749SSergey Zigachev HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 415*b843c749SSergey Zigachev HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 416*b843c749SSergey Zigachev HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 417*b843c749SSergey Zigachev HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 418*b843c749SSergey Zigachev HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh),\ 419*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \ 420*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh), \ 421*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh), \ 422*b843c749SSergey Zigachev HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh) 423*b843c749SSergey Zigachev 424*b843c749SSergey Zigachev #define HWSEQ_REG_FIELD_LIST(type) \ 425*b843c749SSergey Zigachev type DCFE_CLOCK_ENABLE; \ 426*b843c749SSergey Zigachev type DCFEV_CLOCK_ENABLE; \ 427*b843c749SSergey Zigachev type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 428*b843c749SSergey Zigachev type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 429*b843c749SSergey Zigachev type BLND_SCL_V_UPDATE_LOCK; \ 430*b843c749SSergey Zigachev type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 431*b843c749SSergey Zigachev type BLND_BLND_V_UPDATE_LOCK; \ 432*b843c749SSergey Zigachev type BLND_V_UPDATE_LOCK_MODE; \ 433*b843c749SSergey Zigachev type BLND_FEEDTHROUGH_EN; \ 434*b843c749SSergey Zigachev type BLND_ALPHA_MODE; \ 435*b843c749SSergey Zigachev type BLND_MODE; \ 436*b843c749SSergey Zigachev type BLND_MULTIPLIED_MODE; \ 437*b843c749SSergey Zigachev type DP_DTO0_ENABLE; \ 438*b843c749SSergey Zigachev type PIXEL_RATE_SOURCE; \ 439*b843c749SSergey Zigachev type PHYPLL_PIXEL_RATE_SOURCE; \ 440*b843c749SSergey Zigachev type PIXEL_RATE_PLL_SOURCE; \ 441*b843c749SSergey Zigachev /* todo: get these from GVM instead of reading registers ourselves */\ 442*b843c749SSergey Zigachev type PAGE_DIRECTORY_ENTRY_HI32;\ 443*b843c749SSergey Zigachev type PAGE_DIRECTORY_ENTRY_LO32;\ 444*b843c749SSergey Zigachev type LOGICAL_PAGE_NUMBER_HI4;\ 445*b843c749SSergey Zigachev type LOGICAL_PAGE_NUMBER_LO32;\ 446*b843c749SSergey Zigachev type PHYSICAL_PAGE_ADDR_HI4;\ 447*b843c749SSergey Zigachev type PHYSICAL_PAGE_ADDR_LO32;\ 448*b843c749SSergey Zigachev type PHYSICAL_PAGE_NUMBER_MSB;\ 449*b843c749SSergey Zigachev type PHYSICAL_PAGE_NUMBER_LSB;\ 450*b843c749SSergey Zigachev type LOGICAL_ADDR; \ 451*b843c749SSergey Zigachev type ENABLE_L1_TLB;\ 452*b843c749SSergey Zigachev type SYSTEM_ACCESS_MODE;\ 453*b843c749SSergey Zigachev type LVTMA_BLON;\ 454*b843c749SSergey Zigachev type LVTMA_PWRSEQ_TARGET_STATE_R;\ 455*b843c749SSergey Zigachev type LVTMA_DIGON;\ 456*b843c749SSergey Zigachev type LVTMA_DIGON_OVRD; 457*b843c749SSergey Zigachev 458*b843c749SSergey Zigachev #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 459*b843c749SSergey Zigachev type HUBP_VTG_SEL; \ 460*b843c749SSergey Zigachev type HUBP_CLOCK_ENABLE; \ 461*b843c749SSergey Zigachev type DPP_CLOCK_ENABLE; \ 462*b843c749SSergey Zigachev type SDPIF_FB_BASE;\ 463*b843c749SSergey Zigachev type SDPIF_FB_OFFSET;\ 464*b843c749SSergey Zigachev type SDPIF_AGP_BASE;\ 465*b843c749SSergey Zigachev type SDPIF_AGP_BOT;\ 466*b843c749SSergey Zigachev type SDPIF_AGP_TOP;\ 467*b843c749SSergey Zigachev type FB_TOP;\ 468*b843c749SSergey Zigachev type FB_BASE;\ 469*b843c749SSergey Zigachev type FB_OFFSET;\ 470*b843c749SSergey Zigachev type AGP_BASE;\ 471*b843c749SSergey Zigachev type AGP_BOT;\ 472*b843c749SSergey Zigachev type AGP_TOP;\ 473*b843c749SSergey Zigachev type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 474*b843c749SSergey Zigachev type OPP_PIPE_CLOCK_EN;\ 475*b843c749SSergey Zigachev type IP_REQUEST_EN; \ 476*b843c749SSergey Zigachev type DOMAIN0_POWER_FORCEON; \ 477*b843c749SSergey Zigachev type DOMAIN0_POWER_GATE; \ 478*b843c749SSergey Zigachev type DOMAIN1_POWER_FORCEON; \ 479*b843c749SSergey Zigachev type DOMAIN1_POWER_GATE; \ 480*b843c749SSergey Zigachev type DOMAIN2_POWER_FORCEON; \ 481*b843c749SSergey Zigachev type DOMAIN2_POWER_GATE; \ 482*b843c749SSergey Zigachev type DOMAIN3_POWER_FORCEON; \ 483*b843c749SSergey Zigachev type DOMAIN3_POWER_GATE; \ 484*b843c749SSergey Zigachev type DOMAIN4_POWER_FORCEON; \ 485*b843c749SSergey Zigachev type DOMAIN4_POWER_GATE; \ 486*b843c749SSergey Zigachev type DOMAIN5_POWER_FORCEON; \ 487*b843c749SSergey Zigachev type DOMAIN5_POWER_GATE; \ 488*b843c749SSergey Zigachev type DOMAIN6_POWER_FORCEON; \ 489*b843c749SSergey Zigachev type DOMAIN6_POWER_GATE; \ 490*b843c749SSergey Zigachev type DOMAIN7_POWER_FORCEON; \ 491*b843c749SSergey Zigachev type DOMAIN7_POWER_GATE; \ 492*b843c749SSergey Zigachev type DOMAIN0_PGFSM_PWR_STATUS; \ 493*b843c749SSergey Zigachev type DOMAIN1_PGFSM_PWR_STATUS; \ 494*b843c749SSergey Zigachev type DOMAIN2_PGFSM_PWR_STATUS; \ 495*b843c749SSergey Zigachev type DOMAIN3_PGFSM_PWR_STATUS; \ 496*b843c749SSergey Zigachev type DOMAIN4_PGFSM_PWR_STATUS; \ 497*b843c749SSergey Zigachev type DOMAIN5_PGFSM_PWR_STATUS; \ 498*b843c749SSergey Zigachev type DOMAIN6_PGFSM_PWR_STATUS; \ 499*b843c749SSergey Zigachev type DOMAIN7_PGFSM_PWR_STATUS; \ 500*b843c749SSergey Zigachev type DCFCLK_GATE_DIS; \ 501*b843c749SSergey Zigachev type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 502*b843c749SSergey Zigachev type VGA_TEST_ENABLE; \ 503*b843c749SSergey Zigachev type VGA_TEST_RENDER_START; \ 504*b843c749SSergey Zigachev type D1VGA_MODE_ENABLE; \ 505*b843c749SSergey Zigachev type D2VGA_MODE_ENABLE; \ 506*b843c749SSergey Zigachev type D3VGA_MODE_ENABLE; \ 507*b843c749SSergey Zigachev type D4VGA_MODE_ENABLE; \ 508*b843c749SSergey Zigachev type AZALIA_AUDIO_DTO_MODULE; 509*b843c749SSergey Zigachev 510*b843c749SSergey Zigachev struct dce_hwseq_shift { 511*b843c749SSergey Zigachev HWSEQ_REG_FIELD_LIST(uint8_t) 512*b843c749SSergey Zigachev HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 513*b843c749SSergey Zigachev }; 514*b843c749SSergey Zigachev 515*b843c749SSergey Zigachev struct dce_hwseq_mask { 516*b843c749SSergey Zigachev HWSEQ_REG_FIELD_LIST(uint32_t) 517*b843c749SSergey Zigachev HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 518*b843c749SSergey Zigachev }; 519*b843c749SSergey Zigachev 520*b843c749SSergey Zigachev 521*b843c749SSergey Zigachev enum blnd_mode { 522*b843c749SSergey Zigachev BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 523*b843c749SSergey Zigachev BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 524*b843c749SSergey Zigachev BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 525*b843c749SSergey Zigachev }; 526*b843c749SSergey Zigachev 527*b843c749SSergey Zigachev void dce_enable_fe_clock(struct dce_hwseq *hwss, 528*b843c749SSergey Zigachev unsigned int inst, bool enable); 529*b843c749SSergey Zigachev 530*b843c749SSergey Zigachev void dce_pipe_control_lock(struct dc *dc, 531*b843c749SSergey Zigachev struct pipe_ctx *pipe, 532*b843c749SSergey Zigachev bool lock); 533*b843c749SSergey Zigachev 534*b843c749SSergey Zigachev void dce_set_blender_mode(struct dce_hwseq *hws, 535*b843c749SSergey Zigachev unsigned int blnd_inst, enum blnd_mode mode); 536*b843c749SSergey Zigachev 537*b843c749SSergey Zigachev void dce_clock_gating_power_up(struct dce_hwseq *hws, 538*b843c749SSergey Zigachev bool enable); 539*b843c749SSergey Zigachev 540*b843c749SSergey Zigachev void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 541*b843c749SSergey Zigachev struct clock_source *clk_src, 542*b843c749SSergey Zigachev unsigned int tg_inst); 543*b843c749SSergey Zigachev 544*b843c749SSergey Zigachev bool dce_use_lut(enum surface_pixel_format format); 545*b843c749SSergey Zigachev #endif /*__DCE_HWSEQ_H__*/ 546