1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2017 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dce_ipp.h"
27*b843c749SSergey Zigachev #include "reg_helper.h"
28*b843c749SSergey Zigachev #include "dm_services.h"
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev #define REG(reg) \
31*b843c749SSergey Zigachev (ipp_dce->regs->reg)
32*b843c749SSergey Zigachev
33*b843c749SSergey Zigachev #undef FN
34*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
35*b843c749SSergey Zigachev ipp_dce->ipp_shift->field_name, ipp_dce->ipp_mask->field_name
36*b843c749SSergey Zigachev
37*b843c749SSergey Zigachev #define CTX \
38*b843c749SSergey Zigachev ipp_dce->base.ctx
39*b843c749SSergey Zigachev
40*b843c749SSergey Zigachev
dce_ipp_cursor_set_position(struct input_pixel_processor * ipp,const struct dc_cursor_position * position,const struct dc_cursor_mi_param * param)41*b843c749SSergey Zigachev static void dce_ipp_cursor_set_position(
42*b843c749SSergey Zigachev struct input_pixel_processor *ipp,
43*b843c749SSergey Zigachev const struct dc_cursor_position *position,
44*b843c749SSergey Zigachev const struct dc_cursor_mi_param *param)
45*b843c749SSergey Zigachev {
46*b843c749SSergey Zigachev struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
47*b843c749SSergey Zigachev
48*b843c749SSergey Zigachev /* lock cursor registers */
49*b843c749SSergey Zigachev REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
50*b843c749SSergey Zigachev
51*b843c749SSergey Zigachev /* Flag passed in structure differentiates cursor enable/disable. */
52*b843c749SSergey Zigachev /* Update if it differs from cached state. */
53*b843c749SSergey Zigachev REG_UPDATE(CUR_CONTROL, CURSOR_EN, position->enable);
54*b843c749SSergey Zigachev
55*b843c749SSergey Zigachev REG_SET_2(CUR_POSITION, 0,
56*b843c749SSergey Zigachev CURSOR_X_POSITION, position->x,
57*b843c749SSergey Zigachev CURSOR_Y_POSITION, position->y);
58*b843c749SSergey Zigachev
59*b843c749SSergey Zigachev REG_SET_2(CUR_HOT_SPOT, 0,
60*b843c749SSergey Zigachev CURSOR_HOT_SPOT_X, position->x_hotspot,
61*b843c749SSergey Zigachev CURSOR_HOT_SPOT_Y, position->y_hotspot);
62*b843c749SSergey Zigachev
63*b843c749SSergey Zigachev /* unlock cursor registers */
64*b843c749SSergey Zigachev REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
65*b843c749SSergey Zigachev }
66*b843c749SSergey Zigachev
dce_ipp_cursor_set_attributes(struct input_pixel_processor * ipp,const struct dc_cursor_attributes * attributes)67*b843c749SSergey Zigachev static void dce_ipp_cursor_set_attributes(
68*b843c749SSergey Zigachev struct input_pixel_processor *ipp,
69*b843c749SSergey Zigachev const struct dc_cursor_attributes *attributes)
70*b843c749SSergey Zigachev {
71*b843c749SSergey Zigachev struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
72*b843c749SSergey Zigachev int mode;
73*b843c749SSergey Zigachev
74*b843c749SSergey Zigachev /* Lock cursor registers */
75*b843c749SSergey Zigachev REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, true);
76*b843c749SSergey Zigachev
77*b843c749SSergey Zigachev /* Program cursor control */
78*b843c749SSergey Zigachev switch (attributes->color_format) {
79*b843c749SSergey Zigachev case CURSOR_MODE_MONO:
80*b843c749SSergey Zigachev mode = 0;
81*b843c749SSergey Zigachev break;
82*b843c749SSergey Zigachev case CURSOR_MODE_COLOR_1BIT_AND:
83*b843c749SSergey Zigachev mode = 1;
84*b843c749SSergey Zigachev break;
85*b843c749SSergey Zigachev case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
86*b843c749SSergey Zigachev mode = 2;
87*b843c749SSergey Zigachev break;
88*b843c749SSergey Zigachev case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
89*b843c749SSergey Zigachev mode = 3;
90*b843c749SSergey Zigachev break;
91*b843c749SSergey Zigachev default:
92*b843c749SSergey Zigachev BREAK_TO_DEBUGGER(); /* unsupported */
93*b843c749SSergey Zigachev mode = 0;
94*b843c749SSergey Zigachev }
95*b843c749SSergey Zigachev
96*b843c749SSergey Zigachev REG_UPDATE_3(CUR_CONTROL,
97*b843c749SSergey Zigachev CURSOR_MODE, mode,
98*b843c749SSergey Zigachev CURSOR_2X_MAGNIFY, attributes->attribute_flags.bits.ENABLE_MAGNIFICATION,
99*b843c749SSergey Zigachev CUR_INV_TRANS_CLAMP, attributes->attribute_flags.bits.INVERSE_TRANSPARENT_CLAMPING);
100*b843c749SSergey Zigachev
101*b843c749SSergey Zigachev if (attributes->color_format == CURSOR_MODE_MONO) {
102*b843c749SSergey Zigachev REG_SET_3(CUR_COLOR1, 0,
103*b843c749SSergey Zigachev CUR_COLOR1_BLUE, 0,
104*b843c749SSergey Zigachev CUR_COLOR1_GREEN, 0,
105*b843c749SSergey Zigachev CUR_COLOR1_RED, 0);
106*b843c749SSergey Zigachev
107*b843c749SSergey Zigachev REG_SET_3(CUR_COLOR2, 0,
108*b843c749SSergey Zigachev CUR_COLOR2_BLUE, 0xff,
109*b843c749SSergey Zigachev CUR_COLOR2_GREEN, 0xff,
110*b843c749SSergey Zigachev CUR_COLOR2_RED, 0xff);
111*b843c749SSergey Zigachev }
112*b843c749SSergey Zigachev
113*b843c749SSergey Zigachev /*
114*b843c749SSergey Zigachev * Program cursor size -- NOTE: HW spec specifies that HW register
115*b843c749SSergey Zigachev * stores size as (height - 1, width - 1)
116*b843c749SSergey Zigachev */
117*b843c749SSergey Zigachev REG_SET_2(CUR_SIZE, 0,
118*b843c749SSergey Zigachev CURSOR_WIDTH, attributes->width-1,
119*b843c749SSergey Zigachev CURSOR_HEIGHT, attributes->height-1);
120*b843c749SSergey Zigachev
121*b843c749SSergey Zigachev /* Program cursor surface address */
122*b843c749SSergey Zigachev /* SURFACE_ADDRESS_HIGH: Higher order bits (39:32) of hardware cursor
123*b843c749SSergey Zigachev * surface base address in byte. It is 4K byte aligned.
124*b843c749SSergey Zigachev * The correct way to program cursor surface address is to first write
125*b843c749SSergey Zigachev * to CUR_SURFACE_ADDRESS_HIGH, and then write to CUR_SURFACE_ADDRESS
126*b843c749SSergey Zigachev */
127*b843c749SSergey Zigachev REG_SET(CUR_SURFACE_ADDRESS_HIGH, 0,
128*b843c749SSergey Zigachev CURSOR_SURFACE_ADDRESS_HIGH, attributes->address.high_part);
129*b843c749SSergey Zigachev
130*b843c749SSergey Zigachev REG_SET(CUR_SURFACE_ADDRESS, 0,
131*b843c749SSergey Zigachev CURSOR_SURFACE_ADDRESS, attributes->address.low_part);
132*b843c749SSergey Zigachev
133*b843c749SSergey Zigachev /* Unlock Cursor registers. */
134*b843c749SSergey Zigachev REG_UPDATE(CUR_UPDATE, CURSOR_UPDATE_LOCK, false);
135*b843c749SSergey Zigachev }
136*b843c749SSergey Zigachev
137*b843c749SSergey Zigachev
dce_ipp_program_prescale(struct input_pixel_processor * ipp,struct ipp_prescale_params * params)138*b843c749SSergey Zigachev static void dce_ipp_program_prescale(struct input_pixel_processor *ipp,
139*b843c749SSergey Zigachev struct ipp_prescale_params *params)
140*b843c749SSergey Zigachev {
141*b843c749SSergey Zigachev struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
142*b843c749SSergey Zigachev
143*b843c749SSergey Zigachev /* set to bypass mode first before change */
144*b843c749SSergey Zigachev REG_UPDATE(PRESCALE_GRPH_CONTROL,
145*b843c749SSergey Zigachev GRPH_PRESCALE_BYPASS, 1);
146*b843c749SSergey Zigachev
147*b843c749SSergey Zigachev REG_SET_2(PRESCALE_VALUES_GRPH_R, 0,
148*b843c749SSergey Zigachev GRPH_PRESCALE_SCALE_R, params->scale,
149*b843c749SSergey Zigachev GRPH_PRESCALE_BIAS_R, params->bias);
150*b843c749SSergey Zigachev
151*b843c749SSergey Zigachev REG_SET_2(PRESCALE_VALUES_GRPH_G, 0,
152*b843c749SSergey Zigachev GRPH_PRESCALE_SCALE_G, params->scale,
153*b843c749SSergey Zigachev GRPH_PRESCALE_BIAS_G, params->bias);
154*b843c749SSergey Zigachev
155*b843c749SSergey Zigachev REG_SET_2(PRESCALE_VALUES_GRPH_B, 0,
156*b843c749SSergey Zigachev GRPH_PRESCALE_SCALE_B, params->scale,
157*b843c749SSergey Zigachev GRPH_PRESCALE_BIAS_B, params->bias);
158*b843c749SSergey Zigachev
159*b843c749SSergey Zigachev if (params->mode != IPP_PRESCALE_MODE_BYPASS) {
160*b843c749SSergey Zigachev REG_UPDATE(PRESCALE_GRPH_CONTROL,
161*b843c749SSergey Zigachev GRPH_PRESCALE_BYPASS, 0);
162*b843c749SSergey Zigachev
163*b843c749SSergey Zigachev /* If prescale is in use, then legacy lut should be bypassed */
164*b843c749SSergey Zigachev REG_UPDATE(INPUT_GAMMA_CONTROL,
165*b843c749SSergey Zigachev GRPH_INPUT_GAMMA_MODE, 1);
166*b843c749SSergey Zigachev }
167*b843c749SSergey Zigachev }
168*b843c749SSergey Zigachev
dce_ipp_program_input_lut(struct input_pixel_processor * ipp,const struct dc_gamma * gamma)169*b843c749SSergey Zigachev static void dce_ipp_program_input_lut(
170*b843c749SSergey Zigachev struct input_pixel_processor *ipp,
171*b843c749SSergey Zigachev const struct dc_gamma *gamma)
172*b843c749SSergey Zigachev {
173*b843c749SSergey Zigachev int i;
174*b843c749SSergey Zigachev struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
175*b843c749SSergey Zigachev
176*b843c749SSergey Zigachev /* power on LUT memory */
177*b843c749SSergey Zigachev if (REG(DCFE_MEM_PWR_CTRL))
178*b843c749SSergey Zigachev REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 1);
179*b843c749SSergey Zigachev
180*b843c749SSergey Zigachev /* enable all */
181*b843c749SSergey Zigachev REG_SET(DC_LUT_WRITE_EN_MASK, 0, DC_LUT_WRITE_EN_MASK, 0x7);
182*b843c749SSergey Zigachev
183*b843c749SSergey Zigachev /* 256 entry mode */
184*b843c749SSergey Zigachev REG_UPDATE(DC_LUT_RW_MODE, DC_LUT_RW_MODE, 0);
185*b843c749SSergey Zigachev
186*b843c749SSergey Zigachev /* LUT-256, unsigned, integer, new u0.12 format */
187*b843c749SSergey Zigachev REG_SET_3(DC_LUT_CONTROL, 0,
188*b843c749SSergey Zigachev DC_LUT_DATA_R_FORMAT, 3,
189*b843c749SSergey Zigachev DC_LUT_DATA_G_FORMAT, 3,
190*b843c749SSergey Zigachev DC_LUT_DATA_B_FORMAT, 3);
191*b843c749SSergey Zigachev
192*b843c749SSergey Zigachev /* start from index 0 */
193*b843c749SSergey Zigachev REG_SET(DC_LUT_RW_INDEX, 0,
194*b843c749SSergey Zigachev DC_LUT_RW_INDEX, 0);
195*b843c749SSergey Zigachev
196*b843c749SSergey Zigachev for (i = 0; i < gamma->num_entries; i++) {
197*b843c749SSergey Zigachev REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
198*b843c749SSergey Zigachev dc_fixpt_round(
199*b843c749SSergey Zigachev gamma->entries.red[i]));
200*b843c749SSergey Zigachev REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
201*b843c749SSergey Zigachev dc_fixpt_round(
202*b843c749SSergey Zigachev gamma->entries.green[i]));
203*b843c749SSergey Zigachev REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR,
204*b843c749SSergey Zigachev dc_fixpt_round(
205*b843c749SSergey Zigachev gamma->entries.blue[i]));
206*b843c749SSergey Zigachev }
207*b843c749SSergey Zigachev
208*b843c749SSergey Zigachev /* power off LUT memory */
209*b843c749SSergey Zigachev if (REG(DCFE_MEM_PWR_CTRL))
210*b843c749SSergey Zigachev REG_SET(DCFE_MEM_PWR_CTRL, 0, DCP_LUT_MEM_PWR_DIS, 0);
211*b843c749SSergey Zigachev
212*b843c749SSergey Zigachev /* bypass prescale, enable legacy LUT */
213*b843c749SSergey Zigachev REG_UPDATE(PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
214*b843c749SSergey Zigachev REG_UPDATE(INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
215*b843c749SSergey Zigachev }
216*b843c749SSergey Zigachev
dce_ipp_set_degamma(struct input_pixel_processor * ipp,enum ipp_degamma_mode mode)217*b843c749SSergey Zigachev static void dce_ipp_set_degamma(
218*b843c749SSergey Zigachev struct input_pixel_processor *ipp,
219*b843c749SSergey Zigachev enum ipp_degamma_mode mode)
220*b843c749SSergey Zigachev {
221*b843c749SSergey Zigachev struct dce_ipp *ipp_dce = TO_DCE_IPP(ipp);
222*b843c749SSergey Zigachev uint32_t degamma_type = (mode == IPP_DEGAMMA_MODE_HW_sRGB) ? 1 : 0;
223*b843c749SSergey Zigachev
224*b843c749SSergey Zigachev ASSERT(mode == IPP_DEGAMMA_MODE_BYPASS || mode == IPP_DEGAMMA_MODE_HW_sRGB);
225*b843c749SSergey Zigachev
226*b843c749SSergey Zigachev REG_SET_3(DEGAMMA_CONTROL, 0,
227*b843c749SSergey Zigachev GRPH_DEGAMMA_MODE, degamma_type,
228*b843c749SSergey Zigachev CURSOR_DEGAMMA_MODE, degamma_type,
229*b843c749SSergey Zigachev CURSOR2_DEGAMMA_MODE, degamma_type);
230*b843c749SSergey Zigachev }
231*b843c749SSergey Zigachev
232*b843c749SSergey Zigachev static const struct ipp_funcs dce_ipp_funcs = {
233*b843c749SSergey Zigachev .ipp_cursor_set_attributes = dce_ipp_cursor_set_attributes,
234*b843c749SSergey Zigachev .ipp_cursor_set_position = dce_ipp_cursor_set_position,
235*b843c749SSergey Zigachev .ipp_program_prescale = dce_ipp_program_prescale,
236*b843c749SSergey Zigachev .ipp_program_input_lut = dce_ipp_program_input_lut,
237*b843c749SSergey Zigachev .ipp_set_degamma = dce_ipp_set_degamma
238*b843c749SSergey Zigachev };
239*b843c749SSergey Zigachev
240*b843c749SSergey Zigachev /*****************************************/
241*b843c749SSergey Zigachev /* Constructor, Destructor */
242*b843c749SSergey Zigachev /*****************************************/
243*b843c749SSergey Zigachev
dce_ipp_construct(struct dce_ipp * ipp_dce,struct dc_context * ctx,int inst,const struct dce_ipp_registers * regs,const struct dce_ipp_shift * ipp_shift,const struct dce_ipp_mask * ipp_mask)244*b843c749SSergey Zigachev void dce_ipp_construct(
245*b843c749SSergey Zigachev struct dce_ipp *ipp_dce,
246*b843c749SSergey Zigachev struct dc_context *ctx,
247*b843c749SSergey Zigachev int inst,
248*b843c749SSergey Zigachev const struct dce_ipp_registers *regs,
249*b843c749SSergey Zigachev const struct dce_ipp_shift *ipp_shift,
250*b843c749SSergey Zigachev const struct dce_ipp_mask *ipp_mask)
251*b843c749SSergey Zigachev {
252*b843c749SSergey Zigachev ipp_dce->base.ctx = ctx;
253*b843c749SSergey Zigachev ipp_dce->base.inst = inst;
254*b843c749SSergey Zigachev ipp_dce->base.funcs = &dce_ipp_funcs;
255*b843c749SSergey Zigachev
256*b843c749SSergey Zigachev ipp_dce->regs = regs;
257*b843c749SSergey Zigachev ipp_dce->ipp_shift = ipp_shift;
258*b843c749SSergey Zigachev ipp_dce->ipp_mask = ipp_mask;
259*b843c749SSergey Zigachev }
260*b843c749SSergey Zigachev
dce_ipp_destroy(struct input_pixel_processor ** ipp)261*b843c749SSergey Zigachev void dce_ipp_destroy(struct input_pixel_processor **ipp)
262*b843c749SSergey Zigachev {
263*b843c749SSergey Zigachev kfree(TO_DCE_IPP(*ipp));
264*b843c749SSergey Zigachev *ipp = NULL;
265*b843c749SSergey Zigachev }
266