1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dc_bios_types.h"
27*b843c749SSergey Zigachev #include "dce_stream_encoder.h"
28*b843c749SSergey Zigachev #include "reg_helper.h"
29*b843c749SSergey Zigachev #include "hw_shared.h"
30*b843c749SSergey Zigachev
31*b843c749SSergey Zigachev #define DC_LOGGER \
32*b843c749SSergey Zigachev enc110->base.ctx->logger
33*b843c749SSergey Zigachev
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev #define REG(reg)\
36*b843c749SSergey Zigachev (enc110->regs->reg)
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev #undef FN
39*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
40*b843c749SSergey Zigachev enc110->se_shift->field_name, enc110->se_mask->field_name
41*b843c749SSergey Zigachev
42*b843c749SSergey Zigachev #define VBI_LINE_0 0
43*b843c749SSergey Zigachev #define DP_BLANK_MAX_RETRY 20
44*b843c749SSergey Zigachev #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
45*b843c749SSergey Zigachev
46*b843c749SSergey Zigachev #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK
47*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L
48*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L
49*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004
50*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008
51*b843c749SSergey Zigachev #endif
52*b843c749SSergey Zigachev
53*b843c749SSergey Zigachev enum {
54*b843c749SSergey Zigachev DP_MST_UPDATE_MAX_RETRY = 50
55*b843c749SSergey Zigachev };
56*b843c749SSergey Zigachev
57*b843c749SSergey Zigachev #define DCE110_SE(audio)\
58*b843c749SSergey Zigachev container_of(audio, struct dce110_stream_encoder, base)
59*b843c749SSergey Zigachev
60*b843c749SSergey Zigachev #define CTX \
61*b843c749SSergey Zigachev enc110->base.ctx
62*b843c749SSergey Zigachev
dce110_update_generic_info_packet(struct dce110_stream_encoder * enc110,uint32_t packet_index,const struct dc_info_packet * info_packet)63*b843c749SSergey Zigachev static void dce110_update_generic_info_packet(
64*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110,
65*b843c749SSergey Zigachev uint32_t packet_index,
66*b843c749SSergey Zigachev const struct dc_info_packet *info_packet)
67*b843c749SSergey Zigachev {
68*b843c749SSergey Zigachev uint32_t regval;
69*b843c749SSergey Zigachev /* TODOFPGA Figure out a proper number for max_retries polling for lock
70*b843c749SSergey Zigachev * use 50 for now.
71*b843c749SSergey Zigachev */
72*b843c749SSergey Zigachev uint32_t max_retries = 50;
73*b843c749SSergey Zigachev
74*b843c749SSergey Zigachev /*we need turn on clock before programming AFMT block*/
75*b843c749SSergey Zigachev if (REG(AFMT_CNTL))
76*b843c749SSergey Zigachev REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
77*b843c749SSergey Zigachev
78*b843c749SSergey Zigachev if (REG(AFMT_VBI_PACKET_CONTROL1)) {
79*b843c749SSergey Zigachev if (packet_index >= 8)
80*b843c749SSergey Zigachev ASSERT(0);
81*b843c749SSergey Zigachev
82*b843c749SSergey Zigachev /* poll dig_update_lock is not locked -> asic internal signal
83*b843c749SSergey Zigachev * assume otg master lock will unlock it
84*b843c749SSergey Zigachev */
85*b843c749SSergey Zigachev /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS,
86*b843c749SSergey Zigachev 0, 10, max_retries);*/
87*b843c749SSergey Zigachev
88*b843c749SSergey Zigachev /* check if HW reading GSP memory */
89*b843c749SSergey Zigachev REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
90*b843c749SSergey Zigachev 0, 10, max_retries);
91*b843c749SSergey Zigachev
92*b843c749SSergey Zigachev /* HW does is not reading GSP memory not reading too long ->
93*b843c749SSergey Zigachev * something wrong. clear GPS memory access and notify?
94*b843c749SSergey Zigachev * hw SW is writing to GSP memory
95*b843c749SSergey Zigachev */
96*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
97*b843c749SSergey Zigachev }
98*b843c749SSergey Zigachev /* choose which generic packet to use */
99*b843c749SSergey Zigachev {
100*b843c749SSergey Zigachev regval = REG_READ(AFMT_VBI_PACKET_CONTROL);
101*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
102*b843c749SSergey Zigachev AFMT_GENERIC_INDEX, packet_index);
103*b843c749SSergey Zigachev }
104*b843c749SSergey Zigachev
105*b843c749SSergey Zigachev /* write generic packet header
106*b843c749SSergey Zigachev * (4th byte is for GENERIC0 only) */
107*b843c749SSergey Zigachev {
108*b843c749SSergey Zigachev REG_SET_4(AFMT_GENERIC_HDR, 0,
109*b843c749SSergey Zigachev AFMT_GENERIC_HB0, info_packet->hb0,
110*b843c749SSergey Zigachev AFMT_GENERIC_HB1, info_packet->hb1,
111*b843c749SSergey Zigachev AFMT_GENERIC_HB2, info_packet->hb2,
112*b843c749SSergey Zigachev AFMT_GENERIC_HB3, info_packet->hb3);
113*b843c749SSergey Zigachev }
114*b843c749SSergey Zigachev
115*b843c749SSergey Zigachev /* write generic packet contents
116*b843c749SSergey Zigachev * (we never use last 4 bytes)
117*b843c749SSergey Zigachev * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */
118*b843c749SSergey Zigachev {
119*b843c749SSergey Zigachev const uint32_t *content =
120*b843c749SSergey Zigachev (const uint32_t *) &info_packet->sb[0];
121*b843c749SSergey Zigachev
122*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_0, *content++);
123*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_1, *content++);
124*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_2, *content++);
125*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_3, *content++);
126*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_4, *content++);
127*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_5, *content++);
128*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_6, *content++);
129*b843c749SSergey Zigachev REG_WRITE(AFMT_GENERIC_7, *content);
130*b843c749SSergey Zigachev }
131*b843c749SSergey Zigachev
132*b843c749SSergey Zigachev if (!REG(AFMT_VBI_PACKET_CONTROL1)) {
133*b843c749SSergey Zigachev /* force double-buffered packet update */
134*b843c749SSergey Zigachev REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
135*b843c749SSergey Zigachev AFMT_GENERIC0_UPDATE, (packet_index == 0),
136*b843c749SSergey Zigachev AFMT_GENERIC2_UPDATE, (packet_index == 2));
137*b843c749SSergey Zigachev }
138*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
139*b843c749SSergey Zigachev if (REG(AFMT_VBI_PACKET_CONTROL1)) {
140*b843c749SSergey Zigachev switch (packet_index) {
141*b843c749SSergey Zigachev case 0:
142*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
143*b843c749SSergey Zigachev AFMT_GENERIC0_FRAME_UPDATE, 1);
144*b843c749SSergey Zigachev break;
145*b843c749SSergey Zigachev case 1:
146*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
147*b843c749SSergey Zigachev AFMT_GENERIC1_FRAME_UPDATE, 1);
148*b843c749SSergey Zigachev break;
149*b843c749SSergey Zigachev case 2:
150*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
151*b843c749SSergey Zigachev AFMT_GENERIC2_FRAME_UPDATE, 1);
152*b843c749SSergey Zigachev break;
153*b843c749SSergey Zigachev case 3:
154*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
155*b843c749SSergey Zigachev AFMT_GENERIC3_FRAME_UPDATE, 1);
156*b843c749SSergey Zigachev break;
157*b843c749SSergey Zigachev case 4:
158*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
159*b843c749SSergey Zigachev AFMT_GENERIC4_FRAME_UPDATE, 1);
160*b843c749SSergey Zigachev break;
161*b843c749SSergey Zigachev case 5:
162*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
163*b843c749SSergey Zigachev AFMT_GENERIC5_FRAME_UPDATE, 1);
164*b843c749SSergey Zigachev break;
165*b843c749SSergey Zigachev case 6:
166*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
167*b843c749SSergey Zigachev AFMT_GENERIC6_FRAME_UPDATE, 1);
168*b843c749SSergey Zigachev break;
169*b843c749SSergey Zigachev case 7:
170*b843c749SSergey Zigachev REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
171*b843c749SSergey Zigachev AFMT_GENERIC7_FRAME_UPDATE, 1);
172*b843c749SSergey Zigachev break;
173*b843c749SSergey Zigachev default:
174*b843c749SSergey Zigachev break;
175*b843c749SSergey Zigachev }
176*b843c749SSergey Zigachev }
177*b843c749SSergey Zigachev #endif
178*b843c749SSergey Zigachev }
179*b843c749SSergey Zigachev
dce110_update_hdmi_info_packet(struct dce110_stream_encoder * enc110,uint32_t packet_index,const struct dc_info_packet * info_packet)180*b843c749SSergey Zigachev static void dce110_update_hdmi_info_packet(
181*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110,
182*b843c749SSergey Zigachev uint32_t packet_index,
183*b843c749SSergey Zigachev const struct dc_info_packet *info_packet)
184*b843c749SSergey Zigachev {
185*b843c749SSergey Zigachev uint32_t cont, send, line;
186*b843c749SSergey Zigachev
187*b843c749SSergey Zigachev if (info_packet->valid) {
188*b843c749SSergey Zigachev dce110_update_generic_info_packet(
189*b843c749SSergey Zigachev enc110,
190*b843c749SSergey Zigachev packet_index,
191*b843c749SSergey Zigachev info_packet);
192*b843c749SSergey Zigachev
193*b843c749SSergey Zigachev /* enable transmission of packet(s) -
194*b843c749SSergey Zigachev * packet transmission begins on the next frame */
195*b843c749SSergey Zigachev cont = 1;
196*b843c749SSergey Zigachev /* send packet(s) every frame */
197*b843c749SSergey Zigachev send = 1;
198*b843c749SSergey Zigachev /* select line number to send packets on */
199*b843c749SSergey Zigachev line = 2;
200*b843c749SSergey Zigachev } else {
201*b843c749SSergey Zigachev cont = 0;
202*b843c749SSergey Zigachev send = 0;
203*b843c749SSergey Zigachev line = 0;
204*b843c749SSergey Zigachev }
205*b843c749SSergey Zigachev
206*b843c749SSergey Zigachev /* choose which generic packet control to use */
207*b843c749SSergey Zigachev switch (packet_index) {
208*b843c749SSergey Zigachev case 0:
209*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
210*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, cont,
211*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, send,
212*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, line);
213*b843c749SSergey Zigachev break;
214*b843c749SSergey Zigachev case 1:
215*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0,
216*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, cont,
217*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, send,
218*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, line);
219*b843c749SSergey Zigachev break;
220*b843c749SSergey Zigachev case 2:
221*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
222*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, cont,
223*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, send,
224*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, line);
225*b843c749SSergey Zigachev break;
226*b843c749SSergey Zigachev case 3:
227*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1,
228*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, cont,
229*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, send,
230*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, line);
231*b843c749SSergey Zigachev break;
232*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
233*b843c749SSergey Zigachev case 4:
234*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL2))
235*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
236*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, cont,
237*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, send,
238*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, line);
239*b843c749SSergey Zigachev break;
240*b843c749SSergey Zigachev case 5:
241*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL2))
242*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
243*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, cont,
244*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, send,
245*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, line);
246*b843c749SSergey Zigachev break;
247*b843c749SSergey Zigachev case 6:
248*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL3))
249*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
250*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, cont,
251*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, send,
252*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, line);
253*b843c749SSergey Zigachev break;
254*b843c749SSergey Zigachev case 7:
255*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL3))
256*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3,
257*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, cont,
258*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, send,
259*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, line);
260*b843c749SSergey Zigachev break;
261*b843c749SSergey Zigachev #endif
262*b843c749SSergey Zigachev default:
263*b843c749SSergey Zigachev /* invalid HW packet index */
264*b843c749SSergey Zigachev DC_LOG_WARNING(
265*b843c749SSergey Zigachev "Invalid HW packet index: %s()\n",
266*b843c749SSergey Zigachev __func__);
267*b843c749SSergey Zigachev return;
268*b843c749SSergey Zigachev }
269*b843c749SSergey Zigachev }
270*b843c749SSergey Zigachev
271*b843c749SSergey Zigachev /* setup stream encoder in dp mode */
dce110_stream_encoder_dp_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,enum dc_color_space output_color_space)272*b843c749SSergey Zigachev static void dce110_stream_encoder_dp_set_stream_attribute(
273*b843c749SSergey Zigachev struct stream_encoder *enc,
274*b843c749SSergey Zigachev struct dc_crtc_timing *crtc_timing,
275*b843c749SSergey Zigachev enum dc_color_space output_color_space)
276*b843c749SSergey Zigachev {
277*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
278*b843c749SSergey Zigachev uint32_t h_active_start;
279*b843c749SSergey Zigachev uint32_t v_active_start;
280*b843c749SSergey Zigachev uint32_t misc0 = 0;
281*b843c749SSergey Zigachev uint32_t misc1 = 0;
282*b843c749SSergey Zigachev uint32_t h_blank;
283*b843c749SSergey Zigachev uint32_t h_back_porch;
284*b843c749SSergey Zigachev uint8_t synchronous_clock = 0; /* asynchronous mode */
285*b843c749SSergey Zigachev uint8_t colorimetry_bpc;
286*b843c749SSergey Zigachev uint8_t dynamic_range_rgb = 0; /*full range*/
287*b843c749SSergey Zigachev uint8_t dynamic_range_ycbcr = 1; /*bt709*/
288*b843c749SSergey Zigachev #endif
289*b843c749SSergey Zigachev
290*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
291*b843c749SSergey Zigachev
292*b843c749SSergey Zigachev /* set pixel encoding */
293*b843c749SSergey Zigachev switch (crtc_timing->pixel_encoding) {
294*b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR422:
295*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
296*b843c749SSergey Zigachev DP_PIXEL_ENCODING_TYPE_YCBCR422);
297*b843c749SSergey Zigachev break;
298*b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR444:
299*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
300*b843c749SSergey Zigachev DP_PIXEL_ENCODING_TYPE_YCBCR444);
301*b843c749SSergey Zigachev
302*b843c749SSergey Zigachev if (crtc_timing->flags.Y_ONLY)
303*b843c749SSergey Zigachev if (crtc_timing->display_color_depth != COLOR_DEPTH_666)
304*b843c749SSergey Zigachev /* HW testing only, no use case yet.
305*b843c749SSergey Zigachev * Color depth of Y-only could be
306*b843c749SSergey Zigachev * 8, 10, 12, 16 bits */
307*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
308*b843c749SSergey Zigachev DP_PIXEL_ENCODING_TYPE_Y_ONLY);
309*b843c749SSergey Zigachev /* Note: DP_MSA_MISC1 bit 7 is the indicator
310*b843c749SSergey Zigachev * of Y-only mode.
311*b843c749SSergey Zigachev * This bit is set in HW if register
312*b843c749SSergey Zigachev * DP_PIXEL_ENCODING is programmed to 0x4 */
313*b843c749SSergey Zigachev break;
314*b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR420:
315*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
316*b843c749SSergey Zigachev DP_PIXEL_ENCODING_TYPE_YCBCR420);
317*b843c749SSergey Zigachev if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
318*b843c749SSergey Zigachev REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
319*b843c749SSergey Zigachev
320*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
321*b843c749SSergey Zigachev if (enc110->se_mask->DP_VID_N_MUL)
322*b843c749SSergey Zigachev REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
323*b843c749SSergey Zigachev #endif
324*b843c749SSergey Zigachev break;
325*b843c749SSergey Zigachev default:
326*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING,
327*b843c749SSergey Zigachev DP_PIXEL_ENCODING_TYPE_RGB444);
328*b843c749SSergey Zigachev break;
329*b843c749SSergey Zigachev }
330*b843c749SSergey Zigachev
331*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
332*b843c749SSergey Zigachev if (REG(DP_MSA_MISC))
333*b843c749SSergey Zigachev misc1 = REG_READ(DP_MSA_MISC);
334*b843c749SSergey Zigachev #endif
335*b843c749SSergey Zigachev
336*b843c749SSergey Zigachev /* set color depth */
337*b843c749SSergey Zigachev
338*b843c749SSergey Zigachev switch (crtc_timing->display_color_depth) {
339*b843c749SSergey Zigachev case COLOR_DEPTH_666:
340*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
341*b843c749SSergey Zigachev 0);
342*b843c749SSergey Zigachev break;
343*b843c749SSergey Zigachev case COLOR_DEPTH_888:
344*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
345*b843c749SSergey Zigachev DP_COMPONENT_PIXEL_DEPTH_8BPC);
346*b843c749SSergey Zigachev break;
347*b843c749SSergey Zigachev case COLOR_DEPTH_101010:
348*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
349*b843c749SSergey Zigachev DP_COMPONENT_PIXEL_DEPTH_10BPC);
350*b843c749SSergey Zigachev
351*b843c749SSergey Zigachev break;
352*b843c749SSergey Zigachev case COLOR_DEPTH_121212:
353*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
354*b843c749SSergey Zigachev DP_COMPONENT_PIXEL_DEPTH_12BPC);
355*b843c749SSergey Zigachev break;
356*b843c749SSergey Zigachev default:
357*b843c749SSergey Zigachev REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH,
358*b843c749SSergey Zigachev DP_COMPONENT_PIXEL_DEPTH_6BPC);
359*b843c749SSergey Zigachev break;
360*b843c749SSergey Zigachev }
361*b843c749SSergey Zigachev
362*b843c749SSergey Zigachev /* set dynamic range and YCbCr range */
363*b843c749SSergey Zigachev
364*b843c749SSergey Zigachev
365*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
366*b843c749SSergey Zigachev switch (crtc_timing->display_color_depth) {
367*b843c749SSergey Zigachev case COLOR_DEPTH_666:
368*b843c749SSergey Zigachev colorimetry_bpc = 0;
369*b843c749SSergey Zigachev break;
370*b843c749SSergey Zigachev case COLOR_DEPTH_888:
371*b843c749SSergey Zigachev colorimetry_bpc = 1;
372*b843c749SSergey Zigachev break;
373*b843c749SSergey Zigachev case COLOR_DEPTH_101010:
374*b843c749SSergey Zigachev colorimetry_bpc = 2;
375*b843c749SSergey Zigachev break;
376*b843c749SSergey Zigachev case COLOR_DEPTH_121212:
377*b843c749SSergey Zigachev colorimetry_bpc = 3;
378*b843c749SSergey Zigachev break;
379*b843c749SSergey Zigachev default:
380*b843c749SSergey Zigachev colorimetry_bpc = 0;
381*b843c749SSergey Zigachev break;
382*b843c749SSergey Zigachev }
383*b843c749SSergey Zigachev
384*b843c749SSergey Zigachev misc0 = misc0 | synchronous_clock;
385*b843c749SSergey Zigachev misc0 = colorimetry_bpc << 5;
386*b843c749SSergey Zigachev
387*b843c749SSergey Zigachev if (REG(DP_MSA_TIMING_PARAM1)) {
388*b843c749SSergey Zigachev switch (output_color_space) {
389*b843c749SSergey Zigachev case COLOR_SPACE_SRGB:
390*b843c749SSergey Zigachev misc0 = misc0 | 0x0;
391*b843c749SSergey Zigachev misc1 = misc1 & ~0x80; /* bit7 = 0*/
392*b843c749SSergey Zigachev dynamic_range_rgb = 0; /*full range*/
393*b843c749SSergey Zigachev break;
394*b843c749SSergey Zigachev case COLOR_SPACE_SRGB_LIMITED:
395*b843c749SSergey Zigachev misc0 = misc0 | 0x8; /* bit3=1 */
396*b843c749SSergey Zigachev misc1 = misc1 & ~0x80; /* bit7 = 0*/
397*b843c749SSergey Zigachev dynamic_range_rgb = 1; /*limited range*/
398*b843c749SSergey Zigachev break;
399*b843c749SSergey Zigachev case COLOR_SPACE_YCBCR601:
400*b843c749SSergey Zigachev case COLOR_SPACE_YCBCR601_LIMITED:
401*b843c749SSergey Zigachev misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */
402*b843c749SSergey Zigachev misc1 = misc1 & ~0x80; /* bit7 = 0*/
403*b843c749SSergey Zigachev dynamic_range_ycbcr = 0; /*bt601*/
404*b843c749SSergey Zigachev if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
405*b843c749SSergey Zigachev misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
406*b843c749SSergey Zigachev else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
407*b843c749SSergey Zigachev misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
408*b843c749SSergey Zigachev break;
409*b843c749SSergey Zigachev case COLOR_SPACE_YCBCR709:
410*b843c749SSergey Zigachev case COLOR_SPACE_YCBCR709_LIMITED:
411*b843c749SSergey Zigachev misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */
412*b843c749SSergey Zigachev misc1 = misc1 & ~0x80; /* bit7 = 0*/
413*b843c749SSergey Zigachev dynamic_range_ycbcr = 1; /*bt709*/
414*b843c749SSergey Zigachev if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
415*b843c749SSergey Zigachev misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */
416*b843c749SSergey Zigachev else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
417*b843c749SSergey Zigachev misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */
418*b843c749SSergey Zigachev break;
419*b843c749SSergey Zigachev case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
420*b843c749SSergey Zigachev dynamic_range_rgb = 1; /*limited range*/
421*b843c749SSergey Zigachev break;
422*b843c749SSergey Zigachev case COLOR_SPACE_2020_RGB_FULLRANGE:
423*b843c749SSergey Zigachev case COLOR_SPACE_2020_YCBCR:
424*b843c749SSergey Zigachev case COLOR_SPACE_XR_RGB:
425*b843c749SSergey Zigachev case COLOR_SPACE_MSREF_SCRGB:
426*b843c749SSergey Zigachev case COLOR_SPACE_ADOBERGB:
427*b843c749SSergey Zigachev case COLOR_SPACE_DCIP3:
428*b843c749SSergey Zigachev case COLOR_SPACE_XV_YCC_709:
429*b843c749SSergey Zigachev case COLOR_SPACE_XV_YCC_601:
430*b843c749SSergey Zigachev case COLOR_SPACE_DISPLAYNATIVE:
431*b843c749SSergey Zigachev case COLOR_SPACE_DOLBYVISION:
432*b843c749SSergey Zigachev case COLOR_SPACE_APPCTRL:
433*b843c749SSergey Zigachev case COLOR_SPACE_CUSTOMPOINTS:
434*b843c749SSergey Zigachev case COLOR_SPACE_UNKNOWN:
435*b843c749SSergey Zigachev /* do nothing */
436*b843c749SSergey Zigachev break;
437*b843c749SSergey Zigachev }
438*b843c749SSergey Zigachev if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE)
439*b843c749SSergey Zigachev REG_UPDATE_2(
440*b843c749SSergey Zigachev DP_PIXEL_FORMAT,
441*b843c749SSergey Zigachev DP_DYN_RANGE, dynamic_range_rgb,
442*b843c749SSergey Zigachev DP_YCBCR_RANGE, dynamic_range_ycbcr);
443*b843c749SSergey Zigachev
444*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
445*b843c749SSergey Zigachev if (REG(DP_MSA_COLORIMETRY))
446*b843c749SSergey Zigachev REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
447*b843c749SSergey Zigachev
448*b843c749SSergey Zigachev if (REG(DP_MSA_MISC))
449*b843c749SSergey Zigachev REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */
450*b843c749SSergey Zigachev
451*b843c749SSergey Zigachev /* dcn new register
452*b843c749SSergey Zigachev * dc_crtc_timing is vesa dmt struct. data from edid
453*b843c749SSergey Zigachev */
454*b843c749SSergey Zigachev if (REG(DP_MSA_TIMING_PARAM1))
455*b843c749SSergey Zigachev REG_SET_2(DP_MSA_TIMING_PARAM1, 0,
456*b843c749SSergey Zigachev DP_MSA_HTOTAL, crtc_timing->h_total,
457*b843c749SSergey Zigachev DP_MSA_VTOTAL, crtc_timing->v_total);
458*b843c749SSergey Zigachev #endif
459*b843c749SSergey Zigachev
460*b843c749SSergey Zigachev /* calcuate from vesa timing parameters
461*b843c749SSergey Zigachev * h_active_start related to leading edge of sync
462*b843c749SSergey Zigachev */
463*b843c749SSergey Zigachev
464*b843c749SSergey Zigachev h_blank = crtc_timing->h_total - crtc_timing->h_border_left -
465*b843c749SSergey Zigachev crtc_timing->h_addressable - crtc_timing->h_border_right;
466*b843c749SSergey Zigachev
467*b843c749SSergey Zigachev h_back_porch = h_blank - crtc_timing->h_front_porch -
468*b843c749SSergey Zigachev crtc_timing->h_sync_width;
469*b843c749SSergey Zigachev
470*b843c749SSergey Zigachev /* start at begining of left border */
471*b843c749SSergey Zigachev h_active_start = crtc_timing->h_sync_width + h_back_porch;
472*b843c749SSergey Zigachev
473*b843c749SSergey Zigachev
474*b843c749SSergey Zigachev v_active_start = crtc_timing->v_total - crtc_timing->v_border_top -
475*b843c749SSergey Zigachev crtc_timing->v_addressable - crtc_timing->v_border_bottom -
476*b843c749SSergey Zigachev crtc_timing->v_front_porch;
477*b843c749SSergey Zigachev
478*b843c749SSergey Zigachev
479*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
480*b843c749SSergey Zigachev /* start at begining of left border */
481*b843c749SSergey Zigachev if (REG(DP_MSA_TIMING_PARAM2))
482*b843c749SSergey Zigachev REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
483*b843c749SSergey Zigachev DP_MSA_HSTART, h_active_start,
484*b843c749SSergey Zigachev DP_MSA_VSTART, v_active_start);
485*b843c749SSergey Zigachev
486*b843c749SSergey Zigachev if (REG(DP_MSA_TIMING_PARAM3))
487*b843c749SSergey Zigachev REG_SET_4(DP_MSA_TIMING_PARAM3, 0,
488*b843c749SSergey Zigachev DP_MSA_HSYNCWIDTH,
489*b843c749SSergey Zigachev crtc_timing->h_sync_width,
490*b843c749SSergey Zigachev DP_MSA_HSYNCPOLARITY,
491*b843c749SSergey Zigachev !crtc_timing->flags.HSYNC_POSITIVE_POLARITY,
492*b843c749SSergey Zigachev DP_MSA_VSYNCWIDTH,
493*b843c749SSergey Zigachev crtc_timing->v_sync_width,
494*b843c749SSergey Zigachev DP_MSA_VSYNCPOLARITY,
495*b843c749SSergey Zigachev !crtc_timing->flags.VSYNC_POSITIVE_POLARITY);
496*b843c749SSergey Zigachev
497*b843c749SSergey Zigachev /* HWDITH include border or overscan */
498*b843c749SSergey Zigachev if (REG(DP_MSA_TIMING_PARAM4))
499*b843c749SSergey Zigachev REG_SET_2(DP_MSA_TIMING_PARAM4, 0,
500*b843c749SSergey Zigachev DP_MSA_HWIDTH, crtc_timing->h_border_left +
501*b843c749SSergey Zigachev crtc_timing->h_addressable + crtc_timing->h_border_right,
502*b843c749SSergey Zigachev DP_MSA_VHEIGHT, crtc_timing->v_border_top +
503*b843c749SSergey Zigachev crtc_timing->v_addressable + crtc_timing->v_border_bottom);
504*b843c749SSergey Zigachev #endif
505*b843c749SSergey Zigachev }
506*b843c749SSergey Zigachev #endif
507*b843c749SSergey Zigachev }
508*b843c749SSergey Zigachev
dce110_stream_encoder_set_stream_attribute_helper(struct dce110_stream_encoder * enc110,struct dc_crtc_timing * crtc_timing)509*b843c749SSergey Zigachev static void dce110_stream_encoder_set_stream_attribute_helper(
510*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110,
511*b843c749SSergey Zigachev struct dc_crtc_timing *crtc_timing)
512*b843c749SSergey Zigachev {
513*b843c749SSergey Zigachev if (enc110->regs->TMDS_CNTL) {
514*b843c749SSergey Zigachev switch (crtc_timing->pixel_encoding) {
515*b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR422:
516*b843c749SSergey Zigachev REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1);
517*b843c749SSergey Zigachev break;
518*b843c749SSergey Zigachev default:
519*b843c749SSergey Zigachev REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0);
520*b843c749SSergey Zigachev break;
521*b843c749SSergey Zigachev }
522*b843c749SSergey Zigachev REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0);
523*b843c749SSergey Zigachev } else if (enc110->regs->DIG_FE_CNTL) {
524*b843c749SSergey Zigachev switch (crtc_timing->pixel_encoding) {
525*b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR422:
526*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1);
527*b843c749SSergey Zigachev break;
528*b843c749SSergey Zigachev default:
529*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0);
530*b843c749SSergey Zigachev break;
531*b843c749SSergey Zigachev }
532*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0);
533*b843c749SSergey Zigachev }
534*b843c749SSergey Zigachev
535*b843c749SSergey Zigachev }
536*b843c749SSergey Zigachev
537*b843c749SSergey Zigachev /* setup stream encoder in hdmi mode */
dce110_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)538*b843c749SSergey Zigachev static void dce110_stream_encoder_hdmi_set_stream_attribute(
539*b843c749SSergey Zigachev struct stream_encoder *enc,
540*b843c749SSergey Zigachev struct dc_crtc_timing *crtc_timing,
541*b843c749SSergey Zigachev int actual_pix_clk_khz,
542*b843c749SSergey Zigachev bool enable_audio)
543*b843c749SSergey Zigachev {
544*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
545*b843c749SSergey Zigachev struct bp_encoder_control cntl = {0};
546*b843c749SSergey Zigachev
547*b843c749SSergey Zigachev cntl.action = ENCODER_CONTROL_SETUP;
548*b843c749SSergey Zigachev cntl.engine_id = enc110->base.id;
549*b843c749SSergey Zigachev cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
550*b843c749SSergey Zigachev cntl.enable_dp_audio = enable_audio;
551*b843c749SSergey Zigachev cntl.pixel_clock = actual_pix_clk_khz;
552*b843c749SSergey Zigachev cntl.lanes_number = LANE_COUNT_FOUR;
553*b843c749SSergey Zigachev
554*b843c749SSergey Zigachev if (enc110->base.bp->funcs->encoder_control(
555*b843c749SSergey Zigachev enc110->base.bp, &cntl) != BP_RESULT_OK)
556*b843c749SSergey Zigachev return;
557*b843c749SSergey Zigachev
558*b843c749SSergey Zigachev dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
559*b843c749SSergey Zigachev
560*b843c749SSergey Zigachev /* setup HDMI engine */
561*b843c749SSergey Zigachev if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
562*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_CONTROL,
563*b843c749SSergey Zigachev HDMI_PACKET_GEN_VERSION, 1,
564*b843c749SSergey Zigachev HDMI_KEEPOUT_MODE, 1,
565*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 0);
566*b843c749SSergey Zigachev } else if (enc110->regs->DIG_FE_CNTL) {
567*b843c749SSergey Zigachev REG_UPDATE_5(HDMI_CONTROL,
568*b843c749SSergey Zigachev HDMI_PACKET_GEN_VERSION, 1,
569*b843c749SSergey Zigachev HDMI_KEEPOUT_MODE, 1,
570*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 0,
571*b843c749SSergey Zigachev HDMI_DATA_SCRAMBLE_EN, 0,
572*b843c749SSergey Zigachev HDMI_CLOCK_CHANNEL_RATE, 0);
573*b843c749SSergey Zigachev }
574*b843c749SSergey Zigachev
575*b843c749SSergey Zigachev switch (crtc_timing->display_color_depth) {
576*b843c749SSergey Zigachev case COLOR_DEPTH_888:
577*b843c749SSergey Zigachev REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
578*b843c749SSergey Zigachev break;
579*b843c749SSergey Zigachev case COLOR_DEPTH_101010:
580*b843c749SSergey Zigachev if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
581*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
582*b843c749SSergey Zigachev HDMI_DEEP_COLOR_DEPTH, 1,
583*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 0);
584*b843c749SSergey Zigachev } else {
585*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
586*b843c749SSergey Zigachev HDMI_DEEP_COLOR_DEPTH, 1,
587*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 1);
588*b843c749SSergey Zigachev }
589*b843c749SSergey Zigachev break;
590*b843c749SSergey Zigachev case COLOR_DEPTH_121212:
591*b843c749SSergey Zigachev if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
592*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
593*b843c749SSergey Zigachev HDMI_DEEP_COLOR_DEPTH, 2,
594*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 0);
595*b843c749SSergey Zigachev } else {
596*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
597*b843c749SSergey Zigachev HDMI_DEEP_COLOR_DEPTH, 2,
598*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 1);
599*b843c749SSergey Zigachev }
600*b843c749SSergey Zigachev break;
601*b843c749SSergey Zigachev case COLOR_DEPTH_161616:
602*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
603*b843c749SSergey Zigachev HDMI_DEEP_COLOR_DEPTH, 3,
604*b843c749SSergey Zigachev HDMI_DEEP_COLOR_ENABLE, 1);
605*b843c749SSergey Zigachev break;
606*b843c749SSergey Zigachev default:
607*b843c749SSergey Zigachev break;
608*b843c749SSergey Zigachev }
609*b843c749SSergey Zigachev
610*b843c749SSergey Zigachev if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) {
611*b843c749SSergey Zigachev if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
612*b843c749SSergey Zigachev /* enable HDMI data scrambler
613*b843c749SSergey Zigachev * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
614*b843c749SSergey Zigachev * Clock channel frequency is 1/4 of character rate.
615*b843c749SSergey Zigachev */
616*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
617*b843c749SSergey Zigachev HDMI_DATA_SCRAMBLE_EN, 1,
618*b843c749SSergey Zigachev HDMI_CLOCK_CHANNEL_RATE, 1);
619*b843c749SSergey Zigachev } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
620*b843c749SSergey Zigachev
621*b843c749SSergey Zigachev /* TODO: New feature for DCE11, still need to implement */
622*b843c749SSergey Zigachev
623*b843c749SSergey Zigachev /* enable HDMI data scrambler
624*b843c749SSergey Zigachev * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
625*b843c749SSergey Zigachev * Clock channel frequency is the same
626*b843c749SSergey Zigachev * as character rate
627*b843c749SSergey Zigachev */
628*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_CONTROL,
629*b843c749SSergey Zigachev HDMI_DATA_SCRAMBLE_EN, 1,
630*b843c749SSergey Zigachev HDMI_CLOCK_CHANNEL_RATE, 0);
631*b843c749SSergey Zigachev }
632*b843c749SSergey Zigachev }
633*b843c749SSergey Zigachev
634*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
635*b843c749SSergey Zigachev HDMI_GC_CONT, 1,
636*b843c749SSergey Zigachev HDMI_GC_SEND, 1,
637*b843c749SSergey Zigachev HDMI_NULL_SEND, 1);
638*b843c749SSergey Zigachev
639*b843c749SSergey Zigachev /* following belongs to audio */
640*b843c749SSergey Zigachev REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
641*b843c749SSergey Zigachev
642*b843c749SSergey Zigachev REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
643*b843c749SSergey Zigachev
644*b843c749SSergey Zigachev REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
645*b843c749SSergey Zigachev VBI_LINE_0 + 2);
646*b843c749SSergey Zigachev
647*b843c749SSergey Zigachev REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
648*b843c749SSergey Zigachev
649*b843c749SSergey Zigachev }
650*b843c749SSergey Zigachev
651*b843c749SSergey Zigachev /* setup stream encoder in dvi mode */
dce110_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)652*b843c749SSergey Zigachev static void dce110_stream_encoder_dvi_set_stream_attribute(
653*b843c749SSergey Zigachev struct stream_encoder *enc,
654*b843c749SSergey Zigachev struct dc_crtc_timing *crtc_timing,
655*b843c749SSergey Zigachev bool is_dual_link)
656*b843c749SSergey Zigachev {
657*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
658*b843c749SSergey Zigachev struct bp_encoder_control cntl = {0};
659*b843c749SSergey Zigachev
660*b843c749SSergey Zigachev cntl.action = ENCODER_CONTROL_SETUP;
661*b843c749SSergey Zigachev cntl.engine_id = enc110->base.id;
662*b843c749SSergey Zigachev cntl.signal = is_dual_link ?
663*b843c749SSergey Zigachev SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
664*b843c749SSergey Zigachev cntl.enable_dp_audio = false;
665*b843c749SSergey Zigachev cntl.pixel_clock = crtc_timing->pix_clk_khz;
666*b843c749SSergey Zigachev cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
667*b843c749SSergey Zigachev
668*b843c749SSergey Zigachev if (enc110->base.bp->funcs->encoder_control(
669*b843c749SSergey Zigachev enc110->base.bp, &cntl) != BP_RESULT_OK)
670*b843c749SSergey Zigachev return;
671*b843c749SSergey Zigachev
672*b843c749SSergey Zigachev ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
673*b843c749SSergey Zigachev ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
674*b843c749SSergey Zigachev dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing);
675*b843c749SSergey Zigachev }
676*b843c749SSergey Zigachev
dce110_stream_encoder_set_mst_bandwidth(struct stream_encoder * enc,struct fixed31_32 avg_time_slots_per_mtp)677*b843c749SSergey Zigachev static void dce110_stream_encoder_set_mst_bandwidth(
678*b843c749SSergey Zigachev struct stream_encoder *enc,
679*b843c749SSergey Zigachev struct fixed31_32 avg_time_slots_per_mtp)
680*b843c749SSergey Zigachev {
681*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
682*b843c749SSergey Zigachev uint32_t x = dc_fixpt_floor(
683*b843c749SSergey Zigachev avg_time_slots_per_mtp);
684*b843c749SSergey Zigachev uint32_t y = dc_fixpt_ceil(
685*b843c749SSergey Zigachev dc_fixpt_shl(
686*b843c749SSergey Zigachev dc_fixpt_sub_int(
687*b843c749SSergey Zigachev avg_time_slots_per_mtp,
688*b843c749SSergey Zigachev x),
689*b843c749SSergey Zigachev 26));
690*b843c749SSergey Zigachev
691*b843c749SSergey Zigachev {
692*b843c749SSergey Zigachev REG_SET_2(DP_MSE_RATE_CNTL, 0,
693*b843c749SSergey Zigachev DP_MSE_RATE_X, x,
694*b843c749SSergey Zigachev DP_MSE_RATE_Y, y);
695*b843c749SSergey Zigachev }
696*b843c749SSergey Zigachev
697*b843c749SSergey Zigachev /* wait for update to be completed on the link */
698*b843c749SSergey Zigachev /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */
699*b843c749SSergey Zigachev /* is reset to 0 (not pending) */
700*b843c749SSergey Zigachev REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING,
701*b843c749SSergey Zigachev 0,
702*b843c749SSergey Zigachev 10, DP_MST_UPDATE_MAX_RETRY);
703*b843c749SSergey Zigachev }
704*b843c749SSergey Zigachev
dce110_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)705*b843c749SSergey Zigachev static void dce110_stream_encoder_update_hdmi_info_packets(
706*b843c749SSergey Zigachev struct stream_encoder *enc,
707*b843c749SSergey Zigachev const struct encoder_info_frame *info_frame)
708*b843c749SSergey Zigachev {
709*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
710*b843c749SSergey Zigachev
711*b843c749SSergey Zigachev if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
712*b843c749SSergey Zigachev enc110->se_mask->HDMI_AVI_INFO_SEND) {
713*b843c749SSergey Zigachev
714*b843c749SSergey Zigachev if (info_frame->avi.valid) {
715*b843c749SSergey Zigachev const uint32_t *content =
716*b843c749SSergey Zigachev (const uint32_t *) &info_frame->avi.sb[0];
717*b843c749SSergey Zigachev /*we need turn on clock before programming AFMT block*/
718*b843c749SSergey Zigachev if (REG(AFMT_CNTL))
719*b843c749SSergey Zigachev REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
720*b843c749SSergey Zigachev
721*b843c749SSergey Zigachev REG_WRITE(AFMT_AVI_INFO0, content[0]);
722*b843c749SSergey Zigachev
723*b843c749SSergey Zigachev REG_WRITE(AFMT_AVI_INFO1, content[1]);
724*b843c749SSergey Zigachev
725*b843c749SSergey Zigachev REG_WRITE(AFMT_AVI_INFO2, content[2]);
726*b843c749SSergey Zigachev
727*b843c749SSergey Zigachev REG_WRITE(AFMT_AVI_INFO3, content[3]);
728*b843c749SSergey Zigachev
729*b843c749SSergey Zigachev REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION,
730*b843c749SSergey Zigachev info_frame->avi.hb1);
731*b843c749SSergey Zigachev
732*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
733*b843c749SSergey Zigachev HDMI_AVI_INFO_SEND, 1,
734*b843c749SSergey Zigachev HDMI_AVI_INFO_CONT, 1);
735*b843c749SSergey Zigachev
736*b843c749SSergey Zigachev REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE,
737*b843c749SSergey Zigachev VBI_LINE_0 + 2);
738*b843c749SSergey Zigachev
739*b843c749SSergey Zigachev } else {
740*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0,
741*b843c749SSergey Zigachev HDMI_AVI_INFO_SEND, 0,
742*b843c749SSergey Zigachev HDMI_AVI_INFO_CONT, 0);
743*b843c749SSergey Zigachev }
744*b843c749SSergey Zigachev }
745*b843c749SSergey Zigachev
746*b843c749SSergey Zigachev if (enc110->se_mask->HDMI_AVI_INFO_CONT &&
747*b843c749SSergey Zigachev enc110->se_mask->HDMI_AVI_INFO_SEND) {
748*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor);
749*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut);
750*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd);
751*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
752*b843c749SSergey Zigachev }
753*b843c749SSergey Zigachev
754*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
755*b843c749SSergey Zigachev if (enc110->se_mask->HDMI_DB_DISABLE) {
756*b843c749SSergey Zigachev /* for bring up, disable dp double TODO */
757*b843c749SSergey Zigachev if (REG(HDMI_DB_CONTROL))
758*b843c749SSergey Zigachev REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
759*b843c749SSergey Zigachev
760*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi);
761*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor);
762*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut);
763*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd);
764*b843c749SSergey Zigachev dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd);
765*b843c749SSergey Zigachev }
766*b843c749SSergey Zigachev #endif
767*b843c749SSergey Zigachev }
768*b843c749SSergey Zigachev
dce110_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)769*b843c749SSergey Zigachev static void dce110_stream_encoder_stop_hdmi_info_packets(
770*b843c749SSergey Zigachev struct stream_encoder *enc)
771*b843c749SSergey Zigachev {
772*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
773*b843c749SSergey Zigachev
774*b843c749SSergey Zigachev /* stop generic packets 0 & 1 on HDMI */
775*b843c749SSergey Zigachev REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0,
776*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, 0,
777*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, 0,
778*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, 0,
779*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, 0,
780*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, 0,
781*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, 0);
782*b843c749SSergey Zigachev
783*b843c749SSergey Zigachev /* stop generic packets 2 & 3 on HDMI */
784*b843c749SSergey Zigachev REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0,
785*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, 0,
786*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, 0,
787*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, 0,
788*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, 0,
789*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, 0,
790*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, 0);
791*b843c749SSergey Zigachev
792*b843c749SSergey Zigachev #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
793*b843c749SSergey Zigachev /* stop generic packets 2 & 3 on HDMI */
794*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL2))
795*b843c749SSergey Zigachev REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
796*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, 0,
797*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, 0,
798*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, 0,
799*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, 0,
800*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, 0,
801*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, 0);
802*b843c749SSergey Zigachev
803*b843c749SSergey Zigachev if (REG(HDMI_GENERIC_PACKET_CONTROL3))
804*b843c749SSergey Zigachev REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0,
805*b843c749SSergey Zigachev HDMI_GENERIC0_CONT, 0,
806*b843c749SSergey Zigachev HDMI_GENERIC0_LINE, 0,
807*b843c749SSergey Zigachev HDMI_GENERIC0_SEND, 0,
808*b843c749SSergey Zigachev HDMI_GENERIC1_CONT, 0,
809*b843c749SSergey Zigachev HDMI_GENERIC1_LINE, 0,
810*b843c749SSergey Zigachev HDMI_GENERIC1_SEND, 0);
811*b843c749SSergey Zigachev #endif
812*b843c749SSergey Zigachev }
813*b843c749SSergey Zigachev
dce110_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)814*b843c749SSergey Zigachev static void dce110_stream_encoder_update_dp_info_packets(
815*b843c749SSergey Zigachev struct stream_encoder *enc,
816*b843c749SSergey Zigachev const struct encoder_info_frame *info_frame)
817*b843c749SSergey Zigachev {
818*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
819*b843c749SSergey Zigachev uint32_t value = 0;
820*b843c749SSergey Zigachev
821*b843c749SSergey Zigachev if (info_frame->vsc.valid)
822*b843c749SSergey Zigachev dce110_update_generic_info_packet(
823*b843c749SSergey Zigachev enc110,
824*b843c749SSergey Zigachev 0, /* packetIndex */
825*b843c749SSergey Zigachev &info_frame->vsc);
826*b843c749SSergey Zigachev
827*b843c749SSergey Zigachev if (info_frame->spd.valid)
828*b843c749SSergey Zigachev dce110_update_generic_info_packet(
829*b843c749SSergey Zigachev enc110,
830*b843c749SSergey Zigachev 2, /* packetIndex */
831*b843c749SSergey Zigachev &info_frame->spd);
832*b843c749SSergey Zigachev
833*b843c749SSergey Zigachev if (info_frame->hdrsmd.valid)
834*b843c749SSergey Zigachev dce110_update_generic_info_packet(
835*b843c749SSergey Zigachev enc110,
836*b843c749SSergey Zigachev 3, /* packetIndex */
837*b843c749SSergey Zigachev &info_frame->hdrsmd);
838*b843c749SSergey Zigachev
839*b843c749SSergey Zigachev /* enable/disable transmission of packet(s).
840*b843c749SSergey Zigachev * If enabled, packet transmission begins on the next frame
841*b843c749SSergey Zigachev */
842*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
843*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
844*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
845*b843c749SSergey Zigachev
846*b843c749SSergey Zigachev /* This bit is the master enable bit.
847*b843c749SSergey Zigachev * When enabling secondary stream engine,
848*b843c749SSergey Zigachev * this master bit must also be set.
849*b843c749SSergey Zigachev * This register shared with audio info frame.
850*b843c749SSergey Zigachev * Therefore we need to enable master bit
851*b843c749SSergey Zigachev * if at least on of the fields is not 0
852*b843c749SSergey Zigachev */
853*b843c749SSergey Zigachev value = REG_READ(DP_SEC_CNTL);
854*b843c749SSergey Zigachev if (value)
855*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
856*b843c749SSergey Zigachev }
857*b843c749SSergey Zigachev
dce110_stream_encoder_stop_dp_info_packets(struct stream_encoder * enc)858*b843c749SSergey Zigachev static void dce110_stream_encoder_stop_dp_info_packets(
859*b843c749SSergey Zigachev struct stream_encoder *enc)
860*b843c749SSergey Zigachev {
861*b843c749SSergey Zigachev /* stop generic packets on DP */
862*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
863*b843c749SSergey Zigachev uint32_t value = 0;
864*b843c749SSergey Zigachev
865*b843c749SSergey Zigachev if (enc110->se_mask->DP_SEC_AVI_ENABLE) {
866*b843c749SSergey Zigachev REG_SET_7(DP_SEC_CNTL, 0,
867*b843c749SSergey Zigachev DP_SEC_GSP0_ENABLE, 0,
868*b843c749SSergey Zigachev DP_SEC_GSP1_ENABLE, 0,
869*b843c749SSergey Zigachev DP_SEC_GSP2_ENABLE, 0,
870*b843c749SSergey Zigachev DP_SEC_GSP3_ENABLE, 0,
871*b843c749SSergey Zigachev DP_SEC_AVI_ENABLE, 0,
872*b843c749SSergey Zigachev DP_SEC_MPG_ENABLE, 0,
873*b843c749SSergey Zigachev DP_SEC_STREAM_ENABLE, 0);
874*b843c749SSergey Zigachev }
875*b843c749SSergey Zigachev
876*b843c749SSergey Zigachev /* this register shared with audio info frame.
877*b843c749SSergey Zigachev * therefore we need to keep master enabled
878*b843c749SSergey Zigachev * if at least one of the fields is not 0 */
879*b843c749SSergey Zigachev value = REG_READ(DP_SEC_CNTL);
880*b843c749SSergey Zigachev if (value)
881*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
882*b843c749SSergey Zigachev
883*b843c749SSergey Zigachev }
884*b843c749SSergey Zigachev
dce110_stream_encoder_dp_blank(struct stream_encoder * enc)885*b843c749SSergey Zigachev static void dce110_stream_encoder_dp_blank(
886*b843c749SSergey Zigachev struct stream_encoder *enc)
887*b843c749SSergey Zigachev {
888*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
889*b843c749SSergey Zigachev uint32_t retries = 0;
890*b843c749SSergey Zigachev uint32_t reg1 = 0;
891*b843c749SSergey Zigachev uint32_t max_retries = DP_BLANK_MAX_RETRY * 10;
892*b843c749SSergey Zigachev
893*b843c749SSergey Zigachev /* Note: For CZ, we are changing driver default to disable
894*b843c749SSergey Zigachev * stream deferred to next VBLANK. If results are positive, we
895*b843c749SSergey Zigachev * will make the same change to all DCE versions. There are a
896*b843c749SSergey Zigachev * handful of panels that cannot handle disable stream at
897*b843c749SSergey Zigachev * HBLANK and will result in a white line flash across the
898*b843c749SSergey Zigachev * screen on stream disable. */
899*b843c749SSergey Zigachev REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1);
900*b843c749SSergey Zigachev if ((reg1 & 0x1) == 0)
901*b843c749SSergey Zigachev /*stream not enabled*/
902*b843c749SSergey Zigachev return;
903*b843c749SSergey Zigachev /* Specify the video stream disable point
904*b843c749SSergey Zigachev * (2 = start of the next vertical blank) */
905*b843c749SSergey Zigachev REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2);
906*b843c749SSergey Zigachev /* Larger delay to wait until VBLANK - use max retry of
907*b843c749SSergey Zigachev * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode +
908*b843c749SSergey Zigachev * a little more because we may not trust delay accuracy.
909*b843c749SSergey Zigachev */
910*b843c749SSergey Zigachev max_retries = DP_BLANK_MAX_RETRY * 150;
911*b843c749SSergey Zigachev
912*b843c749SSergey Zigachev /* disable DP stream */
913*b843c749SSergey Zigachev REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0);
914*b843c749SSergey Zigachev
915*b843c749SSergey Zigachev /* the encoder stops sending the video stream
916*b843c749SSergey Zigachev * at the start of the vertical blanking.
917*b843c749SSergey Zigachev * Poll for DP_VID_STREAM_STATUS == 0
918*b843c749SSergey Zigachev */
919*b843c749SSergey Zigachev
920*b843c749SSergey Zigachev REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS,
921*b843c749SSergey Zigachev 0,
922*b843c749SSergey Zigachev 10, max_retries);
923*b843c749SSergey Zigachev
924*b843c749SSergey Zigachev ASSERT(retries <= max_retries);
925*b843c749SSergey Zigachev
926*b843c749SSergey Zigachev /* Tell the DP encoder to ignore timing from CRTC, must be done after
927*b843c749SSergey Zigachev * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is
928*b843c749SSergey Zigachev * complete, stream status will be stuck in video stream enabled state,
929*b843c749SSergey Zigachev * i.e. DP_VID_STREAM_STATUS stuck at 1.
930*b843c749SSergey Zigachev */
931*b843c749SSergey Zigachev
932*b843c749SSergey Zigachev REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true);
933*b843c749SSergey Zigachev }
934*b843c749SSergey Zigachev
935*b843c749SSergey Zigachev /* output video stream to link encoder */
dce110_stream_encoder_dp_unblank(struct stream_encoder * enc,const struct encoder_unblank_param * param)936*b843c749SSergey Zigachev static void dce110_stream_encoder_dp_unblank(
937*b843c749SSergey Zigachev struct stream_encoder *enc,
938*b843c749SSergey Zigachev const struct encoder_unblank_param *param)
939*b843c749SSergey Zigachev {
940*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
941*b843c749SSergey Zigachev
942*b843c749SSergey Zigachev if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) {
943*b843c749SSergey Zigachev uint32_t n_vid = 0x8000;
944*b843c749SSergey Zigachev uint32_t m_vid;
945*b843c749SSergey Zigachev
946*b843c749SSergey Zigachev /* M / N = Fstream / Flink
947*b843c749SSergey Zigachev * m_vid / n_vid = pixel rate / link rate
948*b843c749SSergey Zigachev */
949*b843c749SSergey Zigachev
950*b843c749SSergey Zigachev uint64_t m_vid_l = n_vid;
951*b843c749SSergey Zigachev
952*b843c749SSergey Zigachev m_vid_l *= param->pixel_clk_khz;
953*b843c749SSergey Zigachev m_vid_l = div_u64(m_vid_l,
954*b843c749SSergey Zigachev param->link_settings.link_rate
955*b843c749SSergey Zigachev * LINK_RATE_REF_FREQ_IN_KHZ);
956*b843c749SSergey Zigachev
957*b843c749SSergey Zigachev m_vid = (uint32_t) m_vid_l;
958*b843c749SSergey Zigachev
959*b843c749SSergey Zigachev /* enable auto measurement */
960*b843c749SSergey Zigachev
961*b843c749SSergey Zigachev REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
962*b843c749SSergey Zigachev
963*b843c749SSergey Zigachev /* auto measurement need 1 full 0x8000 symbol cycle to kick in,
964*b843c749SSergey Zigachev * therefore program initial value for Mvid and Nvid
965*b843c749SSergey Zigachev */
966*b843c749SSergey Zigachev
967*b843c749SSergey Zigachev REG_UPDATE(DP_VID_N, DP_VID_N, n_vid);
968*b843c749SSergey Zigachev
969*b843c749SSergey Zigachev REG_UPDATE(DP_VID_M, DP_VID_M, m_vid);
970*b843c749SSergey Zigachev
971*b843c749SSergey Zigachev REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
972*b843c749SSergey Zigachev }
973*b843c749SSergey Zigachev
974*b843c749SSergey Zigachev /* set DIG_START to 0x1 to resync FIFO */
975*b843c749SSergey Zigachev
976*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
977*b843c749SSergey Zigachev
978*b843c749SSergey Zigachev /* switch DP encoder to CRTC data */
979*b843c749SSergey Zigachev
980*b843c749SSergey Zigachev REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0);
981*b843c749SSergey Zigachev
982*b843c749SSergey Zigachev /* wait 100us for DIG/DP logic to prime
983*b843c749SSergey Zigachev * (i.e. a few video lines)
984*b843c749SSergey Zigachev */
985*b843c749SSergey Zigachev udelay(100);
986*b843c749SSergey Zigachev
987*b843c749SSergey Zigachev /* the hardware would start sending video at the start of the next DP
988*b843c749SSergey Zigachev * frame (i.e. rising edge of the vblank).
989*b843c749SSergey Zigachev * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this
990*b843c749SSergey Zigachev * register has no effect on enable transition! HW always guarantees
991*b843c749SSergey Zigachev * VID_STREAM enable at start of next frame, and this is not
992*b843c749SSergey Zigachev * programmable
993*b843c749SSergey Zigachev */
994*b843c749SSergey Zigachev
995*b843c749SSergey Zigachev REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true);
996*b843c749SSergey Zigachev }
997*b843c749SSergey Zigachev
dce110_stream_encoder_set_avmute(struct stream_encoder * enc,bool enable)998*b843c749SSergey Zigachev static void dce110_stream_encoder_set_avmute(
999*b843c749SSergey Zigachev struct stream_encoder *enc,
1000*b843c749SSergey Zigachev bool enable)
1001*b843c749SSergey Zigachev {
1002*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1003*b843c749SSergey Zigachev unsigned int value = enable ? 1 : 0;
1004*b843c749SSergey Zigachev
1005*b843c749SSergey Zigachev REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value);
1006*b843c749SSergey Zigachev }
1007*b843c749SSergey Zigachev
1008*b843c749SSergey Zigachev
1009*b843c749SSergey Zigachev #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
1010*b843c749SSergey Zigachev #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
1011*b843c749SSergey Zigachev
1012*b843c749SSergey Zigachev #include "include/audio_types.h"
1013*b843c749SSergey Zigachev
1014*b843c749SSergey Zigachev /**
1015*b843c749SSergey Zigachev * speakersToChannels
1016*b843c749SSergey Zigachev *
1017*b843c749SSergey Zigachev * @brief
1018*b843c749SSergey Zigachev * translate speakers to channels
1019*b843c749SSergey Zigachev *
1020*b843c749SSergey Zigachev * FL - Front Left
1021*b843c749SSergey Zigachev * FR - Front Right
1022*b843c749SSergey Zigachev * RL - Rear Left
1023*b843c749SSergey Zigachev * RR - Rear Right
1024*b843c749SSergey Zigachev * RC - Rear Center
1025*b843c749SSergey Zigachev * FC - Front Center
1026*b843c749SSergey Zigachev * FLC - Front Left Center
1027*b843c749SSergey Zigachev * FRC - Front Right Center
1028*b843c749SSergey Zigachev * RLC - Rear Left Center
1029*b843c749SSergey Zigachev * RRC - Rear Right Center
1030*b843c749SSergey Zigachev * LFE - Low Freq Effect
1031*b843c749SSergey Zigachev *
1032*b843c749SSergey Zigachev * FC
1033*b843c749SSergey Zigachev * FLC FRC
1034*b843c749SSergey Zigachev * FL FR
1035*b843c749SSergey Zigachev *
1036*b843c749SSergey Zigachev * LFE
1037*b843c749SSergey Zigachev * ()
1038*b843c749SSergey Zigachev *
1039*b843c749SSergey Zigachev *
1040*b843c749SSergey Zigachev * RL RR
1041*b843c749SSergey Zigachev * RLC RRC
1042*b843c749SSergey Zigachev * RC
1043*b843c749SSergey Zigachev *
1044*b843c749SSergey Zigachev * ch 8 7 6 5 4 3 2 1
1045*b843c749SSergey Zigachev * 0b00000011 - - - - - - FR FL
1046*b843c749SSergey Zigachev * 0b00000111 - - - - - LFE FR FL
1047*b843c749SSergey Zigachev * 0b00001011 - - - - FC - FR FL
1048*b843c749SSergey Zigachev * 0b00001111 - - - - FC LFE FR FL
1049*b843c749SSergey Zigachev * 0b00010011 - - - RC - - FR FL
1050*b843c749SSergey Zigachev * 0b00010111 - - - RC - LFE FR FL
1051*b843c749SSergey Zigachev * 0b00011011 - - - RC FC - FR FL
1052*b843c749SSergey Zigachev * 0b00011111 - - - RC FC LFE FR FL
1053*b843c749SSergey Zigachev * 0b00110011 - - RR RL - - FR FL
1054*b843c749SSergey Zigachev * 0b00110111 - - RR RL - LFE FR FL
1055*b843c749SSergey Zigachev * 0b00111011 - - RR RL FC - FR FL
1056*b843c749SSergey Zigachev * 0b00111111 - - RR RL FC LFE FR FL
1057*b843c749SSergey Zigachev * 0b01110011 - RC RR RL - - FR FL
1058*b843c749SSergey Zigachev * 0b01110111 - RC RR RL - LFE FR FL
1059*b843c749SSergey Zigachev * 0b01111011 - RC RR RL FC - FR FL
1060*b843c749SSergey Zigachev * 0b01111111 - RC RR RL FC LFE FR FL
1061*b843c749SSergey Zigachev * 0b11110011 RRC RLC RR RL - - FR FL
1062*b843c749SSergey Zigachev * 0b11110111 RRC RLC RR RL - LFE FR FL
1063*b843c749SSergey Zigachev * 0b11111011 RRC RLC RR RL FC - FR FL
1064*b843c749SSergey Zigachev * 0b11111111 RRC RLC RR RL FC LFE FR FL
1065*b843c749SSergey Zigachev * 0b11000011 FRC FLC - - - - FR FL
1066*b843c749SSergey Zigachev * 0b11000111 FRC FLC - - - LFE FR FL
1067*b843c749SSergey Zigachev * 0b11001011 FRC FLC - - FC - FR FL
1068*b843c749SSergey Zigachev * 0b11001111 FRC FLC - - FC LFE FR FL
1069*b843c749SSergey Zigachev * 0b11010011 FRC FLC - RC - - FR FL
1070*b843c749SSergey Zigachev * 0b11010111 FRC FLC - RC - LFE FR FL
1071*b843c749SSergey Zigachev * 0b11011011 FRC FLC - RC FC - FR FL
1072*b843c749SSergey Zigachev * 0b11011111 FRC FLC - RC FC LFE FR FL
1073*b843c749SSergey Zigachev * 0b11110011 FRC FLC RR RL - - FR FL
1074*b843c749SSergey Zigachev * 0b11110111 FRC FLC RR RL - LFE FR FL
1075*b843c749SSergey Zigachev * 0b11111011 FRC FLC RR RL FC - FR FL
1076*b843c749SSergey Zigachev * 0b11111111 FRC FLC RR RL FC LFE FR FL
1077*b843c749SSergey Zigachev *
1078*b843c749SSergey Zigachev * @param
1079*b843c749SSergey Zigachev * speakers - speaker information as it comes from CEA audio block
1080*b843c749SSergey Zigachev */
1081*b843c749SSergey Zigachev /* translate speakers to channels */
1082*b843c749SSergey Zigachev
1083*b843c749SSergey Zigachev union audio_cea_channels {
1084*b843c749SSergey Zigachev uint8_t all;
1085*b843c749SSergey Zigachev struct audio_cea_channels_bits {
1086*b843c749SSergey Zigachev uint32_t FL:1;
1087*b843c749SSergey Zigachev uint32_t FR:1;
1088*b843c749SSergey Zigachev uint32_t LFE:1;
1089*b843c749SSergey Zigachev uint32_t FC:1;
1090*b843c749SSergey Zigachev uint32_t RL_RC:1;
1091*b843c749SSergey Zigachev uint32_t RR:1;
1092*b843c749SSergey Zigachev uint32_t RC_RLC_FLC:1;
1093*b843c749SSergey Zigachev uint32_t RRC_FRC:1;
1094*b843c749SSergey Zigachev } channels;
1095*b843c749SSergey Zigachev };
1096*b843c749SSergey Zigachev
1097*b843c749SSergey Zigachev struct audio_clock_info {
1098*b843c749SSergey Zigachev /* pixel clock frequency*/
1099*b843c749SSergey Zigachev uint32_t pixel_clock_in_10khz;
1100*b843c749SSergey Zigachev /* N - 32KHz audio */
1101*b843c749SSergey Zigachev uint32_t n_32khz;
1102*b843c749SSergey Zigachev /* CTS - 32KHz audio*/
1103*b843c749SSergey Zigachev uint32_t cts_32khz;
1104*b843c749SSergey Zigachev uint32_t n_44khz;
1105*b843c749SSergey Zigachev uint32_t cts_44khz;
1106*b843c749SSergey Zigachev uint32_t n_48khz;
1107*b843c749SSergey Zigachev uint32_t cts_48khz;
1108*b843c749SSergey Zigachev };
1109*b843c749SSergey Zigachev
1110*b843c749SSergey Zigachev /* 25.2MHz/1.001*/
1111*b843c749SSergey Zigachev /* 25.2MHz/1.001*/
1112*b843c749SSergey Zigachev /* 25.2MHz*/
1113*b843c749SSergey Zigachev /* 27MHz */
1114*b843c749SSergey Zigachev /* 27MHz*1.001*/
1115*b843c749SSergey Zigachev /* 27MHz*1.001*/
1116*b843c749SSergey Zigachev /* 54MHz*/
1117*b843c749SSergey Zigachev /* 54MHz*1.001*/
1118*b843c749SSergey Zigachev /* 74.25MHz/1.001*/
1119*b843c749SSergey Zigachev /* 74.25MHz*/
1120*b843c749SSergey Zigachev /* 148.5MHz/1.001*/
1121*b843c749SSergey Zigachev /* 148.5MHz*/
1122*b843c749SSergey Zigachev
1123*b843c749SSergey Zigachev static const struct audio_clock_info audio_clock_info_table[16] = {
1124*b843c749SSergey Zigachev {2517, 4576, 28125, 7007, 31250, 6864, 28125},
1125*b843c749SSergey Zigachev {2518, 4576, 28125, 7007, 31250, 6864, 28125},
1126*b843c749SSergey Zigachev {2520, 4096, 25200, 6272, 28000, 6144, 25200},
1127*b843c749SSergey Zigachev {2700, 4096, 27000, 6272, 30000, 6144, 27000},
1128*b843c749SSergey Zigachev {2702, 4096, 27027, 6272, 30030, 6144, 27027},
1129*b843c749SSergey Zigachev {2703, 4096, 27027, 6272, 30030, 6144, 27027},
1130*b843c749SSergey Zigachev {5400, 4096, 54000, 6272, 60000, 6144, 54000},
1131*b843c749SSergey Zigachev {5405, 4096, 54054, 6272, 60060, 6144, 54054},
1132*b843c749SSergey Zigachev {7417, 11648, 210937, 17836, 234375, 11648, 140625},
1133*b843c749SSergey Zigachev {7425, 4096, 74250, 6272, 82500, 6144, 74250},
1134*b843c749SSergey Zigachev {14835, 11648, 421875, 8918, 234375, 5824, 140625},
1135*b843c749SSergey Zigachev {14850, 4096, 148500, 6272, 165000, 6144, 148500},
1136*b843c749SSergey Zigachev {29670, 5824, 421875, 4459, 234375, 5824, 281250},
1137*b843c749SSergey Zigachev {29700, 3072, 222750, 4704, 247500, 5120, 247500},
1138*b843c749SSergey Zigachev {59340, 5824, 843750, 8918, 937500, 5824, 562500},
1139*b843c749SSergey Zigachev {59400, 3072, 445500, 9408, 990000, 6144, 594000}
1140*b843c749SSergey Zigachev };
1141*b843c749SSergey Zigachev
1142*b843c749SSergey Zigachev static const struct audio_clock_info audio_clock_info_table_36bpc[14] = {
1143*b843c749SSergey Zigachev {2517, 9152, 84375, 7007, 48875, 9152, 56250},
1144*b843c749SSergey Zigachev {2518, 9152, 84375, 7007, 48875, 9152, 56250},
1145*b843c749SSergey Zigachev {2520, 4096, 37800, 6272, 42000, 6144, 37800},
1146*b843c749SSergey Zigachev {2700, 4096, 40500, 6272, 45000, 6144, 40500},
1147*b843c749SSergey Zigachev {2702, 8192, 81081, 6272, 45045, 8192, 54054},
1148*b843c749SSergey Zigachev {2703, 8192, 81081, 6272, 45045, 8192, 54054},
1149*b843c749SSergey Zigachev {5400, 4096, 81000, 6272, 90000, 6144, 81000},
1150*b843c749SSergey Zigachev {5405, 4096, 81081, 6272, 90090, 6144, 81081},
1151*b843c749SSergey Zigachev {7417, 11648, 316406, 17836, 351562, 11648, 210937},
1152*b843c749SSergey Zigachev {7425, 4096, 111375, 6272, 123750, 6144, 111375},
1153*b843c749SSergey Zigachev {14835, 11648, 632812, 17836, 703125, 11648, 421875},
1154*b843c749SSergey Zigachev {14850, 4096, 222750, 6272, 247500, 6144, 222750},
1155*b843c749SSergey Zigachev {29670, 5824, 632812, 8918, 703125, 5824, 421875},
1156*b843c749SSergey Zigachev {29700, 4096, 445500, 4704, 371250, 5120, 371250}
1157*b843c749SSergey Zigachev };
1158*b843c749SSergey Zigachev
1159*b843c749SSergey Zigachev static const struct audio_clock_info audio_clock_info_table_48bpc[14] = {
1160*b843c749SSergey Zigachev {2517, 4576, 56250, 7007, 62500, 6864, 56250},
1161*b843c749SSergey Zigachev {2518, 4576, 56250, 7007, 62500, 6864, 56250},
1162*b843c749SSergey Zigachev {2520, 4096, 50400, 6272, 56000, 6144, 50400},
1163*b843c749SSergey Zigachev {2700, 4096, 54000, 6272, 60000, 6144, 54000},
1164*b843c749SSergey Zigachev {2702, 4096, 54054, 6267, 60060, 8192, 54054},
1165*b843c749SSergey Zigachev {2703, 4096, 54054, 6272, 60060, 8192, 54054},
1166*b843c749SSergey Zigachev {5400, 4096, 108000, 6272, 120000, 6144, 108000},
1167*b843c749SSergey Zigachev {5405, 4096, 108108, 6272, 120120, 6144, 108108},
1168*b843c749SSergey Zigachev {7417, 11648, 421875, 17836, 468750, 11648, 281250},
1169*b843c749SSergey Zigachev {7425, 4096, 148500, 6272, 165000, 6144, 148500},
1170*b843c749SSergey Zigachev {14835, 11648, 843750, 8918, 468750, 11648, 281250},
1171*b843c749SSergey Zigachev {14850, 4096, 297000, 6272, 330000, 6144, 297000},
1172*b843c749SSergey Zigachev {29670, 5824, 843750, 4459, 468750, 5824, 562500},
1173*b843c749SSergey Zigachev {29700, 3072, 445500, 4704, 495000, 5120, 495000}
1174*b843c749SSergey Zigachev
1175*b843c749SSergey Zigachev
1176*b843c749SSergey Zigachev };
1177*b843c749SSergey Zigachev
speakers_to_channels(struct audio_speaker_flags speaker_flags)1178*b843c749SSergey Zigachev static union audio_cea_channels speakers_to_channels(
1179*b843c749SSergey Zigachev struct audio_speaker_flags speaker_flags)
1180*b843c749SSergey Zigachev {
1181*b843c749SSergey Zigachev union audio_cea_channels cea_channels = {0};
1182*b843c749SSergey Zigachev
1183*b843c749SSergey Zigachev /* these are one to one */
1184*b843c749SSergey Zigachev cea_channels.channels.FL = speaker_flags.FL_FR;
1185*b843c749SSergey Zigachev cea_channels.channels.FR = speaker_flags.FL_FR;
1186*b843c749SSergey Zigachev cea_channels.channels.LFE = speaker_flags.LFE;
1187*b843c749SSergey Zigachev cea_channels.channels.FC = speaker_flags.FC;
1188*b843c749SSergey Zigachev
1189*b843c749SSergey Zigachev /* if Rear Left and Right exist move RC speaker to channel 7
1190*b843c749SSergey Zigachev * otherwise to channel 5
1191*b843c749SSergey Zigachev */
1192*b843c749SSergey Zigachev if (speaker_flags.RL_RR) {
1193*b843c749SSergey Zigachev cea_channels.channels.RL_RC = speaker_flags.RL_RR;
1194*b843c749SSergey Zigachev cea_channels.channels.RR = speaker_flags.RL_RR;
1195*b843c749SSergey Zigachev cea_channels.channels.RC_RLC_FLC = speaker_flags.RC;
1196*b843c749SSergey Zigachev } else {
1197*b843c749SSergey Zigachev cea_channels.channels.RL_RC = speaker_flags.RC;
1198*b843c749SSergey Zigachev }
1199*b843c749SSergey Zigachev
1200*b843c749SSergey Zigachev /* FRONT Left Right Center and REAR Left Right Center are exclusive */
1201*b843c749SSergey Zigachev if (speaker_flags.FLC_FRC) {
1202*b843c749SSergey Zigachev cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC;
1203*b843c749SSergey Zigachev cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC;
1204*b843c749SSergey Zigachev } else {
1205*b843c749SSergey Zigachev cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC;
1206*b843c749SSergey Zigachev cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC;
1207*b843c749SSergey Zigachev }
1208*b843c749SSergey Zigachev
1209*b843c749SSergey Zigachev return cea_channels;
1210*b843c749SSergey Zigachev }
1211*b843c749SSergey Zigachev
calc_max_audio_packets_per_line(const struct audio_crtc_info * crtc_info)1212*b843c749SSergey Zigachev static uint32_t calc_max_audio_packets_per_line(
1213*b843c749SSergey Zigachev const struct audio_crtc_info *crtc_info)
1214*b843c749SSergey Zigachev {
1215*b843c749SSergey Zigachev uint32_t max_packets_per_line;
1216*b843c749SSergey Zigachev
1217*b843c749SSergey Zigachev max_packets_per_line =
1218*b843c749SSergey Zigachev crtc_info->h_total - crtc_info->h_active;
1219*b843c749SSergey Zigachev
1220*b843c749SSergey Zigachev if (crtc_info->pixel_repetition)
1221*b843c749SSergey Zigachev max_packets_per_line *= crtc_info->pixel_repetition;
1222*b843c749SSergey Zigachev
1223*b843c749SSergey Zigachev /* for other hdmi features */
1224*b843c749SSergey Zigachev max_packets_per_line -= 58;
1225*b843c749SSergey Zigachev /* for Control Period */
1226*b843c749SSergey Zigachev max_packets_per_line -= 16;
1227*b843c749SSergey Zigachev /* Number of Audio Packets per Line */
1228*b843c749SSergey Zigachev max_packets_per_line /= 32;
1229*b843c749SSergey Zigachev
1230*b843c749SSergey Zigachev return max_packets_per_line;
1231*b843c749SSergey Zigachev }
1232*b843c749SSergey Zigachev
get_audio_clock_info(enum dc_color_depth color_depth,uint32_t crtc_pixel_clock_in_khz,uint32_t actual_pixel_clock_in_khz,struct audio_clock_info * audio_clock_info)1233*b843c749SSergey Zigachev static void get_audio_clock_info(
1234*b843c749SSergey Zigachev enum dc_color_depth color_depth,
1235*b843c749SSergey Zigachev uint32_t crtc_pixel_clock_in_khz,
1236*b843c749SSergey Zigachev uint32_t actual_pixel_clock_in_khz,
1237*b843c749SSergey Zigachev struct audio_clock_info *audio_clock_info)
1238*b843c749SSergey Zigachev {
1239*b843c749SSergey Zigachev const struct audio_clock_info *clock_info;
1240*b843c749SSergey Zigachev uint32_t index;
1241*b843c749SSergey Zigachev uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10;
1242*b843c749SSergey Zigachev uint32_t audio_array_size;
1243*b843c749SSergey Zigachev
1244*b843c749SSergey Zigachev switch (color_depth) {
1245*b843c749SSergey Zigachev case COLOR_DEPTH_161616:
1246*b843c749SSergey Zigachev clock_info = audio_clock_info_table_48bpc;
1247*b843c749SSergey Zigachev audio_array_size = ARRAY_SIZE(
1248*b843c749SSergey Zigachev audio_clock_info_table_48bpc);
1249*b843c749SSergey Zigachev break;
1250*b843c749SSergey Zigachev case COLOR_DEPTH_121212:
1251*b843c749SSergey Zigachev clock_info = audio_clock_info_table_36bpc;
1252*b843c749SSergey Zigachev audio_array_size = ARRAY_SIZE(
1253*b843c749SSergey Zigachev audio_clock_info_table_36bpc);
1254*b843c749SSergey Zigachev break;
1255*b843c749SSergey Zigachev default:
1256*b843c749SSergey Zigachev clock_info = audio_clock_info_table;
1257*b843c749SSergey Zigachev audio_array_size = ARRAY_SIZE(
1258*b843c749SSergey Zigachev audio_clock_info_table);
1259*b843c749SSergey Zigachev break;
1260*b843c749SSergey Zigachev }
1261*b843c749SSergey Zigachev
1262*b843c749SSergey Zigachev if (clock_info != NULL) {
1263*b843c749SSergey Zigachev /* search for exact pixel clock in table */
1264*b843c749SSergey Zigachev for (index = 0; index < audio_array_size; index++) {
1265*b843c749SSergey Zigachev if (clock_info[index].pixel_clock_in_10khz >
1266*b843c749SSergey Zigachev crtc_pixel_clock_in_10khz)
1267*b843c749SSergey Zigachev break; /* not match */
1268*b843c749SSergey Zigachev else if (clock_info[index].pixel_clock_in_10khz ==
1269*b843c749SSergey Zigachev crtc_pixel_clock_in_10khz) {
1270*b843c749SSergey Zigachev /* match found */
1271*b843c749SSergey Zigachev *audio_clock_info = clock_info[index];
1272*b843c749SSergey Zigachev return;
1273*b843c749SSergey Zigachev }
1274*b843c749SSergey Zigachev }
1275*b843c749SSergey Zigachev }
1276*b843c749SSergey Zigachev
1277*b843c749SSergey Zigachev /* not found */
1278*b843c749SSergey Zigachev if (actual_pixel_clock_in_khz == 0)
1279*b843c749SSergey Zigachev actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz;
1280*b843c749SSergey Zigachev
1281*b843c749SSergey Zigachev /* See HDMI spec the table entry under
1282*b843c749SSergey Zigachev * pixel clock of "Other". */
1283*b843c749SSergey Zigachev audio_clock_info->pixel_clock_in_10khz =
1284*b843c749SSergey Zigachev actual_pixel_clock_in_khz / 10;
1285*b843c749SSergey Zigachev audio_clock_info->cts_32khz = actual_pixel_clock_in_khz;
1286*b843c749SSergey Zigachev audio_clock_info->cts_44khz = actual_pixel_clock_in_khz;
1287*b843c749SSergey Zigachev audio_clock_info->cts_48khz = actual_pixel_clock_in_khz;
1288*b843c749SSergey Zigachev
1289*b843c749SSergey Zigachev audio_clock_info->n_32khz = 4096;
1290*b843c749SSergey Zigachev audio_clock_info->n_44khz = 6272;
1291*b843c749SSergey Zigachev audio_clock_info->n_48khz = 6144;
1292*b843c749SSergey Zigachev }
1293*b843c749SSergey Zigachev
dce110_se_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * audio_info)1294*b843c749SSergey Zigachev static void dce110_se_audio_setup(
1295*b843c749SSergey Zigachev struct stream_encoder *enc,
1296*b843c749SSergey Zigachev unsigned int az_inst,
1297*b843c749SSergey Zigachev struct audio_info *audio_info)
1298*b843c749SSergey Zigachev {
1299*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1300*b843c749SSergey Zigachev
1301*b843c749SSergey Zigachev uint32_t speakers = 0;
1302*b843c749SSergey Zigachev uint32_t channels = 0;
1303*b843c749SSergey Zigachev
1304*b843c749SSergey Zigachev ASSERT(audio_info);
1305*b843c749SSergey Zigachev if (audio_info == NULL)
1306*b843c749SSergey Zigachev /* This should not happen.it does so we don't get BSOD*/
1307*b843c749SSergey Zigachev return;
1308*b843c749SSergey Zigachev
1309*b843c749SSergey Zigachev speakers = audio_info->flags.info.ALLSPEAKERS;
1310*b843c749SSergey Zigachev channels = speakers_to_channels(audio_info->flags.speaker_flags).all;
1311*b843c749SSergey Zigachev
1312*b843c749SSergey Zigachev /* setup the audio stream source select (audio -> dig mapping) */
1313*b843c749SSergey Zigachev REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst);
1314*b843c749SSergey Zigachev
1315*b843c749SSergey Zigachev /* Channel allocation */
1316*b843c749SSergey Zigachev REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels);
1317*b843c749SSergey Zigachev }
1318*b843c749SSergey Zigachev
dce110_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)1319*b843c749SSergey Zigachev static void dce110_se_setup_hdmi_audio(
1320*b843c749SSergey Zigachev struct stream_encoder *enc,
1321*b843c749SSergey Zigachev const struct audio_crtc_info *crtc_info)
1322*b843c749SSergey Zigachev {
1323*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1324*b843c749SSergey Zigachev
1325*b843c749SSergey Zigachev struct audio_clock_info audio_clock_info = {0};
1326*b843c749SSergey Zigachev uint32_t max_packets_per_line;
1327*b843c749SSergey Zigachev
1328*b843c749SSergey Zigachev /* For now still do calculation, although this field is ignored when
1329*b843c749SSergey Zigachev above HDMI_PACKET_GEN_VERSION set to 1 */
1330*b843c749SSergey Zigachev max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
1331*b843c749SSergey Zigachev
1332*b843c749SSergey Zigachev /* HDMI_AUDIO_PACKET_CONTROL */
1333*b843c749SSergey Zigachev REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL,
1334*b843c749SSergey Zigachev HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line,
1335*b843c749SSergey Zigachev HDMI_AUDIO_DELAY_EN, 1);
1336*b843c749SSergey Zigachev
1337*b843c749SSergey Zigachev /* AFMT_AUDIO_PACKET_CONTROL */
1338*b843c749SSergey Zigachev REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1339*b843c749SSergey Zigachev
1340*b843c749SSergey Zigachev /* AFMT_AUDIO_PACKET_CONTROL2 */
1341*b843c749SSergey Zigachev REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1342*b843c749SSergey Zigachev AFMT_AUDIO_LAYOUT_OVRD, 0,
1343*b843c749SSergey Zigachev AFMT_60958_OSF_OVRD, 0);
1344*b843c749SSergey Zigachev
1345*b843c749SSergey Zigachev /* HDMI_ACR_PACKET_CONTROL */
1346*b843c749SSergey Zigachev REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
1347*b843c749SSergey Zigachev HDMI_ACR_AUTO_SEND, 1,
1348*b843c749SSergey Zigachev HDMI_ACR_SOURCE, 0,
1349*b843c749SSergey Zigachev HDMI_ACR_AUDIO_PRIORITY, 0);
1350*b843c749SSergey Zigachev
1351*b843c749SSergey Zigachev /* Program audio clock sample/regeneration parameters */
1352*b843c749SSergey Zigachev get_audio_clock_info(crtc_info->color_depth,
1353*b843c749SSergey Zigachev crtc_info->requested_pixel_clock,
1354*b843c749SSergey Zigachev crtc_info->calculated_pixel_clock,
1355*b843c749SSergey Zigachev &audio_clock_info);
1356*b843c749SSergey Zigachev DC_LOG_HW_AUDIO(
1357*b843c749SSergey Zigachev "\n%s:Input::requested_pixel_clock = %d" \
1358*b843c749SSergey Zigachev "calculated_pixel_clock = %d \n", __func__, \
1359*b843c749SSergey Zigachev crtc_info->requested_pixel_clock, \
1360*b843c749SSergey Zigachev crtc_info->calculated_pixel_clock);
1361*b843c749SSergey Zigachev
1362*b843c749SSergey Zigachev /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
1363*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
1364*b843c749SSergey Zigachev
1365*b843c749SSergey Zigachev /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
1366*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
1367*b843c749SSergey Zigachev
1368*b843c749SSergey Zigachev /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
1369*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
1370*b843c749SSergey Zigachev
1371*b843c749SSergey Zigachev /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
1372*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
1373*b843c749SSergey Zigachev
1374*b843c749SSergey Zigachev /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
1375*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
1376*b843c749SSergey Zigachev
1377*b843c749SSergey Zigachev /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
1378*b843c749SSergey Zigachev REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
1379*b843c749SSergey Zigachev
1380*b843c749SSergey Zigachev /* Video driver cannot know in advance which sample rate will
1381*b843c749SSergey Zigachev be used by HD Audio driver
1382*b843c749SSergey Zigachev HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
1383*b843c749SSergey Zigachev programmed below in interruppt callback */
1384*b843c749SSergey Zigachev
1385*b843c749SSergey Zigachev /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
1386*b843c749SSergey Zigachev AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1387*b843c749SSergey Zigachev REG_UPDATE_2(AFMT_60958_0,
1388*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_L, 1,
1389*b843c749SSergey Zigachev AFMT_60958_CS_CLOCK_ACCURACY, 0);
1390*b843c749SSergey Zigachev
1391*b843c749SSergey Zigachev /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
1392*b843c749SSergey Zigachev REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1393*b843c749SSergey Zigachev
1394*b843c749SSergey Zigachev /*AFMT_60958_2 now keep this settings until
1395*b843c749SSergey Zigachev * Programming guide comes out*/
1396*b843c749SSergey Zigachev REG_UPDATE_6(AFMT_60958_2,
1397*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_2, 3,
1398*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_3, 4,
1399*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_4, 5,
1400*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_5, 6,
1401*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_6, 7,
1402*b843c749SSergey Zigachev AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1403*b843c749SSergey Zigachev }
1404*b843c749SSergey Zigachev
dce110_se_setup_dp_audio(struct stream_encoder * enc)1405*b843c749SSergey Zigachev static void dce110_se_setup_dp_audio(
1406*b843c749SSergey Zigachev struct stream_encoder *enc)
1407*b843c749SSergey Zigachev {
1408*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1409*b843c749SSergey Zigachev
1410*b843c749SSergey Zigachev /* --- DP Audio packet configurations --- */
1411*b843c749SSergey Zigachev
1412*b843c749SSergey Zigachev /* ATP Configuration */
1413*b843c749SSergey Zigachev REG_SET(DP_SEC_AUD_N, 0,
1414*b843c749SSergey Zigachev DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
1415*b843c749SSergey Zigachev
1416*b843c749SSergey Zigachev /* Async/auto-calc timestamp mode */
1417*b843c749SSergey Zigachev REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
1418*b843c749SSergey Zigachev DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
1419*b843c749SSergey Zigachev
1420*b843c749SSergey Zigachev /* --- The following are the registers
1421*b843c749SSergey Zigachev * copied from the SetupHDMI --- */
1422*b843c749SSergey Zigachev
1423*b843c749SSergey Zigachev /* AFMT_AUDIO_PACKET_CONTROL */
1424*b843c749SSergey Zigachev REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1425*b843c749SSergey Zigachev
1426*b843c749SSergey Zigachev /* AFMT_AUDIO_PACKET_CONTROL2 */
1427*b843c749SSergey Zigachev /* Program the ATP and AIP next */
1428*b843c749SSergey Zigachev REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2,
1429*b843c749SSergey Zigachev AFMT_AUDIO_LAYOUT_OVRD, 0,
1430*b843c749SSergey Zigachev AFMT_60958_OSF_OVRD, 0);
1431*b843c749SSergey Zigachev
1432*b843c749SSergey Zigachev /* AFMT_INFOFRAME_CONTROL0 */
1433*b843c749SSergey Zigachev REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1434*b843c749SSergey Zigachev
1435*b843c749SSergey Zigachev /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
1436*b843c749SSergey Zigachev REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
1437*b843c749SSergey Zigachev }
1438*b843c749SSergey Zigachev
dce110_se_enable_audio_clock(struct stream_encoder * enc,bool enable)1439*b843c749SSergey Zigachev static void dce110_se_enable_audio_clock(
1440*b843c749SSergey Zigachev struct stream_encoder *enc,
1441*b843c749SSergey Zigachev bool enable)
1442*b843c749SSergey Zigachev {
1443*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1444*b843c749SSergey Zigachev
1445*b843c749SSergey Zigachev if (REG(AFMT_CNTL) == 0)
1446*b843c749SSergey Zigachev return; /* DCE8/10 does not have this register */
1447*b843c749SSergey Zigachev
1448*b843c749SSergey Zigachev REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable);
1449*b843c749SSergey Zigachev
1450*b843c749SSergey Zigachev /* wait for AFMT clock to turn on,
1451*b843c749SSergey Zigachev * expectation: this should complete in 1-2 reads
1452*b843c749SSergey Zigachev *
1453*b843c749SSergey Zigachev * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10);
1454*b843c749SSergey Zigachev *
1455*b843c749SSergey Zigachev * TODO: wait for clock_on does not work well. May need HW
1456*b843c749SSergey Zigachev * program sequence. But audio seems work normally even without wait
1457*b843c749SSergey Zigachev * for clock_on status change
1458*b843c749SSergey Zigachev */
1459*b843c749SSergey Zigachev }
1460*b843c749SSergey Zigachev
dce110_se_enable_dp_audio(struct stream_encoder * enc)1461*b843c749SSergey Zigachev static void dce110_se_enable_dp_audio(
1462*b843c749SSergey Zigachev struct stream_encoder *enc)
1463*b843c749SSergey Zigachev {
1464*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1465*b843c749SSergey Zigachev
1466*b843c749SSergey Zigachev /* Enable Audio packets */
1467*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1468*b843c749SSergey Zigachev
1469*b843c749SSergey Zigachev /* Program the ATP and AIP next */
1470*b843c749SSergey Zigachev REG_UPDATE_2(DP_SEC_CNTL,
1471*b843c749SSergey Zigachev DP_SEC_ATP_ENABLE, 1,
1472*b843c749SSergey Zigachev DP_SEC_AIP_ENABLE, 1);
1473*b843c749SSergey Zigachev
1474*b843c749SSergey Zigachev /* Program STREAM_ENABLE after all the other enables. */
1475*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1476*b843c749SSergey Zigachev }
1477*b843c749SSergey Zigachev
dce110_se_disable_dp_audio(struct stream_encoder * enc)1478*b843c749SSergey Zigachev static void dce110_se_disable_dp_audio(
1479*b843c749SSergey Zigachev struct stream_encoder *enc)
1480*b843c749SSergey Zigachev {
1481*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1482*b843c749SSergey Zigachev uint32_t value = 0;
1483*b843c749SSergey Zigachev
1484*b843c749SSergey Zigachev /* Disable Audio packets */
1485*b843c749SSergey Zigachev REG_UPDATE_5(DP_SEC_CNTL,
1486*b843c749SSergey Zigachev DP_SEC_ASP_ENABLE, 0,
1487*b843c749SSergey Zigachev DP_SEC_ATP_ENABLE, 0,
1488*b843c749SSergey Zigachev DP_SEC_AIP_ENABLE, 0,
1489*b843c749SSergey Zigachev DP_SEC_ACM_ENABLE, 0,
1490*b843c749SSergey Zigachev DP_SEC_STREAM_ENABLE, 0);
1491*b843c749SSergey Zigachev
1492*b843c749SSergey Zigachev /* This register shared with encoder info frame. Therefore we need to
1493*b843c749SSergey Zigachev keep master enabled if at least on of the fields is not 0 */
1494*b843c749SSergey Zigachev value = REG_READ(DP_SEC_CNTL);
1495*b843c749SSergey Zigachev if (value != 0)
1496*b843c749SSergey Zigachev REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1497*b843c749SSergey Zigachev
1498*b843c749SSergey Zigachev }
1499*b843c749SSergey Zigachev
dce110_se_audio_mute_control(struct stream_encoder * enc,bool mute)1500*b843c749SSergey Zigachev void dce110_se_audio_mute_control(
1501*b843c749SSergey Zigachev struct stream_encoder *enc,
1502*b843c749SSergey Zigachev bool mute)
1503*b843c749SSergey Zigachev {
1504*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1505*b843c749SSergey Zigachev
1506*b843c749SSergey Zigachev REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute);
1507*b843c749SSergey Zigachev }
1508*b843c749SSergey Zigachev
dce110_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)1509*b843c749SSergey Zigachev void dce110_se_dp_audio_setup(
1510*b843c749SSergey Zigachev struct stream_encoder *enc,
1511*b843c749SSergey Zigachev unsigned int az_inst,
1512*b843c749SSergey Zigachev struct audio_info *info)
1513*b843c749SSergey Zigachev {
1514*b843c749SSergey Zigachev dce110_se_audio_setup(enc, az_inst, info);
1515*b843c749SSergey Zigachev }
1516*b843c749SSergey Zigachev
dce110_se_dp_audio_enable(struct stream_encoder * enc)1517*b843c749SSergey Zigachev void dce110_se_dp_audio_enable(
1518*b843c749SSergey Zigachev struct stream_encoder *enc)
1519*b843c749SSergey Zigachev {
1520*b843c749SSergey Zigachev dce110_se_enable_audio_clock(enc, true);
1521*b843c749SSergey Zigachev dce110_se_setup_dp_audio(enc);
1522*b843c749SSergey Zigachev dce110_se_enable_dp_audio(enc);
1523*b843c749SSergey Zigachev }
1524*b843c749SSergey Zigachev
dce110_se_dp_audio_disable(struct stream_encoder * enc)1525*b843c749SSergey Zigachev void dce110_se_dp_audio_disable(
1526*b843c749SSergey Zigachev struct stream_encoder *enc)
1527*b843c749SSergey Zigachev {
1528*b843c749SSergey Zigachev dce110_se_disable_dp_audio(enc);
1529*b843c749SSergey Zigachev dce110_se_enable_audio_clock(enc, false);
1530*b843c749SSergey Zigachev }
1531*b843c749SSergey Zigachev
dce110_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)1532*b843c749SSergey Zigachev void dce110_se_hdmi_audio_setup(
1533*b843c749SSergey Zigachev struct stream_encoder *enc,
1534*b843c749SSergey Zigachev unsigned int az_inst,
1535*b843c749SSergey Zigachev struct audio_info *info,
1536*b843c749SSergey Zigachev struct audio_crtc_info *audio_crtc_info)
1537*b843c749SSergey Zigachev {
1538*b843c749SSergey Zigachev dce110_se_enable_audio_clock(enc, true);
1539*b843c749SSergey Zigachev dce110_se_setup_hdmi_audio(enc, audio_crtc_info);
1540*b843c749SSergey Zigachev dce110_se_audio_setup(enc, az_inst, info);
1541*b843c749SSergey Zigachev }
1542*b843c749SSergey Zigachev
dce110_se_hdmi_audio_disable(struct stream_encoder * enc)1543*b843c749SSergey Zigachev void dce110_se_hdmi_audio_disable(
1544*b843c749SSergey Zigachev struct stream_encoder *enc)
1545*b843c749SSergey Zigachev {
1546*b843c749SSergey Zigachev dce110_se_enable_audio_clock(enc, false);
1547*b843c749SSergey Zigachev }
1548*b843c749SSergey Zigachev
1549*b843c749SSergey Zigachev
setup_stereo_sync(struct stream_encoder * enc,int tg_inst,bool enable)1550*b843c749SSergey Zigachev static void setup_stereo_sync(
1551*b843c749SSergey Zigachev struct stream_encoder *enc,
1552*b843c749SSergey Zigachev int tg_inst, bool enable)
1553*b843c749SSergey Zigachev {
1554*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
1555*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst);
1556*b843c749SSergey Zigachev REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable);
1557*b843c749SSergey Zigachev }
1558*b843c749SSergey Zigachev
1559*b843c749SSergey Zigachev
1560*b843c749SSergey Zigachev static const struct stream_encoder_funcs dce110_str_enc_funcs = {
1561*b843c749SSergey Zigachev .dp_set_stream_attribute =
1562*b843c749SSergey Zigachev dce110_stream_encoder_dp_set_stream_attribute,
1563*b843c749SSergey Zigachev .hdmi_set_stream_attribute =
1564*b843c749SSergey Zigachev dce110_stream_encoder_hdmi_set_stream_attribute,
1565*b843c749SSergey Zigachev .dvi_set_stream_attribute =
1566*b843c749SSergey Zigachev dce110_stream_encoder_dvi_set_stream_attribute,
1567*b843c749SSergey Zigachev .set_mst_bandwidth =
1568*b843c749SSergey Zigachev dce110_stream_encoder_set_mst_bandwidth,
1569*b843c749SSergey Zigachev .update_hdmi_info_packets =
1570*b843c749SSergey Zigachev dce110_stream_encoder_update_hdmi_info_packets,
1571*b843c749SSergey Zigachev .stop_hdmi_info_packets =
1572*b843c749SSergey Zigachev dce110_stream_encoder_stop_hdmi_info_packets,
1573*b843c749SSergey Zigachev .update_dp_info_packets =
1574*b843c749SSergey Zigachev dce110_stream_encoder_update_dp_info_packets,
1575*b843c749SSergey Zigachev .stop_dp_info_packets =
1576*b843c749SSergey Zigachev dce110_stream_encoder_stop_dp_info_packets,
1577*b843c749SSergey Zigachev .dp_blank =
1578*b843c749SSergey Zigachev dce110_stream_encoder_dp_blank,
1579*b843c749SSergey Zigachev .dp_unblank =
1580*b843c749SSergey Zigachev dce110_stream_encoder_dp_unblank,
1581*b843c749SSergey Zigachev .audio_mute_control = dce110_se_audio_mute_control,
1582*b843c749SSergey Zigachev
1583*b843c749SSergey Zigachev .dp_audio_setup = dce110_se_dp_audio_setup,
1584*b843c749SSergey Zigachev .dp_audio_enable = dce110_se_dp_audio_enable,
1585*b843c749SSergey Zigachev .dp_audio_disable = dce110_se_dp_audio_disable,
1586*b843c749SSergey Zigachev
1587*b843c749SSergey Zigachev .hdmi_audio_setup = dce110_se_hdmi_audio_setup,
1588*b843c749SSergey Zigachev .hdmi_audio_disable = dce110_se_hdmi_audio_disable,
1589*b843c749SSergey Zigachev .setup_stereo_sync = setup_stereo_sync,
1590*b843c749SSergey Zigachev .set_avmute = dce110_stream_encoder_set_avmute,
1591*b843c749SSergey Zigachev
1592*b843c749SSergey Zigachev };
1593*b843c749SSergey Zigachev
dce110_stream_encoder_construct(struct dce110_stream_encoder * enc110,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,const struct dce110_stream_enc_registers * regs,const struct dce_stream_encoder_shift * se_shift,const struct dce_stream_encoder_mask * se_mask)1594*b843c749SSergey Zigachev void dce110_stream_encoder_construct(
1595*b843c749SSergey Zigachev struct dce110_stream_encoder *enc110,
1596*b843c749SSergey Zigachev struct dc_context *ctx,
1597*b843c749SSergey Zigachev struct dc_bios *bp,
1598*b843c749SSergey Zigachev enum engine_id eng_id,
1599*b843c749SSergey Zigachev const struct dce110_stream_enc_registers *regs,
1600*b843c749SSergey Zigachev const struct dce_stream_encoder_shift *se_shift,
1601*b843c749SSergey Zigachev const struct dce_stream_encoder_mask *se_mask)
1602*b843c749SSergey Zigachev {
1603*b843c749SSergey Zigachev enc110->base.funcs = &dce110_str_enc_funcs;
1604*b843c749SSergey Zigachev enc110->base.ctx = ctx;
1605*b843c749SSergey Zigachev enc110->base.id = eng_id;
1606*b843c749SSergey Zigachev enc110->base.bp = bp;
1607*b843c749SSergey Zigachev enc110->regs = regs;
1608*b843c749SSergey Zigachev enc110->se_shift = se_shift;
1609*b843c749SSergey Zigachev enc110->se_mask = se_mask;
1610*b843c749SSergey Zigachev }
1611