1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "dce/dce_11_0_d.h" 29 #include "dce/dce_11_0_sh_mask.h" 30 #include "gmc/gmc_8_2_sh_mask.h" 31 #include "gmc/gmc_8_2_d.h" 32 33 #include "include/logger_interface.h" 34 35 #include "dce110_compressor.h" 36 37 #define DC_LOGGER \ 38 cp110->base.ctx->logger 39 #define DCP_REG(reg)\ 40 (reg + cp110->offsets.dcp_offset) 41 #define DMIF_REG(reg)\ 42 (reg + cp110->offsets.dmif_offset) 43 44 static const struct dce110_compressor_reg_offsets reg_offsets[] = { 45 { 46 .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 47 .dmif_offset = 48 (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 49 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 50 }, 51 { 52 .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 53 .dmif_offset = 54 (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 55 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 56 }, 57 { 58 .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL), 59 .dmif_offset = 60 (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 61 - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL), 62 } 63 }; 64 65 #if 0 66 static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600; 67 #endif 68 69 enum fbc_idle_force { 70 /* Bit 0 - Display registers updated */ 71 FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001, 72 73 /* Bit 2 - FBC_GRPH_COMP_EN register updated */ 74 FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002, 75 /* Bit 3 - FBC_SRC_SEL register updated */ 76 FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004, 77 /* Bit 4 - FBC_MIN_COMPRESSION register updated */ 78 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008, 79 /* Bit 5 - FBC_ALPHA_COMP_EN register updated */ 80 FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010, 81 /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */ 82 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020, 83 /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */ 84 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040, 85 86 /* Bit 24 - Memory write to region 0 defined by MC registers. */ 87 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000, 88 /* Bit 25 - Memory write to region 1 defined by MC registers */ 89 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000, 90 /* Bit 26 - Memory write to region 2 defined by MC registers */ 91 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000, 92 /* Bit 27 - Memory write to region 3 defined by MC registers. */ 93 FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000, 94 95 /* Bit 28 - Memory write from any client other than MCIF */ 96 FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000, 97 /* Bit 29 - CG statics screen signal is inactive */ 98 FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000, 99 }; 100 101 102 static uint32_t align_to_chunks_number_per_line(uint32_t pixels) 103 { 104 return 256 * ((pixels + 255) / 256); 105 } 106 107 static void reset_lb_on_vblank(struct dc_context *ctx) 108 { 109 uint32_t value, frame_count; 110 uint32_t retry = 0; 111 uint32_t status_pos = 112 dm_read_reg(ctx, mmCRTC_STATUS_POSITION); 113 114 115 /* Only if CRTC is enabled and counter is moving we wait for one frame. */ 116 if (status_pos != dm_read_reg(ctx, mmCRTC_STATUS_POSITION)) { 117 /* Resetting LB on VBlank */ 118 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL); 119 set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); 120 set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); 121 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); 122 123 frame_count = dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT); 124 125 126 for (retry = 10000; retry > 0; retry--) { 127 if (frame_count != dm_read_reg(ctx, mmCRTC_STATUS_FRAME_COUNT)) 128 break; 129 udelay(10); 130 } 131 if (!retry) 132 dm_error("Frame count did not increase for 100ms.\n"); 133 134 /* Resetting LB on VBlank */ 135 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL); 136 set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); 137 set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); 138 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); 139 140 } 141 142 } 143 144 static void wait_for_fbc_state_changed( 145 struct dce110_compressor *cp110, 146 bool enabled) 147 { 148 uint32_t counter = 0; 149 uint32_t addr = mmFBC_STATUS; 150 uint32_t value; 151 152 while (counter < 1000) { 153 value = dm_read_reg(cp110->base.ctx, addr); 154 if (get_reg_field_value( 155 value, 156 FBC_STATUS, 157 FBC_ENABLE_STATUS) == enabled) 158 break; 159 udelay(100); 160 counter++; 161 } 162 163 if (counter == 1000) { 164 DC_LOG_WARNING("%s: wait counter exceeded, changes to HW not applied", 165 __func__); 166 } else { 167 DC_LOG_SYNC("FBC status changed to %d", enabled); 168 } 169 170 171 } 172 173 void dce110_compressor_power_up_fbc(struct compressor *compressor) 174 { 175 uint32_t value; 176 uint32_t addr; 177 178 addr = mmFBC_CNTL; 179 value = dm_read_reg(compressor->ctx, addr); 180 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 181 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); 182 set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); 183 if (compressor->options.bits.CLK_GATING_DISABLED == 1) { 184 /* HW needs to do power measurement comparison. */ 185 set_reg_field_value( 186 value, 187 0, 188 FBC_CNTL, 189 FBC_COMP_CLK_GATE_EN); 190 } 191 dm_write_reg(compressor->ctx, addr, value); 192 193 addr = mmFBC_COMP_MODE; 194 value = dm_read_reg(compressor->ctx, addr); 195 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); 196 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN); 197 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN); 198 dm_write_reg(compressor->ctx, addr, value); 199 200 addr = mmFBC_COMP_CNTL; 201 value = dm_read_reg(compressor->ctx, addr); 202 set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN); 203 dm_write_reg(compressor->ctx, addr, value); 204 /*FBC_MIN_COMPRESSION 0 ==> 2:1 */ 205 /* 1 ==> 4:1 */ 206 /* 2 ==> 8:1 */ 207 /* 0xF ==> 1:1 */ 208 set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION); 209 dm_write_reg(compressor->ctx, addr, value); 210 compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1; 211 212 value = 0; 213 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); 214 215 value = 0xFFFFFF; 216 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); 217 } 218 219 void dce110_compressor_enable_fbc( 220 struct compressor *compressor, 221 struct compr_addr_and_pitch_params *params) 222 { 223 struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); 224 225 if (compressor->options.bits.FBC_SUPPORT && 226 (!dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL))) { 227 228 uint32_t addr; 229 uint32_t value, misc_value; 230 231 232 addr = mmFBC_CNTL; 233 value = dm_read_reg(compressor->ctx, addr); 234 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 235 set_reg_field_value( 236 value, 237 params->inst, 238 FBC_CNTL, FBC_SRC_SEL); 239 dm_write_reg(compressor->ctx, addr, value); 240 241 /* Keep track of enum controller_id FBC is attached to */ 242 compressor->is_enabled = true; 243 compressor->attached_inst = params->inst; 244 cp110->offsets = reg_offsets[params->inst]; 245 246 /* Toggle it as there is bug in HW */ 247 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 248 dm_write_reg(compressor->ctx, addr, value); 249 250 /* FBC usage with scatter & gather for dce110 */ 251 misc_value = dm_read_reg(compressor->ctx, mmFBC_MISC); 252 253 set_reg_field_value(misc_value, 1, 254 FBC_MISC, FBC_INVALIDATE_ON_ERROR); 255 set_reg_field_value(misc_value, 1, 256 FBC_MISC, FBC_DECOMPRESS_ERROR_CLEAR); 257 set_reg_field_value(misc_value, 0x14, 258 FBC_MISC, FBC_SLOW_REQ_INTERVAL); 259 260 dm_write_reg(compressor->ctx, mmFBC_MISC, misc_value); 261 262 /* Enable FBC */ 263 set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN); 264 dm_write_reg(compressor->ctx, addr, value); 265 266 wait_for_fbc_state_changed(cp110, true); 267 } 268 } 269 270 void dce110_compressor_disable_fbc(struct compressor *compressor) 271 { 272 struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); 273 274 if (compressor->options.bits.FBC_SUPPORT) { 275 if (dce110_compressor_is_fbc_enabled_in_hw(compressor, NULL)) { 276 uint32_t reg_data; 277 /* Turn off compression */ 278 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); 279 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 280 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data); 281 282 /* Reset enum controller_id to undefined */ 283 compressor->attached_inst = 0; 284 compressor->is_enabled = false; 285 286 wait_for_fbc_state_changed(cp110, false); 287 } 288 289 /* Sync line buffer - dce100/110 only*/ 290 reset_lb_on_vblank(compressor->ctx); 291 } 292 } 293 294 bool dce110_compressor_is_fbc_enabled_in_hw( 295 struct compressor *compressor, 296 uint32_t *inst) 297 { 298 /* Check the hardware register */ 299 uint32_t value; 300 301 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); 302 if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) { 303 if (inst != NULL) 304 *inst = compressor->attached_inst; 305 return true; 306 } 307 308 value = dm_read_reg(compressor->ctx, mmFBC_MISC); 309 if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) { 310 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); 311 312 if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) { 313 if (inst != NULL) 314 *inst = 315 compressor->attached_inst; 316 return true; 317 } 318 } 319 return false; 320 } 321 322 323 void dce110_compressor_program_compressed_surface_address_and_pitch( 324 struct compressor *compressor, 325 struct compr_addr_and_pitch_params *params) 326 { 327 struct dce110_compressor *cp110 = TO_DCE110_COMPRESSOR(compressor); 328 uint32_t value = 0; 329 uint32_t fbc_pitch = 0; 330 uint32_t compressed_surf_address_low_part = 331 compressor->compr_surface_address.addr.low_part; 332 333 /* Clear content first. */ 334 dm_write_reg( 335 compressor->ctx, 336 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 337 0); 338 dm_write_reg(compressor->ctx, 339 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0); 340 341 /* Write address, HIGH has to be first. */ 342 dm_write_reg(compressor->ctx, 343 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH), 344 compressor->compr_surface_address.addr.high_part); 345 dm_write_reg(compressor->ctx, 346 DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 347 compressed_surf_address_low_part); 348 349 fbc_pitch = align_to_chunks_number_per_line(params->source_view_width); 350 351 if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1) 352 fbc_pitch = fbc_pitch / 8; 353 else 354 DC_LOG_WARNING("%s: Unexpected DCE11 compression ratio", 355 __func__); 356 357 /* Clear content first. */ 358 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0); 359 360 /* Write FBC Pitch. */ 361 set_reg_field_value( 362 value, 363 fbc_pitch, 364 GRPH_COMPRESS_PITCH, 365 GRPH_COMPRESS_PITCH); 366 dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value); 367 368 } 369 370 void dce110_compressor_set_fbc_invalidation_triggers( 371 struct compressor *compressor, 372 uint32_t fbc_trigger) 373 { 374 /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19) 375 * for DCE 11 regions cannot be used - does not work with S/G 376 */ 377 uint32_t addr = mmFBC_CLIENT_REGION_MASK; 378 uint32_t value = dm_read_reg(compressor->ctx, addr); 379 380 set_reg_field_value( 381 value, 382 0, 383 FBC_CLIENT_REGION_MASK, 384 FBC_MEMORY_REGION_MASK); 385 dm_write_reg(compressor->ctx, addr, value); 386 387 /* Setup events when to clear all CSM entries (effectively marking 388 * current compressed data invalid) 389 * For DCE 11 CSM metadata 11111 means - "Not Compressed" 390 * Used as the initial value of the metadata sent to the compressor 391 * after invalidation, to indicate that the compressor should attempt 392 * to compress all chunks on the current pass. Also used when the chunk 393 * is not successfully written to memory. 394 * When this CSM value is detected, FBC reads from the uncompressed 395 * buffer. Set events according to passed in value, these events are 396 * valid for DCE11: 397 * - bit 0 - display register updated 398 * - bit 28 - memory write from any client except from MCIF 399 * - bit 29 - CG static screen signal is inactive 400 * In addition, DCE11.1 also needs to set new DCE11.1 specific events 401 * that are used to trigger invalidation on certain register changes, 402 * for example enabling of Alpha Compression may trigger invalidation of 403 * FBC once bit is set. These events are as follows: 404 * - Bit 2 - FBC_GRPH_COMP_EN register updated 405 * - Bit 3 - FBC_SRC_SEL register updated 406 * - Bit 4 - FBC_MIN_COMPRESSION register updated 407 * - Bit 5 - FBC_ALPHA_COMP_EN register updated 408 * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated 409 * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated 410 */ 411 addr = mmFBC_IDLE_FORCE_CLEAR_MASK; 412 value = dm_read_reg(compressor->ctx, addr); 413 set_reg_field_value( 414 value, 415 fbc_trigger | 416 FBC_IDLE_FORCE_GRPH_COMP_EN | 417 FBC_IDLE_FORCE_SRC_SEL_CHANGE | 418 FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE | 419 FBC_IDLE_FORCE_ALPHA_COMP_EN | 420 FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN | 421 FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF, 422 FBC_IDLE_FORCE_CLEAR_MASK, 423 FBC_IDLE_FORCE_CLEAR_MASK); 424 dm_write_reg(compressor->ctx, addr, value); 425 } 426 427 struct compressor *dce110_compressor_create(struct dc_context *ctx) 428 { 429 struct dce110_compressor *cp110 = 430 kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL); 431 432 if (!cp110) 433 return NULL; 434 435 dce110_compressor_construct(cp110, ctx); 436 return &cp110->base; 437 } 438 439 void dce110_compressor_destroy(struct compressor **compressor) 440 { 441 kfree(TO_DCE110_COMPRESSOR(*compressor)); 442 *compressor = NULL; 443 } 444 445 #if 0 446 bool dce110_get_required_compressed_surfacesize(struct fbc_input_info fbc_input_info, 447 struct fbc_requested_compressed_size size) 448 { 449 bool result = false; 450 451 unsigned int max_x = FBC_MAX_X, max_y = FBC_MAX_Y; 452 453 get_max_support_fbc_buffersize(&max_x, &max_y); 454 455 if (fbc_input_info.dynamic_fbc_buffer_alloc == 0) { 456 /* 457 * For DCE11 here use Max HW supported size: HW Support up to 3840x2400 resolution 458 * or 18000 chunks. 459 */ 460 size.preferred_size = size.min_size = align_to_chunks_number_per_line(max_x) * max_y * 4; /* (For FBC when LPT not supported). */ 461 size.preferred_size_alignment = size.min_size_alignment = 0x100; /* For FBC when LPT not supported */ 462 size.bits.preferred_must_be_framebuffer_pool = 1; 463 size.bits.min_must_be_framebuffer_pool = 1; 464 465 result = true; 466 } 467 /* 468 * Maybe to add registry key support with optional size here to override above 469 * for debugging purposes 470 */ 471 472 return result; 473 } 474 #endif 475 476 void get_max_support_fbc_buffersize(unsigned int *max_x, unsigned int *max_y) 477 { 478 *max_x = FBC_MAX_X; 479 *max_y = FBC_MAX_Y; 480 481 /* if (m_smallLocalFrameBufferMemory == 1) 482 * { 483 * *max_x = FBC_MAX_X_SG; 484 * *max_y = FBC_MAX_Y_SG; 485 * } 486 */ 487 } 488 489 490 #if 0 491 unsigned int controller_id_to_index(enum controller_id controller_id) 492 { 493 unsigned int index = 0; 494 495 switch (controller_id) { 496 case CONTROLLER_ID_D0: 497 index = 0; 498 break; 499 case CONTROLLER_ID_D1: 500 index = 1; 501 break; 502 case CONTROLLER_ID_D2: 503 index = 2; 504 break; 505 case CONTROLLER_ID_D3: 506 index = 3; 507 break; 508 default: 509 break; 510 } 511 return index; 512 } 513 #endif 514 515 516 static const struct compressor_funcs dce110_compressor_funcs = { 517 .power_up_fbc = dce110_compressor_power_up_fbc, 518 .enable_fbc = dce110_compressor_enable_fbc, 519 .disable_fbc = dce110_compressor_disable_fbc, 520 .set_fbc_invalidation_triggers = dce110_compressor_set_fbc_invalidation_triggers, 521 .surface_address_and_pitch = dce110_compressor_program_compressed_surface_address_and_pitch, 522 .is_fbc_enabled_in_hw = dce110_compressor_is_fbc_enabled_in_hw 523 }; 524 525 526 void dce110_compressor_construct(struct dce110_compressor *compressor, 527 struct dc_context *ctx) 528 { 529 530 compressor->base.options.raw = 0; 531 compressor->base.options.bits.FBC_SUPPORT = true; 532 533 /* for dce 11 always use one dram channel for lpt */ 534 compressor->base.lpt_channels_num = 1; 535 compressor->base.options.bits.DUMMY_BACKEND = false; 536 537 /* 538 * check if this system has more than 1 dram channel; if only 1 then lpt 539 * should not be supported 540 */ 541 542 543 compressor->base.options.bits.CLK_GATING_DISABLED = false; 544 545 compressor->base.ctx = ctx; 546 compressor->base.embedded_panel_h_size = 0; 547 compressor->base.embedded_panel_v_size = 0; 548 compressor->base.memory_bus_width = ctx->asic_id.vram_width; 549 compressor->base.allocated_size = 0; 550 compressor->base.preferred_requested_size = 0; 551 compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID; 552 compressor->base.banks_num = 0; 553 compressor->base.raw_size = 0; 554 compressor->base.channel_interleave_size = 0; 555 compressor->base.dram_channels_num = 0; 556 compressor->base.lpt_channels_num = 0; 557 compressor->base.attached_inst = 0; 558 compressor->base.is_enabled = false; 559 compressor->base.funcs = &dce110_compressor_funcs; 560 561 } 562 563