1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev #include "dce/dce_11_2_d.h"
29*b843c749SSergey Zigachev #include "dce/dce_11_2_sh_mask.h"
30*b843c749SSergey Zigachev #include "gmc/gmc_8_1_sh_mask.h"
31*b843c749SSergey Zigachev #include "gmc/gmc_8_1_d.h"
32*b843c749SSergey Zigachev
33*b843c749SSergey Zigachev #include "include/logger_interface.h"
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev #include "dce112_compressor.h"
36*b843c749SSergey Zigachev #define DC_LOGGER \
37*b843c749SSergey Zigachev cp110->base.ctx->logger
38*b843c749SSergey Zigachev #define DCP_REG(reg)\
39*b843c749SSergey Zigachev (reg + cp110->offsets.dcp_offset)
40*b843c749SSergey Zigachev #define DMIF_REG(reg)\
41*b843c749SSergey Zigachev (reg + cp110->offsets.dmif_offset)
42*b843c749SSergey Zigachev
43*b843c749SSergey Zigachev static const struct dce112_compressor_reg_offsets reg_offsets[] = {
44*b843c749SSergey Zigachev {
45*b843c749SSergey Zigachev .dcp_offset = (mmDCP0_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
46*b843c749SSergey Zigachev .dmif_offset =
47*b843c749SSergey Zigachev (mmDMIF_PG0_DPG_PIPE_DPM_CONTROL
48*b843c749SSergey Zigachev - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
49*b843c749SSergey Zigachev },
50*b843c749SSergey Zigachev {
51*b843c749SSergey Zigachev .dcp_offset = (mmDCP1_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
52*b843c749SSergey Zigachev .dmif_offset =
53*b843c749SSergey Zigachev (mmDMIF_PG1_DPG_PIPE_DPM_CONTROL
54*b843c749SSergey Zigachev - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
55*b843c749SSergey Zigachev },
56*b843c749SSergey Zigachev {
57*b843c749SSergey Zigachev .dcp_offset = (mmDCP2_GRPH_CONTROL - mmDCP0_GRPH_CONTROL),
58*b843c749SSergey Zigachev .dmif_offset =
59*b843c749SSergey Zigachev (mmDMIF_PG2_DPG_PIPE_DPM_CONTROL
60*b843c749SSergey Zigachev - mmDMIF_PG0_DPG_PIPE_DPM_CONTROL),
61*b843c749SSergey Zigachev }
62*b843c749SSergey Zigachev };
63*b843c749SSergey Zigachev
64*b843c749SSergey Zigachev static const uint32_t dce11_one_lpt_channel_max_resolution = 2560 * 1600;
65*b843c749SSergey Zigachev
66*b843c749SSergey Zigachev enum fbc_idle_force {
67*b843c749SSergey Zigachev /* Bit 0 - Display registers updated */
68*b843c749SSergey Zigachev FBC_IDLE_FORCE_DISPLAY_REGISTER_UPDATE = 0x00000001,
69*b843c749SSergey Zigachev
70*b843c749SSergey Zigachev /* Bit 2 - FBC_GRPH_COMP_EN register updated */
71*b843c749SSergey Zigachev FBC_IDLE_FORCE_GRPH_COMP_EN = 0x00000002,
72*b843c749SSergey Zigachev /* Bit 3 - FBC_SRC_SEL register updated */
73*b843c749SSergey Zigachev FBC_IDLE_FORCE_SRC_SEL_CHANGE = 0x00000004,
74*b843c749SSergey Zigachev /* Bit 4 - FBC_MIN_COMPRESSION register updated */
75*b843c749SSergey Zigachev FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE = 0x00000008,
76*b843c749SSergey Zigachev /* Bit 5 - FBC_ALPHA_COMP_EN register updated */
77*b843c749SSergey Zigachev FBC_IDLE_FORCE_ALPHA_COMP_EN = 0x00000010,
78*b843c749SSergey Zigachev /* Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated */
79*b843c749SSergey Zigachev FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN = 0x00000020,
80*b843c749SSergey Zigachev /* Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated */
81*b843c749SSergey Zigachev FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF = 0x00000040,
82*b843c749SSergey Zigachev
83*b843c749SSergey Zigachev /* Bit 24 - Memory write to region 0 defined by MC registers. */
84*b843c749SSergey Zigachev FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION0 = 0x01000000,
85*b843c749SSergey Zigachev /* Bit 25 - Memory write to region 1 defined by MC registers */
86*b843c749SSergey Zigachev FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION1 = 0x02000000,
87*b843c749SSergey Zigachev /* Bit 26 - Memory write to region 2 defined by MC registers */
88*b843c749SSergey Zigachev FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION2 = 0x04000000,
89*b843c749SSergey Zigachev /* Bit 27 - Memory write to region 3 defined by MC registers. */
90*b843c749SSergey Zigachev FBC_IDLE_FORCE_MEMORY_WRITE_TO_REGION3 = 0x08000000,
91*b843c749SSergey Zigachev
92*b843c749SSergey Zigachev /* Bit 28 - Memory write from any client other than MCIF */
93*b843c749SSergey Zigachev FBC_IDLE_FORCE_MEMORY_WRITE_OTHER_THAN_MCIF = 0x10000000,
94*b843c749SSergey Zigachev /* Bit 29 - CG statics screen signal is inactive */
95*b843c749SSergey Zigachev FBC_IDLE_FORCE_CG_STATIC_SCREEN_IS_INACTIVE = 0x20000000,
96*b843c749SSergey Zigachev };
97*b843c749SSergey Zigachev
lpt_size_alignment(struct dce112_compressor * cp110)98*b843c749SSergey Zigachev static uint32_t lpt_size_alignment(struct dce112_compressor *cp110)
99*b843c749SSergey Zigachev {
100*b843c749SSergey Zigachev /*LPT_ALIGNMENT (in bytes) = ROW_SIZE * #BANKS * # DRAM CHANNELS. */
101*b843c749SSergey Zigachev return cp110->base.raw_size * cp110->base.banks_num *
102*b843c749SSergey Zigachev cp110->base.dram_channels_num;
103*b843c749SSergey Zigachev }
104*b843c749SSergey Zigachev
lpt_memory_control_config(struct dce112_compressor * cp110,uint32_t lpt_control)105*b843c749SSergey Zigachev static uint32_t lpt_memory_control_config(struct dce112_compressor *cp110,
106*b843c749SSergey Zigachev uint32_t lpt_control)
107*b843c749SSergey Zigachev {
108*b843c749SSergey Zigachev /*LPT MC Config */
109*b843c749SSergey Zigachev if (cp110->base.options.bits.LPT_MC_CONFIG == 1) {
110*b843c749SSergey Zigachev /* POSSIBLE VALUES for LPT NUM_PIPES (DRAM CHANNELS):
111*b843c749SSergey Zigachev * 00 - 1 CHANNEL
112*b843c749SSergey Zigachev * 01 - 2 CHANNELS
113*b843c749SSergey Zigachev * 02 - 4 OR 6 CHANNELS
114*b843c749SSergey Zigachev * (Only for discrete GPU, N/A for CZ)
115*b843c749SSergey Zigachev * 03 - 8 OR 12 CHANNELS
116*b843c749SSergey Zigachev * (Only for discrete GPU, N/A for CZ) */
117*b843c749SSergey Zigachev switch (cp110->base.dram_channels_num) {
118*b843c749SSergey Zigachev case 2:
119*b843c749SSergey Zigachev set_reg_field_value(
120*b843c749SSergey Zigachev lpt_control,
121*b843c749SSergey Zigachev 1,
122*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
123*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_PIPES);
124*b843c749SSergey Zigachev break;
125*b843c749SSergey Zigachev case 1:
126*b843c749SSergey Zigachev set_reg_field_value(
127*b843c749SSergey Zigachev lpt_control,
128*b843c749SSergey Zigachev 0,
129*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
130*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_PIPES);
131*b843c749SSergey Zigachev break;
132*b843c749SSergey Zigachev default:
133*b843c749SSergey Zigachev DC_LOG_WARNING(
134*b843c749SSergey Zigachev "%s: Invalid LPT NUM_PIPES!!!",
135*b843c749SSergey Zigachev __func__);
136*b843c749SSergey Zigachev break;
137*b843c749SSergey Zigachev }
138*b843c749SSergey Zigachev
139*b843c749SSergey Zigachev /* The mapping for LPT NUM_BANKS is in
140*b843c749SSergey Zigachev * GRPH_CONTROL.GRPH_NUM_BANKS register field
141*b843c749SSergey Zigachev * Specifies the number of memory banks for tiling
142*b843c749SSergey Zigachev * purposes. Only applies to 2D and 3D tiling modes.
143*b843c749SSergey Zigachev * POSSIBLE VALUES:
144*b843c749SSergey Zigachev * 00 - DCP_GRPH_NUM_BANKS_2BANK: ADDR_SURF_2_BANK
145*b843c749SSergey Zigachev * 01 - DCP_GRPH_NUM_BANKS_4BANK: ADDR_SURF_4_BANK
146*b843c749SSergey Zigachev * 02 - DCP_GRPH_NUM_BANKS_8BANK: ADDR_SURF_8_BANK
147*b843c749SSergey Zigachev * 03 - DCP_GRPH_NUM_BANKS_16BANK: ADDR_SURF_16_BANK */
148*b843c749SSergey Zigachev switch (cp110->base.banks_num) {
149*b843c749SSergey Zigachev case 16:
150*b843c749SSergey Zigachev set_reg_field_value(
151*b843c749SSergey Zigachev lpt_control,
152*b843c749SSergey Zigachev 3,
153*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
154*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_BANKS);
155*b843c749SSergey Zigachev break;
156*b843c749SSergey Zigachev case 8:
157*b843c749SSergey Zigachev set_reg_field_value(
158*b843c749SSergey Zigachev lpt_control,
159*b843c749SSergey Zigachev 2,
160*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
161*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_BANKS);
162*b843c749SSergey Zigachev break;
163*b843c749SSergey Zigachev case 4:
164*b843c749SSergey Zigachev set_reg_field_value(
165*b843c749SSergey Zigachev lpt_control,
166*b843c749SSergey Zigachev 1,
167*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
168*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_BANKS);
169*b843c749SSergey Zigachev break;
170*b843c749SSergey Zigachev case 2:
171*b843c749SSergey Zigachev set_reg_field_value(
172*b843c749SSergey Zigachev lpt_control,
173*b843c749SSergey Zigachev 0,
174*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
175*b843c749SSergey Zigachev LOW_POWER_TILING_NUM_BANKS);
176*b843c749SSergey Zigachev break;
177*b843c749SSergey Zigachev default:
178*b843c749SSergey Zigachev DC_LOG_WARNING(
179*b843c749SSergey Zigachev "%s: Invalid LPT NUM_BANKS!!!",
180*b843c749SSergey Zigachev __func__);
181*b843c749SSergey Zigachev break;
182*b843c749SSergey Zigachev }
183*b843c749SSergey Zigachev
184*b843c749SSergey Zigachev /* The mapping is in DMIF_ADDR_CALC.
185*b843c749SSergey Zigachev * ADDR_CONFIG_PIPE_INTERLEAVE_SIZE register field for
186*b843c749SSergey Zigachev * Carrizo specifies the memory interleave per pipe.
187*b843c749SSergey Zigachev * It effectively specifies the location of pipe bits in
188*b843c749SSergey Zigachev * the memory address.
189*b843c749SSergey Zigachev * POSSIBLE VALUES:
190*b843c749SSergey Zigachev * 00 - ADDR_CONFIG_PIPE_INTERLEAVE_256B: 256 byte
191*b843c749SSergey Zigachev * interleave
192*b843c749SSergey Zigachev * 01 - ADDR_CONFIG_PIPE_INTERLEAVE_512B: 512 byte
193*b843c749SSergey Zigachev * interleave
194*b843c749SSergey Zigachev */
195*b843c749SSergey Zigachev switch (cp110->base.channel_interleave_size) {
196*b843c749SSergey Zigachev case 256: /*256B */
197*b843c749SSergey Zigachev set_reg_field_value(
198*b843c749SSergey Zigachev lpt_control,
199*b843c749SSergey Zigachev 0,
200*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
201*b843c749SSergey Zigachev LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
202*b843c749SSergey Zigachev break;
203*b843c749SSergey Zigachev case 512: /*512B */
204*b843c749SSergey Zigachev set_reg_field_value(
205*b843c749SSergey Zigachev lpt_control,
206*b843c749SSergey Zigachev 1,
207*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
208*b843c749SSergey Zigachev LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE);
209*b843c749SSergey Zigachev break;
210*b843c749SSergey Zigachev default:
211*b843c749SSergey Zigachev DC_LOG_WARNING(
212*b843c749SSergey Zigachev "%s: Invalid LPT INTERLEAVE_SIZE!!!",
213*b843c749SSergey Zigachev __func__);
214*b843c749SSergey Zigachev break;
215*b843c749SSergey Zigachev }
216*b843c749SSergey Zigachev
217*b843c749SSergey Zigachev /* The mapping for LOW_POWER_TILING_ROW_SIZE is in
218*b843c749SSergey Zigachev * DMIF_ADDR_CALC.ADDR_CONFIG_ROW_SIZE register field
219*b843c749SSergey Zigachev * for Carrizo. Specifies the size of dram row in bytes.
220*b843c749SSergey Zigachev * This should match up with NOOFCOLS field in
221*b843c749SSergey Zigachev * MC_ARB_RAMCFG (ROW_SIZE = 4 * 2 ^^ columns).
222*b843c749SSergey Zigachev * This register DMIF_ADDR_CALC is not used by the
223*b843c749SSergey Zigachev * hardware as it is only used for addrlib assertions.
224*b843c749SSergey Zigachev * POSSIBLE VALUES:
225*b843c749SSergey Zigachev * 00 - ADDR_CONFIG_1KB_ROW: Treat 1KB as DRAM row
226*b843c749SSergey Zigachev * boundary
227*b843c749SSergey Zigachev * 01 - ADDR_CONFIG_2KB_ROW: Treat 2KB as DRAM row
228*b843c749SSergey Zigachev * boundary
229*b843c749SSergey Zigachev * 02 - ADDR_CONFIG_4KB_ROW: Treat 4KB as DRAM row
230*b843c749SSergey Zigachev * boundary */
231*b843c749SSergey Zigachev switch (cp110->base.raw_size) {
232*b843c749SSergey Zigachev case 4096: /*4 KB */
233*b843c749SSergey Zigachev set_reg_field_value(
234*b843c749SSergey Zigachev lpt_control,
235*b843c749SSergey Zigachev 2,
236*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
237*b843c749SSergey Zigachev LOW_POWER_TILING_ROW_SIZE);
238*b843c749SSergey Zigachev break;
239*b843c749SSergey Zigachev case 2048:
240*b843c749SSergey Zigachev set_reg_field_value(
241*b843c749SSergey Zigachev lpt_control,
242*b843c749SSergey Zigachev 1,
243*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
244*b843c749SSergey Zigachev LOW_POWER_TILING_ROW_SIZE);
245*b843c749SSergey Zigachev break;
246*b843c749SSergey Zigachev case 1024:
247*b843c749SSergey Zigachev set_reg_field_value(
248*b843c749SSergey Zigachev lpt_control,
249*b843c749SSergey Zigachev 0,
250*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
251*b843c749SSergey Zigachev LOW_POWER_TILING_ROW_SIZE);
252*b843c749SSergey Zigachev break;
253*b843c749SSergey Zigachev default:
254*b843c749SSergey Zigachev DC_LOG_WARNING(
255*b843c749SSergey Zigachev "%s: Invalid LPT ROW_SIZE!!!",
256*b843c749SSergey Zigachev __func__);
257*b843c749SSergey Zigachev break;
258*b843c749SSergey Zigachev }
259*b843c749SSergey Zigachev } else {
260*b843c749SSergey Zigachev DC_LOG_WARNING(
261*b843c749SSergey Zigachev "%s: LPT MC Configuration is not provided",
262*b843c749SSergey Zigachev __func__);
263*b843c749SSergey Zigachev }
264*b843c749SSergey Zigachev
265*b843c749SSergey Zigachev return lpt_control;
266*b843c749SSergey Zigachev }
267*b843c749SSergey Zigachev
is_source_bigger_than_epanel_size(struct dce112_compressor * cp110,uint32_t source_view_width,uint32_t source_view_height)268*b843c749SSergey Zigachev static bool is_source_bigger_than_epanel_size(
269*b843c749SSergey Zigachev struct dce112_compressor *cp110,
270*b843c749SSergey Zigachev uint32_t source_view_width,
271*b843c749SSergey Zigachev uint32_t source_view_height)
272*b843c749SSergey Zigachev {
273*b843c749SSergey Zigachev if (cp110->base.embedded_panel_h_size != 0 &&
274*b843c749SSergey Zigachev cp110->base.embedded_panel_v_size != 0 &&
275*b843c749SSergey Zigachev ((source_view_width * source_view_height) >
276*b843c749SSergey Zigachev (cp110->base.embedded_panel_h_size *
277*b843c749SSergey Zigachev cp110->base.embedded_panel_v_size)))
278*b843c749SSergey Zigachev return true;
279*b843c749SSergey Zigachev
280*b843c749SSergey Zigachev return false;
281*b843c749SSergey Zigachev }
282*b843c749SSergey Zigachev
align_to_chunks_number_per_line(struct dce112_compressor * cp110,uint32_t pixels)283*b843c749SSergey Zigachev static uint32_t align_to_chunks_number_per_line(
284*b843c749SSergey Zigachev struct dce112_compressor *cp110,
285*b843c749SSergey Zigachev uint32_t pixels)
286*b843c749SSergey Zigachev {
287*b843c749SSergey Zigachev return 256 * ((pixels + 255) / 256);
288*b843c749SSergey Zigachev }
289*b843c749SSergey Zigachev
wait_for_fbc_state_changed(struct dce112_compressor * cp110,bool enabled)290*b843c749SSergey Zigachev static void wait_for_fbc_state_changed(
291*b843c749SSergey Zigachev struct dce112_compressor *cp110,
292*b843c749SSergey Zigachev bool enabled)
293*b843c749SSergey Zigachev {
294*b843c749SSergey Zigachev uint8_t counter = 0;
295*b843c749SSergey Zigachev uint32_t addr = mmFBC_STATUS;
296*b843c749SSergey Zigachev uint32_t value;
297*b843c749SSergey Zigachev
298*b843c749SSergey Zigachev while (counter < 10) {
299*b843c749SSergey Zigachev value = dm_read_reg(cp110->base.ctx, addr);
300*b843c749SSergey Zigachev if (get_reg_field_value(
301*b843c749SSergey Zigachev value,
302*b843c749SSergey Zigachev FBC_STATUS,
303*b843c749SSergey Zigachev FBC_ENABLE_STATUS) == enabled)
304*b843c749SSergey Zigachev break;
305*b843c749SSergey Zigachev udelay(10);
306*b843c749SSergey Zigachev counter++;
307*b843c749SSergey Zigachev }
308*b843c749SSergey Zigachev
309*b843c749SSergey Zigachev if (counter == 10) {
310*b843c749SSergey Zigachev DC_LOG_WARNING(
311*b843c749SSergey Zigachev "%s: wait counter exceeded, changes to HW not applied",
312*b843c749SSergey Zigachev __func__);
313*b843c749SSergey Zigachev }
314*b843c749SSergey Zigachev }
315*b843c749SSergey Zigachev
dce112_compressor_power_up_fbc(struct compressor * compressor)316*b843c749SSergey Zigachev void dce112_compressor_power_up_fbc(struct compressor *compressor)
317*b843c749SSergey Zigachev {
318*b843c749SSergey Zigachev uint32_t value;
319*b843c749SSergey Zigachev uint32_t addr;
320*b843c749SSergey Zigachev
321*b843c749SSergey Zigachev addr = mmFBC_CNTL;
322*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
323*b843c749SSergey Zigachev set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
324*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_CNTL, FBC_EN);
325*b843c749SSergey Zigachev set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE);
326*b843c749SSergey Zigachev if (compressor->options.bits.CLK_GATING_DISABLED == 1) {
327*b843c749SSergey Zigachev /* HW needs to do power measurement comparison. */
328*b843c749SSergey Zigachev set_reg_field_value(
329*b843c749SSergey Zigachev value,
330*b843c749SSergey Zigachev 0,
331*b843c749SSergey Zigachev FBC_CNTL,
332*b843c749SSergey Zigachev FBC_COMP_CLK_GATE_EN);
333*b843c749SSergey Zigachev }
334*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
335*b843c749SSergey Zigachev
336*b843c749SSergey Zigachev addr = mmFBC_COMP_MODE;
337*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
338*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN);
339*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_DPCM4_RGB_EN);
340*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_IND_EN);
341*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
342*b843c749SSergey Zigachev
343*b843c749SSergey Zigachev addr = mmFBC_COMP_CNTL;
344*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
345*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_COMP_CNTL, FBC_DEPTH_RGB08_EN);
346*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
347*b843c749SSergey Zigachev /*FBC_MIN_COMPRESSION 0 ==> 2:1 */
348*b843c749SSergey Zigachev /* 1 ==> 4:1 */
349*b843c749SSergey Zigachev /* 2 ==> 8:1 */
350*b843c749SSergey Zigachev /* 0xF ==> 1:1 */
351*b843c749SSergey Zigachev set_reg_field_value(value, 0xF, FBC_COMP_CNTL, FBC_MIN_COMPRESSION);
352*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
353*b843c749SSergey Zigachev compressor->min_compress_ratio = FBC_COMPRESS_RATIO_1TO1;
354*b843c749SSergey Zigachev
355*b843c749SSergey Zigachev value = 0;
356*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value);
357*b843c749SSergey Zigachev
358*b843c749SSergey Zigachev value = 0xFFFFFF;
359*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value);
360*b843c749SSergey Zigachev }
361*b843c749SSergey Zigachev
dce112_compressor_enable_fbc(struct compressor * compressor,uint32_t paths_num,struct compr_addr_and_pitch_params * params)362*b843c749SSergey Zigachev void dce112_compressor_enable_fbc(
363*b843c749SSergey Zigachev struct compressor *compressor,
364*b843c749SSergey Zigachev uint32_t paths_num,
365*b843c749SSergey Zigachev struct compr_addr_and_pitch_params *params)
366*b843c749SSergey Zigachev {
367*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
368*b843c749SSergey Zigachev
369*b843c749SSergey Zigachev if (compressor->options.bits.FBC_SUPPORT &&
370*b843c749SSergey Zigachev (compressor->options.bits.DUMMY_BACKEND == 0) &&
371*b843c749SSergey Zigachev (!dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) &&
372*b843c749SSergey Zigachev (!is_source_bigger_than_epanel_size(
373*b843c749SSergey Zigachev cp110,
374*b843c749SSergey Zigachev params->source_view_width,
375*b843c749SSergey Zigachev params->source_view_height))) {
376*b843c749SSergey Zigachev
377*b843c749SSergey Zigachev uint32_t addr;
378*b843c749SSergey Zigachev uint32_t value;
379*b843c749SSergey Zigachev
380*b843c749SSergey Zigachev /* Before enabling FBC first need to enable LPT if applicable
381*b843c749SSergey Zigachev * LPT state should always be changed (enable/disable) while FBC
382*b843c749SSergey Zigachev * is disabled */
383*b843c749SSergey Zigachev if (compressor->options.bits.LPT_SUPPORT && (paths_num < 2) &&
384*b843c749SSergey Zigachev (params->source_view_width *
385*b843c749SSergey Zigachev params->source_view_height <=
386*b843c749SSergey Zigachev dce11_one_lpt_channel_max_resolution)) {
387*b843c749SSergey Zigachev dce112_compressor_enable_lpt(compressor);
388*b843c749SSergey Zigachev }
389*b843c749SSergey Zigachev
390*b843c749SSergey Zigachev addr = mmFBC_CNTL;
391*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
392*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
393*b843c749SSergey Zigachev set_reg_field_value(
394*b843c749SSergey Zigachev value,
395*b843c749SSergey Zigachev params->inst,
396*b843c749SSergey Zigachev FBC_CNTL, FBC_SRC_SEL);
397*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
398*b843c749SSergey Zigachev
399*b843c749SSergey Zigachev /* Keep track of enum controller_id FBC is attached to */
400*b843c749SSergey Zigachev compressor->is_enabled = true;
401*b843c749SSergey Zigachev compressor->attached_inst = params->inst;
402*b843c749SSergey Zigachev cp110->offsets = reg_offsets[params->inst];
403*b843c749SSergey Zigachev
404*b843c749SSergey Zigachev /*Toggle it as there is bug in HW */
405*b843c749SSergey Zigachev set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
406*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
407*b843c749SSergey Zigachev set_reg_field_value(value, 1, FBC_CNTL, FBC_GRPH_COMP_EN);
408*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
409*b843c749SSergey Zigachev
410*b843c749SSergey Zigachev wait_for_fbc_state_changed(cp110, true);
411*b843c749SSergey Zigachev }
412*b843c749SSergey Zigachev }
413*b843c749SSergey Zigachev
dce112_compressor_disable_fbc(struct compressor * compressor)414*b843c749SSergey Zigachev void dce112_compressor_disable_fbc(struct compressor *compressor)
415*b843c749SSergey Zigachev {
416*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
417*b843c749SSergey Zigachev
418*b843c749SSergey Zigachev if (compressor->options.bits.FBC_SUPPORT &&
419*b843c749SSergey Zigachev dce112_compressor_is_fbc_enabled_in_hw(compressor, NULL)) {
420*b843c749SSergey Zigachev uint32_t reg_data;
421*b843c749SSergey Zigachev /* Turn off compression */
422*b843c749SSergey Zigachev reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
423*b843c749SSergey Zigachev set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
424*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
425*b843c749SSergey Zigachev
426*b843c749SSergey Zigachev /* Reset enum controller_id to undefined */
427*b843c749SSergey Zigachev compressor->attached_inst = 0;
428*b843c749SSergey Zigachev compressor->is_enabled = false;
429*b843c749SSergey Zigachev
430*b843c749SSergey Zigachev /* Whenever disabling FBC make sure LPT is disabled if LPT
431*b843c749SSergey Zigachev * supported */
432*b843c749SSergey Zigachev if (compressor->options.bits.LPT_SUPPORT)
433*b843c749SSergey Zigachev dce112_compressor_disable_lpt(compressor);
434*b843c749SSergey Zigachev
435*b843c749SSergey Zigachev wait_for_fbc_state_changed(cp110, false);
436*b843c749SSergey Zigachev }
437*b843c749SSergey Zigachev }
438*b843c749SSergey Zigachev
dce112_compressor_is_fbc_enabled_in_hw(struct compressor * compressor,uint32_t * inst)439*b843c749SSergey Zigachev bool dce112_compressor_is_fbc_enabled_in_hw(
440*b843c749SSergey Zigachev struct compressor *compressor,
441*b843c749SSergey Zigachev uint32_t *inst)
442*b843c749SSergey Zigachev {
443*b843c749SSergey Zigachev /* Check the hardware register */
444*b843c749SSergey Zigachev uint32_t value;
445*b843c749SSergey Zigachev
446*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, mmFBC_STATUS);
447*b843c749SSergey Zigachev if (get_reg_field_value(value, FBC_STATUS, FBC_ENABLE_STATUS)) {
448*b843c749SSergey Zigachev if (inst != NULL)
449*b843c749SSergey Zigachev *inst = compressor->attached_inst;
450*b843c749SSergey Zigachev return true;
451*b843c749SSergey Zigachev }
452*b843c749SSergey Zigachev
453*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, mmFBC_MISC);
454*b843c749SSergey Zigachev if (get_reg_field_value(value, FBC_MISC, FBC_STOP_ON_HFLIP_EVENT)) {
455*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, mmFBC_CNTL);
456*b843c749SSergey Zigachev
457*b843c749SSergey Zigachev if (get_reg_field_value(value, FBC_CNTL, FBC_GRPH_COMP_EN)) {
458*b843c749SSergey Zigachev if (inst != NULL)
459*b843c749SSergey Zigachev *inst =
460*b843c749SSergey Zigachev compressor->attached_inst;
461*b843c749SSergey Zigachev return true;
462*b843c749SSergey Zigachev }
463*b843c749SSergey Zigachev }
464*b843c749SSergey Zigachev return false;
465*b843c749SSergey Zigachev }
466*b843c749SSergey Zigachev
dce112_compressor_is_lpt_enabled_in_hw(struct compressor * compressor)467*b843c749SSergey Zigachev bool dce112_compressor_is_lpt_enabled_in_hw(struct compressor *compressor)
468*b843c749SSergey Zigachev {
469*b843c749SSergey Zigachev /* Check the hardware register */
470*b843c749SSergey Zigachev uint32_t value = dm_read_reg(compressor->ctx,
471*b843c749SSergey Zigachev mmLOW_POWER_TILING_CONTROL);
472*b843c749SSergey Zigachev
473*b843c749SSergey Zigachev return get_reg_field_value(
474*b843c749SSergey Zigachev value,
475*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
476*b843c749SSergey Zigachev LOW_POWER_TILING_ENABLE);
477*b843c749SSergey Zigachev }
478*b843c749SSergey Zigachev
dce112_compressor_program_compressed_surface_address_and_pitch(struct compressor * compressor,struct compr_addr_and_pitch_params * params)479*b843c749SSergey Zigachev void dce112_compressor_program_compressed_surface_address_and_pitch(
480*b843c749SSergey Zigachev struct compressor *compressor,
481*b843c749SSergey Zigachev struct compr_addr_and_pitch_params *params)
482*b843c749SSergey Zigachev {
483*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
484*b843c749SSergey Zigachev uint32_t value = 0;
485*b843c749SSergey Zigachev uint32_t fbc_pitch = 0;
486*b843c749SSergey Zigachev uint32_t compressed_surf_address_low_part =
487*b843c749SSergey Zigachev compressor->compr_surface_address.addr.low_part;
488*b843c749SSergey Zigachev
489*b843c749SSergey Zigachev /* Clear content first. */
490*b843c749SSergey Zigachev dm_write_reg(
491*b843c749SSergey Zigachev compressor->ctx,
492*b843c749SSergey Zigachev DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
493*b843c749SSergey Zigachev 0);
494*b843c749SSergey Zigachev dm_write_reg(compressor->ctx,
495*b843c749SSergey Zigachev DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS), 0);
496*b843c749SSergey Zigachev
497*b843c749SSergey Zigachev if (compressor->options.bits.LPT_SUPPORT) {
498*b843c749SSergey Zigachev uint32_t lpt_alignment = lpt_size_alignment(cp110);
499*b843c749SSergey Zigachev
500*b843c749SSergey Zigachev if (lpt_alignment != 0) {
501*b843c749SSergey Zigachev compressed_surf_address_low_part =
502*b843c749SSergey Zigachev ((compressed_surf_address_low_part
503*b843c749SSergey Zigachev + (lpt_alignment - 1)) / lpt_alignment)
504*b843c749SSergey Zigachev * lpt_alignment;
505*b843c749SSergey Zigachev }
506*b843c749SSergey Zigachev }
507*b843c749SSergey Zigachev
508*b843c749SSergey Zigachev /* Write address, HIGH has to be first. */
509*b843c749SSergey Zigachev dm_write_reg(compressor->ctx,
510*b843c749SSergey Zigachev DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH),
511*b843c749SSergey Zigachev compressor->compr_surface_address.addr.high_part);
512*b843c749SSergey Zigachev dm_write_reg(compressor->ctx,
513*b843c749SSergey Zigachev DCP_REG(mmGRPH_COMPRESS_SURFACE_ADDRESS),
514*b843c749SSergey Zigachev compressed_surf_address_low_part);
515*b843c749SSergey Zigachev
516*b843c749SSergey Zigachev fbc_pitch = align_to_chunks_number_per_line(
517*b843c749SSergey Zigachev cp110,
518*b843c749SSergey Zigachev params->source_view_width);
519*b843c749SSergey Zigachev
520*b843c749SSergey Zigachev if (compressor->min_compress_ratio == FBC_COMPRESS_RATIO_1TO1)
521*b843c749SSergey Zigachev fbc_pitch = fbc_pitch / 8;
522*b843c749SSergey Zigachev else
523*b843c749SSergey Zigachev DC_LOG_WARNING(
524*b843c749SSergey Zigachev "%s: Unexpected DCE11 compression ratio",
525*b843c749SSergey Zigachev __func__);
526*b843c749SSergey Zigachev
527*b843c749SSergey Zigachev /* Clear content first. */
528*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), 0);
529*b843c749SSergey Zigachev
530*b843c749SSergey Zigachev /* Write FBC Pitch. */
531*b843c749SSergey Zigachev set_reg_field_value(
532*b843c749SSergey Zigachev value,
533*b843c749SSergey Zigachev fbc_pitch,
534*b843c749SSergey Zigachev GRPH_COMPRESS_PITCH,
535*b843c749SSergey Zigachev GRPH_COMPRESS_PITCH);
536*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, DCP_REG(mmGRPH_COMPRESS_PITCH), value);
537*b843c749SSergey Zigachev
538*b843c749SSergey Zigachev }
539*b843c749SSergey Zigachev
dce112_compressor_disable_lpt(struct compressor * compressor)540*b843c749SSergey Zigachev void dce112_compressor_disable_lpt(struct compressor *compressor)
541*b843c749SSergey Zigachev {
542*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
543*b843c749SSergey Zigachev uint32_t value;
544*b843c749SSergey Zigachev uint32_t addr;
545*b843c749SSergey Zigachev uint32_t inx;
546*b843c749SSergey Zigachev
547*b843c749SSergey Zigachev /* Disable all pipes LPT Stutter */
548*b843c749SSergey Zigachev for (inx = 0; inx < 3; inx++) {
549*b843c749SSergey Zigachev value =
550*b843c749SSergey Zigachev dm_read_reg(
551*b843c749SSergey Zigachev compressor->ctx,
552*b843c749SSergey Zigachev DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
553*b843c749SSergey Zigachev set_reg_field_value(
554*b843c749SSergey Zigachev value,
555*b843c749SSergey Zigachev 0,
556*b843c749SSergey Zigachev DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
557*b843c749SSergey Zigachev STUTTER_ENABLE_NONLPTCH);
558*b843c749SSergey Zigachev dm_write_reg(
559*b843c749SSergey Zigachev compressor->ctx,
560*b843c749SSergey Zigachev DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH),
561*b843c749SSergey Zigachev value);
562*b843c749SSergey Zigachev }
563*b843c749SSergey Zigachev /* Disable Underlay pipe LPT Stutter */
564*b843c749SSergey Zigachev addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
565*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
566*b843c749SSergey Zigachev set_reg_field_value(
567*b843c749SSergey Zigachev value,
568*b843c749SSergey Zigachev 0,
569*b843c749SSergey Zigachev DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
570*b843c749SSergey Zigachev STUTTER_ENABLE_NONLPTCH);
571*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
572*b843c749SSergey Zigachev
573*b843c749SSergey Zigachev /* Disable LPT */
574*b843c749SSergey Zigachev addr = mmLOW_POWER_TILING_CONTROL;
575*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
576*b843c749SSergey Zigachev set_reg_field_value(
577*b843c749SSergey Zigachev value,
578*b843c749SSergey Zigachev 0,
579*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
580*b843c749SSergey Zigachev LOW_POWER_TILING_ENABLE);
581*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
582*b843c749SSergey Zigachev
583*b843c749SSergey Zigachev /* Clear selection of Channel(s) containing Compressed Surface */
584*b843c749SSergey Zigachev addr = mmGMCON_LPT_TARGET;
585*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
586*b843c749SSergey Zigachev set_reg_field_value(
587*b843c749SSergey Zigachev value,
588*b843c749SSergey Zigachev 0xFFFFFFFF,
589*b843c749SSergey Zigachev GMCON_LPT_TARGET,
590*b843c749SSergey Zigachev STCTRL_LPT_TARGET);
591*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, mmGMCON_LPT_TARGET, value);
592*b843c749SSergey Zigachev }
593*b843c749SSergey Zigachev
dce112_compressor_enable_lpt(struct compressor * compressor)594*b843c749SSergey Zigachev void dce112_compressor_enable_lpt(struct compressor *compressor)
595*b843c749SSergey Zigachev {
596*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
597*b843c749SSergey Zigachev uint32_t value;
598*b843c749SSergey Zigachev uint32_t addr;
599*b843c749SSergey Zigachev uint32_t value_control;
600*b843c749SSergey Zigachev uint32_t channels;
601*b843c749SSergey Zigachev
602*b843c749SSergey Zigachev /* Enable LPT Stutter from Display pipe */
603*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx,
604*b843c749SSergey Zigachev DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH));
605*b843c749SSergey Zigachev set_reg_field_value(
606*b843c749SSergey Zigachev value,
607*b843c749SSergey Zigachev 1,
608*b843c749SSergey Zigachev DPG_PIPE_STUTTER_CONTROL_NONLPTCH,
609*b843c749SSergey Zigachev STUTTER_ENABLE_NONLPTCH);
610*b843c749SSergey Zigachev dm_write_reg(compressor->ctx,
611*b843c749SSergey Zigachev DMIF_REG(mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH), value);
612*b843c749SSergey Zigachev
613*b843c749SSergey Zigachev /* Enable Underlay pipe LPT Stutter */
614*b843c749SSergey Zigachev addr = mmDPGV0_PIPE_STUTTER_CONTROL_NONLPTCH;
615*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
616*b843c749SSergey Zigachev set_reg_field_value(
617*b843c749SSergey Zigachev value,
618*b843c749SSergey Zigachev 1,
619*b843c749SSergey Zigachev DPGV0_PIPE_STUTTER_CONTROL_NONLPTCH,
620*b843c749SSergey Zigachev STUTTER_ENABLE_NONLPTCH);
621*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
622*b843c749SSergey Zigachev
623*b843c749SSergey Zigachev /* Selection of Channel(s) containing Compressed Surface: 0xfffffff
624*b843c749SSergey Zigachev * will disable LPT.
625*b843c749SSergey Zigachev * STCTRL_LPT_TARGETn corresponds to channel n. */
626*b843c749SSergey Zigachev addr = mmLOW_POWER_TILING_CONTROL;
627*b843c749SSergey Zigachev value_control = dm_read_reg(compressor->ctx, addr);
628*b843c749SSergey Zigachev channels = get_reg_field_value(value_control,
629*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
630*b843c749SSergey Zigachev LOW_POWER_TILING_MODE);
631*b843c749SSergey Zigachev
632*b843c749SSergey Zigachev addr = mmGMCON_LPT_TARGET;
633*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
634*b843c749SSergey Zigachev set_reg_field_value(
635*b843c749SSergey Zigachev value,
636*b843c749SSergey Zigachev channels + 1, /* not mentioned in programming guide,
637*b843c749SSergey Zigachev but follow DCE8.1 */
638*b843c749SSergey Zigachev GMCON_LPT_TARGET,
639*b843c749SSergey Zigachev STCTRL_LPT_TARGET);
640*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
641*b843c749SSergey Zigachev
642*b843c749SSergey Zigachev /* Enable LPT */
643*b843c749SSergey Zigachev addr = mmLOW_POWER_TILING_CONTROL;
644*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
645*b843c749SSergey Zigachev set_reg_field_value(
646*b843c749SSergey Zigachev value,
647*b843c749SSergey Zigachev 1,
648*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
649*b843c749SSergey Zigachev LOW_POWER_TILING_ENABLE);
650*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
651*b843c749SSergey Zigachev }
652*b843c749SSergey Zigachev
dce112_compressor_program_lpt_control(struct compressor * compressor,struct compr_addr_and_pitch_params * params)653*b843c749SSergey Zigachev void dce112_compressor_program_lpt_control(
654*b843c749SSergey Zigachev struct compressor *compressor,
655*b843c749SSergey Zigachev struct compr_addr_and_pitch_params *params)
656*b843c749SSergey Zigachev {
657*b843c749SSergey Zigachev struct dce112_compressor *cp110 = TO_DCE112_COMPRESSOR(compressor);
658*b843c749SSergey Zigachev uint32_t rows_per_channel;
659*b843c749SSergey Zigachev uint32_t lpt_alignment;
660*b843c749SSergey Zigachev uint32_t source_view_width;
661*b843c749SSergey Zigachev uint32_t source_view_height;
662*b843c749SSergey Zigachev uint32_t lpt_control = 0;
663*b843c749SSergey Zigachev
664*b843c749SSergey Zigachev if (!compressor->options.bits.LPT_SUPPORT)
665*b843c749SSergey Zigachev return;
666*b843c749SSergey Zigachev
667*b843c749SSergey Zigachev lpt_control = dm_read_reg(compressor->ctx,
668*b843c749SSergey Zigachev mmLOW_POWER_TILING_CONTROL);
669*b843c749SSergey Zigachev
670*b843c749SSergey Zigachev /* POSSIBLE VALUES for Low Power Tiling Mode:
671*b843c749SSergey Zigachev * 00 - Use channel 0
672*b843c749SSergey Zigachev * 01 - Use Channel 0 and 1
673*b843c749SSergey Zigachev * 02 - Use Channel 0,1,2,3
674*b843c749SSergey Zigachev * 03 - reserved */
675*b843c749SSergey Zigachev switch (compressor->lpt_channels_num) {
676*b843c749SSergey Zigachev /* case 2:
677*b843c749SSergey Zigachev * Use Channel 0 & 1 / Not used for DCE 11 */
678*b843c749SSergey Zigachev case 1:
679*b843c749SSergey Zigachev /*Use Channel 0 for LPT for DCE 11 */
680*b843c749SSergey Zigachev set_reg_field_value(
681*b843c749SSergey Zigachev lpt_control,
682*b843c749SSergey Zigachev 0,
683*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
684*b843c749SSergey Zigachev LOW_POWER_TILING_MODE);
685*b843c749SSergey Zigachev break;
686*b843c749SSergey Zigachev default:
687*b843c749SSergey Zigachev DC_LOG_WARNING(
688*b843c749SSergey Zigachev "%s: Invalid selected DRAM channels for LPT!!!",
689*b843c749SSergey Zigachev __func__);
690*b843c749SSergey Zigachev break;
691*b843c749SSergey Zigachev }
692*b843c749SSergey Zigachev
693*b843c749SSergey Zigachev lpt_control = lpt_memory_control_config(cp110, lpt_control);
694*b843c749SSergey Zigachev
695*b843c749SSergey Zigachev /* Program LOW_POWER_TILING_ROWS_PER_CHAN field which depends on
696*b843c749SSergey Zigachev * FBC compressed surface pitch.
697*b843c749SSergey Zigachev * LOW_POWER_TILING_ROWS_PER_CHAN = Roundup ((Surface Height *
698*b843c749SSergey Zigachev * Surface Pitch) / (Row Size * Number of Channels *
699*b843c749SSergey Zigachev * Number of Banks)). */
700*b843c749SSergey Zigachev rows_per_channel = 0;
701*b843c749SSergey Zigachev lpt_alignment = lpt_size_alignment(cp110);
702*b843c749SSergey Zigachev source_view_width =
703*b843c749SSergey Zigachev align_to_chunks_number_per_line(
704*b843c749SSergey Zigachev cp110,
705*b843c749SSergey Zigachev params->source_view_width);
706*b843c749SSergey Zigachev source_view_height = (params->source_view_height + 1) & (~0x1);
707*b843c749SSergey Zigachev
708*b843c749SSergey Zigachev if (lpt_alignment != 0) {
709*b843c749SSergey Zigachev rows_per_channel = source_view_width * source_view_height * 4;
710*b843c749SSergey Zigachev rows_per_channel =
711*b843c749SSergey Zigachev (rows_per_channel % lpt_alignment) ?
712*b843c749SSergey Zigachev (rows_per_channel / lpt_alignment + 1) :
713*b843c749SSergey Zigachev rows_per_channel / lpt_alignment;
714*b843c749SSergey Zigachev }
715*b843c749SSergey Zigachev
716*b843c749SSergey Zigachev set_reg_field_value(
717*b843c749SSergey Zigachev lpt_control,
718*b843c749SSergey Zigachev rows_per_channel,
719*b843c749SSergey Zigachev LOW_POWER_TILING_CONTROL,
720*b843c749SSergey Zigachev LOW_POWER_TILING_ROWS_PER_CHAN);
721*b843c749SSergey Zigachev
722*b843c749SSergey Zigachev dm_write_reg(compressor->ctx,
723*b843c749SSergey Zigachev mmLOW_POWER_TILING_CONTROL, lpt_control);
724*b843c749SSergey Zigachev }
725*b843c749SSergey Zigachev
726*b843c749SSergey Zigachev /*
727*b843c749SSergey Zigachev * DCE 11 Frame Buffer Compression Implementation
728*b843c749SSergey Zigachev */
729*b843c749SSergey Zigachev
dce112_compressor_set_fbc_invalidation_triggers(struct compressor * compressor,uint32_t fbc_trigger)730*b843c749SSergey Zigachev void dce112_compressor_set_fbc_invalidation_triggers(
731*b843c749SSergey Zigachev struct compressor *compressor,
732*b843c749SSergey Zigachev uint32_t fbc_trigger)
733*b843c749SSergey Zigachev {
734*b843c749SSergey Zigachev /* Disable region hit event, FBC_MEMORY_REGION_MASK = 0 (bits 16-19)
735*b843c749SSergey Zigachev * for DCE 11 regions cannot be used - does not work with S/G
736*b843c749SSergey Zigachev */
737*b843c749SSergey Zigachev uint32_t addr = mmFBC_CLIENT_REGION_MASK;
738*b843c749SSergey Zigachev uint32_t value = dm_read_reg(compressor->ctx, addr);
739*b843c749SSergey Zigachev
740*b843c749SSergey Zigachev set_reg_field_value(
741*b843c749SSergey Zigachev value,
742*b843c749SSergey Zigachev 0,
743*b843c749SSergey Zigachev FBC_CLIENT_REGION_MASK,
744*b843c749SSergey Zigachev FBC_MEMORY_REGION_MASK);
745*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
746*b843c749SSergey Zigachev
747*b843c749SSergey Zigachev /* Setup events when to clear all CSM entries (effectively marking
748*b843c749SSergey Zigachev * current compressed data invalid)
749*b843c749SSergey Zigachev * For DCE 11 CSM metadata 11111 means - "Not Compressed"
750*b843c749SSergey Zigachev * Used as the initial value of the metadata sent to the compressor
751*b843c749SSergey Zigachev * after invalidation, to indicate that the compressor should attempt
752*b843c749SSergey Zigachev * to compress all chunks on the current pass. Also used when the chunk
753*b843c749SSergey Zigachev * is not successfully written to memory.
754*b843c749SSergey Zigachev * When this CSM value is detected, FBC reads from the uncompressed
755*b843c749SSergey Zigachev * buffer. Set events according to passed in value, these events are
756*b843c749SSergey Zigachev * valid for DCE11:
757*b843c749SSergey Zigachev * - bit 0 - display register updated
758*b843c749SSergey Zigachev * - bit 28 - memory write from any client except from MCIF
759*b843c749SSergey Zigachev * - bit 29 - CG static screen signal is inactive
760*b843c749SSergey Zigachev * In addition, DCE11.1 also needs to set new DCE11.1 specific events
761*b843c749SSergey Zigachev * that are used to trigger invalidation on certain register changes,
762*b843c749SSergey Zigachev * for example enabling of Alpha Compression may trigger invalidation of
763*b843c749SSergey Zigachev * FBC once bit is set. These events are as follows:
764*b843c749SSergey Zigachev * - Bit 2 - FBC_GRPH_COMP_EN register updated
765*b843c749SSergey Zigachev * - Bit 3 - FBC_SRC_SEL register updated
766*b843c749SSergey Zigachev * - Bit 4 - FBC_MIN_COMPRESSION register updated
767*b843c749SSergey Zigachev * - Bit 5 - FBC_ALPHA_COMP_EN register updated
768*b843c749SSergey Zigachev * - Bit 6 - FBC_ZERO_ALPHA_CHUNK_SKIP_EN register updated
769*b843c749SSergey Zigachev * - Bit 7 - FBC_FORCE_COPY_TO_COMP_BUF register updated
770*b843c749SSergey Zigachev */
771*b843c749SSergey Zigachev addr = mmFBC_IDLE_FORCE_CLEAR_MASK;
772*b843c749SSergey Zigachev value = dm_read_reg(compressor->ctx, addr);
773*b843c749SSergey Zigachev set_reg_field_value(
774*b843c749SSergey Zigachev value,
775*b843c749SSergey Zigachev fbc_trigger |
776*b843c749SSergey Zigachev FBC_IDLE_FORCE_GRPH_COMP_EN |
777*b843c749SSergey Zigachev FBC_IDLE_FORCE_SRC_SEL_CHANGE |
778*b843c749SSergey Zigachev FBC_IDLE_FORCE_MIN_COMPRESSION_CHANGE |
779*b843c749SSergey Zigachev FBC_IDLE_FORCE_ALPHA_COMP_EN |
780*b843c749SSergey Zigachev FBC_IDLE_FORCE_ZERO_ALPHA_CHUNK_SKIP_EN |
781*b843c749SSergey Zigachev FBC_IDLE_FORCE_FORCE_COPY_TO_COMP_BUF,
782*b843c749SSergey Zigachev FBC_IDLE_FORCE_CLEAR_MASK,
783*b843c749SSergey Zigachev FBC_IDLE_FORCE_CLEAR_MASK);
784*b843c749SSergey Zigachev dm_write_reg(compressor->ctx, addr, value);
785*b843c749SSergey Zigachev }
786*b843c749SSergey Zigachev
dce112_compressor_construct(struct dce112_compressor * compressor,struct dc_context * ctx)787*b843c749SSergey Zigachev void dce112_compressor_construct(struct dce112_compressor *compressor,
788*b843c749SSergey Zigachev struct dc_context *ctx)
789*b843c749SSergey Zigachev {
790*b843c749SSergey Zigachev struct dc_bios *bp = ctx->dc_bios;
791*b843c749SSergey Zigachev struct embedded_panel_info panel_info;
792*b843c749SSergey Zigachev
793*b843c749SSergey Zigachev compressor->base.options.raw = 0;
794*b843c749SSergey Zigachev compressor->base.options.bits.FBC_SUPPORT = true;
795*b843c749SSergey Zigachev compressor->base.options.bits.LPT_SUPPORT = true;
796*b843c749SSergey Zigachev /* For DCE 11 always use one DRAM channel for LPT */
797*b843c749SSergey Zigachev compressor->base.lpt_channels_num = 1;
798*b843c749SSergey Zigachev compressor->base.options.bits.DUMMY_BACKEND = false;
799*b843c749SSergey Zigachev
800*b843c749SSergey Zigachev /* Check if this system has more than 1 DRAM channel; if only 1 then LPT
801*b843c749SSergey Zigachev * should not be supported */
802*b843c749SSergey Zigachev if (compressor->base.memory_bus_width == 64)
803*b843c749SSergey Zigachev compressor->base.options.bits.LPT_SUPPORT = false;
804*b843c749SSergey Zigachev
805*b843c749SSergey Zigachev compressor->base.options.bits.CLK_GATING_DISABLED = false;
806*b843c749SSergey Zigachev
807*b843c749SSergey Zigachev compressor->base.ctx = ctx;
808*b843c749SSergey Zigachev compressor->base.embedded_panel_h_size = 0;
809*b843c749SSergey Zigachev compressor->base.embedded_panel_v_size = 0;
810*b843c749SSergey Zigachev compressor->base.memory_bus_width = ctx->asic_id.vram_width;
811*b843c749SSergey Zigachev compressor->base.allocated_size = 0;
812*b843c749SSergey Zigachev compressor->base.preferred_requested_size = 0;
813*b843c749SSergey Zigachev compressor->base.min_compress_ratio = FBC_COMPRESS_RATIO_INVALID;
814*b843c749SSergey Zigachev compressor->base.banks_num = 0;
815*b843c749SSergey Zigachev compressor->base.raw_size = 0;
816*b843c749SSergey Zigachev compressor->base.channel_interleave_size = 0;
817*b843c749SSergey Zigachev compressor->base.dram_channels_num = 0;
818*b843c749SSergey Zigachev compressor->base.lpt_channels_num = 0;
819*b843c749SSergey Zigachev compressor->base.attached_inst = 0;
820*b843c749SSergey Zigachev compressor->base.is_enabled = false;
821*b843c749SSergey Zigachev
822*b843c749SSergey Zigachev if (BP_RESULT_OK ==
823*b843c749SSergey Zigachev bp->funcs->get_embedded_panel_info(bp, &panel_info)) {
824*b843c749SSergey Zigachev compressor->base.embedded_panel_h_size =
825*b843c749SSergey Zigachev panel_info.lcd_timing.horizontal_addressable;
826*b843c749SSergey Zigachev compressor->base.embedded_panel_v_size =
827*b843c749SSergey Zigachev panel_info.lcd_timing.vertical_addressable;
828*b843c749SSergey Zigachev }
829*b843c749SSergey Zigachev }
830*b843c749SSergey Zigachev
dce112_compressor_create(struct dc_context * ctx)831*b843c749SSergey Zigachev struct compressor *dce112_compressor_create(struct dc_context *ctx)
832*b843c749SSergey Zigachev {
833*b843c749SSergey Zigachev struct dce112_compressor *cp110 =
834*b843c749SSergey Zigachev kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL);
835*b843c749SSergey Zigachev
836*b843c749SSergey Zigachev if (!cp110)
837*b843c749SSergey Zigachev return NULL;
838*b843c749SSergey Zigachev
839*b843c749SSergey Zigachev dce112_compressor_construct(cp110, ctx);
840*b843c749SSergey Zigachev return &cp110->base;
841*b843c749SSergey Zigachev }
842*b843c749SSergey Zigachev
dce112_compressor_destroy(struct compressor ** compressor)843*b843c749SSergey Zigachev void dce112_compressor_destroy(struct compressor **compressor)
844*b843c749SSergey Zigachev {
845*b843c749SSergey Zigachev kfree(TO_DCE112_COMPRESSOR(*compressor));
846*b843c749SSergey Zigachev *compressor = NULL;
847*b843c749SSergey Zigachev }
848