1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev #include "dc.h"
28*b843c749SSergey Zigachev #include "core_types.h"
29*b843c749SSergey Zigachev #include "dce112_hw_sequencer.h"
30*b843c749SSergey Zigachev
31*b843c749SSergey Zigachev #include "dce110/dce110_hw_sequencer.h"
32*b843c749SSergey Zigachev
33*b843c749SSergey Zigachev /* include DCE11.2 register header files */
34*b843c749SSergey Zigachev #include "dce/dce_11_2_d.h"
35*b843c749SSergey Zigachev #include "dce/dce_11_2_sh_mask.h"
36*b843c749SSergey Zigachev
37*b843c749SSergey Zigachev struct dce112_hw_seq_reg_offsets {
38*b843c749SSergey Zigachev uint32_t crtc;
39*b843c749SSergey Zigachev };
40*b843c749SSergey Zigachev
41*b843c749SSergey Zigachev
42*b843c749SSergey Zigachev static const struct dce112_hw_seq_reg_offsets reg_offsets[] = {
43*b843c749SSergey Zigachev {
44*b843c749SSergey Zigachev .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
45*b843c749SSergey Zigachev },
46*b843c749SSergey Zigachev {
47*b843c749SSergey Zigachev .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
48*b843c749SSergey Zigachev },
49*b843c749SSergey Zigachev {
50*b843c749SSergey Zigachev .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
51*b843c749SSergey Zigachev },
52*b843c749SSergey Zigachev {
53*b843c749SSergey Zigachev .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
54*b843c749SSergey Zigachev },
55*b843c749SSergey Zigachev {
56*b843c749SSergey Zigachev .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
57*b843c749SSergey Zigachev },
58*b843c749SSergey Zigachev {
59*b843c749SSergey Zigachev .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
60*b843c749SSergey Zigachev }
61*b843c749SSergey Zigachev };
62*b843c749SSergey Zigachev #define HW_REG_CRTC(reg, id)\
63*b843c749SSergey Zigachev (reg + reg_offsets[id].crtc)
64*b843c749SSergey Zigachev
65*b843c749SSergey Zigachev /*******************************************************************************
66*b843c749SSergey Zigachev * Private definitions
67*b843c749SSergey Zigachev ******************************************************************************/
68*b843c749SSergey Zigachev
dce112_init_pte(struct dc_context * ctx)69*b843c749SSergey Zigachev static void dce112_init_pte(struct dc_context *ctx)
70*b843c749SSergey Zigachev {
71*b843c749SSergey Zigachev uint32_t addr;
72*b843c749SSergey Zigachev uint32_t value = 0;
73*b843c749SSergey Zigachev uint32_t chunk_int = 0;
74*b843c749SSergey Zigachev uint32_t chunk_mul = 0;
75*b843c749SSergey Zigachev
76*b843c749SSergey Zigachev addr = mmDVMM_PTE_REQ;
77*b843c749SSergey Zigachev value = dm_read_reg(ctx, addr);
78*b843c749SSergey Zigachev
79*b843c749SSergey Zigachev chunk_int = get_reg_field_value(
80*b843c749SSergey Zigachev value,
81*b843c749SSergey Zigachev DVMM_PTE_REQ,
82*b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_INT);
83*b843c749SSergey Zigachev
84*b843c749SSergey Zigachev chunk_mul = get_reg_field_value(
85*b843c749SSergey Zigachev value,
86*b843c749SSergey Zigachev DVMM_PTE_REQ,
87*b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
88*b843c749SSergey Zigachev
89*b843c749SSergey Zigachev if (chunk_int != 0x4 || chunk_mul != 0x4) {
90*b843c749SSergey Zigachev
91*b843c749SSergey Zigachev set_reg_field_value(
92*b843c749SSergey Zigachev value,
93*b843c749SSergey Zigachev 255,
94*b843c749SSergey Zigachev DVMM_PTE_REQ,
95*b843c749SSergey Zigachev MAX_PTEREQ_TO_ISSUE);
96*b843c749SSergey Zigachev
97*b843c749SSergey Zigachev set_reg_field_value(
98*b843c749SSergey Zigachev value,
99*b843c749SSergey Zigachev 4,
100*b843c749SSergey Zigachev DVMM_PTE_REQ,
101*b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_INT);
102*b843c749SSergey Zigachev
103*b843c749SSergey Zigachev set_reg_field_value(
104*b843c749SSergey Zigachev value,
105*b843c749SSergey Zigachev 4,
106*b843c749SSergey Zigachev DVMM_PTE_REQ,
107*b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
108*b843c749SSergey Zigachev
109*b843c749SSergey Zigachev dm_write_reg(ctx, addr, value);
110*b843c749SSergey Zigachev }
111*b843c749SSergey Zigachev }
112*b843c749SSergey Zigachev
dce112_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)113*b843c749SSergey Zigachev static bool dce112_enable_display_power_gating(
114*b843c749SSergey Zigachev struct dc *dc,
115*b843c749SSergey Zigachev uint8_t controller_id,
116*b843c749SSergey Zigachev struct dc_bios *dcb,
117*b843c749SSergey Zigachev enum pipe_gating_control power_gating)
118*b843c749SSergey Zigachev {
119*b843c749SSergey Zigachev enum bp_result bp_result = BP_RESULT_OK;
120*b843c749SSergey Zigachev enum bp_pipe_control_action cntl;
121*b843c749SSergey Zigachev struct dc_context *ctx = dc->ctx;
122*b843c749SSergey Zigachev
123*b843c749SSergey Zigachev if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
124*b843c749SSergey Zigachev return true;
125*b843c749SSergey Zigachev
126*b843c749SSergey Zigachev if (power_gating == PIPE_GATING_CONTROL_INIT)
127*b843c749SSergey Zigachev cntl = ASIC_PIPE_INIT;
128*b843c749SSergey Zigachev else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
129*b843c749SSergey Zigachev cntl = ASIC_PIPE_ENABLE;
130*b843c749SSergey Zigachev else
131*b843c749SSergey Zigachev cntl = ASIC_PIPE_DISABLE;
132*b843c749SSergey Zigachev
133*b843c749SSergey Zigachev if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
134*b843c749SSergey Zigachev
135*b843c749SSergey Zigachev bp_result = dcb->funcs->enable_disp_power_gating(
136*b843c749SSergey Zigachev dcb, controller_id + 1, cntl);
137*b843c749SSergey Zigachev
138*b843c749SSergey Zigachev /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
139*b843c749SSergey Zigachev * by default when command table is called
140*b843c749SSergey Zigachev */
141*b843c749SSergey Zigachev dm_write_reg(ctx,
142*b843c749SSergey Zigachev HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
143*b843c749SSergey Zigachev 0);
144*b843c749SSergey Zigachev }
145*b843c749SSergey Zigachev
146*b843c749SSergey Zigachev if (power_gating != PIPE_GATING_CONTROL_ENABLE)
147*b843c749SSergey Zigachev dce112_init_pte(ctx);
148*b843c749SSergey Zigachev
149*b843c749SSergey Zigachev if (bp_result == BP_RESULT_OK)
150*b843c749SSergey Zigachev return true;
151*b843c749SSergey Zigachev else
152*b843c749SSergey Zigachev return false;
153*b843c749SSergey Zigachev }
154*b843c749SSergey Zigachev
dce112_hw_sequencer_construct(struct dc * dc)155*b843c749SSergey Zigachev void dce112_hw_sequencer_construct(struct dc *dc)
156*b843c749SSergey Zigachev {
157*b843c749SSergey Zigachev /* All registers used by dce11.2 match those in dce11 in offset and
158*b843c749SSergey Zigachev * structure
159*b843c749SSergey Zigachev */
160*b843c749SSergey Zigachev dce110_hw_sequencer_construct(dc);
161*b843c749SSergey Zigachev dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating;
162*b843c749SSergey Zigachev }
163*b843c749SSergey Zigachev
164