1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev *
4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10b843c749SSergey Zigachev *
11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13b843c749SSergey Zigachev *
14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21b843c749SSergey Zigachev *
22b843c749SSergey Zigachev * Authors: AMD
23b843c749SSergey Zigachev *
24b843c749SSergey Zigachev */
25b843c749SSergey Zigachev
26b843c749SSergey Zigachev #include "dm_services.h"
27b843c749SSergey Zigachev #include "dc.h"
28b843c749SSergey Zigachev #include "core_types.h"
29b843c749SSergey Zigachev #include "dce120_hw_sequencer.h"
30b843c749SSergey Zigachev #include "dce/dce_hwseq.h"
31b843c749SSergey Zigachev
32b843c749SSergey Zigachev #include "dce110/dce110_hw_sequencer.h"
33b843c749SSergey Zigachev
34b843c749SSergey Zigachev #include "dce/dce_12_0_offset.h"
35b843c749SSergey Zigachev #include "dce/dce_12_0_sh_mask.h"
36b843c749SSergey Zigachev #include "soc15_hw_ip.h"
37b843c749SSergey Zigachev #include "vega10_ip_offset.h"
38b843c749SSergey Zigachev #include "reg_helper.h"
39b843c749SSergey Zigachev
40b843c749SSergey Zigachev #define CTX \
41b843c749SSergey Zigachev hws->ctx
42b843c749SSergey Zigachev #define REG(reg)\
43b843c749SSergey Zigachev hws->regs->reg
44b843c749SSergey Zigachev
45b843c749SSergey Zigachev #undef FN
46b843c749SSergey Zigachev #define FN(reg_name, field_name) \
47b843c749SSergey Zigachev hws->shifts->field_name, hws->masks->field_name
48b843c749SSergey Zigachev
49b843c749SSergey Zigachev struct dce120_hw_seq_reg_offsets {
50b843c749SSergey Zigachev uint32_t crtc;
51b843c749SSergey Zigachev };
52b843c749SSergey Zigachev
53*78973132SSergey Zigachev #if 0
54b843c749SSergey Zigachev static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
55b843c749SSergey Zigachev {
56b843c749SSergey Zigachev .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
57b843c749SSergey Zigachev },
58b843c749SSergey Zigachev {
59b843c749SSergey Zigachev .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
60b843c749SSergey Zigachev },
61b843c749SSergey Zigachev {
62b843c749SSergey Zigachev .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
63b843c749SSergey Zigachev },
64b843c749SSergey Zigachev {
65b843c749SSergey Zigachev .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
66b843c749SSergey Zigachev },
67b843c749SSergey Zigachev {
68b843c749SSergey Zigachev .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
69b843c749SSergey Zigachev },
70b843c749SSergey Zigachev {
71b843c749SSergey Zigachev .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
72b843c749SSergey Zigachev }
73b843c749SSergey Zigachev };
74*78973132SSergey Zigachev #endif
75b843c749SSergey Zigachev
76b843c749SSergey Zigachev #define HW_REG_CRTC(reg, id)\
77b843c749SSergey Zigachev (reg + reg_offsets[id].crtc)
78b843c749SSergey Zigachev
79b843c749SSergey Zigachev #define CNTL_ID(controller_id)\
80b843c749SSergey Zigachev controller_id
81b843c749SSergey Zigachev /*******************************************************************************
82b843c749SSergey Zigachev * Private definitions
83b843c749SSergey Zigachev ******************************************************************************/
84b843c749SSergey Zigachev #if 0
85b843c749SSergey Zigachev static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
86b843c749SSergey Zigachev {
87b843c749SSergey Zigachev uint32_t addr;
88b843c749SSergey Zigachev uint32_t value = 0;
89b843c749SSergey Zigachev uint32_t chunk_int = 0;
90b843c749SSergey Zigachev uint32_t chunk_mul = 0;
91b843c749SSergey Zigachev /*
92b843c749SSergey Zigachev addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
93b843c749SSergey Zigachev (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
94b843c749SSergey Zigachev
95b843c749SSergey Zigachev value = dm_read_reg(ctx, addr);
96b843c749SSergey Zigachev
97b843c749SSergey Zigachev set_reg_field_value(
98b843c749SSergey Zigachev value, 0, DCP, controller_id,
99b843c749SSergey Zigachev DVMM_PTE_CONTROL,
100b843c749SSergey Zigachev DVMM_USE_SINGLE_PTE);
101b843c749SSergey Zigachev
102b843c749SSergey Zigachev set_reg_field_value_soc15(
103b843c749SSergey Zigachev value, 1, DCP, controller_id,
104b843c749SSergey Zigachev DVMM_PTE_CONTROL,
105b843c749SSergey Zigachev DVMM_PTE_BUFFER_MODE0);
106b843c749SSergey Zigachev
107b843c749SSergey Zigachev set_reg_field_value_soc15(
108b843c749SSergey Zigachev value, 1, DCP, controller_id,
109b843c749SSergey Zigachev DVMM_PTE_CONTROL,
110b843c749SSergey Zigachev DVMM_PTE_BUFFER_MODE1);
111b843c749SSergey Zigachev
112b843c749SSergey Zigachev dm_write_reg(ctx, addr, value);*/
113b843c749SSergey Zigachev
114b843c749SSergey Zigachev addr = mmDVMM_PTE_REQ;
115b843c749SSergey Zigachev value = dm_read_reg(ctx, addr);
116b843c749SSergey Zigachev
117b843c749SSergey Zigachev chunk_int = get_reg_field_value(
118b843c749SSergey Zigachev value,
119b843c749SSergey Zigachev DVMM_PTE_REQ,
120b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_INT);
121b843c749SSergey Zigachev
122b843c749SSergey Zigachev chunk_mul = get_reg_field_value(
123b843c749SSergey Zigachev value,
124b843c749SSergey Zigachev DVMM_PTE_REQ,
125b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
126b843c749SSergey Zigachev
127b843c749SSergey Zigachev if (chunk_int != 0x4 || chunk_mul != 0x4) {
128b843c749SSergey Zigachev
129b843c749SSergey Zigachev set_reg_field_value(
130b843c749SSergey Zigachev value,
131b843c749SSergey Zigachev 255,
132b843c749SSergey Zigachev DVMM_PTE_REQ,
133b843c749SSergey Zigachev MAX_PTEREQ_TO_ISSUE);
134b843c749SSergey Zigachev
135b843c749SSergey Zigachev set_reg_field_value(
136b843c749SSergey Zigachev value,
137b843c749SSergey Zigachev 4,
138b843c749SSergey Zigachev DVMM_PTE_REQ,
139b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_INT);
140b843c749SSergey Zigachev
141b843c749SSergey Zigachev set_reg_field_value(
142b843c749SSergey Zigachev value,
143b843c749SSergey Zigachev 4,
144b843c749SSergey Zigachev DVMM_PTE_REQ,
145b843c749SSergey Zigachev HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
146b843c749SSergey Zigachev
147b843c749SSergey Zigachev dm_write_reg(ctx, addr, value);
148b843c749SSergey Zigachev }
149b843c749SSergey Zigachev }
150b843c749SSergey Zigachev #endif
151b843c749SSergey Zigachev
dce120_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)152b843c749SSergey Zigachev static bool dce120_enable_display_power_gating(
153b843c749SSergey Zigachev struct dc *dc,
154b843c749SSergey Zigachev uint8_t controller_id,
155b843c749SSergey Zigachev struct dc_bios *dcb,
156b843c749SSergey Zigachev enum pipe_gating_control power_gating)
157b843c749SSergey Zigachev {
158b843c749SSergey Zigachev /* disable for bringup */
159b843c749SSergey Zigachev #if 0
160b843c749SSergey Zigachev enum bp_result bp_result = BP_RESULT_OK;
161b843c749SSergey Zigachev enum bp_pipe_control_action cntl;
162b843c749SSergey Zigachev struct dc_context *ctx = dc->ctx;
163b843c749SSergey Zigachev
164b843c749SSergey Zigachev if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
165b843c749SSergey Zigachev return true;
166b843c749SSergey Zigachev
167b843c749SSergey Zigachev if (power_gating == PIPE_GATING_CONTROL_INIT)
168b843c749SSergey Zigachev cntl = ASIC_PIPE_INIT;
169b843c749SSergey Zigachev else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
170b843c749SSergey Zigachev cntl = ASIC_PIPE_ENABLE;
171b843c749SSergey Zigachev else
172b843c749SSergey Zigachev cntl = ASIC_PIPE_DISABLE;
173b843c749SSergey Zigachev
174b843c749SSergey Zigachev if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
175b843c749SSergey Zigachev
176b843c749SSergey Zigachev bp_result = dcb->funcs->enable_disp_power_gating(
177b843c749SSergey Zigachev dcb, controller_id + 1, cntl);
178b843c749SSergey Zigachev
179b843c749SSergey Zigachev /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
180b843c749SSergey Zigachev * by default when command table is called
181b843c749SSergey Zigachev */
182b843c749SSergey Zigachev dm_write_reg(ctx,
183b843c749SSergey Zigachev HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
184b843c749SSergey Zigachev 0);
185b843c749SSergey Zigachev }
186b843c749SSergey Zigachev
187b843c749SSergey Zigachev if (power_gating != PIPE_GATING_CONTROL_ENABLE)
188b843c749SSergey Zigachev dce120_init_pte(ctx, controller_id);
189b843c749SSergey Zigachev
190b843c749SSergey Zigachev if (bp_result == BP_RESULT_OK)
191b843c749SSergey Zigachev return true;
192b843c749SSergey Zigachev else
193b843c749SSergey Zigachev return false;
194b843c749SSergey Zigachev #endif
195b843c749SSergey Zigachev return false;
196b843c749SSergey Zigachev }
197b843c749SSergey Zigachev
dce120_update_dchub(struct dce_hwseq * hws,struct dchub_init_data * dh_data)198b843c749SSergey Zigachev static void dce120_update_dchub(
199b843c749SSergey Zigachev struct dce_hwseq *hws,
200b843c749SSergey Zigachev struct dchub_init_data *dh_data)
201b843c749SSergey Zigachev {
202b843c749SSergey Zigachev /* TODO: port code from dal2 */
203b843c749SSergey Zigachev switch (dh_data->fb_mode) {
204b843c749SSergey Zigachev case FRAME_BUFFER_MODE_ZFB_ONLY:
205b843c749SSergey Zigachev /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
206b843c749SSergey Zigachev REG_UPDATE_2(DCHUB_FB_LOCATION,
207b843c749SSergey Zigachev FB_TOP, 0,
208b843c749SSergey Zigachev FB_BASE, 0x0FFFF);
209b843c749SSergey Zigachev
210b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BASE,
211b843c749SSergey Zigachev AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
212b843c749SSergey Zigachev
213b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BOT,
214b843c749SSergey Zigachev AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
215b843c749SSergey Zigachev
216b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_TOP,
217b843c749SSergey Zigachev AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
218b843c749SSergey Zigachev break;
219b843c749SSergey Zigachev case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
220b843c749SSergey Zigachev /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
221b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BASE,
222b843c749SSergey Zigachev AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
223b843c749SSergey Zigachev
224b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BOT,
225b843c749SSergey Zigachev AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
226b843c749SSergey Zigachev
227b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_TOP,
228b843c749SSergey Zigachev AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
229b843c749SSergey Zigachev break;
230b843c749SSergey Zigachev case FRAME_BUFFER_MODE_LOCAL_ONLY:
231b843c749SSergey Zigachev /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
232b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BASE,
233b843c749SSergey Zigachev AGP_BASE, 0);
234b843c749SSergey Zigachev
235b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_BOT,
236b843c749SSergey Zigachev AGP_BOT, 0x03FFFF);
237b843c749SSergey Zigachev
238b843c749SSergey Zigachev REG_UPDATE(DCHUB_AGP_TOP,
239b843c749SSergey Zigachev AGP_TOP, 0);
240b843c749SSergey Zigachev break;
241b843c749SSergey Zigachev default:
242b843c749SSergey Zigachev break;
243b843c749SSergey Zigachev }
244b843c749SSergey Zigachev
245b843c749SSergey Zigachev dh_data->dchub_initialzied = true;
246b843c749SSergey Zigachev dh_data->dchub_info_valid = false;
247b843c749SSergey Zigachev }
248b843c749SSergey Zigachev
dce120_hw_sequencer_construct(struct dc * dc)249b843c749SSergey Zigachev void dce120_hw_sequencer_construct(struct dc *dc)
250b843c749SSergey Zigachev {
251b843c749SSergey Zigachev /* All registers used by dce11.2 match those in dce11 in offset and
252b843c749SSergey Zigachev * structure
253b843c749SSergey Zigachev */
254b843c749SSergey Zigachev dce110_hw_sequencer_construct(dc);
255b843c749SSergey Zigachev dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
256b843c749SSergey Zigachev dc->hwss.update_dchub = dce120_update_dchub;
257b843c749SSergey Zigachev }
258b843c749SSergey Zigachev
259