1 /*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dc.h"
28 #include "core_types.h"
29 #include "dce120_hw_sequencer.h"
30 #include "dce/dce_hwseq.h"
31
32 #include "dce110/dce110_hw_sequencer.h"
33
34 #include "dce/dce_12_0_offset.h"
35 #include "dce/dce_12_0_sh_mask.h"
36 #include "soc15_hw_ip.h"
37 #include "vega10_ip_offset.h"
38 #include "reg_helper.h"
39
40 #define CTX \
41 hws->ctx
42 #define REG(reg)\
43 hws->regs->reg
44
45 #undef FN
46 #define FN(reg_name, field_name) \
47 hws->shifts->field_name, hws->masks->field_name
48
49 struct dce120_hw_seq_reg_offsets {
50 uint32_t crtc;
51 };
52
53 #if 0
54 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
55 {
56 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
57 },
58 {
59 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
60 },
61 {
62 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
63 },
64 {
65 .crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
66 },
67 {
68 .crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
69 },
70 {
71 .crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC0_CRTC_GSL_CONTROL),
72 }
73 };
74 #endif
75
76 #define HW_REG_CRTC(reg, id)\
77 (reg + reg_offsets[id].crtc)
78
79 #define CNTL_ID(controller_id)\
80 controller_id
81 /*******************************************************************************
82 * Private definitions
83 ******************************************************************************/
84 #if 0
85 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id)
86 {
87 uint32_t addr;
88 uint32_t value = 0;
89 uint32_t chunk_int = 0;
90 uint32_t chunk_mul = 0;
91 /*
92 addr = mmDCP0_DVMM_PTE_CONTROL + controller_id *
93 (mmDCP1_DVMM_PTE_CONTROL- mmDCP0_DVMM_PTE_CONTROL);
94
95 value = dm_read_reg(ctx, addr);
96
97 set_reg_field_value(
98 value, 0, DCP, controller_id,
99 DVMM_PTE_CONTROL,
100 DVMM_USE_SINGLE_PTE);
101
102 set_reg_field_value_soc15(
103 value, 1, DCP, controller_id,
104 DVMM_PTE_CONTROL,
105 DVMM_PTE_BUFFER_MODE0);
106
107 set_reg_field_value_soc15(
108 value, 1, DCP, controller_id,
109 DVMM_PTE_CONTROL,
110 DVMM_PTE_BUFFER_MODE1);
111
112 dm_write_reg(ctx, addr, value);*/
113
114 addr = mmDVMM_PTE_REQ;
115 value = dm_read_reg(ctx, addr);
116
117 chunk_int = get_reg_field_value(
118 value,
119 DVMM_PTE_REQ,
120 HFLIP_PTEREQ_PER_CHUNK_INT);
121
122 chunk_mul = get_reg_field_value(
123 value,
124 DVMM_PTE_REQ,
125 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
126
127 if (chunk_int != 0x4 || chunk_mul != 0x4) {
128
129 set_reg_field_value(
130 value,
131 255,
132 DVMM_PTE_REQ,
133 MAX_PTEREQ_TO_ISSUE);
134
135 set_reg_field_value(
136 value,
137 4,
138 DVMM_PTE_REQ,
139 HFLIP_PTEREQ_PER_CHUNK_INT);
140
141 set_reg_field_value(
142 value,
143 4,
144 DVMM_PTE_REQ,
145 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
146
147 dm_write_reg(ctx, addr, value);
148 }
149 }
150 #endif
151
dce120_enable_display_power_gating(struct dc * dc,uint8_t controller_id,struct dc_bios * dcb,enum pipe_gating_control power_gating)152 static bool dce120_enable_display_power_gating(
153 struct dc *dc,
154 uint8_t controller_id,
155 struct dc_bios *dcb,
156 enum pipe_gating_control power_gating)
157 {
158 /* disable for bringup */
159 #if 0
160 enum bp_result bp_result = BP_RESULT_OK;
161 enum bp_pipe_control_action cntl;
162 struct dc_context *ctx = dc->ctx;
163
164 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
165 return true;
166
167 if (power_gating == PIPE_GATING_CONTROL_INIT)
168 cntl = ASIC_PIPE_INIT;
169 else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
170 cntl = ASIC_PIPE_ENABLE;
171 else
172 cntl = ASIC_PIPE_DISABLE;
173
174 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) {
175
176 bp_result = dcb->funcs->enable_disp_power_gating(
177 dcb, controller_id + 1, cntl);
178
179 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
180 * by default when command table is called
181 */
182 dm_write_reg(ctx,
183 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id),
184 0);
185 }
186
187 if (power_gating != PIPE_GATING_CONTROL_ENABLE)
188 dce120_init_pte(ctx, controller_id);
189
190 if (bp_result == BP_RESULT_OK)
191 return true;
192 else
193 return false;
194 #endif
195 return false;
196 }
197
dce120_update_dchub(struct dce_hwseq * hws,struct dchub_init_data * dh_data)198 static void dce120_update_dchub(
199 struct dce_hwseq *hws,
200 struct dchub_init_data *dh_data)
201 {
202 /* TODO: port code from dal2 */
203 switch (dh_data->fb_mode) {
204 case FRAME_BUFFER_MODE_ZFB_ONLY:
205 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
206 REG_UPDATE_2(DCHUB_FB_LOCATION,
207 FB_TOP, 0,
208 FB_BASE, 0x0FFFF);
209
210 REG_UPDATE(DCHUB_AGP_BASE,
211 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
212
213 REG_UPDATE(DCHUB_AGP_BOT,
214 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
215
216 REG_UPDATE(DCHUB_AGP_TOP,
217 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
218 break;
219 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
220 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
221 REG_UPDATE(DCHUB_AGP_BASE,
222 AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
223
224 REG_UPDATE(DCHUB_AGP_BOT,
225 AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
226
227 REG_UPDATE(DCHUB_AGP_TOP,
228 AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
229 break;
230 case FRAME_BUFFER_MODE_LOCAL_ONLY:
231 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
232 REG_UPDATE(DCHUB_AGP_BASE,
233 AGP_BASE, 0);
234
235 REG_UPDATE(DCHUB_AGP_BOT,
236 AGP_BOT, 0x03FFFF);
237
238 REG_UPDATE(DCHUB_AGP_TOP,
239 AGP_TOP, 0);
240 break;
241 default:
242 break;
243 }
244
245 dh_data->dchub_initialzied = true;
246 dh_data->dchub_info_valid = false;
247 }
248
dce120_hw_sequencer_construct(struct dc * dc)249 void dce120_hw_sequencer_construct(struct dc *dc)
250 {
251 /* All registers used by dce11.2 match those in dce11 in offset and
252 * structure
253 */
254 dce110_hw_sequencer_construct(dc);
255 dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating;
256 dc->hwss.update_dchub = dce120_update_dchub;
257 }
258
259