1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dce/dce_8_0_d.h" 27 #include "dce/dce_8_0_sh_mask.h" 28 29 #include "dm_services.h" 30 31 #include "link_encoder.h" 32 #include "stream_encoder.h" 33 34 #include "resource.h" 35 #include "include/irq_service_interface.h" 36 #include "irq/dce80/irq_service_dce80.h" 37 #include "dce110/dce110_timing_generator.h" 38 #include "dce110/dce110_resource.h" 39 #include "dce80/dce80_timing_generator.h" 40 #include "dce/dce_mem_input.h" 41 #include "dce/dce_link_encoder.h" 42 #include "dce/dce_stream_encoder.h" 43 #include "dce/dce_mem_input.h" 44 #include "dce/dce_ipp.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_opp.h" 47 #include "dce/dce_clocks.h" 48 #include "dce/dce_clock_source.h" 49 #include "dce/dce_audio.h" 50 #include "dce/dce_hwseq.h" 51 #include "dce80/dce80_hw_sequencer.h" 52 #include "dce100/dce100_resource.h" 53 54 #include "reg_helper.h" 55 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_abm.h" 59 /* TODO remove this include */ 60 61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT 62 #include "gmc/gmc_7_1_d.h" 63 #include "gmc/gmc_7_1_sh_mask.h" 64 #endif 65 66 #include "dce80/dce80_resource.h" 67 68 #ifndef mmDP_DPHY_INTERNAL_CTRL 69 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE 70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE 71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE 72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE 73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE 74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE 75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE 76 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE 77 #endif 78 79 80 #ifndef mmBIOS_SCRATCH_2 81 #define mmBIOS_SCRATCH_2 0x05CB 82 #define mmBIOS_SCRATCH_6 0x05CF 83 #endif 84 85 #ifndef mmDP_DPHY_FAST_TRAINING 86 #define mmDP_DPHY_FAST_TRAINING 0x1CCE 87 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 88 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 89 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 90 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 91 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 92 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 93 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE 94 #endif 95 96 97 #ifndef mmHPD_DC_HPD_CONTROL 98 #define mmHPD_DC_HPD_CONTROL 0x189A 99 #define mmHPD0_DC_HPD_CONTROL 0x189A 100 #define mmHPD1_DC_HPD_CONTROL 0x18A2 101 #define mmHPD2_DC_HPD_CONTROL 0x18AA 102 #define mmHPD3_DC_HPD_CONTROL 0x18B2 103 #define mmHPD4_DC_HPD_CONTROL 0x18BA 104 #define mmHPD5_DC_HPD_CONTROL 0x18C2 105 #endif 106 107 #define DCE11_DIG_FE_CNTL 0x4a00 108 #define DCE11_DIG_BE_CNTL 0x4a47 109 #define DCE11_DP_SEC 0x4ac3 110 111 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = { 112 { 113 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 114 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL), 115 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL 116 - mmDPG_WATERMARK_MASK_CONTROL), 117 }, 118 { 119 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 120 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 121 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL 122 - mmDPG_WATERMARK_MASK_CONTROL), 123 }, 124 { 125 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 126 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 127 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL 128 - mmDPG_WATERMARK_MASK_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 133 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL 134 - mmDPG_WATERMARK_MASK_CONTROL), 135 }, 136 { 137 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 138 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 139 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL 140 - mmDPG_WATERMARK_MASK_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL 146 - mmDPG_WATERMARK_MASK_CONTROL), 147 } 148 }; 149 150 /* set register offset */ 151 #define SR(reg_name)\ 152 .reg_name = mm ## reg_name 153 154 /* set register offset with instance */ 155 #define SRI(reg_name, block, id)\ 156 .reg_name = mm ## block ## id ## _ ## reg_name 157 158 159 static const struct dccg_registers disp_clk_regs = { 160 CLK_COMMON_REG_LIST_DCE_BASE() 161 }; 162 163 static const struct dccg_shift disp_clk_shift = { 164 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 165 }; 166 167 static const struct dccg_mask disp_clk_mask = { 168 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 169 }; 170 171 #define ipp_regs(id)\ 172 [id] = {\ 173 IPP_COMMON_REG_LIST_DCE_BASE(id)\ 174 } 175 176 static const struct dce_ipp_registers ipp_regs[] = { 177 ipp_regs(0), 178 ipp_regs(1), 179 ipp_regs(2), 180 ipp_regs(3), 181 ipp_regs(4), 182 ipp_regs(5) 183 }; 184 185 static const struct dce_ipp_shift ipp_shift = { 186 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 187 }; 188 189 static const struct dce_ipp_mask ipp_mask = { 190 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 191 }; 192 193 #define transform_regs(id)\ 194 [id] = {\ 195 XFM_COMMON_REG_LIST_DCE80(id)\ 196 } 197 198 static const struct dce_transform_registers xfm_regs[] = { 199 transform_regs(0), 200 transform_regs(1), 201 transform_regs(2), 202 transform_regs(3), 203 transform_regs(4), 204 transform_regs(5) 205 }; 206 207 static const struct dce_transform_shift xfm_shift = { 208 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) 209 }; 210 211 static const struct dce_transform_mask xfm_mask = { 212 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) 213 }; 214 215 #define aux_regs(id)\ 216 [id] = {\ 217 AUX_REG_LIST(id)\ 218 } 219 220 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 221 aux_regs(0), 222 aux_regs(1), 223 aux_regs(2), 224 aux_regs(3), 225 aux_regs(4), 226 aux_regs(5) 227 }; 228 229 #define hpd_regs(id)\ 230 [id] = {\ 231 HPD_REG_LIST(id)\ 232 } 233 234 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 235 hpd_regs(0), 236 hpd_regs(1), 237 hpd_regs(2), 238 hpd_regs(3), 239 hpd_regs(4), 240 hpd_regs(5) 241 }; 242 243 #define link_regs(id)\ 244 [id] = {\ 245 LE_DCE80_REG_LIST(id)\ 246 } 247 248 static const struct dce110_link_enc_registers link_enc_regs[] = { 249 link_regs(0), 250 link_regs(1), 251 link_regs(2), 252 link_regs(3), 253 link_regs(4), 254 link_regs(5), 255 link_regs(6), 256 }; 257 258 #define stream_enc_regs(id)\ 259 [id] = {\ 260 SE_COMMON_REG_LIST_DCE_BASE(id),\ 261 .AFMT_CNTL = 0,\ 262 } 263 264 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 265 stream_enc_regs(0), 266 stream_enc_regs(1), 267 stream_enc_regs(2), 268 stream_enc_regs(3), 269 stream_enc_regs(4), 270 stream_enc_regs(5), 271 stream_enc_regs(6) 272 }; 273 274 static const struct dce_stream_encoder_shift se_shift = { 275 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) 276 }; 277 278 static const struct dce_stream_encoder_mask se_mask = { 279 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) 280 }; 281 282 #define opp_regs(id)\ 283 [id] = {\ 284 OPP_DCE_80_REG_LIST(id),\ 285 } 286 287 static const struct dce_opp_registers opp_regs[] = { 288 opp_regs(0), 289 opp_regs(1), 290 opp_regs(2), 291 opp_regs(3), 292 opp_regs(4), 293 opp_regs(5) 294 }; 295 296 static const struct dce_opp_shift opp_shift = { 297 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) 298 }; 299 300 static const struct dce_opp_mask opp_mask = { 301 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) 302 }; 303 304 #define aux_engine_regs(id)\ 305 [id] = {\ 306 AUX_COMMON_REG_LIST(id), \ 307 .AUX_RESET_MASK = 0 \ 308 } 309 310 static const struct dce110_aux_registers aux_engine_regs[] = { 311 aux_engine_regs(0), 312 aux_engine_regs(1), 313 aux_engine_regs(2), 314 aux_engine_regs(3), 315 aux_engine_regs(4), 316 aux_engine_regs(5) 317 }; 318 319 #define audio_regs(id)\ 320 [id] = {\ 321 AUD_COMMON_REG_LIST(id)\ 322 } 323 324 static const struct dce_audio_registers audio_regs[] = { 325 audio_regs(0), 326 audio_regs(1), 327 audio_regs(2), 328 audio_regs(3), 329 audio_regs(4), 330 audio_regs(5), 331 audio_regs(6), 332 }; 333 334 static const struct dce_audio_shift audio_shift = { 335 AUD_COMMON_MASK_SH_LIST(__SHIFT) 336 }; 337 338 static const struct dce_aduio_mask audio_mask = { 339 AUD_COMMON_MASK_SH_LIST(_MASK) 340 }; 341 342 #define clk_src_regs(id)\ 343 [id] = {\ 344 CS_COMMON_REG_LIST_DCE_80(id),\ 345 } 346 347 348 static const struct dce110_clk_src_regs clk_src_regs[] = { 349 clk_src_regs(0), 350 clk_src_regs(1), 351 clk_src_regs(2) 352 }; 353 354 static const struct dce110_clk_src_shift cs_shift = { 355 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 356 }; 357 358 static const struct dce110_clk_src_mask cs_mask = { 359 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 360 }; 361 362 static const struct bios_registers bios_regs = { 363 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 364 }; 365 366 static const struct resource_caps res_cap = { 367 .num_timing_generator = 6, 368 .num_audio = 6, 369 .num_stream_encoder = 6, 370 .num_pll = 3, 371 }; 372 373 static const struct resource_caps res_cap_81 = { 374 .num_timing_generator = 4, 375 .num_audio = 7, 376 .num_stream_encoder = 7, 377 .num_pll = 3, 378 }; 379 380 static const struct resource_caps res_cap_83 = { 381 .num_timing_generator = 2, 382 .num_audio = 6, 383 .num_stream_encoder = 6, 384 .num_pll = 2, 385 }; 386 387 static const struct dce_dmcu_registers dmcu_regs = { 388 DMCU_DCE80_REG_LIST() 389 }; 390 391 static const struct dce_dmcu_shift dmcu_shift = { 392 DMCU_MASK_SH_LIST_DCE80(__SHIFT) 393 }; 394 395 static const struct dce_dmcu_mask dmcu_mask = { 396 DMCU_MASK_SH_LIST_DCE80(_MASK) 397 }; 398 static const struct dce_abm_registers abm_regs = { 399 ABM_DCE110_COMMON_REG_LIST() 400 }; 401 402 static const struct dce_abm_shift abm_shift = { 403 ABM_MASK_SH_LIST_DCE110(__SHIFT) 404 }; 405 406 static const struct dce_abm_mask abm_mask = { 407 ABM_MASK_SH_LIST_DCE110(_MASK) 408 }; 409 410 #define CTX ctx 411 #define REG(reg) mm ## reg 412 413 #ifndef mmCC_DC_HDMI_STRAPS 414 #define mmCC_DC_HDMI_STRAPS 0x1918 415 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 416 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 417 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 418 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 419 #endif 420 421 static void read_dce_straps( 422 struct dc_context *ctx, 423 struct resource_straps *straps) 424 { 425 REG_GET_2(CC_DC_HDMI_STRAPS, 426 HDMI_DISABLE, &straps->hdmi_disable, 427 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 428 429 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 430 } 431 432 static struct audio *create_audio( 433 struct dc_context *ctx, unsigned int inst) 434 { 435 return dce_audio_create(ctx, inst, 436 &audio_regs[inst], &audio_shift, &audio_mask); 437 } 438 439 static struct timing_generator *dce80_timing_generator_create( 440 struct dc_context *ctx, 441 uint32_t instance, 442 const struct dce110_timing_generator_offsets *offsets) 443 { 444 struct dce110_timing_generator *tg110 = 445 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 446 447 if (!tg110) 448 return NULL; 449 450 dce80_timing_generator_construct(tg110, ctx, instance, offsets); 451 return &tg110->base; 452 } 453 454 static struct output_pixel_processor *dce80_opp_create( 455 struct dc_context *ctx, 456 uint32_t inst) 457 { 458 struct dce110_opp *opp = 459 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 460 461 if (!opp) 462 return NULL; 463 464 dce110_opp_construct(opp, 465 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 466 return &opp->base; 467 } 468 469 static 470 struct aux_engine *dce80_aux_engine_create( 471 struct dc_context *ctx, 472 uint32_t inst) 473 { 474 struct aux_engine_dce110 *aux_engine = 475 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 476 477 if (!aux_engine) 478 return NULL; 479 480 dce110_aux_engine_construct(aux_engine, ctx, inst, 481 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 482 &aux_engine_regs[inst]); 483 484 return &aux_engine->base; 485 } 486 487 static struct stream_encoder *dce80_stream_encoder_create( 488 enum engine_id eng_id, 489 struct dc_context *ctx) 490 { 491 struct dce110_stream_encoder *enc110 = 492 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 493 494 if (!enc110) 495 return NULL; 496 497 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 498 &stream_enc_regs[eng_id], 499 &se_shift, &se_mask); 500 return &enc110->base; 501 } 502 503 #define SRII(reg_name, block, id)\ 504 .reg_name[id] = mm ## block ## id ## _ ## reg_name 505 506 static const struct dce_hwseq_registers hwseq_reg = { 507 HWSEQ_DCE8_REG_LIST() 508 }; 509 510 static const struct dce_hwseq_shift hwseq_shift = { 511 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) 512 }; 513 514 static const struct dce_hwseq_mask hwseq_mask = { 515 HWSEQ_DCE8_MASK_SH_LIST(_MASK) 516 }; 517 518 static struct dce_hwseq *dce80_hwseq_create( 519 struct dc_context *ctx) 520 { 521 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 522 523 if (hws) { 524 hws->ctx = ctx; 525 hws->regs = &hwseq_reg; 526 hws->shifts = &hwseq_shift; 527 hws->masks = &hwseq_mask; 528 } 529 return hws; 530 } 531 532 static const struct resource_create_funcs res_create_funcs = { 533 .read_dce_straps = read_dce_straps, 534 .create_audio = create_audio, 535 .create_stream_encoder = dce80_stream_encoder_create, 536 .create_hwseq = dce80_hwseq_create, 537 }; 538 539 #define mi_inst_regs(id) { \ 540 MI_DCE8_REG_LIST(id), \ 541 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \ 542 } 543 static const struct dce_mem_input_registers mi_regs[] = { 544 mi_inst_regs(0), 545 mi_inst_regs(1), 546 mi_inst_regs(2), 547 mi_inst_regs(3), 548 mi_inst_regs(4), 549 mi_inst_regs(5), 550 }; 551 552 static const struct dce_mem_input_shift mi_shifts = { 553 MI_DCE8_MASK_SH_LIST(__SHIFT), 554 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 555 }; 556 557 static const struct dce_mem_input_mask mi_masks = { 558 MI_DCE8_MASK_SH_LIST(_MASK), 559 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 560 }; 561 562 static struct mem_input *dce80_mem_input_create( 563 struct dc_context *ctx, 564 uint32_t inst) 565 { 566 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 567 GFP_KERNEL); 568 569 if (!dce_mi) { 570 BREAK_TO_DEBUGGER(); 571 return NULL; 572 } 573 574 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 575 dce_mi->wa.single_head_rdreq_dmif_limit = 2; 576 return &dce_mi->base; 577 } 578 579 static void dce80_transform_destroy(struct transform **xfm) 580 { 581 kfree(TO_DCE_TRANSFORM(*xfm)); 582 *xfm = NULL; 583 } 584 585 static struct transform *dce80_transform_create( 586 struct dc_context *ctx, 587 uint32_t inst) 588 { 589 struct dce_transform *transform = 590 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 591 592 if (!transform) 593 return NULL; 594 595 dce_transform_construct(transform, ctx, inst, 596 &xfm_regs[inst], &xfm_shift, &xfm_mask); 597 transform->prescaler_on = false; 598 return &transform->base; 599 } 600 601 static const struct encoder_feature_support link_enc_feature = { 602 .max_hdmi_deep_color = COLOR_DEPTH_121212, 603 .max_hdmi_pixel_clock = 297000, 604 .flags.bits.IS_HBR2_CAPABLE = true, 605 .flags.bits.IS_TPS3_CAPABLE = true, 606 .flags.bits.IS_YCBCR_CAPABLE = true 607 }; 608 609 static 610 struct link_encoder *dce80_link_encoder_create( 611 const struct encoder_init_data *enc_init_data) 612 { 613 struct dce110_link_encoder *enc110 = 614 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 615 616 if (!enc110) 617 return NULL; 618 619 dce110_link_encoder_construct(enc110, 620 enc_init_data, 621 &link_enc_feature, 622 &link_enc_regs[enc_init_data->transmitter], 623 &link_enc_aux_regs[enc_init_data->channel - 1], 624 &link_enc_hpd_regs[enc_init_data->hpd_source]); 625 return &enc110->base; 626 } 627 628 static 629 struct clock_source *dce80_clock_source_create( 630 struct dc_context *ctx, 631 struct dc_bios *bios, 632 enum clock_source_id id, 633 const struct dce110_clk_src_regs *regs, 634 bool dp_clk_src) 635 { 636 struct dce110_clk_src *clk_src = 637 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 638 639 if (!clk_src) 640 return NULL; 641 642 if (dce110_clk_src_construct(clk_src, ctx, bios, id, 643 regs, &cs_shift, &cs_mask)) { 644 clk_src->base.dp_clk_src = dp_clk_src; 645 return &clk_src->base; 646 } 647 648 BREAK_TO_DEBUGGER(); 649 return NULL; 650 } 651 652 static 653 void dce80_clock_source_destroy(struct clock_source **clk_src) 654 { 655 kfree(TO_DCE110_CLK_SRC(*clk_src)); 656 *clk_src = NULL; 657 } 658 659 static struct input_pixel_processor *dce80_ipp_create( 660 struct dc_context *ctx, uint32_t inst) 661 { 662 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 663 664 if (!ipp) { 665 BREAK_TO_DEBUGGER(); 666 return NULL; 667 } 668 669 dce_ipp_construct(ipp, ctx, inst, 670 &ipp_regs[inst], &ipp_shift, &ipp_mask); 671 return &ipp->base; 672 } 673 674 static void destruct(struct dce110_resource_pool *pool) 675 { 676 unsigned int i; 677 678 for (i = 0; i < pool->base.pipe_count; i++) { 679 if (pool->base.opps[i] != NULL) 680 dce110_opp_destroy(&pool->base.opps[i]); 681 682 if (pool->base.transforms[i] != NULL) 683 dce80_transform_destroy(&pool->base.transforms[i]); 684 685 if (pool->base.ipps[i] != NULL) 686 dce_ipp_destroy(&pool->base.ipps[i]); 687 688 if (pool->base.mis[i] != NULL) { 689 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 690 pool->base.mis[i] = NULL; 691 } 692 693 if (pool->base.timing_generators[i] != NULL) { 694 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 695 pool->base.timing_generators[i] = NULL; 696 } 697 698 if (pool->base.engines[i] != NULL) 699 dce110_engine_destroy(&pool->base.engines[i]); 700 } 701 702 for (i = 0; i < pool->base.stream_enc_count; i++) { 703 if (pool->base.stream_enc[i] != NULL) 704 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 705 } 706 707 for (i = 0; i < pool->base.clk_src_count; i++) { 708 if (pool->base.clock_sources[i] != NULL) { 709 dce80_clock_source_destroy(&pool->base.clock_sources[i]); 710 } 711 } 712 713 if (pool->base.abm != NULL) 714 dce_abm_destroy(&pool->base.abm); 715 716 if (pool->base.dmcu != NULL) 717 dce_dmcu_destroy(&pool->base.dmcu); 718 719 if (pool->base.dp_clock_source != NULL) 720 dce80_clock_source_destroy(&pool->base.dp_clock_source); 721 722 for (i = 0; i < pool->base.audio_count; i++) { 723 if (pool->base.audios[i] != NULL) { 724 dce_aud_destroy(&pool->base.audios[i]); 725 } 726 } 727 728 if (pool->base.dccg != NULL) 729 dce_dccg_destroy(&pool->base.dccg); 730 731 if (pool->base.irqs != NULL) { 732 dal_irq_service_destroy(&pool->base.irqs); 733 } 734 } 735 736 static 737 bool dce80_validate_bandwidth( 738 struct dc *dc, 739 struct dc_state *context) 740 { 741 /* TODO implement when needed but for now hardcode max value*/ 742 context->bw.dce.dispclk_khz = 681000; 743 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER; 744 745 return true; 746 } 747 748 static bool dce80_validate_surface_sets( 749 struct dc_state *context) 750 { 751 int i; 752 753 for (i = 0; i < context->stream_count; i++) { 754 if (context->stream_status[i].plane_count == 0) 755 continue; 756 757 if (context->stream_status[i].plane_count > 1) 758 return false; 759 760 if (context->stream_status[i].plane_states[0]->format 761 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 762 return false; 763 } 764 765 return true; 766 } 767 768 static 769 enum dc_status dce80_validate_global( 770 struct dc *dc, 771 struct dc_state *context) 772 { 773 if (!dce80_validate_surface_sets(context)) 774 return DC_FAIL_SURFACE_VALIDATE; 775 776 return DC_OK; 777 } 778 779 static void dce80_destroy_resource_pool(struct resource_pool **pool) 780 { 781 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 782 783 destruct(dce110_pool); 784 kfree(dce110_pool); 785 *pool = NULL; 786 } 787 788 static const struct resource_funcs dce80_res_pool_funcs = { 789 .destroy = dce80_destroy_resource_pool, 790 .link_enc_create = dce80_link_encoder_create, 791 .validate_bandwidth = dce80_validate_bandwidth, 792 .validate_plane = dce100_validate_plane, 793 .add_stream_to_ctx = dce100_add_stream_to_ctx, 794 .validate_global = dce80_validate_global 795 }; 796 797 static bool dce80_construct( 798 uint8_t num_virtual_links, 799 struct dc *dc, 800 struct dce110_resource_pool *pool) 801 { 802 unsigned int i; 803 struct dc_context *ctx = dc->ctx; 804 struct dc_firmware_info info; 805 struct dc_bios *bp; 806 struct dm_pp_static_clock_info static_clk_info = {0}; 807 808 ctx->dc_bios->regs = &bios_regs; 809 810 pool->base.res_cap = &res_cap; 811 pool->base.funcs = &dce80_res_pool_funcs; 812 813 814 /************************************************* 815 * Resource + asic cap harcoding * 816 *************************************************/ 817 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 818 pool->base.pipe_count = res_cap.num_timing_generator; 819 pool->base.timing_generator_count = res_cap.num_timing_generator; 820 dc->caps.max_downscale_ratio = 200; 821 dc->caps.i2c_speed_in_khz = 40; 822 dc->caps.max_cursor_size = 128; 823 dc->caps.dual_link_dvi = true; 824 825 /************************************************* 826 * Create resources * 827 *************************************************/ 828 829 bp = ctx->dc_bios; 830 831 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 832 info.external_clock_source_frequency_for_dp != 0) { 833 pool->base.dp_clock_source = 834 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 835 836 pool->base.clock_sources[0] = 837 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 838 pool->base.clock_sources[1] = 839 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 840 pool->base.clock_sources[2] = 841 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 842 pool->base.clk_src_count = 3; 843 844 } else { 845 pool->base.dp_clock_source = 846 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 847 848 pool->base.clock_sources[0] = 849 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 850 pool->base.clock_sources[1] = 851 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 852 pool->base.clk_src_count = 2; 853 } 854 855 if (pool->base.dp_clock_source == NULL) { 856 dm_error("DC: failed to create dp clock source!\n"); 857 BREAK_TO_DEBUGGER(); 858 goto res_create_fail; 859 } 860 861 for (i = 0; i < pool->base.clk_src_count; i++) { 862 if (pool->base.clock_sources[i] == NULL) { 863 dm_error("DC: failed to create clock sources!\n"); 864 BREAK_TO_DEBUGGER(); 865 goto res_create_fail; 866 } 867 } 868 869 pool->base.dccg = dce_dccg_create(ctx, 870 &disp_clk_regs, 871 &disp_clk_shift, 872 &disp_clk_mask); 873 if (pool->base.dccg == NULL) { 874 dm_error("DC: failed to create display clock!\n"); 875 BREAK_TO_DEBUGGER(); 876 goto res_create_fail; 877 } 878 879 pool->base.dmcu = dce_dmcu_create(ctx, 880 &dmcu_regs, 881 &dmcu_shift, 882 &dmcu_mask); 883 if (pool->base.dmcu == NULL) { 884 dm_error("DC: failed to create dmcu!\n"); 885 BREAK_TO_DEBUGGER(); 886 goto res_create_fail; 887 } 888 889 pool->base.abm = dce_abm_create(ctx, 890 &abm_regs, 891 &abm_shift, 892 &abm_mask); 893 if (pool->base.abm == NULL) { 894 dm_error("DC: failed to create abm!\n"); 895 BREAK_TO_DEBUGGER(); 896 goto res_create_fail; 897 } 898 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 899 pool->base.dccg->max_clks_state = 900 static_clk_info.max_clocks_state; 901 902 { 903 struct irq_service_init_data init_data; 904 init_data.ctx = dc->ctx; 905 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 906 if (!pool->base.irqs) 907 goto res_create_fail; 908 } 909 910 for (i = 0; i < pool->base.pipe_count; i++) { 911 pool->base.timing_generators[i] = dce80_timing_generator_create( 912 ctx, i, &dce80_tg_offsets[i]); 913 if (pool->base.timing_generators[i] == NULL) { 914 BREAK_TO_DEBUGGER(); 915 dm_error("DC: failed to create tg!\n"); 916 goto res_create_fail; 917 } 918 919 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 920 if (pool->base.mis[i] == NULL) { 921 BREAK_TO_DEBUGGER(); 922 dm_error("DC: failed to create memory input!\n"); 923 goto res_create_fail; 924 } 925 926 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 927 if (pool->base.ipps[i] == NULL) { 928 BREAK_TO_DEBUGGER(); 929 dm_error("DC: failed to create input pixel processor!\n"); 930 goto res_create_fail; 931 } 932 933 pool->base.transforms[i] = dce80_transform_create(ctx, i); 934 if (pool->base.transforms[i] == NULL) { 935 BREAK_TO_DEBUGGER(); 936 dm_error("DC: failed to create transform!\n"); 937 goto res_create_fail; 938 } 939 940 pool->base.opps[i] = dce80_opp_create(ctx, i); 941 if (pool->base.opps[i] == NULL) { 942 BREAK_TO_DEBUGGER(); 943 dm_error("DC: failed to create output pixel processor!\n"); 944 goto res_create_fail; 945 } 946 947 pool->base.engines[i] = dce80_aux_engine_create(ctx, i); 948 if (pool->base.engines[i] == NULL) { 949 BREAK_TO_DEBUGGER(); 950 dm_error( 951 "DC:failed to create aux engine!!\n"); 952 goto res_create_fail; 953 } 954 } 955 956 dc->caps.max_planes = pool->base.pipe_count; 957 dc->caps.disable_dp_clk_share = true; 958 959 if (!resource_construct(num_virtual_links, dc, &pool->base, 960 &res_create_funcs)) 961 goto res_create_fail; 962 963 /* Create hardware sequencer */ 964 dce80_hw_sequencer_construct(dc); 965 966 return true; 967 968 res_create_fail: 969 destruct(pool); 970 return false; 971 } 972 973 struct resource_pool *dce80_create_resource_pool( 974 uint8_t num_virtual_links, 975 struct dc *dc) 976 { 977 struct dce110_resource_pool *pool = 978 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 979 980 if (!pool) 981 return NULL; 982 983 if (dce80_construct(num_virtual_links, dc, pool)) 984 return &pool->base; 985 986 BREAK_TO_DEBUGGER(); 987 return NULL; 988 } 989 990 static bool dce81_construct( 991 uint8_t num_virtual_links, 992 struct dc *dc, 993 struct dce110_resource_pool *pool) 994 { 995 unsigned int i; 996 struct dc_context *ctx = dc->ctx; 997 struct dc_firmware_info info; 998 struct dc_bios *bp; 999 struct dm_pp_static_clock_info static_clk_info = {0}; 1000 1001 ctx->dc_bios->regs = &bios_regs; 1002 1003 pool->base.res_cap = &res_cap_81; 1004 pool->base.funcs = &dce80_res_pool_funcs; 1005 1006 1007 /************************************************* 1008 * Resource + asic cap harcoding * 1009 *************************************************/ 1010 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1011 pool->base.pipe_count = res_cap_81.num_timing_generator; 1012 pool->base.timing_generator_count = res_cap_81.num_timing_generator; 1013 dc->caps.max_downscale_ratio = 200; 1014 dc->caps.i2c_speed_in_khz = 40; 1015 dc->caps.max_cursor_size = 128; 1016 dc->caps.is_apu = true; 1017 1018 /************************************************* 1019 * Create resources * 1020 *************************************************/ 1021 1022 bp = ctx->dc_bios; 1023 1024 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1025 info.external_clock_source_frequency_for_dp != 0) { 1026 pool->base.dp_clock_source = 1027 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1028 1029 pool->base.clock_sources[0] = 1030 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false); 1031 pool->base.clock_sources[1] = 1032 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1033 pool->base.clock_sources[2] = 1034 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1035 pool->base.clk_src_count = 3; 1036 1037 } else { 1038 pool->base.dp_clock_source = 1039 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true); 1040 1041 pool->base.clock_sources[0] = 1042 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false); 1043 pool->base.clock_sources[1] = 1044 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false); 1045 pool->base.clk_src_count = 2; 1046 } 1047 1048 if (pool->base.dp_clock_source == NULL) { 1049 dm_error("DC: failed to create dp clock source!\n"); 1050 BREAK_TO_DEBUGGER(); 1051 goto res_create_fail; 1052 } 1053 1054 for (i = 0; i < pool->base.clk_src_count; i++) { 1055 if (pool->base.clock_sources[i] == NULL) { 1056 dm_error("DC: failed to create clock sources!\n"); 1057 BREAK_TO_DEBUGGER(); 1058 goto res_create_fail; 1059 } 1060 } 1061 1062 pool->base.dccg = dce_dccg_create(ctx, 1063 &disp_clk_regs, 1064 &disp_clk_shift, 1065 &disp_clk_mask); 1066 if (pool->base.dccg == NULL) { 1067 dm_error("DC: failed to create display clock!\n"); 1068 BREAK_TO_DEBUGGER(); 1069 goto res_create_fail; 1070 } 1071 1072 pool->base.dmcu = dce_dmcu_create(ctx, 1073 &dmcu_regs, 1074 &dmcu_shift, 1075 &dmcu_mask); 1076 if (pool->base.dmcu == NULL) { 1077 dm_error("DC: failed to create dmcu!\n"); 1078 BREAK_TO_DEBUGGER(); 1079 goto res_create_fail; 1080 } 1081 1082 pool->base.abm = dce_abm_create(ctx, 1083 &abm_regs, 1084 &abm_shift, 1085 &abm_mask); 1086 if (pool->base.abm == NULL) { 1087 dm_error("DC: failed to create abm!\n"); 1088 BREAK_TO_DEBUGGER(); 1089 goto res_create_fail; 1090 } 1091 1092 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1093 pool->base.dccg->max_clks_state = 1094 static_clk_info.max_clocks_state; 1095 1096 { 1097 struct irq_service_init_data init_data; 1098 init_data.ctx = dc->ctx; 1099 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1100 if (!pool->base.irqs) 1101 goto res_create_fail; 1102 } 1103 1104 for (i = 0; i < pool->base.pipe_count; i++) { 1105 pool->base.timing_generators[i] = dce80_timing_generator_create( 1106 ctx, i, &dce80_tg_offsets[i]); 1107 if (pool->base.timing_generators[i] == NULL) { 1108 BREAK_TO_DEBUGGER(); 1109 dm_error("DC: failed to create tg!\n"); 1110 goto res_create_fail; 1111 } 1112 1113 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1114 if (pool->base.mis[i] == NULL) { 1115 BREAK_TO_DEBUGGER(); 1116 dm_error("DC: failed to create memory input!\n"); 1117 goto res_create_fail; 1118 } 1119 1120 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1121 if (pool->base.ipps[i] == NULL) { 1122 BREAK_TO_DEBUGGER(); 1123 dm_error("DC: failed to create input pixel processor!\n"); 1124 goto res_create_fail; 1125 } 1126 1127 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1128 if (pool->base.transforms[i] == NULL) { 1129 BREAK_TO_DEBUGGER(); 1130 dm_error("DC: failed to create transform!\n"); 1131 goto res_create_fail; 1132 } 1133 1134 pool->base.opps[i] = dce80_opp_create(ctx, i); 1135 if (pool->base.opps[i] == NULL) { 1136 BREAK_TO_DEBUGGER(); 1137 dm_error("DC: failed to create output pixel processor!\n"); 1138 goto res_create_fail; 1139 } 1140 } 1141 1142 dc->caps.max_planes = pool->base.pipe_count; 1143 dc->caps.disable_dp_clk_share = true; 1144 1145 if (!resource_construct(num_virtual_links, dc, &pool->base, 1146 &res_create_funcs)) 1147 goto res_create_fail; 1148 1149 /* Create hardware sequencer */ 1150 dce80_hw_sequencer_construct(dc); 1151 1152 return true; 1153 1154 res_create_fail: 1155 destruct(pool); 1156 return false; 1157 } 1158 1159 struct resource_pool *dce81_create_resource_pool( 1160 uint8_t num_virtual_links, 1161 struct dc *dc) 1162 { 1163 struct dce110_resource_pool *pool = 1164 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1165 1166 if (!pool) 1167 return NULL; 1168 1169 if (dce81_construct(num_virtual_links, dc, pool)) 1170 return &pool->base; 1171 1172 BREAK_TO_DEBUGGER(); 1173 return NULL; 1174 } 1175 1176 static bool dce83_construct( 1177 uint8_t num_virtual_links, 1178 struct dc *dc, 1179 struct dce110_resource_pool *pool) 1180 { 1181 unsigned int i; 1182 struct dc_context *ctx = dc->ctx; 1183 struct dc_firmware_info info; 1184 struct dc_bios *bp; 1185 struct dm_pp_static_clock_info static_clk_info = {0}; 1186 1187 ctx->dc_bios->regs = &bios_regs; 1188 1189 pool->base.res_cap = &res_cap_83; 1190 pool->base.funcs = &dce80_res_pool_funcs; 1191 1192 1193 /************************************************* 1194 * Resource + asic cap harcoding * 1195 *************************************************/ 1196 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1197 pool->base.pipe_count = res_cap_83.num_timing_generator; 1198 pool->base.timing_generator_count = res_cap_83.num_timing_generator; 1199 dc->caps.max_downscale_ratio = 200; 1200 dc->caps.i2c_speed_in_khz = 40; 1201 dc->caps.max_cursor_size = 128; 1202 dc->caps.is_apu = true; 1203 1204 /************************************************* 1205 * Create resources * 1206 *************************************************/ 1207 1208 bp = ctx->dc_bios; 1209 1210 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) && 1211 info.external_clock_source_frequency_for_dp != 0) { 1212 pool->base.dp_clock_source = 1213 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true); 1214 1215 pool->base.clock_sources[0] = 1216 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false); 1217 pool->base.clock_sources[1] = 1218 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1219 pool->base.clk_src_count = 2; 1220 1221 } else { 1222 pool->base.dp_clock_source = 1223 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true); 1224 1225 pool->base.clock_sources[0] = 1226 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false); 1227 pool->base.clk_src_count = 1; 1228 } 1229 1230 if (pool->base.dp_clock_source == NULL) { 1231 dm_error("DC: failed to create dp clock source!\n"); 1232 BREAK_TO_DEBUGGER(); 1233 goto res_create_fail; 1234 } 1235 1236 for (i = 0; i < pool->base.clk_src_count; i++) { 1237 if (pool->base.clock_sources[i] == NULL) { 1238 dm_error("DC: failed to create clock sources!\n"); 1239 BREAK_TO_DEBUGGER(); 1240 goto res_create_fail; 1241 } 1242 } 1243 1244 pool->base.dccg = dce_dccg_create(ctx, 1245 &disp_clk_regs, 1246 &disp_clk_shift, 1247 &disp_clk_mask); 1248 if (pool->base.dccg == NULL) { 1249 dm_error("DC: failed to create display clock!\n"); 1250 BREAK_TO_DEBUGGER(); 1251 goto res_create_fail; 1252 } 1253 1254 pool->base.dmcu = dce_dmcu_create(ctx, 1255 &dmcu_regs, 1256 &dmcu_shift, 1257 &dmcu_mask); 1258 if (pool->base.dmcu == NULL) { 1259 dm_error("DC: failed to create dmcu!\n"); 1260 BREAK_TO_DEBUGGER(); 1261 goto res_create_fail; 1262 } 1263 1264 pool->base.abm = dce_abm_create(ctx, 1265 &abm_regs, 1266 &abm_shift, 1267 &abm_mask); 1268 if (pool->base.abm == NULL) { 1269 dm_error("DC: failed to create abm!\n"); 1270 BREAK_TO_DEBUGGER(); 1271 goto res_create_fail; 1272 } 1273 1274 if (dm_pp_get_static_clocks(ctx, &static_clk_info)) 1275 pool->base.dccg->max_clks_state = 1276 static_clk_info.max_clocks_state; 1277 1278 { 1279 struct irq_service_init_data init_data; 1280 init_data.ctx = dc->ctx; 1281 pool->base.irqs = dal_irq_service_dce80_create(&init_data); 1282 if (!pool->base.irqs) 1283 goto res_create_fail; 1284 } 1285 1286 for (i = 0; i < pool->base.pipe_count; i++) { 1287 pool->base.timing_generators[i] = dce80_timing_generator_create( 1288 ctx, i, &dce80_tg_offsets[i]); 1289 if (pool->base.timing_generators[i] == NULL) { 1290 BREAK_TO_DEBUGGER(); 1291 dm_error("DC: failed to create tg!\n"); 1292 goto res_create_fail; 1293 } 1294 1295 pool->base.mis[i] = dce80_mem_input_create(ctx, i); 1296 if (pool->base.mis[i] == NULL) { 1297 BREAK_TO_DEBUGGER(); 1298 dm_error("DC: failed to create memory input!\n"); 1299 goto res_create_fail; 1300 } 1301 1302 pool->base.ipps[i] = dce80_ipp_create(ctx, i); 1303 if (pool->base.ipps[i] == NULL) { 1304 BREAK_TO_DEBUGGER(); 1305 dm_error("DC: failed to create input pixel processor!\n"); 1306 goto res_create_fail; 1307 } 1308 1309 pool->base.transforms[i] = dce80_transform_create(ctx, i); 1310 if (pool->base.transforms[i] == NULL) { 1311 BREAK_TO_DEBUGGER(); 1312 dm_error("DC: failed to create transform!\n"); 1313 goto res_create_fail; 1314 } 1315 1316 pool->base.opps[i] = dce80_opp_create(ctx, i); 1317 if (pool->base.opps[i] == NULL) { 1318 BREAK_TO_DEBUGGER(); 1319 dm_error("DC: failed to create output pixel processor!\n"); 1320 goto res_create_fail; 1321 } 1322 } 1323 1324 dc->caps.max_planes = pool->base.pipe_count; 1325 dc->caps.disable_dp_clk_share = true; 1326 1327 if (!resource_construct(num_virtual_links, dc, &pool->base, 1328 &res_create_funcs)) 1329 goto res_create_fail; 1330 1331 /* Create hardware sequencer */ 1332 dce80_hw_sequencer_construct(dc); 1333 1334 return true; 1335 1336 res_create_fail: 1337 destruct(pool); 1338 return false; 1339 } 1340 1341 struct resource_pool *dce83_create_resource_pool( 1342 uint8_t num_virtual_links, 1343 struct dc *dc) 1344 { 1345 struct dce110_resource_pool *pool = 1346 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1347 1348 if (!pool) 1349 return NULL; 1350 1351 if (dce83_construct(num_virtual_links, dc, pool)) 1352 return &pool->base; 1353 1354 BREAK_TO_DEBUGGER(); 1355 return NULL; 1356 } 1357