1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 #include "core_types.h" 29 30 #include "reg_helper.h" 31 #include "dcn10_dpp.h" 32 #include "basics/conversion.h" 33 34 35 #define NUM_PHASES 64 36 #define HORZ_MAX_TAPS 8 37 #define VERT_MAX_TAPS 8 38 39 #define BLACK_OFFSET_RGB_Y 0x0 40 #define BLACK_OFFSET_CBCR 0x8000 41 42 #define REG(reg)\ 43 dpp->tf_regs->reg 44 45 #define CTX \ 46 dpp->base.ctx 47 48 #undef FN 49 #define FN(reg_name, field_name) \ 50 dpp->tf_shift->field_name, dpp->tf_mask->field_name 51 52 enum dcn10_coef_filter_type_sel { 53 SCL_COEF_LUMA_VERT_FILTER = 0, 54 SCL_COEF_LUMA_HORZ_FILTER = 1, 55 SCL_COEF_CHROMA_VERT_FILTER = 2, 56 SCL_COEF_CHROMA_HORZ_FILTER = 3, 57 SCL_COEF_ALPHA_VERT_FILTER = 4, 58 SCL_COEF_ALPHA_HORZ_FILTER = 5 59 }; 60 61 enum dscl_autocal_mode { 62 AUTOCAL_MODE_OFF = 0, 63 64 /* Autocal calculate the scaling ratio and initial phase and the 65 * DSCL_MODE_SEL must be set to 1 66 */ 67 AUTOCAL_MODE_AUTOSCALE = 1, 68 /* Autocal perform auto centering without replication and the 69 * DSCL_MODE_SEL must be set to 0 70 */ 71 AUTOCAL_MODE_AUTOCENTER = 2, 72 /* Autocal perform auto centering and auto replication and the 73 * DSCL_MODE_SEL must be set to 0 74 */ 75 AUTOCAL_MODE_AUTOREPLICATE = 3 76 }; 77 78 enum dscl_mode_sel { 79 DSCL_MODE_SCALING_444_BYPASS = 0, 80 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 81 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 82 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 83 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 84 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 85 DSCL_MODE_DSCL_BYPASS = 6 86 }; 87 88 #if 0 89 static void dpp1_dscl_set_overscan( 90 struct dcn10_dpp *dpp, 91 const struct scaler_data *data) 92 { 93 uint32_t left = data->recout.x; 94 uint32_t top = data->recout.y; 95 96 int right = data->h_active - data->recout.x - data->recout.width; 97 int bottom = data->v_active - data->recout.y - data->recout.height; 98 99 if (right < 0) { 100 BREAK_TO_DEBUGGER(); 101 right = 0; 102 } 103 if (bottom < 0) { 104 BREAK_TO_DEBUGGER(); 105 bottom = 0; 106 } 107 108 REG_SET_2(DSCL_EXT_OVERSCAN_LEFT_RIGHT, 0, 109 EXT_OVERSCAN_LEFT, left, 110 EXT_OVERSCAN_RIGHT, right); 111 112 REG_SET_2(DSCL_EXT_OVERSCAN_TOP_BOTTOM, 0, 113 EXT_OVERSCAN_BOTTOM, bottom, 114 EXT_OVERSCAN_TOP, top); 115 } 116 117 static void dpp1_dscl_set_otg_blank( 118 struct dcn10_dpp *dpp, const struct scaler_data *data) 119 { 120 uint32_t h_blank_start = data->h_active; 121 uint32_t h_blank_end = 0; 122 uint32_t v_blank_start = data->v_active; 123 uint32_t v_blank_end = 0; 124 125 REG_SET_2(OTG_H_BLANK, 0, 126 OTG_H_BLANK_START, h_blank_start, 127 OTG_H_BLANK_END, h_blank_end); 128 129 REG_SET_2(OTG_V_BLANK, 0, 130 OTG_V_BLANK_START, v_blank_start, 131 OTG_V_BLANK_END, v_blank_end); 132 } 133 #endif 134 135 static int dpp1_dscl_get_pixel_depth_val(enum lb_pixel_depth depth) 136 { 137 if (depth == LB_PIXEL_DEPTH_30BPP) 138 return 0; /* 10 bpc */ 139 else if (depth == LB_PIXEL_DEPTH_24BPP) 140 return 1; /* 8 bpc */ 141 else if (depth == LB_PIXEL_DEPTH_18BPP) 142 return 2; /* 6 bpc */ 143 else if (depth == LB_PIXEL_DEPTH_36BPP) 144 return 3; /* 12 bpc */ 145 else { 146 ASSERT(0); 147 return -1; /* Unsupported */ 148 } 149 } 150 151 static bool dpp1_dscl_is_video_format(enum pixel_format format) 152 { 153 if (format >= PIXEL_FORMAT_VIDEO_BEGIN 154 && format <= PIXEL_FORMAT_VIDEO_END) 155 return true; 156 else 157 return false; 158 } 159 160 static bool dpp1_dscl_is_420_format(enum pixel_format format) 161 { 162 if (format == PIXEL_FORMAT_420BPP8 || 163 format == PIXEL_FORMAT_420BPP10) 164 return true; 165 else 166 return false; 167 } 168 169 static enum dscl_mode_sel dpp1_dscl_get_dscl_mode( 170 struct dpp *dpp_base, 171 const struct scaler_data *data, 172 bool dbg_always_scale) 173 { 174 const long long one = dc_fixpt_one.value; 175 176 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 177 /* DSCL is processing data in fixed format */ 178 if (data->format == PIXEL_FORMAT_FP16) 179 return DSCL_MODE_DSCL_BYPASS; 180 } 181 182 if (data->ratios.horz.value == one 183 && data->ratios.vert.value == one 184 && data->ratios.horz_c.value == one 185 && data->ratios.vert_c.value == one 186 && !dbg_always_scale) 187 return DSCL_MODE_SCALING_444_BYPASS; 188 189 if (!dpp1_dscl_is_420_format(data->format)) { 190 if (dpp1_dscl_is_video_format(data->format)) 191 return DSCL_MODE_SCALING_444_YCBCR_ENABLE; 192 else 193 return DSCL_MODE_SCALING_444_RGB_ENABLE; 194 } 195 if (data->ratios.horz.value == one && data->ratios.vert.value == one) 196 return DSCL_MODE_SCALING_420_LUMA_BYPASS; 197 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) 198 return DSCL_MODE_SCALING_420_CHROMA_BYPASS; 199 200 return DSCL_MODE_SCALING_420_YCBCR_ENABLE; 201 } 202 203 static void dpp1_dscl_set_lb( 204 struct dcn10_dpp *dpp, 205 const struct line_buffer_params *lb_params, 206 enum lb_memory_config mem_size_config) 207 { 208 /* LB */ 209 if (dpp->base.caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { 210 /* DSCL caps: pixel data processed in fixed format */ 211 uint32_t pixel_depth = dpp1_dscl_get_pixel_depth_val(lb_params->depth); 212 uint32_t dyn_pix_depth = lb_params->dynamic_pixel_depth; 213 214 REG_SET_7(LB_DATA_FORMAT, 0, 215 PIXEL_DEPTH, pixel_depth, /* Pixel depth stored in LB */ 216 PIXEL_EXPAN_MODE, lb_params->pixel_expan_mode, /* Pixel expansion mode */ 217 PIXEL_REDUCE_MODE, 1, /* Pixel reduction mode: Rounding */ 218 DYNAMIC_PIXEL_DEPTH, dyn_pix_depth, /* Dynamic expansion pixel depth */ 219 DITHER_EN, 0, /* Dithering enable: Disabled */ 220 INTERLEAVE_EN, lb_params->interleave_en, /* Interleave source enable */ 221 LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /* Alpha enable */ 222 } 223 224 REG_SET_2(LB_MEMORY_CTRL, 0, 225 MEMORY_CONFIG, mem_size_config, 226 LB_MAX_PARTITIONS, 63); 227 } 228 229 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) 230 { 231 if (taps == 8) 232 return get_filter_8tap_64p(ratio); 233 else if (taps == 7) 234 return get_filter_7tap_64p(ratio); 235 else if (taps == 6) 236 return get_filter_6tap_64p(ratio); 237 else if (taps == 5) 238 return get_filter_5tap_64p(ratio); 239 else if (taps == 4) 240 return get_filter_4tap_64p(ratio); 241 else if (taps == 3) 242 return get_filter_3tap_64p(ratio); 243 else if (taps == 2) 244 return get_filter_2tap_64p(); 245 else if (taps == 1) 246 return NULL; 247 else { 248 /* should never happen, bug */ 249 BREAK_TO_DEBUGGER(); 250 return NULL; 251 } 252 } 253 254 static void dpp1_dscl_set_scaler_filter( 255 struct dcn10_dpp *dpp, 256 uint32_t taps, 257 enum dcn10_coef_filter_type_sel filter_type, 258 const uint16_t *filter) 259 { 260 const int tap_pairs = (taps + 1) / 2; 261 int phase; 262 int pair; 263 uint16_t odd_coef, even_coef; 264 265 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, 266 SCL_COEF_RAM_TAP_PAIR_IDX, 0, 267 SCL_COEF_RAM_PHASE, 0, 268 SCL_COEF_RAM_FILTER_TYPE, filter_type); 269 270 for (phase = 0; phase < (NUM_PHASES / 2 + 1); phase++) { 271 for (pair = 0; pair < tap_pairs; pair++) { 272 even_coef = filter[phase * taps + 2 * pair]; 273 if ((pair * 2 + 1) < taps) 274 odd_coef = filter[phase * taps + 2 * pair + 1]; 275 else 276 odd_coef = 0; 277 278 REG_SET_4(SCL_COEF_RAM_TAP_DATA, 0, 279 /* Even tap coefficient (bits 1:0 fixed to 0) */ 280 SCL_COEF_RAM_EVEN_TAP_COEF, even_coef, 281 /* Write/read control for even coefficient */ 282 SCL_COEF_RAM_EVEN_TAP_COEF_EN, 1, 283 /* Odd tap coefficient (bits 1:0 fixed to 0) */ 284 SCL_COEF_RAM_ODD_TAP_COEF, odd_coef, 285 /* Write/read control for odd coefficient */ 286 SCL_COEF_RAM_ODD_TAP_COEF_EN, 1); 287 } 288 } 289 290 } 291 292 static void dpp1_dscl_set_scl_filter( 293 struct dcn10_dpp *dpp, 294 const struct scaler_data *scl_data, 295 bool chroma_coef_mode) 296 { 297 bool h_2tap_hardcode_coef_en = false; 298 bool v_2tap_hardcode_coef_en = false; 299 bool h_2tap_sharp_en = false; 300 bool v_2tap_sharp_en = false; 301 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; 302 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; 303 bool coef_ram_current; 304 const uint16_t *filter_h = NULL; 305 const uint16_t *filter_v = NULL; 306 const uint16_t *filter_h_c = NULL; 307 const uint16_t *filter_v_c = NULL; 308 309 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 310 && scl_data->taps.h_taps_c < 3 311 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); 312 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 313 && scl_data->taps.v_taps_c < 3 314 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); 315 316 h_2tap_sharp_en = h_2tap_hardcode_coef_en && h_2tap_sharp_factor != 0; 317 v_2tap_sharp_en = v_2tap_hardcode_coef_en && v_2tap_sharp_factor != 0; 318 319 REG_UPDATE_6(DSCL_2TAP_CONTROL, 320 SCL_H_2TAP_HARDCODE_COEF_EN, h_2tap_hardcode_coef_en, 321 SCL_H_2TAP_SHARP_EN, h_2tap_sharp_en, 322 SCL_H_2TAP_SHARP_FACTOR, h_2tap_sharp_factor, 323 SCL_V_2TAP_HARDCODE_COEF_EN, v_2tap_hardcode_coef_en, 324 SCL_V_2TAP_SHARP_EN, v_2tap_sharp_en, 325 SCL_V_2TAP_SHARP_FACTOR, v_2tap_sharp_factor); 326 327 if (!v_2tap_hardcode_coef_en || !h_2tap_hardcode_coef_en) { 328 bool filter_updated = false; 329 330 filter_h = dpp1_dscl_get_filter_coeffs_64p( 331 scl_data->taps.h_taps, scl_data->ratios.horz); 332 filter_v = dpp1_dscl_get_filter_coeffs_64p( 333 scl_data->taps.v_taps, scl_data->ratios.vert); 334 335 filter_updated = (filter_h && (filter_h != dpp->filter_h)) 336 || (filter_v && (filter_v != dpp->filter_v)); 337 338 if (chroma_coef_mode) { 339 filter_h_c = dpp1_dscl_get_filter_coeffs_64p( 340 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); 341 filter_v_c = dpp1_dscl_get_filter_coeffs_64p( 342 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); 343 filter_updated = filter_updated || (filter_h_c && (filter_h_c != dpp->filter_h_c)) 344 || (filter_v_c && (filter_v_c != dpp->filter_v_c)); 345 } 346 347 if (filter_updated) { 348 uint32_t scl_mode = REG_READ(SCL_MODE); 349 350 if (!h_2tap_hardcode_coef_en && filter_h) { 351 dpp1_dscl_set_scaler_filter( 352 dpp, scl_data->taps.h_taps, 353 SCL_COEF_LUMA_HORZ_FILTER, filter_h); 354 } 355 dpp->filter_h = filter_h; 356 if (!v_2tap_hardcode_coef_en && filter_v) { 357 dpp1_dscl_set_scaler_filter( 358 dpp, scl_data->taps.v_taps, 359 SCL_COEF_LUMA_VERT_FILTER, filter_v); 360 } 361 dpp->filter_v = filter_v; 362 if (chroma_coef_mode) { 363 if (!h_2tap_hardcode_coef_en && filter_h_c) { 364 dpp1_dscl_set_scaler_filter( 365 dpp, scl_data->taps.h_taps_c, 366 SCL_COEF_CHROMA_HORZ_FILTER, filter_h_c); 367 } 368 if (!v_2tap_hardcode_coef_en && filter_v_c) { 369 dpp1_dscl_set_scaler_filter( 370 dpp, scl_data->taps.v_taps_c, 371 SCL_COEF_CHROMA_VERT_FILTER, filter_v_c); 372 } 373 } 374 dpp->filter_h_c = filter_h_c; 375 dpp->filter_v_c = filter_v_c; 376 377 coef_ram_current = get_reg_field_value_ex( 378 scl_mode, dpp->tf_mask->SCL_COEF_RAM_SELECT_CURRENT, 379 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); 380 381 /* Swap coefficient RAM and set chroma coefficient mode */ 382 REG_SET_2(SCL_MODE, scl_mode, 383 SCL_COEF_RAM_SELECT, !coef_ram_current, 384 SCL_CHROMA_COEF_MODE, chroma_coef_mode); 385 } 386 } 387 } 388 389 static int dpp1_dscl_get_lb_depth_bpc(enum lb_pixel_depth depth) 390 { 391 if (depth == LB_PIXEL_DEPTH_30BPP) 392 return 10; 393 else if (depth == LB_PIXEL_DEPTH_24BPP) 394 return 8; 395 else if (depth == LB_PIXEL_DEPTH_18BPP) 396 return 6; 397 else if (depth == LB_PIXEL_DEPTH_36BPP) 398 return 12; 399 else { 400 BREAK_TO_DEBUGGER(); 401 return -1; /* Unsupported */ 402 } 403 } 404 405 void dpp1_dscl_calc_lb_num_partitions( 406 const struct scaler_data *scl_data, 407 enum lb_memory_config lb_config, 408 int *num_part_y, 409 int *num_part_c) 410 { 411 int lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a, 412 lb_bpc, memory_line_size_y, memory_line_size_c, memory_line_size_a; 413 414 int line_size = scl_data->viewport.width < scl_data->recout.width ? 415 scl_data->viewport.width : scl_data->recout.width; 416 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? 417 scl_data->viewport_c.width : scl_data->recout.width; 418 419 if (line_size == 0) 420 line_size = 1; 421 422 if (line_size_c == 0) 423 line_size_c = 1; 424 425 426 lb_bpc = dpp1_dscl_get_lb_depth_bpc(scl_data->lb_params.depth); 427 memory_line_size_y = (line_size * lb_bpc + 71) / 72; /* +71 to ceil */ 428 memory_line_size_c = (line_size_c * lb_bpc + 71) / 72; /* +71 to ceil */ 429 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */ 430 431 if (lb_config == LB_MEMORY_CONFIG_1) { 432 lb_memory_size = 816; 433 lb_memory_size_c = 816; 434 lb_memory_size_a = 984; 435 } else if (lb_config == LB_MEMORY_CONFIG_2) { 436 lb_memory_size = 1088; 437 lb_memory_size_c = 1088; 438 lb_memory_size_a = 1312; 439 } else if (lb_config == LB_MEMORY_CONFIG_3) { 440 /* 420 mode: using 3rd mem from Y, Cr and Cb */ 441 lb_memory_size = 816 + 1088 + 848 + 848 + 848; 442 lb_memory_size_c = 816 + 1088; 443 lb_memory_size_a = 984 + 1312 + 456; 444 } else { 445 lb_memory_size = 816 + 1088 + 848; 446 lb_memory_size_c = 816 + 1088 + 848; 447 lb_memory_size_a = 984 + 1312 + 456; 448 } 449 *num_part_y = lb_memory_size / memory_line_size_y; 450 *num_part_c = lb_memory_size_c / memory_line_size_c; 451 num_partitions_a = lb_memory_size_a / memory_line_size_a; 452 453 if (scl_data->lb_params.alpha_en 454 && (num_partitions_a < *num_part_y)) 455 *num_part_y = num_partitions_a; 456 457 if (*num_part_y > 64) 458 *num_part_y = 64; 459 if (*num_part_c > 64) 460 *num_part_c = 64; 461 462 } 463 464 bool dpp1_dscl_is_lb_conf_valid(int ceil_vratio, int num_partitions, int vtaps) 465 { 466 if (ceil_vratio > 2) 467 return vtaps <= (num_partitions - ceil_vratio + 2); 468 else 469 return vtaps <= num_partitions; 470 } 471 472 /*find first match configuration which meets the min required lb size*/ 473 static enum lb_memory_config dpp1_dscl_find_lb_memory_config(struct dcn10_dpp *dpp, 474 const struct scaler_data *scl_data) 475 { 476 int num_part_y, num_part_c; 477 int vtaps = scl_data->taps.v_taps; 478 int vtaps_c = scl_data->taps.v_taps_c; 479 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); 480 int ceil_vratio_c = dc_fixpt_ceil(scl_data->ratios.vert_c); 481 482 if (dpp->base.ctx->dc->debug.use_max_lb) { 483 if (scl_data->format == PIXEL_FORMAT_420BPP8 484 || scl_data->format == PIXEL_FORMAT_420BPP10) 485 return LB_MEMORY_CONFIG_3; 486 return LB_MEMORY_CONFIG_0; 487 } 488 489 dpp->base.caps->dscl_calc_lb_num_partitions( 490 scl_data, LB_MEMORY_CONFIG_1, &num_part_y, &num_part_c); 491 492 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 493 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 494 return LB_MEMORY_CONFIG_1; 495 496 dpp->base.caps->dscl_calc_lb_num_partitions( 497 scl_data, LB_MEMORY_CONFIG_2, &num_part_y, &num_part_c); 498 499 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 500 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 501 return LB_MEMORY_CONFIG_2; 502 503 if (scl_data->format == PIXEL_FORMAT_420BPP8 504 || scl_data->format == PIXEL_FORMAT_420BPP10) { 505 dpp->base.caps->dscl_calc_lb_num_partitions( 506 scl_data, LB_MEMORY_CONFIG_3, &num_part_y, &num_part_c); 507 508 if (dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 509 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)) 510 return LB_MEMORY_CONFIG_3; 511 } 512 513 dpp->base.caps->dscl_calc_lb_num_partitions( 514 scl_data, LB_MEMORY_CONFIG_0, &num_part_y, &num_part_c); 515 516 /*Ensure we can support the requested number of vtaps*/ 517 ASSERT(dpp1_dscl_is_lb_conf_valid(ceil_vratio, num_part_y, vtaps) 518 && dpp1_dscl_is_lb_conf_valid(ceil_vratio_c, num_part_c, vtaps_c)); 519 520 return LB_MEMORY_CONFIG_0; 521 } 522 523 #if 0 524 void dpp1_dscl_set_scaler_auto_scale( 525 struct dpp *dpp_base, 526 const struct scaler_data *scl_data) 527 { 528 enum lb_memory_config lb_config; 529 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 530 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode( 531 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); 532 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN 533 && scl_data->format <= PIXEL_FORMAT_VIDEO_END; 534 535 dpp1_dscl_set_overscan(dpp, scl_data); 536 537 dpp1_dscl_set_otg_blank(dpp, scl_data); 538 539 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); 540 541 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) 542 return; 543 544 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); 545 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); 546 547 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) 548 return; 549 550 /* TODO: v_min */ 551 REG_SET_3(DSCL_AUTOCAL, 0, 552 AUTOCAL_MODE, AUTOCAL_MODE_AUTOSCALE, 553 AUTOCAL_NUM_PIPE, 0, 554 AUTOCAL_PIPE_ID, 0); 555 556 /* Black offsets */ 557 if (ycbcr) 558 REG_SET_2(SCL_BLACK_OFFSET, 0, 559 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 560 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); 561 else 562 563 REG_SET_2(SCL_BLACK_OFFSET, 0, 564 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 565 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); 566 567 REG_SET_4(SCL_TAP_CONTROL, 0, 568 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, 569 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, 570 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, 571 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); 572 573 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); 574 } 575 #endif 576 577 578 static void dpp1_dscl_set_manual_ratio_init( 579 struct dcn10_dpp *dpp, const struct scaler_data *data) 580 { 581 uint32_t init_frac = 0; 582 uint32_t init_int = 0; 583 584 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO, 0, 585 SCL_H_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.horz) << 5); 586 587 REG_SET(SCL_VERT_FILTER_SCALE_RATIO, 0, 588 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); 589 590 REG_SET(SCL_HORZ_FILTER_SCALE_RATIO_C, 0, 591 SCL_H_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.horz_c) << 5); 592 593 REG_SET(SCL_VERT_FILTER_SCALE_RATIO_C, 0, 594 SCL_V_SCALE_RATIO_C, dc_fixpt_u3d19(data->ratios.vert_c) << 5); 595 596 /* 597 * 0.24 format for fraction, first five bits zeroed 598 */ 599 init_frac = dc_fixpt_u0d19(data->inits.h) << 5; 600 init_int = dc_fixpt_floor(data->inits.h); 601 REG_SET_2(SCL_HORZ_FILTER_INIT, 0, 602 SCL_H_INIT_FRAC, init_frac, 603 SCL_H_INIT_INT, init_int); 604 605 init_frac = dc_fixpt_u0d19(data->inits.h_c) << 5; 606 init_int = dc_fixpt_floor(data->inits.h_c); 607 REG_SET_2(SCL_HORZ_FILTER_INIT_C, 0, 608 SCL_H_INIT_FRAC_C, init_frac, 609 SCL_H_INIT_INT_C, init_int); 610 611 init_frac = dc_fixpt_u0d19(data->inits.v) << 5; 612 init_int = dc_fixpt_floor(data->inits.v); 613 REG_SET_2(SCL_VERT_FILTER_INIT, 0, 614 SCL_V_INIT_FRAC, init_frac, 615 SCL_V_INIT_INT, init_int); 616 617 init_frac = dc_fixpt_u0d19(data->inits.v_bot) << 5; 618 init_int = dc_fixpt_floor(data->inits.v_bot); 619 REG_SET_2(SCL_VERT_FILTER_INIT_BOT, 0, 620 SCL_V_INIT_FRAC_BOT, init_frac, 621 SCL_V_INIT_INT_BOT, init_int); 622 623 init_frac = dc_fixpt_u0d19(data->inits.v_c) << 5; 624 init_int = dc_fixpt_floor(data->inits.v_c); 625 REG_SET_2(SCL_VERT_FILTER_INIT_C, 0, 626 SCL_V_INIT_FRAC_C, init_frac, 627 SCL_V_INIT_INT_C, init_int); 628 629 init_frac = dc_fixpt_u0d19(data->inits.v_c_bot) << 5; 630 init_int = dc_fixpt_floor(data->inits.v_c_bot); 631 REG_SET_2(SCL_VERT_FILTER_INIT_BOT_C, 0, 632 SCL_V_INIT_FRAC_BOT_C, init_frac, 633 SCL_V_INIT_INT_BOT_C, init_int); 634 } 635 636 637 638 static void dpp1_dscl_set_recout( 639 struct dcn10_dpp *dpp, const struct rect *recout) 640 { 641 int visual_confirm_on = 0; 642 if (dpp->base.ctx->dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) 643 visual_confirm_on = 1; 644 645 REG_SET_2(RECOUT_START, 0, 646 /* First pixel of RECOUT */ 647 RECOUT_START_X, recout->x, 648 /* First line of RECOUT */ 649 RECOUT_START_Y, recout->y); 650 651 REG_SET_2(RECOUT_SIZE, 0, 652 /* Number of RECOUT horizontal pixels */ 653 RECOUT_WIDTH, recout->width, 654 /* Number of RECOUT vertical lines */ 655 RECOUT_HEIGHT, recout->height 656 - visual_confirm_on * 4 * (dpp->base.inst + 1)); 657 } 658 659 /* Main function to program scaler and line buffer in manual scaling mode */ 660 void dpp1_dscl_set_scaler_manual_scale( 661 struct dpp *dpp_base, 662 const struct scaler_data *scl_data) 663 { 664 enum lb_memory_config lb_config; 665 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 666 enum dscl_mode_sel dscl_mode = dpp1_dscl_get_dscl_mode( 667 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); 668 bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN 669 && scl_data->format <= PIXEL_FORMAT_VIDEO_END; 670 671 if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) 672 return; 673 674 PERF_TRACE(); 675 676 dpp->scl_data = *scl_data; 677 678 /* Autocal off */ 679 REG_SET_3(DSCL_AUTOCAL, 0, 680 AUTOCAL_MODE, AUTOCAL_MODE_OFF, 681 AUTOCAL_NUM_PIPE, 0, 682 AUTOCAL_PIPE_ID, 0); 683 684 /* Recout */ 685 dpp1_dscl_set_recout(dpp, &scl_data->recout); 686 687 /* MPC Size */ 688 REG_SET_2(MPC_SIZE, 0, 689 /* Number of horizontal pixels of MPC */ 690 MPC_WIDTH, scl_data->h_active, 691 /* Number of vertical lines of MPC */ 692 MPC_HEIGHT, scl_data->v_active); 693 694 /* SCL mode */ 695 REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode); 696 697 if (dscl_mode == DSCL_MODE_DSCL_BYPASS) 698 return; 699 700 /* LB */ 701 lb_config = dpp1_dscl_find_lb_memory_config(dpp, scl_data); 702 dpp1_dscl_set_lb(dpp, &scl_data->lb_params, lb_config); 703 704 if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) 705 return; 706 707 /* Black offsets */ 708 if (ycbcr) 709 REG_SET_2(SCL_BLACK_OFFSET, 0, 710 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 711 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_CBCR); 712 else 713 714 REG_SET_2(SCL_BLACK_OFFSET, 0, 715 SCL_BLACK_OFFSET_RGB_Y, BLACK_OFFSET_RGB_Y, 716 SCL_BLACK_OFFSET_CBCR, BLACK_OFFSET_RGB_Y); 717 718 /* Manually calculate scale ratio and init values */ 719 dpp1_dscl_set_manual_ratio_init(dpp, scl_data); 720 721 /* HTaps/VTaps */ 722 REG_SET_4(SCL_TAP_CONTROL, 0, 723 SCL_V_NUM_TAPS, scl_data->taps.v_taps - 1, 724 SCL_H_NUM_TAPS, scl_data->taps.h_taps - 1, 725 SCL_V_NUM_TAPS_C, scl_data->taps.v_taps_c - 1, 726 SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1); 727 728 dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr); 729 PERF_TRACE(); 730 } 731