1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "dm_services.h"
26 #include "dce_calcs.h"
27 #include "reg_helper.h"
28 #include "basics/conversion.h"
29 #include "dcn10_hubp.h"
30
31 #define REG(reg)\
32 hubp1->hubp_regs->reg
33
34 #define CTX \
35 hubp1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 hubp1->hubp_shift->field_name, hubp1->hubp_mask->field_name
40
hubp1_set_blank(struct hubp * hubp,bool blank)41 void hubp1_set_blank(struct hubp *hubp, bool blank)
42 {
43 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
44 uint32_t blank_en = blank ? 1 : 0;
45
46 REG_UPDATE_2(DCHUBP_CNTL,
47 HUBP_BLANK_EN, blank_en,
48 HUBP_TTU_DISABLE, blank_en);
49
50 if (blank) {
51 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
52
53 if (reg_val) {
54 /* init sequence workaround: in case HUBP is
55 * power gated, this wait would timeout.
56 *
57 * we just wrote reg_val to non-0, if it stay 0
58 * it means HUBP is gated
59 */
60 REG_WAIT(DCHUBP_CNTL,
61 HUBP_NO_OUTSTANDING_REQ, 1,
62 1, 200);
63 }
64
65 hubp->mpcc_id = 0xf;
66 hubp->opp_id = 0xf;
67 }
68 }
69
hubp1_disconnect(struct hubp * hubp)70 static void hubp1_disconnect(struct hubp *hubp)
71 {
72 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
73
74 REG_UPDATE(DCHUBP_CNTL,
75 HUBP_TTU_DISABLE, 1);
76
77 REG_UPDATE(CURSOR_CONTROL,
78 CURSOR_ENABLE, 0);
79 }
80
hubp1_disable_control(struct hubp * hubp,bool disable_hubp)81 static void hubp1_disable_control(struct hubp *hubp, bool disable_hubp)
82 {
83 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
84 uint32_t disable = disable_hubp ? 1 : 0;
85
86 REG_UPDATE(DCHUBP_CNTL,
87 HUBP_DISABLE, disable);
88 }
89
hubp1_get_underflow_status(struct hubp * hubp)90 static unsigned int hubp1_get_underflow_status(struct hubp *hubp)
91 {
92 uint32_t hubp_underflow = 0;
93 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
94
95 REG_GET(DCHUBP_CNTL,
96 HUBP_UNDERFLOW_STATUS,
97 &hubp_underflow);
98
99 return hubp_underflow;
100 }
101
hubp1_set_hubp_blank_en(struct hubp * hubp,bool blank)102 static void hubp1_set_hubp_blank_en(struct hubp *hubp, bool blank)
103 {
104 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
105 uint32_t blank_en = blank ? 1 : 0;
106
107 REG_UPDATE(DCHUBP_CNTL, HUBP_BLANK_EN, blank_en);
108 }
109
hubp1_vready_workaround(struct hubp * hubp,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)110 static void hubp1_vready_workaround(struct hubp *hubp,
111 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
112 {
113 uint32_t value = 0;
114 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
115
116 /* set HBUBREQ_DEBUG_DB[12] = 1 */
117 value = REG_READ(HUBPREQ_DEBUG_DB);
118
119 /* hack mode disable */
120 value |= 0x100;
121 value &= ~0x1000;
122
123 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
124 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
125 /* if (eco_fix_needed(otg_global_sync_timing)
126 * set HBUBREQ_DEBUG_DB[12] = 1 */
127 value |= 0x1000;
128 }
129
130 REG_WRITE(HUBPREQ_DEBUG_DB, value);
131 }
132
hubp1_program_tiling(struct hubp * hubp,const union dc_tiling_info * info,const enum surface_pixel_format pixel_format)133 void hubp1_program_tiling(
134 struct hubp *hubp,
135 const union dc_tiling_info *info,
136 const enum surface_pixel_format pixel_format)
137 {
138 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
139
140 REG_UPDATE_6(DCSURF_ADDR_CONFIG,
141 NUM_PIPES, log_2(info->gfx9.num_pipes),
142 NUM_BANKS, log_2(info->gfx9.num_banks),
143 PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
144 NUM_SE, log_2(info->gfx9.num_shader_engines),
145 NUM_RB_PER_SE, log_2(info->gfx9.num_rb_per_se),
146 MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
147
148 REG_UPDATE_4(DCSURF_TILING_CONFIG,
149 SW_MODE, info->gfx9.swizzle,
150 META_LINEAR, info->gfx9.meta_linear,
151 RB_ALIGNED, info->gfx9.rb_aligned,
152 PIPE_ALIGNED, info->gfx9.pipe_aligned);
153 }
154
hubp1_program_size(struct hubp * hubp,enum surface_pixel_format format,const union plane_size * plane_size,struct dc_plane_dcc_param * dcc)155 void hubp1_program_size(
156 struct hubp *hubp,
157 enum surface_pixel_format format,
158 const union plane_size *plane_size,
159 struct dc_plane_dcc_param *dcc)
160 {
161 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
162 uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
163
164 /* Program data and meta surface pitch (calculation from addrlib)
165 * 444 or 420 luma
166 */
167 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END) {
168 ASSERT(plane_size->video.chroma_pitch != 0);
169 /* Chroma pitch zero can cause system hang! */
170
171 pitch = plane_size->video.luma_pitch - 1;
172 meta_pitch = dcc->video.meta_pitch_l - 1;
173 pitch_c = plane_size->video.chroma_pitch - 1;
174 meta_pitch_c = dcc->video.meta_pitch_c - 1;
175 } else {
176 pitch = plane_size->grph.surface_pitch - 1;
177 meta_pitch = dcc->grph.meta_pitch - 1;
178 pitch_c = 0;
179 meta_pitch_c = 0;
180 }
181
182 if (!dcc->enable) {
183 meta_pitch = 0;
184 meta_pitch_c = 0;
185 }
186
187 REG_UPDATE_2(DCSURF_SURFACE_PITCH,
188 PITCH, pitch, META_PITCH, meta_pitch);
189
190 if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
191 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
192 PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
193 }
194
hubp1_program_rotation(struct hubp * hubp,enum dc_rotation_angle rotation,bool horizontal_mirror)195 void hubp1_program_rotation(
196 struct hubp *hubp,
197 enum dc_rotation_angle rotation,
198 bool horizontal_mirror)
199 {
200 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
201 uint32_t mirror;
202
203
204 if (horizontal_mirror)
205 mirror = 1;
206 else
207 mirror = 0;
208
209 /* Program rotation angle and horz mirror - no mirror */
210 if (rotation == ROTATION_ANGLE_0)
211 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
212 ROTATION_ANGLE, 0,
213 H_MIRROR_EN, mirror);
214 else if (rotation == ROTATION_ANGLE_90)
215 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
216 ROTATION_ANGLE, 1,
217 H_MIRROR_EN, mirror);
218 else if (rotation == ROTATION_ANGLE_180)
219 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
220 ROTATION_ANGLE, 2,
221 H_MIRROR_EN, mirror);
222 else if (rotation == ROTATION_ANGLE_270)
223 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
224 ROTATION_ANGLE, 3,
225 H_MIRROR_EN, mirror);
226 }
227
hubp1_program_pixel_format(struct hubp * hubp,enum surface_pixel_format format)228 void hubp1_program_pixel_format(
229 struct hubp *hubp,
230 enum surface_pixel_format format)
231 {
232 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
233 uint32_t red_bar = 3;
234 uint32_t blue_bar = 2;
235
236 /* swap for ABGR format */
237 if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
238 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
239 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
240 || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
241 red_bar = 2;
242 blue_bar = 3;
243 }
244
245 REG_UPDATE_2(HUBPRET_CONTROL,
246 CROSSBAR_SRC_CB_B, blue_bar,
247 CROSSBAR_SRC_CR_R, red_bar);
248
249 /* Mapping is same as ipp programming (cnvc) */
250
251 switch (format) {
252 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
253 REG_UPDATE(DCSURF_SURFACE_CONFIG,
254 SURFACE_PIXEL_FORMAT, 1);
255 break;
256 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
257 REG_UPDATE(DCSURF_SURFACE_CONFIG,
258 SURFACE_PIXEL_FORMAT, 3);
259 break;
260 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
261 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
262 REG_UPDATE(DCSURF_SURFACE_CONFIG,
263 SURFACE_PIXEL_FORMAT, 8);
264 break;
265 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
266 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
268 REG_UPDATE(DCSURF_SURFACE_CONFIG,
269 SURFACE_PIXEL_FORMAT, 10);
270 break;
271 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
272 REG_UPDATE(DCSURF_SURFACE_CONFIG,
273 SURFACE_PIXEL_FORMAT, 22);
274 break;
275 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
277 REG_UPDATE(DCSURF_SURFACE_CONFIG,
278 SURFACE_PIXEL_FORMAT, 24);
279 break;
280
281 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
282 REG_UPDATE(DCSURF_SURFACE_CONFIG,
283 SURFACE_PIXEL_FORMAT, 65);
284 break;
285 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
286 REG_UPDATE(DCSURF_SURFACE_CONFIG,
287 SURFACE_PIXEL_FORMAT, 64);
288 break;
289 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
290 REG_UPDATE(DCSURF_SURFACE_CONFIG,
291 SURFACE_PIXEL_FORMAT, 67);
292 break;
293 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
294 REG_UPDATE(DCSURF_SURFACE_CONFIG,
295 SURFACE_PIXEL_FORMAT, 66);
296 break;
297 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
298 REG_UPDATE(DCSURF_SURFACE_CONFIG,
299 SURFACE_PIXEL_FORMAT, 12);
300 break;
301 default:
302 BREAK_TO_DEBUGGER();
303 break;
304 }
305
306 /* don't see the need of program the xbar in DCN 1.0 */
307 }
308
hubp1_program_surface_flip_and_addr(struct hubp * hubp,const struct dc_plane_address * address,bool flip_immediate)309 bool hubp1_program_surface_flip_and_addr(
310 struct hubp *hubp,
311 const struct dc_plane_address *address,
312 bool flip_immediate)
313 {
314 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
315
316 /* program flip type */
317 REG_SET(DCSURF_FLIP_CONTROL, 0,
318 SURFACE_FLIP_TYPE, flip_immediate);
319
320 /* HW automatically latch rest of address register on write to
321 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
322 *
323 * program high first and then the low addr, order matters!
324 */
325 switch (address->type) {
326 case PLN_ADDR_TYPE_GRAPHICS:
327 /* DCN1.0 does not support const color
328 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
329 * base on address->grph.dcc_const_color
330 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
331 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
332 */
333
334 if (address->grph.addr.quad_part == 0)
335 break;
336
337 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
338 PRIMARY_SURFACE_TMZ, address->tmz_surface,
339 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
340
341 if (address->grph.meta_addr.quad_part != 0) {
342 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
343 PRIMARY_META_SURFACE_ADDRESS_HIGH,
344 address->grph.meta_addr.high_part);
345
346 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
347 PRIMARY_META_SURFACE_ADDRESS,
348 address->grph.meta_addr.low_part);
349 }
350
351 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
352 PRIMARY_SURFACE_ADDRESS_HIGH,
353 address->grph.addr.high_part);
354
355 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
356 PRIMARY_SURFACE_ADDRESS,
357 address->grph.addr.low_part);
358 break;
359 case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
360 if (address->video_progressive.luma_addr.quad_part == 0
361 || address->video_progressive.chroma_addr.quad_part == 0)
362 break;
363
364 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
365 PRIMARY_SURFACE_TMZ, address->tmz_surface,
366 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
367 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
368 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
369
370 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
371 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
372 PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
373 address->video_progressive.chroma_meta_addr.high_part);
374
375 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
376 PRIMARY_META_SURFACE_ADDRESS_C,
377 address->video_progressive.chroma_meta_addr.low_part);
378
379 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
380 PRIMARY_META_SURFACE_ADDRESS_HIGH,
381 address->video_progressive.luma_meta_addr.high_part);
382
383 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
384 PRIMARY_META_SURFACE_ADDRESS,
385 address->video_progressive.luma_meta_addr.low_part);
386 }
387
388 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
389 PRIMARY_SURFACE_ADDRESS_HIGH_C,
390 address->video_progressive.chroma_addr.high_part);
391
392 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
393 PRIMARY_SURFACE_ADDRESS_C,
394 address->video_progressive.chroma_addr.low_part);
395
396 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
397 PRIMARY_SURFACE_ADDRESS_HIGH,
398 address->video_progressive.luma_addr.high_part);
399
400 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
401 PRIMARY_SURFACE_ADDRESS,
402 address->video_progressive.luma_addr.low_part);
403 break;
404 case PLN_ADDR_TYPE_GRPH_STEREO:
405 if (address->grph_stereo.left_addr.quad_part == 0)
406 break;
407 if (address->grph_stereo.right_addr.quad_part == 0)
408 break;
409
410 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
411 PRIMARY_SURFACE_TMZ, address->tmz_surface,
412 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
413 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
414 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
415 SECONDARY_SURFACE_TMZ, address->tmz_surface,
416 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
417 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
418 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
419
420 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
421
422 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
423 SECONDARY_META_SURFACE_ADDRESS_HIGH,
424 address->grph_stereo.right_meta_addr.high_part);
425
426 REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
427 SECONDARY_META_SURFACE_ADDRESS,
428 address->grph_stereo.right_meta_addr.low_part);
429 }
430 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
431
432 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
433 PRIMARY_META_SURFACE_ADDRESS_HIGH,
434 address->grph_stereo.left_meta_addr.high_part);
435
436 REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
437 PRIMARY_META_SURFACE_ADDRESS,
438 address->grph_stereo.left_meta_addr.low_part);
439 }
440
441 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
442 SECONDARY_SURFACE_ADDRESS_HIGH,
443 address->grph_stereo.right_addr.high_part);
444
445 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
446 SECONDARY_SURFACE_ADDRESS,
447 address->grph_stereo.right_addr.low_part);
448
449 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
450 PRIMARY_SURFACE_ADDRESS_HIGH,
451 address->grph_stereo.left_addr.high_part);
452
453 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
454 PRIMARY_SURFACE_ADDRESS,
455 address->grph_stereo.left_addr.low_part);
456 break;
457 default:
458 BREAK_TO_DEBUGGER();
459 break;
460 }
461
462 hubp->request_address = *address;
463
464 return true;
465 }
466
hubp1_dcc_control(struct hubp * hubp,bool enable,bool independent_64b_blks)467 void hubp1_dcc_control(struct hubp *hubp, bool enable,
468 bool independent_64b_blks)
469 {
470 uint32_t dcc_en = enable ? 1 : 0;
471 uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
472 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
473
474 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
475 PRIMARY_SURFACE_DCC_EN, dcc_en,
476 PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
477 SECONDARY_SURFACE_DCC_EN, dcc_en,
478 SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
479 }
480
hubp1_program_surface_config(struct hubp * hubp,enum surface_pixel_format format,union dc_tiling_info * tiling_info,union plane_size * plane_size,enum dc_rotation_angle rotation,struct dc_plane_dcc_param * dcc,bool horizontal_mirror)481 void hubp1_program_surface_config(
482 struct hubp *hubp,
483 enum surface_pixel_format format,
484 union dc_tiling_info *tiling_info,
485 union plane_size *plane_size,
486 enum dc_rotation_angle rotation,
487 struct dc_plane_dcc_param *dcc,
488 bool horizontal_mirror)
489 {
490 hubp1_dcc_control(hubp, dcc->enable, dcc->grph.independent_64b_blks);
491 hubp1_program_tiling(hubp, tiling_info, format);
492 hubp1_program_size(hubp, format, plane_size, dcc);
493 hubp1_program_rotation(hubp, rotation, horizontal_mirror);
494 hubp1_program_pixel_format(hubp, format);
495 }
496
hubp1_program_requestor(struct hubp * hubp,struct _vcs_dpi_display_rq_regs_st * rq_regs)497 void hubp1_program_requestor(
498 struct hubp *hubp,
499 struct _vcs_dpi_display_rq_regs_st *rq_regs)
500 {
501 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
502
503 REG_UPDATE(HUBPRET_CONTROL,
504 DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
505 REG_SET_4(DCN_EXPANSION_MODE, 0,
506 DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
507 PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
508 MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
509 CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
510 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
511 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
512 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
513 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
514 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
515 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
516 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
517 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
518 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
519 REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
520 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
521 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
522 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
523 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
524 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
525 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
526 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
527 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
528 }
529
530
hubp1_program_deadline(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr)531 void hubp1_program_deadline(
532 struct hubp *hubp,
533 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
534 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
535 {
536 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
537
538 /* DLG - Per hubp */
539 REG_SET_2(BLANK_OFFSET_0, 0,
540 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
541 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
542
543 REG_SET(BLANK_OFFSET_1, 0,
544 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
545
546 REG_SET(DST_DIMENSIONS, 0,
547 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
548
549 REG_SET_2(DST_AFTER_SCALER, 0,
550 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
551 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
552
553 if (REG(PREFETCH_SETTINS))
554 REG_SET_2(PREFETCH_SETTINS, 0,
555 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
556 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
557 else
558 REG_SET_2(PREFETCH_SETTINGS, 0,
559 DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
560 VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
561
562 REG_SET_2(VBLANK_PARAMETERS_0, 0,
563 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
564 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
565
566 REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
567 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
568
569 /* DLG - Per luma/chroma */
570 REG_SET(VBLANK_PARAMETERS_1, 0,
571 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
572
573 REG_SET(VBLANK_PARAMETERS_3, 0,
574 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
575
576 if (REG(NOM_PARAMETERS_0))
577 REG_SET(NOM_PARAMETERS_0, 0,
578 DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
579
580 if (REG(NOM_PARAMETERS_1))
581 REG_SET(NOM_PARAMETERS_1, 0,
582 REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
583
584 REG_SET(NOM_PARAMETERS_4, 0,
585 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
586
587 REG_SET(NOM_PARAMETERS_5, 0,
588 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
589
590 REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
591 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
592 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
593
594 REG_SET_2(PER_LINE_DELIVERY, 0,
595 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
596 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
597
598 if (REG(PREFETCH_SETTINS_C))
599 REG_SET(PREFETCH_SETTINS_C, 0,
600 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
601 else
602 REG_SET(PREFETCH_SETTINGS_C, 0,
603 VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
604
605 REG_SET(VBLANK_PARAMETERS_2, 0,
606 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
607
608 REG_SET(VBLANK_PARAMETERS_4, 0,
609 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
610
611 if (REG(NOM_PARAMETERS_2))
612 REG_SET(NOM_PARAMETERS_2, 0,
613 DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
614
615 if (REG(NOM_PARAMETERS_3))
616 REG_SET(NOM_PARAMETERS_3, 0,
617 REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
618
619 REG_SET(NOM_PARAMETERS_6, 0,
620 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
621
622 REG_SET(NOM_PARAMETERS_7, 0,
623 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
624
625 /* TTU - per hubp */
626 REG_SET_2(DCN_TTU_QOS_WM, 0,
627 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
628 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
629
630 REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
631 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
632 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
633
634 /* TTU - per luma/chroma */
635 /* Assumed surf0 is luma and 1 is chroma */
636
637 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
638 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
639 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
640 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
641
642 REG_SET(DCN_SURF0_TTU_CNTL1, 0,
643 REFCYC_PER_REQ_DELIVERY_PRE,
644 ttu_attr->refcyc_per_req_delivery_pre_l);
645
646 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
647 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
648 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
649 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
650
651 REG_SET(DCN_SURF1_TTU_CNTL1, 0,
652 REFCYC_PER_REQ_DELIVERY_PRE,
653 ttu_attr->refcyc_per_req_delivery_pre_c);
654
655 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
656 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
657 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
658 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
659 REG_SET(DCN_CUR0_TTU_CNTL1, 0,
660 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
661 }
662
hubp1_setup(struct hubp * hubp,struct _vcs_dpi_display_dlg_regs_st * dlg_attr,struct _vcs_dpi_display_ttu_regs_st * ttu_attr,struct _vcs_dpi_display_rq_regs_st * rq_regs,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dest)663 static void hubp1_setup(
664 struct hubp *hubp,
665 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
666 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
667 struct _vcs_dpi_display_rq_regs_st *rq_regs,
668 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
669 {
670 /* otg is locked when this func is called. Register are double buffered.
671 * disable the requestors is not needed
672 */
673 hubp1_program_requestor(hubp, rq_regs);
674 hubp1_program_deadline(hubp, dlg_attr, ttu_attr);
675 hubp1_vready_workaround(hubp, pipe_dest);
676 }
677
hubp1_is_flip_pending(struct hubp * hubp)678 bool hubp1_is_flip_pending(struct hubp *hubp)
679 {
680 uint32_t flip_pending = 0;
681 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
682 struct dc_plane_address earliest_inuse_address;
683
684 REG_GET(DCSURF_FLIP_CONTROL,
685 SURFACE_FLIP_PENDING, &flip_pending);
686
687 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
688 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
689
690 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
691 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
692
693 if (flip_pending)
694 return true;
695
696 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
697 return true;
698
699 return false;
700 }
701
702 uint32_t aperture_default_system = 1;
703 uint32_t context0_default_system; /* = 0;*/
704
hubp1_set_vm_system_aperture_settings(struct hubp * hubp,struct vm_system_aperture_param * apt)705 static void hubp1_set_vm_system_aperture_settings(struct hubp *hubp,
706 struct vm_system_aperture_param *apt)
707 {
708 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
709 PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
710 PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
711 PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
712
713 mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
714 mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 12;
715 mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 12;
716
717 REG_SET_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, 0,
718 MC_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, aperture_default_system, /* 1 = system physical memory */
719 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
720 REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
721 MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
722
723 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, 0,
724 MC_VM_SYSTEM_APERTURE_LOW_ADDR_MSB, mc_vm_apt_low.high_part);
725 REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, 0,
726 MC_VM_SYSTEM_APERTURE_LOW_ADDR_LSB, mc_vm_apt_low.low_part);
727
728 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, 0,
729 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB, mc_vm_apt_high.high_part);
730 REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, 0,
731 MC_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB, mc_vm_apt_high.low_part);
732 }
733
hubp1_set_vm_context0_settings(struct hubp * hubp,const struct vm_context0_param * vm0)734 static void hubp1_set_vm_context0_settings(struct hubp *hubp,
735 const struct vm_context0_param *vm0)
736 {
737 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
738 /* pte base */
739 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, 0,
740 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB, vm0->pte_base.high_part);
741 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, 0,
742 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB, vm0->pte_base.low_part);
743
744 /* pte start */
745 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, 0,
746 VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB, vm0->pte_start.high_part);
747 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, 0,
748 VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB, vm0->pte_start.low_part);
749
750 /* pte end */
751 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, 0,
752 VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB, vm0->pte_end.high_part);
753 REG_SET(DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, 0,
754 VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB, vm0->pte_end.low_part);
755
756 /* fault handling */
757 REG_SET_2(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
758 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB, vm0->fault_default.high_part,
759 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_SYSTEM, context0_default_system);
760 REG_SET(DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
761 VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB, vm0->fault_default.low_part);
762
763 /* control: enable VM PTE*/
764 REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
765 ENABLE_L1_TLB, 1,
766 SYSTEM_ACCESS_MODE, 3);
767 }
768
min_set_viewport(struct hubp * hubp,const struct rect * viewport,const struct rect * viewport_c)769 void min_set_viewport(
770 struct hubp *hubp,
771 const struct rect *viewport,
772 const struct rect *viewport_c)
773 {
774 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
775
776 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,
777 PRI_VIEWPORT_WIDTH, viewport->width,
778 PRI_VIEWPORT_HEIGHT, viewport->height);
779
780 REG_SET_2(DCSURF_PRI_VIEWPORT_START, 0,
781 PRI_VIEWPORT_X_START, viewport->x,
782 PRI_VIEWPORT_Y_START, viewport->y);
783
784 /*for stereo*/
785 REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION, 0,
786 SEC_VIEWPORT_WIDTH, viewport->width,
787 SEC_VIEWPORT_HEIGHT, viewport->height);
788
789 REG_SET_2(DCSURF_SEC_VIEWPORT_START, 0,
790 SEC_VIEWPORT_X_START, viewport->x,
791 SEC_VIEWPORT_Y_START, viewport->y);
792
793 /* DC supports NV12 only at the moment */
794 REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,
795 PRI_VIEWPORT_WIDTH_C, viewport_c->width,
796 PRI_VIEWPORT_HEIGHT_C, viewport_c->height);
797
798 REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,
799 PRI_VIEWPORT_X_START_C, viewport_c->x,
800 PRI_VIEWPORT_Y_START_C, viewport_c->y);
801 }
802
hubp1_read_state(struct hubp * hubp)803 void hubp1_read_state(struct hubp *hubp)
804 {
805 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
806 struct dcn_hubp_state *s = &hubp1->state;
807 struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
808 struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
809 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
810
811 /* Requester */
812 REG_GET(HUBPRET_CONTROL,
813 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
814 REG_GET_4(DCN_EXPANSION_MODE,
815 DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
816 PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
817 MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
818 CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
819 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
820 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
821 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
822 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
823 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
824 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
825 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
826 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
827 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
828 REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
829 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
830 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
831 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
832 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
833 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
834 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
835 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
836 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
837
838 /* DLG - Per hubp */
839 REG_GET_2(BLANK_OFFSET_0,
840 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
841 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
842
843 REG_GET(BLANK_OFFSET_1,
844 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
845
846 REG_GET(DST_DIMENSIONS,
847 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
848
849 REG_GET_2(DST_AFTER_SCALER,
850 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
851 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
852
853 if (REG(PREFETCH_SETTINS))
854 REG_GET_2(PREFETCH_SETTINS,
855 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
856 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
857 else
858 REG_GET_2(PREFETCH_SETTINGS,
859 DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
860 VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
861
862 REG_GET_2(VBLANK_PARAMETERS_0,
863 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
864 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
865
866 REG_GET(REF_FREQ_TO_PIX_FREQ,
867 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
868
869 /* DLG - Per luma/chroma */
870 REG_GET(VBLANK_PARAMETERS_1,
871 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
872
873 REG_GET(VBLANK_PARAMETERS_3,
874 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
875
876 if (REG(NOM_PARAMETERS_0))
877 REG_GET(NOM_PARAMETERS_0,
878 DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
879
880 if (REG(NOM_PARAMETERS_1))
881 REG_GET(NOM_PARAMETERS_1,
882 REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
883
884 REG_GET(NOM_PARAMETERS_4,
885 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
886
887 REG_GET(NOM_PARAMETERS_5,
888 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
889
890 REG_GET_2(PER_LINE_DELIVERY_PRE,
891 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
892 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
893
894 REG_GET_2(PER_LINE_DELIVERY,
895 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
896 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
897
898 if (REG(PREFETCH_SETTINS_C))
899 REG_GET(PREFETCH_SETTINS_C,
900 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
901 else
902 REG_GET(PREFETCH_SETTINGS_C,
903 VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
904
905 REG_GET(VBLANK_PARAMETERS_2,
906 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
907
908 REG_GET(VBLANK_PARAMETERS_4,
909 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
910
911 if (REG(NOM_PARAMETERS_2))
912 REG_GET(NOM_PARAMETERS_2,
913 DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
914
915 if (REG(NOM_PARAMETERS_3))
916 REG_GET(NOM_PARAMETERS_3,
917 REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
918
919 REG_GET(NOM_PARAMETERS_6,
920 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
921
922 REG_GET(NOM_PARAMETERS_7,
923 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
924
925 /* TTU - per hubp */
926 REG_GET_2(DCN_TTU_QOS_WM,
927 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
928 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
929
930 REG_GET_2(DCN_GLOBAL_TTU_CNTL,
931 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
932 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
933
934 /* TTU - per luma/chroma */
935 /* Assumed surf0 is luma and 1 is chroma */
936
937 REG_GET_3(DCN_SURF0_TTU_CNTL0,
938 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
939 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
940 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
941
942 REG_GET(DCN_SURF0_TTU_CNTL1,
943 REFCYC_PER_REQ_DELIVERY_PRE,
944 &ttu_attr->refcyc_per_req_delivery_pre_l);
945
946 REG_GET_3(DCN_SURF1_TTU_CNTL0,
947 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
948 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
949 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
950
951 REG_GET(DCN_SURF1_TTU_CNTL1,
952 REFCYC_PER_REQ_DELIVERY_PRE,
953 &ttu_attr->refcyc_per_req_delivery_pre_c);
954
955 /* Rest of hubp */
956 REG_GET(DCSURF_SURFACE_CONFIG,
957 SURFACE_PIXEL_FORMAT, &s->pixel_format);
958
959 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
960 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
961
962 REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
963 PRI_VIEWPORT_WIDTH, &s->viewport_width,
964 PRI_VIEWPORT_HEIGHT, &s->viewport_height);
965
966 REG_GET_2(DCSURF_SURFACE_CONFIG,
967 ROTATION_ANGLE, &s->rotation_angle,
968 H_MIRROR_EN, &s->h_mirror_en);
969
970 REG_GET(DCSURF_TILING_CONFIG,
971 SW_MODE, &s->sw_mode);
972
973 REG_GET(DCSURF_SURFACE_CONTROL,
974 PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
975
976 REG_GET_3(DCHUBP_CNTL,
977 HUBP_BLANK_EN, &s->blank_en,
978 HUBP_TTU_DISABLE, &s->ttu_disable,
979 HUBP_UNDERFLOW_STATUS, &s->underflow_status);
980
981 REG_GET(DCN_GLOBAL_TTU_CNTL,
982 MIN_TTU_VBLANK, &s->min_ttu_vblank);
983
984 REG_GET_2(DCN_TTU_QOS_WM,
985 QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
986 QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
987 }
988
hubp1_get_cursor_pitch(unsigned int pitch)989 enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
990 {
991 enum cursor_pitch hw_pitch;
992
993 switch (pitch) {
994 case 64:
995 hw_pitch = CURSOR_PITCH_64_PIXELS;
996 break;
997 case 128:
998 hw_pitch = CURSOR_PITCH_128_PIXELS;
999 break;
1000 case 256:
1001 hw_pitch = CURSOR_PITCH_256_PIXELS;
1002 break;
1003 default:
1004 DC_ERR("Invalid cursor pitch of %d. "
1005 "Only 64/128/256 is supported on DCN.\n", pitch);
1006 hw_pitch = CURSOR_PITCH_64_PIXELS;
1007 break;
1008 }
1009 return hw_pitch;
1010 }
1011
hubp1_get_lines_per_chunk(unsigned int cur_width,enum dc_cursor_color_format format)1012 static enum cursor_lines_per_chunk hubp1_get_lines_per_chunk(
1013 unsigned int cur_width,
1014 enum dc_cursor_color_format format)
1015 {
1016 enum cursor_lines_per_chunk line_per_chunk;
1017
1018 if (format == CURSOR_MODE_MONO)
1019 /* impl B. expansion in CUR Buffer reader */
1020 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1021 else if (cur_width <= 32)
1022 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
1023 else if (cur_width <= 64)
1024 line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
1025 else if (cur_width <= 128)
1026 line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
1027 else
1028 line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
1029
1030 return line_per_chunk;
1031 }
1032
hubp1_cursor_set_attributes(struct hubp * hubp,const struct dc_cursor_attributes * attr)1033 void hubp1_cursor_set_attributes(
1034 struct hubp *hubp,
1035 const struct dc_cursor_attributes *attr)
1036 {
1037 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1038 enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
1039 enum cursor_lines_per_chunk lpc = hubp1_get_lines_per_chunk(
1040 attr->width, attr->color_format);
1041
1042 hubp->curs_attr = *attr;
1043
1044 REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
1045 CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
1046 REG_UPDATE(CURSOR_SURFACE_ADDRESS,
1047 CURSOR_SURFACE_ADDRESS, attr->address.low_part);
1048
1049 REG_UPDATE_2(CURSOR_SIZE,
1050 CURSOR_WIDTH, attr->width,
1051 CURSOR_HEIGHT, attr->height);
1052
1053 REG_UPDATE_3(CURSOR_CONTROL,
1054 CURSOR_MODE, attr->color_format,
1055 CURSOR_PITCH, hw_pitch,
1056 CURSOR_LINES_PER_CHUNK, lpc);
1057
1058 REG_SET_2(CURSOR_SETTINS, 0,
1059 /* no shift of the cursor HDL schedule */
1060 CURSOR0_DST_Y_OFFSET, 0,
1061 /* used to shift the cursor chunk request deadline */
1062 CURSOR0_CHUNK_HDL_ADJUST, 3);
1063 }
1064
hubp1_cursor_set_position(struct hubp * hubp,const struct dc_cursor_position * pos,const struct dc_cursor_mi_param * param)1065 void hubp1_cursor_set_position(
1066 struct hubp *hubp,
1067 const struct dc_cursor_position *pos,
1068 const struct dc_cursor_mi_param *param)
1069 {
1070 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1071 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
1072 int x_hotspot = pos->x_hotspot;
1073 int y_hotspot = pos->y_hotspot;
1074 uint32_t dst_x_offset;
1075 uint32_t cur_en = pos->enable ? 1 : 0;
1076
1077 /*
1078 * Guard aganst cursor_set_position() from being called with invalid
1079 * attributes
1080 *
1081 * TODO: Look at combining cursor_set_position() and
1082 * cursor_set_attributes() into cursor_update()
1083 */
1084 if (hubp->curs_attr.address.quad_part == 0)
1085 return;
1086
1087 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
1088 src_x_offset = pos->y - pos->y_hotspot - param->viewport.x;
1089 y_hotspot = pos->x_hotspot;
1090 x_hotspot = pos->y_hotspot;
1091 }
1092
1093 if (param->mirror) {
1094 x_hotspot = param->viewport.width - x_hotspot;
1095 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
1096 }
1097
1098 dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
1099 dst_x_offset *= param->ref_clk_khz;
1100 dst_x_offset /= param->pixel_clk_khz;
1101
1102 ASSERT(param->h_scale_ratio.value);
1103
1104 if (param->h_scale_ratio.value)
1105 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1106 dc_fixpt_from_int(dst_x_offset),
1107 param->h_scale_ratio));
1108
1109 if (src_x_offset >= (int)param->viewport.width)
1110 cur_en = 0; /* not visible beyond right edge*/
1111
1112 if (src_x_offset + (int)hubp->curs_attr.width <= 0)
1113 cur_en = 0; /* not visible beyond left edge*/
1114
1115 if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1116 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1117
1118 REG_UPDATE(CURSOR_CONTROL,
1119 CURSOR_ENABLE, cur_en);
1120
1121 REG_SET_2(CURSOR_POSITION, 0,
1122 CURSOR_X_POSITION, pos->x,
1123 CURSOR_Y_POSITION, pos->y);
1124
1125 REG_SET_2(CURSOR_HOT_SPOT, 0,
1126 CURSOR_HOT_SPOT_X, x_hotspot,
1127 CURSOR_HOT_SPOT_Y, y_hotspot);
1128
1129 REG_SET(CURSOR_DST_OFFSET, 0,
1130 CURSOR_DST_X_OFFSET, dst_x_offset);
1131 /* TODO Handle surface pixel formats other than 4:4:4 */
1132 }
1133
hubp1_clk_cntl(struct hubp * hubp,bool enable)1134 void hubp1_clk_cntl(struct hubp *hubp, bool enable)
1135 {
1136 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1137 uint32_t clk_enable = enable ? 1 : 0;
1138
1139 REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1140 }
1141
hubp1_vtg_sel(struct hubp * hubp,uint32_t otg_inst)1142 void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1143 {
1144 struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1145
1146 REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1147 }
1148
1149 static const struct hubp_funcs dcn10_hubp_funcs = {
1150 .hubp_program_surface_flip_and_addr =
1151 hubp1_program_surface_flip_and_addr,
1152 .hubp_program_surface_config =
1153 hubp1_program_surface_config,
1154 .hubp_is_flip_pending = hubp1_is_flip_pending,
1155 .hubp_setup = hubp1_setup,
1156 .hubp_set_vm_system_aperture_settings = hubp1_set_vm_system_aperture_settings,
1157 .hubp_set_vm_context0_settings = hubp1_set_vm_context0_settings,
1158 .set_blank = hubp1_set_blank,
1159 .dcc_control = hubp1_dcc_control,
1160 .mem_program_viewport = min_set_viewport,
1161 .set_hubp_blank_en = hubp1_set_hubp_blank_en,
1162 .set_cursor_attributes = hubp1_cursor_set_attributes,
1163 .set_cursor_position = hubp1_cursor_set_position,
1164 .hubp_disconnect = hubp1_disconnect,
1165 .hubp_clk_cntl = hubp1_clk_cntl,
1166 .hubp_vtg_sel = hubp1_vtg_sel,
1167 .hubp_read_state = hubp1_read_state,
1168 .hubp_disable_control = hubp1_disable_control,
1169 .hubp_get_underflow_status = hubp1_get_underflow_status,
1170
1171 };
1172
1173 /*****************************************/
1174 /* Constructor, Destructor */
1175 /*****************************************/
1176
dcn10_hubp_construct(struct dcn10_hubp * hubp1,struct dc_context * ctx,uint32_t inst,const struct dcn_mi_registers * hubp_regs,const struct dcn_mi_shift * hubp_shift,const struct dcn_mi_mask * hubp_mask)1177 void dcn10_hubp_construct(
1178 struct dcn10_hubp *hubp1,
1179 struct dc_context *ctx,
1180 uint32_t inst,
1181 const struct dcn_mi_registers *hubp_regs,
1182 const struct dcn_mi_shift *hubp_shift,
1183 const struct dcn_mi_mask *hubp_mask)
1184 {
1185 hubp1->base.funcs = &dcn10_hubp_funcs;
1186 hubp1->base.ctx = ctx;
1187 hubp1->hubp_regs = hubp_regs;
1188 hubp1->hubp_shift = hubp_shift;
1189 hubp1->hubp_mask = hubp_mask;
1190 hubp1->base.inst = inst;
1191 hubp1->base.opp_id = 0xf;
1192 hubp1->base.mpcc_id = 0xf;
1193 }
1194
1195
1196