1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_LINK_ENCODER__DCN10_H__ 27 #define __DC_LINK_ENCODER__DCN10_H__ 28 29 #include "link_encoder.h" 30 31 #define TO_DCN10_LINK_ENC(link_encoder)\ 32 container_of(link_encoder, struct dcn10_link_encoder, base) 33 34 35 #define AUX_REG_LIST(id)\ 36 SRI(AUX_CONTROL, DP_AUX, id), \ 37 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 38 39 #define HPD_REG_LIST(id)\ 40 SRI(DC_HPD_CONTROL, HPD, id) 41 42 #define LE_DCN_COMMON_REG_LIST(id) \ 43 SRI(DIG_BE_CNTL, DIG, id), \ 44 SRI(DIG_BE_EN_CNTL, DIG, id), \ 45 SRI(TMDS_CTL_BITS, DIG, id), \ 46 SRI(DP_CONFIG, DP, id), \ 47 SRI(DP_DPHY_CNTL, DP, id), \ 48 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 49 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 50 SRI(DP_DPHY_SYM0, DP, id), \ 51 SRI(DP_DPHY_SYM1, DP, id), \ 52 SRI(DP_DPHY_SYM2, DP, id), \ 53 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 54 SRI(DP_LINK_CNTL, DP, id), \ 55 SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 56 SRI(DP_MSE_SAT0, DP, id), \ 57 SRI(DP_MSE_SAT1, DP, id), \ 58 SRI(DP_MSE_SAT2, DP, id), \ 59 SRI(DP_MSE_SAT_UPDATE, DP, id), \ 60 SRI(DP_SEC_CNTL, DP, id), \ 61 SRI(DP_VID_STREAM_CNTL, DP, id), \ 62 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 63 SRI(DP_SEC_CNTL1, DP, id), \ 64 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 65 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 66 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 67 68 69 #define LE_DCN10_REG_LIST(id)\ 70 LE_DCN_COMMON_REG_LIST(id) 71 72 struct dcn10_link_enc_aux_registers { 73 uint32_t AUX_CONTROL; 74 uint32_t AUX_DPHY_RX_CONTROL0; 75 }; 76 77 struct dcn10_link_enc_hpd_registers { 78 uint32_t DC_HPD_CONTROL; 79 }; 80 81 struct dcn10_link_enc_registers { 82 uint32_t DIG_BE_CNTL; 83 uint32_t DIG_BE_EN_CNTL; 84 uint32_t DP_CONFIG; 85 uint32_t DP_DPHY_CNTL; 86 uint32_t DP_DPHY_INTERNAL_CTRL; 87 uint32_t DP_DPHY_PRBS_CNTL; 88 uint32_t DP_DPHY_SCRAM_CNTL; 89 uint32_t DP_DPHY_SYM0; 90 uint32_t DP_DPHY_SYM1; 91 uint32_t DP_DPHY_SYM2; 92 uint32_t DP_DPHY_TRAINING_PATTERN_SEL; 93 uint32_t DP_LINK_CNTL; 94 uint32_t DP_LINK_FRAMING_CNTL; 95 uint32_t DP_MSE_SAT0; 96 uint32_t DP_MSE_SAT1; 97 uint32_t DP_MSE_SAT2; 98 uint32_t DP_MSE_SAT_UPDATE; 99 uint32_t DP_SEC_CNTL; 100 uint32_t DP_VID_STREAM_CNTL; 101 uint32_t DP_DPHY_FAST_TRAINING; 102 uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 103 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 104 uint32_t DP_SEC_CNTL1; 105 uint32_t TMDS_CTL_BITS; 106 }; 107 108 #define LE_SF(reg_name, field_name, post_fix)\ 109 .field_name = reg_name ## __ ## field_name ## post_fix 110 111 #define LINK_ENCODER_MASK_SH_LIST_DCN10(mask_sh)\ 112 LE_SF(DIG0_DIG_BE_EN_CNTL, DIG_ENABLE, mask_sh),\ 113 LE_SF(DIG0_DIG_BE_CNTL, DIG_HPD_SELECT, mask_sh),\ 114 LE_SF(DIG0_DIG_BE_CNTL, DIG_MODE, mask_sh),\ 115 LE_SF(DIG0_DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, mask_sh),\ 116 LE_SF(DIG0_TMDS_CTL_BITS, TMDS_CTL0, mask_sh), \ 117 LE_SF(DP0_DP_DPHY_CNTL, DPHY_BYPASS, mask_sh),\ 118 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE0, mask_sh),\ 119 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE1, mask_sh),\ 120 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE2, mask_sh),\ 121 LE_SF(DP0_DP_DPHY_CNTL, DPHY_ATEST_SEL_LANE3, mask_sh),\ 122 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, mask_sh),\ 123 LE_SF(DP0_DP_DPHY_PRBS_CNTL, DPHY_PRBS_SEL, mask_sh),\ 124 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM1, mask_sh),\ 125 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM2, mask_sh),\ 126 LE_SF(DP0_DP_DPHY_SYM0, DPHY_SYM3, mask_sh),\ 127 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM4, mask_sh),\ 128 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM5, mask_sh),\ 129 LE_SF(DP0_DP_DPHY_SYM1, DPHY_SYM6, mask_sh),\ 130 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM7, mask_sh),\ 131 LE_SF(DP0_DP_DPHY_SYM2, DPHY_SYM8, mask_sh),\ 132 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, mask_sh),\ 133 LE_SF(DP0_DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, mask_sh),\ 134 LE_SF(DP0_DP_DPHY_FAST_TRAINING, DPHY_RX_FAST_TRAINING_CAPABLE, mask_sh),\ 135 LE_SF(DP0_DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, mask_sh),\ 136 LE_SF(DP0_DP_DPHY_TRAINING_PATTERN_SEL, DPHY_TRAINING_PATTERN_SEL, mask_sh),\ 137 LE_SF(DP0_DP_DPHY_HBR2_PATTERN_CONTROL, DP_DPHY_HBR2_PATTERN_CONTROL, mask_sh),\ 138 LE_SF(DP0_DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, mask_sh),\ 139 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_IDLE_BS_INTERVAL, mask_sh),\ 140 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VBID_DISABLE, mask_sh),\ 141 LE_SF(DP0_DP_LINK_FRAMING_CNTL, DP_VID_ENHANCED_FRAME_MODE, mask_sh),\ 142 LE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ 143 LE_SF(DP0_DP_CONFIG, DP_UDI_LANES, mask_sh),\ 144 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_LINE_NUM, mask_sh),\ 145 LE_SF(DP0_DP_SEC_CNTL1, DP_SEC_GSP0_PRIORITY, mask_sh),\ 146 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC0, mask_sh),\ 147 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SRC1, mask_sh),\ 148 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT0, mask_sh),\ 149 LE_SF(DP0_DP_MSE_SAT0, DP_MSE_SAT_SLOT_COUNT1, mask_sh),\ 150 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC2, mask_sh),\ 151 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SRC3, mask_sh),\ 152 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT2, mask_sh),\ 153 LE_SF(DP0_DP_MSE_SAT1, DP_MSE_SAT_SLOT_COUNT3, mask_sh),\ 154 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_SAT_UPDATE, mask_sh),\ 155 LE_SF(DP0_DP_MSE_SAT_UPDATE, DP_MSE_16_MTP_KEEPOUT, mask_sh),\ 156 LE_SF(DP_AUX0_AUX_CONTROL, AUX_HPD_SEL, mask_sh),\ 157 LE_SF(DP_AUX0_AUX_CONTROL, AUX_LS_READ_EN, mask_sh),\ 158 LE_SF(DP_AUX0_AUX_DPHY_RX_CONTROL0, AUX_RX_RECEIVE_WINDOW, mask_sh),\ 159 LE_SF(HPD0_DC_HPD_CONTROL, DC_HPD_EN, mask_sh) 160 161 #define DCN_LINK_ENCODER_REG_FIELD_LIST(type) \ 162 type DIG_ENABLE;\ 163 type DIG_HPD_SELECT;\ 164 type DIG_MODE;\ 165 type DIG_FE_SOURCE_SELECT;\ 166 type DPHY_BYPASS;\ 167 type DPHY_ATEST_SEL_LANE0;\ 168 type DPHY_ATEST_SEL_LANE1;\ 169 type DPHY_ATEST_SEL_LANE2;\ 170 type DPHY_ATEST_SEL_LANE3;\ 171 type DPHY_PRBS_EN;\ 172 type DPHY_PRBS_SEL;\ 173 type DPHY_SYM1;\ 174 type DPHY_SYM2;\ 175 type DPHY_SYM3;\ 176 type DPHY_SYM4;\ 177 type DPHY_SYM5;\ 178 type DPHY_SYM6;\ 179 type DPHY_SYM7;\ 180 type DPHY_SYM8;\ 181 type DPHY_SCRAMBLER_BS_COUNT;\ 182 type DPHY_SCRAMBLER_ADVANCE;\ 183 type DPHY_RX_FAST_TRAINING_CAPABLE;\ 184 type DPHY_LOAD_BS_COUNT;\ 185 type DPHY_TRAINING_PATTERN_SEL;\ 186 type DP_DPHY_HBR2_PATTERN_CONTROL;\ 187 type DP_LINK_TRAINING_COMPLETE;\ 188 type DP_IDLE_BS_INTERVAL;\ 189 type DP_VBID_DISABLE;\ 190 type DP_VID_ENHANCED_FRAME_MODE;\ 191 type DP_VID_STREAM_ENABLE;\ 192 type DP_UDI_LANES;\ 193 type DP_SEC_GSP0_LINE_NUM;\ 194 type DP_SEC_GSP0_PRIORITY;\ 195 type DP_MSE_SAT_SRC0;\ 196 type DP_MSE_SAT_SRC1;\ 197 type DP_MSE_SAT_SRC2;\ 198 type DP_MSE_SAT_SRC3;\ 199 type DP_MSE_SAT_SLOT_COUNT0;\ 200 type DP_MSE_SAT_SLOT_COUNT1;\ 201 type DP_MSE_SAT_SLOT_COUNT2;\ 202 type DP_MSE_SAT_SLOT_COUNT3;\ 203 type DP_MSE_SAT_UPDATE;\ 204 type DP_MSE_16_MTP_KEEPOUT;\ 205 type DC_HPD_EN;\ 206 type TMDS_CTL0;\ 207 type AUX_HPD_SEL;\ 208 type AUX_LS_READ_EN;\ 209 type AUX_RX_RECEIVE_WINDOW 210 211 struct dcn10_link_enc_shift { 212 DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 213 }; 214 215 struct dcn10_link_enc_mask { 216 DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 217 }; 218 219 struct dcn10_link_encoder { 220 struct link_encoder base; 221 const struct dcn10_link_enc_registers *link_regs; 222 const struct dcn10_link_enc_aux_registers *aux_regs; 223 const struct dcn10_link_enc_hpd_registers *hpd_regs; 224 const struct dcn10_link_enc_shift *link_shift; 225 const struct dcn10_link_enc_mask *link_mask; 226 }; 227 228 229 void dcn10_link_encoder_construct( 230 struct dcn10_link_encoder *enc10, 231 const struct encoder_init_data *init_data, 232 const struct encoder_feature_support *enc_features, 233 const struct dcn10_link_enc_registers *link_regs, 234 const struct dcn10_link_enc_aux_registers *aux_regs, 235 const struct dcn10_link_enc_hpd_registers *hpd_regs, 236 const struct dcn10_link_enc_shift *link_shift, 237 const struct dcn10_link_enc_mask *link_mask); 238 239 bool dcn10_link_encoder_validate_dvi_output( 240 const struct dcn10_link_encoder *enc10, 241 enum signal_type connector_signal, 242 enum signal_type signal, 243 const struct dc_crtc_timing *crtc_timing); 244 245 bool dcn10_link_encoder_validate_rgb_output( 246 const struct dcn10_link_encoder *enc10, 247 const struct dc_crtc_timing *crtc_timing); 248 249 bool dcn10_link_encoder_validate_dp_output( 250 const struct dcn10_link_encoder *enc10, 251 const struct dc_crtc_timing *crtc_timing); 252 253 bool dcn10_link_encoder_validate_wireless_output( 254 const struct dcn10_link_encoder *enc10, 255 const struct dc_crtc_timing *crtc_timing); 256 257 bool dcn10_link_encoder_validate_output_with_stream( 258 struct link_encoder *enc, 259 const struct dc_stream_state *stream); 260 261 /****************** HW programming ************************/ 262 263 /* initialize HW */ /* why do we initialze aux in here? */ 264 void dcn10_link_encoder_hw_init(struct link_encoder *enc); 265 266 void dcn10_link_encoder_destroy(struct link_encoder **enc); 267 268 /* program DIG_MODE in DIG_BE */ 269 /* TODO can this be combined with enable_output? */ 270 void dcn10_link_encoder_setup( 271 struct link_encoder *enc, 272 enum signal_type signal); 273 274 void configure_encoder( 275 struct dcn10_link_encoder *enc10, 276 const struct dc_link_settings *link_settings); 277 278 /* enables TMDS PHY output */ 279 /* TODO: still need depth or just pass in adjusted pixel clock? */ 280 void dcn10_link_encoder_enable_tmds_output( 281 struct link_encoder *enc, 282 enum clock_source_id clock_source, 283 enum dc_color_depth color_depth, 284 enum signal_type signal, 285 uint32_t pixel_clock); 286 287 /* enables DP PHY output */ 288 void dcn10_link_encoder_enable_dp_output( 289 struct link_encoder *enc, 290 const struct dc_link_settings *link_settings, 291 enum clock_source_id clock_source); 292 293 /* enables DP PHY output in MST mode */ 294 void dcn10_link_encoder_enable_dp_mst_output( 295 struct link_encoder *enc, 296 const struct dc_link_settings *link_settings, 297 enum clock_source_id clock_source); 298 299 /* disable PHY output */ 300 void dcn10_link_encoder_disable_output( 301 struct link_encoder *enc, 302 enum signal_type signal); 303 304 /* set DP lane settings */ 305 void dcn10_link_encoder_dp_set_lane_settings( 306 struct link_encoder *enc, 307 const struct link_training_settings *link_settings); 308 309 void dcn10_link_encoder_dp_set_phy_pattern( 310 struct link_encoder *enc, 311 const struct encoder_set_dp_phy_pattern_param *param); 312 313 /* programs DP MST VC payload allocation */ 314 void dcn10_link_encoder_update_mst_stream_allocation_table( 315 struct link_encoder *enc, 316 const struct link_mst_stream_allocation_table *table); 317 318 void dcn10_link_encoder_connect_dig_be_to_fe( 319 struct link_encoder *enc, 320 enum engine_id engine, 321 bool connect); 322 323 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( 324 struct link_encoder *enc, 325 uint32_t index); 326 327 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc); 328 329 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc); 330 331 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 332 bool exit_link_training_required); 333 334 void dcn10_psr_program_secondary_packet(struct link_encoder *enc, 335 unsigned int sdp_transmit_line_num_deadline); 336 337 bool dcn10_is_dig_enabled(struct link_encoder *enc); 338 339 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10); 340 341 #endif /* __DC_LINK_ENCODER__DCN10_H__ */ 342