1b843c749SSergey Zigachev /*
2b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3b843c749SSergey Zigachev *
4b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10b843c749SSergey Zigachev *
11b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13b843c749SSergey Zigachev *
14b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21b843c749SSergey Zigachev *
22b843c749SSergey Zigachev * Authors: AMD
23b843c749SSergey Zigachev *
24b843c749SSergey Zigachev */
25b843c749SSergey Zigachev
26b843c749SSergey Zigachev #include "dm_services.h"
27b843c749SSergey Zigachev #include "dcn10_opp.h"
28b843c749SSergey Zigachev #include "reg_helper.h"
29b843c749SSergey Zigachev
30b843c749SSergey Zigachev #define REG(reg) \
31b843c749SSergey Zigachev (oppn10->regs->reg)
32b843c749SSergey Zigachev
33b843c749SSergey Zigachev #undef FN
34b843c749SSergey Zigachev #define FN(reg_name, field_name) \
35b843c749SSergey Zigachev oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
36b843c749SSergey Zigachev
37b843c749SSergey Zigachev #define CTX \
38b843c749SSergey Zigachev oppn10->base.ctx
39b843c749SSergey Zigachev
40b843c749SSergey Zigachev
41b843c749SSergey Zigachev /************* FORMATTER ************/
42b843c749SSergey Zigachev
43b843c749SSergey Zigachev /**
44b843c749SSergey Zigachev * set_truncation
45b843c749SSergey Zigachev * 1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
46b843c749SSergey Zigachev * 2) enable truncation
47b843c749SSergey Zigachev * 3) HW remove 12bit FMT support for DCE11 power saving reason.
48b843c749SSergey Zigachev */
opp1_set_truncation(struct dcn10_opp * oppn10,const struct bit_depth_reduction_params * params)49b843c749SSergey Zigachev static void opp1_set_truncation(
50b843c749SSergey Zigachev struct dcn10_opp *oppn10,
51b843c749SSergey Zigachev const struct bit_depth_reduction_params *params)
52b843c749SSergey Zigachev {
53b843c749SSergey Zigachev REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
54b843c749SSergey Zigachev FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
55b843c749SSergey Zigachev FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
56b843c749SSergey Zigachev FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
57b843c749SSergey Zigachev }
58b843c749SSergey Zigachev
opp1_set_spatial_dither(struct dcn10_opp * oppn10,const struct bit_depth_reduction_params * params)59b843c749SSergey Zigachev static void opp1_set_spatial_dither(
60b843c749SSergey Zigachev struct dcn10_opp *oppn10,
61b843c749SSergey Zigachev const struct bit_depth_reduction_params *params)
62b843c749SSergey Zigachev {
63b843c749SSergey Zigachev /*Disable spatial (random) dithering*/
64b843c749SSergey Zigachev REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
65b843c749SSergey Zigachev FMT_SPATIAL_DITHER_EN, 0,
66b843c749SSergey Zigachev FMT_SPATIAL_DITHER_MODE, 0,
67b843c749SSergey Zigachev FMT_SPATIAL_DITHER_DEPTH, 0,
68b843c749SSergey Zigachev FMT_TEMPORAL_DITHER_EN, 0,
69b843c749SSergey Zigachev FMT_HIGHPASS_RANDOM_ENABLE, 0,
70b843c749SSergey Zigachev FMT_FRAME_RANDOM_ENABLE, 0,
71b843c749SSergey Zigachev FMT_RGB_RANDOM_ENABLE, 0);
72b843c749SSergey Zigachev
73b843c749SSergey Zigachev
74b843c749SSergey Zigachev /* only use FRAME_COUNTER_MAX if frameRandom == 1*/
75b843c749SSergey Zigachev if (params->flags.FRAME_RANDOM == 1) {
76b843c749SSergey Zigachev if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
77b843c749SSergey Zigachev REG_UPDATE_2(FMT_CONTROL,
78b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
79b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
80b843c749SSergey Zigachev } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
81b843c749SSergey Zigachev REG_UPDATE_2(FMT_CONTROL,
82b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
83b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
84b843c749SSergey Zigachev } else {
85b843c749SSergey Zigachev return;
86b843c749SSergey Zigachev }
87b843c749SSergey Zigachev } else {
88b843c749SSergey Zigachev REG_UPDATE_2(FMT_CONTROL,
89b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
90b843c749SSergey Zigachev FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
91b843c749SSergey Zigachev }
92b843c749SSergey Zigachev
93b843c749SSergey Zigachev /*Set seed for random values for
94b843c749SSergey Zigachev * spatial dithering for R,G,B channels*/
95b843c749SSergey Zigachev
96b843c749SSergey Zigachev REG_SET(FMT_DITHER_RAND_R_SEED, 0,
97b843c749SSergey Zigachev FMT_RAND_R_SEED, params->r_seed_value);
98b843c749SSergey Zigachev
99b843c749SSergey Zigachev REG_SET(FMT_DITHER_RAND_G_SEED, 0,
100b843c749SSergey Zigachev FMT_RAND_G_SEED, params->g_seed_value);
101b843c749SSergey Zigachev
102b843c749SSergey Zigachev REG_SET(FMT_DITHER_RAND_B_SEED, 0,
103b843c749SSergey Zigachev FMT_RAND_B_SEED, params->b_seed_value);
104b843c749SSergey Zigachev
105b843c749SSergey Zigachev /* FMT_OFFSET_R_Cr 31:16 0x0 Setting the zero
106b843c749SSergey Zigachev * offset for the R/Cr channel, lower 4LSB
107b843c749SSergey Zigachev * is forced to zeros. Typically set to 0
108b843c749SSergey Zigachev * RGB and 0x80000 YCbCr.
109b843c749SSergey Zigachev */
110b843c749SSergey Zigachev /* FMT_OFFSET_G_Y 31:16 0x0 Setting the zero
111b843c749SSergey Zigachev * offset for the G/Y channel, lower 4LSB is
112b843c749SSergey Zigachev * forced to zeros. Typically set to 0 RGB
113b843c749SSergey Zigachev * and 0x80000 YCbCr.
114b843c749SSergey Zigachev */
115b843c749SSergey Zigachev /* FMT_OFFSET_B_Cb 31:16 0x0 Setting the zero
116b843c749SSergey Zigachev * offset for the B/Cb channel, lower 4LSB is
117b843c749SSergey Zigachev * forced to zeros. Typically set to 0 RGB and
118b843c749SSergey Zigachev * 0x80000 YCbCr.
119b843c749SSergey Zigachev */
120b843c749SSergey Zigachev
121b843c749SSergey Zigachev REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
122b843c749SSergey Zigachev /*Enable spatial dithering*/
123b843c749SSergey Zigachev FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
124b843c749SSergey Zigachev /* Set spatial dithering mode
125b843c749SSergey Zigachev * (default is Seed patterrn AAAA...)
126b843c749SSergey Zigachev */
127b843c749SSergey Zigachev FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
128b843c749SSergey Zigachev /*Set spatial dithering bit depth*/
129b843c749SSergey Zigachev FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
130b843c749SSergey Zigachev /*Disable High pass filter*/
131b843c749SSergey Zigachev FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
132b843c749SSergey Zigachev /*Reset only at startup*/
133b843c749SSergey Zigachev FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
134b843c749SSergey Zigachev /*Set RGB data dithered with x^28+x^3+1*/
135b843c749SSergey Zigachev FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
136b843c749SSergey Zigachev }
137b843c749SSergey Zigachev
opp1_program_bit_depth_reduction(struct output_pixel_processor * opp,const struct bit_depth_reduction_params * params)138b843c749SSergey Zigachev void opp1_program_bit_depth_reduction(
139b843c749SSergey Zigachev struct output_pixel_processor *opp,
140b843c749SSergey Zigachev const struct bit_depth_reduction_params *params)
141b843c749SSergey Zigachev {
142b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
143b843c749SSergey Zigachev
144b843c749SSergey Zigachev opp1_set_truncation(oppn10, params);
145b843c749SSergey Zigachev opp1_set_spatial_dither(oppn10, params);
146b843c749SSergey Zigachev /* TODO
147b843c749SSergey Zigachev * set_temporal_dither(oppn10, params);
148b843c749SSergey Zigachev */
149b843c749SSergey Zigachev }
150b843c749SSergey Zigachev
151b843c749SSergey Zigachev /**
152b843c749SSergey Zigachev * set_pixel_encoding
153b843c749SSergey Zigachev *
154b843c749SSergey Zigachev * Set Pixel Encoding
155b843c749SSergey Zigachev * 0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
156b843c749SSergey Zigachev * 1: YCbCr 4:2:2
157b843c749SSergey Zigachev */
opp1_set_pixel_encoding(struct dcn10_opp * oppn10,const struct clamping_and_pixel_encoding_params * params)158b843c749SSergey Zigachev static void opp1_set_pixel_encoding(
159b843c749SSergey Zigachev struct dcn10_opp *oppn10,
160b843c749SSergey Zigachev const struct clamping_and_pixel_encoding_params *params)
161b843c749SSergey Zigachev {
162b843c749SSergey Zigachev switch (params->pixel_encoding) {
163b843c749SSergey Zigachev
164b843c749SSergey Zigachev case PIXEL_ENCODING_RGB:
165b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR444:
166b843c749SSergey Zigachev REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
167b843c749SSergey Zigachev break;
168b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR422:
169b843c749SSergey Zigachev REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
170b843c749SSergey Zigachev break;
171b843c749SSergey Zigachev case PIXEL_ENCODING_YCBCR420:
172b843c749SSergey Zigachev REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
173b843c749SSergey Zigachev break;
174b843c749SSergey Zigachev default:
175b843c749SSergey Zigachev break;
176b843c749SSergey Zigachev }
177b843c749SSergey Zigachev }
178b843c749SSergey Zigachev
179b843c749SSergey Zigachev /**
180b843c749SSergey Zigachev * Set Clamping
181b843c749SSergey Zigachev * 1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
182b843c749SSergey Zigachev * 1 for 8 bpc
183b843c749SSergey Zigachev * 2 for 10 bpc
184b843c749SSergey Zigachev * 3 for 12 bpc
185b843c749SSergey Zigachev * 7 for programable
186b843c749SSergey Zigachev * 2) Enable clamp if Limited range requested
187b843c749SSergey Zigachev */
opp1_set_clamping(struct dcn10_opp * oppn10,const struct clamping_and_pixel_encoding_params * params)188b843c749SSergey Zigachev static void opp1_set_clamping(
189b843c749SSergey Zigachev struct dcn10_opp *oppn10,
190b843c749SSergey Zigachev const struct clamping_and_pixel_encoding_params *params)
191b843c749SSergey Zigachev {
192b843c749SSergey Zigachev REG_UPDATE_2(FMT_CLAMP_CNTL,
193b843c749SSergey Zigachev FMT_CLAMP_DATA_EN, 0,
194b843c749SSergey Zigachev FMT_CLAMP_COLOR_FORMAT, 0);
195b843c749SSergey Zigachev
196b843c749SSergey Zigachev switch (params->clamping_level) {
197b843c749SSergey Zigachev case CLAMPING_FULL_RANGE:
198b843c749SSergey Zigachev REG_UPDATE_2(FMT_CLAMP_CNTL,
199b843c749SSergey Zigachev FMT_CLAMP_DATA_EN, 1,
200b843c749SSergey Zigachev FMT_CLAMP_COLOR_FORMAT, 0);
201b843c749SSergey Zigachev break;
202b843c749SSergey Zigachev case CLAMPING_LIMITED_RANGE_8BPC:
203b843c749SSergey Zigachev REG_UPDATE_2(FMT_CLAMP_CNTL,
204b843c749SSergey Zigachev FMT_CLAMP_DATA_EN, 1,
205b843c749SSergey Zigachev FMT_CLAMP_COLOR_FORMAT, 1);
206b843c749SSergey Zigachev break;
207b843c749SSergey Zigachev case CLAMPING_LIMITED_RANGE_10BPC:
208b843c749SSergey Zigachev REG_UPDATE_2(FMT_CLAMP_CNTL,
209b843c749SSergey Zigachev FMT_CLAMP_DATA_EN, 1,
210b843c749SSergey Zigachev FMT_CLAMP_COLOR_FORMAT, 2);
211b843c749SSergey Zigachev
212b843c749SSergey Zigachev break;
213b843c749SSergey Zigachev case CLAMPING_LIMITED_RANGE_12BPC:
214b843c749SSergey Zigachev REG_UPDATE_2(FMT_CLAMP_CNTL,
215b843c749SSergey Zigachev FMT_CLAMP_DATA_EN, 1,
216b843c749SSergey Zigachev FMT_CLAMP_COLOR_FORMAT, 3);
217b843c749SSergey Zigachev break;
218b843c749SSergey Zigachev case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
219b843c749SSergey Zigachev /* TODO */
220b843c749SSergey Zigachev default:
221b843c749SSergey Zigachev break;
222b843c749SSergey Zigachev }
223b843c749SSergey Zigachev
224b843c749SSergey Zigachev }
225b843c749SSergey Zigachev
opp1_set_dyn_expansion(struct output_pixel_processor * opp,enum dc_color_space color_sp,enum dc_color_depth color_dpth,enum signal_type signal)226b843c749SSergey Zigachev void opp1_set_dyn_expansion(
227b843c749SSergey Zigachev struct output_pixel_processor *opp,
228b843c749SSergey Zigachev enum dc_color_space color_sp,
229b843c749SSergey Zigachev enum dc_color_depth color_dpth,
230b843c749SSergey Zigachev enum signal_type signal)
231b843c749SSergey Zigachev {
232b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
233b843c749SSergey Zigachev
234b843c749SSergey Zigachev REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
235b843c749SSergey Zigachev FMT_DYNAMIC_EXP_EN, 0,
236b843c749SSergey Zigachev FMT_DYNAMIC_EXP_MODE, 0);
237b843c749SSergey Zigachev
238b843c749SSergey Zigachev /*00 - 10-bit -> 12-bit dynamic expansion*/
239b843c749SSergey Zigachev /*01 - 8-bit -> 12-bit dynamic expansion*/
240b843c749SSergey Zigachev if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
241b843c749SSergey Zigachev signal == SIGNAL_TYPE_DISPLAY_PORT ||
242b843c749SSergey Zigachev signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
243b843c749SSergey Zigachev signal == SIGNAL_TYPE_VIRTUAL) {
244b843c749SSergey Zigachev switch (color_dpth) {
245b843c749SSergey Zigachev case COLOR_DEPTH_888:
246b843c749SSergey Zigachev REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
247b843c749SSergey Zigachev FMT_DYNAMIC_EXP_EN, 1,
248b843c749SSergey Zigachev FMT_DYNAMIC_EXP_MODE, 1);
249b843c749SSergey Zigachev break;
250b843c749SSergey Zigachev case COLOR_DEPTH_101010:
251b843c749SSergey Zigachev REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
252b843c749SSergey Zigachev FMT_DYNAMIC_EXP_EN, 1,
253b843c749SSergey Zigachev FMT_DYNAMIC_EXP_MODE, 0);
254b843c749SSergey Zigachev break;
255b843c749SSergey Zigachev case COLOR_DEPTH_121212:
256b843c749SSergey Zigachev REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
257b843c749SSergey Zigachev FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
258b843c749SSergey Zigachev FMT_DYNAMIC_EXP_MODE, 0);
259b843c749SSergey Zigachev break;
260b843c749SSergey Zigachev default:
261b843c749SSergey Zigachev break;
262b843c749SSergey Zigachev }
263b843c749SSergey Zigachev }
264b843c749SSergey Zigachev }
265b843c749SSergey Zigachev
opp1_program_clamping_and_pixel_encoding(struct output_pixel_processor * opp,const struct clamping_and_pixel_encoding_params * params)266b843c749SSergey Zigachev static void opp1_program_clamping_and_pixel_encoding(
267b843c749SSergey Zigachev struct output_pixel_processor *opp,
268b843c749SSergey Zigachev const struct clamping_and_pixel_encoding_params *params)
269b843c749SSergey Zigachev {
270b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
271b843c749SSergey Zigachev
272b843c749SSergey Zigachev opp1_set_clamping(oppn10, params);
273b843c749SSergey Zigachev opp1_set_pixel_encoding(oppn10, params);
274b843c749SSergey Zigachev }
275b843c749SSergey Zigachev
opp1_program_fmt(struct output_pixel_processor * opp,struct bit_depth_reduction_params * fmt_bit_depth,struct clamping_and_pixel_encoding_params * clamping)276b843c749SSergey Zigachev void opp1_program_fmt(
277b843c749SSergey Zigachev struct output_pixel_processor *opp,
278b843c749SSergey Zigachev struct bit_depth_reduction_params *fmt_bit_depth,
279b843c749SSergey Zigachev struct clamping_and_pixel_encoding_params *clamping)
280b843c749SSergey Zigachev {
281b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
282b843c749SSergey Zigachev
283b843c749SSergey Zigachev if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
284b843c749SSergey Zigachev REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
285b843c749SSergey Zigachev
286b843c749SSergey Zigachev /* dithering is affected by <CrtcSourceSelect>, hence should be
287b843c749SSergey Zigachev * programmed afterwards */
288b843c749SSergey Zigachev opp1_program_bit_depth_reduction(
289b843c749SSergey Zigachev opp,
290b843c749SSergey Zigachev fmt_bit_depth);
291b843c749SSergey Zigachev
292b843c749SSergey Zigachev opp1_program_clamping_and_pixel_encoding(
293b843c749SSergey Zigachev opp,
294b843c749SSergey Zigachev clamping);
295b843c749SSergey Zigachev
296b843c749SSergey Zigachev return;
297b843c749SSergey Zigachev }
298b843c749SSergey Zigachev
opp1_program_stereo(struct output_pixel_processor * opp,bool enable,const struct dc_crtc_timing * timing)299b843c749SSergey Zigachev void opp1_program_stereo(
300b843c749SSergey Zigachev struct output_pixel_processor *opp,
301b843c749SSergey Zigachev bool enable,
302b843c749SSergey Zigachev const struct dc_crtc_timing *timing)
303b843c749SSergey Zigachev {
304b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
305b843c749SSergey Zigachev
306b843c749SSergey Zigachev uint32_t active_width = timing->h_addressable - timing->h_border_right - timing->h_border_right;
307b843c749SSergey Zigachev uint32_t space1_size = timing->v_total - timing->v_addressable;
308b843c749SSergey Zigachev /* TODO: confirm computation of space2_size */
309b843c749SSergey Zigachev uint32_t space2_size = timing->v_total - timing->v_addressable;
310b843c749SSergey Zigachev
311b843c749SSergey Zigachev if (!enable) {
312b843c749SSergey Zigachev active_width = 0;
313b843c749SSergey Zigachev space1_size = 0;
314b843c749SSergey Zigachev space2_size = 0;
315b843c749SSergey Zigachev }
316b843c749SSergey Zigachev
317b843c749SSergey Zigachev /* TODO: for which cases should FMT_STEREOSYNC_OVERRIDE be set? */
318b843c749SSergey Zigachev REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, 0);
319b843c749SSergey Zigachev
320b843c749SSergey Zigachev REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, active_width);
321b843c749SSergey Zigachev
322b843c749SSergey Zigachev /* Program OPPBUF_3D_VACT_SPACE1_SIZE and OPPBUF_VACT_SPACE2_SIZE registers
323b843c749SSergey Zigachev * In 3D progressive frames, Vactive space happens only in between the 2 frames,
324b843c749SSergey Zigachev * so only need to program OPPBUF_3D_VACT_SPACE1_SIZE
325b843c749SSergey Zigachev * In 3D alternative frames, left and right frames, top and bottom field.
326b843c749SSergey Zigachev */
327b843c749SSergey Zigachev if (timing->timing_3d_format == TIMING_3D_FORMAT_FRAME_ALTERNATE)
328b843c749SSergey Zigachev REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, space2_size);
329b843c749SSergey Zigachev else
330b843c749SSergey Zigachev REG_UPDATE(OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, space1_size);
331b843c749SSergey Zigachev
332b843c749SSergey Zigachev /* TODO: Is programming of OPPBUF_DUMMY_DATA_R/G/B needed? */
333b843c749SSergey Zigachev /*
334b843c749SSergey Zigachev REG_UPDATE(OPPBUF_3D_PARAMETERS_0,
335b843c749SSergey Zigachev OPPBUF_DUMMY_DATA_R, data_r);
336b843c749SSergey Zigachev REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
337b843c749SSergey Zigachev OPPBUF_DUMMY_DATA_G, data_g);
338b843c749SSergey Zigachev REG_UPDATE(OPPBUF_3D_PARAMETERS_1,
339b843c749SSergey Zigachev OPPBUF_DUMMY_DATA_B, _data_b);
340b843c749SSergey Zigachev */
341b843c749SSergey Zigachev }
342b843c749SSergey Zigachev
343*78973132SSergey Zigachev #if 0
344b843c749SSergey Zigachev void opp1_program_oppbuf(
345b843c749SSergey Zigachev struct output_pixel_processor *opp,
346b843c749SSergey Zigachev struct oppbuf_params *oppbuf)
347b843c749SSergey Zigachev {
348b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
349b843c749SSergey Zigachev
350b843c749SSergey Zigachev /* Program the oppbuf active width to be the frame width from mpc */
351b843c749SSergey Zigachev REG_UPDATE(OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, oppbuf->active_width);
352b843c749SSergey Zigachev
353b843c749SSergey Zigachev /* Specifies the number of segments in multi-segment mode (DP-MSO operation)
354b843c749SSergey Zigachev * description "In 1/2/4 segment mode, specifies the horizontal active width in pixels of the display panel.
355b843c749SSergey Zigachev * In 4 segment split left/right mode, specifies the horizontal 1/2 active width in pixels of the display panel.
356b843c749SSergey Zigachev * Used to determine segment boundaries in multi-segment mode. Used to determine the width of the vertical active space in 3D frame packed modes.
357b843c749SSergey Zigachev * OPPBUF_ACTIVE_WIDTH must be integer divisible by the total number of segments."
358b843c749SSergey Zigachev */
359b843c749SSergey Zigachev REG_UPDATE(OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, oppbuf->mso_segmentation);
360b843c749SSergey Zigachev
361b843c749SSergey Zigachev /* description "Specifies the number of overlap pixels (1-8 overlapping pixels supported), used in multi-segment mode (DP-MSO operation)" */
362b843c749SSergey Zigachev REG_UPDATE(OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, oppbuf->mso_overlap_pixel_num);
363b843c749SSergey Zigachev
364b843c749SSergey Zigachev /* description "Specifies the number of times a pixel is replicated (0-15 pixel replications supported).
365b843c749SSergey Zigachev * A value of 0 disables replication. The total number of times a pixel is output is OPPBUF_PIXEL_REPETITION + 1."
366b843c749SSergey Zigachev */
367b843c749SSergey Zigachev REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, oppbuf->pixel_repetition);
368b843c749SSergey Zigachev
369b843c749SSergey Zigachev }
370*78973132SSergey Zigachev #endif
371b843c749SSergey Zigachev
opp1_pipe_clock_control(struct output_pixel_processor * opp,bool enable)372b843c749SSergey Zigachev void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
373b843c749SSergey Zigachev {
374b843c749SSergey Zigachev struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
375b843c749SSergey Zigachev uint32_t regval = enable ? 1 : 0;
376b843c749SSergey Zigachev
377b843c749SSergey Zigachev REG_UPDATE(OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, regval);
378b843c749SSergey Zigachev }
379b843c749SSergey Zigachev
380b843c749SSergey Zigachev /*****************************************/
381b843c749SSergey Zigachev /* Constructor, Destructor */
382b843c749SSergey Zigachev /*****************************************/
383b843c749SSergey Zigachev
opp1_destroy(struct output_pixel_processor ** opp)384b843c749SSergey Zigachev void opp1_destroy(struct output_pixel_processor **opp)
385b843c749SSergey Zigachev {
386b843c749SSergey Zigachev kfree(TO_DCN10_OPP(*opp));
387b843c749SSergey Zigachev *opp = NULL;
388b843c749SSergey Zigachev }
389b843c749SSergey Zigachev
390b843c749SSergey Zigachev static const struct opp_funcs dcn10_opp_funcs = {
391b843c749SSergey Zigachev .opp_set_dyn_expansion = opp1_set_dyn_expansion,
392b843c749SSergey Zigachev .opp_program_fmt = opp1_program_fmt,
393b843c749SSergey Zigachev .opp_program_bit_depth_reduction = opp1_program_bit_depth_reduction,
394b843c749SSergey Zigachev .opp_program_stereo = opp1_program_stereo,
395b843c749SSergey Zigachev .opp_pipe_clock_control = opp1_pipe_clock_control,
396b843c749SSergey Zigachev .opp_destroy = opp1_destroy
397b843c749SSergey Zigachev };
398b843c749SSergey Zigachev
dcn10_opp_construct(struct dcn10_opp * oppn10,struct dc_context * ctx,uint32_t inst,const struct dcn10_opp_registers * regs,const struct dcn10_opp_shift * opp_shift,const struct dcn10_opp_mask * opp_mask)399b843c749SSergey Zigachev void dcn10_opp_construct(struct dcn10_opp *oppn10,
400b843c749SSergey Zigachev struct dc_context *ctx,
401b843c749SSergey Zigachev uint32_t inst,
402b843c749SSergey Zigachev const struct dcn10_opp_registers *regs,
403b843c749SSergey Zigachev const struct dcn10_opp_shift *opp_shift,
404b843c749SSergey Zigachev const struct dcn10_opp_mask *opp_mask)
405b843c749SSergey Zigachev {
406b843c749SSergey Zigachev
407b843c749SSergey Zigachev oppn10->base.ctx = ctx;
408b843c749SSergey Zigachev oppn10->base.inst = inst;
409b843c749SSergey Zigachev oppn10->base.funcs = &dcn10_opp_funcs;
410b843c749SSergey Zigachev
411b843c749SSergey Zigachev oppn10->regs = regs;
412b843c749SSergey Zigachev oppn10->opp_shift = opp_shift;
413b843c749SSergey Zigachev oppn10->opp_mask = opp_mask;
414b843c749SSergey Zigachev }
415