1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #include "dc_bios_types.h" 28 #include "dcn10_stream_encoder.h" 29 #include "reg_helper.h" 30 #include "hw_shared.h" 31 32 #define DC_LOGGER \ 33 enc1->base.ctx->logger 34 35 36 #define REG(reg)\ 37 (enc1->regs->reg) 38 39 #undef FN 40 #define FN(reg_name, field_name) \ 41 enc1->se_shift->field_name, enc1->se_mask->field_name 42 43 #define VBI_LINE_0 0 44 #define DP_BLANK_MAX_RETRY 20 45 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 46 47 48 enum { 49 DP_MST_UPDATE_MAX_RETRY = 50 50 }; 51 52 #define CTX \ 53 enc1->base.ctx 54 55 void enc1_update_generic_info_packet( 56 struct dcn10_stream_encoder *enc1, 57 uint32_t packet_index, 58 const struct dc_info_packet *info_packet) 59 { 60 uint32_t regval; 61 /* TODOFPGA Figure out a proper number for max_retries polling for lock 62 * use 50 for now. 63 */ 64 uint32_t max_retries = 50; 65 66 /*we need turn on clock before programming AFMT block*/ 67 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 68 69 if (packet_index >= 8) 70 ASSERT(0); 71 72 /* poll dig_update_lock is not locked -> asic internal signal 73 * assume otg master lock will unlock it 74 */ 75 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 76 0, 10, max_retries);*/ 77 78 /* check if HW reading GSP memory */ 79 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 80 0, 10, max_retries); 81 82 /* HW does is not reading GSP memory not reading too long -> 83 * something wrong. clear GPS memory access and notify? 84 * hw SW is writing to GSP memory 85 */ 86 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 87 88 /* choose which generic packet to use */ 89 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 90 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 91 AFMT_GENERIC_INDEX, packet_index); 92 93 /* write generic packet header 94 * (4th byte is for GENERIC0 only) 95 */ 96 REG_SET_4(AFMT_GENERIC_HDR, 0, 97 AFMT_GENERIC_HB0, info_packet->hb0, 98 AFMT_GENERIC_HB1, info_packet->hb1, 99 AFMT_GENERIC_HB2, info_packet->hb2, 100 AFMT_GENERIC_HB3, info_packet->hb3); 101 102 /* write generic packet contents 103 * (we never use last 4 bytes) 104 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers 105 */ 106 { 107 const uint32_t *content = 108 (const uint32_t *) &info_packet->sb[0]; 109 110 REG_WRITE(AFMT_GENERIC_0, *content++); 111 REG_WRITE(AFMT_GENERIC_1, *content++); 112 REG_WRITE(AFMT_GENERIC_2, *content++); 113 REG_WRITE(AFMT_GENERIC_3, *content++); 114 REG_WRITE(AFMT_GENERIC_4, *content++); 115 REG_WRITE(AFMT_GENERIC_5, *content++); 116 REG_WRITE(AFMT_GENERIC_6, *content++); 117 REG_WRITE(AFMT_GENERIC_7, *content); 118 } 119 120 switch (packet_index) { 121 case 0: 122 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 123 AFMT_GENERIC0_FRAME_UPDATE, 1); 124 break; 125 case 1: 126 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 127 AFMT_GENERIC1_FRAME_UPDATE, 1); 128 break; 129 case 2: 130 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 131 AFMT_GENERIC2_FRAME_UPDATE, 1); 132 break; 133 case 3: 134 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 135 AFMT_GENERIC3_FRAME_UPDATE, 1); 136 break; 137 case 4: 138 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 139 AFMT_GENERIC4_FRAME_UPDATE, 1); 140 break; 141 case 5: 142 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 143 AFMT_GENERIC5_FRAME_UPDATE, 1); 144 break; 145 case 6: 146 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 147 AFMT_GENERIC6_FRAME_UPDATE, 1); 148 break; 149 case 7: 150 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 151 AFMT_GENERIC7_FRAME_UPDATE, 1); 152 break; 153 default: 154 break; 155 } 156 } 157 158 static void enc1_update_hdmi_info_packet( 159 struct dcn10_stream_encoder *enc1, 160 uint32_t packet_index, 161 const struct dc_info_packet *info_packet) 162 { 163 uint32_t cont, send, line; 164 165 if (info_packet->valid) { 166 enc1_update_generic_info_packet( 167 enc1, 168 packet_index, 169 info_packet); 170 171 /* enable transmission of packet(s) - 172 * packet transmission begins on the next frame 173 */ 174 cont = 1; 175 /* send packet(s) every frame */ 176 send = 1; 177 /* select line number to send packets on */ 178 line = 2; 179 } else { 180 cont = 0; 181 send = 0; 182 line = 0; 183 } 184 185 /* choose which generic packet control to use */ 186 switch (packet_index) { 187 case 0: 188 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 189 HDMI_GENERIC0_CONT, cont, 190 HDMI_GENERIC0_SEND, send, 191 HDMI_GENERIC0_LINE, line); 192 break; 193 case 1: 194 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 195 HDMI_GENERIC1_CONT, cont, 196 HDMI_GENERIC1_SEND, send, 197 HDMI_GENERIC1_LINE, line); 198 break; 199 case 2: 200 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 201 HDMI_GENERIC0_CONT, cont, 202 HDMI_GENERIC0_SEND, send, 203 HDMI_GENERIC0_LINE, line); 204 break; 205 case 3: 206 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 207 HDMI_GENERIC1_CONT, cont, 208 HDMI_GENERIC1_SEND, send, 209 HDMI_GENERIC1_LINE, line); 210 break; 211 case 4: 212 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 213 HDMI_GENERIC0_CONT, cont, 214 HDMI_GENERIC0_SEND, send, 215 HDMI_GENERIC0_LINE, line); 216 break; 217 case 5: 218 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 219 HDMI_GENERIC1_CONT, cont, 220 HDMI_GENERIC1_SEND, send, 221 HDMI_GENERIC1_LINE, line); 222 break; 223 case 6: 224 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 225 HDMI_GENERIC0_CONT, cont, 226 HDMI_GENERIC0_SEND, send, 227 HDMI_GENERIC0_LINE, line); 228 break; 229 case 7: 230 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 231 HDMI_GENERIC1_CONT, cont, 232 HDMI_GENERIC1_SEND, send, 233 HDMI_GENERIC1_LINE, line); 234 break; 235 default: 236 /* invalid HW packet index */ 237 DC_LOG_WARNING( 238 "Invalid HW packet index: %s()\n", 239 __func__); 240 return; 241 } 242 } 243 244 /* setup stream encoder in dp mode */ 245 void enc1_stream_encoder_dp_set_stream_attribute( 246 struct stream_encoder *enc, 247 struct dc_crtc_timing *crtc_timing, 248 enum dc_color_space output_color_space) 249 { 250 uint32_t h_active_start; 251 uint32_t v_active_start; 252 uint32_t misc0 = 0; 253 uint32_t misc1 = 0; 254 uint32_t h_blank; 255 uint32_t h_back_porch; 256 uint8_t synchronous_clock = 0; /* asynchronous mode */ 257 uint8_t colorimetry_bpc; 258 uint8_t dynamic_range_rgb = 0; /*full range*/ 259 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 260 uint8_t dp_pixel_encoding = 0; 261 uint8_t dp_component_depth = 0; 262 263 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 264 265 /* set pixel encoding */ 266 switch (crtc_timing->pixel_encoding) { 267 case PIXEL_ENCODING_YCBCR422: 268 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR422; 269 break; 270 case PIXEL_ENCODING_YCBCR444: 271 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR444; 272 273 if (crtc_timing->flags.Y_ONLY) 274 if (crtc_timing->display_color_depth != COLOR_DEPTH_666) 275 /* HW testing only, no use case yet. 276 * Color depth of Y-only could be 277 * 8, 10, 12, 16 bits 278 */ 279 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_Y_ONLY; 280 281 /* Note: DP_MSA_MISC1 bit 7 is the indicator 282 * of Y-only mode. 283 * This bit is set in HW if register 284 * DP_PIXEL_ENCODING is programmed to 0x4 285 */ 286 break; 287 case PIXEL_ENCODING_YCBCR420: 288 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_YCBCR420; 289 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 290 break; 291 default: 292 dp_pixel_encoding = DP_PIXEL_ENCODING_TYPE_RGB444; 293 break; 294 } 295 296 misc1 = REG_READ(DP_MSA_MISC); 297 /* For YCbCr420 and BT2020 Colorimetry Formats, VSC SDP shall be used. 298 * When MISC1, bit 6, is Set to 1, a Source device uses a VSC SDP to indicate the 299 * Pixel Encoding/Colorimetry Format and that a Sink device shall ignore MISC1, bit 7, 300 * and MISC0, bits 7:1 (MISC1, bit 7, and MISC0, bits 7:1, become "don't care"). 301 */ 302 if ((crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) || 303 (output_color_space == COLOR_SPACE_2020_YCBCR) || 304 (output_color_space == COLOR_SPACE_2020_RGB_FULLRANGE) || 305 (output_color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)) 306 misc1 = misc1 | 0x40; 307 else 308 misc1 = misc1 & ~0x40; 309 310 /* set color depth */ 311 switch (crtc_timing->display_color_depth) { 312 case COLOR_DEPTH_666: 313 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 314 break; 315 case COLOR_DEPTH_888: 316 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_8BPC; 317 break; 318 case COLOR_DEPTH_101010: 319 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_10BPC; 320 break; 321 case COLOR_DEPTH_121212: 322 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_12BPC; 323 break; 324 case COLOR_DEPTH_161616: 325 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_16BPC; 326 break; 327 default: 328 dp_component_depth = DP_COMPONENT_PIXEL_DEPTH_6BPC; 329 break; 330 } 331 332 /* Set DP pixel encoding and component depth */ 333 REG_UPDATE_2(DP_PIXEL_FORMAT, 334 DP_PIXEL_ENCODING, dp_pixel_encoding, 335 DP_COMPONENT_DEPTH, dp_component_depth); 336 337 /* set dynamic range and YCbCr range */ 338 339 switch (crtc_timing->display_color_depth) { 340 case COLOR_DEPTH_666: 341 colorimetry_bpc = 0; 342 break; 343 case COLOR_DEPTH_888: 344 colorimetry_bpc = 1; 345 break; 346 case COLOR_DEPTH_101010: 347 colorimetry_bpc = 2; 348 break; 349 case COLOR_DEPTH_121212: 350 colorimetry_bpc = 3; 351 break; 352 default: 353 colorimetry_bpc = 0; 354 break; 355 } 356 357 misc0 = misc0 | synchronous_clock; 358 misc0 = colorimetry_bpc << 5; 359 360 switch (output_color_space) { 361 case COLOR_SPACE_SRGB: 362 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 363 dynamic_range_rgb = 0; /*full range*/ 364 break; 365 case COLOR_SPACE_SRGB_LIMITED: 366 misc0 = misc0 | 0x8; /* bit3=1 */ 367 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 368 dynamic_range_rgb = 1; /*limited range*/ 369 break; 370 case COLOR_SPACE_YCBCR601: 371 case COLOR_SPACE_YCBCR601_LIMITED: 372 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 373 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 374 dynamic_range_ycbcr = 0; /*bt601*/ 375 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 376 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 377 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 378 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 379 break; 380 case COLOR_SPACE_YCBCR709: 381 case COLOR_SPACE_YCBCR709_LIMITED: 382 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 383 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 384 dynamic_range_ycbcr = 1; /*bt709*/ 385 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 386 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 387 else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) 388 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 389 break; 390 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 391 dynamic_range_rgb = 1; /*limited range*/ 392 break; 393 case COLOR_SPACE_2020_RGB_FULLRANGE: 394 case COLOR_SPACE_2020_YCBCR: 395 case COLOR_SPACE_XR_RGB: 396 case COLOR_SPACE_MSREF_SCRGB: 397 case COLOR_SPACE_ADOBERGB: 398 case COLOR_SPACE_DCIP3: 399 case COLOR_SPACE_XV_YCC_709: 400 case COLOR_SPACE_XV_YCC_601: 401 case COLOR_SPACE_DISPLAYNATIVE: 402 case COLOR_SPACE_DOLBYVISION: 403 case COLOR_SPACE_APPCTRL: 404 case COLOR_SPACE_CUSTOMPOINTS: 405 case COLOR_SPACE_UNKNOWN: 406 /* do nothing */ 407 break; 408 } 409 410 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 411 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 412 413 /* dcn new register 414 * dc_crtc_timing is vesa dmt struct. data from edid 415 */ 416 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 417 DP_MSA_HTOTAL, crtc_timing->h_total, 418 DP_MSA_VTOTAL, crtc_timing->v_total); 419 420 /* calculate from vesa timing parameters 421 * h_active_start related to leading edge of sync 422 */ 423 424 h_blank = crtc_timing->h_total - crtc_timing->h_border_left - 425 crtc_timing->h_addressable - crtc_timing->h_border_right; 426 427 h_back_porch = h_blank - crtc_timing->h_front_porch - 428 crtc_timing->h_sync_width; 429 430 /* start at beginning of left border */ 431 h_active_start = crtc_timing->h_sync_width + h_back_porch; 432 433 434 v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - 435 crtc_timing->v_addressable - crtc_timing->v_border_bottom - 436 crtc_timing->v_front_porch; 437 438 439 /* start at beginning of left border */ 440 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 441 DP_MSA_HSTART, h_active_start, 442 DP_MSA_VSTART, v_active_start); 443 444 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 445 DP_MSA_HSYNCWIDTH, 446 crtc_timing->h_sync_width, 447 DP_MSA_HSYNCPOLARITY, 448 !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, 449 DP_MSA_VSYNCWIDTH, 450 crtc_timing->v_sync_width, 451 DP_MSA_VSYNCPOLARITY, 452 !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); 453 454 /* HWDITH include border or overscan */ 455 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 456 DP_MSA_HWIDTH, crtc_timing->h_border_left + 457 crtc_timing->h_addressable + crtc_timing->h_border_right, 458 DP_MSA_VHEIGHT, crtc_timing->v_border_top + 459 crtc_timing->v_addressable + crtc_timing->v_border_bottom); 460 } 461 462 static void enc1_stream_encoder_set_stream_attribute_helper( 463 struct dcn10_stream_encoder *enc1, 464 struct dc_crtc_timing *crtc_timing) 465 { 466 switch (crtc_timing->pixel_encoding) { 467 case PIXEL_ENCODING_YCBCR422: 468 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 469 break; 470 default: 471 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 472 break; 473 } 474 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 475 } 476 477 /* setup stream encoder in hdmi mode */ 478 void enc1_stream_encoder_hdmi_set_stream_attribute( 479 struct stream_encoder *enc, 480 struct dc_crtc_timing *crtc_timing, 481 int actual_pix_clk_khz, 482 bool enable_audio) 483 { 484 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 485 struct bp_encoder_control cntl = {0}; 486 487 cntl.action = ENCODER_CONTROL_SETUP; 488 cntl.engine_id = enc1->base.id; 489 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 490 cntl.enable_dp_audio = enable_audio; 491 cntl.pixel_clock = actual_pix_clk_khz; 492 cntl.lanes_number = LANE_COUNT_FOUR; 493 494 if (enc1->base.bp->funcs->encoder_control( 495 enc1->base.bp, &cntl) != BP_RESULT_OK) 496 return; 497 498 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 499 500 /* setup HDMI engine */ 501 REG_UPDATE_5(HDMI_CONTROL, 502 HDMI_PACKET_GEN_VERSION, 1, 503 HDMI_KEEPOUT_MODE, 1, 504 HDMI_DEEP_COLOR_ENABLE, 0, 505 HDMI_DATA_SCRAMBLE_EN, 0, 506 HDMI_CLOCK_CHANNEL_RATE, 0); 507 508 509 switch (crtc_timing->display_color_depth) { 510 case COLOR_DEPTH_888: 511 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 512 break; 513 case COLOR_DEPTH_101010: 514 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 515 REG_UPDATE_2(HDMI_CONTROL, 516 HDMI_DEEP_COLOR_DEPTH, 1, 517 HDMI_DEEP_COLOR_ENABLE, 0); 518 } else { 519 REG_UPDATE_2(HDMI_CONTROL, 520 HDMI_DEEP_COLOR_DEPTH, 1, 521 HDMI_DEEP_COLOR_ENABLE, 1); 522 } 523 break; 524 case COLOR_DEPTH_121212: 525 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 526 REG_UPDATE_2(HDMI_CONTROL, 527 HDMI_DEEP_COLOR_DEPTH, 2, 528 HDMI_DEEP_COLOR_ENABLE, 0); 529 } else { 530 REG_UPDATE_2(HDMI_CONTROL, 531 HDMI_DEEP_COLOR_DEPTH, 2, 532 HDMI_DEEP_COLOR_ENABLE, 1); 533 } 534 break; 535 case COLOR_DEPTH_161616: 536 REG_UPDATE_2(HDMI_CONTROL, 537 HDMI_DEEP_COLOR_DEPTH, 3, 538 HDMI_DEEP_COLOR_ENABLE, 1); 539 break; 540 default: 541 break; 542 } 543 544 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 545 /* enable HDMI data scrambler 546 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 547 * Clock channel frequency is 1/4 of character rate. 548 */ 549 REG_UPDATE_2(HDMI_CONTROL, 550 HDMI_DATA_SCRAMBLE_EN, 1, 551 HDMI_CLOCK_CHANNEL_RATE, 1); 552 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 553 554 /* TODO: New feature for DCE11, still need to implement */ 555 556 /* enable HDMI data scrambler 557 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 558 * Clock channel frequency is the same 559 * as character rate 560 */ 561 REG_UPDATE_2(HDMI_CONTROL, 562 HDMI_DATA_SCRAMBLE_EN, 1, 563 HDMI_CLOCK_CHANNEL_RATE, 0); 564 } 565 566 567 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 568 HDMI_GC_CONT, 1, 569 HDMI_GC_SEND, 1, 570 HDMI_NULL_SEND, 1); 571 572 /* following belongs to audio */ 573 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 574 575 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 576 577 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 578 VBI_LINE_0 + 2); 579 580 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 581 } 582 583 /* setup stream encoder in dvi mode */ 584 void enc1_stream_encoder_dvi_set_stream_attribute( 585 struct stream_encoder *enc, 586 struct dc_crtc_timing *crtc_timing, 587 bool is_dual_link) 588 { 589 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 590 struct bp_encoder_control cntl = {0}; 591 592 cntl.action = ENCODER_CONTROL_SETUP; 593 cntl.engine_id = enc1->base.id; 594 cntl.signal = is_dual_link ? 595 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 596 cntl.enable_dp_audio = false; 597 cntl.pixel_clock = crtc_timing->pix_clk_khz; 598 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 599 600 if (enc1->base.bp->funcs->encoder_control( 601 enc1->base.bp, &cntl) != BP_RESULT_OK) 602 return; 603 604 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 605 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 606 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing); 607 } 608 609 void enc1_stream_encoder_set_mst_bandwidth( 610 struct stream_encoder *enc, 611 struct fixed31_32 avg_time_slots_per_mtp) 612 { 613 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 614 uint32_t x = dc_fixpt_floor( 615 avg_time_slots_per_mtp); 616 uint32_t y = dc_fixpt_ceil( 617 dc_fixpt_shl( 618 dc_fixpt_sub_int( 619 avg_time_slots_per_mtp, 620 x), 621 26)); 622 623 REG_SET_2(DP_MSE_RATE_CNTL, 0, 624 DP_MSE_RATE_X, x, 625 DP_MSE_RATE_Y, y); 626 627 /* wait for update to be completed on the link */ 628 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 629 /* is reset to 0 (not pending) */ 630 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 631 0, 632 10, DP_MST_UPDATE_MAX_RETRY); 633 } 634 635 static void enc1_stream_encoder_update_hdmi_info_packets( 636 struct stream_encoder *enc, 637 const struct encoder_info_frame *info_frame) 638 { 639 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 640 641 /* for bring up, disable dp double TODO */ 642 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 643 644 enc1_update_hdmi_info_packet(enc1, 0, &info_frame->avi); 645 enc1_update_hdmi_info_packet(enc1, 1, &info_frame->vendor); 646 enc1_update_hdmi_info_packet(enc1, 2, &info_frame->gamut); 647 enc1_update_hdmi_info_packet(enc1, 3, &info_frame->spd); 648 enc1_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd); 649 } 650 651 static void enc1_stream_encoder_stop_hdmi_info_packets( 652 struct stream_encoder *enc) 653 { 654 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 655 656 /* stop generic packets 0 & 1 on HDMI */ 657 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 658 HDMI_GENERIC1_CONT, 0, 659 HDMI_GENERIC1_LINE, 0, 660 HDMI_GENERIC1_SEND, 0, 661 HDMI_GENERIC0_CONT, 0, 662 HDMI_GENERIC0_LINE, 0, 663 HDMI_GENERIC0_SEND, 0); 664 665 /* stop generic packets 2 & 3 on HDMI */ 666 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 667 HDMI_GENERIC0_CONT, 0, 668 HDMI_GENERIC0_LINE, 0, 669 HDMI_GENERIC0_SEND, 0, 670 HDMI_GENERIC1_CONT, 0, 671 HDMI_GENERIC1_LINE, 0, 672 HDMI_GENERIC1_SEND, 0); 673 674 /* stop generic packets 2 & 3 on HDMI */ 675 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 676 HDMI_GENERIC0_CONT, 0, 677 HDMI_GENERIC0_LINE, 0, 678 HDMI_GENERIC0_SEND, 0, 679 HDMI_GENERIC1_CONT, 0, 680 HDMI_GENERIC1_LINE, 0, 681 HDMI_GENERIC1_SEND, 0); 682 683 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 684 HDMI_GENERIC0_CONT, 0, 685 HDMI_GENERIC0_LINE, 0, 686 HDMI_GENERIC0_SEND, 0, 687 HDMI_GENERIC1_CONT, 0, 688 HDMI_GENERIC1_LINE, 0, 689 HDMI_GENERIC1_SEND, 0); 690 } 691 692 void enc1_stream_encoder_update_dp_info_packets( 693 struct stream_encoder *enc, 694 const struct encoder_info_frame *info_frame) 695 { 696 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 697 uint32_t value = 0; 698 699 if (info_frame->vsc.valid) 700 enc1_update_generic_info_packet( 701 enc1, 702 0, /* packetIndex */ 703 &info_frame->vsc); 704 705 if (info_frame->spd.valid) 706 enc1_update_generic_info_packet( 707 enc1, 708 2, /* packetIndex */ 709 &info_frame->spd); 710 711 if (info_frame->hdrsmd.valid) 712 enc1_update_generic_info_packet( 713 enc1, 714 3, /* packetIndex */ 715 &info_frame->hdrsmd); 716 717 /* enable/disable transmission of packet(s). 718 * If enabled, packet transmission begins on the next frame 719 */ 720 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 721 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 722 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 723 724 725 /* This bit is the master enable bit. 726 * When enabling secondary stream engine, 727 * this master bit must also be set. 728 * This register shared with audio info frame. 729 * Therefore we need to enable master bit 730 * if at least on of the fields is not 0 731 */ 732 value = REG_READ(DP_SEC_CNTL); 733 if (value) 734 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 735 } 736 737 void enc1_stream_encoder_stop_dp_info_packets( 738 struct stream_encoder *enc) 739 { 740 /* stop generic packets on DP */ 741 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 742 uint32_t value = 0; 743 744 REG_SET_10(DP_SEC_CNTL, 0, 745 DP_SEC_GSP0_ENABLE, 0, 746 DP_SEC_GSP1_ENABLE, 0, 747 DP_SEC_GSP2_ENABLE, 0, 748 DP_SEC_GSP3_ENABLE, 0, 749 DP_SEC_GSP4_ENABLE, 0, 750 DP_SEC_GSP5_ENABLE, 0, 751 DP_SEC_GSP6_ENABLE, 0, 752 DP_SEC_GSP7_ENABLE, 0, 753 DP_SEC_MPG_ENABLE, 0, 754 DP_SEC_STREAM_ENABLE, 0); 755 756 /* this register shared with audio info frame. 757 * therefore we need to keep master enabled 758 * if at least one of the fields is not 0 */ 759 value = REG_READ(DP_SEC_CNTL); 760 if (value) 761 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 762 763 } 764 765 void enc1_stream_encoder_dp_blank( 766 struct stream_encoder *enc) 767 { 768 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 769 uint32_t retries = 0; 770 uint32_t reg1 = 0; 771 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 772 773 /* Note: For CZ, we are changing driver default to disable 774 * stream deferred to next VBLANK. If results are positive, we 775 * will make the same change to all DCE versions. There are a 776 * handful of panels that cannot handle disable stream at 777 * HBLANK and will result in a white line flash across the 778 * screen on stream disable. 779 */ 780 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 781 if ((reg1 & 0x1) == 0) 782 /*stream not enabled*/ 783 return; 784 /* Specify the video stream disable point 785 * (2 = start of the next vertical blank) 786 */ 787 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 788 /* Larger delay to wait until VBLANK - use max retry of 789 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 790 * a little more because we may not trust delay accuracy. 791 */ 792 max_retries = DP_BLANK_MAX_RETRY * 150; 793 794 /* disable DP stream */ 795 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 796 797 /* the encoder stops sending the video stream 798 * at the start of the vertical blanking. 799 * Poll for DP_VID_STREAM_STATUS == 0 800 */ 801 802 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 803 0, 804 10, max_retries); 805 806 ASSERT(retries <= max_retries); 807 808 /* Tell the DP encoder to ignore timing from CRTC, must be done after 809 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 810 * complete, stream status will be stuck in video stream enabled state, 811 * i.e. DP_VID_STREAM_STATUS stuck at 1. 812 */ 813 814 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 815 } 816 817 /* output video stream to link encoder */ 818 void enc1_stream_encoder_dp_unblank( 819 struct stream_encoder *enc, 820 const struct encoder_unblank_param *param) 821 { 822 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 823 824 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 825 uint32_t n_vid = 0x8000; 826 uint32_t m_vid; 827 828 /* M / N = Fstream / Flink 829 * m_vid / n_vid = pixel rate / link rate 830 */ 831 832 uint64_t m_vid_l = n_vid; 833 834 m_vid_l *= param->pixel_clk_khz; 835 m_vid_l = div_u64(m_vid_l, 836 param->link_settings.link_rate 837 * LINK_RATE_REF_FREQ_IN_KHZ); 838 839 m_vid = (uint32_t) m_vid_l; 840 841 /* enable auto measurement */ 842 843 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 844 845 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 846 * therefore program initial value for Mvid and Nvid 847 */ 848 849 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 850 851 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 852 853 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 854 } 855 856 /* set DIG_START to 0x1 to resync FIFO */ 857 858 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 859 860 /* switch DP encoder to CRTC data */ 861 862 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 863 864 /* wait 100us for DIG/DP logic to prime 865 * (i.e. a few video lines) 866 */ 867 udelay(100); 868 869 /* the hardware would start sending video at the start of the next DP 870 * frame (i.e. rising edge of the vblank). 871 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 872 * register has no effect on enable transition! HW always guarantees 873 * VID_STREAM enable at start of next frame, and this is not 874 * programmable 875 */ 876 877 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 878 } 879 880 void enc1_stream_encoder_set_avmute( 881 struct stream_encoder *enc, 882 bool enable) 883 { 884 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 885 unsigned int value = enable ? 1 : 0; 886 887 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 888 } 889 890 891 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 892 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 893 894 #include "include/audio_types.h" 895 896 /** 897 * speakersToChannels 898 * 899 * @brief 900 * translate speakers to channels 901 * 902 * FL - Front Left 903 * FR - Front Right 904 * RL - Rear Left 905 * RR - Rear Right 906 * RC - Rear Center 907 * FC - Front Center 908 * FLC - Front Left Center 909 * FRC - Front Right Center 910 * RLC - Rear Left Center 911 * RRC - Rear Right Center 912 * LFE - Low Freq Effect 913 * 914 * FC 915 * FLC FRC 916 * FL FR 917 * 918 * LFE 919 * () 920 * 921 * 922 * RL RR 923 * RLC RRC 924 * RC 925 * 926 * ch 8 7 6 5 4 3 2 1 927 * 0b00000011 - - - - - - FR FL 928 * 0b00000111 - - - - - LFE FR FL 929 * 0b00001011 - - - - FC - FR FL 930 * 0b00001111 - - - - FC LFE FR FL 931 * 0b00010011 - - - RC - - FR FL 932 * 0b00010111 - - - RC - LFE FR FL 933 * 0b00011011 - - - RC FC - FR FL 934 * 0b00011111 - - - RC FC LFE FR FL 935 * 0b00110011 - - RR RL - - FR FL 936 * 0b00110111 - - RR RL - LFE FR FL 937 * 0b00111011 - - RR RL FC - FR FL 938 * 0b00111111 - - RR RL FC LFE FR FL 939 * 0b01110011 - RC RR RL - - FR FL 940 * 0b01110111 - RC RR RL - LFE FR FL 941 * 0b01111011 - RC RR RL FC - FR FL 942 * 0b01111111 - RC RR RL FC LFE FR FL 943 * 0b11110011 RRC RLC RR RL - - FR FL 944 * 0b11110111 RRC RLC RR RL - LFE FR FL 945 * 0b11111011 RRC RLC RR RL FC - FR FL 946 * 0b11111111 RRC RLC RR RL FC LFE FR FL 947 * 0b11000011 FRC FLC - - - - FR FL 948 * 0b11000111 FRC FLC - - - LFE FR FL 949 * 0b11001011 FRC FLC - - FC - FR FL 950 * 0b11001111 FRC FLC - - FC LFE FR FL 951 * 0b11010011 FRC FLC - RC - - FR FL 952 * 0b11010111 FRC FLC - RC - LFE FR FL 953 * 0b11011011 FRC FLC - RC FC - FR FL 954 * 0b11011111 FRC FLC - RC FC LFE FR FL 955 * 0b11110011 FRC FLC RR RL - - FR FL 956 * 0b11110111 FRC FLC RR RL - LFE FR FL 957 * 0b11111011 FRC FLC RR RL FC - FR FL 958 * 0b11111111 FRC FLC RR RL FC LFE FR FL 959 * 960 * @param 961 * speakers - speaker information as it comes from CEA audio block 962 */ 963 /* translate speakers to channels */ 964 965 union audio_cea_channels { 966 uint8_t all; 967 struct audio_cea_channels_bits { 968 uint32_t FL:1; 969 uint32_t FR:1; 970 uint32_t LFE:1; 971 uint32_t FC:1; 972 uint32_t RL_RC:1; 973 uint32_t RR:1; 974 uint32_t RC_RLC_FLC:1; 975 uint32_t RRC_FRC:1; 976 } channels; 977 }; 978 979 struct audio_clock_info { 980 /* pixel clock frequency*/ 981 uint32_t pixel_clock_in_10khz; 982 /* N - 32KHz audio */ 983 uint32_t n_32khz; 984 /* CTS - 32KHz audio*/ 985 uint32_t cts_32khz; 986 uint32_t n_44khz; 987 uint32_t cts_44khz; 988 uint32_t n_48khz; 989 uint32_t cts_48khz; 990 }; 991 992 /* 25.2MHz/1.001*/ 993 /* 25.2MHz/1.001*/ 994 /* 25.2MHz*/ 995 /* 27MHz */ 996 /* 27MHz*1.001*/ 997 /* 27MHz*1.001*/ 998 /* 54MHz*/ 999 /* 54MHz*1.001*/ 1000 /* 74.25MHz/1.001*/ 1001 /* 74.25MHz*/ 1002 /* 148.5MHz/1.001*/ 1003 /* 148.5MHz*/ 1004 1005 static const struct audio_clock_info audio_clock_info_table[16] = { 1006 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1007 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1008 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1009 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1010 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1011 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1012 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1013 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1014 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1015 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1016 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1017 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1018 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1019 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1020 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1021 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1022 }; 1023 1024 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1025 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1026 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1027 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1028 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1029 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1030 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1031 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1032 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1033 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1034 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1035 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1036 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1037 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1038 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1039 }; 1040 1041 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1042 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1043 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1044 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1045 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1046 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1047 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1048 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1049 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1050 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1051 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1052 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1053 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1054 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1055 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1056 1057 1058 }; 1059 1060 static union audio_cea_channels speakers_to_channels( 1061 struct audio_speaker_flags speaker_flags) 1062 { 1063 union audio_cea_channels cea_channels = {0}; 1064 1065 /* these are one to one */ 1066 cea_channels.channels.FL = speaker_flags.FL_FR; 1067 cea_channels.channels.FR = speaker_flags.FL_FR; 1068 cea_channels.channels.LFE = speaker_flags.LFE; 1069 cea_channels.channels.FC = speaker_flags.FC; 1070 1071 /* if Rear Left and Right exist move RC speaker to channel 7 1072 * otherwise to channel 5 1073 */ 1074 if (speaker_flags.RL_RR) { 1075 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1076 cea_channels.channels.RR = speaker_flags.RL_RR; 1077 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1078 } else { 1079 cea_channels.channels.RL_RC = speaker_flags.RC; 1080 } 1081 1082 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1083 if (speaker_flags.FLC_FRC) { 1084 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1085 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1086 } else { 1087 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1088 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1089 } 1090 1091 return cea_channels; 1092 } 1093 1094 static void get_audio_clock_info( 1095 enum dc_color_depth color_depth, 1096 uint32_t crtc_pixel_clock_in_khz, 1097 uint32_t actual_pixel_clock_in_khz, 1098 struct audio_clock_info *audio_clock_info) 1099 { 1100 const struct audio_clock_info *clock_info; 1101 uint32_t index; 1102 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz / 10; 1103 uint32_t audio_array_size; 1104 1105 switch (color_depth) { 1106 case COLOR_DEPTH_161616: 1107 clock_info = audio_clock_info_table_48bpc; 1108 audio_array_size = ARRAY_SIZE( 1109 audio_clock_info_table_48bpc); 1110 break; 1111 case COLOR_DEPTH_121212: 1112 clock_info = audio_clock_info_table_36bpc; 1113 audio_array_size = ARRAY_SIZE( 1114 audio_clock_info_table_36bpc); 1115 break; 1116 default: 1117 clock_info = audio_clock_info_table; 1118 audio_array_size = ARRAY_SIZE( 1119 audio_clock_info_table); 1120 break; 1121 } 1122 1123 if (clock_info != NULL) { 1124 /* search for exact pixel clock in table */ 1125 for (index = 0; index < audio_array_size; index++) { 1126 if (clock_info[index].pixel_clock_in_10khz > 1127 crtc_pixel_clock_in_10khz) 1128 break; /* not match */ 1129 else if (clock_info[index].pixel_clock_in_10khz == 1130 crtc_pixel_clock_in_10khz) { 1131 /* match found */ 1132 *audio_clock_info = clock_info[index]; 1133 return; 1134 } 1135 } 1136 } 1137 1138 /* not found */ 1139 if (actual_pixel_clock_in_khz == 0) 1140 actual_pixel_clock_in_khz = crtc_pixel_clock_in_khz; 1141 1142 /* See HDMI spec the table entry under 1143 * pixel clock of "Other". */ 1144 audio_clock_info->pixel_clock_in_10khz = 1145 actual_pixel_clock_in_khz / 10; 1146 audio_clock_info->cts_32khz = actual_pixel_clock_in_khz; 1147 audio_clock_info->cts_44khz = actual_pixel_clock_in_khz; 1148 audio_clock_info->cts_48khz = actual_pixel_clock_in_khz; 1149 1150 audio_clock_info->n_32khz = 4096; 1151 audio_clock_info->n_44khz = 6272; 1152 audio_clock_info->n_48khz = 6144; 1153 } 1154 1155 static void enc1_se_audio_setup( 1156 struct stream_encoder *enc, 1157 unsigned int az_inst, 1158 struct audio_info *audio_info) 1159 { 1160 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1161 1162 uint32_t speakers = 0; 1163 uint32_t channels = 0; 1164 1165 ASSERT(audio_info); 1166 if (audio_info == NULL) 1167 /* This should not happen.it does so we don't get BSOD*/ 1168 return; 1169 1170 speakers = audio_info->flags.info.ALLSPEAKERS; 1171 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1172 1173 /* setup the audio stream source select (audio -> dig mapping) */ 1174 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1175 1176 /* Channel allocation */ 1177 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1178 } 1179 1180 static void enc1_se_setup_hdmi_audio( 1181 struct stream_encoder *enc, 1182 const struct audio_crtc_info *crtc_info) 1183 { 1184 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1185 1186 struct audio_clock_info audio_clock_info = {0}; 1187 1188 /* HDMI_AUDIO_PACKET_CONTROL */ 1189 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL, 1190 HDMI_AUDIO_DELAY_EN, 1); 1191 1192 /* AFMT_AUDIO_PACKET_CONTROL */ 1193 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1194 1195 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1196 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1197 AFMT_AUDIO_LAYOUT_OVRD, 0, 1198 AFMT_60958_OSF_OVRD, 0); 1199 1200 /* HDMI_ACR_PACKET_CONTROL */ 1201 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1202 HDMI_ACR_AUTO_SEND, 1, 1203 HDMI_ACR_SOURCE, 0, 1204 HDMI_ACR_AUDIO_PRIORITY, 0); 1205 1206 /* Program audio clock sample/regeneration parameters */ 1207 get_audio_clock_info(crtc_info->color_depth, 1208 crtc_info->requested_pixel_clock, 1209 crtc_info->calculated_pixel_clock, 1210 &audio_clock_info); 1211 DC_LOG_HW_AUDIO( 1212 "\n%s:Input::requested_pixel_clock = %d" \ 1213 "calculated_pixel_clock = %d \n", __func__, \ 1214 crtc_info->requested_pixel_clock, \ 1215 crtc_info->calculated_pixel_clock); 1216 1217 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1218 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1219 1220 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1221 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1222 1223 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1224 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1225 1226 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1227 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1228 1229 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1230 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1231 1232 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1233 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1234 1235 /* Video driver cannot know in advance which sample rate will 1236 * be used by HD Audio driver 1237 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1238 * programmed below in interruppt callback 1239 */ 1240 1241 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1242 * AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 1243 */ 1244 REG_UPDATE_2(AFMT_60958_0, 1245 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1246 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1247 1248 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1249 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1250 1251 /* AFMT_60958_2 now keep this settings until 1252 * Programming guide comes out 1253 */ 1254 REG_UPDATE_6(AFMT_60958_2, 1255 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1256 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1257 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1258 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1259 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1260 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1261 } 1262 1263 static void enc1_se_setup_dp_audio( 1264 struct stream_encoder *enc) 1265 { 1266 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1267 1268 /* --- DP Audio packet configurations --- */ 1269 1270 /* ATP Configuration */ 1271 REG_SET(DP_SEC_AUD_N, 0, 1272 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1273 1274 /* Async/auto-calc timestamp mode */ 1275 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1276 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1277 1278 /* --- The following are the registers 1279 * copied from the SetupHDMI --- 1280 */ 1281 1282 /* AFMT_AUDIO_PACKET_CONTROL */ 1283 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1284 1285 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1286 /* Program the ATP and AIP next */ 1287 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1288 AFMT_AUDIO_LAYOUT_OVRD, 0, 1289 AFMT_60958_OSF_OVRD, 0); 1290 1291 /* AFMT_INFOFRAME_CONTROL0 */ 1292 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1293 1294 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1295 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1296 } 1297 1298 static void enc1_se_enable_audio_clock( 1299 struct stream_encoder *enc, 1300 bool enable) 1301 { 1302 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1303 1304 if (REG(AFMT_CNTL) == 0) 1305 return; /* DCE8/10 does not have this register */ 1306 1307 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1308 1309 /* wait for AFMT clock to turn on, 1310 * expectation: this should complete in 1-2 reads 1311 * 1312 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1313 * 1314 * TODO: wait for clock_on does not work well. May need HW 1315 * program sequence. But audio seems work normally even without wait 1316 * for clock_on status change 1317 */ 1318 } 1319 1320 static void enc1_se_enable_dp_audio( 1321 struct stream_encoder *enc) 1322 { 1323 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1324 1325 /* Enable Audio packets */ 1326 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1327 1328 /* Program the ATP and AIP next */ 1329 REG_UPDATE_2(DP_SEC_CNTL, 1330 DP_SEC_ATP_ENABLE, 1, 1331 DP_SEC_AIP_ENABLE, 1); 1332 1333 /* Program STREAM_ENABLE after all the other enables. */ 1334 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1335 } 1336 1337 static void enc1_se_disable_dp_audio( 1338 struct stream_encoder *enc) 1339 { 1340 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1341 uint32_t value = 0; 1342 1343 /* Disable Audio packets */ 1344 REG_UPDATE_5(DP_SEC_CNTL, 1345 DP_SEC_ASP_ENABLE, 0, 1346 DP_SEC_ATP_ENABLE, 0, 1347 DP_SEC_AIP_ENABLE, 0, 1348 DP_SEC_ACM_ENABLE, 0, 1349 DP_SEC_STREAM_ENABLE, 0); 1350 1351 /* This register shared with encoder info frame. Therefore we need to 1352 * keep master enabled if at least on of the fields is not 0 1353 */ 1354 value = REG_READ(DP_SEC_CNTL); 1355 if (value != 0) 1356 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1357 1358 } 1359 1360 void enc1_se_audio_mute_control( 1361 struct stream_encoder *enc, 1362 bool mute) 1363 { 1364 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1365 1366 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1367 } 1368 1369 void enc1_se_dp_audio_setup( 1370 struct stream_encoder *enc, 1371 unsigned int az_inst, 1372 struct audio_info *info) 1373 { 1374 enc1_se_audio_setup(enc, az_inst, info); 1375 } 1376 1377 void enc1_se_dp_audio_enable( 1378 struct stream_encoder *enc) 1379 { 1380 enc1_se_enable_audio_clock(enc, true); 1381 enc1_se_setup_dp_audio(enc); 1382 enc1_se_enable_dp_audio(enc); 1383 } 1384 1385 void enc1_se_dp_audio_disable( 1386 struct stream_encoder *enc) 1387 { 1388 enc1_se_disable_dp_audio(enc); 1389 enc1_se_enable_audio_clock(enc, false); 1390 } 1391 1392 void enc1_se_hdmi_audio_setup( 1393 struct stream_encoder *enc, 1394 unsigned int az_inst, 1395 struct audio_info *info, 1396 struct audio_crtc_info *audio_crtc_info) 1397 { 1398 enc1_se_enable_audio_clock(enc, true); 1399 enc1_se_setup_hdmi_audio(enc, audio_crtc_info); 1400 enc1_se_audio_setup(enc, az_inst, info); 1401 } 1402 1403 void enc1_se_hdmi_audio_disable( 1404 struct stream_encoder *enc) 1405 { 1406 enc1_se_enable_audio_clock(enc, false); 1407 } 1408 1409 1410 void enc1_setup_stereo_sync( 1411 struct stream_encoder *enc, 1412 int tg_inst, bool enable) 1413 { 1414 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); 1415 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1416 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1417 } 1418 1419 1420 static const struct stream_encoder_funcs dcn10_str_enc_funcs = { 1421 .dp_set_stream_attribute = 1422 enc1_stream_encoder_dp_set_stream_attribute, 1423 .hdmi_set_stream_attribute = 1424 enc1_stream_encoder_hdmi_set_stream_attribute, 1425 .dvi_set_stream_attribute = 1426 enc1_stream_encoder_dvi_set_stream_attribute, 1427 .set_mst_bandwidth = 1428 enc1_stream_encoder_set_mst_bandwidth, 1429 .update_hdmi_info_packets = 1430 enc1_stream_encoder_update_hdmi_info_packets, 1431 .stop_hdmi_info_packets = 1432 enc1_stream_encoder_stop_hdmi_info_packets, 1433 .update_dp_info_packets = 1434 enc1_stream_encoder_update_dp_info_packets, 1435 .stop_dp_info_packets = 1436 enc1_stream_encoder_stop_dp_info_packets, 1437 .dp_blank = 1438 enc1_stream_encoder_dp_blank, 1439 .dp_unblank = 1440 enc1_stream_encoder_dp_unblank, 1441 .audio_mute_control = enc1_se_audio_mute_control, 1442 1443 .dp_audio_setup = enc1_se_dp_audio_setup, 1444 .dp_audio_enable = enc1_se_dp_audio_enable, 1445 .dp_audio_disable = enc1_se_dp_audio_disable, 1446 1447 .hdmi_audio_setup = enc1_se_hdmi_audio_setup, 1448 .hdmi_audio_disable = enc1_se_hdmi_audio_disable, 1449 .setup_stereo_sync = enc1_setup_stereo_sync, 1450 .set_avmute = enc1_stream_encoder_set_avmute, 1451 }; 1452 1453 void dcn10_stream_encoder_construct( 1454 struct dcn10_stream_encoder *enc1, 1455 struct dc_context *ctx, 1456 struct dc_bios *bp, 1457 enum engine_id eng_id, 1458 const struct dcn10_stream_enc_registers *regs, 1459 const struct dcn10_stream_encoder_shift *se_shift, 1460 const struct dcn10_stream_encoder_mask *se_mask) 1461 { 1462 enc1->base.funcs = &dcn10_str_enc_funcs; 1463 enc1->base.ctx = ctx; 1464 enc1->base.id = eng_id; 1465 enc1->base.bp = bp; 1466 enc1->regs = regs; 1467 enc1->se_shift = se_shift; 1468 enc1->se_mask = se_mask; 1469 } 1470 1471