1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-16 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 27*b843c749SSergey Zigachev #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "gpio_regs.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev /****************************** new register headers */ 32*b843c749SSergey Zigachev /*** following in header */ 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \ 35*b843c749SSergey Zigachev .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 36*b843c749SSergey Zigachev .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ 37*b843c749SSergey Zigachev .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev #define DDC_GPIO_REG_LIST(cd,id) \ 40*b843c749SSergey Zigachev {\ 41*b843c749SSergey Zigachev DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ 42*b843c749SSergey Zigachev DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\ 43*b843c749SSergey Zigachev DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\ 44*b843c749SSergey Zigachev DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\ 45*b843c749SSergey Zigachev } 46*b843c749SSergey Zigachev 47*b843c749SSergey Zigachev #define DDC_REG_LIST(cd,id) \ 48*b843c749SSergey Zigachev DDC_GPIO_REG_LIST(cd,id),\ 49*b843c749SSergey Zigachev .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ 52*b843c749SSergey Zigachev .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 53*b843c749SSergey Zigachev .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ 54*b843c749SSergey Zigachev .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev #define DDC_GPIO_VGA_REG_LIST(cd) \ 57*b843c749SSergey Zigachev {\ 58*b843c749SSergey Zigachev DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\ 59*b843c749SSergey Zigachev DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\ 60*b843c749SSergey Zigachev DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\ 61*b843c749SSergey Zigachev DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\ 62*b843c749SSergey Zigachev } 63*b843c749SSergey Zigachev 64*b843c749SSergey Zigachev #define DDC_VGA_REG_LIST(cd) \ 65*b843c749SSergey Zigachev DDC_GPIO_VGA_REG_LIST(cd),\ 66*b843c749SSergey Zigachev .ddc_setup = mmDC_I2C_DDCVGA_SETUP 67*b843c749SSergey Zigachev 68*b843c749SSergey Zigachev #define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \ 69*b843c749SSergey Zigachev .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 70*b843c749SSergey Zigachev .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ 71*b843c749SSergey Zigachev .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev #define DDC_GPIO_I2C_REG_LIST(cd) \ 74*b843c749SSergey Zigachev {\ 75*b843c749SSergey Zigachev DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\ 76*b843c749SSergey Zigachev DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\ 77*b843c749SSergey Zigachev DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\ 78*b843c749SSergey Zigachev DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\ 79*b843c749SSergey Zigachev } 80*b843c749SSergey Zigachev 81*b843c749SSergey Zigachev #define DDC_I2C_REG_LIST(cd) \ 82*b843c749SSergey Zigachev DDC_GPIO_I2C_REG_LIST(cd),\ 83*b843c749SSergey Zigachev .ddc_setup = 0 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ 86*b843c749SSergey Zigachev SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 87*b843c749SSergey Zigachev SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ 88*b843c749SSergey Zigachev SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ 89*b843c749SSergey Zigachev SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ 90*b843c749SSergey Zigachev SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ 91*b843c749SSergey Zigachev SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) 92*b843c749SSergey Zigachev 93*b843c749SSergey Zigachev #define DDC_MASK_SH_LIST(mask_sh) \ 94*b843c749SSergey Zigachev DDC_MASK_SH_LIST_COMMON(mask_sh),\ 95*b843c749SSergey Zigachev SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ 96*b843c749SSergey Zigachev SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) 97*b843c749SSergey Zigachev 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev struct ddc_registers { 100*b843c749SSergey Zigachev struct gpio_registers gpio; 101*b843c749SSergey Zigachev uint32_t ddc_setup; 102*b843c749SSergey Zigachev }; 103*b843c749SSergey Zigachev 104*b843c749SSergey Zigachev struct ddc_sh_mask { 105*b843c749SSergey Zigachev /* i2c_dd_setup */ 106*b843c749SSergey Zigachev uint32_t DC_I2C_DDC1_ENABLE; 107*b843c749SSergey Zigachev uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 108*b843c749SSergey Zigachev uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 109*b843c749SSergey Zigachev /* ddc1_mask */ 110*b843c749SSergey Zigachev uint32_t DC_GPIO_DDC1DATA_PD_EN; 111*b843c749SSergey Zigachev uint32_t DC_GPIO_DDC1CLK_PD_EN; 112*b843c749SSergey Zigachev uint32_t AUX_PAD1_MODE; 113*b843c749SSergey Zigachev /* i2cpad_mask */ 114*b843c749SSergey Zigachev uint32_t DC_GPIO_SDA_PD_DIS; 115*b843c749SSergey Zigachev uint32_t DC_GPIO_SCL_PD_DIS; 116*b843c749SSergey Zigachev }; 117*b843c749SSergey Zigachev 118*b843c749SSergey Zigachev 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev /*** following in dc_resource */ 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev #define ddc_data_regs(id) \ 123*b843c749SSergey Zigachev {\ 124*b843c749SSergey Zigachev DDC_REG_LIST(DATA,id)\ 125*b843c749SSergey Zigachev } 126*b843c749SSergey Zigachev 127*b843c749SSergey Zigachev #define ddc_clk_regs(id) \ 128*b843c749SSergey Zigachev {\ 129*b843c749SSergey Zigachev DDC_REG_LIST(CLK,id)\ 130*b843c749SSergey Zigachev } 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev #define ddc_vga_data_regs \ 133*b843c749SSergey Zigachev {\ 134*b843c749SSergey Zigachev DDC_VGA_REG_LIST(DATA)\ 135*b843c749SSergey Zigachev } 136*b843c749SSergey Zigachev 137*b843c749SSergey Zigachev #define ddc_vga_clk_regs \ 138*b843c749SSergey Zigachev {\ 139*b843c749SSergey Zigachev DDC_VGA_REG_LIST(CLK)\ 140*b843c749SSergey Zigachev } 141*b843c749SSergey Zigachev 142*b843c749SSergey Zigachev #define ddc_i2c_data_regs \ 143*b843c749SSergey Zigachev {\ 144*b843c749SSergey Zigachev DDC_I2C_REG_LIST(SDA)\ 145*b843c749SSergey Zigachev } 146*b843c749SSergey Zigachev 147*b843c749SSergey Zigachev #define ddc_i2c_clk_regs \ 148*b843c749SSergey Zigachev {\ 149*b843c749SSergey Zigachev DDC_I2C_REG_LIST(SCL)\ 150*b843c749SSergey Zigachev } 151*b843c749SSergey Zigachev 152*b843c749SSergey Zigachev 153*b843c749SSergey Zigachev #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ 154