1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 27 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 28 29 #include "gpio_regs.h" 30 31 /****************************** new register headers */ 32 /*** following in header */ 33 34 #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \ 35 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 36 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ 37 .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT 38 39 #define DDC_GPIO_REG_LIST(cd,id) \ 40 {\ 41 DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ 42 DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\ 43 DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\ 44 DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\ 45 } 46 47 #define DDC_REG_LIST(cd,id) \ 48 DDC_GPIO_REG_LIST(cd,id),\ 49 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 50 51 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ 52 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 53 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ 54 .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT 55 56 #define DDC_GPIO_VGA_REG_LIST(cd) \ 57 {\ 58 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\ 59 DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\ 60 DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\ 61 DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\ 62 } 63 64 #define DDC_VGA_REG_LIST(cd) \ 65 DDC_GPIO_VGA_REG_LIST(cd),\ 66 .ddc_setup = mmDC_I2C_DDCVGA_SETUP 67 68 #define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \ 69 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 70 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ 71 .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT 72 73 #define DDC_GPIO_I2C_REG_LIST(cd) \ 74 {\ 75 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\ 76 DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\ 77 DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\ 78 DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\ 79 } 80 81 #define DDC_I2C_REG_LIST(cd) \ 82 DDC_GPIO_I2C_REG_LIST(cd),\ 83 .ddc_setup = 0 84 85 #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ 86 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 87 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ 88 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ 89 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ 90 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ 91 SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) 92 93 #define DDC_MASK_SH_LIST(mask_sh) \ 94 DDC_MASK_SH_LIST_COMMON(mask_sh),\ 95 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ 96 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) 97 98 99 struct ddc_registers { 100 struct gpio_registers gpio; 101 uint32_t ddc_setup; 102 }; 103 104 struct ddc_sh_mask { 105 /* i2c_dd_setup */ 106 uint32_t DC_I2C_DDC1_ENABLE; 107 uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 108 uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 109 /* ddc1_mask */ 110 uint32_t DC_GPIO_DDC1DATA_PD_EN; 111 uint32_t DC_GPIO_DDC1CLK_PD_EN; 112 uint32_t AUX_PAD1_MODE; 113 /* i2cpad_mask */ 114 uint32_t DC_GPIO_SDA_PD_DIS; 115 uint32_t DC_GPIO_SCL_PD_DIS; 116 }; 117 118 119 120 /*** following in dc_resource */ 121 122 #define ddc_data_regs(id) \ 123 {\ 124 DDC_REG_LIST(DATA,id)\ 125 } 126 127 #define ddc_clk_regs(id) \ 128 {\ 129 DDC_REG_LIST(CLK,id)\ 130 } 131 132 #define ddc_vga_data_regs \ 133 {\ 134 DDC_VGA_REG_LIST(DATA)\ 135 } 136 137 #define ddc_vga_clk_regs \ 138 {\ 139 DDC_VGA_REG_LIST(CLK)\ 140 } 141 142 #define ddc_i2c_data_regs \ 143 {\ 144 DDC_I2C_REG_LIST(SDA)\ 145 } 146 147 #define ddc_i2c_clk_regs \ 148 {\ 149 DDC_I2C_REG_LIST(SCL)\ 150 } 151 152 153 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ 154