1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-16 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ 27*b843c749SSergey Zigachev #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "gpio_regs.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev #define ONE_MORE_0 1 32*b843c749SSergey Zigachev #define ONE_MORE_1 2 33*b843c749SSergey Zigachev #define ONE_MORE_2 3 34*b843c749SSergey Zigachev #define ONE_MORE_3 4 35*b843c749SSergey Zigachev #define ONE_MORE_4 5 36*b843c749SSergey Zigachev #define ONE_MORE_5 6 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev #define HPD_GPIO_REG_LIST_ENTRY(type,cd,id) \ 40*b843c749SSergey Zigachev .type ## _reg = REG(DC_GPIO_HPD_## type),\ 41*b843c749SSergey Zigachev .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\ 42*b843c749SSergey Zigachev .type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev #define HPD_GPIO_REG_LIST(id) \ 45*b843c749SSergey Zigachev {\ 46*b843c749SSergey Zigachev HPD_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ 47*b843c749SSergey Zigachev HPD_GPIO_REG_LIST_ENTRY(A,cd,id),\ 48*b843c749SSergey Zigachev HPD_GPIO_REG_LIST_ENTRY(EN,cd,id),\ 49*b843c749SSergey Zigachev HPD_GPIO_REG_LIST_ENTRY(Y,cd,id)\ 50*b843c749SSergey Zigachev } 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev #define HPD_REG_LIST(id) \ 53*b843c749SSergey Zigachev HPD_GPIO_REG_LIST(ONE_MORE_ ## id), \ 54*b843c749SSergey Zigachev .int_status = REGI(DC_HPD_INT_STATUS, HPD, id),\ 55*b843c749SSergey Zigachev .toggle_filt_cntl = REGI(DC_HPD_TOGGLE_FILT_CNTL, HPD, id) 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev #define HPD_MASK_SH_LIST(mask_sh) \ 58*b843c749SSergey Zigachev SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE_DELAYED, mask_sh),\ 59*b843c749SSergey Zigachev SF_HPD(DC_HPD_INT_STATUS, DC_HPD_SENSE, mask_sh),\ 60*b843c749SSergey Zigachev SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_CONNECT_INT_DELAY, mask_sh),\ 61*b843c749SSergey Zigachev SF_HPD(DC_HPD_TOGGLE_FILT_CNTL, DC_HPD_DISCONNECT_INT_DELAY, mask_sh) 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev struct hpd_registers { 64*b843c749SSergey Zigachev struct gpio_registers gpio; 65*b843c749SSergey Zigachev uint32_t int_status; 66*b843c749SSergey Zigachev uint32_t toggle_filt_cntl; 67*b843c749SSergey Zigachev }; 68*b843c749SSergey Zigachev 69*b843c749SSergey Zigachev struct hpd_sh_mask { 70*b843c749SSergey Zigachev /* int_status */ 71*b843c749SSergey Zigachev uint32_t DC_HPD_SENSE_DELAYED; 72*b843c749SSergey Zigachev uint32_t DC_HPD_SENSE; 73*b843c749SSergey Zigachev /* toggle_filt_cntl */ 74*b843c749SSergey Zigachev uint32_t DC_HPD_CONNECT_INT_DELAY; 75*b843c749SSergey Zigachev uint32_t DC_HPD_DISCONNECT_INT_DELAY; 76*b843c749SSergey Zigachev }; 77*b843c749SSergey Zigachev 78*b843c749SSergey Zigachev 79*b843c749SSergey Zigachev #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_HPD_REGS_H_ */ 80