1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev #include "include/gpio_types.h"
28*b843c749SSergey Zigachev #include "hw_gpio.h"
29*b843c749SSergey Zigachev
30*b843c749SSergey Zigachev #include "reg_helper.h"
31*b843c749SSergey Zigachev #include "gpio_regs.h"
32*b843c749SSergey Zigachev
33*b843c749SSergey Zigachev #undef FN
34*b843c749SSergey Zigachev #define FN(reg_name, field_name) \
35*b843c749SSergey Zigachev gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
36*b843c749SSergey Zigachev
37*b843c749SSergey Zigachev #define CTX \
38*b843c749SSergey Zigachev gpio->base.ctx
39*b843c749SSergey Zigachev #define REG(reg)\
40*b843c749SSergey Zigachev (gpio->regs->reg)
41*b843c749SSergey Zigachev
store_registers(struct hw_gpio * gpio)42*b843c749SSergey Zigachev static void store_registers(
43*b843c749SSergey Zigachev struct hw_gpio *gpio)
44*b843c749SSergey Zigachev {
45*b843c749SSergey Zigachev REG_GET(MASK_reg, MASK, &gpio->store.mask);
46*b843c749SSergey Zigachev REG_GET(A_reg, A, &gpio->store.a);
47*b843c749SSergey Zigachev REG_GET(EN_reg, EN, &gpio->store.en);
48*b843c749SSergey Zigachev /* TODO store GPIO_MUX_CONTROL if we ever use it */
49*b843c749SSergey Zigachev }
50*b843c749SSergey Zigachev
restore_registers(struct hw_gpio * gpio)51*b843c749SSergey Zigachev static void restore_registers(
52*b843c749SSergey Zigachev struct hw_gpio *gpio)
53*b843c749SSergey Zigachev {
54*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, gpio->store.mask);
55*b843c749SSergey Zigachev REG_UPDATE(A_reg, A, gpio->store.a);
56*b843c749SSergey Zigachev REG_UPDATE(EN_reg, EN, gpio->store.en);
57*b843c749SSergey Zigachev /* TODO restore GPIO_MUX_CONTROL if we ever use it */
58*b843c749SSergey Zigachev }
59*b843c749SSergey Zigachev
dal_hw_gpio_open(struct hw_gpio_pin * ptr,enum gpio_mode mode)60*b843c749SSergey Zigachev bool dal_hw_gpio_open(
61*b843c749SSergey Zigachev struct hw_gpio_pin *ptr,
62*b843c749SSergey Zigachev enum gpio_mode mode)
63*b843c749SSergey Zigachev {
64*b843c749SSergey Zigachev struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
65*b843c749SSergey Zigachev
66*b843c749SSergey Zigachev store_registers(pin);
67*b843c749SSergey Zigachev
68*b843c749SSergey Zigachev ptr->opened = (dal_hw_gpio_config_mode(pin, mode) == GPIO_RESULT_OK);
69*b843c749SSergey Zigachev
70*b843c749SSergey Zigachev return ptr->opened;
71*b843c749SSergey Zigachev }
72*b843c749SSergey Zigachev
dal_hw_gpio_get_value(const struct hw_gpio_pin * ptr,uint32_t * value)73*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_get_value(
74*b843c749SSergey Zigachev const struct hw_gpio_pin *ptr,
75*b843c749SSergey Zigachev uint32_t *value)
76*b843c749SSergey Zigachev {
77*b843c749SSergey Zigachev const struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
78*b843c749SSergey Zigachev
79*b843c749SSergey Zigachev enum gpio_result result = GPIO_RESULT_OK;
80*b843c749SSergey Zigachev
81*b843c749SSergey Zigachev switch (ptr->mode) {
82*b843c749SSergey Zigachev case GPIO_MODE_INPUT:
83*b843c749SSergey Zigachev case GPIO_MODE_OUTPUT:
84*b843c749SSergey Zigachev case GPIO_MODE_HARDWARE:
85*b843c749SSergey Zigachev case GPIO_MODE_FAST_OUTPUT:
86*b843c749SSergey Zigachev REG_GET(Y_reg, Y, value);
87*b843c749SSergey Zigachev break;
88*b843c749SSergey Zigachev default:
89*b843c749SSergey Zigachev result = GPIO_RESULT_NON_SPECIFIC_ERROR;
90*b843c749SSergey Zigachev }
91*b843c749SSergey Zigachev
92*b843c749SSergey Zigachev return result;
93*b843c749SSergey Zigachev }
94*b843c749SSergey Zigachev
dal_hw_gpio_set_value(const struct hw_gpio_pin * ptr,uint32_t value)95*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_set_value(
96*b843c749SSergey Zigachev const struct hw_gpio_pin *ptr,
97*b843c749SSergey Zigachev uint32_t value)
98*b843c749SSergey Zigachev {
99*b843c749SSergey Zigachev struct hw_gpio *gpio = FROM_HW_GPIO_PIN(ptr);
100*b843c749SSergey Zigachev
101*b843c749SSergey Zigachev /* This is the public interface
102*b843c749SSergey Zigachev * where the input comes from client, not shifted yet
103*b843c749SSergey Zigachev * (because client does not know the shifts). */
104*b843c749SSergey Zigachev
105*b843c749SSergey Zigachev switch (ptr->mode) {
106*b843c749SSergey Zigachev case GPIO_MODE_OUTPUT:
107*b843c749SSergey Zigachev REG_UPDATE(A_reg, A, value);
108*b843c749SSergey Zigachev return GPIO_RESULT_OK;
109*b843c749SSergey Zigachev case GPIO_MODE_FAST_OUTPUT:
110*b843c749SSergey Zigachev /* We use (EN) to faster switch (used in DDC GPIO).
111*b843c749SSergey Zigachev * So (A) is grounded, output is driven by (EN = 0)
112*b843c749SSergey Zigachev * to pull the line down (output == 0) and (EN=1)
113*b843c749SSergey Zigachev * then output is tri-state */
114*b843c749SSergey Zigachev REG_UPDATE(EN_reg, EN, ~value);
115*b843c749SSergey Zigachev return GPIO_RESULT_OK;
116*b843c749SSergey Zigachev default:
117*b843c749SSergey Zigachev return GPIO_RESULT_NON_SPECIFIC_ERROR;
118*b843c749SSergey Zigachev }
119*b843c749SSergey Zigachev }
120*b843c749SSergey Zigachev
dal_hw_gpio_change_mode(struct hw_gpio_pin * ptr,enum gpio_mode mode)121*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_change_mode(
122*b843c749SSergey Zigachev struct hw_gpio_pin *ptr,
123*b843c749SSergey Zigachev enum gpio_mode mode)
124*b843c749SSergey Zigachev {
125*b843c749SSergey Zigachev struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
126*b843c749SSergey Zigachev
127*b843c749SSergey Zigachev return dal_hw_gpio_config_mode(pin, mode);
128*b843c749SSergey Zigachev }
129*b843c749SSergey Zigachev
dal_hw_gpio_close(struct hw_gpio_pin * ptr)130*b843c749SSergey Zigachev void dal_hw_gpio_close(
131*b843c749SSergey Zigachev struct hw_gpio_pin *ptr)
132*b843c749SSergey Zigachev {
133*b843c749SSergey Zigachev struct hw_gpio *pin = FROM_HW_GPIO_PIN(ptr);
134*b843c749SSergey Zigachev
135*b843c749SSergey Zigachev restore_registers(pin);
136*b843c749SSergey Zigachev
137*b843c749SSergey Zigachev ptr->mode = GPIO_MODE_UNKNOWN;
138*b843c749SSergey Zigachev ptr->opened = false;
139*b843c749SSergey Zigachev }
140*b843c749SSergey Zigachev
dal_hw_gpio_config_mode(struct hw_gpio * gpio,enum gpio_mode mode)141*b843c749SSergey Zigachev enum gpio_result dal_hw_gpio_config_mode(
142*b843c749SSergey Zigachev struct hw_gpio *gpio,
143*b843c749SSergey Zigachev enum gpio_mode mode)
144*b843c749SSergey Zigachev {
145*b843c749SSergey Zigachev gpio->base.mode = mode;
146*b843c749SSergey Zigachev
147*b843c749SSergey Zigachev switch (mode) {
148*b843c749SSergey Zigachev case GPIO_MODE_INPUT:
149*b843c749SSergey Zigachev /* turn off output enable, act as input pin;
150*b843c749SSergey Zigachev * program the pin as GPIO, mask out signal driven by HW */
151*b843c749SSergey Zigachev REG_UPDATE(EN_reg, EN, 0);
152*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, 1);
153*b843c749SSergey Zigachev return GPIO_RESULT_OK;
154*b843c749SSergey Zigachev case GPIO_MODE_OUTPUT:
155*b843c749SSergey Zigachev /* turn on output enable, act as output pin;
156*b843c749SSergey Zigachev * program the pin as GPIO, mask out signal driven by HW */
157*b843c749SSergey Zigachev REG_UPDATE(A_reg, A, 0);
158*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, 1);
159*b843c749SSergey Zigachev return GPIO_RESULT_OK;
160*b843c749SSergey Zigachev case GPIO_MODE_FAST_OUTPUT:
161*b843c749SSergey Zigachev /* grounding the A register then use the EN register bit
162*b843c749SSergey Zigachev * will have faster effect on the rise time */
163*b843c749SSergey Zigachev REG_UPDATE(A_reg, A, 0);
164*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, 1);
165*b843c749SSergey Zigachev return GPIO_RESULT_OK;
166*b843c749SSergey Zigachev case GPIO_MODE_HARDWARE:
167*b843c749SSergey Zigachev /* program the pin as tri-state, pin is driven by HW */
168*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, 0);
169*b843c749SSergey Zigachev return GPIO_RESULT_OK;
170*b843c749SSergey Zigachev case GPIO_MODE_INTERRUPT:
171*b843c749SSergey Zigachev /* Interrupt mode supported only by HPD (IrqGpio) pins. */
172*b843c749SSergey Zigachev REG_UPDATE(MASK_reg, MASK, 0);
173*b843c749SSergey Zigachev return GPIO_RESULT_OK;
174*b843c749SSergey Zigachev default:
175*b843c749SSergey Zigachev return GPIO_RESULT_NON_SPECIFIC_ERROR;
176*b843c749SSergey Zigachev }
177*b843c749SSergey Zigachev }
178*b843c749SSergey Zigachev
dal_hw_gpio_construct(struct hw_gpio * pin,enum gpio_id id,uint32_t en,struct dc_context * ctx)179*b843c749SSergey Zigachev void dal_hw_gpio_construct(
180*b843c749SSergey Zigachev struct hw_gpio *pin,
181*b843c749SSergey Zigachev enum gpio_id id,
182*b843c749SSergey Zigachev uint32_t en,
183*b843c749SSergey Zigachev struct dc_context *ctx)
184*b843c749SSergey Zigachev {
185*b843c749SSergey Zigachev pin->base.ctx = ctx;
186*b843c749SSergey Zigachev pin->base.id = id;
187*b843c749SSergey Zigachev pin->base.en = en;
188*b843c749SSergey Zigachev pin->base.mode = GPIO_MODE_UNKNOWN;
189*b843c749SSergey Zigachev pin->base.opened = false;
190*b843c749SSergey Zigachev
191*b843c749SSergey Zigachev pin->store.mask = 0;
192*b843c749SSergey Zigachev pin->store.a = 0;
193*b843c749SSergey Zigachev pin->store.en = 0;
194*b843c749SSergey Zigachev pin->store.mux = 0;
195*b843c749SSergey Zigachev
196*b843c749SSergey Zigachev pin->mux_supported = false;
197*b843c749SSergey Zigachev }
198*b843c749SSergey Zigachev
dal_hw_gpio_destruct(struct hw_gpio * pin)199*b843c749SSergey Zigachev void dal_hw_gpio_destruct(
200*b843c749SSergey Zigachev struct hw_gpio *pin)
201*b843c749SSergey Zigachev {
202*b843c749SSergey Zigachev ASSERT(!pin->base.opened);
203*b843c749SSergey Zigachev }
204