1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev /*
29*b843c749SSergey Zigachev * Pre-requisites: headers required by header of this unit
30*b843c749SSergey Zigachev */
31*b843c749SSergey Zigachev #include "include/i2caux_interface.h"
32*b843c749SSergey Zigachev #include "engine.h"
33*b843c749SSergey Zigachev
34*b843c749SSergey Zigachev /*
35*b843c749SSergey Zigachev * Header of this unit
36*b843c749SSergey Zigachev */
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev #include "aux_engine.h"
39*b843c749SSergey Zigachev
40*b843c749SSergey Zigachev /*
41*b843c749SSergey Zigachev * Post-requisites: headers required by this unit
42*b843c749SSergey Zigachev */
43*b843c749SSergey Zigachev
44*b843c749SSergey Zigachev #include "include/link_service_types.h"
45*b843c749SSergey Zigachev
46*b843c749SSergey Zigachev /*
47*b843c749SSergey Zigachev * This unit
48*b843c749SSergey Zigachev */
49*b843c749SSergey Zigachev
50*b843c749SSergey Zigachev enum {
51*b843c749SSergey Zigachev AUX_INVALID_REPLY_RETRY_COUNTER = 1,
52*b843c749SSergey Zigachev AUX_TIMED_OUT_RETRY_COUNTER = 2,
53*b843c749SSergey Zigachev AUX_DEFER_RETRY_COUNTER = 6
54*b843c749SSergey Zigachev };
55*b843c749SSergey Zigachev
56*b843c749SSergey Zigachev #define FROM_ENGINE(ptr) \
57*b843c749SSergey Zigachev container_of((ptr), struct aux_engine, base)
58*b843c749SSergey Zigachev #define DC_LOGGER \
59*b843c749SSergey Zigachev engine->base.ctx->logger
60*b843c749SSergey Zigachev
dal_aux_engine_get_engine_type(const struct engine * engine)61*b843c749SSergey Zigachev enum i2caux_engine_type dal_aux_engine_get_engine_type(
62*b843c749SSergey Zigachev const struct engine *engine)
63*b843c749SSergey Zigachev {
64*b843c749SSergey Zigachev return I2CAUX_ENGINE_TYPE_AUX;
65*b843c749SSergey Zigachev }
66*b843c749SSergey Zigachev
dal_aux_engine_acquire(struct engine * engine,struct ddc * ddc)67*b843c749SSergey Zigachev bool dal_aux_engine_acquire(
68*b843c749SSergey Zigachev struct engine *engine,
69*b843c749SSergey Zigachev struct ddc *ddc)
70*b843c749SSergey Zigachev {
71*b843c749SSergey Zigachev struct aux_engine *aux_engine = FROM_ENGINE(engine);
72*b843c749SSergey Zigachev
73*b843c749SSergey Zigachev enum gpio_result result;
74*b843c749SSergey Zigachev if (aux_engine->funcs->is_engine_available) {
75*b843c749SSergey Zigachev /*check whether SW could use the engine*/
76*b843c749SSergey Zigachev if (!aux_engine->funcs->is_engine_available(aux_engine)) {
77*b843c749SSergey Zigachev return false;
78*b843c749SSergey Zigachev }
79*b843c749SSergey Zigachev }
80*b843c749SSergey Zigachev
81*b843c749SSergey Zigachev result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
82*b843c749SSergey Zigachev GPIO_DDC_CONFIG_TYPE_MODE_AUX);
83*b843c749SSergey Zigachev
84*b843c749SSergey Zigachev if (result != GPIO_RESULT_OK)
85*b843c749SSergey Zigachev return false;
86*b843c749SSergey Zigachev
87*b843c749SSergey Zigachev if (!aux_engine->funcs->acquire_engine(aux_engine)) {
88*b843c749SSergey Zigachev dal_ddc_close(ddc);
89*b843c749SSergey Zigachev return false;
90*b843c749SSergey Zigachev }
91*b843c749SSergey Zigachev
92*b843c749SSergey Zigachev engine->ddc = ddc;
93*b843c749SSergey Zigachev
94*b843c749SSergey Zigachev return true;
95*b843c749SSergey Zigachev }
96*b843c749SSergey Zigachev
97*b843c749SSergey Zigachev struct read_command_context {
98*b843c749SSergey Zigachev uint8_t *buffer;
99*b843c749SSergey Zigachev uint32_t current_read_length;
100*b843c749SSergey Zigachev uint32_t offset;
101*b843c749SSergey Zigachev enum i2caux_transaction_status status;
102*b843c749SSergey Zigachev
103*b843c749SSergey Zigachev struct aux_request_transaction_data request;
104*b843c749SSergey Zigachev struct aux_reply_transaction_data reply;
105*b843c749SSergey Zigachev
106*b843c749SSergey Zigachev uint8_t returned_byte;
107*b843c749SSergey Zigachev
108*b843c749SSergey Zigachev uint32_t timed_out_retry_aux;
109*b843c749SSergey Zigachev uint32_t invalid_reply_retry_aux;
110*b843c749SSergey Zigachev uint32_t defer_retry_aux;
111*b843c749SSergey Zigachev uint32_t defer_retry_i2c;
112*b843c749SSergey Zigachev uint32_t invalid_reply_retry_aux_on_ack;
113*b843c749SSergey Zigachev
114*b843c749SSergey Zigachev bool transaction_complete;
115*b843c749SSergey Zigachev bool operation_succeeded;
116*b843c749SSergey Zigachev };
117*b843c749SSergey Zigachev
process_read_reply(struct aux_engine * engine,struct read_command_context * ctx)118*b843c749SSergey Zigachev static void process_read_reply(
119*b843c749SSergey Zigachev struct aux_engine *engine,
120*b843c749SSergey Zigachev struct read_command_context *ctx)
121*b843c749SSergey Zigachev {
122*b843c749SSergey Zigachev engine->funcs->process_channel_reply(engine, &ctx->reply);
123*b843c749SSergey Zigachev
124*b843c749SSergey Zigachev switch (ctx->reply.status) {
125*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_ACK:
126*b843c749SSergey Zigachev ctx->defer_retry_aux = 0;
127*b843c749SSergey Zigachev if (ctx->returned_byte > ctx->current_read_length) {
128*b843c749SSergey Zigachev ctx->status =
129*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
130*b843c749SSergey Zigachev ctx->operation_succeeded = false;
131*b843c749SSergey Zigachev } else if (ctx->returned_byte < ctx->current_read_length) {
132*b843c749SSergey Zigachev ctx->current_read_length -= ctx->returned_byte;
133*b843c749SSergey Zigachev
134*b843c749SSergey Zigachev ctx->offset += ctx->returned_byte;
135*b843c749SSergey Zigachev
136*b843c749SSergey Zigachev ++ctx->invalid_reply_retry_aux_on_ack;
137*b843c749SSergey Zigachev
138*b843c749SSergey Zigachev if (ctx->invalid_reply_retry_aux_on_ack >
139*b843c749SSergey Zigachev AUX_INVALID_REPLY_RETRY_COUNTER) {
140*b843c749SSergey Zigachev ctx->status =
141*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
142*b843c749SSergey Zigachev ctx->operation_succeeded = false;
143*b843c749SSergey Zigachev }
144*b843c749SSergey Zigachev } else {
145*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
146*b843c749SSergey Zigachev ctx->transaction_complete = true;
147*b843c749SSergey Zigachev ctx->operation_succeeded = true;
148*b843c749SSergey Zigachev }
149*b843c749SSergey Zigachev break;
150*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_NACK:
151*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
152*b843c749SSergey Zigachev ctx->operation_succeeded = false;
153*b843c749SSergey Zigachev break;
154*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_DEFER:
155*b843c749SSergey Zigachev ++ctx->defer_retry_aux;
156*b843c749SSergey Zigachev
157*b843c749SSergey Zigachev if (ctx->defer_retry_aux > AUX_DEFER_RETRY_COUNTER) {
158*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
159*b843c749SSergey Zigachev ctx->operation_succeeded = false;
160*b843c749SSergey Zigachev }
161*b843c749SSergey Zigachev break;
162*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_I2C_DEFER:
163*b843c749SSergey Zigachev ctx->defer_retry_aux = 0;
164*b843c749SSergey Zigachev
165*b843c749SSergey Zigachev ++ctx->defer_retry_i2c;
166*b843c749SSergey Zigachev
167*b843c749SSergey Zigachev if (ctx->defer_retry_i2c > AUX_DEFER_RETRY_COUNTER) {
168*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
169*b843c749SSergey Zigachev ctx->operation_succeeded = false;
170*b843c749SSergey Zigachev }
171*b843c749SSergey Zigachev break;
172*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_HPD_DISCON:
173*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
174*b843c749SSergey Zigachev ctx->operation_succeeded = false;
175*b843c749SSergey Zigachev break;
176*b843c749SSergey Zigachev default:
177*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
178*b843c749SSergey Zigachev ctx->operation_succeeded = false;
179*b843c749SSergey Zigachev }
180*b843c749SSergey Zigachev }
181*b843c749SSergey Zigachev
process_read_request(struct aux_engine * engine,struct read_command_context * ctx)182*b843c749SSergey Zigachev static void process_read_request(
183*b843c749SSergey Zigachev struct aux_engine *engine,
184*b843c749SSergey Zigachev struct read_command_context *ctx)
185*b843c749SSergey Zigachev {
186*b843c749SSergey Zigachev enum aux_channel_operation_result operation_result;
187*b843c749SSergey Zigachev
188*b843c749SSergey Zigachev engine->funcs->submit_channel_request(engine, &ctx->request);
189*b843c749SSergey Zigachev
190*b843c749SSergey Zigachev operation_result = engine->funcs->get_channel_status(
191*b843c749SSergey Zigachev engine, &ctx->returned_byte);
192*b843c749SSergey Zigachev
193*b843c749SSergey Zigachev switch (operation_result) {
194*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_SUCCEEDED:
195*b843c749SSergey Zigachev if (ctx->returned_byte > ctx->current_read_length) {
196*b843c749SSergey Zigachev ctx->status =
197*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
198*b843c749SSergey Zigachev ctx->operation_succeeded = false;
199*b843c749SSergey Zigachev } else {
200*b843c749SSergey Zigachev ctx->timed_out_retry_aux = 0;
201*b843c749SSergey Zigachev ctx->invalid_reply_retry_aux = 0;
202*b843c749SSergey Zigachev
203*b843c749SSergey Zigachev ctx->reply.length = ctx->returned_byte;
204*b843c749SSergey Zigachev ctx->reply.data = ctx->buffer;
205*b843c749SSergey Zigachev
206*b843c749SSergey Zigachev process_read_reply(engine, ctx);
207*b843c749SSergey Zigachev }
208*b843c749SSergey Zigachev break;
209*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
210*b843c749SSergey Zigachev ++ctx->invalid_reply_retry_aux;
211*b843c749SSergey Zigachev
212*b843c749SSergey Zigachev if (ctx->invalid_reply_retry_aux >
213*b843c749SSergey Zigachev AUX_INVALID_REPLY_RETRY_COUNTER) {
214*b843c749SSergey Zigachev ctx->status =
215*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
216*b843c749SSergey Zigachev ctx->operation_succeeded = false;
217*b843c749SSergey Zigachev } else
218*b843c749SSergey Zigachev udelay(400);
219*b843c749SSergey Zigachev break;
220*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
221*b843c749SSergey Zigachev ++ctx->timed_out_retry_aux;
222*b843c749SSergey Zigachev
223*b843c749SSergey Zigachev if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
224*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
225*b843c749SSergey Zigachev ctx->operation_succeeded = false;
226*b843c749SSergey Zigachev } else {
227*b843c749SSergey Zigachev /* DP 1.2a, table 2-58:
228*b843c749SSergey Zigachev * "S3: AUX Request CMD PENDING:
229*b843c749SSergey Zigachev * retry 3 times, with 400usec wait on each"
230*b843c749SSergey Zigachev * The HW timeout is set to 550usec,
231*b843c749SSergey Zigachev * so we should not wait here */
232*b843c749SSergey Zigachev }
233*b843c749SSergey Zigachev break;
234*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
235*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
236*b843c749SSergey Zigachev ctx->operation_succeeded = false;
237*b843c749SSergey Zigachev break;
238*b843c749SSergey Zigachev default:
239*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
240*b843c749SSergey Zigachev ctx->operation_succeeded = false;
241*b843c749SSergey Zigachev }
242*b843c749SSergey Zigachev }
243*b843c749SSergey Zigachev
read_command(struct aux_engine * engine,struct i2caux_transaction_request * request,bool middle_of_transaction)244*b843c749SSergey Zigachev static bool read_command(
245*b843c749SSergey Zigachev struct aux_engine *engine,
246*b843c749SSergey Zigachev struct i2caux_transaction_request *request,
247*b843c749SSergey Zigachev bool middle_of_transaction)
248*b843c749SSergey Zigachev {
249*b843c749SSergey Zigachev struct read_command_context ctx;
250*b843c749SSergey Zigachev
251*b843c749SSergey Zigachev ctx.buffer = request->payload.data;
252*b843c749SSergey Zigachev ctx.current_read_length = request->payload.length;
253*b843c749SSergey Zigachev ctx.offset = 0;
254*b843c749SSergey Zigachev ctx.timed_out_retry_aux = 0;
255*b843c749SSergey Zigachev ctx.invalid_reply_retry_aux = 0;
256*b843c749SSergey Zigachev ctx.defer_retry_aux = 0;
257*b843c749SSergey Zigachev ctx.defer_retry_i2c = 0;
258*b843c749SSergey Zigachev ctx.invalid_reply_retry_aux_on_ack = 0;
259*b843c749SSergey Zigachev ctx.transaction_complete = false;
260*b843c749SSergey Zigachev ctx.operation_succeeded = true;
261*b843c749SSergey Zigachev
262*b843c749SSergey Zigachev if (request->payload.address_space ==
263*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
264*b843c749SSergey Zigachev ctx.request.type = AUX_TRANSACTION_TYPE_DP;
265*b843c749SSergey Zigachev ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
266*b843c749SSergey Zigachev ctx.request.address = request->payload.address;
267*b843c749SSergey Zigachev } else if (request->payload.address_space ==
268*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
269*b843c749SSergey Zigachev ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
270*b843c749SSergey Zigachev ctx.request.action = middle_of_transaction ?
271*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
272*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_READ;
273*b843c749SSergey Zigachev ctx.request.address = request->payload.address >> 1;
274*b843c749SSergey Zigachev } else {
275*b843c749SSergey Zigachev /* in DAL2, there was no return in such case */
276*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
277*b843c749SSergey Zigachev return false;
278*b843c749SSergey Zigachev }
279*b843c749SSergey Zigachev
280*b843c749SSergey Zigachev ctx.request.delay = 0;
281*b843c749SSergey Zigachev
282*b843c749SSergey Zigachev do {
283*b843c749SSergey Zigachev memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
284*b843c749SSergey Zigachev
285*b843c749SSergey Zigachev ctx.request.data = ctx.buffer + ctx.offset;
286*b843c749SSergey Zigachev ctx.request.length = ctx.current_read_length;
287*b843c749SSergey Zigachev
288*b843c749SSergey Zigachev process_read_request(engine, &ctx);
289*b843c749SSergey Zigachev
290*b843c749SSergey Zigachev request->status = ctx.status;
291*b843c749SSergey Zigachev
292*b843c749SSergey Zigachev if (ctx.operation_succeeded && !ctx.transaction_complete)
293*b843c749SSergey Zigachev if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
294*b843c749SSergey Zigachev msleep(engine->delay);
295*b843c749SSergey Zigachev } while (ctx.operation_succeeded && !ctx.transaction_complete);
296*b843c749SSergey Zigachev
297*b843c749SSergey Zigachev if (request->payload.address_space ==
298*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
299*b843c749SSergey Zigachev DC_LOG_I2C_AUX("READ: addr:0x%x value:0x%x Result:%d",
300*b843c749SSergey Zigachev request->payload.address,
301*b843c749SSergey Zigachev request->payload.data[0],
302*b843c749SSergey Zigachev ctx.operation_succeeded);
303*b843c749SSergey Zigachev }
304*b843c749SSergey Zigachev
305*b843c749SSergey Zigachev return ctx.operation_succeeded;
306*b843c749SSergey Zigachev }
307*b843c749SSergey Zigachev
308*b843c749SSergey Zigachev struct write_command_context {
309*b843c749SSergey Zigachev bool mot;
310*b843c749SSergey Zigachev
311*b843c749SSergey Zigachev uint8_t *buffer;
312*b843c749SSergey Zigachev uint32_t current_write_length;
313*b843c749SSergey Zigachev enum i2caux_transaction_status status;
314*b843c749SSergey Zigachev
315*b843c749SSergey Zigachev struct aux_request_transaction_data request;
316*b843c749SSergey Zigachev struct aux_reply_transaction_data reply;
317*b843c749SSergey Zigachev
318*b843c749SSergey Zigachev uint8_t returned_byte;
319*b843c749SSergey Zigachev
320*b843c749SSergey Zigachev uint32_t timed_out_retry_aux;
321*b843c749SSergey Zigachev uint32_t invalid_reply_retry_aux;
322*b843c749SSergey Zigachev uint32_t defer_retry_aux;
323*b843c749SSergey Zigachev uint32_t defer_retry_i2c;
324*b843c749SSergey Zigachev uint32_t max_defer_retry;
325*b843c749SSergey Zigachev uint32_t ack_m_retry;
326*b843c749SSergey Zigachev
327*b843c749SSergey Zigachev uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
328*b843c749SSergey Zigachev
329*b843c749SSergey Zigachev bool transaction_complete;
330*b843c749SSergey Zigachev bool operation_succeeded;
331*b843c749SSergey Zigachev };
332*b843c749SSergey Zigachev
process_write_reply(struct aux_engine * engine,struct write_command_context * ctx)333*b843c749SSergey Zigachev static void process_write_reply(
334*b843c749SSergey Zigachev struct aux_engine *engine,
335*b843c749SSergey Zigachev struct write_command_context *ctx)
336*b843c749SSergey Zigachev {
337*b843c749SSergey Zigachev engine->funcs->process_channel_reply(engine, &ctx->reply);
338*b843c749SSergey Zigachev
339*b843c749SSergey Zigachev switch (ctx->reply.status) {
340*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_ACK:
341*b843c749SSergey Zigachev ctx->operation_succeeded = true;
342*b843c749SSergey Zigachev
343*b843c749SSergey Zigachev if (ctx->returned_byte) {
344*b843c749SSergey Zigachev ctx->request.action = ctx->mot ?
345*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
346*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
347*b843c749SSergey Zigachev
348*b843c749SSergey Zigachev ctx->current_write_length = 0;
349*b843c749SSergey Zigachev
350*b843c749SSergey Zigachev ++ctx->ack_m_retry;
351*b843c749SSergey Zigachev
352*b843c749SSergey Zigachev if (ctx->ack_m_retry > AUX_DEFER_RETRY_COUNTER) {
353*b843c749SSergey Zigachev ctx->status =
354*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
355*b843c749SSergey Zigachev ctx->operation_succeeded = false;
356*b843c749SSergey Zigachev } else
357*b843c749SSergey Zigachev udelay(300);
358*b843c749SSergey Zigachev } else {
359*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
360*b843c749SSergey Zigachev ctx->defer_retry_aux = 0;
361*b843c749SSergey Zigachev ctx->ack_m_retry = 0;
362*b843c749SSergey Zigachev ctx->transaction_complete = true;
363*b843c749SSergey Zigachev }
364*b843c749SSergey Zigachev break;
365*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_NACK:
366*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
367*b843c749SSergey Zigachev ctx->operation_succeeded = false;
368*b843c749SSergey Zigachev break;
369*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_AUX_DEFER:
370*b843c749SSergey Zigachev ++ctx->defer_retry_aux;
371*b843c749SSergey Zigachev
372*b843c749SSergey Zigachev if (ctx->defer_retry_aux > ctx->max_defer_retry) {
373*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
374*b843c749SSergey Zigachev ctx->operation_succeeded = false;
375*b843c749SSergey Zigachev }
376*b843c749SSergey Zigachev break;
377*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_I2C_DEFER:
378*b843c749SSergey Zigachev ctx->defer_retry_aux = 0;
379*b843c749SSergey Zigachev ctx->current_write_length = 0;
380*b843c749SSergey Zigachev
381*b843c749SSergey Zigachev ctx->request.action = ctx->mot ?
382*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT :
383*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST;
384*b843c749SSergey Zigachev
385*b843c749SSergey Zigachev ++ctx->defer_retry_i2c;
386*b843c749SSergey Zigachev
387*b843c749SSergey Zigachev if (ctx->defer_retry_i2c > ctx->max_defer_retry) {
388*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
389*b843c749SSergey Zigachev ctx->operation_succeeded = false;
390*b843c749SSergey Zigachev }
391*b843c749SSergey Zigachev break;
392*b843c749SSergey Zigachev case AUX_TRANSACTION_REPLY_HPD_DISCON:
393*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
394*b843c749SSergey Zigachev ctx->operation_succeeded = false;
395*b843c749SSergey Zigachev break;
396*b843c749SSergey Zigachev default:
397*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
398*b843c749SSergey Zigachev ctx->operation_succeeded = false;
399*b843c749SSergey Zigachev }
400*b843c749SSergey Zigachev }
401*b843c749SSergey Zigachev
process_write_request(struct aux_engine * engine,struct write_command_context * ctx)402*b843c749SSergey Zigachev static void process_write_request(
403*b843c749SSergey Zigachev struct aux_engine *engine,
404*b843c749SSergey Zigachev struct write_command_context *ctx)
405*b843c749SSergey Zigachev {
406*b843c749SSergey Zigachev enum aux_channel_operation_result operation_result;
407*b843c749SSergey Zigachev
408*b843c749SSergey Zigachev engine->funcs->submit_channel_request(engine, &ctx->request);
409*b843c749SSergey Zigachev
410*b843c749SSergey Zigachev operation_result = engine->funcs->get_channel_status(
411*b843c749SSergey Zigachev engine, &ctx->returned_byte);
412*b843c749SSergey Zigachev
413*b843c749SSergey Zigachev switch (operation_result) {
414*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_SUCCEEDED:
415*b843c749SSergey Zigachev ctx->timed_out_retry_aux = 0;
416*b843c749SSergey Zigachev ctx->invalid_reply_retry_aux = 0;
417*b843c749SSergey Zigachev
418*b843c749SSergey Zigachev ctx->reply.length = ctx->returned_byte;
419*b843c749SSergey Zigachev ctx->reply.data = ctx->reply_data;
420*b843c749SSergey Zigachev
421*b843c749SSergey Zigachev process_write_reply(engine, ctx);
422*b843c749SSergey Zigachev break;
423*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_INVALID_REPLY:
424*b843c749SSergey Zigachev ++ctx->invalid_reply_retry_aux;
425*b843c749SSergey Zigachev
426*b843c749SSergey Zigachev if (ctx->invalid_reply_retry_aux >
427*b843c749SSergey Zigachev AUX_INVALID_REPLY_RETRY_COUNTER) {
428*b843c749SSergey Zigachev ctx->status =
429*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR;
430*b843c749SSergey Zigachev ctx->operation_succeeded = false;
431*b843c749SSergey Zigachev } else
432*b843c749SSergey Zigachev udelay(400);
433*b843c749SSergey Zigachev break;
434*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_TIMEOUT:
435*b843c749SSergey Zigachev ++ctx->timed_out_retry_aux;
436*b843c749SSergey Zigachev
437*b843c749SSergey Zigachev if (ctx->timed_out_retry_aux > AUX_TIMED_OUT_RETRY_COUNTER) {
438*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
439*b843c749SSergey Zigachev ctx->operation_succeeded = false;
440*b843c749SSergey Zigachev } else {
441*b843c749SSergey Zigachev /* DP 1.2a, table 2-58:
442*b843c749SSergey Zigachev * "S3: AUX Request CMD PENDING:
443*b843c749SSergey Zigachev * retry 3 times, with 400usec wait on each"
444*b843c749SSergey Zigachev * The HW timeout is set to 550usec,
445*b843c749SSergey Zigachev * so we should not wait here */
446*b843c749SSergey Zigachev }
447*b843c749SSergey Zigachev break;
448*b843c749SSergey Zigachev case AUX_CHANNEL_OPERATION_FAILED_HPD_DISCON:
449*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON;
450*b843c749SSergey Zigachev ctx->operation_succeeded = false;
451*b843c749SSergey Zigachev break;
452*b843c749SSergey Zigachev default:
453*b843c749SSergey Zigachev ctx->status = I2CAUX_TRANSACTION_STATUS_UNKNOWN;
454*b843c749SSergey Zigachev ctx->operation_succeeded = false;
455*b843c749SSergey Zigachev }
456*b843c749SSergey Zigachev }
457*b843c749SSergey Zigachev
write_command(struct aux_engine * engine,struct i2caux_transaction_request * request,bool middle_of_transaction)458*b843c749SSergey Zigachev static bool write_command(
459*b843c749SSergey Zigachev struct aux_engine *engine,
460*b843c749SSergey Zigachev struct i2caux_transaction_request *request,
461*b843c749SSergey Zigachev bool middle_of_transaction)
462*b843c749SSergey Zigachev {
463*b843c749SSergey Zigachev struct write_command_context ctx;
464*b843c749SSergey Zigachev
465*b843c749SSergey Zigachev ctx.mot = middle_of_transaction;
466*b843c749SSergey Zigachev ctx.buffer = request->payload.data;
467*b843c749SSergey Zigachev ctx.current_write_length = request->payload.length;
468*b843c749SSergey Zigachev ctx.timed_out_retry_aux = 0;
469*b843c749SSergey Zigachev ctx.invalid_reply_retry_aux = 0;
470*b843c749SSergey Zigachev ctx.defer_retry_aux = 0;
471*b843c749SSergey Zigachev ctx.defer_retry_i2c = 0;
472*b843c749SSergey Zigachev ctx.ack_m_retry = 0;
473*b843c749SSergey Zigachev ctx.transaction_complete = false;
474*b843c749SSergey Zigachev ctx.operation_succeeded = true;
475*b843c749SSergey Zigachev
476*b843c749SSergey Zigachev if (request->payload.address_space ==
477*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
478*b843c749SSergey Zigachev ctx.request.type = AUX_TRANSACTION_TYPE_DP;
479*b843c749SSergey Zigachev ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_WRITE;
480*b843c749SSergey Zigachev ctx.request.address = request->payload.address;
481*b843c749SSergey Zigachev } else if (request->payload.address_space ==
482*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
483*b843c749SSergey Zigachev ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
484*b843c749SSergey Zigachev ctx.request.action = middle_of_transaction ?
485*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
486*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
487*b843c749SSergey Zigachev ctx.request.address = request->payload.address >> 1;
488*b843c749SSergey Zigachev } else {
489*b843c749SSergey Zigachev /* in DAL2, there was no return in such case */
490*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
491*b843c749SSergey Zigachev return false;
492*b843c749SSergey Zigachev }
493*b843c749SSergey Zigachev
494*b843c749SSergey Zigachev ctx.request.delay = 0;
495*b843c749SSergey Zigachev
496*b843c749SSergey Zigachev ctx.max_defer_retry =
497*b843c749SSergey Zigachev (engine->max_defer_write_retry > AUX_DEFER_RETRY_COUNTER) ?
498*b843c749SSergey Zigachev engine->max_defer_write_retry : AUX_DEFER_RETRY_COUNTER;
499*b843c749SSergey Zigachev
500*b843c749SSergey Zigachev do {
501*b843c749SSergey Zigachev ctx.request.data = ctx.buffer;
502*b843c749SSergey Zigachev ctx.request.length = ctx.current_write_length;
503*b843c749SSergey Zigachev
504*b843c749SSergey Zigachev process_write_request(engine, &ctx);
505*b843c749SSergey Zigachev
506*b843c749SSergey Zigachev request->status = ctx.status;
507*b843c749SSergey Zigachev
508*b843c749SSergey Zigachev if (ctx.operation_succeeded && !ctx.transaction_complete)
509*b843c749SSergey Zigachev if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C)
510*b843c749SSergey Zigachev msleep(engine->delay);
511*b843c749SSergey Zigachev } while (ctx.operation_succeeded && !ctx.transaction_complete);
512*b843c749SSergey Zigachev
513*b843c749SSergey Zigachev if (request->payload.address_space ==
514*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
515*b843c749SSergey Zigachev DC_LOG_I2C_AUX("WRITE: addr:0x%x value:0x%x Result:%d",
516*b843c749SSergey Zigachev request->payload.address,
517*b843c749SSergey Zigachev request->payload.data[0],
518*b843c749SSergey Zigachev ctx.operation_succeeded);
519*b843c749SSergey Zigachev }
520*b843c749SSergey Zigachev
521*b843c749SSergey Zigachev return ctx.operation_succeeded;
522*b843c749SSergey Zigachev }
523*b843c749SSergey Zigachev
end_of_transaction_command(struct aux_engine * engine,struct i2caux_transaction_request * request)524*b843c749SSergey Zigachev static bool end_of_transaction_command(
525*b843c749SSergey Zigachev struct aux_engine *engine,
526*b843c749SSergey Zigachev struct i2caux_transaction_request *request)
527*b843c749SSergey Zigachev {
528*b843c749SSergey Zigachev struct i2caux_transaction_request dummy_request;
529*b843c749SSergey Zigachev uint8_t dummy_data;
530*b843c749SSergey Zigachev
531*b843c749SSergey Zigachev /* [tcheng] We only need to send the stop (read with MOT = 0)
532*b843c749SSergey Zigachev * for I2C-over-Aux, not native AUX */
533*b843c749SSergey Zigachev
534*b843c749SSergey Zigachev if (request->payload.address_space !=
535*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C)
536*b843c749SSergey Zigachev return false;
537*b843c749SSergey Zigachev
538*b843c749SSergey Zigachev dummy_request.operation = request->operation;
539*b843c749SSergey Zigachev dummy_request.payload.address_space = request->payload.address_space;
540*b843c749SSergey Zigachev dummy_request.payload.address = request->payload.address;
541*b843c749SSergey Zigachev
542*b843c749SSergey Zigachev /*
543*b843c749SSergey Zigachev * Add a dummy byte due to some receiver quirk
544*b843c749SSergey Zigachev * where one byte is sent along with MOT = 0.
545*b843c749SSergey Zigachev * Ideally this should be 0.
546*b843c749SSergey Zigachev */
547*b843c749SSergey Zigachev
548*b843c749SSergey Zigachev dummy_request.payload.length = 0;
549*b843c749SSergey Zigachev dummy_request.payload.data = &dummy_data;
550*b843c749SSergey Zigachev
551*b843c749SSergey Zigachev if (request->operation == I2CAUX_TRANSACTION_READ)
552*b843c749SSergey Zigachev return read_command(engine, &dummy_request, false);
553*b843c749SSergey Zigachev else
554*b843c749SSergey Zigachev return write_command(engine, &dummy_request, false);
555*b843c749SSergey Zigachev
556*b843c749SSergey Zigachev /* according Syed, it does not need now DoDummyMOT */
557*b843c749SSergey Zigachev }
558*b843c749SSergey Zigachev
dal_aux_engine_submit_request(struct engine * engine,struct i2caux_transaction_request * request,bool middle_of_transaction)559*b843c749SSergey Zigachev bool dal_aux_engine_submit_request(
560*b843c749SSergey Zigachev struct engine *engine,
561*b843c749SSergey Zigachev struct i2caux_transaction_request *request,
562*b843c749SSergey Zigachev bool middle_of_transaction)
563*b843c749SSergey Zigachev {
564*b843c749SSergey Zigachev struct aux_engine *aux_engine = FROM_ENGINE(engine);
565*b843c749SSergey Zigachev
566*b843c749SSergey Zigachev bool result;
567*b843c749SSergey Zigachev bool mot_used = true;
568*b843c749SSergey Zigachev
569*b843c749SSergey Zigachev switch (request->operation) {
570*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_READ:
571*b843c749SSergey Zigachev result = read_command(aux_engine, request, mot_used);
572*b843c749SSergey Zigachev break;
573*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_WRITE:
574*b843c749SSergey Zigachev result = write_command(aux_engine, request, mot_used);
575*b843c749SSergey Zigachev break;
576*b843c749SSergey Zigachev default:
577*b843c749SSergey Zigachev result = false;
578*b843c749SSergey Zigachev }
579*b843c749SSergey Zigachev
580*b843c749SSergey Zigachev /* [tcheng]
581*b843c749SSergey Zigachev * need to send stop for the last transaction to free up the AUX
582*b843c749SSergey Zigachev * if the above command fails, this would be the last transaction */
583*b843c749SSergey Zigachev
584*b843c749SSergey Zigachev if (!middle_of_transaction || !result)
585*b843c749SSergey Zigachev end_of_transaction_command(aux_engine, request);
586*b843c749SSergey Zigachev
587*b843c749SSergey Zigachev /* mask AUX interrupt */
588*b843c749SSergey Zigachev
589*b843c749SSergey Zigachev return result;
590*b843c749SSergey Zigachev }
591*b843c749SSergey Zigachev
dal_aux_engine_construct(struct aux_engine * engine,struct dc_context * ctx)592*b843c749SSergey Zigachev void dal_aux_engine_construct(
593*b843c749SSergey Zigachev struct aux_engine *engine,
594*b843c749SSergey Zigachev struct dc_context *ctx)
595*b843c749SSergey Zigachev {
596*b843c749SSergey Zigachev dal_i2caux_construct_engine(&engine->base, ctx);
597*b843c749SSergey Zigachev engine->delay = 0;
598*b843c749SSergey Zigachev engine->max_defer_write_retry = 0;
599*b843c749SSergey Zigachev }
600*b843c749SSergey Zigachev
dal_aux_engine_destruct(struct aux_engine * engine)601*b843c749SSergey Zigachev void dal_aux_engine_destruct(
602*b843c749SSergey Zigachev struct aux_engine *engine)
603*b843c749SSergey Zigachev {
604*b843c749SSergey Zigachev dal_i2caux_destruct_engine(&engine->base);
605*b843c749SSergey Zigachev }
606