1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "include/logger_interface.h" 28 /* 29 * Pre-requisites: headers required by header of this unit 30 */ 31 32 #include "include/i2caux_interface.h" 33 #include "../engine.h" 34 #include "../i2c_engine.h" 35 #include "../i2c_hw_engine.h" 36 #include "../i2c_generic_hw_engine.h" 37 /* 38 * Header of this unit 39 */ 40 41 #include "i2c_hw_engine_dce110.h" 42 43 /* 44 * Post-requisites: headers required by this unit 45 */ 46 #include "reg_helper.h" 47 48 /* 49 * This unit 50 */ 51 #define DC_LOGGER \ 52 hw_engine->base.base.base.ctx->logger 53 54 enum dc_i2c_status { 55 DC_I2C_STATUS__DC_I2C_STATUS_IDLE, 56 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW, 57 DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW 58 }; 59 60 enum dc_i2c_arbitration { 61 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL, 62 DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_HIGH 63 }; 64 65 66 67 /* 68 * @brief 69 * Cast pointer to 'struct i2c_hw_engine *' 70 * to pointer 'struct i2c_hw_engine_dce110 *' 71 */ 72 #define FROM_I2C_HW_ENGINE(ptr) \ 73 container_of((ptr), struct i2c_hw_engine_dce110, base) 74 /* 75 * @brief 76 * Cast pointer to 'struct i2c_engine *' 77 * to pointer to 'struct i2c_hw_engine_dce110 *' 78 */ 79 #define FROM_I2C_ENGINE(ptr) \ 80 FROM_I2C_HW_ENGINE(container_of((ptr), struct i2c_hw_engine, base)) 81 82 /* 83 * @brief 84 * Cast pointer to 'struct engine *' 85 * to 'pointer to struct i2c_hw_engine_dce110 *' 86 */ 87 #define FROM_ENGINE(ptr) \ 88 FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base)) 89 90 #define CTX \ 91 hw_engine->base.base.base.ctx 92 93 #define REG(reg_name)\ 94 (hw_engine->regs->reg_name) 95 96 #undef FN 97 #define FN(reg_name, field_name) \ 98 hw_engine->i2c_shift->field_name, hw_engine->i2c_mask->field_name 99 100 #include "reg_helper.h" 101 102 static void disable_i2c_hw_engine( 103 struct i2c_hw_engine_dce110 *hw_engine) 104 { 105 REG_UPDATE_N(SETUP, 1, FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 0); 106 } 107 108 static void release_engine( 109 struct engine *engine) 110 { 111 struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine); 112 113 struct i2c_engine *base = NULL; 114 bool safe_to_reset; 115 116 base = &hw_engine->base.base; 117 118 /* Restore original HW engine speed */ 119 120 base->funcs->set_speed(base, hw_engine->base.original_speed); 121 122 /* Release I2C */ 123 REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1); 124 125 /* Reset HW engine */ 126 { 127 uint32_t i2c_sw_status = 0; 128 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 129 /* if used by SW, safe to reset */ 130 safe_to_reset = (i2c_sw_status == 1); 131 } 132 133 if (safe_to_reset) 134 REG_UPDATE_2( 135 DC_I2C_CONTROL, 136 DC_I2C_SOFT_RESET, 1, 137 DC_I2C_SW_STATUS_RESET, 1); 138 else 139 REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1); 140 141 /* HW I2c engine - clock gating feature */ 142 if (!hw_engine->engine_keep_power_up_count) 143 disable_i2c_hw_engine(hw_engine); 144 } 145 146 static bool setup_engine( 147 struct i2c_engine *i2c_engine) 148 { 149 struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine); 150 uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE; 151 uint32_t reset_length = 0; 152 153 if (hw_engine->base.base.setup_limit != 0) 154 i2c_setup_limit = hw_engine->base.base.setup_limit; 155 156 /* Program pin select */ 157 REG_UPDATE_6( 158 DC_I2C_CONTROL, 159 DC_I2C_GO, 0, 160 DC_I2C_SOFT_RESET, 0, 161 DC_I2C_SEND_RESET, 0, 162 DC_I2C_SW_STATUS_RESET, 1, 163 DC_I2C_TRANSACTION_COUNT, 0, 164 DC_I2C_DDC_SELECT, hw_engine->engine_id); 165 166 /* Program time limit */ 167 if (hw_engine->base.base.send_reset_length == 0) { 168 /*pre-dcn*/ 169 REG_UPDATE_N( 170 SETUP, 2, 171 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit, 172 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1); 173 } else { 174 reset_length = hw_engine->base.base.send_reset_length; 175 } 176 /* Program HW priority 177 * set to High - interrupt software I2C at any time 178 * Enable restart of SW I2C that was interrupted by HW 179 * disable queuing of software while I2C is in use by HW */ 180 REG_UPDATE_2( 181 DC_I2C_ARBITRATION, 182 DC_I2C_NO_QUEUED_SW_GO, 0, 183 DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL); 184 185 return true; 186 } 187 188 static uint32_t get_speed( 189 const struct i2c_engine *i2c_engine) 190 { 191 const struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine); 192 uint32_t pre_scale = 0; 193 194 REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale); 195 196 /* [anaumov] it seems following is unnecessary */ 197 /*ASSERT(value.bits.DC_I2C_DDC1_PRESCALE);*/ 198 return pre_scale ? 199 hw_engine->reference_frequency / pre_scale : 200 hw_engine->base.default_speed; 201 } 202 203 static void set_speed( 204 struct i2c_engine *i2c_engine, 205 uint32_t speed) 206 { 207 struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine); 208 209 if (speed) { 210 if (hw_engine->i2c_mask->DC_I2C_DDC1_START_STOP_TIMING_CNTL) 211 REG_UPDATE_N( 212 SPEED, 3, 213 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed, 214 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2, 215 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1); 216 else 217 REG_UPDATE_N( 218 SPEED, 2, 219 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), hw_engine->reference_frequency / speed, 220 FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2); 221 } 222 } 223 224 static inline void reset_hw_engine(struct engine *engine) 225 { 226 struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine); 227 228 REG_UPDATE_2( 229 DC_I2C_CONTROL, 230 DC_I2C_SW_STATUS_RESET, 1, 231 DC_I2C_SW_STATUS_RESET, 1); 232 } 233 234 static bool is_hw_busy(struct engine *engine) 235 { 236 struct i2c_hw_engine_dce110 *hw_engine = FROM_ENGINE(engine); 237 uint32_t i2c_sw_status = 0; 238 239 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 240 if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE) 241 return false; 242 243 reset_hw_engine(engine); 244 245 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 246 return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE; 247 } 248 249 250 #define STOP_TRANS_PREDICAT \ 251 ((hw_engine->transaction_count == 3) || \ 252 (request->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) || \ 253 (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) 254 255 #define SET_I2C_TRANSACTION(id) \ 256 do { \ 257 REG_UPDATE_N(DC_I2C_TRANSACTION##id, 5, \ 258 FN(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0), 1, \ 259 FN(DC_I2C_TRANSACTION0, DC_I2C_START0), 1, \ 260 FN(DC_I2C_TRANSACTION0, DC_I2C_STOP0), STOP_TRANS_PREDICAT ? 1:0, \ 261 FN(DC_I2C_TRANSACTION0, DC_I2C_RW0), (0 != (request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)), \ 262 FN(DC_I2C_TRANSACTION0, DC_I2C_COUNT0), length); \ 263 if (STOP_TRANS_PREDICAT) \ 264 last_transaction = true; \ 265 } while (false) 266 267 268 static bool process_transaction( 269 struct i2c_hw_engine_dce110 *hw_engine, 270 struct i2c_request_transaction_data *request) 271 { 272 uint32_t length = request->length; 273 uint8_t *buffer = request->data; 274 uint32_t value = 0; 275 276 bool last_transaction = false; 277 278 struct dc_context *ctx = NULL; 279 280 ctx = hw_engine->base.base.base.ctx; 281 282 283 284 switch (hw_engine->transaction_count) { 285 case 0: 286 SET_I2C_TRANSACTION(0); 287 break; 288 case 1: 289 SET_I2C_TRANSACTION(1); 290 break; 291 case 2: 292 SET_I2C_TRANSACTION(2); 293 break; 294 case 3: 295 SET_I2C_TRANSACTION(3); 296 break; 297 default: 298 /* TODO Warning ? */ 299 break; 300 } 301 302 303 /* Write the I2C address and I2C data 304 * into the hardware circular buffer, one byte per entry. 305 * As an example, the 7-bit I2C slave address for CRT monitor 306 * for reading DDC/EDID information is 0b1010001. 307 * For an I2C send operation, the LSB must be programmed to 0; 308 * for I2C receive operation, the LSB must be programmed to 1. */ 309 if (hw_engine->transaction_count == 0) { 310 value = REG_SET_4(DC_I2C_DATA, 0, 311 DC_I2C_DATA_RW, false, 312 DC_I2C_DATA, request->address, 313 DC_I2C_INDEX, 0, 314 DC_I2C_INDEX_WRITE, 1); 315 hw_engine->buffer_used_write = 0; 316 } else 317 value = REG_SET_2(DC_I2C_DATA, 0, 318 DC_I2C_DATA_RW, false, 319 DC_I2C_DATA, request->address); 320 321 hw_engine->buffer_used_write++; 322 323 if (!(request->action & I2CAUX_TRANSACTION_ACTION_I2C_READ)) { 324 while (length) { 325 REG_SET_2(DC_I2C_DATA, value, 326 DC_I2C_INDEX_WRITE, 0, 327 DC_I2C_DATA, *buffer++); 328 hw_engine->buffer_used_write++; 329 --length; 330 } 331 } 332 333 ++hw_engine->transaction_count; 334 hw_engine->buffer_used_bytes += length + 1; 335 336 return last_transaction; 337 } 338 339 static void execute_transaction( 340 struct i2c_hw_engine_dce110 *hw_engine) 341 { 342 REG_UPDATE_N(SETUP, 5, 343 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0, 344 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0, 345 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0, 346 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0, 347 FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0); 348 349 350 REG_UPDATE_5(DC_I2C_CONTROL, 351 DC_I2C_SOFT_RESET, 0, 352 DC_I2C_SW_STATUS_RESET, 0, 353 DC_I2C_SEND_RESET, 0, 354 DC_I2C_GO, 0, 355 DC_I2C_TRANSACTION_COUNT, hw_engine->transaction_count - 1); 356 357 /* start I2C transfer */ 358 REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1); 359 360 /* all transactions were executed and HW buffer became empty 361 * (even though it actually happens when status becomes DONE) */ 362 hw_engine->transaction_count = 0; 363 hw_engine->buffer_used_bytes = 0; 364 } 365 366 static void submit_channel_request( 367 struct i2c_engine *engine, 368 struct i2c_request_transaction_data *request) 369 { 370 request->status = I2C_CHANNEL_OPERATION_SUCCEEDED; 371 372 if (!process_transaction(FROM_I2C_ENGINE(engine), request)) 373 return; 374 375 if (is_hw_busy(&engine->base)) { 376 request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY; 377 return; 378 } 379 380 execute_transaction(FROM_I2C_ENGINE(engine)); 381 } 382 383 static void process_channel_reply( 384 struct i2c_engine *engine, 385 struct i2c_reply_transaction_data *reply) 386 { 387 uint32_t length = reply->length; 388 uint8_t *buffer = reply->data; 389 390 struct i2c_hw_engine_dce110 *hw_engine = 391 FROM_I2C_ENGINE(engine); 392 393 394 REG_SET_3(DC_I2C_DATA, 0, 395 DC_I2C_INDEX, hw_engine->buffer_used_write, 396 DC_I2C_DATA_RW, 1, 397 DC_I2C_INDEX_WRITE, 1); 398 399 while (length) { 400 /* after reading the status, 401 * if the I2C operation executed successfully 402 * (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller 403 * should read data bytes from I2C circular data buffer */ 404 405 uint32_t i2c_data; 406 407 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); 408 *buffer++ = i2c_data; 409 410 --length; 411 } 412 } 413 414 static enum i2c_channel_operation_result get_channel_status( 415 struct i2c_engine *i2c_engine, 416 uint8_t *returned_bytes) 417 { 418 uint32_t i2c_sw_status = 0; 419 struct i2c_hw_engine_dce110 *hw_engine = FROM_I2C_ENGINE(i2c_engine); 420 uint32_t value = 421 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); 422 423 if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW) 424 return I2C_CHANNEL_OPERATION_ENGINE_BUSY; 425 else if (value & hw_engine->i2c_mask->DC_I2C_SW_STOPPED_ON_NACK) 426 return I2C_CHANNEL_OPERATION_NO_RESPONSE; 427 else if (value & hw_engine->i2c_mask->DC_I2C_SW_TIMEOUT) 428 return I2C_CHANNEL_OPERATION_TIMEOUT; 429 else if (value & hw_engine->i2c_mask->DC_I2C_SW_ABORTED) 430 return I2C_CHANNEL_OPERATION_FAILED; 431 else if (value & hw_engine->i2c_mask->DC_I2C_SW_DONE) 432 return I2C_CHANNEL_OPERATION_SUCCEEDED; 433 434 /* 435 * this is the case when HW used for communication, I2C_SW_STATUS 436 * could be zero 437 */ 438 return I2C_CHANNEL_OPERATION_SUCCEEDED; 439 } 440 441 static uint32_t get_hw_buffer_available_size( 442 const struct i2c_hw_engine *engine) 443 { 444 return I2C_HW_BUFFER_SIZE - 445 FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes; 446 } 447 448 static uint32_t get_transaction_timeout( 449 const struct i2c_hw_engine *engine, 450 uint32_t length) 451 { 452 uint32_t speed = engine->base.funcs->get_speed(&engine->base); 453 454 uint32_t period_timeout; 455 uint32_t num_of_clock_stretches; 456 457 if (!speed) 458 return 0; 459 460 period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed; 461 462 num_of_clock_stretches = 1 + (length << 3) + 1; 463 num_of_clock_stretches += 464 (FROM_I2C_HW_ENGINE(engine)->buffer_used_bytes << 3) + 465 (FROM_I2C_HW_ENGINE(engine)->transaction_count << 1); 466 467 return period_timeout * num_of_clock_stretches; 468 } 469 470 static void destroy( 471 struct i2c_engine **i2c_engine) 472 { 473 struct i2c_hw_engine_dce110 *engine_dce110 = 474 FROM_I2C_ENGINE(*i2c_engine); 475 476 dal_i2c_hw_engine_destruct(&engine_dce110->base); 477 478 kfree(engine_dce110); 479 480 *i2c_engine = NULL; 481 } 482 483 static const struct i2c_engine_funcs i2c_engine_funcs = { 484 .destroy = destroy, 485 .get_speed = get_speed, 486 .set_speed = set_speed, 487 .setup_engine = setup_engine, 488 .submit_channel_request = submit_channel_request, 489 .process_channel_reply = process_channel_reply, 490 .get_channel_status = get_channel_status, 491 .acquire_engine = dal_i2c_hw_engine_acquire_engine, 492 }; 493 494 static const struct engine_funcs engine_funcs = { 495 .release_engine = release_engine, 496 .get_engine_type = dal_i2c_hw_engine_get_engine_type, 497 .acquire = dal_i2c_engine_acquire, 498 .submit_request = dal_i2c_hw_engine_submit_request, 499 }; 500 501 static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = { 502 .get_hw_buffer_available_size = get_hw_buffer_available_size, 503 .get_transaction_timeout = get_transaction_timeout, 504 .wait_on_operation_result = dal_i2c_hw_engine_wait_on_operation_result, 505 }; 506 507 static void construct( 508 struct i2c_hw_engine_dce110 *hw_engine, 509 const struct i2c_hw_engine_dce110_create_arg *arg) 510 { 511 uint32_t xtal_ref_div = 0; 512 513 dal_i2c_hw_engine_construct(&hw_engine->base, arg->ctx); 514 515 hw_engine->base.base.base.funcs = &engine_funcs; 516 hw_engine->base.base.funcs = &i2c_engine_funcs; 517 hw_engine->base.funcs = &i2c_hw_engine_funcs; 518 hw_engine->base.default_speed = arg->default_speed; 519 520 hw_engine->regs = arg->regs; 521 hw_engine->i2c_shift = arg->i2c_shift; 522 hw_engine->i2c_mask = arg->i2c_mask; 523 524 hw_engine->engine_id = arg->engine_id; 525 526 hw_engine->buffer_used_bytes = 0; 527 hw_engine->transaction_count = 0; 528 hw_engine->engine_keep_power_up_count = 1; 529 530 531 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); 532 533 if (xtal_ref_div == 0) { 534 DC_LOG_WARNING("Invalid base timer divider [%s]\n", 535 __func__); 536 xtal_ref_div = 2; 537 } 538 539 /*Calculating Reference Clock by divding original frequency by 540 * XTAL_REF_DIV. 541 * At upper level, uint32_t reference_frequency = 542 * dal_i2caux_get_reference_clock(as) >> 1 543 * which already divided by 2. So we need x2 to get original 544 * reference clock from ppll_info 545 */ 546 hw_engine->reference_frequency = 547 (arg->reference_frequency * 2) / xtal_ref_div; 548 } 549 550 struct i2c_engine *dal_i2c_hw_engine_dce110_create( 551 const struct i2c_hw_engine_dce110_create_arg *arg) 552 { 553 struct i2c_hw_engine_dce110 *engine_dce10; 554 555 if (!arg) { 556 ASSERT_CRITICAL(false); 557 return NULL; 558 } 559 if (!arg->reference_frequency) { 560 ASSERT_CRITICAL(false); 561 return NULL; 562 } 563 564 engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110), 565 GFP_KERNEL); 566 567 if (!engine_dce10) { 568 ASSERT_CRITICAL(false); 569 return NULL; 570 } 571 572 construct(engine_dce10, arg); 573 return &engine_dce10->base.base; 574 } 575