1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_I2C_HW_ENGINE_DCE110_H__ 27 #define __DAL_I2C_HW_ENGINE_DCE110_H__ 28 29 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\ 30 SRI(SETUP, DC_I2C_DDC, id),\ 31 SRI(SPEED, DC_I2C_DDC, id),\ 32 SR(DC_I2C_ARBITRATION),\ 33 SR(DC_I2C_CONTROL),\ 34 SR(DC_I2C_SW_STATUS),\ 35 SR(DC_I2C_TRANSACTION0),\ 36 SR(DC_I2C_TRANSACTION1),\ 37 SR(DC_I2C_TRANSACTION2),\ 38 SR(DC_I2C_TRANSACTION3),\ 39 SR(DC_I2C_DATA),\ 40 SR(MICROSECOND_TIME_BASE_DIV) 41 42 #define I2C_SF(reg_name, field_name, post_fix)\ 43 .field_name = reg_name ## __ ## field_name ## post_fix 44 45 #define I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 46 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 47 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT, mask_sh),\ 48 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN, mask_sh),\ 49 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN, mask_sh),\ 50 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\ 51 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\ 52 I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\ 53 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\ 54 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\ 55 I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_PRIORITY, mask_sh),\ 56 I2C_SF(DC_I2C_CONTROL, DC_I2C_SOFT_RESET, mask_sh),\ 57 I2C_SF(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, mask_sh),\ 58 I2C_SF(DC_I2C_CONTROL, DC_I2C_GO, mask_sh),\ 59 I2C_SF(DC_I2C_CONTROL, DC_I2C_SEND_RESET, mask_sh),\ 60 I2C_SF(DC_I2C_CONTROL, DC_I2C_TRANSACTION_COUNT, mask_sh),\ 61 I2C_SF(DC_I2C_CONTROL, DC_I2C_DDC_SELECT, mask_sh),\ 62 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE, mask_sh),\ 63 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD, mask_sh),\ 64 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STOPPED_ON_NACK, mask_sh),\ 65 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_TIMEOUT, mask_sh),\ 66 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_ABORTED, mask_sh),\ 67 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_DONE, mask_sh),\ 68 I2C_SF(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, mask_sh),\ 69 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP_ON_NACK0, mask_sh),\ 70 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_START0, mask_sh),\ 71 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_RW0, mask_sh),\ 72 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_STOP0, mask_sh),\ 73 I2C_SF(DC_I2C_TRANSACTION0, DC_I2C_COUNT0, mask_sh),\ 74 I2C_SF(DC_I2C_DATA, DC_I2C_DATA_RW, mask_sh),\ 75 I2C_SF(DC_I2C_DATA, DC_I2C_DATA, mask_sh),\ 76 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX, mask_sh),\ 77 I2C_SF(DC_I2C_DATA, DC_I2C_INDEX_WRITE, mask_sh),\ 78 I2C_SF(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, mask_sh) 79 80 #define I2C_COMMON_MASK_SH_LIST_DCE100(mask_sh)\ 81 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) 82 83 #define I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh)\ 84 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 85 I2C_SF(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL, mask_sh) 86 87 struct dce110_i2c_hw_engine_shift { 88 uint8_t DC_I2C_DDC1_ENABLE; 89 uint8_t DC_I2C_DDC1_TIME_LIMIT; 90 uint8_t DC_I2C_DDC1_DATA_DRIVE_EN; 91 uint8_t DC_I2C_DDC1_CLK_DRIVE_EN; 92 uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL; 93 uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 94 uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 95 uint8_t DC_I2C_SW_DONE_USING_I2C_REG; 96 uint8_t DC_I2C_NO_QUEUED_SW_GO; 97 uint8_t DC_I2C_SW_PRIORITY; 98 uint8_t DC_I2C_SOFT_RESET; 99 uint8_t DC_I2C_SW_STATUS_RESET; 100 uint8_t DC_I2C_GO; 101 uint8_t DC_I2C_SEND_RESET; 102 uint8_t DC_I2C_TRANSACTION_COUNT; 103 uint8_t DC_I2C_DDC_SELECT; 104 uint8_t DC_I2C_DDC1_PRESCALE; 105 uint8_t DC_I2C_DDC1_THRESHOLD; 106 uint8_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 107 uint8_t DC_I2C_SW_STOPPED_ON_NACK; 108 uint8_t DC_I2C_SW_TIMEOUT; 109 uint8_t DC_I2C_SW_ABORTED; 110 uint8_t DC_I2C_SW_DONE; 111 uint8_t DC_I2C_SW_STATUS; 112 uint8_t DC_I2C_STOP_ON_NACK0; 113 uint8_t DC_I2C_START0; 114 uint8_t DC_I2C_RW0; 115 uint8_t DC_I2C_STOP0; 116 uint8_t DC_I2C_COUNT0; 117 uint8_t DC_I2C_DATA_RW; 118 uint8_t DC_I2C_DATA; 119 uint8_t DC_I2C_INDEX; 120 uint8_t DC_I2C_INDEX_WRITE; 121 uint8_t XTAL_REF_DIV; 122 }; 123 124 struct dce110_i2c_hw_engine_mask { 125 uint32_t DC_I2C_DDC1_ENABLE; 126 uint32_t DC_I2C_DDC1_TIME_LIMIT; 127 uint32_t DC_I2C_DDC1_DATA_DRIVE_EN; 128 uint32_t DC_I2C_DDC1_CLK_DRIVE_EN; 129 uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL; 130 uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY; 131 uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY; 132 uint32_t DC_I2C_SW_DONE_USING_I2C_REG; 133 uint32_t DC_I2C_NO_QUEUED_SW_GO; 134 uint32_t DC_I2C_SW_PRIORITY; 135 uint32_t DC_I2C_SOFT_RESET; 136 uint32_t DC_I2C_SW_STATUS_RESET; 137 uint32_t DC_I2C_GO; 138 uint32_t DC_I2C_SEND_RESET; 139 uint32_t DC_I2C_TRANSACTION_COUNT; 140 uint32_t DC_I2C_DDC_SELECT; 141 uint32_t DC_I2C_DDC1_PRESCALE; 142 uint32_t DC_I2C_DDC1_THRESHOLD; 143 uint32_t DC_I2C_DDC1_START_STOP_TIMING_CNTL; 144 uint32_t DC_I2C_SW_STOPPED_ON_NACK; 145 uint32_t DC_I2C_SW_TIMEOUT; 146 uint32_t DC_I2C_SW_ABORTED; 147 uint32_t DC_I2C_SW_DONE; 148 uint32_t DC_I2C_SW_STATUS; 149 uint32_t DC_I2C_STOP_ON_NACK0; 150 uint32_t DC_I2C_START0; 151 uint32_t DC_I2C_RW0; 152 uint32_t DC_I2C_STOP0; 153 uint32_t DC_I2C_COUNT0; 154 uint32_t DC_I2C_DATA_RW; 155 uint32_t DC_I2C_DATA; 156 uint32_t DC_I2C_INDEX; 157 uint32_t DC_I2C_INDEX_WRITE; 158 uint32_t XTAL_REF_DIV; 159 }; 160 161 struct dce110_i2c_hw_engine_registers { 162 uint32_t SETUP; 163 uint32_t SPEED; 164 uint32_t DC_I2C_ARBITRATION; 165 uint32_t DC_I2C_CONTROL; 166 uint32_t DC_I2C_SW_STATUS; 167 uint32_t DC_I2C_TRANSACTION0; 168 uint32_t DC_I2C_TRANSACTION1; 169 uint32_t DC_I2C_TRANSACTION2; 170 uint32_t DC_I2C_TRANSACTION3; 171 uint32_t DC_I2C_DATA; 172 uint32_t MICROSECOND_TIME_BASE_DIV; 173 }; 174 175 struct i2c_hw_engine_dce110 { 176 struct i2c_hw_engine base; 177 const struct dce110_i2c_hw_engine_registers *regs; 178 const struct dce110_i2c_hw_engine_shift *i2c_shift; 179 const struct dce110_i2c_hw_engine_mask *i2c_mask; 180 struct { 181 uint32_t DC_I2C_DDCX_SETUP; 182 uint32_t DC_I2C_DDCX_SPEED; 183 } addr; 184 uint32_t engine_id; 185 /* expressed in kilohertz */ 186 uint32_t reference_frequency; 187 /* number of bytes currently used in HW buffer */ 188 uint32_t buffer_used_bytes; 189 /* number of bytes used for write transaction in HW buffer 190 * - this will be used as the index to read from*/ 191 uint32_t buffer_used_write; 192 /* number of pending transactions (before GO) */ 193 uint32_t transaction_count; 194 uint32_t engine_keep_power_up_count; 195 uint32_t i2_setup_time_limit; 196 }; 197 198 struct i2c_hw_engine_dce110_create_arg { 199 uint32_t engine_id; 200 uint32_t reference_frequency; 201 uint32_t default_speed; 202 struct dc_context *ctx; 203 const struct dce110_i2c_hw_engine_registers *regs; 204 const struct dce110_i2c_hw_engine_shift *i2c_shift; 205 const struct dce110_i2c_hw_engine_mask *i2c_mask; 206 }; 207 208 struct i2c_engine *dal_i2c_hw_engine_dce110_create( 209 const struct i2c_hw_engine_dce110_create_arg *arg); 210 211 enum { 212 I2C_SETUP_TIME_LIMIT_DCE = 255, 213 I2C_SETUP_TIME_LIMIT_DCN = 3, 214 I2C_HW_BUFFER_SIZE = 538, 215 I2C_SEND_RESET_LENGTH_9 = 9, 216 I2C_SEND_RESET_LENGTH_10 = 10, 217 }; 218 #endif 219