1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev /*
29*b843c749SSergey Zigachev * Pre-requisites: headers required by header of this unit
30*b843c749SSergey Zigachev */
31*b843c749SSergey Zigachev #include "include/i2caux_interface.h"
32*b843c749SSergey Zigachev #include "../i2caux.h"
33*b843c749SSergey Zigachev
34*b843c749SSergey Zigachev /*
35*b843c749SSergey Zigachev * Header of this unit
36*b843c749SSergey Zigachev */
37*b843c749SSergey Zigachev
38*b843c749SSergey Zigachev #include "i2caux_dce80.h"
39*b843c749SSergey Zigachev
40*b843c749SSergey Zigachev /*
41*b843c749SSergey Zigachev * Post-requisites: headers required by this unit
42*b843c749SSergey Zigachev */
43*b843c749SSergey Zigachev
44*b843c749SSergey Zigachev #include "../engine.h"
45*b843c749SSergey Zigachev #include "../i2c_engine.h"
46*b843c749SSergey Zigachev #include "../i2c_sw_engine.h"
47*b843c749SSergey Zigachev #include "i2c_sw_engine_dce80.h"
48*b843c749SSergey Zigachev #include "../i2c_hw_engine.h"
49*b843c749SSergey Zigachev #include "i2c_hw_engine_dce80.h"
50*b843c749SSergey Zigachev #include "../i2c_generic_hw_engine.h"
51*b843c749SSergey Zigachev #include "../aux_engine.h"
52*b843c749SSergey Zigachev
53*b843c749SSergey Zigachev
54*b843c749SSergey Zigachev #include "../dce110/aux_engine_dce110.h"
55*b843c749SSergey Zigachev #include "../dce110/i2caux_dce110.h"
56*b843c749SSergey Zigachev
57*b843c749SSergey Zigachev #include "dce/dce_8_0_d.h"
58*b843c749SSergey Zigachev #include "dce/dce_8_0_sh_mask.h"
59*b843c749SSergey Zigachev
60*b843c749SSergey Zigachev
61*b843c749SSergey Zigachev /* set register offset */
62*b843c749SSergey Zigachev #define SR(reg_name)\
63*b843c749SSergey Zigachev .reg_name = mm ## reg_name
64*b843c749SSergey Zigachev
65*b843c749SSergey Zigachev /* set register offset with instance */
66*b843c749SSergey Zigachev #define SRI(reg_name, block, id)\
67*b843c749SSergey Zigachev .reg_name = mm ## block ## id ## _ ## reg_name
68*b843c749SSergey Zigachev
69*b843c749SSergey Zigachev #define aux_regs(id)\
70*b843c749SSergey Zigachev [id] = {\
71*b843c749SSergey Zigachev AUX_COMMON_REG_LIST(id), \
72*b843c749SSergey Zigachev .AUX_RESET_MASK = 0 \
73*b843c749SSergey Zigachev }
74*b843c749SSergey Zigachev
75*b843c749SSergey Zigachev static const struct dce110_aux_registers dce80_aux_regs[] = {
76*b843c749SSergey Zigachev aux_regs(0),
77*b843c749SSergey Zigachev aux_regs(1),
78*b843c749SSergey Zigachev aux_regs(2),
79*b843c749SSergey Zigachev aux_regs(3),
80*b843c749SSergey Zigachev aux_regs(4),
81*b843c749SSergey Zigachev aux_regs(5)
82*b843c749SSergey Zigachev };
83*b843c749SSergey Zigachev
84*b843c749SSergey Zigachev /*
85*b843c749SSergey Zigachev * This unit
86*b843c749SSergey Zigachev */
87*b843c749SSergey Zigachev
88*b843c749SSergey Zigachev #define FROM_I2C_AUX(ptr) \
89*b843c749SSergey Zigachev container_of((ptr), struct i2caux_dce80, base)
90*b843c749SSergey Zigachev
destruct(struct i2caux_dce80 * i2caux_dce80)91*b843c749SSergey Zigachev static void destruct(
92*b843c749SSergey Zigachev struct i2caux_dce80 *i2caux_dce80)
93*b843c749SSergey Zigachev {
94*b843c749SSergey Zigachev dal_i2caux_destruct(&i2caux_dce80->base);
95*b843c749SSergey Zigachev }
96*b843c749SSergey Zigachev
destroy(struct i2caux ** i2c_engine)97*b843c749SSergey Zigachev static void destroy(
98*b843c749SSergey Zigachev struct i2caux **i2c_engine)
99*b843c749SSergey Zigachev {
100*b843c749SSergey Zigachev struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(*i2c_engine);
101*b843c749SSergey Zigachev
102*b843c749SSergey Zigachev destruct(i2caux_dce80);
103*b843c749SSergey Zigachev
104*b843c749SSergey Zigachev kfree(i2caux_dce80);
105*b843c749SSergey Zigachev
106*b843c749SSergey Zigachev *i2c_engine = NULL;
107*b843c749SSergey Zigachev }
108*b843c749SSergey Zigachev
acquire_i2c_hw_engine(struct i2caux * i2caux,struct ddc * ddc)109*b843c749SSergey Zigachev static struct i2c_engine *acquire_i2c_hw_engine(
110*b843c749SSergey Zigachev struct i2caux *i2caux,
111*b843c749SSergey Zigachev struct ddc *ddc)
112*b843c749SSergey Zigachev {
113*b843c749SSergey Zigachev struct i2caux_dce80 *i2caux_dce80 = FROM_I2C_AUX(i2caux);
114*b843c749SSergey Zigachev
115*b843c749SSergey Zigachev struct i2c_engine *engine = NULL;
116*b843c749SSergey Zigachev bool non_generic;
117*b843c749SSergey Zigachev
118*b843c749SSergey Zigachev if (!ddc)
119*b843c749SSergey Zigachev return NULL;
120*b843c749SSergey Zigachev
121*b843c749SSergey Zigachev if (ddc->hw_info.hw_supported) {
122*b843c749SSergey Zigachev enum gpio_ddc_line line = dal_ddc_get_line(ddc);
123*b843c749SSergey Zigachev
124*b843c749SSergey Zigachev if (line < GPIO_DDC_LINE_COUNT) {
125*b843c749SSergey Zigachev non_generic = true;
126*b843c749SSergey Zigachev engine = i2caux->i2c_hw_engines[line];
127*b843c749SSergey Zigachev }
128*b843c749SSergey Zigachev }
129*b843c749SSergey Zigachev
130*b843c749SSergey Zigachev if (!engine) {
131*b843c749SSergey Zigachev non_generic = false;
132*b843c749SSergey Zigachev engine = i2caux->i2c_generic_hw_engine;
133*b843c749SSergey Zigachev }
134*b843c749SSergey Zigachev
135*b843c749SSergey Zigachev if (!engine)
136*b843c749SSergey Zigachev return NULL;
137*b843c749SSergey Zigachev
138*b843c749SSergey Zigachev if (non_generic) {
139*b843c749SSergey Zigachev if (!i2caux_dce80->i2c_hw_buffer_in_use &&
140*b843c749SSergey Zigachev engine->base.funcs->acquire(&engine->base, ddc)) {
141*b843c749SSergey Zigachev i2caux_dce80->i2c_hw_buffer_in_use = true;
142*b843c749SSergey Zigachev return engine;
143*b843c749SSergey Zigachev }
144*b843c749SSergey Zigachev } else {
145*b843c749SSergey Zigachev if (engine->base.funcs->acquire(&engine->base, ddc))
146*b843c749SSergey Zigachev return engine;
147*b843c749SSergey Zigachev }
148*b843c749SSergey Zigachev
149*b843c749SSergey Zigachev return NULL;
150*b843c749SSergey Zigachev }
151*b843c749SSergey Zigachev
release_engine(struct i2caux * i2caux,struct engine * engine)152*b843c749SSergey Zigachev static void release_engine(
153*b843c749SSergey Zigachev struct i2caux *i2caux,
154*b843c749SSergey Zigachev struct engine *engine)
155*b843c749SSergey Zigachev {
156*b843c749SSergey Zigachev if (engine->funcs->get_engine_type(engine) ==
157*b843c749SSergey Zigachev I2CAUX_ENGINE_TYPE_I2C_DDC_HW)
158*b843c749SSergey Zigachev FROM_I2C_AUX(i2caux)->i2c_hw_buffer_in_use = false;
159*b843c749SSergey Zigachev
160*b843c749SSergey Zigachev dal_i2caux_release_engine(i2caux, engine);
161*b843c749SSergey Zigachev }
162*b843c749SSergey Zigachev
163*b843c749SSergey Zigachev static const enum gpio_ddc_line hw_ddc_lines[] = {
164*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC1,
165*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC2,
166*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC3,
167*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC4,
168*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC5,
169*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC6,
170*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC_VGA
171*b843c749SSergey Zigachev };
172*b843c749SSergey Zigachev
173*b843c749SSergey Zigachev static const enum gpio_ddc_line hw_aux_lines[] = {
174*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC1,
175*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC2,
176*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC3,
177*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC4,
178*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC5,
179*b843c749SSergey Zigachev GPIO_DDC_LINE_DDC6
180*b843c749SSergey Zigachev };
181*b843c749SSergey Zigachev
182*b843c749SSergey Zigachev static const struct i2caux_funcs i2caux_funcs = {
183*b843c749SSergey Zigachev .destroy = destroy,
184*b843c749SSergey Zigachev .acquire_i2c_hw_engine = acquire_i2c_hw_engine,
185*b843c749SSergey Zigachev .release_engine = release_engine,
186*b843c749SSergey Zigachev .acquire_i2c_sw_engine = dal_i2caux_acquire_i2c_sw_engine,
187*b843c749SSergey Zigachev .acquire_aux_engine = dal_i2caux_acquire_aux_engine,
188*b843c749SSergey Zigachev };
189*b843c749SSergey Zigachev
construct(struct i2caux_dce80 * i2caux_dce80,struct dc_context * ctx)190*b843c749SSergey Zigachev static void construct(
191*b843c749SSergey Zigachev struct i2caux_dce80 *i2caux_dce80,
192*b843c749SSergey Zigachev struct dc_context *ctx)
193*b843c749SSergey Zigachev {
194*b843c749SSergey Zigachev /* Entire family have I2C engine reference clock frequency
195*b843c749SSergey Zigachev * changed from XTALIN (27) to XTALIN/2 (13.5) */
196*b843c749SSergey Zigachev
197*b843c749SSergey Zigachev struct i2caux *base = &i2caux_dce80->base;
198*b843c749SSergey Zigachev
199*b843c749SSergey Zigachev uint32_t reference_frequency =
200*b843c749SSergey Zigachev dal_i2caux_get_reference_clock(ctx->dc_bios) >> 1;
201*b843c749SSergey Zigachev
202*b843c749SSergey Zigachev /*bool use_i2c_sw_engine = dal_adapter_service_is_feature_supported(as,
203*b843c749SSergey Zigachev FEATURE_RESTORE_USAGE_I2C_SW_ENGINE);*/
204*b843c749SSergey Zigachev
205*b843c749SSergey Zigachev /* Use SWI2C for dce8 currently, sicne we have bug with hwi2c */
206*b843c749SSergey Zigachev bool use_i2c_sw_engine = true;
207*b843c749SSergey Zigachev
208*b843c749SSergey Zigachev uint32_t i;
209*b843c749SSergey Zigachev
210*b843c749SSergey Zigachev dal_i2caux_construct(base, ctx);
211*b843c749SSergey Zigachev
212*b843c749SSergey Zigachev i2caux_dce80->base.funcs = &i2caux_funcs;
213*b843c749SSergey Zigachev i2caux_dce80->i2c_hw_buffer_in_use = false;
214*b843c749SSergey Zigachev
215*b843c749SSergey Zigachev /* Create I2C HW engines (HW + SW pairs)
216*b843c749SSergey Zigachev * for all lines which has assisted HW DDC
217*b843c749SSergey Zigachev * 'i' (loop counter) used as DDC/AUX engine_id */
218*b843c749SSergey Zigachev
219*b843c749SSergey Zigachev i = 0;
220*b843c749SSergey Zigachev
221*b843c749SSergey Zigachev do {
222*b843c749SSergey Zigachev enum gpio_ddc_line line_id = hw_ddc_lines[i];
223*b843c749SSergey Zigachev
224*b843c749SSergey Zigachev struct i2c_hw_engine_dce80_create_arg hw_arg;
225*b843c749SSergey Zigachev
226*b843c749SSergey Zigachev if (use_i2c_sw_engine) {
227*b843c749SSergey Zigachev struct i2c_sw_engine_dce80_create_arg sw_arg;
228*b843c749SSergey Zigachev
229*b843c749SSergey Zigachev sw_arg.engine_id = i;
230*b843c749SSergey Zigachev sw_arg.default_speed = base->default_i2c_sw_speed;
231*b843c749SSergey Zigachev sw_arg.ctx = ctx;
232*b843c749SSergey Zigachev base->i2c_sw_engines[line_id] =
233*b843c749SSergey Zigachev dal_i2c_sw_engine_dce80_create(&sw_arg);
234*b843c749SSergey Zigachev }
235*b843c749SSergey Zigachev
236*b843c749SSergey Zigachev hw_arg.engine_id = i;
237*b843c749SSergey Zigachev hw_arg.reference_frequency = reference_frequency;
238*b843c749SSergey Zigachev hw_arg.default_speed = base->default_i2c_hw_speed;
239*b843c749SSergey Zigachev hw_arg.ctx = ctx;
240*b843c749SSergey Zigachev
241*b843c749SSergey Zigachev base->i2c_hw_engines[line_id] =
242*b843c749SSergey Zigachev dal_i2c_hw_engine_dce80_create(&hw_arg);
243*b843c749SSergey Zigachev
244*b843c749SSergey Zigachev ++i;
245*b843c749SSergey Zigachev } while (i < ARRAY_SIZE(hw_ddc_lines));
246*b843c749SSergey Zigachev
247*b843c749SSergey Zigachev /* Create AUX engines for all lines which has assisted HW AUX
248*b843c749SSergey Zigachev * 'i' (loop counter) used as DDC/AUX engine_id */
249*b843c749SSergey Zigachev
250*b843c749SSergey Zigachev i = 0;
251*b843c749SSergey Zigachev
252*b843c749SSergey Zigachev do {
253*b843c749SSergey Zigachev enum gpio_ddc_line line_id = hw_aux_lines[i];
254*b843c749SSergey Zigachev
255*b843c749SSergey Zigachev struct aux_engine_dce110_init_data arg;
256*b843c749SSergey Zigachev
257*b843c749SSergey Zigachev arg.engine_id = i;
258*b843c749SSergey Zigachev arg.timeout_period = base->aux_timeout_period;
259*b843c749SSergey Zigachev arg.ctx = ctx;
260*b843c749SSergey Zigachev arg.regs = &dce80_aux_regs[i];
261*b843c749SSergey Zigachev
262*b843c749SSergey Zigachev base->aux_engines[line_id] =
263*b843c749SSergey Zigachev dal_aux_engine_dce110_create(&arg);
264*b843c749SSergey Zigachev
265*b843c749SSergey Zigachev ++i;
266*b843c749SSergey Zigachev } while (i < ARRAY_SIZE(hw_aux_lines));
267*b843c749SSergey Zigachev
268*b843c749SSergey Zigachev /* TODO Generic I2C SW and HW */
269*b843c749SSergey Zigachev }
270*b843c749SSergey Zigachev
dal_i2caux_dce80_create(struct dc_context * ctx)271*b843c749SSergey Zigachev struct i2caux *dal_i2caux_dce80_create(
272*b843c749SSergey Zigachev struct dc_context *ctx)
273*b843c749SSergey Zigachev {
274*b843c749SSergey Zigachev struct i2caux_dce80 *i2caux_dce80 =
275*b843c749SSergey Zigachev kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL);
276*b843c749SSergey Zigachev
277*b843c749SSergey Zigachev if (!i2caux_dce80) {
278*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
279*b843c749SSergey Zigachev return NULL;
280*b843c749SSergey Zigachev }
281*b843c749SSergey Zigachev
282*b843c749SSergey Zigachev construct(i2caux_dce80, ctx);
283*b843c749SSergey Zigachev return &i2caux_dce80->base;
284*b843c749SSergey Zigachev }
285