1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev *
4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev *
11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev *
14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev *
22*b843c749SSergey Zigachev * Authors: AMD
23*b843c749SSergey Zigachev *
24*b843c749SSergey Zigachev */
25*b843c749SSergey Zigachev
26*b843c749SSergey Zigachev #include "dm_services.h"
27*b843c749SSergey Zigachev
28*b843c749SSergey Zigachev /*
29*b843c749SSergey Zigachev * Pre-requisites: headers required by header of this unit
30*b843c749SSergey Zigachev */
31*b843c749SSergey Zigachev #include "include/i2caux_interface.h"
32*b843c749SSergey Zigachev #include "engine.h"
33*b843c749SSergey Zigachev #include "i2c_engine.h"
34*b843c749SSergey Zigachev
35*b843c749SSergey Zigachev /*
36*b843c749SSergey Zigachev * Header of this unit
37*b843c749SSergey Zigachev */
38*b843c749SSergey Zigachev
39*b843c749SSergey Zigachev #include "i2c_sw_engine.h"
40*b843c749SSergey Zigachev
41*b843c749SSergey Zigachev /*
42*b843c749SSergey Zigachev * Post-requisites: headers required by this unit
43*b843c749SSergey Zigachev */
44*b843c749SSergey Zigachev
45*b843c749SSergey Zigachev /*
46*b843c749SSergey Zigachev * This unit
47*b843c749SSergey Zigachev */
48*b843c749SSergey Zigachev
49*b843c749SSergey Zigachev #define SCL false
50*b843c749SSergey Zigachev #define SDA true
51*b843c749SSergey Zigachev
read_bit_from_ddc(struct ddc * ddc,bool data_nor_clock)52*b843c749SSergey Zigachev static inline bool read_bit_from_ddc(
53*b843c749SSergey Zigachev struct ddc *ddc,
54*b843c749SSergey Zigachev bool data_nor_clock)
55*b843c749SSergey Zigachev {
56*b843c749SSergey Zigachev uint32_t value = 0;
57*b843c749SSergey Zigachev
58*b843c749SSergey Zigachev if (data_nor_clock)
59*b843c749SSergey Zigachev dal_gpio_get_value(ddc->pin_data, &value);
60*b843c749SSergey Zigachev else
61*b843c749SSergey Zigachev dal_gpio_get_value(ddc->pin_clock, &value);
62*b843c749SSergey Zigachev
63*b843c749SSergey Zigachev return (value != 0);
64*b843c749SSergey Zigachev }
65*b843c749SSergey Zigachev
write_bit_to_ddc(struct ddc * ddc,bool data_nor_clock,bool bit)66*b843c749SSergey Zigachev static inline void write_bit_to_ddc(
67*b843c749SSergey Zigachev struct ddc *ddc,
68*b843c749SSergey Zigachev bool data_nor_clock,
69*b843c749SSergey Zigachev bool bit)
70*b843c749SSergey Zigachev {
71*b843c749SSergey Zigachev uint32_t value = bit ? 1 : 0;
72*b843c749SSergey Zigachev
73*b843c749SSergey Zigachev if (data_nor_clock)
74*b843c749SSergey Zigachev dal_gpio_set_value(ddc->pin_data, value);
75*b843c749SSergey Zigachev else
76*b843c749SSergey Zigachev dal_gpio_set_value(ddc->pin_clock, value);
77*b843c749SSergey Zigachev }
78*b843c749SSergey Zigachev
wait_for_scl_high(struct dc_context * ctx,struct ddc * ddc,uint16_t clock_delay_div_4)79*b843c749SSergey Zigachev static bool wait_for_scl_high(
80*b843c749SSergey Zigachev struct dc_context *ctx,
81*b843c749SSergey Zigachev struct ddc *ddc,
82*b843c749SSergey Zigachev uint16_t clock_delay_div_4)
83*b843c749SSergey Zigachev {
84*b843c749SSergey Zigachev uint32_t scl_retry = 0;
85*b843c749SSergey Zigachev uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
86*b843c749SSergey Zigachev
87*b843c749SSergey Zigachev udelay(clock_delay_div_4);
88*b843c749SSergey Zigachev
89*b843c749SSergey Zigachev /* 3 milliseconds delay
90*b843c749SSergey Zigachev * to wake up some displays from "low power" state.
91*b843c749SSergey Zigachev */
92*b843c749SSergey Zigachev
93*b843c749SSergey Zigachev do {
94*b843c749SSergey Zigachev if (read_bit_from_ddc(ddc, SCL))
95*b843c749SSergey Zigachev return true;
96*b843c749SSergey Zigachev
97*b843c749SSergey Zigachev udelay(clock_delay_div_4);
98*b843c749SSergey Zigachev
99*b843c749SSergey Zigachev ++scl_retry;
100*b843c749SSergey Zigachev } while (scl_retry <= scl_retry_max);
101*b843c749SSergey Zigachev
102*b843c749SSergey Zigachev return false;
103*b843c749SSergey Zigachev }
104*b843c749SSergey Zigachev
start_sync(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4)105*b843c749SSergey Zigachev static bool start_sync(
106*b843c749SSergey Zigachev struct dc_context *ctx,
107*b843c749SSergey Zigachev struct ddc *ddc_handle,
108*b843c749SSergey Zigachev uint16_t clock_delay_div_4)
109*b843c749SSergey Zigachev {
110*b843c749SSergey Zigachev uint32_t retry = 0;
111*b843c749SSergey Zigachev
112*b843c749SSergey Zigachev /* The I2C communications start signal is:
113*b843c749SSergey Zigachev * the SDA going low from high, while the SCL is high. */
114*b843c749SSergey Zigachev
115*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
116*b843c749SSergey Zigachev
117*b843c749SSergey Zigachev udelay(clock_delay_div_4);
118*b843c749SSergey Zigachev
119*b843c749SSergey Zigachev do {
120*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, true);
121*b843c749SSergey Zigachev
122*b843c749SSergey Zigachev if (!read_bit_from_ddc(ddc_handle, SDA)) {
123*b843c749SSergey Zigachev ++retry;
124*b843c749SSergey Zigachev continue;
125*b843c749SSergey Zigachev }
126*b843c749SSergey Zigachev
127*b843c749SSergey Zigachev udelay(clock_delay_div_4);
128*b843c749SSergey Zigachev
129*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
130*b843c749SSergey Zigachev
131*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
132*b843c749SSergey Zigachev break;
133*b843c749SSergey Zigachev
134*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, false);
135*b843c749SSergey Zigachev
136*b843c749SSergey Zigachev udelay(clock_delay_div_4);
137*b843c749SSergey Zigachev
138*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
139*b843c749SSergey Zigachev
140*b843c749SSergey Zigachev udelay(clock_delay_div_4);
141*b843c749SSergey Zigachev
142*b843c749SSergey Zigachev return true;
143*b843c749SSergey Zigachev } while (retry <= I2C_SW_RETRIES);
144*b843c749SSergey Zigachev
145*b843c749SSergey Zigachev return false;
146*b843c749SSergey Zigachev }
147*b843c749SSergey Zigachev
stop_sync(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4)148*b843c749SSergey Zigachev static bool stop_sync(
149*b843c749SSergey Zigachev struct dc_context *ctx,
150*b843c749SSergey Zigachev struct ddc *ddc_handle,
151*b843c749SSergey Zigachev uint16_t clock_delay_div_4)
152*b843c749SSergey Zigachev {
153*b843c749SSergey Zigachev uint32_t retry = 0;
154*b843c749SSergey Zigachev
155*b843c749SSergey Zigachev /* The I2C communications stop signal is:
156*b843c749SSergey Zigachev * the SDA going high from low, while the SCL is high. */
157*b843c749SSergey Zigachev
158*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
159*b843c749SSergey Zigachev
160*b843c749SSergey Zigachev udelay(clock_delay_div_4);
161*b843c749SSergey Zigachev
162*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, false);
163*b843c749SSergey Zigachev
164*b843c749SSergey Zigachev udelay(clock_delay_div_4);
165*b843c749SSergey Zigachev
166*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
167*b843c749SSergey Zigachev
168*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
169*b843c749SSergey Zigachev return false;
170*b843c749SSergey Zigachev
171*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, true);
172*b843c749SSergey Zigachev
173*b843c749SSergey Zigachev do {
174*b843c749SSergey Zigachev udelay(clock_delay_div_4);
175*b843c749SSergey Zigachev
176*b843c749SSergey Zigachev if (read_bit_from_ddc(ddc_handle, SDA))
177*b843c749SSergey Zigachev return true;
178*b843c749SSergey Zigachev
179*b843c749SSergey Zigachev ++retry;
180*b843c749SSergey Zigachev } while (retry <= 2);
181*b843c749SSergey Zigachev
182*b843c749SSergey Zigachev return false;
183*b843c749SSergey Zigachev }
184*b843c749SSergey Zigachev
write_byte(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4,uint8_t byte)185*b843c749SSergey Zigachev static bool write_byte(
186*b843c749SSergey Zigachev struct dc_context *ctx,
187*b843c749SSergey Zigachev struct ddc *ddc_handle,
188*b843c749SSergey Zigachev uint16_t clock_delay_div_4,
189*b843c749SSergey Zigachev uint8_t byte)
190*b843c749SSergey Zigachev {
191*b843c749SSergey Zigachev int32_t shift = 7;
192*b843c749SSergey Zigachev bool ack;
193*b843c749SSergey Zigachev
194*b843c749SSergey Zigachev /* bits are transmitted serially, starting from MSB */
195*b843c749SSergey Zigachev
196*b843c749SSergey Zigachev do {
197*b843c749SSergey Zigachev udelay(clock_delay_div_4);
198*b843c749SSergey Zigachev
199*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
200*b843c749SSergey Zigachev
201*b843c749SSergey Zigachev udelay(clock_delay_div_4);
202*b843c749SSergey Zigachev
203*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
204*b843c749SSergey Zigachev
205*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
206*b843c749SSergey Zigachev return false;
207*b843c749SSergey Zigachev
208*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
209*b843c749SSergey Zigachev
210*b843c749SSergey Zigachev --shift;
211*b843c749SSergey Zigachev } while (shift >= 0);
212*b843c749SSergey Zigachev
213*b843c749SSergey Zigachev /* The display sends ACK by preventing the SDA from going high
214*b843c749SSergey Zigachev * after the SCL pulse we use to send our last data bit.
215*b843c749SSergey Zigachev * If the SDA goes high after that bit, it's a NACK */
216*b843c749SSergey Zigachev
217*b843c749SSergey Zigachev udelay(clock_delay_div_4);
218*b843c749SSergey Zigachev
219*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, true);
220*b843c749SSergey Zigachev
221*b843c749SSergey Zigachev udelay(clock_delay_div_4);
222*b843c749SSergey Zigachev
223*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
224*b843c749SSergey Zigachev
225*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
226*b843c749SSergey Zigachev return false;
227*b843c749SSergey Zigachev
228*b843c749SSergey Zigachev /* read ACK bit */
229*b843c749SSergey Zigachev
230*b843c749SSergey Zigachev ack = !read_bit_from_ddc(ddc_handle, SDA);
231*b843c749SSergey Zigachev
232*b843c749SSergey Zigachev udelay(clock_delay_div_4 << 1);
233*b843c749SSergey Zigachev
234*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
235*b843c749SSergey Zigachev
236*b843c749SSergey Zigachev udelay(clock_delay_div_4 << 1);
237*b843c749SSergey Zigachev
238*b843c749SSergey Zigachev return ack;
239*b843c749SSergey Zigachev }
240*b843c749SSergey Zigachev
read_byte(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4,uint8_t * byte,bool more)241*b843c749SSergey Zigachev static bool read_byte(
242*b843c749SSergey Zigachev struct dc_context *ctx,
243*b843c749SSergey Zigachev struct ddc *ddc_handle,
244*b843c749SSergey Zigachev uint16_t clock_delay_div_4,
245*b843c749SSergey Zigachev uint8_t *byte,
246*b843c749SSergey Zigachev bool more)
247*b843c749SSergey Zigachev {
248*b843c749SSergey Zigachev int32_t shift = 7;
249*b843c749SSergey Zigachev
250*b843c749SSergey Zigachev uint8_t data = 0;
251*b843c749SSergey Zigachev
252*b843c749SSergey Zigachev /* The data bits are read from MSB to LSB;
253*b843c749SSergey Zigachev * bit is read while SCL is high */
254*b843c749SSergey Zigachev
255*b843c749SSergey Zigachev do {
256*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
257*b843c749SSergey Zigachev
258*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
259*b843c749SSergey Zigachev return false;
260*b843c749SSergey Zigachev
261*b843c749SSergey Zigachev if (read_bit_from_ddc(ddc_handle, SDA))
262*b843c749SSergey Zigachev data |= (1 << shift);
263*b843c749SSergey Zigachev
264*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
265*b843c749SSergey Zigachev
266*b843c749SSergey Zigachev udelay(clock_delay_div_4 << 1);
267*b843c749SSergey Zigachev
268*b843c749SSergey Zigachev --shift;
269*b843c749SSergey Zigachev } while (shift >= 0);
270*b843c749SSergey Zigachev
271*b843c749SSergey Zigachev /* read only whole byte */
272*b843c749SSergey Zigachev
273*b843c749SSergey Zigachev *byte = data;
274*b843c749SSergey Zigachev
275*b843c749SSergey Zigachev udelay(clock_delay_div_4);
276*b843c749SSergey Zigachev
277*b843c749SSergey Zigachev /* send the acknowledge bit:
278*b843c749SSergey Zigachev * SDA low means ACK, SDA high means NACK */
279*b843c749SSergey Zigachev
280*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, !more);
281*b843c749SSergey Zigachev
282*b843c749SSergey Zigachev udelay(clock_delay_div_4);
283*b843c749SSergey Zigachev
284*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, true);
285*b843c749SSergey Zigachev
286*b843c749SSergey Zigachev if (!wait_for_scl_high(ctx, ddc_handle, clock_delay_div_4))
287*b843c749SSergey Zigachev return false;
288*b843c749SSergey Zigachev
289*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SCL, false);
290*b843c749SSergey Zigachev
291*b843c749SSergey Zigachev udelay(clock_delay_div_4);
292*b843c749SSergey Zigachev
293*b843c749SSergey Zigachev write_bit_to_ddc(ddc_handle, SDA, true);
294*b843c749SSergey Zigachev
295*b843c749SSergey Zigachev udelay(clock_delay_div_4);
296*b843c749SSergey Zigachev
297*b843c749SSergey Zigachev return true;
298*b843c749SSergey Zigachev }
299*b843c749SSergey Zigachev
i2c_write(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4,uint8_t address,uint32_t length,const uint8_t * data)300*b843c749SSergey Zigachev static bool i2c_write(
301*b843c749SSergey Zigachev struct dc_context *ctx,
302*b843c749SSergey Zigachev struct ddc *ddc_handle,
303*b843c749SSergey Zigachev uint16_t clock_delay_div_4,
304*b843c749SSergey Zigachev uint8_t address,
305*b843c749SSergey Zigachev uint32_t length,
306*b843c749SSergey Zigachev const uint8_t *data)
307*b843c749SSergey Zigachev {
308*b843c749SSergey Zigachev uint32_t i = 0;
309*b843c749SSergey Zigachev
310*b843c749SSergey Zigachev if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
311*b843c749SSergey Zigachev return false;
312*b843c749SSergey Zigachev
313*b843c749SSergey Zigachev while (i < length) {
314*b843c749SSergey Zigachev if (!write_byte(ctx, ddc_handle, clock_delay_div_4, data[i]))
315*b843c749SSergey Zigachev return false;
316*b843c749SSergey Zigachev ++i;
317*b843c749SSergey Zigachev }
318*b843c749SSergey Zigachev
319*b843c749SSergey Zigachev return true;
320*b843c749SSergey Zigachev }
321*b843c749SSergey Zigachev
i2c_read(struct dc_context * ctx,struct ddc * ddc_handle,uint16_t clock_delay_div_4,uint8_t address,uint32_t length,uint8_t * data)322*b843c749SSergey Zigachev static bool i2c_read(
323*b843c749SSergey Zigachev struct dc_context *ctx,
324*b843c749SSergey Zigachev struct ddc *ddc_handle,
325*b843c749SSergey Zigachev uint16_t clock_delay_div_4,
326*b843c749SSergey Zigachev uint8_t address,
327*b843c749SSergey Zigachev uint32_t length,
328*b843c749SSergey Zigachev uint8_t *data)
329*b843c749SSergey Zigachev {
330*b843c749SSergey Zigachev uint32_t i = 0;
331*b843c749SSergey Zigachev
332*b843c749SSergey Zigachev if (!write_byte(ctx, ddc_handle, clock_delay_div_4, address))
333*b843c749SSergey Zigachev return false;
334*b843c749SSergey Zigachev
335*b843c749SSergey Zigachev while (i < length) {
336*b843c749SSergey Zigachev if (!read_byte(ctx, ddc_handle, clock_delay_div_4, data + i,
337*b843c749SSergey Zigachev i < length - 1))
338*b843c749SSergey Zigachev return false;
339*b843c749SSergey Zigachev ++i;
340*b843c749SSergey Zigachev }
341*b843c749SSergey Zigachev
342*b843c749SSergey Zigachev return true;
343*b843c749SSergey Zigachev }
344*b843c749SSergey Zigachev
345*b843c749SSergey Zigachev /*
346*b843c749SSergey Zigachev * @brief
347*b843c749SSergey Zigachev * Cast 'struct i2c_engine *'
348*b843c749SSergey Zigachev * to 'struct i2c_sw_engine *'
349*b843c749SSergey Zigachev */
350*b843c749SSergey Zigachev #define FROM_I2C_ENGINE(ptr) \
351*b843c749SSergey Zigachev container_of((ptr), struct i2c_sw_engine, base)
352*b843c749SSergey Zigachev
353*b843c749SSergey Zigachev /*
354*b843c749SSergey Zigachev * @brief
355*b843c749SSergey Zigachev * Cast 'struct engine *'
356*b843c749SSergey Zigachev * to 'struct i2c_sw_engine *'
357*b843c749SSergey Zigachev */
358*b843c749SSergey Zigachev #define FROM_ENGINE(ptr) \
359*b843c749SSergey Zigachev FROM_I2C_ENGINE(container_of((ptr), struct i2c_engine, base))
360*b843c749SSergey Zigachev
dal_i2c_sw_engine_get_engine_type(const struct engine * engine)361*b843c749SSergey Zigachev enum i2caux_engine_type dal_i2c_sw_engine_get_engine_type(
362*b843c749SSergey Zigachev const struct engine *engine)
363*b843c749SSergey Zigachev {
364*b843c749SSergey Zigachev return I2CAUX_ENGINE_TYPE_I2C_SW;
365*b843c749SSergey Zigachev }
366*b843c749SSergey Zigachev
dal_i2c_sw_engine_submit_request(struct engine * engine,struct i2caux_transaction_request * i2caux_request,bool middle_of_transaction)367*b843c749SSergey Zigachev bool dal_i2c_sw_engine_submit_request(
368*b843c749SSergey Zigachev struct engine *engine,
369*b843c749SSergey Zigachev struct i2caux_transaction_request *i2caux_request,
370*b843c749SSergey Zigachev bool middle_of_transaction)
371*b843c749SSergey Zigachev {
372*b843c749SSergey Zigachev struct i2c_sw_engine *sw_engine = FROM_ENGINE(engine);
373*b843c749SSergey Zigachev
374*b843c749SSergey Zigachev struct i2c_engine *base = &sw_engine->base;
375*b843c749SSergey Zigachev
376*b843c749SSergey Zigachev struct i2c_request_transaction_data request;
377*b843c749SSergey Zigachev bool operation_succeeded = false;
378*b843c749SSergey Zigachev
379*b843c749SSergey Zigachev if (i2caux_request->operation == I2CAUX_TRANSACTION_READ)
380*b843c749SSergey Zigachev request.action = middle_of_transaction ?
381*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT :
382*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_READ;
383*b843c749SSergey Zigachev else if (i2caux_request->operation == I2CAUX_TRANSACTION_WRITE)
384*b843c749SSergey Zigachev request.action = middle_of_transaction ?
385*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT :
386*b843c749SSergey Zigachev I2CAUX_TRANSACTION_ACTION_I2C_WRITE;
387*b843c749SSergey Zigachev else {
388*b843c749SSergey Zigachev i2caux_request->status =
389*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION;
390*b843c749SSergey Zigachev /* in DAL2, there was no "return false" */
391*b843c749SSergey Zigachev return false;
392*b843c749SSergey Zigachev }
393*b843c749SSergey Zigachev
394*b843c749SSergey Zigachev request.address = (uint8_t)i2caux_request->payload.address;
395*b843c749SSergey Zigachev request.length = i2caux_request->payload.length;
396*b843c749SSergey Zigachev request.data = i2caux_request->payload.data;
397*b843c749SSergey Zigachev
398*b843c749SSergey Zigachev base->funcs->submit_channel_request(base, &request);
399*b843c749SSergey Zigachev
400*b843c749SSergey Zigachev if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
401*b843c749SSergey Zigachev (request.status == I2C_CHANNEL_OPERATION_FAILED))
402*b843c749SSergey Zigachev i2caux_request->status =
403*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY;
404*b843c749SSergey Zigachev else {
405*b843c749SSergey Zigachev enum i2c_channel_operation_result operation_result;
406*b843c749SSergey Zigachev
407*b843c749SSergey Zigachev do {
408*b843c749SSergey Zigachev operation_result =
409*b843c749SSergey Zigachev base->funcs->get_channel_status(base, NULL);
410*b843c749SSergey Zigachev
411*b843c749SSergey Zigachev switch (operation_result) {
412*b843c749SSergey Zigachev case I2C_CHANNEL_OPERATION_SUCCEEDED:
413*b843c749SSergey Zigachev i2caux_request->status =
414*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_SUCCEEDED;
415*b843c749SSergey Zigachev operation_succeeded = true;
416*b843c749SSergey Zigachev break;
417*b843c749SSergey Zigachev case I2C_CHANNEL_OPERATION_NO_RESPONSE:
418*b843c749SSergey Zigachev i2caux_request->status =
419*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_NACK;
420*b843c749SSergey Zigachev break;
421*b843c749SSergey Zigachev case I2C_CHANNEL_OPERATION_TIMEOUT:
422*b843c749SSergey Zigachev i2caux_request->status =
423*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT;
424*b843c749SSergey Zigachev break;
425*b843c749SSergey Zigachev case I2C_CHANNEL_OPERATION_FAILED:
426*b843c749SSergey Zigachev i2caux_request->status =
427*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE;
428*b843c749SSergey Zigachev break;
429*b843c749SSergey Zigachev default:
430*b843c749SSergey Zigachev i2caux_request->status =
431*b843c749SSergey Zigachev I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION;
432*b843c749SSergey Zigachev break;
433*b843c749SSergey Zigachev }
434*b843c749SSergey Zigachev } while (operation_result == I2C_CHANNEL_OPERATION_ENGINE_BUSY);
435*b843c749SSergey Zigachev }
436*b843c749SSergey Zigachev
437*b843c749SSergey Zigachev return operation_succeeded;
438*b843c749SSergey Zigachev }
439*b843c749SSergey Zigachev
dal_i2c_sw_engine_get_speed(const struct i2c_engine * engine)440*b843c749SSergey Zigachev uint32_t dal_i2c_sw_engine_get_speed(
441*b843c749SSergey Zigachev const struct i2c_engine *engine)
442*b843c749SSergey Zigachev {
443*b843c749SSergey Zigachev return FROM_I2C_ENGINE(engine)->speed;
444*b843c749SSergey Zigachev }
445*b843c749SSergey Zigachev
dal_i2c_sw_engine_set_speed(struct i2c_engine * engine,uint32_t speed)446*b843c749SSergey Zigachev void dal_i2c_sw_engine_set_speed(
447*b843c749SSergey Zigachev struct i2c_engine *engine,
448*b843c749SSergey Zigachev uint32_t speed)
449*b843c749SSergey Zigachev {
450*b843c749SSergey Zigachev struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
451*b843c749SSergey Zigachev
452*b843c749SSergey Zigachev ASSERT(speed);
453*b843c749SSergey Zigachev
454*b843c749SSergey Zigachev sw_engine->speed = speed ? speed : I2CAUX_DEFAULT_I2C_SW_SPEED;
455*b843c749SSergey Zigachev
456*b843c749SSergey Zigachev sw_engine->clock_delay = 1000 / sw_engine->speed;
457*b843c749SSergey Zigachev
458*b843c749SSergey Zigachev if (sw_engine->clock_delay < 12)
459*b843c749SSergey Zigachev sw_engine->clock_delay = 12;
460*b843c749SSergey Zigachev }
461*b843c749SSergey Zigachev
dal_i2caux_i2c_sw_engine_acquire_engine(struct i2c_engine * engine,struct ddc * ddc)462*b843c749SSergey Zigachev bool dal_i2caux_i2c_sw_engine_acquire_engine(
463*b843c749SSergey Zigachev struct i2c_engine *engine,
464*b843c749SSergey Zigachev struct ddc *ddc)
465*b843c749SSergey Zigachev {
466*b843c749SSergey Zigachev enum gpio_result result;
467*b843c749SSergey Zigachev
468*b843c749SSergey Zigachev result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
469*b843c749SSergey Zigachev GPIO_DDC_CONFIG_TYPE_MODE_I2C);
470*b843c749SSergey Zigachev
471*b843c749SSergey Zigachev if (result != GPIO_RESULT_OK)
472*b843c749SSergey Zigachev return false;
473*b843c749SSergey Zigachev
474*b843c749SSergey Zigachev engine->base.ddc = ddc;
475*b843c749SSergey Zigachev
476*b843c749SSergey Zigachev return true;
477*b843c749SSergey Zigachev }
478*b843c749SSergey Zigachev
dal_i2c_sw_engine_submit_channel_request(struct i2c_engine * engine,struct i2c_request_transaction_data * req)479*b843c749SSergey Zigachev void dal_i2c_sw_engine_submit_channel_request(
480*b843c749SSergey Zigachev struct i2c_engine *engine,
481*b843c749SSergey Zigachev struct i2c_request_transaction_data *req)
482*b843c749SSergey Zigachev {
483*b843c749SSergey Zigachev struct i2c_sw_engine *sw_engine = FROM_I2C_ENGINE(engine);
484*b843c749SSergey Zigachev
485*b843c749SSergey Zigachev struct ddc *ddc = engine->base.ddc;
486*b843c749SSergey Zigachev uint16_t clock_delay_div_4 = sw_engine->clock_delay >> 2;
487*b843c749SSergey Zigachev
488*b843c749SSergey Zigachev /* send sync (start / repeated start) */
489*b843c749SSergey Zigachev
490*b843c749SSergey Zigachev bool result = start_sync(engine->base.ctx, ddc, clock_delay_div_4);
491*b843c749SSergey Zigachev
492*b843c749SSergey Zigachev /* process payload */
493*b843c749SSergey Zigachev
494*b843c749SSergey Zigachev if (result) {
495*b843c749SSergey Zigachev switch (req->action) {
496*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_ACTION_I2C_WRITE:
497*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT:
498*b843c749SSergey Zigachev result = i2c_write(engine->base.ctx, ddc, clock_delay_div_4,
499*b843c749SSergey Zigachev req->address, req->length, req->data);
500*b843c749SSergey Zigachev break;
501*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_ACTION_I2C_READ:
502*b843c749SSergey Zigachev case I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT:
503*b843c749SSergey Zigachev result = i2c_read(engine->base.ctx, ddc, clock_delay_div_4,
504*b843c749SSergey Zigachev req->address, req->length, req->data);
505*b843c749SSergey Zigachev break;
506*b843c749SSergey Zigachev default:
507*b843c749SSergey Zigachev result = false;
508*b843c749SSergey Zigachev break;
509*b843c749SSergey Zigachev }
510*b843c749SSergey Zigachev }
511*b843c749SSergey Zigachev
512*b843c749SSergey Zigachev /* send stop if not 'mot' or operation failed */
513*b843c749SSergey Zigachev
514*b843c749SSergey Zigachev if (!result ||
515*b843c749SSergey Zigachev (req->action == I2CAUX_TRANSACTION_ACTION_I2C_WRITE) ||
516*b843c749SSergey Zigachev (req->action == I2CAUX_TRANSACTION_ACTION_I2C_READ))
517*b843c749SSergey Zigachev if (!stop_sync(engine->base.ctx, ddc, clock_delay_div_4))
518*b843c749SSergey Zigachev result = false;
519*b843c749SSergey Zigachev
520*b843c749SSergey Zigachev req->status = result ?
521*b843c749SSergey Zigachev I2C_CHANNEL_OPERATION_SUCCEEDED :
522*b843c749SSergey Zigachev I2C_CHANNEL_OPERATION_FAILED;
523*b843c749SSergey Zigachev }
524*b843c749SSergey Zigachev
dal_i2c_sw_engine_get_channel_status(struct i2c_engine * engine,uint8_t * returned_bytes)525*b843c749SSergey Zigachev enum i2c_channel_operation_result dal_i2c_sw_engine_get_channel_status(
526*b843c749SSergey Zigachev struct i2c_engine *engine,
527*b843c749SSergey Zigachev uint8_t *returned_bytes)
528*b843c749SSergey Zigachev {
529*b843c749SSergey Zigachev /* No arbitration with VBIOS is performed since DCE 6.0 */
530*b843c749SSergey Zigachev return I2C_CHANNEL_OPERATION_SUCCEEDED;
531*b843c749SSergey Zigachev }
532*b843c749SSergey Zigachev
dal_i2c_sw_engine_destruct(struct i2c_sw_engine * engine)533*b843c749SSergey Zigachev void dal_i2c_sw_engine_destruct(
534*b843c749SSergey Zigachev struct i2c_sw_engine *engine)
535*b843c749SSergey Zigachev {
536*b843c749SSergey Zigachev dal_i2c_engine_destruct(&engine->base);
537*b843c749SSergey Zigachev }
538*b843c749SSergey Zigachev
destroy(struct i2c_engine ** ptr)539*b843c749SSergey Zigachev static void destroy(
540*b843c749SSergey Zigachev struct i2c_engine **ptr)
541*b843c749SSergey Zigachev {
542*b843c749SSergey Zigachev dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr));
543*b843c749SSergey Zigachev
544*b843c749SSergey Zigachev kfree(*ptr);
545*b843c749SSergey Zigachev *ptr = NULL;
546*b843c749SSergey Zigachev }
547*b843c749SSergey Zigachev
548*b843c749SSergey Zigachev static const struct i2c_engine_funcs i2c_engine_funcs = {
549*b843c749SSergey Zigachev .acquire_engine = dal_i2caux_i2c_sw_engine_acquire_engine,
550*b843c749SSergey Zigachev .destroy = destroy,
551*b843c749SSergey Zigachev .get_speed = dal_i2c_sw_engine_get_speed,
552*b843c749SSergey Zigachev .set_speed = dal_i2c_sw_engine_set_speed,
553*b843c749SSergey Zigachev .setup_engine = dal_i2c_engine_setup_i2c_engine,
554*b843c749SSergey Zigachev .submit_channel_request = dal_i2c_sw_engine_submit_channel_request,
555*b843c749SSergey Zigachev .process_channel_reply = dal_i2c_engine_process_channel_reply,
556*b843c749SSergey Zigachev .get_channel_status = dal_i2c_sw_engine_get_channel_status,
557*b843c749SSergey Zigachev };
558*b843c749SSergey Zigachev
release_engine(struct engine * engine)559*b843c749SSergey Zigachev static void release_engine(
560*b843c749SSergey Zigachev struct engine *engine)
561*b843c749SSergey Zigachev {
562*b843c749SSergey Zigachev
563*b843c749SSergey Zigachev }
564*b843c749SSergey Zigachev
565*b843c749SSergey Zigachev static const struct engine_funcs engine_funcs = {
566*b843c749SSergey Zigachev .release_engine = release_engine,
567*b843c749SSergey Zigachev .get_engine_type = dal_i2c_sw_engine_get_engine_type,
568*b843c749SSergey Zigachev .acquire = dal_i2c_engine_acquire,
569*b843c749SSergey Zigachev .submit_request = dal_i2c_sw_engine_submit_request,
570*b843c749SSergey Zigachev };
571*b843c749SSergey Zigachev
dal_i2c_sw_engine_construct(struct i2c_sw_engine * engine,const struct i2c_sw_engine_create_arg * arg)572*b843c749SSergey Zigachev void dal_i2c_sw_engine_construct(
573*b843c749SSergey Zigachev struct i2c_sw_engine *engine,
574*b843c749SSergey Zigachev const struct i2c_sw_engine_create_arg *arg)
575*b843c749SSergey Zigachev {
576*b843c749SSergey Zigachev dal_i2c_engine_construct(&engine->base, arg->ctx);
577*b843c749SSergey Zigachev dal_i2c_sw_engine_set_speed(&engine->base, arg->default_speed);
578*b843c749SSergey Zigachev engine->base.funcs = &i2c_engine_funcs;
579*b843c749SSergey Zigachev engine->base.base.funcs = &engine_funcs;
580*b843c749SSergey Zigachev }
581*b843c749SSergey Zigachev
dal_i2c_sw_engine_create(const struct i2c_sw_engine_create_arg * arg)582*b843c749SSergey Zigachev struct i2c_engine *dal_i2c_sw_engine_create(
583*b843c749SSergey Zigachev const struct i2c_sw_engine_create_arg *arg)
584*b843c749SSergey Zigachev {
585*b843c749SSergey Zigachev struct i2c_sw_engine *engine;
586*b843c749SSergey Zigachev
587*b843c749SSergey Zigachev if (!arg) {
588*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
589*b843c749SSergey Zigachev return NULL;
590*b843c749SSergey Zigachev }
591*b843c749SSergey Zigachev
592*b843c749SSergey Zigachev engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL);
593*b843c749SSergey Zigachev
594*b843c749SSergey Zigachev if (!engine) {
595*b843c749SSergey Zigachev BREAK_TO_DEBUGGER();
596*b843c749SSergey Zigachev return NULL;
597*b843c749SSergey Zigachev }
598*b843c749SSergey Zigachev
599*b843c749SSergey Zigachev dal_i2c_sw_engine_construct(engine, arg);
600*b843c749SSergey Zigachev return &engine->base;
601*b843c749SSergey Zigachev }
602