xref: /dragonfly/sys/dev/drm/amd/display/dc/inc/resource.h (revision b843c749)
1*b843c749SSergey Zigachev /*
2*b843c749SSergey Zigachev  * Copyright 2015 Advanced Micro Devices, Inc.
3*b843c749SSergey Zigachev  *
4*b843c749SSergey Zigachev  * Permission is hereby granted, free of charge, to any person obtaining a
5*b843c749SSergey Zigachev  * copy of this software and associated documentation files (the "Software"),
6*b843c749SSergey Zigachev  * to deal in the Software without restriction, including without limitation
7*b843c749SSergey Zigachev  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*b843c749SSergey Zigachev  * and/or sell copies of the Software, and to permit persons to whom the
9*b843c749SSergey Zigachev  * Software is furnished to do so, subject to the following conditions:
10*b843c749SSergey Zigachev  *
11*b843c749SSergey Zigachev  * The above copyright notice and this permission notice shall be included in
12*b843c749SSergey Zigachev  * all copies or substantial portions of the Software.
13*b843c749SSergey Zigachev  *
14*b843c749SSergey Zigachev  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*b843c749SSergey Zigachev  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*b843c749SSergey Zigachev  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*b843c749SSergey Zigachev  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*b843c749SSergey Zigachev  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*b843c749SSergey Zigachev  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*b843c749SSergey Zigachev  * OTHER DEALINGS IN THE SOFTWARE.
21*b843c749SSergey Zigachev  *
22*b843c749SSergey Zigachev  * Authors: AMD
23*b843c749SSergey Zigachev  */
24*b843c749SSergey Zigachev 
25*b843c749SSergey Zigachev #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
26*b843c749SSergey Zigachev #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_
27*b843c749SSergey Zigachev 
28*b843c749SSergey Zigachev #include "core_types.h"
29*b843c749SSergey Zigachev #include "core_status.h"
30*b843c749SSergey Zigachev #include "dal_asic_id.h"
31*b843c749SSergey Zigachev #include "dm_pp_smu.h"
32*b843c749SSergey Zigachev 
33*b843c749SSergey Zigachev /* TODO unhardcode, 4 for CZ*/
34*b843c749SSergey Zigachev #define MEMORY_TYPE_MULTIPLIER 4
35*b843c749SSergey Zigachev 
36*b843c749SSergey Zigachev enum dce_version resource_parse_asic_id(
37*b843c749SSergey Zigachev 		struct hw_asic_id asic_id);
38*b843c749SSergey Zigachev 
39*b843c749SSergey Zigachev struct resource_caps {
40*b843c749SSergey Zigachev 	int num_timing_generator;
41*b843c749SSergey Zigachev 	int num_opp;
42*b843c749SSergey Zigachev 	int num_video_plane;
43*b843c749SSergey Zigachev 	int num_audio;
44*b843c749SSergey Zigachev 	int num_stream_encoder;
45*b843c749SSergey Zigachev 	int num_pll;
46*b843c749SSergey Zigachev 	int num_dwb;
47*b843c749SSergey Zigachev };
48*b843c749SSergey Zigachev 
49*b843c749SSergey Zigachev struct resource_straps {
50*b843c749SSergey Zigachev 	uint32_t hdmi_disable;
51*b843c749SSergey Zigachev 	uint32_t dc_pinstraps_audio;
52*b843c749SSergey Zigachev 	uint32_t audio_stream_number;
53*b843c749SSergey Zigachev };
54*b843c749SSergey Zigachev 
55*b843c749SSergey Zigachev struct resource_create_funcs {
56*b843c749SSergey Zigachev 	void (*read_dce_straps)(
57*b843c749SSergey Zigachev 			struct dc_context *ctx, struct resource_straps *straps);
58*b843c749SSergey Zigachev 
59*b843c749SSergey Zigachev 	struct audio *(*create_audio)(
60*b843c749SSergey Zigachev 			struct dc_context *ctx, unsigned int inst);
61*b843c749SSergey Zigachev 
62*b843c749SSergey Zigachev 	struct stream_encoder *(*create_stream_encoder)(
63*b843c749SSergey Zigachev 			enum engine_id eng_id, struct dc_context *ctx);
64*b843c749SSergey Zigachev 
65*b843c749SSergey Zigachev 	struct dce_hwseq *(*create_hwseq)(
66*b843c749SSergey Zigachev 			struct dc_context *ctx);
67*b843c749SSergey Zigachev };
68*b843c749SSergey Zigachev 
69*b843c749SSergey Zigachev bool resource_construct(
70*b843c749SSergey Zigachev 	unsigned int num_virtual_links,
71*b843c749SSergey Zigachev 	struct dc *dc,
72*b843c749SSergey Zigachev 	struct resource_pool *pool,
73*b843c749SSergey Zigachev 	const struct resource_create_funcs *create_funcs);
74*b843c749SSergey Zigachev 
75*b843c749SSergey Zigachev struct resource_pool *dc_create_resource_pool(
76*b843c749SSergey Zigachev 				struct dc *dc,
77*b843c749SSergey Zigachev 				int num_virtual_links,
78*b843c749SSergey Zigachev 				enum dce_version dc_version,
79*b843c749SSergey Zigachev 				struct hw_asic_id asic_id);
80*b843c749SSergey Zigachev 
81*b843c749SSergey Zigachev void dc_destroy_resource_pool(struct dc *dc);
82*b843c749SSergey Zigachev 
83*b843c749SSergey Zigachev enum dc_status resource_map_pool_resources(
84*b843c749SSergey Zigachev 		const struct dc *dc,
85*b843c749SSergey Zigachev 		struct dc_state *context,
86*b843c749SSergey Zigachev 		struct dc_stream_state *stream);
87*b843c749SSergey Zigachev 
88*b843c749SSergey Zigachev bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx);
89*b843c749SSergey Zigachev 
90*b843c749SSergey Zigachev enum dc_status resource_build_scaling_params_for_context(
91*b843c749SSergey Zigachev 		const struct dc *dc,
92*b843c749SSergey Zigachev 		struct dc_state *context);
93*b843c749SSergey Zigachev 
94*b843c749SSergey Zigachev void resource_build_info_frame(struct pipe_ctx *pipe_ctx);
95*b843c749SSergey Zigachev 
96*b843c749SSergey Zigachev void resource_unreference_clock_source(
97*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
98*b843c749SSergey Zigachev 		const struct resource_pool *pool,
99*b843c749SSergey Zigachev 		struct clock_source *clock_source);
100*b843c749SSergey Zigachev 
101*b843c749SSergey Zigachev void resource_reference_clock_source(
102*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
103*b843c749SSergey Zigachev 		const struct resource_pool *pool,
104*b843c749SSergey Zigachev 		struct clock_source *clock_source);
105*b843c749SSergey Zigachev 
106*b843c749SSergey Zigachev int resource_get_clock_source_reference(
107*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
108*b843c749SSergey Zigachev 		const struct resource_pool *pool,
109*b843c749SSergey Zigachev 		struct clock_source *clock_source);
110*b843c749SSergey Zigachev 
111*b843c749SSergey Zigachev bool resource_are_streams_timing_synchronizable(
112*b843c749SSergey Zigachev 		struct dc_stream_state *stream1,
113*b843c749SSergey Zigachev 		struct dc_stream_state *stream2);
114*b843c749SSergey Zigachev 
115*b843c749SSergey Zigachev struct clock_source *resource_find_used_clk_src_for_sharing(
116*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
117*b843c749SSergey Zigachev 		struct pipe_ctx *pipe_ctx);
118*b843c749SSergey Zigachev 
119*b843c749SSergey Zigachev struct clock_source *dc_resource_find_first_free_pll(
120*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
121*b843c749SSergey Zigachev 		const struct resource_pool *pool);
122*b843c749SSergey Zigachev 
123*b843c749SSergey Zigachev struct pipe_ctx *resource_get_head_pipe_for_stream(
124*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
125*b843c749SSergey Zigachev 		struct dc_stream_state *stream);
126*b843c749SSergey Zigachev 
127*b843c749SSergey Zigachev bool resource_attach_surfaces_to_context(
128*b843c749SSergey Zigachev 		struct dc_plane_state *const *plane_state,
129*b843c749SSergey Zigachev 		int surface_count,
130*b843c749SSergey Zigachev 		struct dc_stream_state *dc_stream,
131*b843c749SSergey Zigachev 		struct dc_state *context,
132*b843c749SSergey Zigachev 		const struct resource_pool *pool);
133*b843c749SSergey Zigachev 
134*b843c749SSergey Zigachev struct pipe_ctx *find_idle_secondary_pipe(
135*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
136*b843c749SSergey Zigachev 		const struct resource_pool *pool);
137*b843c749SSergey Zigachev 
138*b843c749SSergey Zigachev bool resource_is_stream_unchanged(
139*b843c749SSergey Zigachev 	struct dc_state *old_context, struct dc_stream_state *stream);
140*b843c749SSergey Zigachev 
141*b843c749SSergey Zigachev bool resource_validate_attach_surfaces(
142*b843c749SSergey Zigachev 		const struct dc_validation_set set[],
143*b843c749SSergey Zigachev 		int set_count,
144*b843c749SSergey Zigachev 		const struct dc_state *old_context,
145*b843c749SSergey Zigachev 		struct dc_state *context,
146*b843c749SSergey Zigachev 		const struct resource_pool *pool);
147*b843c749SSergey Zigachev 
148*b843c749SSergey Zigachev void resource_validate_ctx_update_pointer_after_copy(
149*b843c749SSergey Zigachev 		const struct dc_state *src_ctx,
150*b843c749SSergey Zigachev 		struct dc_state *dst_ctx);
151*b843c749SSergey Zigachev 
152*b843c749SSergey Zigachev enum dc_status resource_map_clock_resources(
153*b843c749SSergey Zigachev 		const struct dc *dc,
154*b843c749SSergey Zigachev 		struct dc_state *context,
155*b843c749SSergey Zigachev 		struct dc_stream_state *stream);
156*b843c749SSergey Zigachev 
157*b843c749SSergey Zigachev enum dc_status resource_map_phy_clock_resources(
158*b843c749SSergey Zigachev 		const struct dc *dc,
159*b843c749SSergey Zigachev 		struct dc_state *context,
160*b843c749SSergey Zigachev 		struct dc_stream_state *stream);
161*b843c749SSergey Zigachev 
162*b843c749SSergey Zigachev bool pipe_need_reprogram(
163*b843c749SSergey Zigachev 		struct pipe_ctx *pipe_ctx_old,
164*b843c749SSergey Zigachev 		struct pipe_ctx *pipe_ctx);
165*b843c749SSergey Zigachev 
166*b843c749SSergey Zigachev void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
167*b843c749SSergey Zigachev 		struct bit_depth_reduction_params *fmt_bit_depth);
168*b843c749SSergey Zigachev 
169*b843c749SSergey Zigachev void update_audio_usage(
170*b843c749SSergey Zigachev 		struct resource_context *res_ctx,
171*b843c749SSergey Zigachev 		const struct resource_pool *pool,
172*b843c749SSergey Zigachev 		struct audio *audio,
173*b843c749SSergey Zigachev 		bool acquired);
174*b843c749SSergey Zigachev #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
175