1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DAL_DPCD_DEFS_H__ 27*b843c749SSergey Zigachev #define __DAL_DPCD_DEFS_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include <drm/drm_dp_helper.h> 30*b843c749SSergey Zigachev #ifndef DP_SINK_HW_REVISION_START // can remove this once the define gets into linux drm_dp_helper.h 31*b843c749SSergey Zigachev #define DP_SINK_HW_REVISION_START 0x409 32*b843c749SSergey Zigachev #endif 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev enum dpcd_revision { 35*b843c749SSergey Zigachev DPCD_REV_10 = 0x10, 36*b843c749SSergey Zigachev DPCD_REV_11 = 0x11, 37*b843c749SSergey Zigachev DPCD_REV_12 = 0x12, 38*b843c749SSergey Zigachev DPCD_REV_13 = 0x13, 39*b843c749SSergey Zigachev DPCD_REV_14 = 0x14 40*b843c749SSergey Zigachev }; 41*b843c749SSergey Zigachev 42*b843c749SSergey Zigachev /* these are the types stored at DOWNSTREAMPORT_PRESENT */ 43*b843c749SSergey Zigachev enum dpcd_downstream_port_type { 44*b843c749SSergey Zigachev DOWNSTREAM_DP = 0, 45*b843c749SSergey Zigachev DOWNSTREAM_VGA, 46*b843c749SSergey Zigachev DOWNSTREAM_DVI_HDMI, 47*b843c749SSergey Zigachev DOWNSTREAM_NONDDC /* has no EDID (TV,CV) */ 48*b843c749SSergey Zigachev }; 49*b843c749SSergey Zigachev 50*b843c749SSergey Zigachev enum dpcd_link_test_patterns { 51*b843c749SSergey Zigachev LINK_TEST_PATTERN_NONE = 0, 52*b843c749SSergey Zigachev LINK_TEST_PATTERN_COLOR_RAMP, 53*b843c749SSergey Zigachev LINK_TEST_PATTERN_VERTICAL_BARS, 54*b843c749SSergey Zigachev LINK_TEST_PATTERN_COLOR_SQUARES 55*b843c749SSergey Zigachev }; 56*b843c749SSergey Zigachev 57*b843c749SSergey Zigachev enum dpcd_test_color_format { 58*b843c749SSergey Zigachev TEST_COLOR_FORMAT_RGB = 0, 59*b843c749SSergey Zigachev TEST_COLOR_FORMAT_YCBCR422, 60*b843c749SSergey Zigachev TEST_COLOR_FORMAT_YCBCR444 61*b843c749SSergey Zigachev }; 62*b843c749SSergey Zigachev 63*b843c749SSergey Zigachev enum dpcd_test_bit_depth { 64*b843c749SSergey Zigachev TEST_BIT_DEPTH_6 = 0, 65*b843c749SSergey Zigachev TEST_BIT_DEPTH_8, 66*b843c749SSergey Zigachev TEST_BIT_DEPTH_10, 67*b843c749SSergey Zigachev TEST_BIT_DEPTH_12, 68*b843c749SSergey Zigachev TEST_BIT_DEPTH_16 69*b843c749SSergey Zigachev }; 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev /* PHY (encoder) test patterns 72*b843c749SSergey Zigachev The order of test patterns follows DPCD register PHY_TEST_PATTERN (0x248) 73*b843c749SSergey Zigachev */ 74*b843c749SSergey Zigachev enum dpcd_phy_test_patterns { 75*b843c749SSergey Zigachev PHY_TEST_PATTERN_NONE = 0, 76*b843c749SSergey Zigachev PHY_TEST_PATTERN_D10_2, 77*b843c749SSergey Zigachev PHY_TEST_PATTERN_SYMBOL_ERROR, 78*b843c749SSergey Zigachev PHY_TEST_PATTERN_PRBS7, 79*b843c749SSergey Zigachev PHY_TEST_PATTERN_80BIT_CUSTOM,/* For DP1.2 only */ 80*b843c749SSergey Zigachev PHY_TEST_PATTERN_CP2520_1, 81*b843c749SSergey Zigachev PHY_TEST_PATTERN_CP2520_2, 82*b843c749SSergey Zigachev PHY_TEST_PATTERN_CP2520_3, /* same as TPS4 */ 83*b843c749SSergey Zigachev }; 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev enum dpcd_test_dyn_range { 86*b843c749SSergey Zigachev TEST_DYN_RANGE_VESA = 0, 87*b843c749SSergey Zigachev TEST_DYN_RANGE_CEA 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev enum dpcd_audio_test_pattern { 91*b843c749SSergey Zigachev AUDIO_TEST_PATTERN_OPERATOR_DEFINED = 0,/* direct HW translation */ 92*b843c749SSergey Zigachev AUDIO_TEST_PATTERN_SAWTOOTH 93*b843c749SSergey Zigachev }; 94*b843c749SSergey Zigachev 95*b843c749SSergey Zigachev enum dpcd_audio_sampling_rate { 96*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_32KHZ = 0,/* direct HW translation */ 97*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_44_1KHZ, 98*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_48KHZ, 99*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_88_2KHZ, 100*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_96KHZ, 101*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_176_4KHZ, 102*b843c749SSergey Zigachev AUDIO_SAMPLING_RATE_192KHZ 103*b843c749SSergey Zigachev }; 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev enum dpcd_audio_channels { 106*b843c749SSergey Zigachev AUDIO_CHANNELS_1 = 0,/* direct HW translation */ 107*b843c749SSergey Zigachev AUDIO_CHANNELS_2, 108*b843c749SSergey Zigachev AUDIO_CHANNELS_3, 109*b843c749SSergey Zigachev AUDIO_CHANNELS_4, 110*b843c749SSergey Zigachev AUDIO_CHANNELS_5, 111*b843c749SSergey Zigachev AUDIO_CHANNELS_6, 112*b843c749SSergey Zigachev AUDIO_CHANNELS_7, 113*b843c749SSergey Zigachev AUDIO_CHANNELS_8, 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev AUDIO_CHANNELS_COUNT 116*b843c749SSergey Zigachev }; 117*b843c749SSergey Zigachev 118*b843c749SSergey Zigachev enum dpcd_audio_test_pattern_periods { 119*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_NOTUSED = 0,/* direct HW translation */ 120*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_3, 121*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_6, 122*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_12, 123*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_24, 124*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_48, 125*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_96, 126*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_192, 127*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_384, 128*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_768, 129*b843c749SSergey Zigachev DPCD_AUDIO_TEST_PATTERN_PERIOD_1536 130*b843c749SSergey Zigachev }; 131*b843c749SSergey Zigachev 132*b843c749SSergey Zigachev /* This enum is for programming DPCD TRAINING_PATTERN_SET */ 133*b843c749SSergey Zigachev enum dpcd_training_patterns { 134*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_VIDEOIDLE = 0,/* direct HW translation! */ 135*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_1, 136*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_2, 137*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_3, 138*b843c749SSergey Zigachev DPCD_TRAINING_PATTERN_4 = 7 139*b843c749SSergey Zigachev }; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev /* This enum is for use with PsrSinkPsrStatus.bits.sinkSelfRefreshStatus 142*b843c749SSergey Zigachev It defines the possible PSR states. */ 143*b843c749SSergey Zigachev enum dpcd_psr_sink_states { 144*b843c749SSergey Zigachev PSR_SINK_STATE_INACTIVE = 0, 145*b843c749SSergey Zigachev PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SOURCE_TIMING = 1, 146*b843c749SSergey Zigachev PSR_SINK_STATE_ACTIVE_DISPLAY_FROM_SINK_RFB = 2, 147*b843c749SSergey Zigachev PSR_SINK_STATE_ACTIVE_CAPTURE_DISPLAY_ON_SINK_TIMING = 3, 148*b843c749SSergey Zigachev PSR_SINK_STATE_ACTIVE_CAPTURE_TIMING_RESYNC = 4, 149*b843c749SSergey Zigachev PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, 150*b843c749SSergey Zigachev }; 151*b843c749SSergey Zigachev 152*b843c749SSergey Zigachev #endif /* __DAL_DPCD_DEFS_H__ */ 153