1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2012-15 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev * Authors: AMD 23*b843c749SSergey Zigachev * 24*b843c749SSergey Zigachev */ 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #ifndef __DAL_GRPH_OBJECT_CTRL_DEFS_H__ 27*b843c749SSergey Zigachev #define __DAL_GRPH_OBJECT_CTRL_DEFS_H__ 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #include "grph_object_defs.h" 30*b843c749SSergey Zigachev 31*b843c749SSergey Zigachev /* 32*b843c749SSergey Zigachev * ##################################################### 33*b843c749SSergey Zigachev * ##################################################### 34*b843c749SSergey Zigachev * 35*b843c749SSergey Zigachev * These defines shared between asic_control/bios_parser and other 36*b843c749SSergey Zigachev * DAL components 37*b843c749SSergey Zigachev * 38*b843c749SSergey Zigachev * ##################################################### 39*b843c749SSergey Zigachev * ##################################################### 40*b843c749SSergey Zigachev */ 41*b843c749SSergey Zigachev 42*b843c749SSergey Zigachev enum display_output_bit_depth { 43*b843c749SSergey Zigachev PANEL_UNDEFINE = 0, 44*b843c749SSergey Zigachev PANEL_6BIT_COLOR = 1, 45*b843c749SSergey Zigachev PANEL_8BIT_COLOR = 2, 46*b843c749SSergey Zigachev PANEL_10BIT_COLOR = 3, 47*b843c749SSergey Zigachev PANEL_12BIT_COLOR = 4, 48*b843c749SSergey Zigachev PANEL_16BIT_COLOR = 5, 49*b843c749SSergey Zigachev }; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev 52*b843c749SSergey Zigachev /* Device type as abstracted by ATOM BIOS */ 53*b843c749SSergey Zigachev enum dal_device_type { 54*b843c749SSergey Zigachev DEVICE_TYPE_UNKNOWN = 0, 55*b843c749SSergey Zigachev DEVICE_TYPE_LCD, 56*b843c749SSergey Zigachev DEVICE_TYPE_CRT, 57*b843c749SSergey Zigachev DEVICE_TYPE_DFP, 58*b843c749SSergey Zigachev DEVICE_TYPE_CV, 59*b843c749SSergey Zigachev DEVICE_TYPE_TV, 60*b843c749SSergey Zigachev DEVICE_TYPE_CF, 61*b843c749SSergey Zigachev DEVICE_TYPE_WIRELESS 62*b843c749SSergey Zigachev }; 63*b843c749SSergey Zigachev 64*b843c749SSergey Zigachev /* Device ID as abstracted by ATOM BIOS */ 65*b843c749SSergey Zigachev struct device_id { 66*b843c749SSergey Zigachev enum dal_device_type device_type:16; 67*b843c749SSergey Zigachev uint32_t enum_id:16; /* 1 based enum */ 68*b843c749SSergey Zigachev uint16_t raw_device_tag; 69*b843c749SSergey Zigachev }; 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev struct graphics_object_i2c_info { 72*b843c749SSergey Zigachev struct gpio_info { 73*b843c749SSergey Zigachev uint32_t clk_mask_register_index; 74*b843c749SSergey Zigachev uint32_t clk_en_register_index; 75*b843c749SSergey Zigachev uint32_t clk_y_register_index; 76*b843c749SSergey Zigachev uint32_t clk_a_register_index; 77*b843c749SSergey Zigachev uint32_t data_mask_register_index; 78*b843c749SSergey Zigachev uint32_t data_en_register_index; 79*b843c749SSergey Zigachev uint32_t data_y_register_index; 80*b843c749SSergey Zigachev uint32_t data_a_register_index; 81*b843c749SSergey Zigachev 82*b843c749SSergey Zigachev uint32_t clk_mask_shift; 83*b843c749SSergey Zigachev uint32_t clk_en_shift; 84*b843c749SSergey Zigachev uint32_t clk_y_shift; 85*b843c749SSergey Zigachev uint32_t clk_a_shift; 86*b843c749SSergey Zigachev uint32_t data_mask_shift; 87*b843c749SSergey Zigachev uint32_t data_en_shift; 88*b843c749SSergey Zigachev uint32_t data_y_shift; 89*b843c749SSergey Zigachev uint32_t data_a_shift; 90*b843c749SSergey Zigachev } gpio_info; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev bool i2c_hw_assist; 93*b843c749SSergey Zigachev uint32_t i2c_line; 94*b843c749SSergey Zigachev uint32_t i2c_engine_id; 95*b843c749SSergey Zigachev uint32_t i2c_slave_address; 96*b843c749SSergey Zigachev }; 97*b843c749SSergey Zigachev 98*b843c749SSergey Zigachev struct graphics_object_hpd_info { 99*b843c749SSergey Zigachev uint8_t hpd_int_gpio_uid; 100*b843c749SSergey Zigachev uint8_t hpd_active; 101*b843c749SSergey Zigachev }; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev struct connector_device_tag_info { 104*b843c749SSergey Zigachev uint32_t acpi_device; 105*b843c749SSergey Zigachev struct device_id dev_id; 106*b843c749SSergey Zigachev }; 107*b843c749SSergey Zigachev 108*b843c749SSergey Zigachev struct device_timing { 109*b843c749SSergey Zigachev struct misc_info { 110*b843c749SSergey Zigachev uint32_t HORIZONTAL_CUT_OFF:1; 111*b843c749SSergey Zigachev /* 0=Active High, 1=Active Low */ 112*b843c749SSergey Zigachev uint32_t H_SYNC_POLARITY:1; 113*b843c749SSergey Zigachev /* 0=Active High, 1=Active Low */ 114*b843c749SSergey Zigachev uint32_t V_SYNC_POLARITY:1; 115*b843c749SSergey Zigachev uint32_t VERTICAL_CUT_OFF:1; 116*b843c749SSergey Zigachev uint32_t H_REPLICATION_BY2:1; 117*b843c749SSergey Zigachev uint32_t V_REPLICATION_BY2:1; 118*b843c749SSergey Zigachev uint32_t COMPOSITE_SYNC:1; 119*b843c749SSergey Zigachev uint32_t INTERLACE:1; 120*b843c749SSergey Zigachev uint32_t DOUBLE_CLOCK:1; 121*b843c749SSergey Zigachev uint32_t RGB888:1; 122*b843c749SSergey Zigachev uint32_t GREY_LEVEL:2; 123*b843c749SSergey Zigachev uint32_t SPATIAL:1; 124*b843c749SSergey Zigachev uint32_t TEMPORAL:1; 125*b843c749SSergey Zigachev uint32_t API_ENABLED:1; 126*b843c749SSergey Zigachev } misc_info; 127*b843c749SSergey Zigachev 128*b843c749SSergey Zigachev uint32_t pixel_clk; /* in KHz */ 129*b843c749SSergey Zigachev uint32_t horizontal_addressable; 130*b843c749SSergey Zigachev uint32_t horizontal_blanking_time; 131*b843c749SSergey Zigachev uint32_t vertical_addressable; 132*b843c749SSergey Zigachev uint32_t vertical_blanking_time; 133*b843c749SSergey Zigachev uint32_t horizontal_sync_offset; 134*b843c749SSergey Zigachev uint32_t horizontal_sync_width; 135*b843c749SSergey Zigachev uint32_t vertical_sync_offset; 136*b843c749SSergey Zigachev uint32_t vertical_sync_width; 137*b843c749SSergey Zigachev uint32_t horizontal_border; 138*b843c749SSergey Zigachev uint32_t vertical_border; 139*b843c749SSergey Zigachev }; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev struct supported_refresh_rate { 142*b843c749SSergey Zigachev uint32_t REFRESH_RATE_30HZ:1; 143*b843c749SSergey Zigachev uint32_t REFRESH_RATE_40HZ:1; 144*b843c749SSergey Zigachev uint32_t REFRESH_RATE_48HZ:1; 145*b843c749SSergey Zigachev uint32_t REFRESH_RATE_50HZ:1; 146*b843c749SSergey Zigachev uint32_t REFRESH_RATE_60HZ:1; 147*b843c749SSergey Zigachev }; 148*b843c749SSergey Zigachev 149*b843c749SSergey Zigachev struct embedded_panel_info { 150*b843c749SSergey Zigachev struct device_timing lcd_timing; 151*b843c749SSergey Zigachev uint32_t ss_id; 152*b843c749SSergey Zigachev struct supported_refresh_rate supported_rr; 153*b843c749SSergey Zigachev uint32_t drr_enabled; 154*b843c749SSergey Zigachev uint32_t min_drr_refresh_rate; 155*b843c749SSergey Zigachev bool realtek_eDPToLVDS; 156*b843c749SSergey Zigachev }; 157*b843c749SSergey Zigachev 158*b843c749SSergey Zigachev struct dc_firmware_info { 159*b843c749SSergey Zigachev struct pll_info { 160*b843c749SSergey Zigachev uint32_t crystal_frequency; /* in KHz */ 161*b843c749SSergey Zigachev uint32_t min_input_pxl_clk_pll_frequency; /* in KHz */ 162*b843c749SSergey Zigachev uint32_t max_input_pxl_clk_pll_frequency; /* in KHz */ 163*b843c749SSergey Zigachev uint32_t min_output_pxl_clk_pll_frequency; /* in KHz */ 164*b843c749SSergey Zigachev uint32_t max_output_pxl_clk_pll_frequency; /* in KHz */ 165*b843c749SSergey Zigachev } pll_info; 166*b843c749SSergey Zigachev 167*b843c749SSergey Zigachev struct firmware_feature { 168*b843c749SSergey Zigachev uint32_t memory_clk_ss_percentage; 169*b843c749SSergey Zigachev uint32_t engine_clk_ss_percentage; 170*b843c749SSergey Zigachev } feature; 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev uint32_t default_display_engine_pll_frequency; /* in KHz */ 173*b843c749SSergey Zigachev uint32_t external_clock_source_frequency_for_dp; /* in KHz */ 174*b843c749SSergey Zigachev uint32_t smu_gpu_pll_output_freq; /* in KHz */ 175*b843c749SSergey Zigachev uint8_t min_allowed_bl_level; 176*b843c749SSergey Zigachev uint8_t remote_display_config; 177*b843c749SSergey Zigachev uint32_t default_memory_clk; /* in KHz */ 178*b843c749SSergey Zigachev uint32_t default_engine_clk; /* in KHz */ 179*b843c749SSergey Zigachev uint32_t dp_phy_ref_clk; /* in KHz - DCE12 only */ 180*b843c749SSergey Zigachev uint32_t i2c_engine_ref_clk; /* in KHz - DCE12 only */ 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev 183*b843c749SSergey Zigachev }; 184*b843c749SSergey Zigachev 185*b843c749SSergey Zigachev struct step_and_delay_info { 186*b843c749SSergey Zigachev uint32_t step; 187*b843c749SSergey Zigachev uint32_t delay; 188*b843c749SSergey Zigachev uint32_t recommended_ref_div; 189*b843c749SSergey Zigachev }; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev struct spread_spectrum_info { 192*b843c749SSergey Zigachev struct spread_spectrum_type { 193*b843c749SSergey Zigachev bool CENTER_MODE:1; 194*b843c749SSergey Zigachev bool EXTERNAL:1; 195*b843c749SSergey Zigachev bool STEP_AND_DELAY_INFO:1; 196*b843c749SSergey Zigachev } type; 197*b843c749SSergey Zigachev 198*b843c749SSergey Zigachev /* in unit of 0.01% (spreadPercentageDivider = 100), 199*b843c749SSergey Zigachev otherwise in 0.001% units (spreadPercentageDivider = 1000); */ 200*b843c749SSergey Zigachev uint32_t spread_spectrum_percentage; 201*b843c749SSergey Zigachev uint32_t spread_percentage_divider; /* 100 or 1000 */ 202*b843c749SSergey Zigachev uint32_t spread_spectrum_range; /* modulation freq (HZ)*/ 203*b843c749SSergey Zigachev 204*b843c749SSergey Zigachev union { 205*b843c749SSergey Zigachev struct step_and_delay_info step_and_delay_info; 206*b843c749SSergey Zigachev /* For mem/engine/uvd, Clock Out frequence (VCO ), 207*b843c749SSergey Zigachev in unit of kHz. For TMDS/HDMI/LVDS, it is pixel clock, 208*b843c749SSergey Zigachev for DP, it is link clock ( 270000 or 162000 ) */ 209*b843c749SSergey Zigachev uint32_t target_clock_range; /* in KHz */ 210*b843c749SSergey Zigachev }; 211*b843c749SSergey Zigachev 212*b843c749SSergey Zigachev }; 213*b843c749SSergey Zigachev 214*b843c749SSergey Zigachev struct graphics_object_encoder_cap_info { 215*b843c749SSergey Zigachev uint32_t dp_hbr2_cap:1; 216*b843c749SSergey Zigachev uint32_t dp_hbr2_validated:1; 217*b843c749SSergey Zigachev /* 218*b843c749SSergey Zigachev * TODO: added MST and HDMI 6G capable flags 219*b843c749SSergey Zigachev */ 220*b843c749SSergey Zigachev uint32_t reserved:15; 221*b843c749SSergey Zigachev }; 222*b843c749SSergey Zigachev 223*b843c749SSergey Zigachev struct din_connector_info { 224*b843c749SSergey Zigachev uint32_t gpio_id; 225*b843c749SSergey Zigachev bool gpio_tv_active_state; 226*b843c749SSergey Zigachev }; 227*b843c749SSergey Zigachev 228*b843c749SSergey Zigachev /* Invalid channel mapping */ 229*b843c749SSergey Zigachev enum { INVALID_DDI_CHANNEL_MAPPING = 0x0 }; 230*b843c749SSergey Zigachev 231*b843c749SSergey Zigachev /** 232*b843c749SSergey Zigachev * DDI PHY channel mapping reflecting XBAR setting 233*b843c749SSergey Zigachev */ 234*b843c749SSergey Zigachev union ddi_channel_mapping { 235*b843c749SSergey Zigachev struct mapping { 236*b843c749SSergey Zigachev uint8_t lane0:2; /* Mapping for lane 0 */ 237*b843c749SSergey Zigachev uint8_t lane1:2; /* Mapping for lane 1 */ 238*b843c749SSergey Zigachev uint8_t lane2:2; /* Mapping for lane 2 */ 239*b843c749SSergey Zigachev uint8_t lane3:2; /* Mapping for lane 3 */ 240*b843c749SSergey Zigachev } mapping; 241*b843c749SSergey Zigachev uint8_t raw; 242*b843c749SSergey Zigachev }; 243*b843c749SSergey Zigachev 244*b843c749SSergey Zigachev /** 245*b843c749SSergey Zigachev * Transmitter output configuration description 246*b843c749SSergey Zigachev */ 247*b843c749SSergey Zigachev struct transmitter_configuration_info { 248*b843c749SSergey Zigachev /* DDI PHY ID for the transmitter */ 249*b843c749SSergey Zigachev enum transmitter transmitter_phy_id; 250*b843c749SSergey Zigachev /* DDI PHY channel mapping reflecting crossbar setting */ 251*b843c749SSergey Zigachev union ddi_channel_mapping output_channel_mapping; 252*b843c749SSergey Zigachev }; 253*b843c749SSergey Zigachev 254*b843c749SSergey Zigachev struct transmitter_configuration { 255*b843c749SSergey Zigachev /* Configuration for the primary transmitter */ 256*b843c749SSergey Zigachev struct transmitter_configuration_info primary_transmitter_config; 257*b843c749SSergey Zigachev /* Secondary transmitter configuration for Dual-link DVI */ 258*b843c749SSergey Zigachev struct transmitter_configuration_info secondary_transmitter_config; 259*b843c749SSergey Zigachev }; 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev /* These size should be sufficient to store info coming from BIOS */ 262*b843c749SSergey Zigachev #define NUMBER_OF_UCHAR_FOR_GUID 16 263*b843c749SSergey Zigachev #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 264*b843c749SSergey Zigachev #define NUMBER_OF_CSR_M3_ARB 10 265*b843c749SSergey Zigachev #define NUMBER_OF_DISP_CLK_VOLTAGE 4 266*b843c749SSergey Zigachev #define NUMBER_OF_AVAILABLE_SCLK 5 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev struct i2c_reg_info { 269*b843c749SSergey Zigachev unsigned char i2c_reg_index; 270*b843c749SSergey Zigachev unsigned char i2c_reg_val; 271*b843c749SSergey Zigachev }; 272*b843c749SSergey Zigachev 273*b843c749SSergey Zigachev struct ext_hdmi_settings { 274*b843c749SSergey Zigachev unsigned char slv_addr; 275*b843c749SSergey Zigachev unsigned char reg_num; 276*b843c749SSergey Zigachev struct i2c_reg_info reg_settings[9]; 277*b843c749SSergey Zigachev unsigned char reg_num_6g; 278*b843c749SSergey Zigachev struct i2c_reg_info reg_settings_6g[3]; 279*b843c749SSergey Zigachev }; 280*b843c749SSergey Zigachev 281*b843c749SSergey Zigachev 282*b843c749SSergey Zigachev /* V6 */ 283*b843c749SSergey Zigachev struct integrated_info { 284*b843c749SSergey Zigachev struct clock_voltage_caps { 285*b843c749SSergey Zigachev /* The Voltage Index indicated by FUSE, same voltage index 286*b843c749SSergey Zigachev shared with SCLK DPM fuse table */ 287*b843c749SSergey Zigachev uint32_t voltage_index; 288*b843c749SSergey Zigachev /* Maximum clock supported with specified voltage index */ 289*b843c749SSergey Zigachev uint32_t max_supported_clk; /* in KHz */ 290*b843c749SSergey Zigachev } disp_clk_voltage[NUMBER_OF_DISP_CLK_VOLTAGE]; 291*b843c749SSergey Zigachev 292*b843c749SSergey Zigachev struct display_connection_info { 293*b843c749SSergey Zigachev struct external_display_path { 294*b843c749SSergey Zigachev /* A bit vector to show what devices are supported */ 295*b843c749SSergey Zigachev uint32_t device_tag; 296*b843c749SSergey Zigachev /* 16bit device ACPI id. */ 297*b843c749SSergey Zigachev uint32_t device_acpi_enum; 298*b843c749SSergey Zigachev /* A physical connector for displays to plug in, 299*b843c749SSergey Zigachev using object connector definitions */ 300*b843c749SSergey Zigachev struct graphics_object_id device_connector_id; 301*b843c749SSergey Zigachev /* An index into external AUX/DDC channel LUT */ 302*b843c749SSergey Zigachev uint8_t ext_aux_ddc_lut_index; 303*b843c749SSergey Zigachev /* An index into external HPD pin LUT */ 304*b843c749SSergey Zigachev uint8_t ext_hpd_pin_lut_index; 305*b843c749SSergey Zigachev /* external encoder object id */ 306*b843c749SSergey Zigachev struct graphics_object_id ext_encoder_obj_id; 307*b843c749SSergey Zigachev /* XBAR mapping of the PHY channels */ 308*b843c749SSergey Zigachev union ddi_channel_mapping channel_mapping; 309*b843c749SSergey Zigachev 310*b843c749SSergey Zigachev unsigned short caps; 311*b843c749SSergey Zigachev } path[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; 312*b843c749SSergey Zigachev 313*b843c749SSergey Zigachev uint8_t gu_id[NUMBER_OF_UCHAR_FOR_GUID]; 314*b843c749SSergey Zigachev uint8_t checksum; 315*b843c749SSergey Zigachev } ext_disp_conn_info; /* exiting long long time */ 316*b843c749SSergey Zigachev 317*b843c749SSergey Zigachev struct available_s_clk_list { 318*b843c749SSergey Zigachev /* Maximum clock supported with specified voltage index */ 319*b843c749SSergey Zigachev uint32_t supported_s_clk; /* in KHz */ 320*b843c749SSergey Zigachev /* The Voltage Index indicated by FUSE for specified SCLK */ 321*b843c749SSergey Zigachev uint32_t voltage_index; 322*b843c749SSergey Zigachev /* The Voltage ID indicated by FUSE for specified SCLK */ 323*b843c749SSergey Zigachev uint32_t voltage_id; 324*b843c749SSergey Zigachev } avail_s_clk[NUMBER_OF_AVAILABLE_SCLK]; 325*b843c749SSergey Zigachev 326*b843c749SSergey Zigachev uint8_t memory_type; 327*b843c749SSergey Zigachev uint8_t ma_channel_number; 328*b843c749SSergey Zigachev uint32_t boot_up_engine_clock; /* in KHz */ 329*b843c749SSergey Zigachev uint32_t dentist_vco_freq; /* in KHz */ 330*b843c749SSergey Zigachev uint32_t boot_up_uma_clock; /* in KHz */ 331*b843c749SSergey Zigachev uint32_t boot_up_req_display_vector; 332*b843c749SSergey Zigachev uint32_t other_display_misc; 333*b843c749SSergey Zigachev uint32_t gpu_cap_info; 334*b843c749SSergey Zigachev uint32_t sb_mmio_base_addr; 335*b843c749SSergey Zigachev uint32_t system_config; 336*b843c749SSergey Zigachev uint32_t cpu_cap_info; 337*b843c749SSergey Zigachev uint32_t max_nb_voltage; 338*b843c749SSergey Zigachev uint32_t min_nb_voltage; 339*b843c749SSergey Zigachev uint32_t boot_up_nb_voltage; 340*b843c749SSergey Zigachev uint32_t ext_disp_conn_info_offset; 341*b843c749SSergey Zigachev uint32_t csr_m3_arb_cntl_default[NUMBER_OF_CSR_M3_ARB]; 342*b843c749SSergey Zigachev uint32_t csr_m3_arb_cntl_uvd[NUMBER_OF_CSR_M3_ARB]; 343*b843c749SSergey Zigachev uint32_t csr_m3_arb_cntl_fs3d[NUMBER_OF_CSR_M3_ARB]; 344*b843c749SSergey Zigachev uint32_t gmc_restore_reset_time; 345*b843c749SSergey Zigachev uint32_t minimum_n_clk; 346*b843c749SSergey Zigachev uint32_t idle_n_clk; 347*b843c749SSergey Zigachev uint32_t ddr_dll_power_up_time; 348*b843c749SSergey Zigachev uint32_t ddr_pll_power_up_time; 349*b843c749SSergey Zigachev /* start for V6 */ 350*b843c749SSergey Zigachev uint32_t pcie_clk_ss_type; 351*b843c749SSergey Zigachev uint32_t lvds_ss_percentage; 352*b843c749SSergey Zigachev uint32_t lvds_sspread_rate_in_10hz; 353*b843c749SSergey Zigachev uint32_t hdmi_ss_percentage; 354*b843c749SSergey Zigachev uint32_t hdmi_sspread_rate_in_10hz; 355*b843c749SSergey Zigachev uint32_t dvi_ss_percentage; 356*b843c749SSergey Zigachev uint32_t dvi_sspread_rate_in_10_hz; 357*b843c749SSergey Zigachev uint32_t sclk_dpm_boost_margin; 358*b843c749SSergey Zigachev uint32_t sclk_dpm_throttle_margin; 359*b843c749SSergey Zigachev uint32_t sclk_dpm_tdp_limit_pg; 360*b843c749SSergey Zigachev uint32_t sclk_dpm_tdp_limit_boost; 361*b843c749SSergey Zigachev uint32_t boost_engine_clock; 362*b843c749SSergey Zigachev uint32_t boost_vid_2bit; 363*b843c749SSergey Zigachev uint32_t enable_boost; 364*b843c749SSergey Zigachev uint32_t gnb_tdp_limit; 365*b843c749SSergey Zigachev /* Start from V7 */ 366*b843c749SSergey Zigachev uint32_t max_lvds_pclk_freq_in_single_link; 367*b843c749SSergey Zigachev uint32_t lvds_misc; 368*b843c749SSergey Zigachev uint32_t lvds_pwr_on_seq_dig_on_to_de_in_4ms; 369*b843c749SSergey Zigachev uint32_t lvds_pwr_on_seq_de_to_vary_bl_in_4ms; 370*b843c749SSergey Zigachev uint32_t lvds_pwr_off_seq_vary_bl_to_de_in4ms; 371*b843c749SSergey Zigachev uint32_t lvds_pwr_off_seq_de_to_dig_on_in4ms; 372*b843c749SSergey Zigachev uint32_t lvds_off_to_on_delay_in_4ms; 373*b843c749SSergey Zigachev uint32_t lvds_pwr_on_seq_vary_bl_to_blon_in_4ms; 374*b843c749SSergey Zigachev uint32_t lvds_pwr_off_seq_blon_to_vary_bl_in_4ms; 375*b843c749SSergey Zigachev uint32_t lvds_reserved1; 376*b843c749SSergey Zigachev uint32_t lvds_bit_depth_control_val; 377*b843c749SSergey Zigachev //Start from V9 378*b843c749SSergey Zigachev unsigned char dp0_ext_hdmi_slv_addr; 379*b843c749SSergey Zigachev unsigned char dp0_ext_hdmi_reg_num; 380*b843c749SSergey Zigachev struct i2c_reg_info dp0_ext_hdmi_reg_settings[9]; 381*b843c749SSergey Zigachev unsigned char dp0_ext_hdmi_6g_reg_num; 382*b843c749SSergey Zigachev struct i2c_reg_info dp0_ext_hdmi_6g_reg_settings[3]; 383*b843c749SSergey Zigachev unsigned char dp1_ext_hdmi_slv_addr; 384*b843c749SSergey Zigachev unsigned char dp1_ext_hdmi_reg_num; 385*b843c749SSergey Zigachev struct i2c_reg_info dp1_ext_hdmi_reg_settings[9]; 386*b843c749SSergey Zigachev unsigned char dp1_ext_hdmi_6g_reg_num; 387*b843c749SSergey Zigachev struct i2c_reg_info dp1_ext_hdmi_6g_reg_settings[3]; 388*b843c749SSergey Zigachev unsigned char dp2_ext_hdmi_slv_addr; 389*b843c749SSergey Zigachev unsigned char dp2_ext_hdmi_reg_num; 390*b843c749SSergey Zigachev struct i2c_reg_info dp2_ext_hdmi_reg_settings[9]; 391*b843c749SSergey Zigachev unsigned char dp2_ext_hdmi_6g_reg_num; 392*b843c749SSergey Zigachev struct i2c_reg_info dp2_ext_hdmi_6g_reg_settings[3]; 393*b843c749SSergey Zigachev unsigned char dp3_ext_hdmi_slv_addr; 394*b843c749SSergey Zigachev unsigned char dp3_ext_hdmi_reg_num; 395*b843c749SSergey Zigachev struct i2c_reg_info dp3_ext_hdmi_reg_settings[9]; 396*b843c749SSergey Zigachev unsigned char dp3_ext_hdmi_6g_reg_num; 397*b843c749SSergey Zigachev struct i2c_reg_info dp3_ext_hdmi_6g_reg_settings[3]; 398*b843c749SSergey Zigachev /* V11 */ 399*b843c749SSergey Zigachev uint32_t dp_ss_control; 400*b843c749SSergey Zigachev }; 401*b843c749SSergey Zigachev 402*b843c749SSergey Zigachev /** 403*b843c749SSergey Zigachev * Power source ids. 404*b843c749SSergey Zigachev */ 405*b843c749SSergey Zigachev enum power_source { 406*b843c749SSergey Zigachev POWER_SOURCE_AC = 0, 407*b843c749SSergey Zigachev POWER_SOURCE_DC, 408*b843c749SSergey Zigachev POWER_SOURCE_LIMITED_POWER, 409*b843c749SSergey Zigachev POWER_SOURCE_LIMITED_POWER_2, 410*b843c749SSergey Zigachev POWER_SOURCE_MAX 411*b843c749SSergey Zigachev }; 412*b843c749SSergey Zigachev 413*b843c749SSergey Zigachev struct bios_event_info { 414*b843c749SSergey Zigachev uint32_t thermal_state; 415*b843c749SSergey Zigachev uint32_t backlight_level; 416*b843c749SSergey Zigachev enum power_source powerSource; 417*b843c749SSergey Zigachev bool has_thermal_state_changed; 418*b843c749SSergey Zigachev bool has_power_source_changed; 419*b843c749SSergey Zigachev bool has_forced_mode_changed; 420*b843c749SSergey Zigachev bool forced_mode; 421*b843c749SSergey Zigachev bool backlight_changed; 422*b843c749SSergey Zigachev }; 423*b843c749SSergey Zigachev 424*b843c749SSergey Zigachev /* 425*b843c749SSergey Zigachev * DFS-bypass flag 426*b843c749SSergey Zigachev */ 427*b843c749SSergey Zigachev /* Copy of SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS from atombios.h */ 428*b843c749SSergey Zigachev enum { 429*b843c749SSergey Zigachev DFS_BYPASS_ENABLE = 0x10 430*b843c749SSergey Zigachev }; 431*b843c749SSergey Zigachev 432*b843c749SSergey Zigachev enum { 433*b843c749SSergey Zigachev INVALID_BACKLIGHT = -1 434*b843c749SSergey Zigachev }; 435*b843c749SSergey Zigachev 436*b843c749SSergey Zigachev struct panel_backlight_boundaries { 437*b843c749SSergey Zigachev uint32_t min_signal_level; 438*b843c749SSergey Zigachev uint32_t max_signal_level; 439*b843c749SSergey Zigachev }; 440*b843c749SSergey Zigachev 441*b843c749SSergey Zigachev 442*b843c749SSergey Zigachev #endif 443