1c59a5c48SFrançois Tigeot /* 2c59a5c48SFrançois Tigeot * Copyright 2015 Advanced Micro Devices, Inc. 3c59a5c48SFrançois Tigeot * 4c59a5c48SFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 5c59a5c48SFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 6c59a5c48SFrançois Tigeot * to deal in the Software without restriction, including without limitation 7c59a5c48SFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c59a5c48SFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 9c59a5c48SFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 10c59a5c48SFrançois Tigeot * 11c59a5c48SFrançois Tigeot * The above copyright notice and this permission notice shall be included in 12c59a5c48SFrançois Tigeot * all copies or substantial portions of the Software. 13c59a5c48SFrançois Tigeot * 14c59a5c48SFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c59a5c48SFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c59a5c48SFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c59a5c48SFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c59a5c48SFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c59a5c48SFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c59a5c48SFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 21c59a5c48SFrançois Tigeot */ 22c59a5c48SFrançois Tigeot 23c59a5c48SFrançois Tigeot #ifndef __AMD_SHARED_H__ 24c59a5c48SFrançois Tigeot #define __AMD_SHARED_H__ 25c59a5c48SFrançois Tigeot 26*b843c749SSergey Zigachev #include <drm/amd_asic_type.h> 27c59a5c48SFrançois Tigeot 28c59a5c48SFrançois Tigeot 29*b843c749SSergey Zigachev #define AMD_MAX_USEC_TIMEOUT 200000 /* 200 ms */ 30c59a5c48SFrançois Tigeot 31c59a5c48SFrançois Tigeot /* 32c59a5c48SFrançois Tigeot * Chip flags 33c59a5c48SFrançois Tigeot */ 34c59a5c48SFrançois Tigeot enum amd_chip_flags { 35c59a5c48SFrançois Tigeot AMD_ASIC_MASK = 0x0000ffffUL, 36c59a5c48SFrançois Tigeot AMD_FLAGS_MASK = 0xffff0000UL, 37c59a5c48SFrançois Tigeot AMD_IS_MOBILITY = 0x00010000UL, 38c59a5c48SFrançois Tigeot AMD_IS_APU = 0x00020000UL, 39c59a5c48SFrançois Tigeot AMD_IS_PX = 0x00040000UL, 40c59a5c48SFrançois Tigeot AMD_EXP_HW_SUPPORT = 0x00080000UL, 41c59a5c48SFrançois Tigeot }; 42c59a5c48SFrançois Tigeot 43c59a5c48SFrançois Tigeot enum amd_ip_block_type { 44c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_COMMON, 45c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_GMC, 46c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_IH, 47c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_SMC, 48*b843c749SSergey Zigachev AMD_IP_BLOCK_TYPE_PSP, 49c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_DCE, 50c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_GFX, 51c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_SDMA, 52c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_UVD, 53c59a5c48SFrançois Tigeot AMD_IP_BLOCK_TYPE_VCE, 54d78d3a22SFrançois Tigeot AMD_IP_BLOCK_TYPE_ACP, 55*b843c749SSergey Zigachev AMD_IP_BLOCK_TYPE_VCN 56c59a5c48SFrançois Tigeot }; 57c59a5c48SFrançois Tigeot 58c59a5c48SFrançois Tigeot enum amd_clockgating_state { 59c59a5c48SFrançois Tigeot AMD_CG_STATE_GATE = 0, 60c59a5c48SFrançois Tigeot AMD_CG_STATE_UNGATE, 61c59a5c48SFrançois Tigeot }; 62c59a5c48SFrançois Tigeot 63*b843c749SSergey Zigachev 64c59a5c48SFrançois Tigeot enum amd_powergating_state { 65c59a5c48SFrançois Tigeot AMD_PG_STATE_GATE = 0, 66c59a5c48SFrançois Tigeot AMD_PG_STATE_UNGATE, 67c59a5c48SFrançois Tigeot }; 68c59a5c48SFrançois Tigeot 69*b843c749SSergey Zigachev 70d78d3a22SFrançois Tigeot /* CG flags */ 71d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_MGCG (1 << 0) 72d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_MGLS (1 << 1) 73d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_CGCG (1 << 2) 74d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_CGLS (1 << 3) 75d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_CGTS (1 << 4) 76d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 77d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6) 78d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7) 79d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_MC_LS (1 << 8) 80d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_MC_MGCG (1 << 9) 81d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_SDMA_LS (1 << 10) 82d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11) 83d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_BIF_LS (1 << 12) 84d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_UVD_MGCG (1 << 13) 85d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_VCE_MGCG (1 << 14) 86d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_HDP_LS (1 << 15) 87d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_HDP_MGCG (1 << 16) 88d78d3a22SFrançois Tigeot #define AMD_CG_SUPPORT_ROM_MGCG (1 << 17) 89*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_DRM_LS (1 << 18) 90*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_BIF_MGCG (1 << 19) 91*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20) 92*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21) 93*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_DRM_MGCG (1 << 22) 94*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_DF_MGCG (1 << 23) 95*b843c749SSergey Zigachev #define AMD_CG_SUPPORT_VCN_MGCG (1 << 24) 96d78d3a22SFrançois Tigeot /* PG flags */ 97d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_GFX_PG (1 << 0) 98d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_GFX_SMG (1 << 1) 99d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_GFX_DMG (1 << 2) 100d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_UVD (1 << 3) 101d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_VCE (1 << 4) 102d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_CP (1 << 5) 103d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_GDS (1 << 6) 104d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7) 105d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_SDMA (1 << 8) 106d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_ACP (1 << 9) 107d78d3a22SFrançois Tigeot #define AMD_PG_SUPPORT_SAMU (1 << 10) 108*b843c749SSergey Zigachev #define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11) 109*b843c749SSergey Zigachev #define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12) 110*b843c749SSergey Zigachev #define AMD_PG_SUPPORT_MMHUB (1 << 13) 111*b843c749SSergey Zigachev #define AMD_PG_SUPPORT_VCN (1 << 14) 112d78d3a22SFrançois Tigeot 113*b843c749SSergey Zigachev enum PP_FEATURE_MASK { 114*b843c749SSergey Zigachev PP_SCLK_DPM_MASK = 0x1, 115*b843c749SSergey Zigachev PP_MCLK_DPM_MASK = 0x2, 116*b843c749SSergey Zigachev PP_PCIE_DPM_MASK = 0x4, 117*b843c749SSergey Zigachev PP_SCLK_DEEP_SLEEP_MASK = 0x8, 118*b843c749SSergey Zigachev PP_POWER_CONTAINMENT_MASK = 0x10, 119*b843c749SSergey Zigachev PP_UVD_HANDSHAKE_MASK = 0x20, 120*b843c749SSergey Zigachev PP_SMC_VOLTAGE_CONTROL_MASK = 0x40, 121*b843c749SSergey Zigachev PP_VBI_TIME_SUPPORT_MASK = 0x80, 122*b843c749SSergey Zigachev PP_ULV_MASK = 0x100, 123*b843c749SSergey Zigachev PP_ENABLE_GFX_CG_THRU_SMU = 0x200, 124*b843c749SSergey Zigachev PP_CLOCK_STRETCH_MASK = 0x400, 125*b843c749SSergey Zigachev PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800, 126*b843c749SSergey Zigachev PP_SOCCLK_DPM_MASK = 0x1000, 127*b843c749SSergey Zigachev PP_DCEFCLK_DPM_MASK = 0x2000, 128*b843c749SSergey Zigachev PP_OVERDRIVE_MASK = 0x4000, 129*b843c749SSergey Zigachev PP_GFXOFF_MASK = 0x8000, 130*b843c749SSergey Zigachev PP_ACG_MASK = 0x10000, 131*b843c749SSergey Zigachev PP_STUTTER_MODE = 0x20000, 132d78d3a22SFrançois Tigeot }; 133d78d3a22SFrançois Tigeot 134*b843c749SSergey Zigachev /** 135*b843c749SSergey Zigachev * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks 136*b843c749SSergey Zigachev */ 137c59a5c48SFrançois Tigeot struct amd_ip_funcs { 138*b843c749SSergey Zigachev /** @name: Name of IP block */ 139d78d3a22SFrançois Tigeot char *name; 140*b843c749SSergey Zigachev /** 141*b843c749SSergey Zigachev * @early_init: 142*b843c749SSergey Zigachev * 143*b843c749SSergey Zigachev * sets up early driver state (pre sw_init), 144*b843c749SSergey Zigachev * does not configure hw - Optional 145*b843c749SSergey Zigachev */ 146c59a5c48SFrançois Tigeot int (*early_init)(void *handle); 147*b843c749SSergey Zigachev /** @late_init: sets up late driver/hw state (post hw_init) - Optional */ 148c59a5c48SFrançois Tigeot int (*late_init)(void *handle); 149*b843c749SSergey Zigachev /** @sw_init: sets up driver state, does not configure hw */ 150c59a5c48SFrançois Tigeot int (*sw_init)(void *handle); 151*b843c749SSergey Zigachev /** @sw_fini: tears down driver state, does not configure hw */ 152c59a5c48SFrançois Tigeot int (*sw_fini)(void *handle); 153*b843c749SSergey Zigachev /** @hw_init: sets up the hw state */ 154c59a5c48SFrançois Tigeot int (*hw_init)(void *handle); 155*b843c749SSergey Zigachev /** @hw_fini: tears down the hw state */ 156c59a5c48SFrançois Tigeot int (*hw_fini)(void *handle); 157*b843c749SSergey Zigachev /** @late_fini: final cleanup */ 158d78d3a22SFrançois Tigeot void (*late_fini)(void *handle); 159*b843c749SSergey Zigachev /** @suspend: handles IP specific hw/sw changes for suspend */ 160c59a5c48SFrançois Tigeot int (*suspend)(void *handle); 161*b843c749SSergey Zigachev /** @resume: handles IP specific hw/sw changes for resume */ 162c59a5c48SFrançois Tigeot int (*resume)(void *handle); 163*b843c749SSergey Zigachev /** @is_idle: returns current IP block idle status */ 164c59a5c48SFrançois Tigeot bool (*is_idle)(void *handle); 165*b843c749SSergey Zigachev /** @wait_for_idle: poll for idle */ 166c59a5c48SFrançois Tigeot int (*wait_for_idle)(void *handle); 167*b843c749SSergey Zigachev /** @check_soft_reset: check soft reset the IP block */ 168*b843c749SSergey Zigachev bool (*check_soft_reset)(void *handle); 169*b843c749SSergey Zigachev /** @pre_soft_reset: pre soft reset the IP block */ 170*b843c749SSergey Zigachev int (*pre_soft_reset)(void *handle); 171*b843c749SSergey Zigachev /** @soft_reset: soft reset the IP block */ 172c59a5c48SFrançois Tigeot int (*soft_reset)(void *handle); 173*b843c749SSergey Zigachev /** @post_soft_reset: post soft reset the IP block */ 174*b843c749SSergey Zigachev int (*post_soft_reset)(void *handle); 175*b843c749SSergey Zigachev /** @set_clockgating_state: enable/disable cg for the IP block */ 176c59a5c48SFrançois Tigeot int (*set_clockgating_state)(void *handle, 177c59a5c48SFrançois Tigeot enum amd_clockgating_state state); 178*b843c749SSergey Zigachev /** @set_powergating_state: enable/disable pg for the IP block */ 179c59a5c48SFrançois Tigeot int (*set_powergating_state)(void *handle, 180c59a5c48SFrançois Tigeot enum amd_powergating_state state); 181*b843c749SSergey Zigachev /** @get_clockgating_state: get current clockgating status */ 182*b843c749SSergey Zigachev void (*get_clockgating_state)(void *handle, u32 *flags); 183c59a5c48SFrançois Tigeot }; 184c59a5c48SFrançois Tigeot 185*b843c749SSergey Zigachev 186c59a5c48SFrançois Tigeot #endif /* __AMD_SHARED_H__ */ 187