1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * 3*b843c749SSergey Zigachev * Copyright (C) 2016 Advanced Micro Devices, Inc. 4*b843c749SSergey Zigachev * 5*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 6*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 7*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 8*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 10*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 11*b843c749SSergey Zigachev * 12*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included 13*b843c749SSergey Zigachev * in all copies or substantial portions of the Software. 14*b843c749SSergey Zigachev * 15*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16*b843c749SSergey Zigachev * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19*b843c749SSergey Zigachev * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20*b843c749SSergey Zigachev * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev */ 22*b843c749SSergey Zigachev 23*b843c749SSergey Zigachev #ifndef BIF_3_0_D_H 24*b843c749SSergey Zigachev #define BIF_3_0_D_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C 27*b843c749SSergey Zigachev #define ixPB0_DFT_JIT_INJ_REG0 0x13000 28*b843c749SSergey Zigachev #define ixPB0_DFT_JIT_INJ_REG1 0x13004 29*b843c749SSergey Zigachev #define ixPB0_DFT_JIT_INJ_REG2 0x13008 30*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG0 0x10004 31*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG1 0x10008 32*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG2 0x1000C 33*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG3 0x10010 34*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG4 0x10014 35*b843c749SSergey Zigachev #define ixPB0_GLB_CTRL_REG5 0x10018 36*b843c749SSergey Zigachev #define ixPB0_GLB_OVRD_REG0 0x10030 37*b843c749SSergey Zigachev #define ixPB0_GLB_OVRD_REG1 0x10034 38*b843c749SSergey Zigachev #define ixPB0_GLB_OVRD_REG2 0x10038 39*b843c749SSergey Zigachev #define ixPB0_GLB_SCI_STAT_OVRD_REG0 0x1001C 40*b843c749SSergey Zigachev #define ixPB0_GLB_SCI_STAT_OVRD_REG1 0x10020 41*b843c749SSergey Zigachev #define ixPB0_GLB_SCI_STAT_OVRD_REG2 0x10024 42*b843c749SSergey Zigachev #define ixPB0_GLB_SCI_STAT_OVRD_REG3 0x10028 43*b843c749SSergey Zigachev #define ixPB0_GLB_SCI_STAT_OVRD_REG4 0x1002C 44*b843c749SSergey Zigachev #define ixPB0_HW_DEBUG 0x12004 45*b843c749SSergey Zigachev #define ixPB0_PIF_CNTL 0x0010 46*b843c749SSergey Zigachev #define ixPB0_PIF_CNTL2 0x0014 47*b843c749SSergey Zigachev #define ixPB0_PIF_HW_DEBUG 0x0002 48*b843c749SSergey Zigachev #define ixPB0_PIF_PAIRING 0x0011 49*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_0 0x0020 50*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_10 0x0032 51*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_1 0x0021 52*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_11 0x0033 53*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_12 0x0034 54*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_13 0x0035 55*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_14 0x0036 56*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_15 0x0037 57*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_2 0x0022 58*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_3 0x0023 59*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_4 0x0024 60*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_5 0x0025 61*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_6 0x0026 62*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_7 0x0027 63*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_8 0x0030 64*b843c749SSergey Zigachev #define ixPB0_PIF_PDNB_OVERRIDE_9 0x0031 65*b843c749SSergey Zigachev #define ixPB0_PIF_PWRDOWN_0 0x0012 66*b843c749SSergey Zigachev #define ixPB0_PIF_PWRDOWN_1 0x0013 67*b843c749SSergey Zigachev #define ixPB0_PIF_PWRDOWN_2 0x0017 68*b843c749SSergey Zigachev #define ixPB0_PIF_PWRDOWN_3 0x0018 69*b843c749SSergey Zigachev #define ixPB0_PIF_SC_CTL 0x0016 70*b843c749SSergey Zigachev #define ixPB0_PIF_SCRATCH 0x0001 71*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_0 0x0028 72*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_10 0x003A 73*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_1 0x0029 74*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_11 0x003B 75*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_12 0x003C 76*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_13 0x003D 77*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_14 0x003E 78*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_15 0x003F 79*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_2 0x002A 80*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_3 0x002B 81*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_4 0x002C 82*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_5 0x002D 83*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_6 0x002E 84*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_7 0x002F 85*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_8 0x0038 86*b843c749SSergey Zigachev #define ixPB0_PIF_SEQ_STATUS_9 0x0039 87*b843c749SSergey Zigachev #define ixPB0_PIF_TXPHYSTATUS 0x0015 88*b843c749SSergey Zigachev #define ixPB0_PLL_LC0_CTRL_REG0 0x14480 89*b843c749SSergey Zigachev #define ixPB0_PLL_LC0_OVRD_REG0 0x14490 90*b843c749SSergey Zigachev #define ixPB0_PLL_LC0_OVRD_REG1 0x14494 91*b843c749SSergey Zigachev #define ixPB0_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 92*b843c749SSergey Zigachev #define ixPB0_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 93*b843c749SSergey Zigachev #define ixPB0_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 94*b843c749SSergey Zigachev #define ixPB0_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 95*b843c749SSergey Zigachev #define ixPB0_PLL_RO0_CTRL_REG0 0x14440 96*b843c749SSergey Zigachev #define ixPB0_PLL_RO0_OVRD_REG0 0x14450 97*b843c749SSergey Zigachev #define ixPB0_PLL_RO0_OVRD_REG1 0x14454 98*b843c749SSergey Zigachev #define ixPB0_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 99*b843c749SSergey Zigachev #define ixPB0_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 100*b843c749SSergey Zigachev #define ixPB0_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 101*b843c749SSergey Zigachev #define ixPB0_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 102*b843c749SSergey Zigachev #define ixPB0_PLL_RO_GLB_CTRL_REG0 0x14000 103*b843c749SSergey Zigachev #define ixPB0_PLL_RO_GLB_OVRD_REG0 0x14010 104*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG0 0x16000 105*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG1 0x16004 106*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG2 0x16008 107*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG3 0x1600C 108*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG4 0x16010 109*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG5 0x16014 110*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG6 0x16018 111*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG7 0x1601C 112*b843c749SSergey Zigachev #define ixPB0_RX_GLB_CTRL_REG8 0x16020 113*b843c749SSergey Zigachev #define ixPB0_RX_GLB_OVRD_REG0 0x16030 114*b843c749SSergey Zigachev #define ixPB0_RX_GLB_OVRD_REG1 0x16034 115*b843c749SSergey Zigachev #define ixPB0_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 116*b843c749SSergey Zigachev #define ixPB0_RX_LANE0_CTRL_REG0 0x16440 117*b843c749SSergey Zigachev #define ixPB0_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 118*b843c749SSergey Zigachev #define ixPB0_RX_LANE10_CTRL_REG0 0x17500 119*b843c749SSergey Zigachev #define ixPB0_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 120*b843c749SSergey Zigachev #define ixPB0_RX_LANE11_CTRL_REG0 0x17600 121*b843c749SSergey Zigachev #define ixPB0_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 122*b843c749SSergey Zigachev #define ixPB0_RX_LANE12_CTRL_REG0 0x17840 123*b843c749SSergey Zigachev #define ixPB0_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 124*b843c749SSergey Zigachev #define ixPB0_RX_LANE13_CTRL_REG0 0x17880 125*b843c749SSergey Zigachev #define ixPB0_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 126*b843c749SSergey Zigachev #define ixPB0_RX_LANE14_CTRL_REG0 0x17900 127*b843c749SSergey Zigachev #define ixPB0_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 128*b843c749SSergey Zigachev #define ixPB0_RX_LANE15_CTRL_REG0 0x17A00 129*b843c749SSergey Zigachev #define ixPB0_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 130*b843c749SSergey Zigachev #define ixPB0_RX_LANE1_CTRL_REG0 0x16480 131*b843c749SSergey Zigachev #define ixPB0_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 132*b843c749SSergey Zigachev #define ixPB0_RX_LANE2_CTRL_REG0 0x16500 133*b843c749SSergey Zigachev #define ixPB0_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 134*b843c749SSergey Zigachev #define ixPB0_RX_LANE3_CTRL_REG0 0x16600 135*b843c749SSergey Zigachev #define ixPB0_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 136*b843c749SSergey Zigachev #define ixPB0_RX_LANE4_CTRL_REG0 0x16800 137*b843c749SSergey Zigachev #define ixPB0_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 138*b843c749SSergey Zigachev #define ixPB0_RX_LANE5_CTRL_REG0 0x16880 139*b843c749SSergey Zigachev #define ixPB0_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 140*b843c749SSergey Zigachev #define ixPB0_RX_LANE6_CTRL_REG0 0x16900 141*b843c749SSergey Zigachev #define ixPB0_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 142*b843c749SSergey Zigachev #define ixPB0_RX_LANE7_CTRL_REG0 0x16A00 143*b843c749SSergey Zigachev #define ixPB0_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 144*b843c749SSergey Zigachev #define ixPB0_RX_LANE8_CTRL_REG0 0x17440 145*b843c749SSergey Zigachev #define ixPB0_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 146*b843c749SSergey Zigachev #define ixPB0_RX_LANE9_CTRL_REG0 0x17480 147*b843c749SSergey Zigachev #define ixPB0_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 148*b843c749SSergey Zigachev #define ixPB0_STRAP_GLB_REG0 0x12020 149*b843c749SSergey Zigachev #define ixPB0_STRAP_PLL_REG0 0x12030 150*b843c749SSergey Zigachev #define ixPB0_STRAP_RX_REG0 0x12028 151*b843c749SSergey Zigachev #define ixPB0_STRAP_RX_REG1 0x1202C 152*b843c749SSergey Zigachev #define ixPB0_STRAP_TX_REG0 0x12024 153*b843c749SSergey Zigachev #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 154*b843c749SSergey Zigachev #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 155*b843c749SSergey Zigachev #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 156*b843c749SSergey Zigachev #define ixPB0_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 157*b843c749SSergey Zigachev #define ixPB0_TX_GLB_CTRL_REG0 0x18000 158*b843c749SSergey Zigachev #define ixPB0_TX_GLB_LANE_SKEW_CTRL 0x18004 159*b843c749SSergey Zigachev #define ixPB0_TX_GLB_OVRD_REG0 0x18030 160*b843c749SSergey Zigachev #define ixPB0_TX_GLB_OVRD_REG1 0x18034 161*b843c749SSergey Zigachev #define ixPB0_TX_GLB_OVRD_REG2 0x18038 162*b843c749SSergey Zigachev #define ixPB0_TX_GLB_OVRD_REG3 0x1803C 163*b843c749SSergey Zigachev #define ixPB0_TX_GLB_OVRD_REG4 0x18040 164*b843c749SSergey Zigachev #define ixPB0_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 165*b843c749SSergey Zigachev #define ixPB0_TX_LANE0_CTRL_REG0 0x18440 166*b843c749SSergey Zigachev #define ixPB0_TX_LANE0_OVRD_REG0 0x18444 167*b843c749SSergey Zigachev #define ixPB0_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 168*b843c749SSergey Zigachev #define ixPB0_TX_LANE10_CTRL_REG0 0x19500 169*b843c749SSergey Zigachev #define ixPB0_TX_LANE10_OVRD_REG0 0x19504 170*b843c749SSergey Zigachev #define ixPB0_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 171*b843c749SSergey Zigachev #define ixPB0_TX_LANE11_CTRL_REG0 0x19600 172*b843c749SSergey Zigachev #define ixPB0_TX_LANE11_OVRD_REG0 0x19604 173*b843c749SSergey Zigachev #define ixPB0_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 174*b843c749SSergey Zigachev #define ixPB0_TX_LANE12_CTRL_REG0 0x19840 175*b843c749SSergey Zigachev #define ixPB0_TX_LANE12_OVRD_REG0 0x19844 176*b843c749SSergey Zigachev #define ixPB0_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 177*b843c749SSergey Zigachev #define ixPB0_TX_LANE13_CTRL_REG0 0x19880 178*b843c749SSergey Zigachev #define ixPB0_TX_LANE13_OVRD_REG0 0x19884 179*b843c749SSergey Zigachev #define ixPB0_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 180*b843c749SSergey Zigachev #define ixPB0_TX_LANE14_CTRL_REG0 0x19900 181*b843c749SSergey Zigachev #define ixPB0_TX_LANE14_OVRD_REG0 0x19904 182*b843c749SSergey Zigachev #define ixPB0_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 183*b843c749SSergey Zigachev #define ixPB0_TX_LANE15_CTRL_REG0 0x19A00 184*b843c749SSergey Zigachev #define ixPB0_TX_LANE15_OVRD_REG0 0x19A04 185*b843c749SSergey Zigachev #define ixPB0_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 186*b843c749SSergey Zigachev #define ixPB0_TX_LANE1_CTRL_REG0 0x18480 187*b843c749SSergey Zigachev #define ixPB0_TX_LANE1_OVRD_REG0 0x18484 188*b843c749SSergey Zigachev #define ixPB0_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 189*b843c749SSergey Zigachev #define ixPB0_TX_LANE2_CTRL_REG0 0x18500 190*b843c749SSergey Zigachev #define ixPB0_TX_LANE2_OVRD_REG0 0x18504 191*b843c749SSergey Zigachev #define ixPB0_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 192*b843c749SSergey Zigachev #define ixPB0_TX_LANE3_CTRL_REG0 0x18600 193*b843c749SSergey Zigachev #define ixPB0_TX_LANE3_OVRD_REG0 0x18604 194*b843c749SSergey Zigachev #define ixPB0_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 195*b843c749SSergey Zigachev #define ixPB0_TX_LANE4_CTRL_REG0 0x18840 196*b843c749SSergey Zigachev #define ixPB0_TX_LANE4_OVRD_REG0 0x18844 197*b843c749SSergey Zigachev #define ixPB0_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 198*b843c749SSergey Zigachev #define ixPB0_TX_LANE5_CTRL_REG0 0x18880 199*b843c749SSergey Zigachev #define ixPB0_TX_LANE5_OVRD_REG0 0x18884 200*b843c749SSergey Zigachev #define ixPB0_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 201*b843c749SSergey Zigachev #define ixPB0_TX_LANE6_CTRL_REG0 0x18900 202*b843c749SSergey Zigachev #define ixPB0_TX_LANE6_OVRD_REG0 0x18904 203*b843c749SSergey Zigachev #define ixPB0_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 204*b843c749SSergey Zigachev #define ixPB0_TX_LANE7_CTRL_REG0 0x18A00 205*b843c749SSergey Zigachev #define ixPB0_TX_LANE7_OVRD_REG0 0x18A04 206*b843c749SSergey Zigachev #define ixPB0_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 207*b843c749SSergey Zigachev #define ixPB0_TX_LANE8_CTRL_REG0 0x19440 208*b843c749SSergey Zigachev #define ixPB0_TX_LANE8_OVRD_REG0 0x19444 209*b843c749SSergey Zigachev #define ixPB0_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 210*b843c749SSergey Zigachev #define ixPB0_TX_LANE9_CTRL_REG0 0x19480 211*b843c749SSergey Zigachev #define ixPB0_TX_LANE9_OVRD_REG0 0x19484 212*b843c749SSergey Zigachev #define ixPB0_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 213*b843c749SSergey Zigachev #define ixPB1_DFT_DEBUG_CTRL_REG0 0x1300C 214*b843c749SSergey Zigachev #define ixPB1_DFT_JIT_INJ_REG0 0x13000 215*b843c749SSergey Zigachev #define ixPB1_DFT_JIT_INJ_REG1 0x13004 216*b843c749SSergey Zigachev #define ixPB1_DFT_JIT_INJ_REG2 0x13008 217*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG0 0x10004 218*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG1 0x10008 219*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG2 0x1000C 220*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG3 0x10010 221*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG4 0x10014 222*b843c749SSergey Zigachev #define ixPB1_GLB_CTRL_REG5 0x10018 223*b843c749SSergey Zigachev #define ixPB1_GLB_OVRD_REG0 0x10030 224*b843c749SSergey Zigachev #define ixPB1_GLB_OVRD_REG1 0x10034 225*b843c749SSergey Zigachev #define ixPB1_GLB_OVRD_REG2 0x10038 226*b843c749SSergey Zigachev #define ixPB1_GLB_SCI_STAT_OVRD_REG0 0x1001C 227*b843c749SSergey Zigachev #define ixPB1_GLB_SCI_STAT_OVRD_REG1 0x10020 228*b843c749SSergey Zigachev #define ixPB1_GLB_SCI_STAT_OVRD_REG2 0x10024 229*b843c749SSergey Zigachev #define ixPB1_GLB_SCI_STAT_OVRD_REG3 0x10028 230*b843c749SSergey Zigachev #define ixPB1_GLB_SCI_STAT_OVRD_REG4 0x1002C 231*b843c749SSergey Zigachev #define ixPB1_HW_DEBUG 0x12004 232*b843c749SSergey Zigachev #define ixPB1_PIF_CNTL 0x0010 233*b843c749SSergey Zigachev #define ixPB1_PIF_CNTL2 0x0014 234*b843c749SSergey Zigachev #define ixPB1_PIF_HW_DEBUG 0x0002 235*b843c749SSergey Zigachev #define ixPB1_PIF_PAIRING 0x0011 236*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_0 0x0020 237*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_10 0x0032 238*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_1 0x0021 239*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_11 0x0033 240*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_12 0x0034 241*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_13 0x0035 242*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_14 0x0036 243*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_15 0x0037 244*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_2 0x0022 245*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_3 0x0023 246*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_4 0x0024 247*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_5 0x0025 248*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_6 0x0026 249*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_7 0x0027 250*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_8 0x0030 251*b843c749SSergey Zigachev #define ixPB1_PIF_PDNB_OVERRIDE_9 0x0031 252*b843c749SSergey Zigachev #define ixPB1_PIF_PWRDOWN_0 0x0012 253*b843c749SSergey Zigachev #define ixPB1_PIF_PWRDOWN_1 0x0013 254*b843c749SSergey Zigachev #define ixPB1_PIF_PWRDOWN_2 0x0017 255*b843c749SSergey Zigachev #define ixPB1_PIF_PWRDOWN_3 0x0018 256*b843c749SSergey Zigachev #define ixPB1_PIF_SC_CTL 0x0016 257*b843c749SSergey Zigachev #define ixPB1_PIF_SCRATCH 0x0001 258*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_0 0x0028 259*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_10 0x003A 260*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_1 0x0029 261*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_11 0x003B 262*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_12 0x003C 263*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_13 0x003D 264*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_14 0x003E 265*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_15 0x003F 266*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_2 0x002A 267*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_3 0x002B 268*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_4 0x002C 269*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_5 0x002D 270*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_6 0x002E 271*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_7 0x002F 272*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_8 0x0038 273*b843c749SSergey Zigachev #define ixPB1_PIF_SEQ_STATUS_9 0x0039 274*b843c749SSergey Zigachev #define ixPB1_PIF_TXPHYSTATUS 0x0015 275*b843c749SSergey Zigachev #define ixPB1_PLL_LC0_CTRL_REG0 0x14480 276*b843c749SSergey Zigachev #define ixPB1_PLL_LC0_OVRD_REG0 0x14490 277*b843c749SSergey Zigachev #define ixPB1_PLL_LC0_OVRD_REG1 0x14494 278*b843c749SSergey Zigachev #define ixPB1_PLL_LC0_SCI_STAT_OVRD_REG0 0x14500 279*b843c749SSergey Zigachev #define ixPB1_PLL_LC1_SCI_STAT_OVRD_REG0 0x14504 280*b843c749SSergey Zigachev #define ixPB1_PLL_LC2_SCI_STAT_OVRD_REG0 0x14508 281*b843c749SSergey Zigachev #define ixPB1_PLL_LC3_SCI_STAT_OVRD_REG0 0x1450C 282*b843c749SSergey Zigachev #define ixPB1_PLL_RO0_CTRL_REG0 0x14440 283*b843c749SSergey Zigachev #define ixPB1_PLL_RO0_OVRD_REG0 0x14450 284*b843c749SSergey Zigachev #define ixPB1_PLL_RO0_OVRD_REG1 0x14454 285*b843c749SSergey Zigachev #define ixPB1_PLL_RO0_SCI_STAT_OVRD_REG0 0x14460 286*b843c749SSergey Zigachev #define ixPB1_PLL_RO1_SCI_STAT_OVRD_REG0 0x14464 287*b843c749SSergey Zigachev #define ixPB1_PLL_RO2_SCI_STAT_OVRD_REG0 0x14468 288*b843c749SSergey Zigachev #define ixPB1_PLL_RO3_SCI_STAT_OVRD_REG0 0x1446C 289*b843c749SSergey Zigachev #define ixPB1_PLL_RO_GLB_CTRL_REG0 0x14000 290*b843c749SSergey Zigachev #define ixPB1_PLL_RO_GLB_OVRD_REG0 0x14010 291*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG0 0x16000 292*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG1 0x16004 293*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG2 0x16008 294*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG3 0x1600C 295*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG4 0x16010 296*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG5 0x16014 297*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG6 0x16018 298*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG7 0x1601C 299*b843c749SSergey Zigachev #define ixPB1_RX_GLB_CTRL_REG8 0x16020 300*b843c749SSergey Zigachev #define ixPB1_RX_GLB_OVRD_REG0 0x16030 301*b843c749SSergey Zigachev #define ixPB1_RX_GLB_OVRD_REG1 0x16034 302*b843c749SSergey Zigachev #define ixPB1_RX_GLB_SCI_STAT_OVRD_REG0 0x16028 303*b843c749SSergey Zigachev #define ixPB1_RX_LANE0_CTRL_REG0 0x16440 304*b843c749SSergey Zigachev #define ixPB1_RX_LANE0_SCI_STAT_OVRD_REG0 0x16448 305*b843c749SSergey Zigachev #define ixPB1_RX_LANE10_CTRL_REG0 0x17500 306*b843c749SSergey Zigachev #define ixPB1_RX_LANE10_SCI_STAT_OVRD_REG0 0x17508 307*b843c749SSergey Zigachev #define ixPB1_RX_LANE11_CTRL_REG0 0x17600 308*b843c749SSergey Zigachev #define ixPB1_RX_LANE11_SCI_STAT_OVRD_REG0 0x17608 309*b843c749SSergey Zigachev #define ixPB1_RX_LANE12_CTRL_REG0 0x17840 310*b843c749SSergey Zigachev #define ixPB1_RX_LANE12_SCI_STAT_OVRD_REG0 0x17848 311*b843c749SSergey Zigachev #define ixPB1_RX_LANE13_CTRL_REG0 0x17880 312*b843c749SSergey Zigachev #define ixPB1_RX_LANE13_SCI_STAT_OVRD_REG0 0x17888 313*b843c749SSergey Zigachev #define ixPB1_RX_LANE14_CTRL_REG0 0x17900 314*b843c749SSergey Zigachev #define ixPB1_RX_LANE14_SCI_STAT_OVRD_REG0 0x17908 315*b843c749SSergey Zigachev #define ixPB1_RX_LANE15_CTRL_REG0 0x17A00 316*b843c749SSergey Zigachev #define ixPB1_RX_LANE15_SCI_STAT_OVRD_REG0 0x17A08 317*b843c749SSergey Zigachev #define ixPB1_RX_LANE1_CTRL_REG0 0x16480 318*b843c749SSergey Zigachev #define ixPB1_RX_LANE1_SCI_STAT_OVRD_REG0 0x16488 319*b843c749SSergey Zigachev #define ixPB1_RX_LANE2_CTRL_REG0 0x16500 320*b843c749SSergey Zigachev #define ixPB1_RX_LANE2_SCI_STAT_OVRD_REG0 0x16508 321*b843c749SSergey Zigachev #define ixPB1_RX_LANE3_CTRL_REG0 0x16600 322*b843c749SSergey Zigachev #define ixPB1_RX_LANE3_SCI_STAT_OVRD_REG0 0x16608 323*b843c749SSergey Zigachev #define ixPB1_RX_LANE4_CTRL_REG0 0x16800 324*b843c749SSergey Zigachev #define ixPB1_RX_LANE4_SCI_STAT_OVRD_REG0 0x16848 325*b843c749SSergey Zigachev #define ixPB1_RX_LANE5_CTRL_REG0 0x16880 326*b843c749SSergey Zigachev #define ixPB1_RX_LANE5_SCI_STAT_OVRD_REG0 0x16888 327*b843c749SSergey Zigachev #define ixPB1_RX_LANE6_CTRL_REG0 0x16900 328*b843c749SSergey Zigachev #define ixPB1_RX_LANE6_SCI_STAT_OVRD_REG0 0x16908 329*b843c749SSergey Zigachev #define ixPB1_RX_LANE7_CTRL_REG0 0x16A00 330*b843c749SSergey Zigachev #define ixPB1_RX_LANE7_SCI_STAT_OVRD_REG0 0x16A08 331*b843c749SSergey Zigachev #define ixPB1_RX_LANE8_CTRL_REG0 0x17440 332*b843c749SSergey Zigachev #define ixPB1_RX_LANE8_SCI_STAT_OVRD_REG0 0x17448 333*b843c749SSergey Zigachev #define ixPB1_RX_LANE9_CTRL_REG0 0x17480 334*b843c749SSergey Zigachev #define ixPB1_RX_LANE9_SCI_STAT_OVRD_REG0 0x17488 335*b843c749SSergey Zigachev #define ixPB1_STRAP_GLB_REG0 0x12020 336*b843c749SSergey Zigachev #define ixPB1_STRAP_PLL_REG0 0x12030 337*b843c749SSergey Zigachev #define ixPB1_STRAP_RX_REG0 0x12028 338*b843c749SSergey Zigachev #define ixPB1_STRAP_RX_REG1 0x1202C 339*b843c749SSergey Zigachev #define ixPB1_STRAP_TX_REG0 0x12024 340*b843c749SSergey Zigachev #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG0 0x18014 341*b843c749SSergey Zigachev #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG1 0x18018 342*b843c749SSergey Zigachev #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG2 0x1801C 343*b843c749SSergey Zigachev #define ixPB1_TX_GLB_COEFF_ACCEPT_TABLE_REG3 0x18020 344*b843c749SSergey Zigachev #define ixPB1_TX_GLB_CTRL_REG0 0x18000 345*b843c749SSergey Zigachev #define ixPB1_TX_GLB_LANE_SKEW_CTRL 0x18004 346*b843c749SSergey Zigachev #define ixPB1_TX_GLB_OVRD_REG0 0x18030 347*b843c749SSergey Zigachev #define ixPB1_TX_GLB_OVRD_REG1 0x18034 348*b843c749SSergey Zigachev #define ixPB1_TX_GLB_OVRD_REG2 0x18038 349*b843c749SSergey Zigachev #define ixPB1_TX_GLB_OVRD_REG3 0x1803C 350*b843c749SSergey Zigachev #define ixPB1_TX_GLB_OVRD_REG4 0x18040 351*b843c749SSergey Zigachev #define ixPB1_TX_GLB_SCI_STAT_OVRD_REG0 0x18010 352*b843c749SSergey Zigachev #define ixPB1_TX_LANE0_CTRL_REG0 0x18440 353*b843c749SSergey Zigachev #define ixPB1_TX_LANE0_OVRD_REG0 0x18444 354*b843c749SSergey Zigachev #define ixPB1_TX_LANE0_SCI_STAT_OVRD_REG0 0x18448 355*b843c749SSergey Zigachev #define ixPB1_TX_LANE10_CTRL_REG0 0x19500 356*b843c749SSergey Zigachev #define ixPB1_TX_LANE10_OVRD_REG0 0x19504 357*b843c749SSergey Zigachev #define ixPB1_TX_LANE10_SCI_STAT_OVRD_REG0 0x19508 358*b843c749SSergey Zigachev #define ixPB1_TX_LANE11_CTRL_REG0 0x19600 359*b843c749SSergey Zigachev #define ixPB1_TX_LANE11_OVRD_REG0 0x19604 360*b843c749SSergey Zigachev #define ixPB1_TX_LANE11_SCI_STAT_OVRD_REG0 0x19608 361*b843c749SSergey Zigachev #define ixPB1_TX_LANE12_CTRL_REG0 0x19840 362*b843c749SSergey Zigachev #define ixPB1_TX_LANE12_OVRD_REG0 0x19844 363*b843c749SSergey Zigachev #define ixPB1_TX_LANE12_SCI_STAT_OVRD_REG0 0x19848 364*b843c749SSergey Zigachev #define ixPB1_TX_LANE13_CTRL_REG0 0x19880 365*b843c749SSergey Zigachev #define ixPB1_TX_LANE13_OVRD_REG0 0x19884 366*b843c749SSergey Zigachev #define ixPB1_TX_LANE13_SCI_STAT_OVRD_REG0 0x19888 367*b843c749SSergey Zigachev #define ixPB1_TX_LANE14_CTRL_REG0 0x19900 368*b843c749SSergey Zigachev #define ixPB1_TX_LANE14_OVRD_REG0 0x19904 369*b843c749SSergey Zigachev #define ixPB1_TX_LANE14_SCI_STAT_OVRD_REG0 0x19908 370*b843c749SSergey Zigachev #define ixPB1_TX_LANE15_CTRL_REG0 0x19A00 371*b843c749SSergey Zigachev #define ixPB1_TX_LANE15_OVRD_REG0 0x19A04 372*b843c749SSergey Zigachev #define ixPB1_TX_LANE15_SCI_STAT_OVRD_REG0 0x19A08 373*b843c749SSergey Zigachev #define ixPB1_TX_LANE1_CTRL_REG0 0x18480 374*b843c749SSergey Zigachev #define ixPB1_TX_LANE1_OVRD_REG0 0x18484 375*b843c749SSergey Zigachev #define ixPB1_TX_LANE1_SCI_STAT_OVRD_REG0 0x18488 376*b843c749SSergey Zigachev #define ixPB1_TX_LANE2_CTRL_REG0 0x18500 377*b843c749SSergey Zigachev #define ixPB1_TX_LANE2_OVRD_REG0 0x18504 378*b843c749SSergey Zigachev #define ixPB1_TX_LANE2_SCI_STAT_OVRD_REG0 0x18508 379*b843c749SSergey Zigachev #define ixPB1_TX_LANE3_CTRL_REG0 0x18600 380*b843c749SSergey Zigachev #define ixPB1_TX_LANE3_OVRD_REG0 0x18604 381*b843c749SSergey Zigachev #define ixPB1_TX_LANE3_SCI_STAT_OVRD_REG0 0x18608 382*b843c749SSergey Zigachev #define ixPB1_TX_LANE4_CTRL_REG0 0x18840 383*b843c749SSergey Zigachev #define ixPB1_TX_LANE4_OVRD_REG0 0x18844 384*b843c749SSergey Zigachev #define ixPB1_TX_LANE4_SCI_STAT_OVRD_REG0 0x18848 385*b843c749SSergey Zigachev #define ixPB1_TX_LANE5_CTRL_REG0 0x18880 386*b843c749SSergey Zigachev #define ixPB1_TX_LANE5_OVRD_REG0 0x18884 387*b843c749SSergey Zigachev #define ixPB1_TX_LANE5_SCI_STAT_OVRD_REG0 0x18888 388*b843c749SSergey Zigachev #define ixPB1_TX_LANE6_CTRL_REG0 0x18900 389*b843c749SSergey Zigachev #define ixPB1_TX_LANE6_OVRD_REG0 0x18904 390*b843c749SSergey Zigachev #define ixPB1_TX_LANE6_SCI_STAT_OVRD_REG0 0x18908 391*b843c749SSergey Zigachev #define ixPB1_TX_LANE7_CTRL_REG0 0x18A00 392*b843c749SSergey Zigachev #define ixPB1_TX_LANE7_OVRD_REG0 0x18A04 393*b843c749SSergey Zigachev #define ixPB1_TX_LANE7_SCI_STAT_OVRD_REG0 0x18A08 394*b843c749SSergey Zigachev #define ixPB1_TX_LANE8_CTRL_REG0 0x19440 395*b843c749SSergey Zigachev #define ixPB1_TX_LANE8_OVRD_REG0 0x19444 396*b843c749SSergey Zigachev #define ixPB1_TX_LANE8_SCI_STAT_OVRD_REG0 0x19448 397*b843c749SSergey Zigachev #define ixPB1_TX_LANE9_CTRL_REG0 0x19480 398*b843c749SSergey Zigachev #define ixPB1_TX_LANE9_OVRD_REG0 0x19484 399*b843c749SSergey Zigachev #define ixPB1_TX_LANE9_SCI_STAT_OVRD_REG0 0x19488 400*b843c749SSergey Zigachev #define ixPCIE_BUS_CNTL 0x0021 401*b843c749SSergey Zigachev #define ixPCIE_CFG_CNTL 0x003C 402*b843c749SSergey Zigachev #define ixPCIE_CI_CNTL 0x0020 403*b843c749SSergey Zigachev #define ixPCIE_CNTL 0x0010 404*b843c749SSergey Zigachev #define ixPCIE_CNTL2 0x001C 405*b843c749SSergey Zigachev #define ixPCIE_CONFIG_CNTL 0x0011 406*b843c749SSergey Zigachev #define ixPCIE_DEBUG_CNTL 0x0012 407*b843c749SSergey Zigachev #define ixPCIE_ERR_CNTL 0x006A 408*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_CAP 0x00E0 409*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_CNTL 0x00E5 410*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_LATENCY_INDICATOR 0x00E4 411*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x00E7 412*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x00E8 413*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x00E9 414*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x00EA 415*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x00EB 416*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x00EC 417*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x00ED 418*b843c749SSergey Zigachev #define ixPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x00EE 419*b843c749SSergey Zigachev #define ixPCIE_FC_CPL 0x0062 420*b843c749SSergey Zigachev #define ixPCIE_FC_NP 0x0061 421*b843c749SSergey Zigachev #define ixPCIE_FC_P 0x0060 422*b843c749SSergey Zigachev #define ixPCIE_HW_DEBUG 0x0002 423*b843c749SSergey Zigachev #define ixPCIE_I2C_REG_ADDR_EXPAND 0x003A 424*b843c749SSergey Zigachev #define ixPCIE_I2C_REG_DATA 0x003B 425*b843c749SSergey Zigachev #define ixPCIE_INT_CNTL 0x001A 426*b843c749SSergey Zigachev #define ixPCIE_INT_STATUS 0x001B 427*b843c749SSergey Zigachev #define ixPCIE_LC_BEST_EQ_SETTINGS 0x00B9 428*b843c749SSergey Zigachev #define ixPCIE_LC_BW_CHANGE_CNTL 0x00B2 429*b843c749SSergey Zigachev #define ixPCIE_LC_CDR_CNTL 0x00B3 430*b843c749SSergey Zigachev #define ixPCIE_LC_CNTL 0x00A0 431*b843c749SSergey Zigachev #define ixPCIE_LC_CNTL2 0x00B1 432*b843c749SSergey Zigachev #define ixPCIE_LC_CNTL3 0x00B5 433*b843c749SSergey Zigachev #define ixPCIE_LC_CNTL4 0x00B6 434*b843c749SSergey Zigachev #define ixPCIE_LC_CNTL5 0x00B7 435*b843c749SSergey Zigachev #define ixPCIE_LC_FORCE_COEFF 0x00B8 436*b843c749SSergey Zigachev #define ixPCIE_LC_FORCE_EQ_REQ_COEFF 0x00BA 437*b843c749SSergey Zigachev #define ixPCIE_LC_LANE_CNTL 0x00B4 438*b843c749SSergey Zigachev #define ixPCIE_LC_LINK_WIDTH_CNTL 0x00A2 439*b843c749SSergey Zigachev #define ixPCIE_LC_N_FTS_CNTL 0x00A3 440*b843c749SSergey Zigachev #define ixPCIE_LC_SPEED_CNTL 0x00A4 441*b843c749SSergey Zigachev #define ixPCIE_LC_STATE0 0x00A5 442*b843c749SSergey Zigachev #define ixPCIE_LC_STATE10 0x0026 443*b843c749SSergey Zigachev #define ixPCIE_LC_STATE1 0x00A6 444*b843c749SSergey Zigachev #define ixPCIE_LC_STATE11 0x0027 445*b843c749SSergey Zigachev #define ixPCIE_LC_STATE2 0x00A7 446*b843c749SSergey Zigachev #define ixPCIE_LC_STATE3 0x00A8 447*b843c749SSergey Zigachev #define ixPCIE_LC_STATE4 0x00A9 448*b843c749SSergey Zigachev #define ixPCIE_LC_STATE5 0x00AA 449*b843c749SSergey Zigachev #define ixPCIE_LC_STATE6 0x0022 450*b843c749SSergey Zigachev #define ixPCIE_LC_STATE7 0x0023 451*b843c749SSergey Zigachev #define ixPCIE_LC_STATE8 0x0024 452*b843c749SSergey Zigachev #define ixPCIE_LC_STATE9 0x0025 453*b843c749SSergey Zigachev #define ixPCIE_LC_STATUS1 0x0028 454*b843c749SSergey Zigachev #define ixPCIE_LC_STATUS2 0x0029 455*b843c749SSergey Zigachev #define ixPCIE_LC_TRAINING_CNTL 0x00A1 456*b843c749SSergey Zigachev #define ixPCIE_P_BUF_STATUS 0x0041 457*b843c749SSergey Zigachev #define ixPCIE_P_CNTL 0x0040 458*b843c749SSergey Zigachev #define ixPCIE_P_DECODER_STATUS 0x0042 459*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x0093 460*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x0094 461*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_MST_C_CLK 0x0087 462*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_MST_R_CLK 0x0084 463*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_SLV_NS_C_CLK 0x0090 464*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_SLV_R_CLK 0x008A 465*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_SLV_S_C_CLK 0x008D 466*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_TXCLK 0x0081 467*b843c749SSergey Zigachev #define ixPCIE_PERF_CNTL_TXCLK2 0x0095 468*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_MST_C_CLK 0x0088 469*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_MST_R_CLK 0x0085 470*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x0091 471*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_SLV_R_CLK 0x008B 472*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_SLV_S_C_CLK 0x008E 473*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_TXCLK 0x0082 474*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT0_TXCLK2 0x0096 475*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_MST_C_CLK 0x0089 476*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_MST_R_CLK 0x0086 477*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x0092 478*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_SLV_R_CLK 0x008C 479*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_SLV_S_C_CLK 0x008F 480*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_TXCLK 0x0083 481*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT1_TXCLK2 0x0097 482*b843c749SSergey Zigachev #define ixPCIE_PERF_COUNT_CNTL 0x0080 483*b843c749SSergey Zigachev #define ixPCIEP_HW_DEBUG 0x0002 484*b843c749SSergey Zigachev #define ixPCIE_P_MISC_STATUS 0x0043 485*b843c749SSergey Zigachev #define ixPCIEP_PORT_CNTL 0x0010 486*b843c749SSergey Zigachev #define ixPCIE_P_PORT_LANE_STATUS 0x0050 487*b843c749SSergey Zigachev #define ixPCIE_PRBS_CLR 0x00C8 488*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_0 0x00D0 489*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_10 0x00DA 490*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_1 0x00D1 491*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_11 0x00DB 492*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_12 0x00DC 493*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_13 0x00DD 494*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_14 0x00DE 495*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_15 0x00DF 496*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_2 0x00D2 497*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_3 0x00D3 498*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_4 0x00D4 499*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_5 0x00D5 500*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_6 0x00D6 501*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_7 0x00D7 502*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_8 0x00D8 503*b843c749SSergey Zigachev #define ixPCIE_PRBS_ERRCNT_9 0x00D9 504*b843c749SSergey Zigachev #define ixPCIE_PRBS_FREERUN 0x00CB 505*b843c749SSergey Zigachev #define ixPCIE_PRBS_HI_BITCNT 0x00CF 506*b843c749SSergey Zigachev #define ixPCIE_PRBS_LO_BITCNT 0x00CE 507*b843c749SSergey Zigachev #define ixPCIE_PRBS_MISC 0x00CC 508*b843c749SSergey Zigachev #define ixPCIE_PRBS_STATUS1 0x00C9 509*b843c749SSergey Zigachev #define ixPCIE_PRBS_STATUS2 0x00CA 510*b843c749SSergey Zigachev #define ixPCIE_PRBS_USER_PATTERN 0x00CD 511*b843c749SSergey Zigachev #define ixPCIE_P_RCV_L0S_FTS_DET 0x0050 512*b843c749SSergey Zigachev #define ixPCIEP_RESERVED 0x0000 513*b843c749SSergey Zigachev #define ixPCIEP_SCRATCH 0x0001 514*b843c749SSergey Zigachev #define ixPCIEP_STRAP_LC 0x00C0 515*b843c749SSergey Zigachev #define ixPCIEP_STRAP_MISC 0x00C1 516*b843c749SSergey Zigachev #define ixPCIE_RESERVED 0x0000 517*b843c749SSergey Zigachev #define ixPCIE_RX_CNTL 0x0070 518*b843c749SSergey Zigachev #define ixPCIE_RX_CNTL2 0x001D 519*b843c749SSergey Zigachev #define ixPCIE_RX_CNTL3 0x0074 520*b843c749SSergey Zigachev #define ixPCIE_RX_CREDITS_ALLOCATED_CPL 0x0082 521*b843c749SSergey Zigachev #define ixPCIE_RX_CREDITS_ALLOCATED_NP 0x0081 522*b843c749SSergey Zigachev #define ixPCIE_RX_CREDITS_ALLOCATED_P 0x0080 523*b843c749SSergey Zigachev #define ixPCIE_RX_EXPECTED_SEQNUM 0x0071 524*b843c749SSergey Zigachev #define ixPCIE_RX_LAST_TLP0 0x0031 525*b843c749SSergey Zigachev #define ixPCIE_RX_LAST_TLP1 0x0032 526*b843c749SSergey Zigachev #define ixPCIE_RX_LAST_TLP2 0x0033 527*b843c749SSergey Zigachev #define ixPCIE_RX_LAST_TLP3 0x0034 528*b843c749SSergey Zigachev #define ixPCIE_RX_NUM_NAK 0x000E 529*b843c749SSergey Zigachev #define ixPCIE_RX_NUM_NAK_GENERATED 0x000F 530*b843c749SSergey Zigachev #define ixPCIE_RX_VENDOR_SPECIFIC 0x0072 531*b843c749SSergey Zigachev #define ixPCIE_SCRATCH 0x0001 532*b843c749SSergey Zigachev #define ixPCIE_STRAP_F0 0x00B0 533*b843c749SSergey Zigachev #define ixPCIE_STRAP_F1 0x00B1 534*b843c749SSergey Zigachev #define ixPCIE_STRAP_F2 0x00B2 535*b843c749SSergey Zigachev #define ixPCIE_STRAP_F3 0x00B3 536*b843c749SSergey Zigachev #define ixPCIE_STRAP_F4 0x00B4 537*b843c749SSergey Zigachev #define ixPCIE_STRAP_F5 0x00B5 538*b843c749SSergey Zigachev #define ixPCIE_STRAP_F6 0x00B6 539*b843c749SSergey Zigachev #define ixPCIE_STRAP_F7 0x00B7 540*b843c749SSergey Zigachev #define ixPCIE_STRAP_I2C_BD 0x00C4 541*b843c749SSergey Zigachev #define ixPCIE_STRAP_MISC 0x00C0 542*b843c749SSergey Zigachev #define ixPCIE_STRAP_MISC2 0x00C1 543*b843c749SSergey Zigachev #define ixPCIE_STRAP_PI 0x00C2 544*b843c749SSergey Zigachev #define ixPCIE_TX_ACK_LATENCY_LIMIT 0x0026 545*b843c749SSergey Zigachev #define ixPCIE_TX_CNTL 0x0020 546*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_ADVT_CPL 0x0032 547*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_ADVT_NP 0x0031 548*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_ADVT_P 0x0030 549*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_FCU_THRESHOLD 0x0037 550*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_INIT_CPL 0x0035 551*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_INIT_NP 0x0034 552*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_INIT_P 0x0033 553*b843c749SSergey Zigachev #define ixPCIE_TX_CREDITS_STATUS 0x0036 554*b843c749SSergey Zigachev #define ixPCIE_TX_LAST_TLP0 0x0035 555*b843c749SSergey Zigachev #define ixPCIE_TX_LAST_TLP1 0x0036 556*b843c749SSergey Zigachev #define ixPCIE_TX_LAST_TLP2 0x0037 557*b843c749SSergey Zigachev #define ixPCIE_TX_LAST_TLP3 0x0038 558*b843c749SSergey Zigachev #define ixPCIE_TX_REPLAY 0x0025 559*b843c749SSergey Zigachev #define ixPCIE_TX_REQUESTER_ID 0x0021 560*b843c749SSergey Zigachev #define ixPCIE_TX_REQUEST_NUM_CNTL 0x0023 561*b843c749SSergey Zigachev #define ixPCIE_TX_SEQ 0x0024 562*b843c749SSergey Zigachev #define ixPCIE_TX_VENDOR_SPECIFIC 0x0022 563*b843c749SSergey Zigachev #define ixPCIE_WPR_CNTL 0x0030 564*b843c749SSergey Zigachev #define mmBACO_CNTL 0x14E5 565*b843c749SSergey Zigachev #define mmBF_ANA_ISO_CNTL 0x14C7 566*b843c749SSergey Zigachev #define mmBIF_BACO_DEBUG 0x14DF 567*b843c749SSergey Zigachev #define mmBIF_BACO_DEBUG_LATCH 0x14DC 568*b843c749SSergey Zigachev #define mmBIF_BACO_MSIC 0x14DE 569*b843c749SSergey Zigachev #define mmBIF_BUSNUM_CNTL1 0x1525 570*b843c749SSergey Zigachev #define mmBIF_BUSNUM_CNTL2 0x152B 571*b843c749SSergey Zigachev #define mmBIF_BUSNUM_LIST0 0x1526 572*b843c749SSergey Zigachev #define mmBIF_BUSNUM_LIST1 0x1527 573*b843c749SSergey Zigachev #define mmBIF_BUSY_DELAY_CNTR 0x1529 574*b843c749SSergey Zigachev #define mmBIF_CLK_PDWN_DELAY_TIMER 0x151F 575*b843c749SSergey Zigachev #define mmBIF_DEBUG_CNTL 0x151C 576*b843c749SSergey Zigachev #define mmBIF_DEBUG_MUX 0x151D 577*b843c749SSergey Zigachev #define mmBIF_DEBUG_OUT 0x151E 578*b843c749SSergey Zigachev #define mmBIF_DEVFUNCNUM_LIST0 0x14E8 579*b843c749SSergey Zigachev #define mmBIF_DEVFUNCNUM_LIST1 0x14E7 580*b843c749SSergey Zigachev #define mmBIF_FB_EN 0x1524 581*b843c749SSergey Zigachev #define mmBIF_FEATURES_CONTROL_MISC 0x14C2 582*b843c749SSergey Zigachev #define mmBIF_PERFCOUNTER0_RESULT 0x152D 583*b843c749SSergey Zigachev #define mmBIF_PERFCOUNTER1_RESULT 0x152E 584*b843c749SSergey Zigachev #define mmBIF_PERFMON_CNTL 0x152C 585*b843c749SSergey Zigachev #define mmBIF_PIF_TXCLK_SWITCH_TIMER 0x152F 586*b843c749SSergey Zigachev #define mmBIF_RESET_EN 0x1511 587*b843c749SSergey Zigachev #define mmBIF_SCRATCH0 0x150E 588*b843c749SSergey Zigachev #define mmBIF_SCRATCH1 0x150F 589*b843c749SSergey Zigachev #define mmBIF_SSA_DISP_LOWER 0x14D2 590*b843c749SSergey Zigachev #define mmBIF_SSA_DISP_UPPER 0x14D3 591*b843c749SSergey Zigachev #define mmBIF_SSA_GFX0_LOWER 0x14CA 592*b843c749SSergey Zigachev #define mmBIF_SSA_GFX0_UPPER 0x14CB 593*b843c749SSergey Zigachev #define mmBIF_SSA_GFX1_LOWER 0x14CC 594*b843c749SSergey Zigachev #define mmBIF_SSA_GFX1_UPPER 0x14CD 595*b843c749SSergey Zigachev #define mmBIF_SSA_GFX2_LOWER 0x14CE 596*b843c749SSergey Zigachev #define mmBIF_SSA_GFX2_UPPER 0x14CF 597*b843c749SSergey Zigachev #define mmBIF_SSA_GFX3_LOWER 0x14D0 598*b843c749SSergey Zigachev #define mmBIF_SSA_GFX3_UPPER 0x14D1 599*b843c749SSergey Zigachev #define mmBIF_SSA_MC_LOWER 0x14D4 600*b843c749SSergey Zigachev #define mmBIF_SSA_MC_UPPER 0x14D5 601*b843c749SSergey Zigachev #define mmBIF_SSA_PWR_STATUS 0x14C8 602*b843c749SSergey Zigachev #define mmBIF_XDMA_HI 0x14C1 603*b843c749SSergey Zigachev #define mmBIF_XDMA_LO 0x14C0 604*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_0 0x05C9 605*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_10 0x05D3 606*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_1 0x05CA 607*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_11 0x05D4 608*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_12 0x05D5 609*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_13 0x05D6 610*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_14 0x05D7 611*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_15 0x05D8 612*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_2 0x05CB 613*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_3 0x05CC 614*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_4 0x05CD 615*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_5 0x05CE 616*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_6 0x05CF 617*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_7 0x05D0 618*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_8 0x05D1 619*b843c749SSergey Zigachev #define mmBIOS_SCRATCH_9 0x05D2 620*b843c749SSergey Zigachev #define mmBUS_CNTL 0x1508 621*b843c749SSergey Zigachev #define mmCAPTURE_HOST_BUSNUM 0x153C 622*b843c749SSergey Zigachev #define mmCLKREQB_PAD_CNTL 0x1521 623*b843c749SSergey Zigachev #define mmCONFIG_APER_SIZE 0x150C 624*b843c749SSergey Zigachev #define mmCONFIG_CNTL 0x1509 625*b843c749SSergey Zigachev #define mmCONFIG_F0_BASE 0x150B 626*b843c749SSergey Zigachev #define mmCONFIG_MEMSIZE 0x150A 627*b843c749SSergey Zigachev #define mmCONFIG_REG_APER_SIZE 0x150D 628*b843c749SSergey Zigachev #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x1520 629*b843c749SSergey Zigachev #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x1528 630*b843c749SSergey Zigachev #define mmHOST_BUSNUM 0x153D 631*b843c749SSergey Zigachev #define mmHW_DEBUG 0x1515 632*b843c749SSergey Zigachev #define mmIMPCTL_RESET 0x14F5 633*b843c749SSergey Zigachev #define mmINTERRUPT_CNTL 0x151A 634*b843c749SSergey Zigachev #define mmINTERRUPT_CNTL2 0x151B 635*b843c749SSergey Zigachev #define mmMASTER_CREDIT_CNTL 0x1516 636*b843c749SSergey Zigachev #define mmMM_CFGREGS_CNTL 0x1513 637*b843c749SSergey Zigachev #define mmMM_DATA 0x0001 638*b843c749SSergey Zigachev #define mmMM_INDEX 0x0000 639*b843c749SSergey Zigachev #define mmMM_INDEX_HI 0x0006 640*b843c749SSergey Zigachev #define mmNEW_REFCLKB_TIMER 0x14EA 641*b843c749SSergey Zigachev #define mmNEW_REFCLKB_TIMER_1 0x14E9 642*b843c749SSergey Zigachev #define mmPCIE_DATA 0x000D 643*b843c749SSergey Zigachev #define mmPCIE_INDEX 0x000C 644*b843c749SSergey Zigachev #define mmPEER0_FB_OFFSET_HI 0x14F3 645*b843c749SSergey Zigachev #define mmPEER0_FB_OFFSET_LO 0x14F2 646*b843c749SSergey Zigachev #define mmPEER1_FB_OFFSET_HI 0x14F1 647*b843c749SSergey Zigachev #define mmPEER1_FB_OFFSET_LO 0x14F0 648*b843c749SSergey Zigachev #define mmPEER2_FB_OFFSET_HI 0x14EF 649*b843c749SSergey Zigachev #define mmPEER2_FB_OFFSET_LO 0x14EE 650*b843c749SSergey Zigachev #define mmPEER3_FB_OFFSET_HI 0x14ED 651*b843c749SSergey Zigachev #define mmPEER3_FB_OFFSET_LO 0x14EC 652*b843c749SSergey Zigachev #define mmPEER_REG_RANGE0 0x153E 653*b843c749SSergey Zigachev #define mmPEER_REG_RANGE1 0x153F 654*b843c749SSergey Zigachev #define mmSLAVE_HANG_ERROR 0x153B 655*b843c749SSergey Zigachev #define mmSLAVE_HANG_PROTECTION_CNTL 0x1536 656*b843c749SSergey Zigachev #define mmSLAVE_REQ_CREDIT_CNTL 0x1517 657*b843c749SSergey Zigachev #define mmSMBCLK_PAD_CNTL 0x1523 658*b843c749SSergey Zigachev #define mmSMBDAT_PAD_CNTL 0x1522 659*b843c749SSergey Zigachev #define mmSMBUS_BACO_DUMMY 0x14C6 660*b843c749SSergey Zigachev 661*b843c749SSergey Zigachev #endif 662