1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * 3*b843c749SSergey Zigachev * Copyright (C) 2016 Advanced Micro Devices, Inc. 4*b843c749SSergey Zigachev * 5*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 6*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 7*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 8*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 10*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 11*b843c749SSergey Zigachev * 12*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included 13*b843c749SSergey Zigachev * in all copies or substantial portions of the Software. 14*b843c749SSergey Zigachev * 15*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16*b843c749SSergey Zigachev * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19*b843c749SSergey Zigachev * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20*b843c749SSergey Zigachev * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev */ 22*b843c749SSergey Zigachev 23*b843c749SSergey Zigachev #ifndef DCE_6_0_SH_MASK_H 24*b843c749SSergey Zigachev #define DCE_6_0_SH_MASK_H 25*b843c749SSergey Zigachev 26*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL 27*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 28*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL 29*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 30*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 31*b843c749SSergey Zigachev #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 32*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L 33*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 34*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L 35*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 36*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE_MASK 0x0000ff00L 37*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CATEGORY_CODE__SHIFT 0x00000008 38*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK 0x00f00000L 39*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000014 40*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK 0x30000000L 41*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY__SHIFT 0x0000001c 42*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_C_MASK 0x00000004L 43*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_C__SHIFT 0x00000002 44*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_D_MASK 0x00000038L 45*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_D__SHIFT 0x00000003 46*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_MODE_MASK 0x000000c0L 47*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_MODE__SHIFT 0x00000006 48*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY_MASK 0x0f000000L 49*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000018 50*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER_MASK 0x000f0000L 51*b843c749SSergey Zigachev #define AFMT_60958_0__AFMT_60958_CS_SOURCE_NUMBER__SHIFT 0x00000010 52*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R_MASK 0x00f00000L 53*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000014 54*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x000000f0L 55*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000004 56*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH_MASK 0x0000000fL 57*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_CS_WORD_LENGTH__SHIFT 0x00000000 58*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_VALID_L_MASK 0x00010000L 59*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_VALID_L__SHIFT 0x00000010 60*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_VALID_R_MASK 0x00040000L 61*b843c749SSergey Zigachev #define AFMT_60958_1__AFMT_60958_VALID_R__SHIFT 0x00000012 62*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 63*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 64*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 65*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 66*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4_MASK 0x00000f00L 67*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000008 68*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5_MASK 0x0000f000L 69*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x0000000c 70*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6_MASK 0x000f0000L 71*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000010 72*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7_MASK 0x00f00000L 73*b843c749SSergey Zigachev #define AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000014 74*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL_MASK 0x0000f000L 75*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CH_SEL__SHIFT 0x0000000c 76*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT_MASK 0x00000010L 77*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_CONT__SHIFT 0x00000004 78*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT_MASK 0xffff0000L 79*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_COUNT__SHIFT 0x00000010 80*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN_MASK 0x00000001L 81*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_EN__SHIFT 0x00000000 82*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE_MASK 0x00000100L 83*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_CONTROL__AFMT_AUDIO_CRC_SOURCE__SHIFT 0x00000008 84*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE_MASK 0x00000001L 85*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_DONE__SHIFT 0x00000000 86*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC_MASK 0xffffff00L 87*b843c749SSergey Zigachev #define AFMT_AUDIO_CRC_RESULT__AFMT_AUDIO_CRC__SHIFT 0x00000008 88*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE_MASK 0x00000100L 89*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_BASE__SHIFT 0x00000008 90*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV_MASK 0x00070000L 91*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_DIV__SHIFT 0x00000010 92*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI_MASK 0x00007000L 93*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_DBG_MULTI__SHIFT 0x0000000c 94*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL_MASK 0x00000007L 95*b843c749SSergey Zigachev #define AFMT_AUDIO_DBG_DTO_CNTL__AFMT_AUDIO_DTO_FS_DIV_SEL__SHIFT 0x00000000 96*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC_MASK 0x00000700L 97*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CC__SHIFT 0x00000008 98*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_MASK 0x000000ffL 99*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET_MASK 0x00ff0000L 100*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM_OFFSET__SHIFT 0x00000010 101*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CHECKSUM__SHIFT 0x00000000 102*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT_MASK 0x00007800L 103*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CT__SHIFT 0x0000000b 104*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT_MASK 0x1f000000L 105*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO0__AFMT_AUDIO_INFO_CXT__SHIFT 0x00000018 106*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA_MASK 0x000000ffL 107*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_CA__SHIFT 0x00000000 108*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH_MASK 0x00008000L 109*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_DM_INH__SHIFT 0x0000000f 110*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL_MASK 0x00030000L 111*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LFEPBL__SHIFT 0x00000010 112*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV_MASK 0x00007800L 113*b843c749SSergey Zigachev #define AFMT_AUDIO_INFO1__AFMT_AUDIO_INFO_LSV__SHIFT 0x0000000b 114*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD_MASK 0x10000000L 115*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_60958_OSF_OVRD__SHIFT 0x0000001c 116*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE_MASK 0x0000ff00L 117*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT 0x00000008 118*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD_MASK 0x00000001L 119*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_OVRD__SHIFT 0x00000000 120*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT_MASK 0x00000002L 121*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_LAYOUT_SELECT__SHIFT 0x00000001 122*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID_MASK 0x00ff0000L 123*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_DP_AUDIO_STREAM_ID__SHIFT 0x00000010 124*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD_MASK 0x01000000L 125*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL2__AFMT_HBR_ENABLE_OVRD__SHIFT 0x00000018 126*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK 0x04000000L 127*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE__SHIFT 0x0000001a 128*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP_MASK 0x01000000L 129*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_CHANNEL_SWAP__SHIFT 0x00000018 130*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK_MASK 0x00800000L 131*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_FIFO_OVERFLOW_ACK__SHIFT 0x00000017 132*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK 0x00000001L 133*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND__SHIFT 0x00000000 134*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN_MASK 0x00001000L 135*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_EN__SHIFT 0x0000000c 136*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE_MASK 0x00004000L 137*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_TEST_MODE__SHIFT 0x0000000e 138*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK_MASK 0x40000000L 139*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_AZ_AUDIO_ENABLE_CHG_ACK__SHIFT 0x0000001e 140*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB_MASK 0x80000000L 141*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_BLANK_TEST_DATA_ON_ENC_ENB__SHIFT 0x0000001f 142*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS_MASK 0x00000800L 143*b843c749SSergey Zigachev #define AFMT_AUDIO_PACKET_CONTROL__AFMT_RESET_FIFO_WHEN_AUDIO_DIS__SHIFT 0x0000000b 144*b843c749SSergey Zigachev #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT_MASK 0x00000007L 145*b843c749SSergey Zigachev #define AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT 0x00000000 146*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A_MASK 0x00001000L 147*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_A__SHIFT 0x0000000c 148*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B_MASK 0x00000c00L 149*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_B__SHIFT 0x0000000a 150*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM_MASK 0x000000ffL 151*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_CHECKSUM__SHIFT 0x00000000 152*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C_MASK 0x00c00000L 153*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_C__SHIFT 0x00000016 154*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC_MASK 0x70000000L 155*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_EC__SHIFT 0x0000001c 156*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC_MASK 0x80000000L 157*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_ITC__SHIFT 0x0000001f 158*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M_MASK 0x00300000L 159*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_M__SHIFT 0x00000014 160*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD_MASK 0x00008000L 161*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_PB1_RSVD__SHIFT 0x0000000f 162*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q_MASK 0x0c000000L 163*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Q__SHIFT 0x0000001a 164*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R_MASK 0x000f0000L 165*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_R__SHIFT 0x00000010 166*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC_MASK 0x03000000L 167*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_SC__SHIFT 0x00000018 168*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S_MASK 0x00000300L 169*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_S__SHIFT 0x00000008 170*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y_MASK 0x00006000L 171*b843c749SSergey Zigachev #define AFMT_AVI_INFO0__AFMT_AVI_INFO_Y__SHIFT 0x0000000d 172*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN_MASK 0x00003000L 173*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_CN__SHIFT 0x0000000c 174*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD_MASK 0x00000080L 175*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PB4_RSVD__SHIFT 0x00000007 176*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR_MASK 0x00000f00L 177*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_PR__SHIFT 0x00000008 178*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP_MASK 0xffff0000L 179*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_TOP__SHIFT 0x00000010 180*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC_MASK 0x0000007fL 181*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_VIC__SHIFT 0x00000000 182*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ_MASK 0x0000c000L 183*b843c749SSergey Zigachev #define AFMT_AVI_INFO1__AFMT_AVI_INFO_YQ__SHIFT 0x0000000e 184*b843c749SSergey Zigachev #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM_MASK 0x0000ffffL 185*b843c749SSergey Zigachev #define AFMT_AVI_INFO2__AFMT_AVI_INFO_BOTTOM__SHIFT 0x00000000 186*b843c749SSergey Zigachev #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT_MASK 0xffff0000L 187*b843c749SSergey Zigachev #define AFMT_AVI_INFO2__AFMT_AVI_INFO_LEFT__SHIFT 0x00000010 188*b843c749SSergey Zigachev #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT_MASK 0x0000ffffL 189*b843c749SSergey Zigachev #define AFMT_AVI_INFO3__AFMT_AVI_INFO_RIGHT__SHIFT 0x00000000 190*b843c749SSergey Zigachev #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION_MASK 0xff000000L 191*b843c749SSergey Zigachev #define AFMT_AVI_INFO3__AFMT_AVI_INFO_VERSION__SHIFT 0x00000018 192*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0_MASK 0x000000ffL 193*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE0__SHIFT 0x00000000 194*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1_MASK 0x0000ff00L 195*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE1__SHIFT 0x00000008 196*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2_MASK 0x00ff0000L 197*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE2__SHIFT 0x00000010 198*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3_MASK 0xff000000L 199*b843c749SSergey Zigachev #define AFMT_GENERIC_0__AFMT_GENERIC_BYTE3__SHIFT 0x00000018 200*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4_MASK 0x000000ffL 201*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE4__SHIFT 0x00000000 202*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5_MASK 0x0000ff00L 203*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE5__SHIFT 0x00000008 204*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6_MASK 0x00ff0000L 205*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE6__SHIFT 0x00000010 206*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7_MASK 0xff000000L 207*b843c749SSergey Zigachev #define AFMT_GENERIC_1__AFMT_GENERIC_BYTE7__SHIFT 0x00000018 208*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10_MASK 0x00ff0000L 209*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE10__SHIFT 0x00000010 210*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11_MASK 0xff000000L 211*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE11__SHIFT 0x00000018 212*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8_MASK 0x000000ffL 213*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE8__SHIFT 0x00000000 214*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9_MASK 0x0000ff00L 215*b843c749SSergey Zigachev #define AFMT_GENERIC_2__AFMT_GENERIC_BYTE9__SHIFT 0x00000008 216*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12_MASK 0x000000ffL 217*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE12__SHIFT 0x00000000 218*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13_MASK 0x0000ff00L 219*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE13__SHIFT 0x00000008 220*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14_MASK 0x00ff0000L 221*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE14__SHIFT 0x00000010 222*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15_MASK 0xff000000L 223*b843c749SSergey Zigachev #define AFMT_GENERIC_3__AFMT_GENERIC_BYTE15__SHIFT 0x00000018 224*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16_MASK 0x000000ffL 225*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE16__SHIFT 0x00000000 226*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17_MASK 0x0000ff00L 227*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE17__SHIFT 0x00000008 228*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18_MASK 0x00ff0000L 229*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE18__SHIFT 0x00000010 230*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19_MASK 0xff000000L 231*b843c749SSergey Zigachev #define AFMT_GENERIC_4__AFMT_GENERIC_BYTE19__SHIFT 0x00000018 232*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20_MASK 0x000000ffL 233*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE20__SHIFT 0x00000000 234*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21_MASK 0x0000ff00L 235*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE21__SHIFT 0x00000008 236*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22_MASK 0x00ff0000L 237*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE22__SHIFT 0x00000010 238*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23_MASK 0xff000000L 239*b843c749SSergey Zigachev #define AFMT_GENERIC_5__AFMT_GENERIC_BYTE23__SHIFT 0x00000018 240*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24_MASK 0x000000ffL 241*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE24__SHIFT 0x00000000 242*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25_MASK 0x0000ff00L 243*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE25__SHIFT 0x00000008 244*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26_MASK 0x00ff0000L 245*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE26__SHIFT 0x00000010 246*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27_MASK 0xff000000L 247*b843c749SSergey Zigachev #define AFMT_GENERIC_6__AFMT_GENERIC_BYTE27__SHIFT 0x00000018 248*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28_MASK 0x000000ffL 249*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE28__SHIFT 0x00000000 250*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29_MASK 0x0000ff00L 251*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE29__SHIFT 0x00000008 252*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30_MASK 0x00ff0000L 253*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE30__SHIFT 0x00000010 254*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31_MASK 0xff000000L 255*b843c749SSergey Zigachev #define AFMT_GENERIC_7__AFMT_GENERIC_BYTE31__SHIFT 0x00000018 256*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0_MASK 0x000000ffL 257*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB0__SHIFT 0x00000000 258*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1_MASK 0x0000ff00L 259*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB1__SHIFT 0x00000008 260*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2_MASK 0x00ff0000L 261*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB2__SHIFT 0x00000010 262*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3_MASK 0xff000000L 263*b843c749SSergey Zigachev #define AFMT_GENERIC_HDR__AFMT_GENERIC_HB3__SHIFT 0x00000018 264*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE_MASK 0x00000040L 265*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_SOURCE__SHIFT 0x00000006 266*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK 0x00000080L 267*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE__SHIFT 0x00000007 268*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE_MASK 0x00000400L 269*b843c749SSergey Zigachev #define AFMT_INFOFRAME_CONTROL0__AFMT_MPEG_INFO_UPDATE__SHIFT 0x0000000a 270*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE_MASK 0x00000040L 271*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_CONTINUE__SHIFT 0x00000006 272*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_STATUS_MASK 0x00000007L 273*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_STATUS__SHIFT 0x00000000 274*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_VALID_MASK 0x00000080L 275*b843c749SSergey Zigachev #define AFMT_ISRC1_0__AFMT_ISRC_VALID__SHIFT 0x00000007 276*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0_MASK 0x000000ffL 277*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC0__SHIFT 0x00000000 278*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1_MASK 0x0000ff00L 279*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC1__SHIFT 0x00000008 280*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2_MASK 0x00ff0000L 281*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC2__SHIFT 0x00000010 282*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3_MASK 0xff000000L 283*b843c749SSergey Zigachev #define AFMT_ISRC1_1__AFMT_UPC_EAN_ISRC3__SHIFT 0x00000018 284*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4_MASK 0x000000ffL 285*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC4__SHIFT 0x00000000 286*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5_MASK 0x0000ff00L 287*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC5__SHIFT 0x00000008 288*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6_MASK 0x00ff0000L 289*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC6__SHIFT 0x00000010 290*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7_MASK 0xff000000L 291*b843c749SSergey Zigachev #define AFMT_ISRC1_2__AFMT_UPC_EAN_ISRC7__SHIFT 0x00000018 292*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10_MASK 0x00ff0000L 293*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC10__SHIFT 0x00000010 294*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11_MASK 0xff000000L 295*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC11__SHIFT 0x00000018 296*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8_MASK 0x000000ffL 297*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC8__SHIFT 0x00000000 298*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9_MASK 0x0000ff00L 299*b843c749SSergey Zigachev #define AFMT_ISRC1_3__AFMT_UPC_EAN_ISRC9__SHIFT 0x00000008 300*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12_MASK 0x000000ffL 301*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC12__SHIFT 0x00000000 302*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13_MASK 0x0000ff00L 303*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC13__SHIFT 0x00000008 304*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14_MASK 0x00ff0000L 305*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC14__SHIFT 0x00000010 306*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15_MASK 0xff000000L 307*b843c749SSergey Zigachev #define AFMT_ISRC1_4__AFMT_UPC_EAN_ISRC15__SHIFT 0x00000018 308*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16_MASK 0x000000ffL 309*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC16__SHIFT 0x00000000 310*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17_MASK 0x0000ff00L 311*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC17__SHIFT 0x00000008 312*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18_MASK 0x00ff0000L 313*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC18__SHIFT 0x00000010 314*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19_MASK 0xff000000L 315*b843c749SSergey Zigachev #define AFMT_ISRC2_0__AFMT_UPC_EAN_ISRC19__SHIFT 0x00000018 316*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20_MASK 0x000000ffL 317*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC20__SHIFT 0x00000000 318*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21_MASK 0x0000ff00L 319*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC21__SHIFT 0x00000008 320*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22_MASK 0x00ff0000L 321*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC22__SHIFT 0x00000010 322*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23_MASK 0xff000000L 323*b843c749SSergey Zigachev #define AFMT_ISRC2_1__AFMT_UPC_EAN_ISRC23__SHIFT 0x00000018 324*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24_MASK 0x000000ffL 325*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC24__SHIFT 0x00000000 326*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25_MASK 0x0000ff00L 327*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC25__SHIFT 0x00000008 328*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26_MASK 0x00ff0000L 329*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC26__SHIFT 0x00000010 330*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27_MASK 0xff000000L 331*b843c749SSergey Zigachev #define AFMT_ISRC2_2__AFMT_UPC_EAN_ISRC27__SHIFT 0x00000018 332*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28_MASK 0x000000ffL 333*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC28__SHIFT 0x00000000 334*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29_MASK 0x0000ff00L 335*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC29__SHIFT 0x00000008 336*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30_MASK 0x00ff0000L 337*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC30__SHIFT 0x00000010 338*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31_MASK 0xff000000L 339*b843c749SSergey Zigachev #define AFMT_ISRC2_3__AFMT_UPC_EAN_ISRC31__SHIFT 0x00000018 340*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM_MASK 0x000000ffL 341*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_CHECKSUM__SHIFT 0x00000000 342*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0_MASK 0x0000ff00L 343*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB0__SHIFT 0x00000008 344*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1_MASK 0x00ff0000L 345*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB1__SHIFT 0x00000010 346*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2_MASK 0xff000000L 347*b843c749SSergey Zigachev #define AFMT_MPEG_INFO0__AFMT_MPEG_INFO_MB2__SHIFT 0x00000018 348*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR_MASK 0x00001000L 349*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_FR__SHIFT 0x0000000c 350*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3_MASK 0x000000ffL 351*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MB3__SHIFT 0x00000000 352*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF_MASK 0x00000300L 353*b843c749SSergey Zigachev #define AFMT_MPEG_INFO1__AFMT_MPEG_INFO_MF__SHIFT 0x00000008 354*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN_MASK 0x80000000L 355*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL0__AFMT_RAMP_DATA_SIGN__SHIFT 0x0000001f 356*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT_MASK 0x00ffffffL 357*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL0__AFMT_RAMP_MAX_COUNT__SHIFT 0x00000000 358*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE_MASK 0xff000000L 359*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL1__AFMT_AUDIO_TEST_CH_DISABLE__SHIFT 0x00000018 360*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT_MASK 0x00ffffffL 361*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL1__AFMT_RAMP_MIN_COUNT__SHIFT 0x00000000 362*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT_MASK 0x00ffffffL 363*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL2__AFMT_RAMP_INC_COUNT__SHIFT 0x00000000 364*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT_MASK 0x00ffffffL 365*b843c749SSergey Zigachev #define AFMT_RAMP_CONTROL3__AFMT_RAMP_DEC_COUNT__SHIFT 0x00000000 366*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AUDIO_ENABLE_MASK 0x00000010L 367*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AUDIO_ENABLE__SHIFT 0x00000004 368*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW_MASK 0x01000000L 369*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AUDIO_FIFO_OVERFLOW__SHIFT 0x00000018 370*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG_MASK 0x40000000L 371*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AZ_AUDIO_ENABLE_CHG__SHIFT 0x0000001e 372*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE_MASK 0x00000100L 373*b843c749SSergey Zigachev #define AFMT_STATUS__AFMT_AZ_HBR_ENABLE__SHIFT 0x00000008 374*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE_MASK 0x00000004L 375*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC0_UPDATE__SHIFT 0x00000002 376*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE_MASK 0x00000008L 377*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC2_UPDATE__SHIFT 0x00000003 378*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX_MASK 0xc0000000L 379*b843c749SSergey Zigachev #define AFMT_VBI_PACKET_CONTROL__AFMT_GENERIC_INDEX__SHIFT 0x0000001e 380*b843c749SSergey Zigachev #define ATTR00__ATTR_PAL_MASK 0x0000003fL 381*b843c749SSergey Zigachev #define ATTR00__ATTR_PAL__SHIFT 0x00000000 382*b843c749SSergey Zigachev #define ATTR01__ATTR_PAL_MASK 0x0000003fL 383*b843c749SSergey Zigachev #define ATTR01__ATTR_PAL__SHIFT 0x00000000 384*b843c749SSergey Zigachev #define ATTR02__ATTR_PAL_MASK 0x0000003fL 385*b843c749SSergey Zigachev #define ATTR02__ATTR_PAL__SHIFT 0x00000000 386*b843c749SSergey Zigachev #define ATTR03__ATTR_PAL_MASK 0x0000003fL 387*b843c749SSergey Zigachev #define ATTR03__ATTR_PAL__SHIFT 0x00000000 388*b843c749SSergey Zigachev #define ATTR04__ATTR_PAL_MASK 0x0000003fL 389*b843c749SSergey Zigachev #define ATTR04__ATTR_PAL__SHIFT 0x00000000 390*b843c749SSergey Zigachev #define ATTR05__ATTR_PAL_MASK 0x0000003fL 391*b843c749SSergey Zigachev #define ATTR05__ATTR_PAL__SHIFT 0x00000000 392*b843c749SSergey Zigachev #define ATTR06__ATTR_PAL_MASK 0x0000003fL 393*b843c749SSergey Zigachev #define ATTR06__ATTR_PAL__SHIFT 0x00000000 394*b843c749SSergey Zigachev #define ATTR07__ATTR_PAL_MASK 0x0000003fL 395*b843c749SSergey Zigachev #define ATTR07__ATTR_PAL__SHIFT 0x00000000 396*b843c749SSergey Zigachev #define ATTR08__ATTR_PAL_MASK 0x0000003fL 397*b843c749SSergey Zigachev #define ATTR08__ATTR_PAL__SHIFT 0x00000000 398*b843c749SSergey Zigachev #define ATTR09__ATTR_PAL_MASK 0x0000003fL 399*b843c749SSergey Zigachev #define ATTR09__ATTR_PAL__SHIFT 0x00000000 400*b843c749SSergey Zigachev #define ATTR0A__ATTR_PAL_MASK 0x0000003fL 401*b843c749SSergey Zigachev #define ATTR0A__ATTR_PAL__SHIFT 0x00000000 402*b843c749SSergey Zigachev #define ATTR0B__ATTR_PAL_MASK 0x0000003fL 403*b843c749SSergey Zigachev #define ATTR0B__ATTR_PAL__SHIFT 0x00000000 404*b843c749SSergey Zigachev #define ATTR0C__ATTR_PAL_MASK 0x0000003fL 405*b843c749SSergey Zigachev #define ATTR0C__ATTR_PAL__SHIFT 0x00000000 406*b843c749SSergey Zigachev #define ATTR0D__ATTR_PAL_MASK 0x0000003fL 407*b843c749SSergey Zigachev #define ATTR0D__ATTR_PAL__SHIFT 0x00000000 408*b843c749SSergey Zigachev #define ATTR0E__ATTR_PAL_MASK 0x0000003fL 409*b843c749SSergey Zigachev #define ATTR0E__ATTR_PAL__SHIFT 0x00000000 410*b843c749SSergey Zigachev #define ATTR0F__ATTR_PAL_MASK 0x0000003fL 411*b843c749SSergey Zigachev #define ATTR0F__ATTR_PAL__SHIFT 0x00000000 412*b843c749SSergey Zigachev #define ATTR10__ATTR_BLINK_EN_MASK 0x00000008L 413*b843c749SSergey Zigachev #define ATTR10__ATTR_BLINK_EN__SHIFT 0x00000003 414*b843c749SSergey Zigachev #define ATTR10__ATTR_CSEL_EN_MASK 0x00000080L 415*b843c749SSergey Zigachev #define ATTR10__ATTR_CSEL_EN__SHIFT 0x00000007 416*b843c749SSergey Zigachev #define ATTR10__ATTR_GRPH_MODE_MASK 0x00000001L 417*b843c749SSergey Zigachev #define ATTR10__ATTR_GRPH_MODE__SHIFT 0x00000000 418*b843c749SSergey Zigachev #define ATTR10__ATTR_LGRPH_EN_MASK 0x00000004L 419*b843c749SSergey Zigachev #define ATTR10__ATTR_LGRPH_EN__SHIFT 0x00000002 420*b843c749SSergey Zigachev #define ATTR10__ATTR_MONO_EN_MASK 0x00000002L 421*b843c749SSergey Zigachev #define ATTR10__ATTR_MONO_EN__SHIFT 0x00000001 422*b843c749SSergey Zigachev #define ATTR10__ATTR_PANTOPONLY_MASK 0x00000020L 423*b843c749SSergey Zigachev #define ATTR10__ATTR_PANTOPONLY__SHIFT 0x00000005 424*b843c749SSergey Zigachev #define ATTR10__ATTR_PCLKBY2_MASK 0x00000040L 425*b843c749SSergey Zigachev #define ATTR10__ATTR_PCLKBY2__SHIFT 0x00000006 426*b843c749SSergey Zigachev #define ATTR11__ATTR_OVSC_MASK 0x000000ffL 427*b843c749SSergey Zigachev #define ATTR11__ATTR_OVSC__SHIFT 0x00000000 428*b843c749SSergey Zigachev #define ATTR12__ATTR_MAP_EN_MASK 0x0000000fL 429*b843c749SSergey Zigachev #define ATTR12__ATTR_MAP_EN__SHIFT 0x00000000 430*b843c749SSergey Zigachev #define ATTR12__ATTR_VSMUX_MASK 0x00000030L 431*b843c749SSergey Zigachev #define ATTR12__ATTR_VSMUX__SHIFT 0x00000004 432*b843c749SSergey Zigachev #define ATTR13__ATTR_PPAN_MASK 0x0000000fL 433*b843c749SSergey Zigachev #define ATTR13__ATTR_PPAN__SHIFT 0x00000000 434*b843c749SSergey Zigachev #define ATTR14__ATTR_CSEL1_MASK 0x00000003L 435*b843c749SSergey Zigachev #define ATTR14__ATTR_CSEL1__SHIFT 0x00000000 436*b843c749SSergey Zigachev #define ATTR14__ATTR_CSEL2_MASK 0x0000000cL 437*b843c749SSergey Zigachev #define ATTR14__ATTR_CSEL2__SHIFT 0x00000002 438*b843c749SSergey Zigachev #define ATTRDR__ATTR_DATA_MASK 0x000000ffL 439*b843c749SSergey Zigachev #define ATTRDR__ATTR_DATA__SHIFT 0x00000000 440*b843c749SSergey Zigachev #define ATTRDW__ATTR_DATA_MASK 0x000000ffL 441*b843c749SSergey Zigachev #define ATTRDW__ATTR_DATA__SHIFT 0x00000000 442*b843c749SSergey Zigachev #define ATTRX__ATTR_IDX_MASK 0x0000001fL 443*b843c749SSergey Zigachev #define ATTRX__ATTR_IDX__SHIFT 0x00000000 444*b843c749SSergey Zigachev #define ATTRX__ATTR_PAL_RW_ENB_MASK 0x00000020L 445*b843c749SSergey Zigachev #define ATTRX__ATTR_PAL_RW_ENB__SHIFT 0x00000005 446*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 447*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 448*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 449*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 450*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 451*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 452*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 453*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 454*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 455*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 456*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 457*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 458*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 459*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 460*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 461*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 462*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 463*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 464*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 465*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 466*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 467*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 468*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 469*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 470*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 471*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 472*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 473*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 474*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 475*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 476*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 477*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 478*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 479*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 480*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 481*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 482*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 483*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 484*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 485*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 486*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 487*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 488*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 489*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 490*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 491*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 492*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 493*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 494*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 495*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 496*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 497*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 498*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 499*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 500*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 501*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 502*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 503*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 504*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 505*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 506*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 507*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 508*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 509*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 510*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 511*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 512*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 513*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 514*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 515*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 516*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 517*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 518*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 519*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 520*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 521*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 522*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 523*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 524*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 525*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 526*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 527*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 528*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 529*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 530*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 531*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 532*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 533*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 534*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 535*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 536*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 537*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 538*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 539*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 540*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 541*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 542*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 543*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 544*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 545*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 546*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 547*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 548*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 549*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 550*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 551*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 552*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 553*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 554*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 555*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 556*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 557*b843c749SSergey Zigachev #define AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 558*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY_MASK 0x00000003L 559*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_ARB_PRIORITY__SHIFT 0x00000000 560*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG_MASK 0x02000000L 561*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_DONE_USING_AUX_REG__SHIFT 0x00000019 562*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ_MASK 0x01000000L 563*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000018 564*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ_MASK 0x01000000L 565*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_DMCU_USE_AUX_REG_REQ__SHIFT 0x00000018 566*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO_MASK 0x00000400L 567*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_NO_QUEUED_LS_GO__SHIFT 0x0000000a 568*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO_MASK 0x00000100L 569*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_NO_QUEUED_SW_GO__SHIFT 0x00000008 570*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS_MASK 0x0000000cL 571*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_REG_RW_CNTL_STATUS__SHIFT 0x00000002 572*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG_MASK 0x00020000L 573*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_DONE_USING_AUX_REG__SHIFT 0x00000011 574*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ_MASK 0x00010000L 575*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_PENDING_USE_AUX_REG_REQ__SHIFT 0x00000010 576*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ_MASK 0x00010000L 577*b843c749SSergey Zigachev #define AUX_ARB_CONTROL__AUX_SW_USE_AUX_REG_REQ__SHIFT 0x00000010 578*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_DEGLITCH_EN_MASK 0x20000000L 579*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_DEGLITCH_EN__SHIFT 0x0000001d 580*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_EN_MASK 0x00000001L 581*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_EN__SHIFT 0x00000000 582*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_HPD_SEL_MASK 0x00700000L 583*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_HPD_SEL__SHIFT 0x00000014 584*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON_MASK 0x00010000L 585*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_IGNORE_HPD_DISCON__SHIFT 0x00000010 586*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_IMPCAL_REQ_EN_MASK 0x01000000L 587*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_IMPCAL_REQ_EN__SHIFT 0x00000018 588*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_LS_READ_EN_MASK 0x00000100L 589*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_LS_READ_EN__SHIFT 0x00000008 590*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE_MASK 0x00001000L 591*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_LS_UPDATE_DISABLE__SHIFT 0x0000000c 592*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_MODE_DET_EN_MASK 0x00040000L 593*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_MODE_DET_EN__SHIFT 0x00000012 594*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_TEST_MODE_MASK 0x10000000L 595*b843c749SSergey Zigachev #define AUX_CONTROL__AUX_TEST_MODE__SHIFT 0x0000001c 596*b843c749SSergey Zigachev #define AUX_CONTROL__SPARE_0_MASK 0x40000000L 597*b843c749SSergey Zigachev #define AUX_CONTROL__SPARE_0__SHIFT 0x0000001e 598*b843c749SSergey Zigachev #define AUX_CONTROL__SPARE_1_MASK 0x80000000L 599*b843c749SSergey Zigachev #define AUX_CONTROL__SPARE_1__SHIFT 0x0000001f 600*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT_MASK 0x00020000L 601*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT__SHIFT 0x00000011 602*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START_MASK 0x00040000L 603*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_START__SHIFT 0x00000012 604*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP_MASK 0x00080000L 605*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_ALLOW_BELOW_THRESHOLD_STOP__SHIFT 0x00000013 606*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK 0x70000000L 607*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD__SHIFT 0x0000001c 608*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN_MASK 0x00003000L 609*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_HALF_SYM_DETECT_LEN__SHIFT 0x0000000c 610*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN_MASK 0x00300000L 611*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_PHASE_DETECT_LEN__SHIFT 0x00000014 612*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW_MASK 0x00000700L 613*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_RECEIVE_WINDOW__SHIFT 0x00000008 614*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW_MASK 0x00000070L 615*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_START_WINDOW__SHIFT 0x00000004 616*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN_MASK 0x07000000L 617*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_TIMEOUT_LEN__SHIFT 0x00000018 618*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN_MASK 0x00010000L 619*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL0__AUX_RX_TRANSITION_FILTER_EN__SHIFT 0x00000010 620*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK 0x000000ffL 621*b843c749SSergey Zigachev #define AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 0x00000000 622*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT_MASK 0x001f0000L 623*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_FRACT__SHIFT 0x00000010 624*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD_MASK 0x3fe00000L 625*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_HALF_SYM_PERIOD__SHIFT 0x00000015 626*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_STATE_MASK 0x00000007L 627*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_STATE__SHIFT 0x00000000 628*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT_MASK 0x00001f00L 629*b843c749SSergey Zigachev #define AUX_DPHY_RX_STATUS__AUX_RX_SYNC_VALID_COUNT__SHIFT 0x00000008 630*b843c749SSergey Zigachev #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN_MASK 0x00000007L 631*b843c749SSergey Zigachev #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_LEN__SHIFT 0x00000000 632*b843c749SSergey Zigachev #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS_MASK 0x00003f00L 633*b843c749SSergey Zigachev #define AUX_DPHY_TX_CONTROL__AUX_TX_PRECHARGE_SYMBOLS__SHIFT 0x00000008 634*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE_MASK 0x00000030L 635*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_RATE__SHIFT 0x00000004 636*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV_MASK 0x01ff0000L 637*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_DIV__SHIFT 0x00000010 638*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL_MASK 0x00000001L 639*b843c749SSergey Zigachev #define AUX_DPHY_TX_REF_CONTROL__AUX_TX_REF_SEL__SHIFT 0x00000000 640*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE_MASK 0x00000001L 641*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT 0x00000000 642*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD_MASK 0x01ff0000L 643*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_HALF_SYM_PERIOD__SHIFT 0x00000010 644*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_STATE_MASK 0x00000070L 645*b843c749SSergey Zigachev #define AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT 0x00000004 646*b843c749SSergey Zigachev #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN_MASK 0x00000001L 647*b843c749SSergey Zigachev #define AUX_GTC_SYNC_CONTROL__AUX_GTC_SYNC_EN__SHIFT 0x00000000 648*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK_MASK 0x00000020L 649*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_ACK__SHIFT 0x00000005 650*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT_MASK 0x00000010L 651*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_INT__SHIFT 0x00000004 652*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK_MASK 0x00000040L 653*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_LS_DONE_MASK__SHIFT 0x00000006 654*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK_MASK 0x00000002L 655*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_ACK__SHIFT 0x00000001 656*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT_MASK 0x00000001L 657*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_INT__SHIFT 0x00000000 658*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK_MASK 0x00000004L 659*b843c749SSergey Zigachev #define AUX_INTERRUPT_CONTROL__AUX_SW_DONE_MASK__SHIFT 0x00000002 660*b843c749SSergey Zigachev #define AUX_LS_DATA__AUX_LS_DATA_MASK 0x0000ff00L 661*b843c749SSergey Zigachev #define AUX_LS_DATA__AUX_LS_DATA__SHIFT 0x00000008 662*b843c749SSergey Zigachev #define AUX_LS_DATA__AUX_LS_INDEX_MASK 0x001f0000L 663*b843c749SSergey Zigachev #define AUX_LS_DATA__AUX_LS_INDEX__SHIFT 0x00000010 664*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_CP_IRQ_MASK 0x20000000L 665*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_CP_IRQ__SHIFT 0x0000001d 666*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_DONE_MASK 0x00000001L 667*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_DONE__SHIFT 0x00000000 668*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_HPD_DISCON_MASK 0x00000200L 669*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_HPD_DISCON__SHIFT 0x00000009 670*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE_MASK 0x00000800L 671*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_NON_AUX_MODE__SHIFT 0x0000000b 672*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT_MASK 0x1f000000L 673*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_REPLY_BYTE_COUNT__SHIFT 0x00000018 674*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_REQ_MASK 0x00000002L 675*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_REQ__SHIFT 0x00000001 676*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START_MASK 0x00080000L 677*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_INVALID_START__SHIFT 0x00000013 678*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP_MASK 0x00004000L 679*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_INVALID_STOP__SHIFT 0x0000000e 680*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL_MASK 0x00001000L 681*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 682*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW_MASK 0x00000100L 683*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_OVERFLOW__SHIFT 0x00000008 684*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE_MASK 0x00000400L 685*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_PARTIAL_BYTE__SHIFT 0x0000000a 686*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H_MASK 0x00400000L 687*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_H__SHIFT 0x00000016 688*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L_MASK 0x00800000L 689*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_INVALID_L__SHIFT 0x00000017 690*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET_MASK 0x00100000L 691*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_RECV_NO_DET__SHIFT 0x00000014 692*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H_MASK 0x00040000L 693*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_H__SHIFT 0x00000012 694*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L_MASK 0x00020000L 695*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_SYNC_INVALID_L__SHIFT 0x00000011 696*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_MASK 0x00000080L 697*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT__SHIFT 0x00000007 698*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE_MASK 0x00000070L 699*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_RX_TIMEOUT_STATE__SHIFT 0x00000004 700*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK_MASK 0x80000000L 701*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_UPDATED_ACK__SHIFT 0x0000001f 702*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_UPDATED_MASK 0x40000000L 703*b843c749SSergey Zigachev #define AUX_LS_STATUS__AUX_LS_UPDATED__SHIFT 0x0000001e 704*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK_MASK 0x00000400L 705*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_AK__SHIFT 0x0000000a 706*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_CALOUT_ERROR_MASK 0x00000200L 707*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_CALOUT_ERROR__SHIFT 0x00000009 708*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT_MASK 0x00000100L 709*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_CALOUT__SHIFT 0x00000008 710*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE_MASK 0x00000001L 711*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_ENABLE__SHIFT 0x00000000 712*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 713*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 714*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE_MASK 0x0f000000L 715*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_OVERRIDE__SHIFT 0x00000018 716*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY_MASK 0x00f00000L 717*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_STEP_DELAY__SHIFT 0x00000014 718*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE_MASK 0x000f0000L 719*b843c749SSergey Zigachev #define AUXN_IMPCAL__AUXN_IMPCAL_VALUE__SHIFT 0x00000010 720*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK_MASK 0x00000400L 721*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_AK__SHIFT 0x0000000a 722*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_CALOUT_ERROR_MASK 0x00000200L 723*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_CALOUT_ERROR__SHIFT 0x00000009 724*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT_MASK 0x00000100L 725*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_CALOUT__SHIFT 0x00000008 726*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE_MASK 0x00000001L 727*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_ENABLE__SHIFT 0x00000000 728*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE_MASK 0x10000000L 729*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_ENABLE__SHIFT 0x0000001c 730*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE_MASK 0x0f000000L 731*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_OVERRIDE__SHIFT 0x00000018 732*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY_MASK 0x00f00000L 733*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_STEP_DELAY__SHIFT 0x00000014 734*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE_MASK 0x000f0000L 735*b843c749SSergey Zigachev #define AUXP_IMPCAL__AUXP_IMPCAL_VALUE__SHIFT 0x00000010 736*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_LS_READ_TRIG_MASK 0x00000004L 737*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_LS_READ_TRIG__SHIFT 0x00000002 738*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_GO_MASK 0x00000001L 739*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_GO__SHIFT 0x00000000 740*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_START_DELAY_MASK 0x000000f0L 741*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_START_DELAY__SHIFT 0x00000004 742*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_WR_BYTES_MASK 0x001f0000L 743*b843c749SSergey Zigachev #define AUX_SW_CONTROL__AUX_SW_WR_BYTES__SHIFT 0x00000010 744*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE_MASK 0x80000000L 745*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_AUTOINCREMENT_DISABLE__SHIFT 0x0000001f 746*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_DATA_MASK 0x0000ff00L 747*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_DATA_RW_MASK 0x00000001L 748*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_DATA_RW__SHIFT 0x00000000 749*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_DATA__SHIFT 0x00000008 750*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_INDEX_MASK 0x001f0000L 751*b843c749SSergey Zigachev #define AUX_SW_DATA__AUX_SW_INDEX__SHIFT 0x00000010 752*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_ARB_STATUS_MASK 0xc0000000L 753*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_ARB_STATUS__SHIFT 0x0000001e 754*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_DONE_MASK 0x00000001L 755*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_DONE__SHIFT 0x00000000 756*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_HPD_DISCON_MASK 0x00000200L 757*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_HPD_DISCON__SHIFT 0x00000009 758*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE_MASK 0x00000800L 759*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_NON_AUX_MODE__SHIFT 0x0000000b 760*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT_MASK 0x1f000000L 761*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_REPLY_BYTE_COUNT__SHIFT 0x00000018 762*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_REQ_MASK 0x00000002L 763*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_REQ__SHIFT 0x00000001 764*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START_MASK 0x00080000L 765*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_INVALID_START__SHIFT 0x00000013 766*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP_MASK 0x00004000L 767*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_INVALID_STOP__SHIFT 0x0000000e 768*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL_MASK 0x00001000L 769*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_MIN_COUNT_VIOL__SHIFT 0x0000000c 770*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW_MASK 0x00000100L 771*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_OVERFLOW__SHIFT 0x00000008 772*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE_MASK 0x00000400L 773*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_PARTIAL_BYTE__SHIFT 0x0000000a 774*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H_MASK 0x00400000L 775*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_H__SHIFT 0x00000016 776*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK 0x00800000L 777*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L__SHIFT 0x00000017 778*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET_MASK 0x00100000L 779*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_RECV_NO_DET__SHIFT 0x00000014 780*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H_MASK 0x00040000L 781*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_H__SHIFT 0x00000012 782*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L_MASK 0x00020000L 783*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_SYNC_INVALID_L__SHIFT 0x00000011 784*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_MASK 0x00000080L 785*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT__SHIFT 0x00000007 786*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE_MASK 0x00000070L 787*b843c749SSergey Zigachev #define AUX_SW_STATUS__AUX_SW_RX_TIMEOUT_STATE__SHIFT 0x00000004 788*b843c749SSergey Zigachev #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER_MASK 0xffffffffL 789*b843c749SSergey Zigachev #define AZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER__APPLICATION_POSITION_IN_CYCLIC_BUFFER__SHIFT 0x00000000 790*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE_MASK 0xffff0000L 791*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_MODULE__SHIFT 0x00000010 792*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE_MASK 0x0000ffffL 793*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO__AZALIA_AUDIO_DTO_PHASE__SHIFT 0x00000000 794*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO_MASK 0x00000300L 795*b843c749SSergey Zigachev #define AZALIA_AUDIO_DTO_CONTROL__AZALIA_AUDIO_FORCE_DTO__SHIFT 0x00000008 796*b843c749SSergey Zigachev #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS_MASK 0x00000030L 797*b843c749SSergey Zigachev #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_ISOCHRONOUS__SHIFT 0x00000004 798*b843c749SSergey Zigachev #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP_MASK 0x00000003L 799*b843c749SSergey Zigachev #define AZALIA_BDL_DMA_CONTROL__BDL_DMA_NON_SNOOP__SHIFT 0x00000000 800*b843c749SSergey Zigachev #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG_MASK 0xffffffffL 801*b843c749SSergey Zigachev #define AZALIA_CONTROLLER_DEBUG__CONTROLLER_DEBUG__SHIFT 0x00000000 802*b843c749SSergey Zigachev #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS_MASK 0x00000010L 803*b843c749SSergey Zigachev #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_ISOCHRONOUS__SHIFT 0x00000004 804*b843c749SSergey Zigachev #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP_MASK 0x00000001L 805*b843c749SSergey Zigachev #define AZALIA_CORB_DMA_CONTROL__CORB_DMA_NON_SNOOP__SHIFT 0x00000000 806*b843c749SSergey Zigachev #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT_MASK 0xffffffffL 807*b843c749SSergey Zigachev #define AZALIA_CUMULATIVE_LATENCY_COUNT__AZALIA_CUMULATIVE_LATENCY_COUNT__SHIFT 0x00000000 808*b843c749SSergey Zigachev #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT_MASK 0xffffffffL 809*b843c749SSergey Zigachev #define AZALIA_CUMULATIVE_REQUEST_COUNT__AZALIA_CUMULATIVE_REQUEST_COUNT__SHIFT 0x00000000 810*b843c749SSergey Zigachev #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE_MASK 0x00000001L 811*b843c749SSergey Zigachev #define AZALIA_CYCLIC_BUFFER_SYNC__CYCLIC_BUFFER_SYNC_ENABLE__SHIFT 0x00000000 812*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD_MASK 0x00010000L 813*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__AZALIA_IOC_GENERATION_METHOD__SHIFT 0x00000010 814*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL_MASK 0x00020000L 815*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__AZALIA_UNDERFLOW_CONTROL__SHIFT 0x00000011 816*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS_MASK 0x00000030L 817*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_ISOCHRONOUS__SHIFT 0x00000004 818*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP_MASK 0x00000003L 819*b843c749SSergey Zigachev #define AZALIA_DATA_DMA_CONTROL__DATA_DMA_NON_SNOOP__SHIFT 0x00000000 820*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT_MASK 0x00000070L 821*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__COMPRESSED_CHANNEL_COUNT__SHIFT 0x00000004 822*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT_MASK 0x00000007L 823*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL__HBR_CHANNEL_COUNT__SHIFT 0x00000000 824*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 825*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 826*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 827*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 828*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 829*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 830*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 831*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 832*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 833*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 834*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 835*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 836*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 837*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 838*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 839*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 840*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 841*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 842*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 843*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 844*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 845*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 846*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 847*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 848*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 849*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 850*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 851*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 852*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 853*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 854*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 855*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 856*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 857*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 858*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 859*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 860*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE_MASK 0x00000001L 861*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING__PRESENTATION_TIME_EMBEDDING_ENABLE__SHIFT 0x00000000 862*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 863*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 864*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 865*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 866*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 867*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 868*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 869*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 870*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 871*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 872*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 873*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 874*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 875*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 876*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 877*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 878*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 879*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 880*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 881*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 882*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 883*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 884*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 885*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 886*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 887*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 888*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 889*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 890*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 891*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 892*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 893*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 894*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 895*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 896*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 897*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 898*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_PIN_DEBUG__AZALIA_DEBUG__SHIFT 0x00000000 899*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 900*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 901*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 902*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 903*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG_MASK 0xffffffffL 904*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_DEBUG__CODEC_DEBUG__SHIFT 0x00000000 905*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA_MASK 0xffffffffL 906*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_DATA__AZALIA_ENDPOINT_REG_DATA__SHIFT 0x00000000 907*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX_MASK 0x000000ffL 908*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_INDEX__SHIFT 0x00000000 909*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK 0x00000100L 910*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN__SHIFT 0x00000008 911*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 912*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 913*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 914*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 915*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 916*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 917*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 918*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 919*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 920*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 921*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 922*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 923*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 924*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 925*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 926*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 927*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 928*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 929*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 930*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 931*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 932*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 933*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 934*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 935*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 936*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 937*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 938*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 939*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 940*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 941*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 942*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 943*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 944*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 945*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 946*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 947*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 948*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 949*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS_MASK 0x00000007L 950*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT 0x00000000 951*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 952*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 953*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 954*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 955*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 956*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 957*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS_MASK 0x00000007L 958*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__MAX_CHANNELS__SHIFT 0x00000000 959*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 960*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 961*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 962*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 963*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS_MASK 0x00000007L 964*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__MAX_CHANNELS__SHIFT 0x00000000 965*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 966*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 967*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 968*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 969*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS_MASK 0x00000007L 970*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__MAX_CHANNELS__SHIFT 0x00000000 971*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 972*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 973*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 974*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 975*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS_MASK 0x00000007L 976*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__MAX_CHANNELS__SHIFT 0x00000000 977*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 978*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 979*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 980*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 981*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS_MASK 0x00000007L 982*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__MAX_CHANNELS__SHIFT 0x00000000 983*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 984*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 985*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 986*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 987*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS_MASK 0x00000007L 988*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__MAX_CHANNELS__SHIFT 0x00000000 989*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 990*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 991*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 992*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 993*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS_MASK 0x00000007L 994*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__MAX_CHANNELS__SHIFT 0x00000000 995*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 996*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 997*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 998*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 999*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS_MASK 0x00000007L 1000*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__MAX_CHANNELS__SHIFT 0x00000000 1001*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1002*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1003*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1004*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1005*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS_MASK 0x00000007L 1006*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__MAX_CHANNELS__SHIFT 0x00000000 1007*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1008*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1009*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1010*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1011*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS_MASK 0x00000007L 1012*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__MAX_CHANNELS__SHIFT 0x00000000 1013*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1014*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1015*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1016*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1017*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS_MASK 0x00000007L 1018*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__MAX_CHANNELS__SHIFT 0x00000000 1019*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1020*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1021*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1022*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1023*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS_MASK 0x00000007L 1024*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__MAX_CHANNELS__SHIFT 0x00000000 1025*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1026*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1027*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1028*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1029*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS_MASK 0x00000007L 1030*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__MAX_CHANNELS__SHIFT 0x00000000 1031*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1032*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1033*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION_MASK 0x0000ff00L 1034*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__CHANNEL_ALLOCATION__SHIFT 0x00000008 1035*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT_MASK 0x80000000L 1036*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DOWN_MIX_INHIBIT__SHIFT 0x0000001f 1037*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK 0x00020000L 1038*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION__SHIFT 0x00000011 1039*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO_MASK 0x00fc0000L 1040*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__EXTRA_CONNECTION_INFO__SHIFT 0x00000012 1041*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK 0x00010000L 1042*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION__SHIFT 0x00000010 1043*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT_MASK 0x78000000L 1044*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__LEVEL_SHIFT__SHIFT 0x0000001b 1045*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK 0x0000007fL 1046*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT 0x00000000 1047*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK 0x80000000L 1048*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED__SHIFT 0x0000001f 1049*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1050*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1051*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1052*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1053*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE_MASK 0x00000002L 1054*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1055*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID_MASK 0x0000f000L 1056*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x0000000c 1057*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE_MASK 0x00000100L 1058*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_ENABLE__SHIFT 0x00000008 1059*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE_MASK 0x00000200L 1060*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL3_MUTE__SHIFT 0x00000009 1061*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID_MASK 0x00f00000L 1062*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000014 1063*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE_MASK 0x00010000L 1064*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_ENABLE__SHIFT 0x00000010 1065*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE_MASK 0x00020000L 1066*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL5_MUTE__SHIFT 0x00000011 1067*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID_MASK 0xf0000000L 1068*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x0000001c 1069*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE_MASK 0x01000000L 1070*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_ENABLE__SHIFT 0x00000018 1071*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE_MASK 0x02000000L 1072*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2__MULTICHANNEL7_MUTE__SHIFT 0x00000019 1073*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1074*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1075*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1076*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1077*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1078*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1079*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x0000f000L 1080*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x0000000c 1081*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000100L 1082*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000008 1083*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000200L 1084*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000009 1085*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x00f00000L 1086*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000014 1087*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00010000L 1088*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000010 1089*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00020000L 1090*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000011 1091*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0xf0000000L 1092*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x0000001c 1093*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x01000000L 1094*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000018 1095*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE_MASK 0x02000000L 1096*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000019 1097*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1098*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1099*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1100*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1101*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1102*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1103*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1104*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1105*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1106*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1107*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1108*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1109*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1110*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1111*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1112*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1113*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1114*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1115*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE_MASK 0x00000001L 1116*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_CAPABLE__SHIFT 0x00000000 1117*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE_MASK 0x00000010L 1118*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR__HBR_ENABLE__SHIFT 0x00000004 1119*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1120*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1121*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1122*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1123*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1124*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1125*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID_MASK 0x0000ffffL 1126*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__MANUFACTURER_ID__SHIFT 0x00000000 1127*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID_MASK 0xffff0000L 1128*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0__PRODUCT_ID__SHIFT 0x00000010 1129*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1130*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1131*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0_MASK 0xffffffffL 1132*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2__PORT_ID0__SHIFT 0x00000000 1133*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1_MASK 0xffffffffL 1134*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3__PORT_ID1__SHIFT 0x00000000 1135*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0_MASK 0x000000ffL 1136*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION0__SHIFT 0x00000000 1137*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1_MASK 0x0000ff00L 1138*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION1__SHIFT 0x00000008 1139*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2_MASK 0x00ff0000L 1140*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION2__SHIFT 0x00000010 1141*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3_MASK 0xff000000L 1142*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4__DESCRIPTION3__SHIFT 0x00000018 1143*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4_MASK 0x000000ffL 1144*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION4__SHIFT 0x00000000 1145*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5_MASK 0x0000ff00L 1146*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION5__SHIFT 0x00000008 1147*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6_MASK 0x00ff0000L 1148*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION6__SHIFT 0x00000010 1149*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7_MASK 0xff000000L 1150*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5__DESCRIPTION7__SHIFT 0x00000018 1151*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10_MASK 0x00ff0000L 1152*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION10__SHIFT 0x00000010 1153*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11_MASK 0xff000000L 1154*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION11__SHIFT 0x00000018 1155*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8_MASK 0x000000ffL 1156*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION8__SHIFT 0x00000000 1157*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9_MASK 0x0000ff00L 1158*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6__DESCRIPTION9__SHIFT 0x00000008 1159*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12_MASK 0x000000ffL 1160*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION12__SHIFT 0x00000000 1161*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13_MASK 0x0000ff00L 1162*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION13__SHIFT 0x00000008 1163*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14_MASK 0x00ff0000L 1164*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION14__SHIFT 0x00000010 1165*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15_MASK 0xff000000L 1166*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7__DESCRIPTION15__SHIFT 0x00000018 1167*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16_MASK 0x000000ffL 1168*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION16__SHIFT 0x00000000 1169*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17_MASK 0x0000ff00L 1170*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8__DESCRIPTION17__SHIFT 0x00000008 1171*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1172*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1173*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE_MASK 0x10000000L 1174*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_FORCE__SHIFT 0x0000001c 1175*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD_MASK 0x03ffffffL 1176*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE__UNSOLICITED_RESPONSE_PAYLOAD__SHIFT 0x00000000 1177*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1178*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1179*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1180*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1181*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1182*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1183*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1184*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1185*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1186*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1187*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1188*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1189*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1190*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1191*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1192*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1193*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1194*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1195*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1196*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1197*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1198*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1199*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1200*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1201*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1202*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1203*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1204*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1205*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1206*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1207*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1208*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1209*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1210*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1211*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1212*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1213*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1214*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1215*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1216*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1217*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1218*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1219*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1220*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1221*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1222*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1223*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1224*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1225*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1226*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1227*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1228*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1229*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW_MASK 0x0000003fL 1230*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_RESYNC_FIFO_CONTROL__RESYNC_FIFO_STARTUP_KEEPOUT_WINDOW__SHIFT 0x00000000 1231*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1232*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1233*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1234*b843c749SSergey Zigachev #define AZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1235*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1236*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1237*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1238*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1239*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1240*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1241*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1242*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1243*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1244*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1245*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1246*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1247*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1248*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1249*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1250*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1251*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1252*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1253*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1254*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1255*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1256*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1257*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1258*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1259*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1260*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1261*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1262*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1263*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1264*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1265*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1266*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1267*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1268*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1269*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1270*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1271*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1272*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1273*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1274*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1275*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1276*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1277*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1278*b843c749SSergey Zigachev #define AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1279*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID_MASK 0x0000000fL 1280*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__CHANNEL_ID__SHIFT 0x00000000 1281*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID_MASK 0x000000f0L 1282*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID__STREAM_ID__SHIFT 0x00000004 1283*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE_MASK 0x00000070L 1284*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__BITS_PER_SAMPLE__SHIFT 0x00000004 1285*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS_MASK 0x0000000fL 1286*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__NUMBER_OF_CHANNELS__SHIFT 0x00000000 1287*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR_MASK 0x00000700L 1288*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_DIVISOR__SHIFT 0x00000008 1289*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE_MASK 0x00003800L 1290*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_MULTIPLE__SHIFT 0x0000000b 1291*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE_MASK 0x00004000L 1292*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__SAMPLE_BASE_RATE__SHIFT 0x0000000e 1293*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_MASK 0x00008000L 1294*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R_MASK 0x00008000L 1295*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE_R__SHIFT 0x0000000f 1296*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT__STREAM_TYPE__SHIFT 0x0000000f 1297*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC_MASK 0x0000007fL 1298*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2__CC__SHIFT 0x00000000 1299*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE_MASK 0x00000080L 1300*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3__KEEPALIVE__SHIFT 0x00000007 1301*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC_MASK 0x00007f00L 1302*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__CC__SHIFT 0x00000008 1303*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY_MASK 0x00000010L 1304*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__COPY__SHIFT 0x00000004 1305*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN_MASK 0x00000001L 1306*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__DIGEN__SHIFT 0x00000000 1307*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE_MASK 0x00800000L 1308*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__KEEPALIVE__SHIFT 0x00000017 1309*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L_MASK 0x00000080L 1310*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__L__SHIFT 0x00000007 1311*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO_MASK 0x00000020L 1312*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__NON_AUDIO__SHIFT 0x00000005 1313*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE_MASK 0x00000008L 1314*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRE__SHIFT 0x00000003 1315*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO_MASK 0x00000040L 1316*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__PRO__SHIFT 0x00000006 1317*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG_MASK 0x00000004L 1318*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__VCFG__SHIFT 0x00000002 1319*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V_MASK 0x00000002L 1320*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER__V__SHIFT 0x00000001 1321*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE_MASK 0x000000ffL 1322*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE__RAMP_RATE__SHIFT 0x00000000 1323*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1324*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1325*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1326*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1327*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1328*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1329*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1330*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1331*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1332*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1333*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE_MASK 0x00000010L 1334*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__FORMAT_OVERRIDE__SHIFT 0x00000004 1335*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1336*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1337*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1338*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1339*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1340*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1341*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1342*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1343*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1344*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1345*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1346*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1347*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1348*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1349*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1350*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1351*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS_MASK 0xffffffffL 1352*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS__STREAM_FORMATS__SHIFT 0x00000000 1353*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1354*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1355*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1356*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1357*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY_MASK 0x00700000L 1358*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CAPABILITY__SHIFT 0x00000014 1359*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL_MASK 0x00000003L 1360*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL__STRIPE_CONTROL__SHIFT 0x00000000 1361*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION_MASK 0x0000003fL 1362*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION__CONVERTER_SYNCHRONIZATION__SHIFT 0x00000000 1363*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK_MASK 0x00000200L 1364*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__CLKSTOPOK__SHIFT 0x00000009 1365*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT_MASK 0x000000f0L 1366*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_ACT__SHIFT 0x00000004 1367*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET_MASK 0x0000000fL 1368*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SET__SHIFT 0x00000000 1369*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET_MASK 0x00000400L 1370*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE__POWER_STATE_SETTINGS_RESET__SHIFT 0x0000000a 1371*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET_MASK 0x00000001L 1372*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET__CODEC_RESET__SHIFT 0x00000000 1373*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1_MASK 0x000000ffL 1374*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000000 1375*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2_MASK 0x000000ffL 1376*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000000 1377*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3_MASK 0x000000ffL 1378*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000000 1379*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0_MASK 0x000000ffL 1380*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE0__SHIFT 0x00000000 1381*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1_MASK 0x0000ff00L 1382*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE1__SHIFT 0x00000008 1383*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2_MASK 0x00ff0000L 1384*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE2__SHIFT 0x00000010 1385*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3_MASK 0xff000000L 1386*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID__SUBSYSTEM_ID_BYTE3__SHIFT 0x00000018 1387*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_MASK 0xffffffffL 1388*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__AZALIA_CODEC_FUNCTION_PARAMETER_GROUP_TYPE__SHIFT 0x00000000 1389*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES_MASK 0x3fffffffL 1390*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__AZALIA_CODEC_FUNCTION_PARAMETER_POWER_STATES__SHIFT 0x00000000 1391*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP_MASK 0x40000000L 1392*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__CLKSTOP__SHIFT 0x0000001e 1393*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS_MASK 0x80000000L 1394*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES__EPSS__SHIFT 0x0000001f 1395*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_MASK 0xffffffffL 1396*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__AZALIA_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS__SHIFT 0x00000000 1397*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1398*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1399*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES_MASK 0x001f0000L 1400*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_BIT_CAPABILITIES__SHIFT 0x00000010 1401*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES_MASK 0x00000fffL 1402*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES__AUDIO_RATE_CAPABILITIES__SHIFT 0x00000000 1403*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO_MASK 0xffffffffL 1404*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_ASSOCIATION_INFO__ASSOCIATION_INFO__SHIFT 0x00000000 1405*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR_MASK 0xffffffffL 1406*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA__DESCRIPTOR__SHIFT 0x00000000 1407*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2_MASK 0x00ff0000L 1408*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__DESCRIPTOR_BYTE_2__SHIFT 0x00000010 1409*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE_MASK 0x00000078L 1410*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__FORMAT_CODE__SHIFT 0x00000003 1411*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS_MASK 0x00000007L 1412*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__MAX_CHANNELS__SHIFT 0x00000000 1413*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_MASK 0x0000ff00L 1414*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES__SHIFT 0x00000008 1415*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO_MASK 0xff000000L 1416*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR__SUPPORTED_FREQUENCIES_STEREO__SHIFT 0x00000018 1417*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA_MASK 0xffffffffL 1418*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA__SINK_DATA__SHIFT 0x00000000 1419*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX_MASK 0x000000ffL 1420*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX__SINK_INFO_INDEX__SHIFT 0x00000000 1421*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION_MASK 0x000000ffL 1422*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION__CHANNEL_ALLOCATION__SHIFT 0x00000000 1423*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT_MASK 0x00000080L 1424*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__DOWN_MIX_INHIBIT__SHIFT 0x00000007 1425*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT_MASK 0x00000078L 1426*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO__LEVEL_SHIFT__SHIFT 0x00000003 1427*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE_MASK 0x00000001L 1428*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_CAPABLE__SHIFT 0x00000000 1429*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE_MASK 0x00000010L 1430*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_HBR__HBR_ENABLE__SHIFT 0x00000004 1431*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC_MASK 0x0000ff00L 1432*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__AUDIO_LIPSYNC__SHIFT 0x00000008 1433*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC_MASK 0x000000ffL 1434*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC__VIDEO_LIPSYNC__SHIFT 0x00000000 1435*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID_MASK 0x0000ffffL 1436*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID__MANUFACTURER_ID__SHIFT 0x00000000 1437*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID_MASK 0x000000f0L 1438*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_CHANNEL_ID__SHIFT 0x00000004 1439*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE_MASK 0x00000001L 1440*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_ENABLE__SHIFT 0x00000000 1441*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE_MASK 0x00000002L 1442*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE__MULTICHANNEL01_MUTE__SHIFT 0x00000001 1443*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID_MASK 0x000000f0L 1444*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_CHANNEL_ID__SHIFT 0x00000004 1445*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE_MASK 0x00000001L 1446*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_ENABLE__SHIFT 0x00000000 1447*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE_MASK 0x00000002L 1448*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE__MULTICHANNEL1_MUTE__SHIFT 0x00000001 1449*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID_MASK 0x000000f0L 1450*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_CHANNEL_ID__SHIFT 0x00000004 1451*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE_MASK 0x00000001L 1452*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_ENABLE__SHIFT 0x00000000 1453*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE_MASK 0x00000002L 1454*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE__MULTICHANNEL23_MUTE__SHIFT 0x00000001 1455*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID_MASK 0x000000f0L 1456*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_CHANNEL_ID__SHIFT 0x00000004 1457*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE_MASK 0x00000001L 1458*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_ENABLE__SHIFT 0x00000000 1459*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE_MASK 0x00000002L 1460*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE__MULTICHANNEL3_MUTE__SHIFT 0x00000001 1461*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID_MASK 0x000000f0L 1462*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_CHANNEL_ID__SHIFT 0x00000004 1463*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE_MASK 0x00000001L 1464*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_ENABLE__SHIFT 0x00000000 1465*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE_MASK 0x00000002L 1466*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE__MULTICHANNEL45_MUTE__SHIFT 0x00000001 1467*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID_MASK 0x000000f0L 1468*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_CHANNEL_ID__SHIFT 0x00000004 1469*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE_MASK 0x00000001L 1470*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_ENABLE__SHIFT 0x00000000 1471*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE_MASK 0x00000002L 1472*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE__MULTICHANNEL5_MUTE__SHIFT 0x00000001 1473*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID_MASK 0x000000f0L 1474*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_CHANNEL_ID__SHIFT 0x00000004 1475*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE_MASK 0x00000001L 1476*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_ENABLE__SHIFT 0x00000000 1477*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE_MASK 0x00000002L 1478*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE__MULTICHANNEL67_MUTE__SHIFT 0x00000001 1479*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID_MASK 0x000000f0L 1480*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_CHANNEL_ID__SHIFT 0x00000004 1481*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE_MASK 0x00000001L 1482*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_ENABLE__SHIFT 0x00000000 1483*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE_MASK 0x00000002L 1484*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE__MULTICHANNEL7_MUTE__SHIFT 0x00000001 1485*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE_MASK 0x00000001L 1486*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE__MULTICHANNEL_MODE__SHIFT 0x00000000 1487*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID_MASK 0xffffffffL 1488*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID0__PORTID__SHIFT 0x00000000 1489*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID_MASK 0xffffffffL 1490*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PORTID1__PORTID__SHIFT 0x00000000 1491*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID_MASK 0x0000ffffL 1492*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID__PRODUCT_ID__SHIFT 0x00000000 1493*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR_MASK 0x000000f0L 1494*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__COLOR__SHIFT 0x00000004 1495*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC_MASK 0x0000000fL 1496*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2__MISC__SHIFT 0x00000000 1497*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE_MASK 0x0000000fL 1498*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__CONNECTION_TYPE__SHIFT 0x00000000 1499*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE_MASK 0x000000f0L 1500*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3__DEFAULT_DEVICE__SHIFT 0x00000004 1501*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION_MASK 0x0000003fL 1502*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__LOCATION__SHIFT 0x00000000 1503*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY_MASK 0x000000c0L 1504*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4__PORT_CONNECTIVITY__SHIFT 0x00000006 1505*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR_MASK 0x0000f000L 1506*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__COLOR__SHIFT 0x0000000c 1507*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE_MASK 0x000f0000L 1508*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__CONNECTION_TYPE__SHIFT 0x00000010 1509*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION_MASK 0x000000f0L 1510*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_ASSOCIATION__SHIFT 0x00000004 1511*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE_MASK 0x00f00000L 1512*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__DEFAULT_DEVICE__SHIFT 0x00000014 1513*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION_MASK 0x3f000000L 1514*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__LOCATION__SHIFT 0x00000018 1515*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC_MASK 0x00000f00L 1516*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__MISC__SHIFT 0x00000008 1517*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK 0xc0000000L 1518*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT 0x0000001e 1519*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE_MASK 0x0000000fL 1520*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__SEQUENCE__SHIFT 0x00000000 1521*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY_MASK 0xffffffffL 1522*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY__CONNECTION_LIST_ENTRY__SHIFT 0x00000000 1523*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE_MASK 0x7fffffffL 1524*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__IMPEDANCE_SENSE__SHIFT 0x00000000 1525*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT_MASK 0x80000000L 1526*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE__PRESENCE_DETECT__SHIFT 0x0000001f 1527*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION_MASK 0x00000200L 1528*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__DP_CONNECTION__SHIFT 0x00000009 1529*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO_MASK 0x0000fc00L 1530*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__EXTRA_CONNECTION_INFO__SHIFT 0x0000000a 1531*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION_MASK 0x00000100L 1532*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__HDMI_CONNECTION__SHIFT 0x00000008 1533*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION_MASK 0x0000007fL 1534*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION__SPEAKER_ALLOCATION__SHIFT 0x00000000 1535*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN_MASK 0x000000ffL 1536*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN__SINK_DESCRIPTION_LEN__SHIFT 0x00000000 1537*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE_MASK 0x00000080L 1538*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__ENABLE__SHIFT 0x00000007 1539*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG_MASK 0x0000003fL 1540*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE__TAG__SHIFT 0x00000000 1541*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE_MASK 0x00000040L 1542*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL__OUT_ENABLE__SHIFT 0x00000006 1543*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE_MASK 0x00000008L 1544*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AMPLIFIER_PARAMETER_OVERRIDE__SHIFT 0x00000003 1545*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES_MASK 0x00000001L 1546*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_CHANNEL_CAPABILITIES__SHIFT 0x00000000 1547*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY_MASK 0x000f0000L 1548*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__AUDIO_WIDGET_CAPABILITIES_DELAY__SHIFT 0x00000010 1549*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST_MASK 0x00000100L 1550*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__CONNECTION_LIST__SHIFT 0x00000008 1551*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL_MASK 0x00000200L 1552*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__DIGITAL__SHIFT 0x00000009 1553*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT_MASK 0x00000002L 1554*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__INPUT_AMPLIFIER_PRESENT__SHIFT 0x00000001 1555*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP_MASK 0x00000800L 1556*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__LR_SWAP__SHIFT 0x0000000b 1557*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT_MASK 0x00000004L 1558*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__OUTPUT_AMPLIFIER_PRESENT__SHIFT 0x00000002 1559*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL_MASK 0x00000400L 1560*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0x0000000a 1561*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET_MASK 0x00000040L 1562*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__PROCESSING_WIDGET__SHIFT 0x00000006 1563*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE_MASK 0x00000020L 1564*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__STRIPE__SHIFT 0x00000005 1565*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE_MASK 0x00f00000L 1566*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__TYPE__SHIFT 0x00000014 1567*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY_MASK 0x00000080L 1568*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__UNSOLICITED_RESPONSE_CAPABILITY__SHIFT 0x00000007 1569*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS_MASK 0x00000040L 1570*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__BALANCED_I_O_PINS__SHIFT 0x00000006 1571*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP_MASK 0x01000000L 1572*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__DP__SHIFT 0x00000018 1573*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE_MASK 0x00010000L 1574*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__EAPD_CAPABLE__SHIFT 0x00000010 1575*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI_MASK 0x00000080L 1576*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HDMI__SHIFT 0x00000007 1577*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE_MASK 0x00000008L 1578*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__HEADPHONE_DRIVE_CAPABLE__SHIFT 0x00000003 1579*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE_MASK 0x00000001L 1580*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__IMPEDANCE_SENSE_CAPABLE__SHIFT 0x00000000 1581*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE_MASK 0x00000020L 1582*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__INPUT_CAPABLE__SHIFT 0x00000005 1583*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY_MASK 0x00000004L 1584*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__JACK_DETECTION_CAPABILITY__SHIFT 0x00000002 1585*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE_MASK 0x00000010L 1586*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__OUTPUT_CAPABLE__SHIFT 0x00000004 1587*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED_MASK 0x00000002L 1588*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__TRIGGER_REQUIRED__SHIFT 0x00000001 1589*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL_MASK 0x0000ff00L 1590*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES__VREF_CONTROL__SHIFT 0x00000008 1591*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH_MASK 0xffffffffL 1592*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH__CONNECTION_LIST_LENGTH__SHIFT 0x00000000 1593*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID_MASK 0xffffffffL 1594*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID__AZALIA_CODEC_ROOT_PARAMETER_REVISION_ID__SHIFT 0x00000000 1595*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT_MASK 0xffffffffL 1596*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__AZALIA_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT__SHIFT 0x00000000 1597*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_MASK 0xffffffffL 1598*b843c749SSergey Zigachev #define AZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__AZALIA_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID__SHIFT 0x00000000 1599*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE_MASK 0x00000003L 1600*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_MODE__SHIFT 0x00000000 1601*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER_MASK 0x0000003cL 1602*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0__IEC_60958_CS_SOURCE_NUMBER__SHIFT 0x00000002 1603*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_MASK 0x00000003L 1604*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN_MASK 0x00000004L 1605*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY_OVRRD_EN__SHIFT 0x00000002 1606*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_CLOCK_ACCURACY__SHIFT 0x00000000 1607*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_MASK 0x00000078L 1608*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN_MASK 0x00000080L 1609*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH_OVRRD_EN__SHIFT 0x00000007 1610*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1__IEC_60958_CS_WORD_LENGTH__SHIFT 0x00000003 1611*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_MASK 0x0000003fL 1612*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000040L 1613*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000006 1614*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2__IEC_60958_CS_SAMPLING_FREQUENCY__SHIFT 0x00000000 1615*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_MASK 0x0000000fL 1616*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN_MASK 0x00000010L 1617*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY_OVRRD_EN__SHIFT 0x00000004 1618*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3__IEC_60958_CS_ORIGINAL_SAMPLING_FREQUENCY__SHIFT 0x00000000 1619*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_MASK 0x00000060L 1620*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A__SHIFT 0x00000005 1621*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID_MASK 0x00000080L 1622*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_CGMS_A_VALID__SHIFT 0x00000007 1623*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO_MASK 0x00000010L 1624*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_MPEG_SURROUND_INFO__SHIFT 0x00000004 1625*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF_MASK 0x0000000fL 1626*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4__IEC_60958_CS_SAMPLING_FREQUENCY_COEFF__SHIFT 0x00000000 1627*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L_MASK 0x0000000fL 1628*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_L__SHIFT 0x00000000 1629*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R_MASK 0x000000f0L 1630*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5__IEC_60958_CS_CHANNEL_NUMBER_R__SHIFT 0x00000004 1631*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2_MASK 0x0000000fL 1632*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_2__SHIFT 0x00000000 1633*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3_MASK 0x000000f0L 1634*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6__IEC_60958_CS_CHANNEL_NUMBER_3__SHIFT 0x00000004 1635*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4_MASK 0x0000000fL 1636*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_4__SHIFT 0x00000000 1637*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5_MASK 0x000000f0L 1638*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7__IEC_60958_CS_CHANNEL_NUMBER_5__SHIFT 0x00000004 1639*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6_MASK 0x0000000fL 1640*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_6__SHIFT 0x00000000 1641*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7_MASK 0x000000f0L 1642*b843c749SSergey Zigachev #define AZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8__IEC_60958_CS_CHANNEL_NUMBER_7__SHIFT 0x00000004 1643*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE_MASK 0x00007f00L 1644*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MAX_FIFO_SIZE__SHIFT 0x00000008 1645*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT_MASK 0x00ff0000L 1646*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MAX_LATENCY_SUPPORT__SHIFT 0x00000010 1647*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE_MASK 0x0000007fL 1648*b843c749SSergey Zigachev #define AZALIA_FIFO_SIZE_CONTROL__MIN_FIFO_SIZE__SHIFT 0x00000000 1649*b843c749SSergey Zigachev #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x00000006L 1650*b843c749SSergey Zigachev #define AZALIA_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x00000001 1651*b843c749SSergey Zigachev #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET_MASK 0x00000001L 1652*b843c749SSergey Zigachev #define AZALIA_LATENCY_COUNTER_CONTROL__AZALIA_LATENCY_COUNTER_RESET__SHIFT 0x00000000 1653*b843c749SSergey Zigachev #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY_MASK 0x0000ffffL 1654*b843c749SSergey Zigachev #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTPUT_PAYLOAD_CAPABILITY__SHIFT 0x00000000 1655*b843c749SSergey Zigachev #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY_MASK 0xffff0000L 1656*b843c749SSergey Zigachev #define AZALIA_OUTPUT_PAYLOAD_CAPABILITY__OUTSTRMPAY__SHIFT 0x00000010 1657*b843c749SSergey Zigachev #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL_MASK 0x000000ffL 1658*b843c749SSergey Zigachev #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__LATENCY_HIDING_LEVEL__SHIFT 0x00000000 1659*b843c749SSergey Zigachev #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE_MASK 0x00000100L 1660*b843c749SSergey Zigachev #define AZALIA_OUTPUT_STREAM_ARBITER_CONTROL__SYS_MEM_ACTIVE_ENABLE__SHIFT 0x00000008 1661*b843c749SSergey Zigachev #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP_MASK 0x00000010L 1662*b843c749SSergey Zigachev #define AZALIA_RIRB_AND_DP_CONTROL__DP_DMA_NON_SNOOP__SHIFT 0x00000004 1663*b843c749SSergey Zigachev #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP_MASK 0x00000001L 1664*b843c749SSergey Zigachev #define AZALIA_RIRB_AND_DP_CONTROL__RIRB_NON_SNOOP__SHIFT 0x00000000 1665*b843c749SSergey Zigachev #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL_MASK 0x00000030L 1666*b843c749SSergey Zigachev #define AZALIA_SCLK_CONTROL__AUDIO_SCLK_CONTROL__SHIFT 0x00000004 1667*b843c749SSergey Zigachev #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA_MASK 0xffffffffL 1668*b843c749SSergey Zigachev #define AZALIA_STREAM_DATA__AZALIA_STREAM_REG_DATA__SHIFT 0x00000000 1669*b843c749SSergey Zigachev #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA_MASK 0xffffffffL 1670*b843c749SSergey Zigachev #define AZALIA_STREAM_DEBUG__STREAM_DEBUG_DATA__SHIFT 0x00000000 1671*b843c749SSergey Zigachev #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX_MASK 0x000000ffL 1672*b843c749SSergey Zigachev #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_INDEX__SHIFT 0x00000000 1673*b843c749SSergey Zigachev #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN_MASK 0x00000100L 1674*b843c749SSergey Zigachev #define AZALIA_STREAM_INDEX__AZALIA_STREAM_REG_WRITE_EN__SHIFT 0x00000008 1675*b843c749SSergey Zigachev #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE_MASK 0xffffffffL 1676*b843c749SSergey Zigachev #define AZALIA_UNDERFLOW_FILLER_SAMPLE__AZALIA_UNDERFLOW_FILLER_SAMPLE__SHIFT 0x00000000 1677*b843c749SSergey Zigachev #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT_MASK 0xffffffffL 1678*b843c749SSergey Zigachev #define AZALIA_WORSTCASE_LATENCY_COUNT__AZALIA_WORSTCASE_LATENCY_COUNT__SHIFT 0x00000000 1679*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA_MASK 0xffffffffL 1680*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_DATA__AZ_TEST_DEBUG_DATA__SHIFT 0x00000000 1681*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX_MASK 0x000000ffL 1682*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_INDEX__SHIFT 0x00000000 1683*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 1684*b843c749SSergey Zigachev #define AZ_TEST_DEBUG_INDEX__AZ_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 1685*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN_MASK 0x00000008L 1686*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_CALC_FINAL_DUTY_CYCLE_EN__SHIFT 0x00000003 1687*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN_MASK 0x00000004L 1688*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_LEVEL_EN__SHIFT 0x00000002 1689*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE_MASK 0xffff0000L 1690*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_AUTO_UPDATE_CURRENT_ABM_STEP_SIZE__SHIFT 0x00000010 1691*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN_MASK 0x00000001L 1692*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_ABM_EN__SHIFT 0x00000000 1693*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN_MASK 0x00000002L 1694*b843c749SSergey Zigachev #define BL1_PWM_ABM_CNTL__BL1_PWM_USE_AMBIENT_LEVEL_EN__SHIFT 0x00000001 1695*b843c749SSergey Zigachev #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL_MASK 0x0001ffffL 1696*b843c749SSergey Zigachev #define BL1_PWM_AMBIENT_LIGHT_LEVEL__BL1_PWM_AMBIENT_LIGHT_LEVEL__SHIFT 0x00000000 1697*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 1698*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 1699*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 1700*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 1701*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 1702*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 1703*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 1704*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 1705*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 1706*b843c749SSergey Zigachev #define BL1_PWM_BL_UPDATE_SAMPLE_RATE__BL1_PWM_BL_UPDATE_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 1707*b843c749SSergey Zigachev #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL_MASK 0x0001ffffL 1708*b843c749SSergey Zigachev #define BL1_PWM_CURRENT_ABM_LEVEL__BL1_PWM_CURRENT_ABM_LEVEL__SHIFT 0x00000000 1709*b843c749SSergey Zigachev #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE_MASK 0x0001ffffL 1710*b843c749SSergey Zigachev #define BL1_PWM_FINAL_DUTY_CYCLE__BL1_PWM_FINAL_DUTY_CYCLE__SHIFT 0x00000000 1711*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL_MASK 0x000e0000L 1712*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_FRAME_START_DISP_SEL__SHIFT 0x00000011 1713*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1714*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1715*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1716*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1717*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK_MASK 0x00000001L 1718*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_LOCK__SHIFT 0x00000000 1719*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING_MASK 0x00000100L 1720*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_REG_UPDATE_PENDING__SHIFT 0x00000008 1721*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START_MASK 0x00010000L 1722*b843c749SSergey Zigachev #define BL1_PWM_GRP2_REG_LOCK__BL1_PWM_GRP2_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1723*b843c749SSergey Zigachev #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE_MASK 0x0001ffffL 1724*b843c749SSergey Zigachev #define BL1_PWM_MINIMUM_DUTY_CYCLE__BL1_PWM_MINIMUM_DUTY_CYCLE__SHIFT 0x00000000 1725*b843c749SSergey Zigachev #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL_MASK 0x0001ffffL 1726*b843c749SSergey Zigachev #define BL1_PWM_TARGET_ABM_LEVEL__BL1_PWM_TARGET_ABM_LEVEL__SHIFT 0x00000000 1727*b843c749SSergey Zigachev #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL_MASK 0x0001ffffL 1728*b843c749SSergey Zigachev #define BL1_PWM_USER_LEVEL__BL1_PWM_USER_LEVEL__SHIFT 0x00000000 1729*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE_MASK 0x40000000L 1730*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_BL_OUT_ENABLE__SHIFT 0x0000001e 1731*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_MASK 0x80000000L 1732*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN__SHIFT 0x0000001f 1733*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE_MASK 0x0000ffffL 1734*b843c749SSergey Zigachev #define BL_PWM_CNTL2__BL_PWM_POST_FRAME_START_DELAY_BEFORE_UPDATE__SHIFT 0x00000000 1735*b843c749SSergey Zigachev #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT_MASK 0x30000000L 1736*b843c749SSergey Zigachev #define BL_PWM_CNTL2__DBG_BL_PWM_INPUT_REFCLK_SELECT__SHIFT 0x0000001c 1737*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT_MASK 0x0000ffffL 1738*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_ACTIVE_INT_FRAC_CNT__SHIFT 0x00000000 1739*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_PWM_EN_MASK 0x80000000L 1740*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_PWM_EN__SHIFT 0x0000001f 1741*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN_MASK 0x40000000L 1742*b843c749SSergey Zigachev #define BL_PWM_CNTL__BL_PWM_FRACTIONAL_EN__SHIFT 0x0000001e 1743*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL_MASK 0x000e0000L 1744*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_FRAME_START_DISP_SEL__SHIFT 0x00000011 1745*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN_MASK 0x80000000L 1746*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001f 1747*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_MASK 0x01000000L 1748*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000018 1749*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK_MASK 0x00000001L 1750*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_LOCK__SHIFT 0x00000000 1751*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING_MASK 0x00000100L 1752*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_REG_UPDATE_PENDING__SHIFT 0x00000008 1753*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START_MASK 0x00010000L 1754*b843c749SSergey Zigachev #define BL_PWM_GRP1_REG_LOCK__BL_PWM_GRP1_UPDATE_AT_FRAME_START__SHIFT 0x00000010 1755*b843c749SSergey Zigachev #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT_MASK 0x000f0000L 1756*b843c749SSergey Zigachev #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_BITCNT__SHIFT 0x00000010 1757*b843c749SSergey Zigachev #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD_MASK 0x0000ffffL 1758*b843c749SSergey Zigachev #define BL_PWM_PERIOD_CNTL__BL_PWM_PERIOD__SHIFT 0x00000000 1759*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE_MASK 0x10000000L 1760*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_COMPLETE__SHIFT 0x0000001c 1761*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN_MASK 0x00000004L 1762*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_DACADJ_EN__SHIFT 0x00000002 1763*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN_MASK 0x00000002L 1764*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_EN__SHIFT 0x00000001 1765*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB_MASK 0x00000001L 1766*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_INITB__SHIFT 0x00000000 1767*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK_MASK 0x00700000L 1768*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_MASK__SHIFT 0x00000014 1769*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST_MASK 0x00003ff0L 1770*b843c749SSergey Zigachev #define BPHYC_DAC_AUTO_CALIB_CONTROL__BPHYC_DAC_CAL_WAIT_ADJUST__SHIFT 0x00000004 1771*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR_MASK 0x0f000000L 1772*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_ANALOG_MONITOR__SHIFT 0x00000018 1773*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT_MASK 0x003f0000L 1774*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_BANDGAP_ADJUSTMENT__SHIFT 0x00000010 1775*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON_MASK 0x10000000L 1776*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_COREMON__SHIFT 0x0000001c 1777*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL_MASK 0x00003f00L 1778*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_FINE_CONTROL__SHIFT 0x00000008 1779*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL_MASK 0x00000003L 1780*b843c749SSergey Zigachev #define BPHYC_DAC_MACRO_CNTL__BPHYC_DAC_WHITE_LEVEL__SHIFT 0x00000000 1781*b843c749SSergey Zigachev #define CC_DC_PIPE_DIS__DC_PIPE_DIS_MASK 0x0000007eL 1782*b843c749SSergey Zigachev #define CC_DC_PIPE_DIS__DC_PIPE_DIS__SHIFT 0x00000001 1783*b843c749SSergey Zigachev #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_MASK 0x00000007L 1784*b843c749SSergey Zigachev #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE_MASK 0x00000010L 1785*b843c749SSergey Zigachev #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY_OVERRIDE_ENABLE__SHIFT 0x00000004 1786*b843c749SSergey Zigachev #define CC_RCU_DC_AUDIO_PORT_CONNECTIVITY__PORT_CONNECTIVITY__SHIFT 0x00000000 1787*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11_MASK 0x0000ffffL 1788*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C11__SHIFT 0x00000000 1789*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12_MASK 0xffff0000L 1790*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C11_C12__COMM_MATRIXA_TRANS_C12__SHIFT 0x00000010 1791*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13_MASK 0x0000ffffL 1792*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C13__SHIFT 0x00000000 1793*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14_MASK 0xffff0000L 1794*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C13_C14__COMM_MATRIXA_TRANS_C14__SHIFT 0x00000010 1795*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21_MASK 0x0000ffffL 1796*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C21__SHIFT 0x00000000 1797*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22_MASK 0xffff0000L 1798*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C21_C22__COMM_MATRIXA_TRANS_C22__SHIFT 0x00000010 1799*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23_MASK 0x0000ffffL 1800*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C23__SHIFT 0x00000000 1801*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24_MASK 0xffff0000L 1802*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C23_C24__COMM_MATRIXA_TRANS_C24__SHIFT 0x00000010 1803*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31_MASK 0x0000ffffL 1804*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C31__SHIFT 0x00000000 1805*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32_MASK 0xffff0000L 1806*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C31_C32__COMM_MATRIXA_TRANS_C32__SHIFT 0x00000010 1807*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33_MASK 0x0000ffffL 1808*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C33__SHIFT 0x00000000 1809*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34_MASK 0xffff0000L 1810*b843c749SSergey Zigachev #define COMM_MATRIXA_TRANS_C33_C34__COMM_MATRIXA_TRANS_C34__SHIFT 0x00000010 1811*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11_MASK 0x0000ffffL 1812*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C11__SHIFT 0x00000000 1813*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12_MASK 0xffff0000L 1814*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C11_C12__COMM_MATRIXB_TRANS_C12__SHIFT 0x00000010 1815*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13_MASK 0x0000ffffL 1816*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C13__SHIFT 0x00000000 1817*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14_MASK 0xffff0000L 1818*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C13_C14__COMM_MATRIXB_TRANS_C14__SHIFT 0x00000010 1819*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21_MASK 0x0000ffffL 1820*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C21__SHIFT 0x00000000 1821*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22_MASK 0xffff0000L 1822*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C21_C22__COMM_MATRIXB_TRANS_C22__SHIFT 0x00000010 1823*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23_MASK 0x0000ffffL 1824*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C23__SHIFT 0x00000000 1825*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24_MASK 0xffff0000L 1826*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C23_C24__COMM_MATRIXB_TRANS_C24__SHIFT 0x00000010 1827*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31_MASK 0x0000ffffL 1828*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C31__SHIFT 0x00000000 1829*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32_MASK 0xffff0000L 1830*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C31_C32__COMM_MATRIXB_TRANS_C32__SHIFT 0x00000010 1831*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33_MASK 0x0000ffffL 1832*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C33__SHIFT 0x00000000 1833*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34_MASK 0xffff0000L 1834*b843c749SSergey Zigachev #define COMM_MATRIXB_TRANS_C33_C34__COMM_MATRIXB_TRANS_C34__SHIFT 0x00000010 1835*b843c749SSergey Zigachev #define CRT00__H_TOTAL_MASK 0x000000ffL 1836*b843c749SSergey Zigachev #define CRT00__H_TOTAL__SHIFT 0x00000000 1837*b843c749SSergey Zigachev #define CRT01__H_DISP_END_MASK 0x000000ffL 1838*b843c749SSergey Zigachev #define CRT01__H_DISP_END__SHIFT 0x00000000 1839*b843c749SSergey Zigachev #define CRT02__H_BLANK_START_MASK 0x000000ffL 1840*b843c749SSergey Zigachev #define CRT02__H_BLANK_START__SHIFT 0x00000000 1841*b843c749SSergey Zigachev #define CRT03__CR10CR11_R_DIS_B_MASK 0x00000080L 1842*b843c749SSergey Zigachev #define CRT03__CR10CR11_R_DIS_B__SHIFT 0x00000007 1843*b843c749SSergey Zigachev #define CRT03__H_BLANK_END_MASK 0x0000001fL 1844*b843c749SSergey Zigachev #define CRT03__H_BLANK_END__SHIFT 0x00000000 1845*b843c749SSergey Zigachev #define CRT03__H_DE_SKEW_MASK 0x00000060L 1846*b843c749SSergey Zigachev #define CRT03__H_DE_SKEW__SHIFT 0x00000005 1847*b843c749SSergey Zigachev #define CRT04__H_SYNC_START_MASK 0x000000ffL 1848*b843c749SSergey Zigachev #define CRT04__H_SYNC_START__SHIFT 0x00000000 1849*b843c749SSergey Zigachev #define CRT05__H_BLANK_END_B5_MASK 0x00000080L 1850*b843c749SSergey Zigachev #define CRT05__H_BLANK_END_B5__SHIFT 0x00000007 1851*b843c749SSergey Zigachev #define CRT05__H_SYNC_END_MASK 0x0000001fL 1852*b843c749SSergey Zigachev #define CRT05__H_SYNC_END__SHIFT 0x00000000 1853*b843c749SSergey Zigachev #define CRT05__H_SYNC_SKEW_MASK 0x00000060L 1854*b843c749SSergey Zigachev #define CRT05__H_SYNC_SKEW__SHIFT 0x00000005 1855*b843c749SSergey Zigachev #define CRT06__V_TOTAL_MASK 0x000000ffL 1856*b843c749SSergey Zigachev #define CRT06__V_TOTAL__SHIFT 0x00000000 1857*b843c749SSergey Zigachev #define CRT07__LINE_CMP_B8_MASK 0x00000010L 1858*b843c749SSergey Zigachev #define CRT07__LINE_CMP_B8__SHIFT 0x00000004 1859*b843c749SSergey Zigachev #define CRT07__V_BLANK_START_B8_MASK 0x00000008L 1860*b843c749SSergey Zigachev #define CRT07__V_BLANK_START_B8__SHIFT 0x00000003 1861*b843c749SSergey Zigachev #define CRT07__V_DISP_END_B8_MASK 0x00000002L 1862*b843c749SSergey Zigachev #define CRT07__V_DISP_END_B8__SHIFT 0x00000001 1863*b843c749SSergey Zigachev #define CRT07__V_DISP_END_B9_MASK 0x00000040L 1864*b843c749SSergey Zigachev #define CRT07__V_DISP_END_B9__SHIFT 0x00000006 1865*b843c749SSergey Zigachev #define CRT07__V_SYNC_START_B8_MASK 0x00000004L 1866*b843c749SSergey Zigachev #define CRT07__V_SYNC_START_B8__SHIFT 0x00000002 1867*b843c749SSergey Zigachev #define CRT07__V_SYNC_START_B9_MASK 0x00000080L 1868*b843c749SSergey Zigachev #define CRT07__V_SYNC_START_B9__SHIFT 0x00000007 1869*b843c749SSergey Zigachev #define CRT07__V_TOTAL_B8_MASK 0x00000001L 1870*b843c749SSergey Zigachev #define CRT07__V_TOTAL_B8__SHIFT 0x00000000 1871*b843c749SSergey Zigachev #define CRT07__V_TOTAL_B9_MASK 0x00000020L 1872*b843c749SSergey Zigachev #define CRT07__V_TOTAL_B9__SHIFT 0x00000005 1873*b843c749SSergey Zigachev #define CRT08__BYTE_PAN_MASK 0x00000060L 1874*b843c749SSergey Zigachev #define CRT08__BYTE_PAN__SHIFT 0x00000005 1875*b843c749SSergey Zigachev #define CRT08__ROW_SCAN_START_MASK 0x0000001fL 1876*b843c749SSergey Zigachev #define CRT08__ROW_SCAN_START__SHIFT 0x00000000 1877*b843c749SSergey Zigachev #define CRT09__DOUBLE_CHAR_HEIGHT_MASK 0x00000080L 1878*b843c749SSergey Zigachev #define CRT09__DOUBLE_CHAR_HEIGHT__SHIFT 0x00000007 1879*b843c749SSergey Zigachev #define CRT09__LINE_CMP_B9_MASK 0x00000040L 1880*b843c749SSergey Zigachev #define CRT09__LINE_CMP_B9__SHIFT 0x00000006 1881*b843c749SSergey Zigachev #define CRT09__MAX_ROW_SCAN_MASK 0x0000001fL 1882*b843c749SSergey Zigachev #define CRT09__MAX_ROW_SCAN__SHIFT 0x00000000 1883*b843c749SSergey Zigachev #define CRT09__V_BLANK_START_B9_MASK 0x00000020L 1884*b843c749SSergey Zigachev #define CRT09__V_BLANK_START_B9__SHIFT 0x00000005 1885*b843c749SSergey Zigachev #define CRT0A__CURSOR_DISABLE_MASK 0x00000020L 1886*b843c749SSergey Zigachev #define CRT0A__CURSOR_DISABLE__SHIFT 0x00000005 1887*b843c749SSergey Zigachev #define CRT0A__CURSOR_START_MASK 0x0000001fL 1888*b843c749SSergey Zigachev #define CRT0A__CURSOR_START__SHIFT 0x00000000 1889*b843c749SSergey Zigachev #define CRT0B__CURSOR_END_MASK 0x0000001fL 1890*b843c749SSergey Zigachev #define CRT0B__CURSOR_END__SHIFT 0x00000000 1891*b843c749SSergey Zigachev #define CRT0B__CURSOR_SKEW_MASK 0x00000060L 1892*b843c749SSergey Zigachev #define CRT0B__CURSOR_SKEW__SHIFT 0x00000005 1893*b843c749SSergey Zigachev #define CRT0C__DISP_START_MASK 0x000000ffL 1894*b843c749SSergey Zigachev #define CRT0C__DISP_START__SHIFT 0x00000000 1895*b843c749SSergey Zigachev #define CRT0D__DISP_START_MASK 0x000000ffL 1896*b843c749SSergey Zigachev #define CRT0D__DISP_START__SHIFT 0x00000000 1897*b843c749SSergey Zigachev #define CRT0E__CURSOR_LOC_HI_MASK 0x000000ffL 1898*b843c749SSergey Zigachev #define CRT0E__CURSOR_LOC_HI__SHIFT 0x00000000 1899*b843c749SSergey Zigachev #define CRT0F__CURSOR_LOC_LO_MASK 0x000000ffL 1900*b843c749SSergey Zigachev #define CRT0F__CURSOR_LOC_LO__SHIFT 0x00000000 1901*b843c749SSergey Zigachev #define CRT10__V_SYNC_START_MASK 0x000000ffL 1902*b843c749SSergey Zigachev #define CRT10__V_SYNC_START__SHIFT 0x00000000 1903*b843c749SSergey Zigachev #define CRT11__C0T7_WR_ONLY_MASK 0x00000080L 1904*b843c749SSergey Zigachev #define CRT11__C0T7_WR_ONLY__SHIFT 0x00000007 1905*b843c749SSergey Zigachev #define CRT11__SEL5_REFRESH_CYC_MASK 0x00000040L 1906*b843c749SSergey Zigachev #define CRT11__SEL5_REFRESH_CYC__SHIFT 0x00000006 1907*b843c749SSergey Zigachev #define CRT11__V_INTR_CLR_MASK 0x00000010L 1908*b843c749SSergey Zigachev #define CRT11__V_INTR_CLR__SHIFT 0x00000004 1909*b843c749SSergey Zigachev #define CRT11__V_INTR_EN_MASK 0x00000020L 1910*b843c749SSergey Zigachev #define CRT11__V_INTR_EN__SHIFT 0x00000005 1911*b843c749SSergey Zigachev #define CRT11__V_SYNC_END_MASK 0x0000000fL 1912*b843c749SSergey Zigachev #define CRT11__V_SYNC_END__SHIFT 0x00000000 1913*b843c749SSergey Zigachev #define CRT12__V_DISP_END_MASK 0x000000ffL 1914*b843c749SSergey Zigachev #define CRT12__V_DISP_END__SHIFT 0x00000000 1915*b843c749SSergey Zigachev #define CRT13__DISP_PITCH_MASK 0x000000ffL 1916*b843c749SSergey Zigachev #define CRT13__DISP_PITCH__SHIFT 0x00000000 1917*b843c749SSergey Zigachev #define CRT14__ADDR_CNT_BY4_MASK 0x00000020L 1918*b843c749SSergey Zigachev #define CRT14__ADDR_CNT_BY4__SHIFT 0x00000005 1919*b843c749SSergey Zigachev #define CRT14__DOUBLE_WORD_MASK 0x00000040L 1920*b843c749SSergey Zigachev #define CRT14__DOUBLE_WORD__SHIFT 0x00000006 1921*b843c749SSergey Zigachev #define CRT14__UNDRLN_LOC_MASK 0x0000001fL 1922*b843c749SSergey Zigachev #define CRT14__UNDRLN_LOC__SHIFT 0x00000000 1923*b843c749SSergey Zigachev #define CRT15__V_BLANK_START_MASK 0x000000ffL 1924*b843c749SSergey Zigachev #define CRT15__V_BLANK_START__SHIFT 0x00000000 1925*b843c749SSergey Zigachev #define CRT16__V_BLANK_END_MASK 0x000000ffL 1926*b843c749SSergey Zigachev #define CRT16__V_BLANK_END__SHIFT 0x00000000 1927*b843c749SSergey Zigachev #define CRT17__ADDR_CNT_BY2_MASK 0x00000008L 1928*b843c749SSergey Zigachev #define CRT17__ADDR_CNT_BY2__SHIFT 0x00000003 1929*b843c749SSergey Zigachev #define CRT17__BYTE_MODE_MASK 0x00000040L 1930*b843c749SSergey Zigachev #define CRT17__BYTE_MODE__SHIFT 0x00000006 1931*b843c749SSergey Zigachev #define CRT17__CRTC_SYNC_EN_MASK 0x00000080L 1932*b843c749SSergey Zigachev #define CRT17__CRTC_SYNC_EN__SHIFT 0x00000007 1933*b843c749SSergey Zigachev #define CRT17__RA0_AS_A13B_MASK 0x00000001L 1934*b843c749SSergey Zigachev #define CRT17__RA0_AS_A13B__SHIFT 0x00000000 1935*b843c749SSergey Zigachev #define CRT17__RA1_AS_A14B_MASK 0x00000002L 1936*b843c749SSergey Zigachev #define CRT17__RA1_AS_A14B__SHIFT 0x00000001 1937*b843c749SSergey Zigachev #define CRT17__VCOUNT_BY2_MASK 0x00000004L 1938*b843c749SSergey Zigachev #define CRT17__VCOUNT_BY2__SHIFT 0x00000002 1939*b843c749SSergey Zigachev #define CRT17__WRAP_A15TOA0_MASK 0x00000020L 1940*b843c749SSergey Zigachev #define CRT17__WRAP_A15TOA0__SHIFT 0x00000005 1941*b843c749SSergey Zigachev #define CRT18__LINE_CMP_MASK 0x000000ffL 1942*b843c749SSergey Zigachev #define CRT18__LINE_CMP__SHIFT 0x00000000 1943*b843c749SSergey Zigachev #define CRT1E__GRPH_DEC_RD1_MASK 0x00000002L 1944*b843c749SSergey Zigachev #define CRT1E__GRPH_DEC_RD1__SHIFT 0x00000001 1945*b843c749SSergey Zigachev #define CRT1F__GRPH_DEC_RD0_MASK 0x000000ffL 1946*b843c749SSergey Zigachev #define CRT1F__GRPH_DEC_RD0__SHIFT 0x00000000 1947*b843c749SSergey Zigachev #define CRT22__GRPH_LATCH_DATA_MASK 0x000000ffL 1948*b843c749SSergey Zigachev #define CRT22__GRPH_LATCH_DATA__SHIFT 0x00000000 1949*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL_MASK 0x00000100L 1950*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_ADD_PIXEL__SHIFT 0x00000008 1951*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1952*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1953*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1954*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1955*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL_MASK 0x00000200L 1956*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_DROP_PIXEL__SHIFT 0x00000009 1957*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE_MASK 0x00000003L 1958*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__CRTC0_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1959*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE_MASK 0x00000010L 1960*b843c749SSergey Zigachev #define CRTC0_PIXEL_RATE_CNTL__DP_DTO0_ENABLE__SHIFT 0x00000004 1961*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL_MASK 0x00000100L 1962*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_ADD_PIXEL__SHIFT 0x00000008 1963*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1964*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1965*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1966*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1967*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL_MASK 0x00000200L 1968*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_DROP_PIXEL__SHIFT 0x00000009 1969*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE_MASK 0x00000003L 1970*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__CRTC1_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1971*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE_MASK 0x00000010L 1972*b843c749SSergey Zigachev #define CRTC1_PIXEL_RATE_CNTL__DP_DTO1_ENABLE__SHIFT 0x00000004 1973*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL_MASK 0x00000100L 1974*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_ADD_PIXEL__SHIFT 0x00000008 1975*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 1976*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 1977*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 1978*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 1979*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL_MASK 0x00000200L 1980*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_DROP_PIXEL__SHIFT 0x00000009 1981*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE_MASK 0x00000003L 1982*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__CRTC2_PIXEL_RATE_SOURCE__SHIFT 0x00000000 1983*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE_MASK 0x00000010L 1984*b843c749SSergey Zigachev #define CRTC2_PIXEL_RATE_CNTL__DP_DTO2_ENABLE__SHIFT 0x00000004 1985*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB_MASK 0x00000010L 1986*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_DB__SHIFT 0x00000004 1987*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN_MASK 0x00000001L 1988*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_EN__SHIFT 0x00000000 1989*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_MASK 0x000c0000L 1990*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_MASK 0x00010000L 1991*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING_MASK 0x00020000L 1992*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET_PENDING__SHIFT 0x00000011 1993*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT_RESET__SHIFT 0x00000010 1994*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_F_COUNT__SHIFT 0x00000012 1995*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR_MASK 0x00001000L 1996*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_STEREO_SEL_OVR__SHIFT 0x0000000c 1997*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE_MASK 0x00000300L 1998*b843c749SSergey Zigachev #define CRTC_3D_STRUCTURE_CONTROL__CRTC_3D_STRUCTURE_V_UPDATE_MODE__SHIFT 0x00000008 1999*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL_MASK 0x00000100L 2000*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_ADD_PIXEL__SHIFT 0x00000008 2001*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2002*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2003*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2004*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2005*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL_MASK 0x00000200L 2006*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_DROP_PIXEL__SHIFT 0x00000009 2007*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE_MASK 0x00000003L 2008*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__CRTC3_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2009*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE_MASK 0x00000010L 2010*b843c749SSergey Zigachev #define CRTC3_PIXEL_RATE_CNTL__DP_DTO3_ENABLE__SHIFT 0x00000004 2011*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL_MASK 0x00000100L 2012*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_ADD_PIXEL__SHIFT 0x00000008 2013*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2014*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2015*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2016*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2017*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL_MASK 0x00000200L 2018*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_DROP_PIXEL__SHIFT 0x00000009 2019*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE_MASK 0x00000003L 2020*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__CRTC4_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2021*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE_MASK 0x00000010L 2022*b843c749SSergey Zigachev #define CRTC4_PIXEL_RATE_CNTL__DP_DTO4_ENABLE__SHIFT 0x00000004 2023*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL_MASK 0x00000100L 2024*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_ADD_PIXEL__SHIFT 0x00000008 2025*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT_MASK 0x0fff0000L 2026*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_ERROR_COUNT__SHIFT 0x00000010 2027*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR_MASK 0x0000c000L 2028*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DISPOUT_FIFO_ERROR__SHIFT 0x0000000e 2029*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL_MASK 0x00000200L 2030*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_DROP_PIXEL__SHIFT 0x00000009 2031*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE_MASK 0x00000003L 2032*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__CRTC5_PIXEL_RATE_SOURCE__SHIFT 0x00000000 2033*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE_MASK 0x00000010L 2034*b843c749SSergey Zigachev #define CRTC5_PIXEL_RATE_CNTL__DP_DTO5_ENABLE__SHIFT 0x00000004 2035*b843c749SSergey Zigachev #define CRTC8_DATA__VCRTC_DATA_MASK 0x000000ffL 2036*b843c749SSergey Zigachev #define CRTC8_DATA__VCRTC_DATA__SHIFT 0x00000000 2037*b843c749SSergey Zigachev #define CRTC8_IDX__VCRTC_IDX_MASK 0x0000003fL 2038*b843c749SSergey Zigachev #define CRTC8_IDX__VCRTC_IDX__SHIFT 0x00000000 2039*b843c749SSergey Zigachev #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT_MASK 0x000000ffL 2040*b843c749SSergey Zigachev #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000000 2041*b843c749SSergey Zigachev #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT_MASK 0x00010000L 2042*b843c749SSergey Zigachev #define CRTC_ALLOW_STOP_OFF_V_CNT__CRTC_DISABLE_ALLOW_STOP_OFF_V_CNT__SHIFT 0x00000010 2043*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB_MASK 0x000003ffL 2044*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_B_CB__SHIFT 0x00000000 2045*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y_MASK 0x000ffc00L 2046*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_G_Y__SHIFT 0x0000000a 2047*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR_MASK 0x3ff00000L 2048*b843c749SSergey Zigachev #define CRTC_BLACK_COLOR__CRTC_BLACK_COLOR_R_CR__SHIFT 0x00000014 2049*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK 0x00000100L 2050*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN__SHIFT 0x00000008 2051*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE_MASK 0x00010000L 2052*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_BLANK_DE_MODE__SHIFT 0x00000010 2053*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE_MASK 0x00000001L 2054*b843c749SSergey Zigachev #define CRTC_BLANK_CONTROL__CRTC_CURRENT_BLANK_STATE__SHIFT 0x00000000 2055*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB_MASK 0x000003ffL 2056*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_BLUE_CB__SHIFT 0x00000000 2057*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y_MASK 0x000ffc00L 2058*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_GREEN_Y__SHIFT 0x0000000a 2059*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR_MASK 0x3ff00000L 2060*b843c749SSergey Zigachev #define CRTC_BLANK_DATA_COLOR__CRTC_BLANK_DATA_COLOR_RED_CR__SHIFT 0x00000014 2061*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE_MASK 0x00010000L 2062*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_CURRENT_MASTER_EN_STATE__SHIFT 0x00000010 2063*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL_MASK 0x00000300L 2064*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_DISABLE_POINT_CNTL__SHIFT 0x00000008 2065*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE_MASK 0x01000000L 2066*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_DISP_READ_REQUEST_DISABLE__SHIFT 0x00000018 2067*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL_MASK 0x00002000L 2068*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_FIELD_NUMBER_CNTL__SHIFT 0x0000000d 2069*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL_MASK 0x00700000L 2070*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_HBLANK_EARLY_CONTROL__SHIFT 0x00000014 2071*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_MASTER_EN_MASK 0x00000001L 2072*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_MASTER_EN__SHIFT 0x00000000 2073*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_SOF_PULL_EN_MASK 0x20000000L 2074*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_SOF_PULL_EN__SHIFT 0x0000001d 2075*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_START_POINT_CNTL_MASK 0x00001000L 2076*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_START_POINT_CNTL__SHIFT 0x0000000c 2077*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL_MASK 0x00000010L 2078*b843c749SSergey Zigachev #define CRTC_CONTROL__CRTC_SYNC_RESET_SEL__SHIFT 0x00000004 2079*b843c749SSergey Zigachev #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN_MASK 0x00000001L 2080*b843c749SSergey Zigachev #define CRTC_COUNT_CONTROL__CRTC_HORZ_COUNT_BY2_EN__SHIFT 0x00000000 2081*b843c749SSergey Zigachev #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT_MASK 0x0000001eL 2082*b843c749SSergey Zigachev #define CRTC_COUNT_CONTROL__CRTC_HORZ_REPETITION_COUNT__SHIFT 0x00000001 2083*b843c749SSergey Zigachev #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT_MASK 0x00000001L 2084*b843c749SSergey Zigachev #define CRTC_COUNT_RESET__CRTC_RESET_FRAME_COUNT__SHIFT 0x00000000 2085*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE_MASK 0x80000000L 2086*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE__SHIFT 0x0000001f 2087*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL_MASK 0x1f000000L 2088*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_TEST_CLK_SEL__SHIFT 0x00000018 2089*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE_MASK 0x00000100L 2090*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_DCP_GATE_DISABLE__SHIFT 0x00000008 2091*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE_MASK 0x00001000L 2092*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_G_SCL_GATE_DISABLE__SHIFT 0x0000000c 2093*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE_MASK 0x00000010L 2094*b843c749SSergey Zigachev #define CRTC_DCFE_CLOCK_CONTROL__CRTC_DISPCLK_R_DCFE_GATE_DISABLE__SHIFT 0x00000004 2095*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_MASK 0x00010000L 2096*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_BLANK_DATA_DOUBLE_BUFFER_EN__SHIFT 0x00000010 2097*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY_MASK 0x00000100L 2098*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_INSTANTLY__SHIFT 0x00000008 2099*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING_MASK 0x00000001L 2100*b843c749SSergey Zigachev #define CRTC_DOUBLE_BUFFER_CONTROL__CRTC_UPDATE_PENDING__SHIFT 0x00000000 2101*b843c749SSergey Zigachev #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV_MASK 0x0000001eL 2102*b843c749SSergey Zigachev #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CLK_DIV__SHIFT 0x00000001 2103*b843c749SSergey Zigachev #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN_MASK 0x00000001L 2104*b843c749SSergey Zigachev #define CRTC_DTMTEST_CNTL__CRTC_DTMTEST_CRTC_EN__SHIFT 0x00000000 2105*b843c749SSergey Zigachev #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT_MASK 0x1fff0000L 2106*b843c749SSergey Zigachev #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_HORZ_COUNT__SHIFT 0x00000010 2107*b843c749SSergey Zigachev #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT_MASK 0x00001fffL 2108*b843c749SSergey Zigachev #define CRTC_DTMTEST_STATUS_POSITION__CRTC_DTMTEST_VERT_COUNT__SHIFT 0x00000000 2109*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY_MASK 0x00010000L 2110*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_GRANULARITY__SHIFT 0x00000010 2111*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS_MASK 0x01000000L 2112*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_INPUT_STATUS__SHIFT 0x00000018 2113*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY_MASK 0x00000100L 2114*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_POLARITY__SHIFT 0x00000008 2115*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT_MASK 0x0000001fL 2116*b843c749SSergey Zigachev #define CRTC_FLOW_CONTROL__CRTC_FLOW_CONTROL_SOURCE_SELECT__SHIFT 0x00000000 2117*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK_MASK 0x00000010L 2118*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CHECK__SHIFT 0x00000004 2119*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR_MASK 0x01000000L 2120*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_CLEAR__SHIFT 0x00000018 2121*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE_MASK 0x00000003L 2122*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_MODE__SHIFT 0x00000000 2123*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED_MASK 0x00010000L 2124*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_OCCURRED__SHIFT 0x00000010 2125*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL_MASK 0x00000100L 2126*b843c749SSergey Zigachev #define CRTC_FORCE_COUNT_NOW_CNTL__CRTC_FORCE_COUNT_NOW_TRIG_SEL__SHIFT 0x00000008 2127*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS_MASK 0x10000000L 2128*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_ALL_FIELDS__SHIFT 0x0000001c 2129*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM_MASK 0x00001fffL 2130*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_CHECK_LINE_NUM__SHIFT 0x00000000 2131*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY_MASK 0x001f0000L 2132*b843c749SSergey Zigachev #define CRTC_GSL_CONTROL__CRTC_GSL_FORCE_DELAY__SHIFT 0x00000010 2133*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR_MASK 0x00080000L 2134*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_CLEAR__SHIFT 0x00000013 2135*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY_MASK 0x0000ff00L 2136*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_DELAY__SHIFT 0x00000008 2137*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT_MASK 0x000000ffL 2138*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_LIMIT__SHIFT 0x00000000 2139*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASK 0xff000000L 2140*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER_MASK 0x00800000L 2141*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MASTER_FASTER__SHIFT 0x00000017 2142*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE_MASK 0x00060000L 2143*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_MODE__SHIFT 0x00000011 2144*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED_MASK 0x00100000L 2145*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_OCCURRED__SHIFT 0x00000014 2146*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP__SHIFT 0x00000018 2147*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL_MASK 0x00010000L 2148*b843c749SSergey Zigachev #define CRTC_GSL_VSYNC_GAP__CRTC_GSL_VSYNC_GAP_SOURCE_SEL__SHIFT 0x00000010 2149*b843c749SSergey Zigachev #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END_MASK 0x1fff0000L 2150*b843c749SSergey Zigachev #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_END__SHIFT 0x00000010 2151*b843c749SSergey Zigachev #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START_MASK 0x00001fffL 2152*b843c749SSergey Zigachev #define CRTC_GSL_WINDOW__CRTC_GSL_WINDOW_START__SHIFT 0x00000000 2153*b843c749SSergey Zigachev #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS_MASK 0x00010000L 2154*b843c749SSergey Zigachev #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_DIS__SHIFT 0x00000010 2155*b843c749SSergey Zigachev #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM_MASK 0x000003ffL 2156*b843c749SSergey Zigachev #define CRTC_H_BLANK_EARLY_NUM__CRTC_H_BLANK_EARLY_NUM__SHIFT 0x00000000 2157*b843c749SSergey Zigachev #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END_MASK 0x1fff0000L 2158*b843c749SSergey Zigachev #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_END__SHIFT 0x00000010 2159*b843c749SSergey Zigachev #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START_MASK 0x00001fffL 2160*b843c749SSergey Zigachev #define CRTC_H_BLANK_START_END__CRTC_H_BLANK_START__SHIFT 0x00000000 2161*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN_MASK 0x00010000L 2162*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_COMP_SYNC_A_EN__SHIFT 0x00000010 2163*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF_MASK 0x00020000L 2164*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_CUTOFF__SHIFT 0x00000011 2165*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL_MASK 0x00000001L 2166*b843c749SSergey Zigachev #define CRTC_H_SYNC_A_CNTL__CRTC_H_SYNC_A_POL__SHIFT 0x00000000 2167*b843c749SSergey Zigachev #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END_MASK 0x1fff0000L 2168*b843c749SSergey Zigachev #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_END__SHIFT 0x00000010 2169*b843c749SSergey Zigachev #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START_MASK 0x00001fffL 2170*b843c749SSergey Zigachev #define CRTC_H_SYNC_A__CRTC_H_SYNC_A_START__SHIFT 0x00000000 2171*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN_MASK 0x00010000L 2172*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_COMP_SYNC_B_EN__SHIFT 0x00000010 2173*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF_MASK 0x00020000L 2174*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_CUTOFF__SHIFT 0x00000011 2175*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL_MASK 0x00000001L 2176*b843c749SSergey Zigachev #define CRTC_H_SYNC_B_CNTL__CRTC_H_SYNC_B_POL__SHIFT 0x00000000 2177*b843c749SSergey Zigachev #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END_MASK 0x1fff0000L 2178*b843c749SSergey Zigachev #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_END__SHIFT 0x00000010 2179*b843c749SSergey Zigachev #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START_MASK 0x00001fffL 2180*b843c749SSergey Zigachev #define CRTC_H_SYNC_B__CRTC_H_SYNC_B_START__SHIFT 0x00000000 2181*b843c749SSergey Zigachev #define CRTC_H_TOTAL__CRTC_H_TOTAL_MASK 0x00001fffL 2182*b843c749SSergey Zigachev #define CRTC_H_TOTAL__CRTC_H_TOTAL__SHIFT 0x00000000 2183*b843c749SSergey Zigachev #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE_MASK 0x00000001L 2184*b843c749SSergey Zigachev #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_ENABLE__SHIFT 0x00000000 2185*b843c749SSergey Zigachev #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD_MASK 0x00030000L 2186*b843c749SSergey Zigachev #define CRTC_INTERLACE_CONTROL__CRTC_INTERLACE_FORCE_NEXT_FIELD__SHIFT 0x00000010 2187*b843c749SSergey Zigachev #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD_MASK 0x00000001L 2188*b843c749SSergey Zigachev #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_CURRENT_FIELD__SHIFT 0x00000000 2189*b843c749SSergey Zigachev #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD_MASK 0x00000002L 2190*b843c749SSergey Zigachev #define CRTC_INTERLACE_STATUS__CRTC_INTERLACE_NEXT_FIELD__SHIFT 0x00000001 2191*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK_MASK 0x00000100L 2192*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_MSK__SHIFT 0x00000008 2193*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE_MASK 0x00000200L 2194*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_COUNT_NOW_INT_TYPE__SHIFT 0x00000009 2195*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_MASK 0x00010000L 2196*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK__SHIFT 0x00000010 2197*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_MASK 0x00020000L 2198*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE__SHIFT 0x00000011 2199*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK_MASK 0x40000000L 2200*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_MSK__SHIFT 0x0000001e 2201*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE_MASK 0x80000000L 2202*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_GSL_VSYNC_GAP_INT_TYPE__SHIFT 0x0000001f 2203*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK_MASK 0x00000001L 2204*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_MSK__SHIFT 0x00000000 2205*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE_MASK 0x00000002L 2206*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_SNAPSHOT_INT_TYPE__SHIFT 0x00000001 2207*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK_MASK 0x01000000L 2208*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_MSK__SHIFT 0x00000018 2209*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE_MASK 0x04000000L 2210*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGA_INT_TYPE__SHIFT 0x0000001a 2211*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK_MASK 0x02000000L 2212*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_MSK__SHIFT 0x00000019 2213*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE_MASK 0x08000000L 2214*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_TRIGB_INT_TYPE__SHIFT 0x0000001b 2215*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK_MASK 0x10000000L 2216*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_MSK__SHIFT 0x0000001c 2217*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE_MASK 0x20000000L 2218*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_VSYNC_NOM_INT_TYPE__SHIFT 0x0000001d 2219*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK 0x00000010L 2220*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK__SHIFT 0x00000004 2221*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE_MASK 0x00000020L 2222*b843c749SSergey Zigachev #define CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_TYPE__SHIFT 0x00000005 2223*b843c749SSergey Zigachev #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_MASK 0x00000001L 2224*b843c749SSergey Zigachev #define CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE__SHIFT 0x00000000 2225*b843c749SSergey Zigachev #define CRTC_MASTER_EN__CRTC_MASTER_EN_MASK 0x00000001L 2226*b843c749SSergey Zigachev #define CRTC_MASTER_EN__CRTC_MASTER_EN__SHIFT 0x00000000 2227*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_MASK 0xffffff00L 2228*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_CNTL_CHAR_INSERT__SHIFT 0x00000008 2229*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE_MASK 0x00000003L 2230*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT__CRTC_MVP_INBAND_OUT_MODE__SHIFT 0x00000000 2231*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER_MASK 0x000000ffL 2232*b843c749SSergey Zigachev #define CRTC_MVP_INBAND_CNTL_INSERT_TIMER__CRTC_MVP_INBAND_CNTL_CHAR_INSERT_TIMER__SHIFT 0x00000000 2233*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_MASK 0x00100000L 2234*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR__SHIFT 0x00000014 2235*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED_MASK 0x00000010L 2236*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_AFR_HSYNC_SWITCH_DONE_OCCURRED__SHIFT 0x00000004 2237*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR_MASK 0x00010000L 2238*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_CLEAR__SHIFT 0x00000010 2239*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED_MASK 0x00000001L 2240*b843c749SSergey Zigachev #define CRTC_MVP_STATUS__CRTC_FLIP_NOW_OCCURRED__SHIFT 0x00000000 2241*b843c749SSergey Zigachev #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM_MASK 0x00001fffL 2242*b843c749SSergey Zigachev #define CRTC_NOM_VERT_POSITION__CRTC_VERT_COUNT_NOM__SHIFT 0x00000000 2243*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE_MASK 0x000003ffL 2244*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_BLUE__SHIFT 0x00000000 2245*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN_MASK 0x000ffc00L 2246*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_GREEN__SHIFT 0x0000000a 2247*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED_MASK 0x3ff00000L 2248*b843c749SSergey Zigachev #define CRTC_OVERSCAN_COLOR__CRTC_OVERSCAN_COLOR_RED__SHIFT 0x00000014 2249*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL_MASK 0x00000003L 2250*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_CONTROL__CRTC_AUTO_SNAPSHOT_TRIG_SEL__SHIFT 0x00000000 2251*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT_MASK 0x00ffffffL 2252*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_FRAME__CRTC_SNAPSHOT_FRAME_COUNT__SHIFT 0x00000000 2253*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT_MASK 0x1fff0000L 2254*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_HORZ_COUNT__SHIFT 0x00000010 2255*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT_MASK 0x00001fffL 2256*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_POSITION__CRTC_SNAPSHOT_VERT_COUNT__SHIFT 0x00000000 2257*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR_MASK 0x00000002L 2258*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_CLEAR__SHIFT 0x00000001 2259*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER_MASK 0x00000004L 2260*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_MANUAL_TRIGGER__SHIFT 0x00000002 2261*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED_MASK 0x00000001L 2262*b843c749SSergey Zigachev #define CRTC_SNAPSHOT_STATUS__CRTC_SNAPSHOT_OCCURRED__SHIFT 0x00000000 2263*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION_MASK 0x000f0000L 2264*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_ADVANCED_START_LINE_POSITION__SHIFT 0x00000010 2265*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY_MASK 0x00000100L 2266*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_INTERLACE_START_LINE_EARLY__SHIFT 0x00000008 2267*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY_MASK 0x00000001L 2268*b843c749SSergey Zigachev #define CRTC_START_LINE_CONTROL__CRTC_PROGRESSIVE_START_LINE_EARLY__SHIFT 0x00000000 2269*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_ACTIVE_DISP_MASK 0x00020000L 2270*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_ACTIVE_DISP__SHIFT 0x00000011 2271*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_BLANK_MASK 0x00010000L 2272*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_BLANK__SHIFT 0x00000010 2273*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_SYNC_A_MASK 0x00040000L 2274*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_H_SYNC_A__SHIFT 0x00000012 2275*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_ACTIVE_DISP_MASK 0x00000002L 2276*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_ACTIVE_DISP__SHIFT 0x00000001 2277*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE_MASK 0x00000020L 2278*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_BLANK_3D_STRUCTURE__SHIFT 0x00000005 2279*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_BLANK_MASK 0x00000001L 2280*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_BLANK__SHIFT 0x00000000 2281*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_START_LINE_MASK 0x00000010L 2282*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_START_LINE__SHIFT 0x00000004 2283*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_SYNC_A_MASK 0x00000004L 2284*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_SYNC_A__SHIFT 0x00000002 2285*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_UPDATE_MASK 0x00000008L 2286*b843c749SSergey Zigachev #define CRTC_STATUS__CRTC_V_UPDATE__SHIFT 0x00000003 2287*b843c749SSergey Zigachev #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT_MASK 0x00ffffffL 2288*b843c749SSergey Zigachev #define CRTC_STATUS_FRAME_COUNT__CRTC_FRAME_COUNT__SHIFT 0x00000000 2289*b843c749SSergey Zigachev #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT_MASK 0x1fffffffL 2290*b843c749SSergey Zigachev #define CRTC_STATUS_HV_COUNT__CRTC_HV_COUNT__SHIFT 0x00000000 2291*b843c749SSergey Zigachev #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT_MASK 0x1fff0000L 2292*b843c749SSergey Zigachev #define CRTC_STATUS_POSITION__CRTC_HORZ_COUNT__SHIFT 0x00000010 2293*b843c749SSergey Zigachev #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT_MASK 0x00001fffL 2294*b843c749SSergey Zigachev #define CRTC_STATUS_POSITION__CRTC_VERT_COUNT__SHIFT 0x00000000 2295*b843c749SSergey Zigachev #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT_MASK 0x1fffffffL 2296*b843c749SSergey Zigachev #define CRTC_STATUS_VF_COUNT__CRTC_VF_COUNT__SHIFT 0x00000000 2297*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN_MASK 0x01000000L 2298*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_EN__SHIFT 0x00000018 2299*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM_MASK 0x00001fffL 2300*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_LINE_NUM__SHIFT 0x00000000 2301*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY_MASK 0x00008000L 2302*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_OUTPUT_POLARITY__SHIFT 0x0000000f 2303*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY_MASK 0x00010000L 2304*b843c749SSergey Zigachev #define CRTC_STEREO_CONTROL__CRTC_STEREO_SYNC_SELECT_POLARITY__SHIFT 0x00000010 2305*b843c749SSergey Zigachev #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE_MASK 0x00000003L 2306*b843c749SSergey Zigachev #define CRTC_STEREO_FORCE_NEXT_EYE__CRTC_STEREO_FORCE_NEXT_EYE__SHIFT 0x00000000 2307*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE_MASK 0x00000001L 2308*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_CURRENT_EYE__SHIFT 0x00000000 2309*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING_MASK 0x03000000L 2310*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_FORCE_NEXT_EYE_PENDING__SHIFT 0x00000018 2311*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT_MASK 0x00000100L 2312*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_OUTPUT__SHIFT 0x00000008 2313*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT_MASK 0x00010000L 2314*b843c749SSergey Zigachev #define CRTC_STEREO_STATUS__CRTC_STEREO_SYNC_SELECT__SHIFT 0x00000010 2315*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA_MASK 0xffffffffL 2316*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_DATA__CRTC_TEST_DEBUG_DATA__SHIFT 0x00000000 2317*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX_MASK 0x000000ffL 2318*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_INDEX__SHIFT 0x00000000 2319*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 2320*b843c749SSergey Zigachev #define CRTC_TEST_DEBUG_INDEX__CRTC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 2321*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA_MASK 0x0000ffffL 2322*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_DATA__SHIFT 0x00000000 2323*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK_MASK 0x003f0000L 2324*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_COLOR__CRTC_TEST_PATTERN_MASK__SHIFT 0x00000010 2325*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT_MASK 0xff000000L 2326*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_COLOR_FORMAT__SHIFT 0x00000018 2327*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE_MASK 0x00010000L 2328*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_DYNAMIC_RANGE__SHIFT 0x00000010 2329*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN_MASK 0x00000001L 2330*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_EN__SHIFT 0x00000000 2331*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE_MASK 0x00000700L 2332*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_CONTROL__CRTC_TEST_PATTERN_MODE__SHIFT 0x00000008 2333*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES_MASK 0x0000f000L 2334*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_HRES__SHIFT 0x0000000c 2335*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0_MASK 0x0000000fL 2336*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC0__SHIFT 0x00000000 2337*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1_MASK 0x000000f0L 2338*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_INC1__SHIFT 0x00000004 2339*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET_MASK 0xffff0000L 2340*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_RAMP0_OFFSET__SHIFT 0x00000010 2341*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES_MASK 0x00000f00L 2342*b843c749SSergey Zigachev #define CRTC_TEST_PATTERN_PARAMETERS__CRTC_TEST_PATTERN_VRES__SHIFT 0x00000008 2343*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR_MASK 0x80000000L 2344*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_CLEAR__SHIFT 0x0000001f 2345*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY_MASK 0x1f000000L 2346*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_DELAY__SHIFT 0x00000018 2347*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2348*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2349*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT_MASK 0x00300000L 2350*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_FREQUENCY_SELECT__SHIFT 0x00000014 2351*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS_MASK 0x00000200L 2352*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_INPUT_STATUS__SHIFT 0x00000009 2353*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED_MASK 0x00000800L 2354*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_OCCURRED__SHIFT 0x0000000b 2355*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT_MASK 0x000000e0L 2356*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_SELECT__SHIFT 0x00000005 2357*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS_MASK 0x00000400L 2358*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_POLARITY_STATUS__SHIFT 0x0000000a 2359*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN_MASK 0x00000100L 2360*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RESYNC_BYPASS_EN__SHIFT 0x00000008 2361*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2362*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2363*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT_MASK 0x0000001fL 2364*b843c749SSergey Zigachev #define CRTC_TRIGA_CNTL__CRTC_TRIGA_SOURCE_SELECT__SHIFT 0x00000000 2365*b843c749SSergey Zigachev #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG_MASK 0x00000001L 2366*b843c749SSergey Zigachev #define CRTC_TRIGA_MANUAL_TRIG__CRTC_TRIGA_MANUAL_TRIG__SHIFT 0x00000000 2367*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR_MASK 0x80000000L 2368*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_CLEAR__SHIFT 0x0000001f 2369*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY_MASK 0x1f000000L 2370*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_DELAY__SHIFT 0x00000018 2371*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL_MASK 0x00030000L 2372*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FALLING_EDGE_DETECT_CNTL__SHIFT 0x00000010 2373*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT_MASK 0x00300000L 2374*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_FREQUENCY_SELECT__SHIFT 0x00000014 2375*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS_MASK 0x00000200L 2376*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_INPUT_STATUS__SHIFT 0x00000009 2377*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED_MASK 0x00000800L 2378*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_OCCURRED__SHIFT 0x0000000b 2379*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT_MASK 0x000000e0L 2380*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_SELECT__SHIFT 0x00000005 2381*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS_MASK 0x00000400L 2382*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_POLARITY_STATUS__SHIFT 0x0000000a 2383*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN_MASK 0x00000100L 2384*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RESYNC_BYPASS_EN__SHIFT 0x00000008 2385*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL_MASK 0x00003000L 2386*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_RISING_EDGE_DETECT_CNTL__SHIFT 0x0000000c 2387*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT_MASK 0x0000001fL 2388*b843c749SSergey Zigachev #define CRTC_TRIGB_CNTL__CRTC_TRIGB_SOURCE_SELECT__SHIFT 0x00000000 2389*b843c749SSergey Zigachev #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG_MASK 0x00000001L 2390*b843c749SSergey Zigachev #define CRTC_TRIGB_MANUAL_TRIG__CRTC_TRIGB_MANUAL_TRIG__SHIFT 0x00000000 2391*b843c749SSergey Zigachev #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK_MASK 0x00000001L 2392*b843c749SSergey Zigachev #define CRTC_UPDATE_LOCK__CRTC_UPDATE_LOCK__SHIFT 0x00000000 2393*b843c749SSergey Zigachev #define CRTC_VBI_END__CRTC_VBI_H_END_MASK 0x1fff0000L 2394*b843c749SSergey Zigachev #define CRTC_VBI_END__CRTC_VBI_H_END__SHIFT 0x00000010 2395*b843c749SSergey Zigachev #define CRTC_VBI_END__CRTC_VBI_V_END_MASK 0x00001fffL 2396*b843c749SSergey Zigachev #define CRTC_VBI_END__CRTC_VBI_V_END__SHIFT 0x00000000 2397*b843c749SSergey Zigachev #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END_MASK 0x1fff0000L 2398*b843c749SSergey Zigachev #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_END__SHIFT 0x00000010 2399*b843c749SSergey Zigachev #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK 0x00001fffL 2400*b843c749SSergey Zigachev #define CRTC_V_BLANK_START_END__CRTC_V_BLANK_START__SHIFT 0x00000000 2401*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE_MASK 0x00030000L 2402*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_AUTO_FORCE_VSYNC_MODE__SHIFT 0x00000010 2403*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_MASK 0x00000100L 2404*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR__SHIFT 0x00000008 2405*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED_MASK 0x00000001L 2406*b843c749SSergey Zigachev #define CRTC_VERT_SYNC_CONTROL__CRTC_FORCE_VSYNC_NEXT_LINE_OCCURRED__SHIFT 0x00000000 2407*b843c749SSergey Zigachev #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE_MASK 0x00000001L 2408*b843c749SSergey Zigachev #define CRTC_VGA_PARAMETER_CAPTURE_MODE__CRTC_VGA_PARAMETER_CAPTURE_MODE__SHIFT 0x00000000 2409*b843c749SSergey Zigachev #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL_MASK 0x00000001L 2410*b843c749SSergey Zigachev #define CRTC_V_SYNC_A_CNTL__CRTC_V_SYNC_A_POL__SHIFT 0x00000000 2411*b843c749SSergey Zigachev #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END_MASK 0x1fff0000L 2412*b843c749SSergey Zigachev #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_END__SHIFT 0x00000010 2413*b843c749SSergey Zigachev #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START_MASK 0x00001fffL 2414*b843c749SSergey Zigachev #define CRTC_V_SYNC_A__CRTC_V_SYNC_A_START__SHIFT 0x00000000 2415*b843c749SSergey Zigachev #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL_MASK 0x00000001L 2416*b843c749SSergey Zigachev #define CRTC_V_SYNC_B_CNTL__CRTC_V_SYNC_B_POL__SHIFT 0x00000000 2417*b843c749SSergey Zigachev #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END_MASK 0x1fff0000L 2418*b843c749SSergey Zigachev #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_END__SHIFT 0x00000010 2419*b843c749SSergey Zigachev #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START_MASK 0x00001fffL 2420*b843c749SSergey Zigachev #define CRTC_V_SYNC_B__CRTC_V_SYNC_B_START__SHIFT 0x00000000 2421*b843c749SSergey Zigachev #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR_MASK 0x00000010L 2422*b843c749SSergey Zigachev #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_INT_CLEAR__SHIFT 0x00000004 2423*b843c749SSergey Zigachev #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM_MASK 0x00000001L 2424*b843c749SSergey Zigachev #define CRTC_VSYNC_NOM_INT_STATUS__CRTC_VSYNC_NOM__SHIFT 0x00000000 2425*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT_MASK 0x00000100L 2426*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT__SHIFT 0x00000008 2427*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC_MASK 0x00001000L 2428*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC__SHIFT 0x0000000c 2429*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK_MASK 0xffff0000L 2430*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK__SHIFT 0x00000010 2431*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL_MASK 0x00000010L 2432*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL__SHIFT 0x00000004 2433*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL_MASK 0x00000001L 2434*b843c749SSergey Zigachev #define CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL__SHIFT 0x00000000 2435*b843c749SSergey Zigachev #define CRTC_V_TOTAL__CRTC_V_TOTAL_MASK 0x00001fffL 2436*b843c749SSergey Zigachev #define CRTC_V_TOTAL__CRTC_V_TOTAL__SHIFT 0x00000000 2437*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_MASK 0x00000100L 2438*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK__SHIFT 0x00000008 2439*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000010L 2440*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x00000004 2441*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MASK 0x00000001L 2442*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK_MASK 0x00001000L 2443*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_MSK__SHIFT 0x0000000c 2444*b843c749SSergey Zigachev #define CRTC_V_TOTAL_INT_STATUS__CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED__SHIFT 0x00000000 2445*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING_MASK 0x00010000L 2446*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MAX__CRTC_ALLOW_VBLANK_EXTENSION_FOR_MC_TRAINING__SHIFT 0x00000010 2447*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX_MASK 0x00001fffL 2448*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MAX__CRTC_V_TOTAL_MAX__SHIFT 0x00000000 2449*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN_MASK 0x00001fffL 2450*b843c749SSergey Zigachev #define CRTC_V_TOTAL_MIN__CRTC_V_TOTAL_MIN__SHIFT 0x00000000 2451*b843c749SSergey Zigachev #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK 0x00000100L 2452*b843c749SSergey Zigachev #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR__SHIFT 0x00000008 2453*b843c749SSergey Zigachev #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED_MASK 0x00000001L 2454*b843c749SSergey Zigachev #define CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_OCCURRED__SHIFT 0x00000000 2455*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_BLUE_MASK 0x000000ffL 2456*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_BLUE__SHIFT 0x00000000 2457*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_GREEN_MASK 0x0000ff00L 2458*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_GREEN__SHIFT 0x00000008 2459*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_RED_MASK 0x00ff0000L 2460*b843c749SSergey Zigachev #define CUR_COLOR1__CUR_COLOR1_RED__SHIFT 0x00000010 2461*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_BLUE_MASK 0x000000ffL 2462*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_BLUE__SHIFT 0x00000000 2463*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_GREEN_MASK 0x0000ff00L 2464*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_GREEN__SHIFT 0x00000008 2465*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_RED_MASK 0x00ff0000L 2466*b843c749SSergey Zigachev #define CUR_COLOR2__CUR_COLOR2_RED__SHIFT 0x00000010 2467*b843c749SSergey Zigachev #define CUR_CONTROL__CUR_INV_TRANS_CLAMP_MASK 0x00000010L 2468*b843c749SSergey Zigachev #define CUR_CONTROL__CUR_INV_TRANS_CLAMP__SHIFT 0x00000004 2469*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x00010000L 2470*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x00000010 2471*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_EN_MASK 0x00000001L 2472*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_EN__SHIFT 0x00000000 2473*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_FORCE_MC_ON_MASK 0x00100000L 2474*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_FORCE_MC_ON__SHIFT 0x00000014 2475*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_MODE_MASK 0x00000300L 2476*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_MODE__SHIFT 0x00000008 2477*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_URGENT_CONTROL_MASK 0x07000000L 2478*b843c749SSergey Zigachev #define CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT 0x00000018 2479*b843c749SSergey Zigachev #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X_MASK 0x003f0000L 2480*b843c749SSergey Zigachev #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_X__SHIFT 0x00000010 2481*b843c749SSergey Zigachev #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y_MASK 0x0000003fL 2482*b843c749SSergey Zigachev #define CUR_HOT_SPOT__CURSOR_HOT_SPOT_Y__SHIFT 0x00000000 2483*b843c749SSergey Zigachev #define CUR_POSITION__CURSOR_X_POSITION_MASK 0x3fff0000L 2484*b843c749SSergey Zigachev #define CUR_POSITION__CURSOR_X_POSITION__SHIFT 0x00000010 2485*b843c749SSergey Zigachev #define CUR_POSITION__CURSOR_Y_POSITION_MASK 0x00003fffL 2486*b843c749SSergey Zigachev #define CUR_POSITION__CURSOR_Y_POSITION__SHIFT 0x00000000 2487*b843c749SSergey Zigachev #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS_MASK 0x00000001L 2488*b843c749SSergey Zigachev #define CUR_REQUEST_FILTER_CNTL__CUR_REQUEST_FILTER_DIS__SHIFT 0x00000000 2489*b843c749SSergey Zigachev #define CUR_SIZE__CURSOR_HEIGHT_MASK 0x0000003fL 2490*b843c749SSergey Zigachev #define CUR_SIZE__CURSOR_HEIGHT__SHIFT 0x00000000 2491*b843c749SSergey Zigachev #define CUR_SIZE__CURSOR_WIDTH_MASK 0x003f0000L 2492*b843c749SSergey Zigachev #define CUR_SIZE__CURSOR_WIDTH__SHIFT 0x00000010 2493*b843c749SSergey Zigachev #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS_MASK 0xffffffffL 2494*b843c749SSergey Zigachev #define CUR_SURFACE_ADDRESS__CURSOR_SURFACE_ADDRESS__SHIFT 0x00000000 2495*b843c749SSergey Zigachev #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 2496*b843c749SSergey Zigachev #define CUR_SURFACE_ADDRESS_HIGH__CURSOR_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 2497*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 2498*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 2499*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK 0x00010000L 2500*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_LOCK__SHIFT 0x00000010 2501*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_PENDING_MASK 0x00000001L 2502*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_PENDING__SHIFT 0x00000000 2503*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_TAKEN_MASK 0x00000002L 2504*b843c749SSergey Zigachev #define CUR_UPDATE__CURSOR_UPDATE_TAKEN__SHIFT 0x00000001 2505*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK 0x00000001L 2506*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_MODE_ENABLE__SHIFT 0x00000000 2507*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2508*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2509*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_ROTATE_MASK 0x03000000L 2510*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_ROTATE__SHIFT 0x00000018 2511*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2512*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2513*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK 0x00000100L 2514*b843c749SSergey Zigachev #define D1VGA_CONTROL__D1VGA_TIMING_SELECT__SHIFT 0x00000008 2515*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_MODE_ENABLE_MASK 0x00000001L 2516*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_MODE_ENABLE__SHIFT 0x00000000 2517*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2518*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2519*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_ROTATE_MASK 0x03000000L 2520*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_ROTATE__SHIFT 0x00000018 2521*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2522*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2523*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_TIMING_SELECT_MASK 0x00000100L 2524*b843c749SSergey Zigachev #define D2VGA_CONTROL__D2VGA_TIMING_SELECT__SHIFT 0x00000008 2525*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_MODE_ENABLE_MASK 0x00000001L 2526*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_MODE_ENABLE__SHIFT 0x00000000 2527*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2528*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2529*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_ROTATE_MASK 0x03000000L 2530*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_ROTATE__SHIFT 0x00000018 2531*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2532*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2533*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_TIMING_SELECT_MASK 0x00000100L 2534*b843c749SSergey Zigachev #define D3VGA_CONTROL__D3VGA_TIMING_SELECT__SHIFT 0x00000008 2535*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_MODE_ENABLE_MASK 0x00000001L 2536*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_MODE_ENABLE__SHIFT 0x00000000 2537*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2538*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2539*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_ROTATE_MASK 0x03000000L 2540*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_ROTATE__SHIFT 0x00000018 2541*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2542*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2543*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_TIMING_SELECT_MASK 0x00000100L 2544*b843c749SSergey Zigachev #define D4VGA_CONTROL__D4VGA_TIMING_SELECT__SHIFT 0x00000008 2545*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_MODE_ENABLE_MASK 0x00000001L 2546*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_MODE_ENABLE__SHIFT 0x00000000 2547*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2548*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2549*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_ROTATE_MASK 0x03000000L 2550*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_ROTATE__SHIFT 0x00000018 2551*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2552*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2553*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_TIMING_SELECT_MASK 0x00000100L 2554*b843c749SSergey Zigachev #define D5VGA_CONTROL__D5VGA_TIMING_SELECT__SHIFT 0x00000008 2555*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_MODE_ENABLE_MASK 0x00000001L 2556*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_MODE_ENABLE__SHIFT 0x00000000 2557*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN_MASK 0x00010000L 2558*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_OVERSCAN_COLOR_EN__SHIFT 0x00000010 2559*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_ROTATE_MASK 0x03000000L 2560*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_ROTATE__SHIFT 0x00000018 2561*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT_MASK 0x00000200L 2562*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_SYNC_POLARITY_SELECT__SHIFT 0x00000009 2563*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_TIMING_SELECT_MASK 0x00000100L 2564*b843c749SSergey Zigachev #define D6VGA_CONTROL__D6VGA_TIMING_SELECT__SHIFT 0x00000008 2565*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER_MASK 0x000000ffL 2566*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_POWERUP_COUNTER__SHIFT 0x00000000 2567*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE_MASK 0x00000100L 2568*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL2__DAC_AUTODETECT_TESTMODE__SHIFT 0x00000008 2569*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY_MASK 0x000000ffL 2570*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_IN_DELAY__SHIFT 0x00000000 2571*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY_MASK 0x0000ff00L 2572*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL3__DAC_AUTODET_COMPARATOR_OUT_DELAY__SHIFT 0x00000008 2573*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK_MASK 0x00070000L 2574*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_CHECK_MASK__SHIFT 0x00000010 2575*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER_MASK 0x0000ff00L 2576*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_FRAME_TIME_COUNTER__SHIFT 0x00000008 2577*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE_MASK 0x00000003L 2578*b843c749SSergey Zigachev #define DAC_AUTODETECT_CONTROL__DAC_AUTODETECT_MODE__SHIFT 0x00000000 2579*b843c749SSergey Zigachev #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK_MASK 0x00000001L 2580*b843c749SSergey Zigachev #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_ACK__SHIFT 0x00000000 2581*b843c749SSergey Zigachev #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE_MASK 0x00010000L 2582*b843c749SSergey Zigachev #define DAC_AUTODETECT_INT_CONTROL__DAC_AUTODETECT_INT_ENABLE__SHIFT 0x00000010 2583*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE_MASK 0x03000000L 2584*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_BLUE_SENSE__SHIFT 0x00000018 2585*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT_MASK 0x00000010L 2586*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_CONNECT__SHIFT 0x00000004 2587*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE_MASK 0x00030000L 2588*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_GREEN_SENSE__SHIFT 0x00000010 2589*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE_MASK 0x00000300L 2590*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_RED_SENSE__SHIFT 0x00000008 2591*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS_MASK 0x00000001L 2592*b843c749SSergey Zigachev #define DAC_AUTODETECT_STATUS__DAC_AUTODETECT_STATUS__SHIFT 0x00000000 2593*b843c749SSergey Zigachev #define DAC_CLK_ENABLE__DACA_CLK_ENABLE_MASK 0x00000001L 2594*b843c749SSergey Zigachev #define DAC_CLK_ENABLE__DACA_CLK_ENABLE__SHIFT 0x00000000 2595*b843c749SSergey Zigachev #define DAC_CLK_ENABLE__DACB_CLK_ENABLE_MASK 0x00000010L 2596*b843c749SSergey Zigachev #define DAC_CLK_ENABLE__DACB_CLK_ENABLE__SHIFT 0x00000004 2597*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE_MASK 0x00040000L 2598*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_B_ASYNC_ENABLE__SHIFT 0x00000012 2599*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN_MASK 0x00000001L 2600*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_COMP_DDET_REF_EN__SHIFT 0x00000000 2601*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN_MASK 0x00000100L 2602*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_COMP_SDET_REF_EN__SHIFT 0x00000008 2603*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE_MASK 0x00020000L 2604*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_G_ASYNC_ENABLE__SHIFT 0x00000011 2605*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE_MASK 0x00010000L 2606*b843c749SSergey Zigachev #define DAC_COMPARATOR_ENABLE__DAC_R_ASYNC_ENABLE__SHIFT 0x00000010 2607*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE_MASK 0x00000002L 2608*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_BLUE__SHIFT 0x00000001 2609*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN_MASK 0x00000004L 2610*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_GREEN__SHIFT 0x00000002 2611*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_MASK 0x00000001L 2612*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED_MASK 0x00000008L 2613*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT_RED__SHIFT 0x00000003 2614*b843c749SSergey Zigachev #define DAC_COMPARATOR_OUTPUT__DAC_COMPARATOR_OUTPUT__SHIFT 0x00000000 2615*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_DFORCE_EN_MASK 0x00000001L 2616*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_DFORCE_EN__SHIFT 0x00000000 2617*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_TV_ENABLE_MASK 0x00000100L 2618*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_TV_ENABLE__SHIFT 0x00000008 2619*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_ZSCALE_SHIFT_MASK 0x00010000L 2620*b843c749SSergey Zigachev #define DAC_CONTROL__DAC_ZSCALE_SHIFT__SHIFT 0x00000010 2621*b843c749SSergey Zigachev #define DAC_CRC_CONTROL__DAC_CRC_FIELD_MASK 0x00000001L 2622*b843c749SSergey Zigachev #define DAC_CRC_CONTROL__DAC_CRC_FIELD__SHIFT 0x00000000 2623*b843c749SSergey Zigachev #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb_MASK 0x00000100L 2624*b843c749SSergey Zigachev #define DAC_CRC_CONTROL__DAC_CRC_ONLY_BLANKb__SHIFT 0x00000008 2625*b843c749SSergey Zigachev #define DAC_CRC_EN__DAC_CRC_CONT_EN_MASK 0x00010000L 2626*b843c749SSergey Zigachev #define DAC_CRC_EN__DAC_CRC_CONT_EN__SHIFT 0x00000010 2627*b843c749SSergey Zigachev #define DAC_CRC_EN__DAC_CRC_EN_MASK 0x00000001L 2628*b843c749SSergey Zigachev #define DAC_CRC_EN__DAC_CRC_EN__SHIFT 0x00000000 2629*b843c749SSergey Zigachev #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL_MASK 0x0000003fL 2630*b843c749SSergey Zigachev #define DAC_CRC_SIG_CONTROL__DAC_CRC_SIG_CONTROL__SHIFT 0x00000000 2631*b843c749SSergey Zigachev #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK_MASK 0x0000003fL 2632*b843c749SSergey Zigachev #define DAC_CRC_SIG_CONTROL_MASK__DAC_CRC_SIG_CONTROL_MASK__SHIFT 0x00000000 2633*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE_MASK 0x000003ffL 2634*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_BLUE__SHIFT 0x00000000 2635*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN_MASK 0x000ffc00L 2636*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_GREEN__SHIFT 0x0000000a 2637*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED_MASK 0x3ff00000L 2638*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB__DAC_CRC_SIG_RED__SHIFT 0x00000014 2639*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK_MASK 0x000003ffL 2640*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 2641*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK_MASK 0x000ffc00L 2642*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_GREEN_MASK__SHIFT 0x0000000a 2643*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK_MASK 0x3ff00000L 2644*b843c749SSergey Zigachev #define DAC_CRC_SIG_RGB_MASK__DAC_CRC_SIG_RED_MASK__SHIFT 0x00000014 2645*b843c749SSergey Zigachev #define DAC_DATA__DAC_DATA_MASK 0x0000003fL 2646*b843c749SSergey Zigachev #define DAC_DATA__DAC_DATA__SHIFT 0x00000000 2647*b843c749SSergey Zigachev #define DAC_DFT_CONFIG__DAC_DFT_CONFIG_MASK 0xffffffffL 2648*b843c749SSergey Zigachev #define DAC_DFT_CONFIG__DAC_DFT_CONFIG__SHIFT 0x00000000 2649*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_ENABLE_MASK 0x00000001L 2650*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_ENABLE__SHIFT 0x00000000 2651*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE_MASK 0x00000002L 2652*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ENABLE__SHIFT 0x00000001 2653*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK_MASK 0x00000020L 2654*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_ACK__SHIFT 0x00000005 2655*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR_MASK 0x00000010L 2656*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_ERROR__SHIFT 0x00000004 2657*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW_MASK 0x0000000cL 2658*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_POINTER_SKEW__SHIFT 0x00000002 2659*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM_MASK 0x00000100L 2660*b843c749SSergey Zigachev #define DAC_ENABLE__DAC_RESYNC_FIFO_TVOUT_SIM__SHIFT 0x00000008 2661*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 2662*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 2663*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED_MASK 0x20000000L 2664*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_CALIBRATED__SHIFT 0x0000001d 2665*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 2666*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 2667*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 2668*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 2669*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 2670*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 2671*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 2672*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 2673*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 2674*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 2675*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 2676*b843c749SSergey Zigachev #define DAC_FIFO_STATUS__DAC_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 2677*b843c749SSergey Zigachev #define DAC_FORCE_DATA__DAC_FORCE_DATA_MASK 0x000003ffL 2678*b843c749SSergey Zigachev #define DAC_FORCE_DATA__DAC_FORCE_DATA__SHIFT 0x00000000 2679*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN_MASK 0x00000001L 2680*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_EN__SHIFT 0x00000000 2681*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x01000000L 2682*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000018 2683*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL_MASK 0x00000700L 2684*b843c749SSergey Zigachev #define DAC_FORCE_OUTPUT_CNTL__DAC_FORCE_DATA_SEL__SHIFT 0x00000008 2685*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2686*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED0__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2687*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2688*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED1__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2689*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2690*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED2__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2691*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED_MASK 0xffffffffL 2692*b843c749SSergey Zigachev #define DAC_MACRO_CNTL_RESERVED3__DAC_MACRO_CNTL_RESERVED__SHIFT 0x00000000 2693*b843c749SSergey Zigachev #define DAC_MASK__DAC_MASK_MASK 0x000000ffL 2694*b843c749SSergey Zigachev #define DAC_MASK__DAC_MASK__SHIFT 0x00000000 2695*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE_MASK 0x00000100L 2696*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_BLUE__SHIFT 0x00000008 2697*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN_MASK 0x00010000L 2698*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_GREEN__SHIFT 0x00000010 2699*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_MASK 0x00000001L 2700*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_RED_MASK 0x01000000L 2701*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN_RED__SHIFT 0x00000018 2702*b843c749SSergey Zigachev #define DAC_POWERDOWN__DAC_POWERDOWN__SHIFT 0x00000000 2703*b843c749SSergey Zigachev #define DAC_PWR_CNTL__DAC_BG_MODE_MASK 0x00000003L 2704*b843c749SSergey Zigachev #define DAC_PWR_CNTL__DAC_BG_MODE__SHIFT 0x00000000 2705*b843c749SSergey Zigachev #define DAC_PWR_CNTL__DAC_PWRCNTL_MASK 0x00030000L 2706*b843c749SSergey Zigachev #define DAC_PWR_CNTL__DAC_PWRCNTL__SHIFT 0x00000010 2707*b843c749SSergey Zigachev #define DAC_R_INDEX__DAC_R_INDEX_MASK 0x000000ffL 2708*b843c749SSergey Zigachev #define DAC_R_INDEX__DAC_R_INDEX__SHIFT 0x00000000 2709*b843c749SSergey Zigachev #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT_MASK 0x00000007L 2710*b843c749SSergey Zigachev #define DAC_SOURCE_SELECT__DAC_SOURCE_SELECT__SHIFT 0x00000000 2711*b843c749SSergey Zigachev #define DAC_SOURCE_SELECT__DAC_TV_SELECT_MASK 0x00000008L 2712*b843c749SSergey Zigachev #define DAC_SOURCE_SELECT__DAC_TV_SELECT__SHIFT 0x00000003 2713*b843c749SSergey Zigachev #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT_MASK 0x00000007L 2714*b843c749SSergey Zigachev #define DAC_STEREOSYNC_SELECT__DAC_STEREOSYNC_SELECT__SHIFT 0x00000000 2715*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE_MASK 0x00000001L 2716*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_HSYNCA_TRISTATE__SHIFT 0x00000000 2717*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE_MASK 0x00010000L 2718*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_SYNCA_TRISTATE__SHIFT 0x00000010 2719*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE_MASK 0x00000100L 2720*b843c749SSergey Zigachev #define DAC_SYNC_TRISTATE_CONTROL__DAC_VSYNCA_TRISTATE__SHIFT 0x00000008 2721*b843c749SSergey Zigachev #define DAC_W_INDEX__DAC_W_INDEX_MASK 0x000000ffL 2722*b843c749SSergey Zigachev #define DAC_W_INDEX__DAC_W_INDEX__SHIFT 0x00000000 2723*b843c749SSergey Zigachev #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR_MASK 0x00000100L 2724*b843c749SSergey Zigachev #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_CLEAR__SHIFT 0x00000008 2725*b843c749SSergey Zigachev #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME_MASK 0x00000001L 2726*b843c749SSergey Zigachev #define DC_ABM1_ACE_CNTL_MISC__ABM1_ACE_REG_WR_MISSED_FRAME__SHIFT 0x00000000 2727*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK_MASK 0x80000000L 2728*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_LOCK__SHIFT 0x0000001f 2729*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0_MASK 0x07ff0000L 2730*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_OFFSET_0__SHIFT 0x00000010 2731*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0_MASK 0x00007fffL 2732*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_0__ABM1_ACE_SLOPE_0__SHIFT 0x00000000 2733*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK_MASK 0x80000000L 2734*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_LOCK__SHIFT 0x0000001f 2735*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1_MASK 0x07ff0000L 2736*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_OFFSET_1__SHIFT 0x00000010 2737*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1_MASK 0x00007fffL 2738*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_1__ABM1_ACE_SLOPE_1__SHIFT 0x00000000 2739*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK_MASK 0x80000000L 2740*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_LOCK__SHIFT 0x0000001f 2741*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2_MASK 0x07ff0000L 2742*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_OFFSET_2__SHIFT 0x00000010 2743*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2_MASK 0x00007fffL 2744*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_2__ABM1_ACE_SLOPE_2__SHIFT 0x00000000 2745*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK_MASK 0x80000000L 2746*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_LOCK__SHIFT 0x0000001f 2747*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3_MASK 0x07ff0000L 2748*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_OFFSET_3__SHIFT 0x00000010 2749*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3_MASK 0x00007fffL 2750*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_3__ABM1_ACE_SLOPE_3__SHIFT 0x00000000 2751*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK_MASK 0x80000000L 2752*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_LOCK__SHIFT 0x0000001f 2753*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4_MASK 0x07ff0000L 2754*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_OFFSET_4__SHIFT 0x00000010 2755*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4_MASK 0x00007fffL 2756*b843c749SSergey Zigachev #define DC_ABM1_ACE_OFFSET_SLOPE_4__ABM1_ACE_SLOPE_4__SHIFT 0x00000000 2757*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK_MASK 0x80000000L 2758*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_LOCK__SHIFT 0x0000001f 2759*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1_MASK 0x000003ffL 2760*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_1__SHIFT 0x00000000 2761*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2_MASK 0x03ff0000L 2762*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_12__ABM1_ACE_THRES_2__SHIFT 0x00000010 2763*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING_MASK 0x40000000L 2764*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_DBUF_REG_UPDATE_PENDING__SHIFT 0x0000001e 2765*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN_MASK 0x10000000L 2766*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001c 2767*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK_MASK 0x80000000L 2768*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_LOCK__SHIFT 0x0000001f 2769*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN_MASK 0x20000000L 2770*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_READBACK_DB_REG_VALUE_EN__SHIFT 0x0000001d 2771*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3_MASK 0x000003ffL 2772*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_3__SHIFT 0x00000000 2773*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4_MASK 0x03ff0000L 2774*b843c749SSergey Zigachev #define DC_ABM1_ACE_THRES_34__ABM1_ACE_THRES_4__SHIFT 0x00000010 2775*b843c749SSergey Zigachev #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK_MASK 0x80000000L 2776*b843c749SSergey Zigachev #define DC_ABM1_BL_MASTER_LOCK__ABM1_BL_MASTER_LOCK__SHIFT 0x0000001f 2777*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE_MASK 0x80000000L 2778*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_BLANK_MODE_SUPPORT_ENABLE__SHIFT 0x0000001f 2779*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_EN_MASK 0x00000001L 2780*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_EN__SHIFT 0x00000000 2781*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT_MASK 0x00000700L 2782*b843c749SSergey Zigachev #define DC_ABM1_CNTL__ABM1_SOURCE_SELECT__SHIFT 0x00000008 2783*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT_MASK 0x00010000L 2784*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_BL_FORCE_INTERRUPT__SHIFT 0x00000010 2785*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT_MASK 0x00000001L 2786*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_HG_FORCE_INTERRUPT__SHIFT 0x00000000 2787*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT_MASK 0x00000100L 2788*b843c749SSergey Zigachev #define DC_ABM1_DEBUG_MISC__ABM1_LS_FORCE_INTERRUPT__SHIFT 0x00000008 2789*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG_MASK 0xffffffffL 2790*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_1_32_SHIFT_FLAG__ABM1_HG_BIN_1_32_SHIFT_FLAG__SHIFT 0x00000000 2791*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX_MASK 0xffffffffL 2792*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_17_24_SHIFT_INDEX__ABM1_HG_BIN_17_24_SHIFT_INDEX__SHIFT 0x00000000 2793*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX_MASK 0xffffffffL 2794*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_1_8_SHIFT_INDEX__ABM1_HG_BIN_1_8_SHIFT_INDEX__SHIFT 0x00000000 2795*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX_MASK 0xffffffffL 2796*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_25_32_SHIFT_INDEX__ABM1_HG_BIN_25_32_SHIFT_INDEX__SHIFT 0x00000000 2797*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX_MASK 0xffffffffL 2798*b843c749SSergey Zigachev #define DC_ABM1_HG_BIN_9_16_SHIFT_INDEX__ABM1_HG_BIN_9_16_SHIFT_INDEX__SHIFT 0x00000000 2799*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS_MASK 0x00000004L 2800*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_IN_PROGRESS__SHIFT 0x00000002 2801*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR_MASK 0x80000000L 2802*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x0000001f 2803*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME_MASK 0x00000400L 2804*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_BL_REG_READ_MISSED_FRAME__SHIFT 0x0000000a 2805*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS_MASK 0x00000001L 2806*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_IN_PROGRESS__SHIFT 0x00000000 2807*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR_MASK 0x00010000L 2808*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000010 2809*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME_MASK 0x00000100L 2810*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_HG_REG_READ_MISSED_FRAME__SHIFT 0x00000008 2811*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS_MASK 0x00000002L 2812*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_IN_PROGRESS__SHIFT 0x00000001 2813*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR_MASK 0x01000000L 2814*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_CLEAR__SHIFT 0x00000018 2815*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME_MASK 0x00000200L 2816*b843c749SSergey Zigachev #define DC_ABM1_HGLS_REG_READ_PROGRESS__ABM1_LS_REG_READ_MISSED_FRAME__SHIFT 0x00000009 2817*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN_MASK 0x00800000L 2818*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_READBACK_DB_REG_VALUE_EN__SHIFT 0x00000017 2819*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL_MASK 0x07000000L 2820*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_FRAME_START_DISP_SEL__SHIFT 0x00000018 2821*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START_MASK 0x10000000L 2822*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_AT_FRAME_START__SHIFT 0x0000001c 2823*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING_MASK 0x40000000L 2824*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_DBUF_HGLS_REG_UPDATE_PENDING__SHIFT 0x0000001e 2825*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL_MASK 0x00030000L 2826*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_BIN_BITWIDTH_SIZE_SEL__SHIFT 0x00000010 2827*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL_MASK 0x00001000L 2828*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_FINE_MODE_BIN_SEL__SHIFT 0x0000000c 2829*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN_MASK 0x20000000L 2830*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_IGNORE_MASTER_LOCK_EN__SHIFT 0x0000001d 2831*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2832*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2833*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL_MASK 0x00000003L 2834*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_NUM_OF_BINS_SEL__SHIFT 0x00000000 2835*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL_MASK 0x00000100L 2836*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_HG_VMAX_SEL__SHIFT 0x00000008 2837*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN_MASK 0x00100000L 2838*b843c749SSergey Zigachev #define DC_ABM1_HG_MISC_CTRL__ABM1_OVR_SCAN_PIXEL_PROCESS_EN__SHIFT 0x00000014 2839*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10_MASK 0xffffffffL 2840*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_10__ABM1_HG_RESULT_10__SHIFT 0x00000000 2841*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11_MASK 0xffffffffL 2842*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_11__ABM1_HG_RESULT_11__SHIFT 0x00000000 2843*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12_MASK 0xffffffffL 2844*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_12__ABM1_HG_RESULT_12__SHIFT 0x00000000 2845*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13_MASK 0xffffffffL 2846*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_13__ABM1_HG_RESULT_13__SHIFT 0x00000000 2847*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14_MASK 0xffffffffL 2848*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_14__ABM1_HG_RESULT_14__SHIFT 0x00000000 2849*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15_MASK 0xffffffffL 2850*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_15__ABM1_HG_RESULT_15__SHIFT 0x00000000 2851*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16_MASK 0xffffffffL 2852*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_16__ABM1_HG_RESULT_16__SHIFT 0x00000000 2853*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17_MASK 0xffffffffL 2854*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_17__ABM1_HG_RESULT_17__SHIFT 0x00000000 2855*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18_MASK 0xffffffffL 2856*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_18__ABM1_HG_RESULT_18__SHIFT 0x00000000 2857*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19_MASK 0xffffffffL 2858*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_19__ABM1_HG_RESULT_19__SHIFT 0x00000000 2859*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1_MASK 0xffffffffL 2860*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_1__ABM1_HG_RESULT_1__SHIFT 0x00000000 2861*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20_MASK 0xffffffffL 2862*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_20__ABM1_HG_RESULT_20__SHIFT 0x00000000 2863*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21_MASK 0xffffffffL 2864*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_21__ABM1_HG_RESULT_21__SHIFT 0x00000000 2865*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22_MASK 0xffffffffL 2866*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_22__ABM1_HG_RESULT_22__SHIFT 0x00000000 2867*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23_MASK 0xffffffffL 2868*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_23__ABM1_HG_RESULT_23__SHIFT 0x00000000 2869*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24_MASK 0xffffffffL 2870*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_24__ABM1_HG_RESULT_24__SHIFT 0x00000000 2871*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2_MASK 0xffffffffL 2872*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_2__ABM1_HG_RESULT_2__SHIFT 0x00000000 2873*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3_MASK 0xffffffffL 2874*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_3__ABM1_HG_RESULT_3__SHIFT 0x00000000 2875*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4_MASK 0xffffffffL 2876*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_4__ABM1_HG_RESULT_4__SHIFT 0x00000000 2877*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5_MASK 0xffffffffL 2878*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_5__ABM1_HG_RESULT_5__SHIFT 0x00000000 2879*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6_MASK 0xffffffffL 2880*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_6__ABM1_HG_RESULT_6__SHIFT 0x00000000 2881*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7_MASK 0xffffffffL 2882*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_7__ABM1_HG_RESULT_7__SHIFT 0x00000000 2883*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8_MASK 0xffffffffL 2884*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_8__ABM1_HG_RESULT_8__SHIFT 0x00000000 2885*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9_MASK 0xffffffffL 2886*b843c749SSergey Zigachev #define DC_ABM1_HG_RESULT_9__ABM1_HG_RESULT_9__SHIFT 0x00000000 2887*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2888*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2889*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2890*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2891*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2892*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2893*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2894*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2895*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2896*b843c749SSergey Zigachev #define DC_ABM1_HG_SAMPLE_RATE__ABM1_HG_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2897*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2898*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2899*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B_MASK 0x0000000fL 2900*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_B__SHIFT 0x00000000 2901*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G_MASK 0x00000f00L 2902*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_G__SHIFT 0x00000008 2903*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R_MASK 0x000f0000L 2904*b843c749SSergey Zigachev #define DC_ABM1_IPCSC_COEFF_SEL__ABM1_IPCSC_COEFF_SEL_R__SHIFT 0x00000010 2905*b843c749SSergey Zigachev #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA_MASK 0x03ff0000L 2906*b843c749SSergey Zigachev #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MAX_LUMA__SHIFT 0x00000010 2907*b843c749SSergey Zigachev #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA_MASK 0x000003ffL 2908*b843c749SSergey Zigachev #define DC_ABM1_LS_FILTERED_MIN_MAX_LUMA__ABM1_LS_FILTERED_MIN_LUMA__SHIFT 0x00000000 2909*b843c749SSergey Zigachev #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2910*b843c749SSergey Zigachev #define DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT__ABM1_LS_MAX_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2911*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA_MASK 0x03ff0000L 2912*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MAX_LUMA__SHIFT 0x00000010 2913*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA_MASK 0x000003ffL 2914*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_LUMA__ABM1_LS_MIN_LUMA__SHIFT 0x00000000 2915*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2916*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2917*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES_MASK 0x03ff0000L 2918*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MAX_PIXEL_VALUE_THRES__SHIFT 0x00000010 2919*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES_MASK 0x000003ffL 2920*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES__ABM1_LS_MIN_PIXEL_VALUE_THRES__SHIFT 0x00000000 2921*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT_MASK 0x00ffffffL 2922*b843c749SSergey Zigachev #define DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT__ABM1_LS_MIN_PIXEL_VALUE_COUNT__SHIFT 0x00000000 2923*b843c749SSergey Zigachev #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN_MASK 0x00ffffffL 2924*b843c749SSergey Zigachev #define DC_ABM1_LS_OVR_SCAN_BIN__ABM1_LS_OVR_SCAN_BIN__SHIFT 0x00000000 2925*b843c749SSergey Zigachev #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT_MASK 0x00ffffffL 2926*b843c749SSergey Zigachev #define DC_ABM1_LS_PIXEL_COUNT__ABM1_LS_PIXEL_COUNT__SHIFT 0x00000000 2927*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK_MASK 0x80000000L 2928*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_HGLS_REG_LOCK__SHIFT 0x0000001f 2929*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET_MASK 0x00ff0000L 2930*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_INITIAL_SAMPLE_RATE_COUNT_VALUE_WHEN_RESET__SHIFT 0x00000010 2931*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER_MASK 0x00000002L 2932*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_RESET_SAMPLE_RATE_FRAME_COUNTER__SHIFT 0x00000001 2933*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN_MASK 0x00000001L 2934*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_COUNT_EN__SHIFT 0x00000000 2935*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT_MASK 0x0000ff00L 2936*b843c749SSergey Zigachev #define DC_ABM1_LS_SAMPLE_RATE__ABM1_LS_SAMPLE_RATE_FRAME_COUNT__SHIFT 0x00000008 2937*b843c749SSergey Zigachev #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA_MASK 0xffffffffL 2938*b843c749SSergey Zigachev #define DC_ABM1_LS_SUM_OF_LUMA__ABM1_LS_SUM_OF_LUMA__SHIFT 0x00000000 2939*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE_MASK 0x3ff00000L 2940*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_B_PIXEL_VALUE__SHIFT 0x00000014 2941*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE_MASK 0x000ffc00L 2942*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_G_PIXEL_VALUE__SHIFT 0x0000000a 2943*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE_MASK 0x000003ffL 2944*b843c749SSergey Zigachev #define DC_ABM1_OVERSCAN_PIXEL_VALUE__ABM1_OVERSCAN_R_PIXEL_VALUE__SHIFT 0x00000000 2945*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE_MASK 0xffffffffL 2946*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO0_MODULE__DCCG_AUDIO_DTO0_MODULE__SHIFT 0x00000000 2947*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE_MASK 0xffffffffL 2948*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO0_PHASE__DCCG_AUDIO_DTO0_PHASE__SHIFT 0x00000000 2949*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE_MASK 0xffffffffL 2950*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO1_MODULE__DCCG_AUDIO_DTO1_MODULE__SHIFT 0x00000000 2951*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE_MASK 0xffffffffL 2952*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO1_PHASE__DCCG_AUDIO_DTO1_PHASE__SHIFT 0x00000000 2953*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL_MASK 0x00000007L 2954*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT 0x00000000 2955*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL_MASK 0x00000010L 2956*b843c749SSergey Zigachev #define DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO_SEL__SHIFT 0x00000004 2957*b843c749SSergey Zigachev #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA_MASK 0xffffffffL 2958*b843c749SSergey Zigachev #define DCCG_CAC_STATUS__CAC_STATUS_RDDATA__SHIFT 0x00000000 2959*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE_MASK 0x00000010L 2960*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DACACLK_GATE_DISABLE__SHIFT 0x00000004 2961*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE_MASK 0x00000020L 2962*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DACBCLK_GATE_DISABLE__SHIFT 0x00000005 2963*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE_MASK 0x00000001L 2964*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_DCCG_GATE_DISABLE__SHIFT 0x00000000 2965*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID_MASK 0x07000000L 2966*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_RAMP_DIV_ID__SHIFT 0x00000018 2967*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE_MASK 0x00000002L 2968*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_GATE_DISABLE__SHIFT 0x00000001 2969*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE_MASK 0x00100000L 2970*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DISPCLK_R_DCCG_RAMP_DISABLE__SHIFT 0x00000014 2971*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE_MASK 0x00000040L 2972*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__DVOACLK_GATE_DISABLE__SHIFT 0x00000006 2973*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE_MASK 0x00010000L 2974*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__PCLK_TV_GATE_DISABLE__SHIFT 0x00000010 2975*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE_MASK 0x00000004L 2976*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SCLK_GATE_DISABLE__SHIFT 0x00000002 2977*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID_MASK 0x70000000L 2978*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SCLK_RAMP_DIV_ID__SHIFT 0x0000001c 2979*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE_MASK 0x00000100L 2980*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKA_GATE_DISABLE__SHIFT 0x00000008 2981*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE_MASK 0x00000200L 2982*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKB_GATE_DISABLE__SHIFT 0x00000009 2983*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE_MASK 0x00000400L 2984*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKC_GATE_DISABLE__SHIFT 0x0000000a 2985*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE_MASK 0x00000800L 2986*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKD_GATE_DISABLE__SHIFT 0x0000000b 2987*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE_MASK 0x00001000L 2988*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKE_GATE_DISABLE__SHIFT 0x0000000c 2989*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE_MASK 0x00002000L 2990*b843c749SSergey Zigachev #define DCCG_GATE_DISABLE_CNTL__SYMCLKF_GATE_DISABLE__SHIFT 0x0000000d 2991*b843c749SSergey Zigachev #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE_MASK 0x00000001L 2992*b843c749SSergey Zigachev #define DCCG_GTC_CNTL__DCCG_GTC_ENABLE__SHIFT 0x00000000 2993*b843c749SSergey Zigachev #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT_MASK 0xffffffffL 2994*b843c749SSergey Zigachev #define DCCG_GTC_CURRENT__DCCG_GTC_CURRENT__SHIFT 0x00000000 2995*b843c749SSergey Zigachev #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO_MASK 0xffffffffL 2996*b843c749SSergey Zigachev #define DCCG_GTC_DTO_MODULO__DCCG_GTC_DTO_MODULO__SHIFT 0x00000000 2997*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL_MASK 0x00000700L 2998*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_CRTC_SEL__SHIFT 0x00000008 2999*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE_MASK 0x00000001L 3000*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_DISPCLK_ENABLE__SHIFT 0x00000000 3001*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE_MASK 0x00000002L 3002*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_DPREFCLK_ENABLE__SHIFT 0x00000001 3003*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC_MASK 0x00000080L 3004*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_HSYNC__SHIFT 0x00000007 3005*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC_MASK 0x00000040L 3006*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_MODE_VSYNC__SHIFT 0x00000006 3007*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE_MASK 0x00000010L 3008*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK0_ENABLE__SHIFT 0x00000004 3009*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE_MASK 0x00000004L 3010*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK1_ENABLE__SHIFT 0x00000002 3011*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE_MASK 0x00000008L 3012*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_PIXCLK2_ENABLE__SHIFT 0x00000003 3013*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN_MASK 0x00000020L 3014*b843c749SSergey Zigachev #define DCCG_PERFMON_CNTL__DCCG_PERF_RUN__SHIFT 0x00000005 3015*b843c749SSergey Zigachev #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET_MASK 0x00000001L 3016*b843c749SSergey Zigachev #define DCCG_SOFT_RESET__REFCLK_SOFT_RESET__SHIFT 0x00000000 3017*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV_MASK 0x00010000L 3018*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_INV__SHIFT 0x00000010 3019*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL_MASK 0x000000ffL 3020*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICA_SEL__SHIFT 0x00000000 3021*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV_MASK 0x01000000L 3022*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_INV__SHIFT 0x00000018 3023*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL_MASK 0x0000ff00L 3024*b843c749SSergey Zigachev #define DCCG_TEST_CLK_SEL__DCCG_TEST_CLK_GENERICB_SEL__SHIFT 0x00000008 3025*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA_MASK 0xffffffffL 3026*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_DATA__DCCG_TEST_DEBUG_DATA__SHIFT 0x00000000 3027*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL_MASK 0x00001000L 3028*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_DBG_SEL__SHIFT 0x0000000c 3029*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX_MASK 0x000000ffL 3030*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_INDEX__SHIFT 0x00000000 3031*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 3032*b843c749SSergey Zigachev #define DCCG_TEST_DEBUG_INDEX__DCCG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 3033*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS_MASK 0x00000004L 3034*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__AZ_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3035*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS_MASK 0x04000000L 3036*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__AZ_MEM_SHUTDOWN_DIS__SHIFT 0x0000001a 3037*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL_MASK 0x00000001L 3038*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DCCG_VPCLK_POL__SHIFT 0x00000000 3039*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS_MASK 0x00000008L 3040*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMCU_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3041*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS_MASK 0x00010000L 3042*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMCU_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 3043*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS_MASK 0x00000100L 3044*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF0_LIGHT_SLEEP_DIS__SHIFT 0x00000008 3045*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS_MASK 0x00100000L 3046*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF0_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 3047*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS_MASK 0x00000200L 3048*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF1_LIGHT_SLEEP_DIS__SHIFT 0x00000009 3049*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS_MASK 0x00200000L 3050*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF1_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 3051*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS_MASK 0x00000400L 3052*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF2_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 3053*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS_MASK 0x00400000L 3054*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF2_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 3055*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS_MASK 0x00000800L 3056*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF3_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 3057*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS_MASK 0x00800000L 3058*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF3_MEM_SHUTDOWN_DIS__SHIFT 0x00000017 3059*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS_MASK 0x00001000L 3060*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF4_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 3061*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS_MASK 0x01000000L 3062*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF4_MEM_SHUTDOWN_DIS__SHIFT 0x00000018 3063*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS_MASK 0x00002000L 3064*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF5_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 3065*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS_MASK 0x02000000L 3066*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF5_MEM_SHUTDOWN_DIS__SHIFT 0x00000019 3067*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000020L 3068*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF_XLR_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000005 3069*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00040000L 3070*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__DMIF_XLR_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000012 3071*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS_MASK 0x00004000L 3072*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__FBC_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 3073*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 3074*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__FBC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 3075*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000010L 3076*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__MCIF_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000004 3077*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE_MASK 0x00020000L 3078*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__MCIF_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000011 3079*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE_MASK 0x00000002L 3080*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__VGA_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000001 3081*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS_MASK 0x00008000L 3082*b843c749SSergey Zigachev #define DCCG_VPCLK_CNTL__VIP_LIGHT_SLEEP_DIS__SHIFT 0x0000000f 3083*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL_MASK 0xffffffffL 3084*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK1_SEL__DCDEBUG_BUS_CLK1_SEL__SHIFT 0x00000000 3085*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL_MASK 0xffffffffL 3086*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK2_SEL__DCDEBUG_BUS_CLK2_SEL__SHIFT 0x00000000 3087*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL_MASK 0xffffffffL 3088*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK3_SEL__DCDEBUG_BUS_CLK3_SEL__SHIFT 0x00000000 3089*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL_MASK 0xffffffffL 3090*b843c749SSergey Zigachev #define DCDEBUG_BUS_CLK4_SEL__DCDEBUG_BUS_CLK4_SEL__SHIFT 0x00000000 3091*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL_MASK 0x0000001fL 3092*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_BLOCK_SEL__SHIFT 0x00000000 3093*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN_MASK 0x00000020L 3094*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_EN__SHIFT 0x00000005 3095*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL_MASK 0x00000040L 3096*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_PIN_SEL__SHIFT 0x00000006 3097*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL_MASK 0x00300000L 3098*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_SEL__SHIFT 0x00000014 3099*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN_MASK 0x00000080L 3100*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_EN__SHIFT 0x00000007 3101*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA_MASK 0x000fff00L 3102*b843c749SSergey Zigachev #define DCDEBUG_OUT_CNTL__DCDEBUG_OUT_TEST_DATA__SHIFT 0x00000008 3103*b843c749SSergey Zigachev #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA_MASK 0xffffffffL 3104*b843c749SSergey Zigachev #define DCDEBUG_OUT_DATA__DCDEBUG_OUT_DATA__SHIFT 0x00000000 3105*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN_MASK 0x00001000L 3106*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_EN__SHIFT 0x0000000c 3107*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL_MASK 0x0000000fL 3108*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_PIN_SEL__SHIFT 0x00000000 3109*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL_MASK 0x000001f0L 3110*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE1_REGBIT_SEL__SHIFT 0x00000004 3111*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN_MASK 0x10000000L 3112*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_EN__SHIFT 0x0000001c 3113*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL_MASK 0x000f0000L 3114*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_PIN_SEL__SHIFT 0x00000010 3115*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL_MASK 0x01f00000L 3116*b843c749SSergey Zigachev #define DCDEBUG_OUT_PIN_OVERRIDE__DCDEBUG_OUT_OVERRIDE2_REGBIT_SEL__SHIFT 0x00000014 3117*b843c749SSergey Zigachev #define DC_DMCU_SCRATCH__DMCU_SCRATCH_MASK 0xffffffffL 3118*b843c749SSergey Zigachev #define DC_DMCU_SCRATCH__DMCU_SCRATCH__SHIFT 0x00000000 3119*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN_MASK 0x00200000L 3120*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__DVO_ALTER_MAPPING_EN__SHIFT 0x00000015 3121*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN_MASK 0x00100000L 3122*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__VIP_ALTER_MAPPING_EN__SHIFT 0x00000014 3123*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__VIP_MUX_EN_MASK 0x00080000L 3124*b843c749SSergey Zigachev #define DC_DVODATA_CONFIG__VIP_MUX_EN__SHIFT 0x00000013 3125*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET_MASK 0x00000010L 3126*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__CRTC0_SOFT_RESET__SHIFT 0x00000004 3127*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3128*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__DCP0_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3129*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET_MASK 0x00000002L 3130*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__DCP0_REQ_SOFT_RESET__SHIFT 0x00000001 3131*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET_MASK 0x00000004L 3132*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__SCL0_ALU_SOFT_RESET__SHIFT 0x00000002 3133*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET_MASK 0x00000008L 3134*b843c749SSergey Zigachev #define DCFE0_SOFT_RESET__SCL0_SOFT_RESET__SHIFT 0x00000003 3135*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET_MASK 0x00000010L 3136*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__CRTC1_SOFT_RESET__SHIFT 0x00000004 3137*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3138*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__DCP1_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3139*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET_MASK 0x00000002L 3140*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__DCP1_REQ_SOFT_RESET__SHIFT 0x00000001 3141*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET_MASK 0x00000004L 3142*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__SCL1_ALU_SOFT_RESET__SHIFT 0x00000002 3143*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET_MASK 0x00000008L 3144*b843c749SSergey Zigachev #define DCFE1_SOFT_RESET__SCL1_SOFT_RESET__SHIFT 0x00000003 3145*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET_MASK 0x00000010L 3146*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__CRTC2_SOFT_RESET__SHIFT 0x00000004 3147*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3148*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__DCP2_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3149*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET_MASK 0x00000002L 3150*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__DCP2_REQ_SOFT_RESET__SHIFT 0x00000001 3151*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET_MASK 0x00000004L 3152*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__SCL2_ALU_SOFT_RESET__SHIFT 0x00000002 3153*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET_MASK 0x00000008L 3154*b843c749SSergey Zigachev #define DCFE2_SOFT_RESET__SCL2_SOFT_RESET__SHIFT 0x00000003 3155*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET_MASK 0x00000010L 3156*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__CRTC3_SOFT_RESET__SHIFT 0x00000004 3157*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3158*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__DCP3_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3159*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET_MASK 0x00000002L 3160*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__DCP3_REQ_SOFT_RESET__SHIFT 0x00000001 3161*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET_MASK 0x00000004L 3162*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__SCL3_ALU_SOFT_RESET__SHIFT 0x00000002 3163*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET_MASK 0x00000008L 3164*b843c749SSergey Zigachev #define DCFE3_SOFT_RESET__SCL3_SOFT_RESET__SHIFT 0x00000003 3165*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET_MASK 0x00000010L 3166*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__CRTC4_SOFT_RESET__SHIFT 0x00000004 3167*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3168*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__DCP4_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3169*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET_MASK 0x00000002L 3170*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__DCP4_REQ_SOFT_RESET__SHIFT 0x00000001 3171*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET_MASK 0x00000004L 3172*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__SCL4_ALU_SOFT_RESET__SHIFT 0x00000002 3173*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET_MASK 0x00000008L 3174*b843c749SSergey Zigachev #define DCFE4_SOFT_RESET__SCL4_SOFT_RESET__SHIFT 0x00000003 3175*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET_MASK 0x00000010L 3176*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__CRTC5_SOFT_RESET__SHIFT 0x00000004 3177*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET_MASK 0x00000001L 3178*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__DCP5_PIXPIPE_SOFT_RESET__SHIFT 0x00000000 3179*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET_MASK 0x00000002L 3180*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__DCP5_REQ_SOFT_RESET__SHIFT 0x00000001 3181*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET_MASK 0x00000004L 3182*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__SCL5_ALU_SOFT_RESET__SHIFT 0x00000002 3183*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET_MASK 0x00000008L 3184*b843c749SSergey Zigachev #define DCFE5_SOFT_RESET__SCL5_SOFT_RESET__SHIFT 0x00000003 3185*b843c749SSergey Zigachev #define DCFE_DBG_SEL__DCFE_DBG_SEL_MASK 0x0000000fL 3186*b843c749SSergey Zigachev #define DCFE_DBG_SEL__DCFE_DBG_SEL__SHIFT 0x00000000 3187*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS_MASK 0x00000001L 3188*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_LIGHT_SLEEP_DIS__SHIFT 0x00000000 3189*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE_MASK 0x00000300L 3190*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_CURSOR_MEM_PWR_STATE__SHIFT 0x00000008 3191*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS_MASK 0x00000004L 3192*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000002 3193*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE_MASK 0x00003000L 3194*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__DCP_LUT_MEM_PWR_STATE__SHIFT 0x0000000c 3195*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS_MASK 0x20000000L 3196*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB1_MEM_SHUTDOWN_DIS__SHIFT 0x0000001d 3197*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS_MASK 0x40000000L 3198*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB2_MEM_SHUTDOWN_DIS__SHIFT 0x0000001e 3199*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS_MASK 0x00000010L 3200*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 3201*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0_MASK 0x00030000L 3202*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_0__SHIFT 0x00000010 3203*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1_MASK 0x00c00000L 3204*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_1__SHIFT 0x00000016 3205*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2_MASK 0x03000000L 3206*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__LB_MEM_PWR_STATE_2__SHIFT 0x00000018 3207*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS_MASK 0x00000008L 3208*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_LIGHT_SLEEP_DIS__SHIFT 0x00000003 3209*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE_MASK 0x0000c000L 3210*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__OVLSCL_MEM_PWR_STATE__SHIFT 0x0000000e 3211*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS_MASK 0x10000000L 3212*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__PIPE_MEM_SHUTDOWN_DIS__SHIFT 0x0000001c 3213*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS_MASK 0x00000040L 3214*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_LIGHT_SLEEP_DIS__SHIFT 0x00000006 3215*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE_MASK 0x00300000L 3216*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__REGAMMA_LUT_MEM_PWR_STATE__SHIFT 0x00000014 3217*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS_MASK 0x00000020L 3218*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_LIGHT_SLEEP_DIS__SHIFT 0x00000005 3219*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE_MASK 0x000c0000L 3220*b843c749SSergey Zigachev #define DCFE_MEM_LIGHT_SLEEP_CNTL__SCL_MEM_PWR_STATE__SHIFT 0x00000012 3221*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_EN_MASK 0x00000001L 3222*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_EN__SHIFT 0x00000000 3223*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_SEL_MASK 0x00000f00L 3224*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_SEL__SHIFT 0x00000008 3225*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3226*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3227*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3228*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3229*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3230*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3231*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3232*b843c749SSergey Zigachev #define DC_GENERICA__GENERICA_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3233*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_EN_MASK 0x00000001L 3234*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_EN__SHIFT 0x00000000 3235*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_SEL_MASK 0x00000f00L 3236*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_SEL__SHIFT 0x00000008 3237*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL_MASK 0x07000000L 3238*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_DIV2_SEL__SHIFT 0x00000018 3239*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL_MASK 0x00070000L 3240*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_CLK_SEL__SHIFT 0x00000010 3241*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL_MASK 0x00700000L 3242*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_FBDIV_SSC_CLK_SEL__SHIFT 0x00000014 3243*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL_MASK 0x00007000L 3244*b843c749SSergey Zigachev #define DC_GENERICB__GENERICB_UNIPHY_REFDIV_CLK_SEL__SHIFT 0x0000000c 3245*b843c749SSergey Zigachev #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A_MASK 0x00000001L 3246*b843c749SSergey Zigachev #define DC_GPIO_DDC1_A__DC_GPIO_DDC1CLK_A__SHIFT 0x00000000 3247*b843c749SSergey Zigachev #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A_MASK 0x00000100L 3248*b843c749SSergey Zigachev #define DC_GPIO_DDC1_A__DC_GPIO_DDC1DATA_A__SHIFT 0x00000008 3249*b843c749SSergey Zigachev #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN_MASK 0x00000001L 3250*b843c749SSergey Zigachev #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1CLK_EN__SHIFT 0x00000000 3251*b843c749SSergey Zigachev #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN_MASK 0x00000100L 3252*b843c749SSergey Zigachev #define DC_GPIO_DDC1_EN__DC_GPIO_DDC1DATA_EN__SHIFT 0x00000008 3253*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN_MASK 0x00400000L 3254*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__ALLOW_HW_DDC1_PD_EN__SHIFT 0x00000016 3255*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__AUX1_POL_MASK 0x00100000L 3256*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__AUX1_POL__SHIFT 0x00000014 3257*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE_MASK 0x00010000L 3258*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__AUX_PAD1_MODE__SHIFT 0x00000010 3259*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK_MASK 0x00000001L 3260*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_MASK__SHIFT 0x00000000 3261*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN_MASK 0x00000010L 3262*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_PD_EN__SHIFT 0x00000004 3263*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV_MASK 0x00000040L 3264*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_RECV__SHIFT 0x00000006 3265*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR_MASK 0x0f000000L 3266*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1CLK_STR__SHIFT 0x00000018 3267*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK_MASK 0x00000100L 3268*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_MASK__SHIFT 0x00000008 3269*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN_MASK 0x00001000L 3270*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_PD_EN__SHIFT 0x0000000c 3271*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV_MASK 0x00004000L 3272*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_RECV__SHIFT 0x0000000e 3273*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR_MASK 0xf0000000L 3274*b843c749SSergey Zigachev #define DC_GPIO_DDC1_MASK__DC_GPIO_DDC1DATA_STR__SHIFT 0x0000001c 3275*b843c749SSergey Zigachev #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y_MASK 0x00000001L 3276*b843c749SSergey Zigachev #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1CLK_Y__SHIFT 0x00000000 3277*b843c749SSergey Zigachev #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y_MASK 0x00000100L 3278*b843c749SSergey Zigachev #define DC_GPIO_DDC1_Y__DC_GPIO_DDC1DATA_Y__SHIFT 0x00000008 3279*b843c749SSergey Zigachev #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A_MASK 0x00000001L 3280*b843c749SSergey Zigachev #define DC_GPIO_DDC2_A__DC_GPIO_DDC2CLK_A__SHIFT 0x00000000 3281*b843c749SSergey Zigachev #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A_MASK 0x00000100L 3282*b843c749SSergey Zigachev #define DC_GPIO_DDC2_A__DC_GPIO_DDC2DATA_A__SHIFT 0x00000008 3283*b843c749SSergey Zigachev #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN_MASK 0x00000001L 3284*b843c749SSergey Zigachev #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2CLK_EN__SHIFT 0x00000000 3285*b843c749SSergey Zigachev #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN_MASK 0x00000100L 3286*b843c749SSergey Zigachev #define DC_GPIO_DDC2_EN__DC_GPIO_DDC2DATA_EN__SHIFT 0x00000008 3287*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN_MASK 0x00400000L 3288*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__ALLOW_HW_DDC2_PD_EN__SHIFT 0x00000016 3289*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__AUX2_POL_MASK 0x00100000L 3290*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__AUX2_POL__SHIFT 0x00000014 3291*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE_MASK 0x00010000L 3292*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__AUX_PAD2_MODE__SHIFT 0x00000010 3293*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK_MASK 0x00000001L 3294*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_MASK__SHIFT 0x00000000 3295*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN_MASK 0x00000010L 3296*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_PD_EN__SHIFT 0x00000004 3297*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV_MASK 0x00000040L 3298*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_RECV__SHIFT 0x00000006 3299*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR_MASK 0x0f000000L 3300*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2CLK_STR__SHIFT 0x00000018 3301*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK_MASK 0x00000100L 3302*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_MASK__SHIFT 0x00000008 3303*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN_MASK 0x00001000L 3304*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_PD_EN__SHIFT 0x0000000c 3305*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV_MASK 0x00004000L 3306*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_RECV__SHIFT 0x0000000e 3307*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR_MASK 0xf0000000L 3308*b843c749SSergey Zigachev #define DC_GPIO_DDC2_MASK__DC_GPIO_DDC2DATA_STR__SHIFT 0x0000001c 3309*b843c749SSergey Zigachev #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y_MASK 0x00000001L 3310*b843c749SSergey Zigachev #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2CLK_Y__SHIFT 0x00000000 3311*b843c749SSergey Zigachev #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y_MASK 0x00000100L 3312*b843c749SSergey Zigachev #define DC_GPIO_DDC2_Y__DC_GPIO_DDC2DATA_Y__SHIFT 0x00000008 3313*b843c749SSergey Zigachev #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A_MASK 0x00000001L 3314*b843c749SSergey Zigachev #define DC_GPIO_DDC3_A__DC_GPIO_DDC3CLK_A__SHIFT 0x00000000 3315*b843c749SSergey Zigachev #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A_MASK 0x00000100L 3316*b843c749SSergey Zigachev #define DC_GPIO_DDC3_A__DC_GPIO_DDC3DATA_A__SHIFT 0x00000008 3317*b843c749SSergey Zigachev #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN_MASK 0x00000001L 3318*b843c749SSergey Zigachev #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3CLK_EN__SHIFT 0x00000000 3319*b843c749SSergey Zigachev #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN_MASK 0x00000100L 3320*b843c749SSergey Zigachev #define DC_GPIO_DDC3_EN__DC_GPIO_DDC3DATA_EN__SHIFT 0x00000008 3321*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN_MASK 0x00400000L 3322*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__ALLOW_HW_DDC3_PD_EN__SHIFT 0x00000016 3323*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__AUX3_POL_MASK 0x00100000L 3324*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__AUX3_POL__SHIFT 0x00000014 3325*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE_MASK 0x00010000L 3326*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__AUX_PAD3_MODE__SHIFT 0x00000010 3327*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK_MASK 0x00000001L 3328*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_MASK__SHIFT 0x00000000 3329*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN_MASK 0x00000010L 3330*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_PD_EN__SHIFT 0x00000004 3331*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV_MASK 0x00000040L 3332*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_RECV__SHIFT 0x00000006 3333*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR_MASK 0x0f000000L 3334*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3CLK_STR__SHIFT 0x00000018 3335*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK_MASK 0x00000100L 3336*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_MASK__SHIFT 0x00000008 3337*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN_MASK 0x00001000L 3338*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_PD_EN__SHIFT 0x0000000c 3339*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV_MASK 0x00004000L 3340*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_RECV__SHIFT 0x0000000e 3341*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR_MASK 0xf0000000L 3342*b843c749SSergey Zigachev #define DC_GPIO_DDC3_MASK__DC_GPIO_DDC3DATA_STR__SHIFT 0x0000001c 3343*b843c749SSergey Zigachev #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y_MASK 0x00000001L 3344*b843c749SSergey Zigachev #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3CLK_Y__SHIFT 0x00000000 3345*b843c749SSergey Zigachev #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y_MASK 0x00000100L 3346*b843c749SSergey Zigachev #define DC_GPIO_DDC3_Y__DC_GPIO_DDC3DATA_Y__SHIFT 0x00000008 3347*b843c749SSergey Zigachev #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A_MASK 0x00000001L 3348*b843c749SSergey Zigachev #define DC_GPIO_DDC4_A__DC_GPIO_DDC4CLK_A__SHIFT 0x00000000 3349*b843c749SSergey Zigachev #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A_MASK 0x00000100L 3350*b843c749SSergey Zigachev #define DC_GPIO_DDC4_A__DC_GPIO_DDC4DATA_A__SHIFT 0x00000008 3351*b843c749SSergey Zigachev #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN_MASK 0x00000001L 3352*b843c749SSergey Zigachev #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4CLK_EN__SHIFT 0x00000000 3353*b843c749SSergey Zigachev #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN_MASK 0x00000100L 3354*b843c749SSergey Zigachev #define DC_GPIO_DDC4_EN__DC_GPIO_DDC4DATA_EN__SHIFT 0x00000008 3355*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN_MASK 0x00400000L 3356*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__ALLOW_HW_DDC4_PD_EN__SHIFT 0x00000016 3357*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__AUX4_POL_MASK 0x00100000L 3358*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__AUX4_POL__SHIFT 0x00000014 3359*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE_MASK 0x00010000L 3360*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__AUX_PAD4_MODE__SHIFT 0x00000010 3361*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK_MASK 0x00000001L 3362*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_MASK__SHIFT 0x00000000 3363*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN_MASK 0x00000010L 3364*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_PD_EN__SHIFT 0x00000004 3365*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV_MASK 0x00000040L 3366*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_RECV__SHIFT 0x00000006 3367*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR_MASK 0x0f000000L 3368*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4CLK_STR__SHIFT 0x00000018 3369*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK_MASK 0x00000100L 3370*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_MASK__SHIFT 0x00000008 3371*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN_MASK 0x00001000L 3372*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_PD_EN__SHIFT 0x0000000c 3373*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV_MASK 0x00004000L 3374*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_RECV__SHIFT 0x0000000e 3375*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR_MASK 0xf0000000L 3376*b843c749SSergey Zigachev #define DC_GPIO_DDC4_MASK__DC_GPIO_DDC4DATA_STR__SHIFT 0x0000001c 3377*b843c749SSergey Zigachev #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y_MASK 0x00000001L 3378*b843c749SSergey Zigachev #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4CLK_Y__SHIFT 0x00000000 3379*b843c749SSergey Zigachev #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y_MASK 0x00000100L 3380*b843c749SSergey Zigachev #define DC_GPIO_DDC4_Y__DC_GPIO_DDC4DATA_Y__SHIFT 0x00000008 3381*b843c749SSergey Zigachev #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A_MASK 0x00000001L 3382*b843c749SSergey Zigachev #define DC_GPIO_DDC5_A__DC_GPIO_DDC5CLK_A__SHIFT 0x00000000 3383*b843c749SSergey Zigachev #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A_MASK 0x00000100L 3384*b843c749SSergey Zigachev #define DC_GPIO_DDC5_A__DC_GPIO_DDC5DATA_A__SHIFT 0x00000008 3385*b843c749SSergey Zigachev #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN_MASK 0x00000001L 3386*b843c749SSergey Zigachev #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5CLK_EN__SHIFT 0x00000000 3387*b843c749SSergey Zigachev #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN_MASK 0x00000100L 3388*b843c749SSergey Zigachev #define DC_GPIO_DDC5_EN__DC_GPIO_DDC5DATA_EN__SHIFT 0x00000008 3389*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN_MASK 0x00400000L 3390*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__ALLOW_HW_DDC5_PD_EN__SHIFT 0x00000016 3391*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__AUX5_POL_MASK 0x00100000L 3392*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__AUX5_POL__SHIFT 0x00000014 3393*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE_MASK 0x00010000L 3394*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__AUX_PAD5_MODE__SHIFT 0x00000010 3395*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK_MASK 0x00000001L 3396*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_MASK__SHIFT 0x00000000 3397*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN_MASK 0x00000010L 3398*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_PD_EN__SHIFT 0x00000004 3399*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV_MASK 0x00000040L 3400*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_RECV__SHIFT 0x00000006 3401*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR_MASK 0x0f000000L 3402*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5CLK_STR__SHIFT 0x00000018 3403*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK_MASK 0x00000100L 3404*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_MASK__SHIFT 0x00000008 3405*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN_MASK 0x00001000L 3406*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_PD_EN__SHIFT 0x0000000c 3407*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV_MASK 0x00004000L 3408*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_RECV__SHIFT 0x0000000e 3409*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR_MASK 0xf0000000L 3410*b843c749SSergey Zigachev #define DC_GPIO_DDC5_MASK__DC_GPIO_DDC5DATA_STR__SHIFT 0x0000001c 3411*b843c749SSergey Zigachev #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y_MASK 0x00000001L 3412*b843c749SSergey Zigachev #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5CLK_Y__SHIFT 0x00000000 3413*b843c749SSergey Zigachev #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y_MASK 0x00000100L 3414*b843c749SSergey Zigachev #define DC_GPIO_DDC5_Y__DC_GPIO_DDC5DATA_Y__SHIFT 0x00000008 3415*b843c749SSergey Zigachev #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A_MASK 0x00000001L 3416*b843c749SSergey Zigachev #define DC_GPIO_DDC6_A__DC_GPIO_DDC6CLK_A__SHIFT 0x00000000 3417*b843c749SSergey Zigachev #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A_MASK 0x00000100L 3418*b843c749SSergey Zigachev #define DC_GPIO_DDC6_A__DC_GPIO_DDC6DATA_A__SHIFT 0x00000008 3419*b843c749SSergey Zigachev #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN_MASK 0x00000001L 3420*b843c749SSergey Zigachev #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6CLK_EN__SHIFT 0x00000000 3421*b843c749SSergey Zigachev #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN_MASK 0x00000100L 3422*b843c749SSergey Zigachev #define DC_GPIO_DDC6_EN__DC_GPIO_DDC6DATA_EN__SHIFT 0x00000008 3423*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN_MASK 0x00400000L 3424*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__ALLOW_HW_DDC6_PD_EN__SHIFT 0x00000016 3425*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__AUX6_POL_MASK 0x00100000L 3426*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__AUX6_POL__SHIFT 0x00000014 3427*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE_MASK 0x00010000L 3428*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__AUX_PAD6_MODE__SHIFT 0x00000010 3429*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK_MASK 0x00000001L 3430*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_MASK__SHIFT 0x00000000 3431*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN_MASK 0x00000010L 3432*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_PD_EN__SHIFT 0x00000004 3433*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV_MASK 0x00000040L 3434*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_RECV__SHIFT 0x00000006 3435*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR_MASK 0x0f000000L 3436*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6CLK_STR__SHIFT 0x00000018 3437*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK_MASK 0x00000100L 3438*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_MASK__SHIFT 0x00000008 3439*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN_MASK 0x00001000L 3440*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_PD_EN__SHIFT 0x0000000c 3441*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV_MASK 0x00004000L 3442*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_RECV__SHIFT 0x0000000e 3443*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR_MASK 0xf0000000L 3444*b843c749SSergey Zigachev #define DC_GPIO_DDC6_MASK__DC_GPIO_DDC6DATA_STR__SHIFT 0x0000001c 3445*b843c749SSergey Zigachev #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y_MASK 0x00000001L 3446*b843c749SSergey Zigachev #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6CLK_Y__SHIFT 0x00000000 3447*b843c749SSergey Zigachev #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y_MASK 0x00000100L 3448*b843c749SSergey Zigachev #define DC_GPIO_DDC6_Y__DC_GPIO_DDC6DATA_Y__SHIFT 0x00000008 3449*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A_MASK 0x00000001L 3450*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGACLK_A__SHIFT 0x00000000 3451*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A_MASK 0x00000100L 3452*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_A__DC_GPIO_DDCVGADATA_A__SHIFT 0x00000008 3453*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN_MASK 0x00000001L 3454*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGACLK_EN__SHIFT 0x00000000 3455*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN_MASK 0x00000100L 3456*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_EN__DC_GPIO_DDCVGADATA_EN__SHIFT 0x00000008 3457*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN_MASK 0x00400000L 3458*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__ALLOW_HW_DDCVGA_PD_EN__SHIFT 0x00000016 3459*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE_MASK 0x00010000L 3460*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__AUX_PADVGA_MODE__SHIFT 0x00000010 3461*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL_MASK 0x00100000L 3462*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__AUXVGA_POL__SHIFT 0x00000014 3463*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK_MASK 0x00000001L 3464*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_MASK__SHIFT 0x00000000 3465*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV_MASK 0x00000040L 3466*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_RECV__SHIFT 0x00000006 3467*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR_MASK 0x0f000000L 3468*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGACLK_STR__SHIFT 0x00000018 3469*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK_MASK 0x00000100L 3470*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_MASK__SHIFT 0x00000008 3471*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN_MASK 0x00001000L 3472*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_PD_EN__SHIFT 0x0000000c 3473*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV_MASK 0x00004000L 3474*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_RECV__SHIFT 0x0000000e 3475*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR_MASK 0xf0000000L 3476*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_MASK__DC_GPIO_DDCVGADATA_STR__SHIFT 0x0000001c 3477*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y_MASK 0x00000001L 3478*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGACLK_Y__SHIFT 0x00000000 3479*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y_MASK 0x00000100L 3480*b843c749SSergey Zigachev #define DC_GPIO_DDCVGA_Y__DC_GPIO_DDCVGADATA_Y__SHIFT 0x00000008 3481*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_MASK 0x00010000L 3482*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL__SHIFT 0x00000010 3483*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG_MASK 0x00000300L 3484*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_MACRO_DEBUG__SHIFT 0x00000008 3485*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG_MASK 0x00000001L 3486*b843c749SSergey Zigachev #define DC_GPIO_DEBUG__DC_GPIO_VIP_DEBUG__SHIFT 0x00000000 3487*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A_MASK 0x10000000L 3488*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCLK_A__SHIFT 0x0000001c 3489*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A_MASK 0x07000000L 3490*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVOCNTL_A__SHIFT 0x00000018 3491*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A_MASK 0x00ffffffL 3492*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_DVODATA_A__SHIFT 0x00000000 3493*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A_MASK 0xc0000000L 3494*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_A__DC_GPIO_MVP_DVOCNTL_A__SHIFT 0x0000001e 3495*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN_MASK 0x10000000L 3496*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCLK_EN__SHIFT 0x0000001c 3497*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN_MASK 0x07000000L 3498*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVOCNTL_EN__SHIFT 0x00000018 3499*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN_MASK 0x00ffffffL 3500*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_DVODATA_EN__SHIFT 0x00000000 3501*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN_MASK 0xc0000000L 3502*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_EN__DC_GPIO_MVP_DVOCNTL_EN__SHIFT 0x0000001e 3503*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK_MASK 0x10000000L 3504*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCLK_MASK__SHIFT 0x0000001c 3505*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK_MASK 0x07000000L 3506*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVOCNTL_MASK__SHIFT 0x00000018 3507*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK_MASK 0x00ffffffL 3508*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_DVODATA_MASK__SHIFT 0x00000000 3509*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK_MASK 0xc0000000L 3510*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_MASK__DC_GPIO_MVP_DVOCNTL_MASK__SHIFT 0x0000001e 3511*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y_MASK 0x10000000L 3512*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCLK_Y__SHIFT 0x0000001c 3513*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y_MASK 0x07000000L 3514*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVOCNTL_Y__SHIFT 0x00000018 3515*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y_MASK 0x00ffffffL 3516*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_DVODATA_Y__SHIFT 0x00000000 3517*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y_MASK 0xc0000000L 3518*b843c749SSergey Zigachev #define DC_GPIO_DVODATA_Y__DC_GPIO_MVP_DVOCNTL_Y__SHIFT 0x0000001e 3519*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A_MASK 0x00000001L 3520*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICA_A__SHIFT 0x00000000 3521*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A_MASK 0x00000100L 3522*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICB_A__SHIFT 0x00000008 3523*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A_MASK 0x00010000L 3524*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICC_A__SHIFT 0x00000010 3525*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A_MASK 0x00100000L 3526*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICD_A__SHIFT 0x00000014 3527*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A_MASK 0x00200000L 3528*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICE_A__SHIFT 0x00000015 3529*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A_MASK 0x00400000L 3530*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICF_A__SHIFT 0x00000016 3531*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A_MASK 0x00800000L 3532*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_A__DC_GPIO_GENERICG_A__SHIFT 0x00000017 3533*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN_MASK 0x00000001L 3534*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICA_EN__SHIFT 0x00000000 3535*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN_MASK 0x00000100L 3536*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICB_EN__SHIFT 0x00000008 3537*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN_MASK 0x00010000L 3538*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICC_EN__SHIFT 0x00000010 3539*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN_MASK 0x00100000L 3540*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICD_EN__SHIFT 0x00000014 3541*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN_MASK 0x00200000L 3542*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICE_EN__SHIFT 0x00000015 3543*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN_MASK 0x00400000L 3544*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICF_EN__SHIFT 0x00000016 3545*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN_MASK 0x00800000L 3546*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_EN__DC_GPIO_GENERICG_EN__SHIFT 0x00000017 3547*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK_MASK 0x00000001L 3548*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_MASK__SHIFT 0x00000000 3549*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS_MASK 0x00000002L 3550*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_PD_DIS__SHIFT 0x00000001 3551*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV_MASK 0x00000004L 3552*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICA_RECV__SHIFT 0x00000002 3553*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK_MASK 0x00000010L 3554*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_MASK__SHIFT 0x00000004 3555*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS_MASK 0x00000020L 3556*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_PD_DIS__SHIFT 0x00000005 3557*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV_MASK 0x00000040L 3558*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICB_RECV__SHIFT 0x00000006 3559*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK_MASK 0x00000100L 3560*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_MASK__SHIFT 0x00000008 3561*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS_MASK 0x00000200L 3562*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_PD_DIS__SHIFT 0x00000009 3563*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV_MASK 0x00000400L 3564*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICC_RECV__SHIFT 0x0000000a 3565*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK_MASK 0x00001000L 3566*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_MASK__SHIFT 0x0000000c 3567*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS_MASK 0x00002000L 3568*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_PD_DIS__SHIFT 0x0000000d 3569*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV_MASK 0x00004000L 3570*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICD_RECV__SHIFT 0x0000000e 3571*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK_MASK 0x00010000L 3572*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_MASK__SHIFT 0x00000010 3573*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS_MASK 0x00020000L 3574*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_PD_DIS__SHIFT 0x00000011 3575*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV_MASK 0x00040000L 3576*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICE_RECV__SHIFT 0x00000012 3577*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK_MASK 0x00100000L 3578*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_MASK__SHIFT 0x00000014 3579*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS_MASK 0x00200000L 3580*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_PD_DIS__SHIFT 0x00000015 3581*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV_MASK 0x00400000L 3582*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICF_RECV__SHIFT 0x00000016 3583*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK_MASK 0x01000000L 3584*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_MASK__SHIFT 0x00000018 3585*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS_MASK 0x02000000L 3586*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_PD_DIS__SHIFT 0x00000019 3587*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV_MASK 0x04000000L 3588*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_MASK__DC_GPIO_GENERICG_RECV__SHIFT 0x0000001a 3589*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y_MASK 0x00000001L 3590*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICA_Y__SHIFT 0x00000000 3591*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y_MASK 0x00000100L 3592*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICB_Y__SHIFT 0x00000008 3593*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y_MASK 0x00010000L 3594*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICC_Y__SHIFT 0x00000010 3595*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y_MASK 0x00100000L 3596*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICD_Y__SHIFT 0x00000014 3597*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y_MASK 0x00200000L 3598*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICE_Y__SHIFT 0x00000015 3599*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y_MASK 0x00400000L 3600*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICF_Y__SHIFT 0x00000016 3601*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y_MASK 0x00800000L 3602*b843c749SSergey Zigachev #define DC_GPIO_GENERIC_Y__DC_GPIO_GENERICG_Y__SHIFT 0x00000017 3603*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A_MASK 0x00000001L 3604*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_CLK_A__SHIFT 0x00000000 3605*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A_MASK 0x00000100L 3606*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_GENLK_VSYNC_A__SHIFT 0x00000008 3607*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A_MASK 0x00010000L 3608*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_A_A__SHIFT 0x00000010 3609*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A_MASK 0x01000000L 3610*b843c749SSergey Zigachev #define DC_GPIO_GENLK_A__DC_GPIO_SWAPLOCK_B_A__SHIFT 0x00000018 3611*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN_MASK 0x00000001L 3612*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_CLK_EN__SHIFT 0x00000000 3613*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN_MASK 0x00000100L 3614*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_GENLK_VSYNC_EN__SHIFT 0x00000008 3615*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN_MASK 0x00010000L 3616*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_A_EN__SHIFT 0x00000010 3617*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN_MASK 0x01000000L 3618*b843c749SSergey Zigachev #define DC_GPIO_GENLK_EN__DC_GPIO_SWAPLOCK_B_EN__SHIFT 0x00000018 3619*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK_MASK 0x00000001L 3620*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_MASK__SHIFT 0x00000000 3621*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS_MASK 0x00000002L 3622*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PD_DIS__SHIFT 0x00000001 3623*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN_MASK 0x00000008L 3624*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_PU_EN__SHIFT 0x00000003 3625*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV_MASK 0x00000004L 3626*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_CLK_RECV__SHIFT 0x00000002 3627*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK_MASK 0x00000100L 3628*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_MASK__SHIFT 0x00000008 3629*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS_MASK 0x00000200L 3630*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PD_DIS__SHIFT 0x00000009 3631*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN_MASK 0x00000800L 3632*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_PU_EN__SHIFT 0x0000000b 3633*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV_MASK 0x00000400L 3634*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_GENLK_VSYNC_RECV__SHIFT 0x0000000a 3635*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK_MASK 0x00010000L 3636*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_MASK__SHIFT 0x00000010 3637*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS_MASK 0x00020000L 3638*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PD_DIS__SHIFT 0x00000011 3639*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN_MASK 0x00080000L 3640*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_PU_EN__SHIFT 0x00000013 3641*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV_MASK 0x00040000L 3642*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_A_RECV__SHIFT 0x00000012 3643*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK_MASK 0x01000000L 3644*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_MASK__SHIFT 0x00000018 3645*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS_MASK 0x02000000L 3646*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PD_DIS__SHIFT 0x00000019 3647*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN_MASK 0x08000000L 3648*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_PU_EN__SHIFT 0x0000001b 3649*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV_MASK 0x04000000L 3650*b843c749SSergey Zigachev #define DC_GPIO_GENLK_MASK__DC_GPIO_SWAPLOCK_B_RECV__SHIFT 0x0000001a 3651*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y_MASK 0x00000001L 3652*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_CLK_Y__SHIFT 0x00000000 3653*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y_MASK 0x00000100L 3654*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_GENLK_VSYNC_Y__SHIFT 0x00000008 3655*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y_MASK 0x00010000L 3656*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_A_Y__SHIFT 0x00000010 3657*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y_MASK 0x01000000L 3658*b843c749SSergey Zigachev #define DC_GPIO_GENLK_Y__DC_GPIO_SWAPLOCK_B_Y__SHIFT 0x00000018 3659*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A_MASK 0x00000001L 3660*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD1_A__SHIFT 0x00000000 3661*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A_MASK 0x00000100L 3662*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD2_A__SHIFT 0x00000008 3663*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A_MASK 0x00010000L 3664*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD3_A__SHIFT 0x00000010 3665*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A_MASK 0x01000000L 3666*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD4_A__SHIFT 0x00000018 3667*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A_MASK 0x04000000L 3668*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD5_A__SHIFT 0x0000001a 3669*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A_MASK 0x10000000L 3670*b843c749SSergey Zigachev #define DC_GPIO_HPD_A__DC_GPIO_HPD6_A__SHIFT 0x0000001c 3671*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN_MASK 0x00000001L 3672*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD1_EN__SHIFT 0x00000000 3673*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN_MASK 0x00000100L 3674*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD2_EN__SHIFT 0x00000008 3675*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN_MASK 0x00010000L 3676*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD3_EN__SHIFT 0x00000010 3677*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN_MASK 0x01000000L 3678*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD4_EN__SHIFT 0x00000018 3679*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN_MASK 0x04000000L 3680*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD5_EN__SHIFT 0x0000001a 3681*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN_MASK 0x10000000L 3682*b843c749SSergey Zigachev #define DC_GPIO_HPD_EN__DC_GPIO_HPD6_EN__SHIFT 0x0000001c 3683*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK_MASK 0x00000001L 3684*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_MASK__SHIFT 0x00000000 3685*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS_MASK 0x00000010L 3686*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_PD_DIS__SHIFT 0x00000004 3687*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV_MASK 0x00000040L 3688*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD1_RECV__SHIFT 0x00000006 3689*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK_MASK 0x00000100L 3690*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_MASK__SHIFT 0x00000008 3691*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS_MASK 0x00000200L 3692*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_PD_DIS__SHIFT 0x00000009 3693*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV_MASK 0x00000400L 3694*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD2_RECV__SHIFT 0x0000000a 3695*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK_MASK 0x00010000L 3696*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_MASK__SHIFT 0x00000010 3697*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS_MASK 0x00020000L 3698*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_PD_DIS__SHIFT 0x00000011 3699*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV_MASK 0x00040000L 3700*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD3_RECV__SHIFT 0x00000012 3701*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK_MASK 0x00100000L 3702*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_MASK__SHIFT 0x00000014 3703*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS_MASK 0x00200000L 3704*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_PD_DIS__SHIFT 0x00000015 3705*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV_MASK 0x00400000L 3706*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD4_RECV__SHIFT 0x00000016 3707*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK_MASK 0x01000000L 3708*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_MASK__SHIFT 0x00000018 3709*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS_MASK 0x02000000L 3710*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_PD_DIS__SHIFT 0x00000019 3711*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV_MASK 0x04000000L 3712*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD5_RECV__SHIFT 0x0000001a 3713*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK_MASK 0x10000000L 3714*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_MASK__SHIFT 0x0000001c 3715*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS_MASK 0x20000000L 3716*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_PD_DIS__SHIFT 0x0000001d 3717*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV_MASK 0x40000000L 3718*b843c749SSergey Zigachev #define DC_GPIO_HPD_MASK__DC_GPIO_HPD6_RECV__SHIFT 0x0000001e 3719*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y_MASK 0x00000001L 3720*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD1_Y__SHIFT 0x00000000 3721*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y_MASK 0x00000100L 3722*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD2_Y__SHIFT 0x00000008 3723*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y_MASK 0x00010000L 3724*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD3_Y__SHIFT 0x00000010 3725*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y_MASK 0x01000000L 3726*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD4_Y__SHIFT 0x00000018 3727*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y_MASK 0x04000000L 3728*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD5_Y__SHIFT 0x0000001a 3729*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y_MASK 0x10000000L 3730*b843c749SSergey Zigachev #define DC_GPIO_HPD_Y__DC_GPIO_HPD6_Y__SHIFT 0x0000001c 3731*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A_MASK 0x00000001L 3732*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_A__DC_GPIO_SCL_A__SHIFT 0x00000000 3733*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A_MASK 0x00000002L 3734*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_A__DC_GPIO_SDA_A__SHIFT 0x00000001 3735*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN_MASK 0x00000001L 3736*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_EN__DC_GPIO_SCL_EN__SHIFT 0x00000000 3737*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN_MASK 0x00000002L 3738*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_EN__DC_GPIO_SDA_EN__SHIFT 0x00000001 3739*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK_MASK 0x00000001L 3740*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_MASK__SHIFT 0x00000000 3741*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS_MASK 0x00000002L 3742*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_PD_DIS__SHIFT 0x00000001 3743*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV_MASK 0x00000004L 3744*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SCL_RECV__SHIFT 0x00000002 3745*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK_MASK 0x00000010L 3746*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_MASK__SHIFT 0x00000004 3747*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS_MASK 0x00000020L 3748*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_PD_DIS__SHIFT 0x00000005 3749*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV_MASK 0x00000040L 3750*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_MASK__DC_GPIO_SDA_RECV__SHIFT 0x00000006 3751*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN_MASK 0x0000000fL 3752*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SN__SHIFT 0x00000000 3753*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP_MASK 0x000000f0L 3754*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_STRENGTH__I2C_STRENGTH_SP__SHIFT 0x00000004 3755*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y_MASK 0x00000001L 3756*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_Y__DC_GPIO_SCL_Y__SHIFT 0x00000000 3757*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y_MASK 0x00000002L 3758*b843c749SSergey Zigachev #define DC_GPIO_I2CPAD_Y__DC_GPIO_SDA_Y__SHIFT 0x00000001 3759*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN_MASK 0x0000000fL 3760*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SN__SHIFT 0x00000000 3761*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP_MASK 0x000000f0L 3762*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__GENLK_STRENGTH_SP__SHIFT 0x00000004 3763*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN_MASK 0x0f000000L 3764*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SN__SHIFT 0x00000018 3765*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP_MASK 0xf0000000L 3766*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_1__SYNC_STRENGTH_SP__SHIFT 0x0000001c 3767*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN_MASK 0x000f0000L 3768*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SN__SHIFT 0x00000010 3769*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP_MASK 0x00f00000L 3770*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__PWRSEQ_STRENGTH_SP__SHIFT 0x00000014 3771*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN_MASK 0x0000000fL 3772*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SN__SHIFT 0x00000000 3773*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP_MASK 0x000000f0L 3774*b843c749SSergey Zigachev #define DC_GPIO_PAD_STRENGTH_2__STRENGTH_SP__SHIFT 0x00000004 3775*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A_MASK 0x00000001L 3776*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_BLON_A__SHIFT 0x00000000 3777*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A_MASK 0x00000100L 3778*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_DIGON_A__SHIFT 0x00000008 3779*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A_MASK 0x00010000L 3780*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_A__DC_GPIO_ENA_BL_A__SHIFT 0x00000010 3781*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN_MASK 0x00000001L 3782*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_BLON_EN__SHIFT 0x00000000 3783*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN_MASK 0x00000100L 3784*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_DIGON_EN__SHIFT 0x00000008 3785*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN_MASK 0x00010000L 3786*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_ENA_BL_EN__SHIFT 0x00000010 3787*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN_MASK 0x00000002L 3788*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_EN__DC_GPIO_VARY_BL_GENERICA_EN__SHIFT 0x00000001 3789*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK_MASK 0x00000001L 3790*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_MASK__SHIFT 0x00000000 3791*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS_MASK 0x00000010L 3792*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_PD_DIS__SHIFT 0x00000004 3793*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV_MASK 0x00000040L 3794*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_BLON_RECV__SHIFT 0x00000006 3795*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK_MASK 0x00000100L 3796*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_MASK__SHIFT 0x00000008 3797*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS_MASK 0x00001000L 3798*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_PD_DIS__SHIFT 0x0000000c 3799*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV_MASK 0x00004000L 3800*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_DIGON_RECV__SHIFT 0x0000000e 3801*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK_MASK 0x00010000L 3802*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_MASK__SHIFT 0x00000010 3803*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS_MASK 0x00100000L 3804*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_PD_DIS__SHIFT 0x00000014 3805*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV_MASK 0x00400000L 3806*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_MASK__DC_GPIO_ENA_BL_RECV__SHIFT 0x00000016 3807*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y_MASK 0x00000001L 3808*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_BLON_Y__SHIFT 0x00000000 3809*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y_MASK 0x00000100L 3810*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_DIGON_Y__SHIFT 0x00000008 3811*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y_MASK 0x00010000L 3812*b843c749SSergey Zigachev #define DC_GPIO_PWRSEQ_Y__DC_GPIO_ENA_BL_Y__SHIFT 0x00000010 3813*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A_MASK 0x00000001L 3814*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_A__DC_GPIO_HSYNCA_A__SHIFT 0x00000000 3815*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A_MASK 0x00000100L 3816*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_A__DC_GPIO_VSYNCA_A__SHIFT 0x00000008 3817*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN_MASK 0x00000001L 3818*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_EN__DC_GPIO_HSYNCA_EN__SHIFT 0x00000000 3819*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN_MASK 0x00000100L 3820*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_EN__DC_GPIO_VSYNCA_EN__SHIFT 0x00000008 3821*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK_MASK 0x07000000L 3822*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_CRTC_HSYNC_MASK__SHIFT 0x00000018 3823*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK_MASK 0x00000001L 3824*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_MASK__SHIFT 0x00000000 3825*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS_MASK 0x00000010L 3826*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_PD_DIS__SHIFT 0x00000004 3827*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV_MASK 0x00000040L 3828*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_HSYNCA_RECV__SHIFT 0x00000006 3829*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK_MASK 0x70000000L 3830*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_CRTC_VSYNC_MASK__SHIFT 0x0000001c 3831*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK_MASK 0x00000100L 3832*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_MASK__SHIFT 0x00000008 3833*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS_MASK 0x00001000L 3834*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_PD_DIS__SHIFT 0x0000000c 3835*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV_MASK 0x00004000L 3836*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_MASK__DC_GPIO_VSYNCA_RECV__SHIFT 0x0000000e 3837*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y_MASK 0x00000001L 3838*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_Y__DC_GPIO_HSYNCA_Y__SHIFT 0x00000000 3839*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y_MASK 0x00000100L 3840*b843c749SSergey Zigachev #define DC_GPIO_SYNCA_Y__DC_GPIO_VSYNCA_Y__SHIFT 0x00000008 3841*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT_MASK 0x0000003fL 3842*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_READ_SELECT__SHIFT 0x00000000 3843*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM_MASK 0x00000700L 3844*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D1_VSYNC_NOM__SHIFT 0x00000008 3845*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM_MASK 0x00003800L 3846*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D2_VSYNC_NOM__SHIFT 0x0000000b 3847*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM_MASK 0x0001c000L 3848*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D3_VSYNC_NOM__SHIFT 0x0000000e 3849*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM_MASK 0x000e0000L 3850*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D4_VSYNC_NOM__SHIFT 0x00000011 3851*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM_MASK 0x00700000L 3852*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D5_VSYNC_NOM__SHIFT 0x00000014 3853*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM_MASK 0x03800000L 3854*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ_CNTL__DC_GPU_TIMER_START_POSITION_D6_VSYNC_NOM__SHIFT 0x00000017 3855*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ_MASK 0xffffffffL 3856*b843c749SSergey Zigachev #define DC_GPU_TIMER_READ__DC_GPU_TIMER_READ__SHIFT 0x00000000 3857*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP_MASK 0x00000007L 3858*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D1_P_FLIP__SHIFT 0x00000000 3859*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP_MASK 0x00000070L 3860*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D2_P_FLIP__SHIFT 0x00000004 3861*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP_MASK 0x00000700L 3862*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D3_P_FLIP__SHIFT 0x00000008 3863*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP_MASK 0x00007000L 3864*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D4_P_FLIP__SHIFT 0x0000000c 3865*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP_MASK 0x00070000L 3866*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D5_P_FLIP__SHIFT 0x00000010 3867*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP_MASK 0x00700000L 3868*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_P_FLIP__DC_GPU_TIMER_START_POSITION_D6_P_FLIP__SHIFT 0x00000014 3869*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE_MASK 0x00000007L 3870*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D1_V_UPDATE__SHIFT 0x00000000 3871*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE_MASK 0x00000070L 3872*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D2_V_UPDATE__SHIFT 0x00000004 3873*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE_MASK 0x00000700L 3874*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D3_V_UPDATE__SHIFT 0x00000008 3875*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE_MASK 0x00007000L 3876*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D4_V_UPDATE__SHIFT 0x0000000c 3877*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE_MASK 0x00070000L 3878*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D5_V_UPDATE__SHIFT 0x00000010 3879*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE_MASK 0x00700000L 3880*b843c749SSergey Zigachev #define DC_GPU_TIMER_START_POSITION_V_UPDATE__DC_GPU_TIMER_START_POSITION_D6_V_UPDATE__SHIFT 0x00000014 3881*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER_MASK 0x00001fffL 3882*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT 0x00000000 3883*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_EN_MASK 0x10000000L 3884*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_EN__SHIFT 0x0000001c 3885*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER_MASK 0x03ff0000L 3886*b843c749SSergey Zigachev #define DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT 0x00000010 3887*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3888*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3889*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN_MASK 0x01000000L 3890*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3891*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3892*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3893*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3894*b843c749SSergey Zigachev #define DC_HPD1_FAST_TRAIN_CNTL__DC_HPD1_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3895*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK 0x00000001L 3896*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK__SHIFT 0x00000000 3897*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK 0x00010000L 3898*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN__SHIFT 0x00000010 3899*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK 0x00000100L 3900*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY__SHIFT 0x00000008 3901*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK 0x00100000L 3902*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK__SHIFT 0x00000014 3903*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK 0x01000000L 3904*b843c749SSergey Zigachev #define DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN__SHIFT 0x00000018 3905*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS_MASK 0x00000001L 3906*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_INT_STATUS__SHIFT 0x00000000 3907*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS_MASK 0x00000100L 3908*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_RX_INT_STATUS__SHIFT 0x00000008 3909*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED_MASK 0x00000010L 3910*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_DELAYED__SHIFT 0x00000004 3911*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK 0x00000002L 3912*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_SENSE__SHIFT 0x00000001 3913*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3914*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3915*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3916*b843c749SSergey Zigachev #define DC_HPD1_INT_STATUS__DC_HPD1_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3917*b843c749SSergey Zigachev #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY_MASK 0x000000ffL 3918*b843c749SSergey Zigachev #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_CONNECT_INT_DELAY__SHIFT 0x00000000 3919*b843c749SSergey Zigachev #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3920*b843c749SSergey Zigachev #define DC_HPD1_TOGGLE_FILT_CNTL__DC_HPD1_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3921*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER_MASK 0x00001fffL 3922*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_CONNECTION_TIMER__SHIFT 0x00000000 3923*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_EN_MASK 0x10000000L 3924*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_EN__SHIFT 0x0000001c 3925*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER_MASK 0x03ff0000L 3926*b843c749SSergey Zigachev #define DC_HPD2_CONTROL__DC_HPD2_RX_INT_TIMER__SHIFT 0x00000010 3927*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3928*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3929*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN_MASK 0x01000000L 3930*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3931*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3932*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3933*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3934*b843c749SSergey Zigachev #define DC_HPD2_FAST_TRAIN_CNTL__DC_HPD2_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3935*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK_MASK 0x00000001L 3936*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_ACK__SHIFT 0x00000000 3937*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN_MASK 0x00010000L 3938*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_EN__SHIFT 0x00000010 3939*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK 0x00000100L 3940*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY__SHIFT 0x00000008 3941*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK_MASK 0x00100000L 3942*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_ACK__SHIFT 0x00000014 3943*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN_MASK 0x01000000L 3944*b843c749SSergey Zigachev #define DC_HPD2_INT_CONTROL__DC_HPD2_RX_INT_EN__SHIFT 0x00000018 3945*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS_MASK 0x00000001L 3946*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_INT_STATUS__SHIFT 0x00000000 3947*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS_MASK 0x00000100L 3948*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_RX_INT_STATUS__SHIFT 0x00000008 3949*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED_MASK 0x00000010L 3950*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_DELAYED__SHIFT 0x00000004 3951*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK 0x00000002L 3952*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_SENSE__SHIFT 0x00000001 3953*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3954*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3955*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3956*b843c749SSergey Zigachev #define DC_HPD2_INT_STATUS__DC_HPD2_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3957*b843c749SSergey Zigachev #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY_MASK 0x000000ffL 3958*b843c749SSergey Zigachev #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_CONNECT_INT_DELAY__SHIFT 0x00000000 3959*b843c749SSergey Zigachev #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 3960*b843c749SSergey Zigachev #define DC_HPD2_TOGGLE_FILT_CNTL__DC_HPD2_DISCONNECT_INT_DELAY__SHIFT 0x00000014 3961*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER_MASK 0x00001fffL 3962*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_CONNECTION_TIMER__SHIFT 0x00000000 3963*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_EN_MASK 0x10000000L 3964*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_EN__SHIFT 0x0000001c 3965*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER_MASK 0x03ff0000L 3966*b843c749SSergey Zigachev #define DC_HPD3_CONTROL__DC_HPD3_RX_INT_TIMER__SHIFT 0x00000010 3967*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 3968*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 3969*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN_MASK 0x01000000L 3970*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_AUX_TX_EN__SHIFT 0x00000018 3971*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 3972*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 3973*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 3974*b843c749SSergey Zigachev #define DC_HPD3_FAST_TRAIN_CNTL__DC_HPD3_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 3975*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK_MASK 0x00000001L 3976*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_ACK__SHIFT 0x00000000 3977*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN_MASK 0x00010000L 3978*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_EN__SHIFT 0x00000010 3979*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK 0x00000100L 3980*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY__SHIFT 0x00000008 3981*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK_MASK 0x00100000L 3982*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_ACK__SHIFT 0x00000014 3983*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN_MASK 0x01000000L 3984*b843c749SSergey Zigachev #define DC_HPD3_INT_CONTROL__DC_HPD3_RX_INT_EN__SHIFT 0x00000018 3985*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS_MASK 0x00000001L 3986*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_INT_STATUS__SHIFT 0x00000000 3987*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS_MASK 0x00000100L 3988*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_RX_INT_STATUS__SHIFT 0x00000008 3989*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED_MASK 0x00000010L 3990*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_DELAYED__SHIFT 0x00000004 3991*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK 0x00000002L 3992*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_SENSE__SHIFT 0x00000001 3993*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 3994*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 3995*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 3996*b843c749SSergey Zigachev #define DC_HPD3_INT_STATUS__DC_HPD3_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 3997*b843c749SSergey Zigachev #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY_MASK 0x000000ffL 3998*b843c749SSergey Zigachev #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_CONNECT_INT_DELAY__SHIFT 0x00000000 3999*b843c749SSergey Zigachev #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4000*b843c749SSergey Zigachev #define DC_HPD3_TOGGLE_FILT_CNTL__DC_HPD3_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4001*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER_MASK 0x00001fffL 4002*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_CONNECTION_TIMER__SHIFT 0x00000000 4003*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_EN_MASK 0x10000000L 4004*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_EN__SHIFT 0x0000001c 4005*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER_MASK 0x03ff0000L 4006*b843c749SSergey Zigachev #define DC_HPD4_CONTROL__DC_HPD4_RX_INT_TIMER__SHIFT 0x00000010 4007*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4008*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4009*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN_MASK 0x01000000L 4010*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4011*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4012*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4013*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4014*b843c749SSergey Zigachev #define DC_HPD4_FAST_TRAIN_CNTL__DC_HPD4_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4015*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK_MASK 0x00000001L 4016*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_ACK__SHIFT 0x00000000 4017*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN_MASK 0x00010000L 4018*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_EN__SHIFT 0x00000010 4019*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK 0x00000100L 4020*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY__SHIFT 0x00000008 4021*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK_MASK 0x00100000L 4022*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_ACK__SHIFT 0x00000014 4023*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN_MASK 0x01000000L 4024*b843c749SSergey Zigachev #define DC_HPD4_INT_CONTROL__DC_HPD4_RX_INT_EN__SHIFT 0x00000018 4025*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS_MASK 0x00000001L 4026*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_INT_STATUS__SHIFT 0x00000000 4027*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS_MASK 0x00000100L 4028*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_RX_INT_STATUS__SHIFT 0x00000008 4029*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED_MASK 0x00000010L 4030*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_DELAYED__SHIFT 0x00000004 4031*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK 0x00000002L 4032*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_SENSE__SHIFT 0x00000001 4033*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4034*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4035*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4036*b843c749SSergey Zigachev #define DC_HPD4_INT_STATUS__DC_HPD4_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4037*b843c749SSergey Zigachev #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY_MASK 0x000000ffL 4038*b843c749SSergey Zigachev #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_CONNECT_INT_DELAY__SHIFT 0x00000000 4039*b843c749SSergey Zigachev #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4040*b843c749SSergey Zigachev #define DC_HPD4_TOGGLE_FILT_CNTL__DC_HPD4_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4041*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER_MASK 0x00001fffL 4042*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_CONNECTION_TIMER__SHIFT 0x00000000 4043*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_EN_MASK 0x10000000L 4044*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_EN__SHIFT 0x0000001c 4045*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER_MASK 0x03ff0000L 4046*b843c749SSergey Zigachev #define DC_HPD5_CONTROL__DC_HPD5_RX_INT_TIMER__SHIFT 0x00000010 4047*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4048*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4049*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN_MASK 0x01000000L 4050*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4051*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4052*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4053*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4054*b843c749SSergey Zigachev #define DC_HPD5_FAST_TRAIN_CNTL__DC_HPD5_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4055*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK_MASK 0x00000001L 4056*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_ACK__SHIFT 0x00000000 4057*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN_MASK 0x00010000L 4058*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_EN__SHIFT 0x00000010 4059*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK 0x00000100L 4060*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY__SHIFT 0x00000008 4061*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK_MASK 0x00100000L 4062*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_ACK__SHIFT 0x00000014 4063*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN_MASK 0x01000000L 4064*b843c749SSergey Zigachev #define DC_HPD5_INT_CONTROL__DC_HPD5_RX_INT_EN__SHIFT 0x00000018 4065*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS_MASK 0x00000001L 4066*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_INT_STATUS__SHIFT 0x00000000 4067*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS_MASK 0x00000100L 4068*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_RX_INT_STATUS__SHIFT 0x00000008 4069*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED_MASK 0x00000010L 4070*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_DELAYED__SHIFT 0x00000004 4071*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK 0x00000002L 4072*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_SENSE__SHIFT 0x00000001 4073*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4074*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4075*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4076*b843c749SSergey Zigachev #define DC_HPD5_INT_STATUS__DC_HPD5_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4077*b843c749SSergey Zigachev #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY_MASK 0x000000ffL 4078*b843c749SSergey Zigachev #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_CONNECT_INT_DELAY__SHIFT 0x00000000 4079*b843c749SSergey Zigachev #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4080*b843c749SSergey Zigachev #define DC_HPD5_TOGGLE_FILT_CNTL__DC_HPD5_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4081*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER_MASK 0x00001fffL 4082*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_CONNECTION_TIMER__SHIFT 0x00000000 4083*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_EN_MASK 0x10000000L 4084*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_EN__SHIFT 0x0000001c 4085*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER_MASK 0x03ff0000L 4086*b843c749SSergey Zigachev #define DC_HPD6_CONTROL__DC_HPD6_RX_INT_TIMER__SHIFT 0x00000010 4087*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY_MASK 0x000000ffL 4088*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_DELAY__SHIFT 0x00000000 4089*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN_MASK 0x01000000L 4090*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_AUX_TX_EN__SHIFT 0x00000018 4091*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY_MASK 0x000ff000L 4092*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_DELAY__SHIFT 0x0000000c 4093*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN_MASK 0x10000000L 4094*b843c749SSergey Zigachev #define DC_HPD6_FAST_TRAIN_CNTL__DC_HPD6_CONNECT_FAST_TRAIN_EN__SHIFT 0x0000001c 4095*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK_MASK 0x00000001L 4096*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_ACK__SHIFT 0x00000000 4097*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN_MASK 0x00010000L 4098*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_EN__SHIFT 0x00000010 4099*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK 0x00000100L 4100*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY__SHIFT 0x00000008 4101*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK_MASK 0x00100000L 4102*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_ACK__SHIFT 0x00000014 4103*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN_MASK 0x01000000L 4104*b843c749SSergey Zigachev #define DC_HPD6_INT_CONTROL__DC_HPD6_RX_INT_EN__SHIFT 0x00000018 4105*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS_MASK 0x00000001L 4106*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_INT_STATUS__SHIFT 0x00000000 4107*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS_MASK 0x00000100L 4108*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_RX_INT_STATUS__SHIFT 0x00000008 4109*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED_MASK 0x00000010L 4110*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_DELAYED__SHIFT 0x00000004 4111*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK 0x00000002L 4112*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_SENSE__SHIFT 0x00000001 4113*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL_MASK 0x000ff000L 4114*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_CON_TIMER_VAL__SHIFT 0x0000000c 4115*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL_MASK 0xff000000L 4116*b843c749SSergey Zigachev #define DC_HPD6_INT_STATUS__DC_HPD6_TOGGLE_FILT_DISCON_TIMER_VAL__SHIFT 0x00000018 4117*b843c749SSergey Zigachev #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY_MASK 0x000000ffL 4118*b843c749SSergey Zigachev #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_CONNECT_INT_DELAY__SHIFT 0x00000000 4119*b843c749SSergey Zigachev #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY_MASK 0x0ff00000L 4120*b843c749SSergey Zigachev #define DC_HPD6_TOGGLE_FILT_CNTL__DC_HPD6_DISCONNECT_INT_DELAY__SHIFT 0x00000014 4121*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER_MASK 0x00000100L 4122*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_ABORT_HW_XFER__SHIFT 0x00000008 4123*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER_MASK 0x00001000L 4124*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_ABORT_SW_XFER__SHIFT 0x0000000c 4125*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG_MASK 0x02000000L 4126*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_DMCU_DONE_USING_I2C_REG__SHIFT 0x00000019 4127*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ_MASK 0x01000000L 4128*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_DMCU_USE_I2C_REG_REQ__SHIFT 0x00000018 4129*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO_MASK 0x00000010L 4130*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_NO_QUEUED_SW_GO__SHIFT 0x00000004 4131*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS_MASK 0x0000000cL 4132*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_REG_RW_CNTL_STATUS__SHIFT 0x00000002 4133*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG_MASK 0x00200000L 4134*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_DONE_USING_I2C_REG__SHIFT 0x00000015 4135*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_MASK 0x00000003L 4136*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY__SHIFT 0x00000000 4137*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ_MASK 0x00100000L 4138*b843c749SSergey Zigachev #define DC_I2C_ARBITRATION__DC_I2C_SW_USE_I2C_REG_REQ__SHIFT 0x00000014 4139*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL_MASK 0x80000000L 4140*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 4141*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT_MASK 0x00000700L 4142*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_DDC_SELECT__SHIFT 0x00000008 4143*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_GO_MASK 0x00000001L 4144*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_GO__SHIFT 0x00000000 4145*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SEND_RESET_MASK 0x00000004L 4146*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SEND_RESET__SHIFT 0x00000002 4147*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET_MASK 0x00000002L 4148*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SOFT_RESET__SHIFT 0x00000001 4149*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET_MASK 0x00000008L 4150*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_SW_STATUS_RESET__SHIFT 0x00000003 4151*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT_MASK 0x00300000L 4152*b843c749SSergey Zigachev #define DC_I2C_CONTROL__DC_I2C_TRANSACTION_COUNT__SHIFT 0x00000014 4153*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_DATA_MASK 0x0000ff00L 4154*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_DATA_RW_MASK 0x00000001L 4155*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_DATA_RW__SHIFT 0x00000000 4156*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_DATA__SHIFT 0x00000008 4157*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_INDEX_MASK 0x00ff0000L 4158*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_INDEX__SHIFT 0x00000010 4159*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_INDEX_WRITE_MASK 0x80000000L 4160*b843c749SSergey Zigachev #define DC_I2C_DATA__DC_I2C_INDEX_WRITE__SHIFT 0x0000001f 4161*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4162*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4163*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE_MASK 0x70000000L 4164*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATE__SHIFT 0x0000001c 4165*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS_MASK 0x00100000L 4166*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_EDID_DETECT_STATUS__SHIFT 0x00000014 4167*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE_MASK 0x00000008L 4168*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_DONE__SHIFT 0x00000003 4169*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ_MASK 0x00010000L 4170*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_REQ__SHIFT 0x00000010 4171*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS_MASK 0x00000003L 4172*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_STATUS__SHIFT 0x00000000 4173*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG_MASK 0x00020000L 4174*b843c749SSergey Zigachev #define DC_I2C_DDC1_HW_STATUS__DC_I2C_DDC1_HW_URG__SHIFT 0x00000011 4175*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN_MASK 0x00000080L 4176*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_CLK_DRIVE_EN__SHIFT 0x00000007 4177*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN_MASK 0x00000001L 4178*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_EN__SHIFT 0x00000000 4179*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL_MASK 0x00000002L 4180*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_DATA_DRIVE_SEL__SHIFT 0x00000001 4181*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE_MASK 0x00000010L 4182*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_ENABLE__SHIFT 0x00000004 4183*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE_MASK 0x00000020L 4184*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_EDID_DETECT_MODE__SHIFT 0x00000005 4185*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE_MASK 0x00000040L 4186*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_ENABLE__SHIFT 0x00000006 4187*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4188*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_BYTE_DELAY__SHIFT 0x00000008 4189*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4190*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4191*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT_MASK 0xff000000L 4192*b843c749SSergey Zigachev #define DC_I2C_DDC1_SETUP__DC_I2C_DDC1_TIME_LIMIT__SHIFT 0x00000018 4193*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4194*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4195*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE_MASK 0xffff0000L 4196*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_PRESCALE__SHIFT 0x00000010 4197*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD_MASK 0x00000003L 4198*b843c749SSergey Zigachev #define DC_I2C_DDC1_SPEED__DC_I2C_DDC1_THRESHOLD__SHIFT 0x00000000 4199*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4200*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4201*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE_MASK 0x70000000L 4202*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATE__SHIFT 0x0000001c 4203*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS_MASK 0x00100000L 4204*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_EDID_DETECT_STATUS__SHIFT 0x00000014 4205*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE_MASK 0x00000008L 4206*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_DONE__SHIFT 0x00000003 4207*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ_MASK 0x00010000L 4208*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_REQ__SHIFT 0x00000010 4209*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS_MASK 0x00000003L 4210*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_STATUS__SHIFT 0x00000000 4211*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG_MASK 0x00020000L 4212*b843c749SSergey Zigachev #define DC_I2C_DDC2_HW_STATUS__DC_I2C_DDC2_HW_URG__SHIFT 0x00000011 4213*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN_MASK 0x00000080L 4214*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_CLK_DRIVE_EN__SHIFT 0x00000007 4215*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN_MASK 0x00000001L 4216*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_EN__SHIFT 0x00000000 4217*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL_MASK 0x00000002L 4218*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_DATA_DRIVE_SEL__SHIFT 0x00000001 4219*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE_MASK 0x00000010L 4220*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_ENABLE__SHIFT 0x00000004 4221*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE_MASK 0x00000020L 4222*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_EDID_DETECT_MODE__SHIFT 0x00000005 4223*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE_MASK 0x00000040L 4224*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_ENABLE__SHIFT 0x00000006 4225*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4226*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_BYTE_DELAY__SHIFT 0x00000008 4227*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4228*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4229*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT_MASK 0xff000000L 4230*b843c749SSergey Zigachev #define DC_I2C_DDC2_SETUP__DC_I2C_DDC2_TIME_LIMIT__SHIFT 0x00000018 4231*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4232*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4233*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE_MASK 0xffff0000L 4234*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_PRESCALE__SHIFT 0x00000010 4235*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD_MASK 0x00000003L 4236*b843c749SSergey Zigachev #define DC_I2C_DDC2_SPEED__DC_I2C_DDC2_THRESHOLD__SHIFT 0x00000000 4237*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4238*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4239*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE_MASK 0x70000000L 4240*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATE__SHIFT 0x0000001c 4241*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS_MASK 0x00100000L 4242*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_EDID_DETECT_STATUS__SHIFT 0x00000014 4243*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE_MASK 0x00000008L 4244*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_DONE__SHIFT 0x00000003 4245*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ_MASK 0x00010000L 4246*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_REQ__SHIFT 0x00000010 4247*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS_MASK 0x00000003L 4248*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_STATUS__SHIFT 0x00000000 4249*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG_MASK 0x00020000L 4250*b843c749SSergey Zigachev #define DC_I2C_DDC3_HW_STATUS__DC_I2C_DDC3_HW_URG__SHIFT 0x00000011 4251*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN_MASK 0x00000080L 4252*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_CLK_DRIVE_EN__SHIFT 0x00000007 4253*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN_MASK 0x00000001L 4254*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_EN__SHIFT 0x00000000 4255*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL_MASK 0x00000002L 4256*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_DATA_DRIVE_SEL__SHIFT 0x00000001 4257*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE_MASK 0x00000010L 4258*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_ENABLE__SHIFT 0x00000004 4259*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE_MASK 0x00000020L 4260*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_EDID_DETECT_MODE__SHIFT 0x00000005 4261*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE_MASK 0x00000040L 4262*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_ENABLE__SHIFT 0x00000006 4263*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4264*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_BYTE_DELAY__SHIFT 0x00000008 4265*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4266*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4267*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT_MASK 0xff000000L 4268*b843c749SSergey Zigachev #define DC_I2C_DDC3_SETUP__DC_I2C_DDC3_TIME_LIMIT__SHIFT 0x00000018 4269*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4270*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4271*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE_MASK 0xffff0000L 4272*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_PRESCALE__SHIFT 0x00000010 4273*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD_MASK 0x00000003L 4274*b843c749SSergey Zigachev #define DC_I2C_DDC3_SPEED__DC_I2C_DDC3_THRESHOLD__SHIFT 0x00000000 4275*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4276*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4277*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE_MASK 0x70000000L 4278*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATE__SHIFT 0x0000001c 4279*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS_MASK 0x00100000L 4280*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_EDID_DETECT_STATUS__SHIFT 0x00000014 4281*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE_MASK 0x00000008L 4282*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_DONE__SHIFT 0x00000003 4283*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ_MASK 0x00010000L 4284*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_REQ__SHIFT 0x00000010 4285*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS_MASK 0x00000003L 4286*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_STATUS__SHIFT 0x00000000 4287*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG_MASK 0x00020000L 4288*b843c749SSergey Zigachev #define DC_I2C_DDC4_HW_STATUS__DC_I2C_DDC4_HW_URG__SHIFT 0x00000011 4289*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN_MASK 0x00000080L 4290*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_CLK_DRIVE_EN__SHIFT 0x00000007 4291*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN_MASK 0x00000001L 4292*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_EN__SHIFT 0x00000000 4293*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL_MASK 0x00000002L 4294*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_DATA_DRIVE_SEL__SHIFT 0x00000001 4295*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE_MASK 0x00000010L 4296*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_ENABLE__SHIFT 0x00000004 4297*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE_MASK 0x00000020L 4298*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_EDID_DETECT_MODE__SHIFT 0x00000005 4299*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE_MASK 0x00000040L 4300*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_ENABLE__SHIFT 0x00000006 4301*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4302*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_BYTE_DELAY__SHIFT 0x00000008 4303*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4304*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4305*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT_MASK 0xff000000L 4306*b843c749SSergey Zigachev #define DC_I2C_DDC4_SETUP__DC_I2C_DDC4_TIME_LIMIT__SHIFT 0x00000018 4307*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4308*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4309*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE_MASK 0xffff0000L 4310*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_PRESCALE__SHIFT 0x00000010 4311*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD_MASK 0x00000003L 4312*b843c749SSergey Zigachev #define DC_I2C_DDC4_SPEED__DC_I2C_DDC4_THRESHOLD__SHIFT 0x00000000 4313*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4314*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4315*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE_MASK 0x70000000L 4316*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATE__SHIFT 0x0000001c 4317*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS_MASK 0x00100000L 4318*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_EDID_DETECT_STATUS__SHIFT 0x00000014 4319*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE_MASK 0x00000008L 4320*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_DONE__SHIFT 0x00000003 4321*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ_MASK 0x00010000L 4322*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_REQ__SHIFT 0x00000010 4323*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS_MASK 0x00000003L 4324*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_STATUS__SHIFT 0x00000000 4325*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG_MASK 0x00020000L 4326*b843c749SSergey Zigachev #define DC_I2C_DDC5_HW_STATUS__DC_I2C_DDC5_HW_URG__SHIFT 0x00000011 4327*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN_MASK 0x00000080L 4328*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_CLK_DRIVE_EN__SHIFT 0x00000007 4329*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN_MASK 0x00000001L 4330*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_EN__SHIFT 0x00000000 4331*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL_MASK 0x00000002L 4332*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_DATA_DRIVE_SEL__SHIFT 0x00000001 4333*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE_MASK 0x00000010L 4334*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_ENABLE__SHIFT 0x00000004 4335*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE_MASK 0x00000020L 4336*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_EDID_DETECT_MODE__SHIFT 0x00000005 4337*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE_MASK 0x00000040L 4338*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_ENABLE__SHIFT 0x00000006 4339*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4340*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_BYTE_DELAY__SHIFT 0x00000008 4341*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4342*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4343*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT_MASK 0xff000000L 4344*b843c749SSergey Zigachev #define DC_I2C_DDC5_SETUP__DC_I2C_DDC5_TIME_LIMIT__SHIFT 0x00000018 4345*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4346*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4347*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE_MASK 0xffff0000L 4348*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_PRESCALE__SHIFT 0x00000010 4349*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD_MASK 0x00000003L 4350*b843c749SSergey Zigachev #define DC_I2C_DDC5_SPEED__DC_I2C_DDC5_THRESHOLD__SHIFT 0x00000000 4351*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4352*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4353*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE_MASK 0x70000000L 4354*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATE__SHIFT 0x0000001c 4355*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS_MASK 0x00100000L 4356*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_EDID_DETECT_STATUS__SHIFT 0x00000014 4357*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE_MASK 0x00000008L 4358*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_DONE__SHIFT 0x00000003 4359*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ_MASK 0x00010000L 4360*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_REQ__SHIFT 0x00000010 4361*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS_MASK 0x00000003L 4362*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_STATUS__SHIFT 0x00000000 4363*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG_MASK 0x00020000L 4364*b843c749SSergey Zigachev #define DC_I2C_DDC6_HW_STATUS__DC_I2C_DDC6_HW_URG__SHIFT 0x00000011 4365*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN_MASK 0x00000080L 4366*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_CLK_DRIVE_EN__SHIFT 0x00000007 4367*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN_MASK 0x00000001L 4368*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_EN__SHIFT 0x00000000 4369*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL_MASK 0x00000002L 4370*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_DATA_DRIVE_SEL__SHIFT 0x00000001 4371*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE_MASK 0x00000010L 4372*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_ENABLE__SHIFT 0x00000004 4373*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE_MASK 0x00000020L 4374*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_EDID_DETECT_MODE__SHIFT 0x00000005 4375*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE_MASK 0x00000040L 4376*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_ENABLE__SHIFT 0x00000006 4377*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4378*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_BYTE_DELAY__SHIFT 0x00000008 4379*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4380*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4381*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT_MASK 0xff000000L 4382*b843c749SSergey Zigachev #define DC_I2C_DDC6_SETUP__DC_I2C_DDC6_TIME_LIMIT__SHIFT 0x00000018 4383*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4384*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4385*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE_MASK 0xffff0000L 4386*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_PRESCALE__SHIFT 0x00000010 4387*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD_MASK 0x00000003L 4388*b843c749SSergey Zigachev #define DC_I2C_DDC6_SPEED__DC_I2C_DDC6_THRESHOLD__SHIFT 0x00000000 4389*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES_MASK 0x0f000000L 4390*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_NUM_VALID_TRIES__SHIFT 0x00000018 4391*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE_MASK 0x70000000L 4392*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATE__SHIFT 0x0000001c 4393*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS_MASK 0x00100000L 4394*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_EDID_DETECT_STATUS__SHIFT 0x00000014 4395*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE_MASK 0x00000008L 4396*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_DONE__SHIFT 0x00000003 4397*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ_MASK 0x00010000L 4398*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_REQ__SHIFT 0x00000010 4399*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS_MASK 0x00000003L 4400*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_STATUS__SHIFT 0x00000000 4401*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG_MASK 0x00020000L 4402*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_HW_STATUS__DC_I2C_DDCVGA_HW_URG__SHIFT 0x00000011 4403*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN_MASK 0x00000080L 4404*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_CLK_DRIVE_EN__SHIFT 0x00000007 4405*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN_MASK 0x00000001L 4406*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_EN__SHIFT 0x00000000 4407*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL_MASK 0x00000002L 4408*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_DATA_DRIVE_SEL__SHIFT 0x00000001 4409*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE_MASK 0x00000010L 4410*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_ENABLE__SHIFT 0x00000004 4411*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE_MASK 0x00000020L 4412*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_EDID_DETECT_MODE__SHIFT 0x00000005 4413*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE_MASK 0x00000040L 4414*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_ENABLE__SHIFT 0x00000006 4415*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY_MASK 0x0000ff00L 4416*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_BYTE_DELAY__SHIFT 0x00000008 4417*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY_MASK 0x00ff0000L 4418*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_INTRA_TRANSACTION_DELAY__SHIFT 0x00000010 4419*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT_MASK 0xff000000L 4420*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SETUP__DC_I2C_DDCVGA_TIME_LIMIT__SHIFT 0x00000018 4421*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 4422*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 4423*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE_MASK 0xffff0000L 4424*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_PRESCALE__SHIFT 0x00000010 4425*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD_MASK 0x00000003L 4426*b843c749SSergey Zigachev #define DC_I2C_DDCVGA_SPEED__DC_I2C_DDCVGA_THRESHOLD__SHIFT 0x00000000 4427*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID_MASK 0x00f00000L 4428*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_NUM_TRIES_UNTIL_VALID__SHIFT 0x00000014 4429*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET_MASK 0x10000000L 4430*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_SEND_RESET__SHIFT 0x0000001c 4431*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME_MASK 0x0000ffffL 4432*b843c749SSergey Zigachev #define DC_I2C_EDID_DETECT_CTRL__DC_I2C_EDID_DETECT_WAIT_TIME__SHIFT 0x00000000 4433*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK_MASK 0x00000020L 4434*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_ACK__SHIFT 0x00000005 4435*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT_MASK 0x00000010L 4436*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_INT__SHIFT 0x00000004 4437*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK_MASK 0x00000040L 4438*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC1_HW_DONE_MASK__SHIFT 0x00000006 4439*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK_MASK 0x00000200L 4440*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_ACK__SHIFT 0x00000009 4441*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT_MASK 0x00000100L 4442*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_INT__SHIFT 0x00000008 4443*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK_MASK 0x00000400L 4444*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC2_HW_DONE_MASK__SHIFT 0x0000000a 4445*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK_MASK 0x00002000L 4446*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_ACK__SHIFT 0x0000000d 4447*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT_MASK 0x00001000L 4448*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_INT__SHIFT 0x0000000c 4449*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK_MASK 0x00004000L 4450*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC3_HW_DONE_MASK__SHIFT 0x0000000e 4451*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK_MASK 0x00020000L 4452*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_ACK__SHIFT 0x00000011 4453*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT_MASK 0x00010000L 4454*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_INT__SHIFT 0x00000010 4455*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK_MASK 0x00040000L 4456*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC4_HW_DONE_MASK__SHIFT 0x00000012 4457*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK_MASK 0x00200000L 4458*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_ACK__SHIFT 0x00000015 4459*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT_MASK 0x00100000L 4460*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_INT__SHIFT 0x00000014 4461*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK_MASK 0x00400000L 4462*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC5_HW_DONE_MASK__SHIFT 0x00000016 4463*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK_MASK 0x02000000L 4464*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_ACK__SHIFT 0x00000019 4465*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT_MASK 0x01000000L 4466*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_INT__SHIFT 0x00000018 4467*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK_MASK 0x04000000L 4468*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDC6_HW_DONE_MASK__SHIFT 0x0000001a 4469*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK_MASK 0x10000000L 4470*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_ACK__SHIFT 0x0000001c 4471*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT_MASK 0x08000000L 4472*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_INT__SHIFT 0x0000001b 4473*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK_MASK 0x20000000L 4474*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_DDCVGA_HW_DONE_MASK__SHIFT 0x0000001d 4475*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK_MASK 0x00000002L 4476*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_ACK__SHIFT 0x00000001 4477*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT_MASK 0x00000001L 4478*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_INT__SHIFT 0x00000000 4479*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK_MASK 0x00000004L 4480*b843c749SSergey Zigachev #define DC_I2C_INTERRUPT_CONTROL__DC_I2C_SW_DONE_MASK__SHIFT 0x00000002 4481*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED_MASK 0x00000010L 4482*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_ABORTED__SHIFT 0x00000004 4483*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW_MASK 0x00000080L 4484*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_BUFFER_OVERFLOW__SHIFT 0x00000007 4485*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE_MASK 0x00000004L 4486*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_DONE__SHIFT 0x00000002 4487*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED_MASK 0x00000040L 4488*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_INTERRUPTED__SHIFT 0x00000006 4489*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0_MASK 0x00001000L 4490*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK0__SHIFT 0x0000000c 4491*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1_MASK 0x00002000L 4492*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK1__SHIFT 0x0000000d 4493*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2_MASK 0x00004000L 4494*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK2__SHIFT 0x0000000e 4495*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3_MASK 0x00008000L 4496*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_NACK3__SHIFT 0x0000000f 4497*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ_MASK 0x00040000L 4498*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_REQ__SHIFT 0x00000012 4499*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS_MASK 0x00000003L 4500*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_STATUS__SHIFT 0x00000000 4501*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK_MASK 0x00000100L 4502*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_STOPPED_ON_NACK__SHIFT 0x00000008 4503*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT_MASK 0x00000020L 4504*b843c749SSergey Zigachev #define DC_I2C_SW_STATUS__DC_I2C_SW_TIMEOUT__SHIFT 0x00000005 4505*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0_MASK 0x00ff0000L 4506*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_COUNT0__SHIFT 0x00000010 4507*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_RW0_MASK 0x00000001L 4508*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_RW0__SHIFT 0x00000000 4509*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_START0_MASK 0x00001000L 4510*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_START0__SHIFT 0x0000000c 4511*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_STOP0_MASK 0x00002000L 4512*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_STOP0__SHIFT 0x0000000d 4513*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0_MASK 0x00000100L 4514*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION0__DC_I2C_STOP_ON_NACK0__SHIFT 0x00000008 4515*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1_MASK 0x00ff0000L 4516*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_COUNT1__SHIFT 0x00000010 4517*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_RW1_MASK 0x00000001L 4518*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_RW1__SHIFT 0x00000000 4519*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_START1_MASK 0x00001000L 4520*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_START1__SHIFT 0x0000000c 4521*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_STOP1_MASK 0x00002000L 4522*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_STOP1__SHIFT 0x0000000d 4523*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1_MASK 0x00000100L 4524*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION1__DC_I2C_STOP_ON_NACK1__SHIFT 0x00000008 4525*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2_MASK 0x00ff0000L 4526*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_COUNT2__SHIFT 0x00000010 4527*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_RW2_MASK 0x00000001L 4528*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_RW2__SHIFT 0x00000000 4529*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_START2_MASK 0x00001000L 4530*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_START2__SHIFT 0x0000000c 4531*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_STOP2_MASK 0x00002000L 4532*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_STOP2__SHIFT 0x0000000d 4533*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2_MASK 0x00000100L 4534*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION2__DC_I2C_STOP_ON_NACK2__SHIFT 0x00000008 4535*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3_MASK 0x00ff0000L 4536*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_COUNT3__SHIFT 0x00000010 4537*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_RW3_MASK 0x00000001L 4538*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_RW3__SHIFT 0x00000000 4539*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_START3_MASK 0x00001000L 4540*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_START3__SHIFT 0x0000000c 4541*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_STOP3_MASK 0x00002000L 4542*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_STOP3__SHIFT 0x0000000d 4543*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3_MASK 0x00000100L 4544*b843c749SSergey Zigachev #define DC_I2C_TRANSACTION3__DC_I2C_STOP_ON_NACK3__SHIFT 0x00000008 4545*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL_MASK 0xf8000000L 4546*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DCI_PG_TEST_CLK_SEL__SHIFT 0x0000001b 4547*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL_MASK 0x0000001fL 4548*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DCI_TEST_CLK_SEL__SHIFT 0x00000000 4549*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS_MASK 0x00008000L 4550*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMCU_GATE_DIS__SHIFT 0x0000000f 4551*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS_MASK 0x00010000L 4552*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF0_GATE_DIS__SHIFT 0x00000010 4553*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS_MASK 0x00020000L 4554*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF1_GATE_DIS__SHIFT 0x00000011 4555*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS_MASK 0x00040000L 4556*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF2_GATE_DIS__SHIFT 0x00000012 4557*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS_MASK 0x00080000L 4558*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF3_GATE_DIS__SHIFT 0x00000013 4559*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS_MASK 0x00100000L 4560*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF4_GATE_DIS__SHIFT 0x00000014 4561*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS_MASK 0x00200000L 4562*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_DMIF5_GATE_DIS__SHIFT 0x00000015 4563*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS_MASK 0x00000200L 4564*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_FBC_GATE_DIS__SHIFT 0x00000009 4565*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS_MASK 0x00000800L 4566*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_VGA_GATE_DIS__SHIFT 0x0000000b 4567*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS_MASK 0x00002000L 4568*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_G_VIP_GATE_DIS__SHIFT 0x0000000d 4569*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS_MASK 0x00000040L 4570*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_M_GATE_DIS__SHIFT 0x00000006 4571*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS_MASK 0x00000020L 4572*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_DCI_GATE_DIS__SHIFT 0x00000005 4573*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS_MASK 0x00004000L 4574*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_DMCU_GATE_DIS__SHIFT 0x0000000e 4575*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS_MASK 0x00000400L 4576*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_VGA_GATE_DIS__SHIFT 0x0000000a 4577*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS_MASK 0x00001000L 4578*b843c749SSergey Zigachev #define DCI_CLK_CNTL__DISPCLK_R_VIP_GATE_DIS__SHIFT 0x0000000c 4579*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS_MASK 0x00400000L 4580*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_G_DMIF_GATE_DIS__SHIFT 0x00000016 4581*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS_MASK 0x00800000L 4582*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_G_DMIFTRK_GATE_DIS__SHIFT 0x00000017 4583*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS_MASK 0x00000100L 4584*b843c749SSergey Zigachev #define DCI_CLK_CNTL__SCLK_R_AZ_GATE_DIS__SHIFT 0x00000008 4585*b843c749SSergey Zigachev #define DCI_DEBUG_CONFIG__DCI_DBG_SEL_MASK 0x0000000fL 4586*b843c749SSergey Zigachev #define DCI_DEBUG_CONFIG__DCI_DBG_SEL__SHIFT 0x00000000 4587*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000001L 4588*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000000 4589*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE_MASK 0x00003000L 4590*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000c 4591*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000040L 4592*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF0_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000006 4593*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000002L 4594*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000001 4595*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE_MASK 0x0000c000L 4596*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_PWR_STATE__SHIFT 0x0000000e 4597*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000080L 4598*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF1_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000007 4599*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000004L 4600*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000002 4601*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE_MASK 0x00030000L 4602*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_PWR_STATE__SHIFT 0x00000010 4603*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000100L 4604*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF2_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 4605*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000008L 4606*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4607*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE_MASK 0x000c0000L 4608*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_PWR_STATE__SHIFT 0x00000012 4609*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000200L 4610*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF3_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x00000009 4611*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000010L 4612*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4613*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE_MASK 0x00300000L 4614*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_PWR_STATE__SHIFT 0x00000014 4615*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000400L 4616*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF4_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000a 4617*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS_MASK 0x00000020L 4618*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 4619*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE_MASK 0x00c00000L 4620*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_PWR_STATE__SHIFT 0x00000016 4621*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS_MASK 0x00000800L 4622*b843c749SSergey Zigachev #define DCI_MEM_PWR_CNTL__DMIF5_ASYNC_MEM_SHUTDOWN_DIS__SHIFT 0x0000000b 4623*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE_MASK 0x00000003L 4624*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM1_PWR_STATE__SHIFT 0x00000000 4625*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE_MASK 0x0000000cL 4626*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM2_PWR_STATE__SHIFT 0x00000002 4627*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE_MASK 0x00000030L 4628*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE2__DMCU_ERAM3_PWR_STATE__SHIFT 0x00000004 4629*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE_MASK 0x00c00000L 4630*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__AZ_MEM_PWR_STATE__SHIFT 0x00000016 4631*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE_MASK 0x30000000L 4632*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMCU_IRAM_PWR_STATE__SHIFT 0x0000001c 4633*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE_MASK 0x00000003L 4634*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMCU_MEM_PWR_STATE__SHIFT 0x00000000 4635*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE_MASK 0x0000000cL 4636*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF0_MEM_PWR_STATE__SHIFT 0x00000002 4637*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE_MASK 0x00000030L 4638*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF1_MEM_PWR_STATE__SHIFT 0x00000004 4639*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE_MASK 0x000000c0L 4640*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF2_MEM_PWR_STATE__SHIFT 0x00000006 4641*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE_MASK 0x00000300L 4642*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF3_MEM_PWR_STATE__SHIFT 0x00000008 4643*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE_MASK 0x00000c00L 4644*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF4_MEM_PWR_STATE__SHIFT 0x0000000a 4645*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE_MASK 0x00003000L 4646*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF5_MEM_PWR_STATE__SHIFT 0x0000000c 4647*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE_MASK 0x0c000000L 4648*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM1_PWR_STATE__SHIFT 0x0000001a 4649*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE_MASK 0x03000000L 4650*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__DMIF_XLR_MEM_PWR_STATE__SHIFT 0x00000018 4651*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE_MASK 0x00030000L 4652*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__FBC_MEM_PWR_STATE__SHIFT 0x00000010 4653*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE_MASK 0x000c0000L 4654*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__MCIF_MEM_PWR_STATE__SHIFT 0x00000012 4655*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE_MASK 0x0000c000L 4656*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__VGA_MEM_PWR_STATE__SHIFT 0x0000000e 4657*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE_MASK 0x00300000L 4658*b843c749SSergey Zigachev #define DCI_MEM_PWR_STATE__VIP_MEM_PWR_STATE__SHIFT 0x00000014 4659*b843c749SSergey Zigachev #define DCIO_DEBUG10__DCIO_DIGC_DEBUG_MASK 0xffffffffL 4660*b843c749SSergey Zigachev #define DCIO_DEBUG10__DCIO_DIGC_DEBUG__SHIFT 0x00000000 4661*b843c749SSergey Zigachev #define DCIO_DEBUG11__DCIO_DIGD_DEBUG_MASK 0xffffffffL 4662*b843c749SSergey Zigachev #define DCIO_DEBUG11__DCIO_DIGD_DEBUG__SHIFT 0x00000000 4663*b843c749SSergey Zigachev #define DCIO_DEBUG12__DCIO_DIGE_DEBUG_MASK 0xffffffffL 4664*b843c749SSergey Zigachev #define DCIO_DEBUG12__DCIO_DIGE_DEBUG__SHIFT 0x00000000 4665*b843c749SSergey Zigachev #define DCIO_DEBUG13__DCIO_DIGF_DEBUG_MASK 0xffffffffL 4666*b843c749SSergey Zigachev #define DCIO_DEBUG13__DCIO_DIGF_DEBUG__SHIFT 0x00000000 4667*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE_MASK 0x00040000L 4668*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_CLK_TRISTATE__SHIFT 0x00000012 4669*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_MASK 0x00008000L 4670*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX_MASK 0x00004000L 4671*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_PREMUX__SHIFT 0x0000000e 4672*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG_MASK 0x00002000L 4673*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0_REG__SHIFT 0x0000000d 4674*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_A0__SHIFT 0x0000000f 4675*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_MASK 0x00100000L 4676*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX_MASK 0x00080000L 4677*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_PREMUX__SHIFT 0x00000013 4678*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG_MASK 0x00010000L 4679*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN_REG__SHIFT 0x00000010 4680*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_EN__SHIFT 0x00000014 4681*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG_MASK 0x00400000L 4682*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MASK_REG__SHIFT 0x00000016 4683*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX_MASK 0x00200000L 4684*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_MUX__SHIFT 0x00000015 4685*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_MASK 0x08000000L 4686*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX_MASK 0x04000000L 4687*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0_PREMUX__SHIFT 0x0000001a 4688*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVOCNTL1_SEL0__SHIFT 0x0000001b 4689*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE_MASK 0x00800000L 4690*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_ENABLE__SHIFT 0x00000017 4691*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE_MASK 0x00020000L 4692*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_HSYNC_TRISTATE__SHIFT 0x00000011 4693*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL_MASK 0x02000000L 4694*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_RATE_SEL__SHIFT 0x00000019 4695*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE_MASK 0x01000000L 4696*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_DVO_VSYNC_TRISTATE__SHIFT 0x00000018 4697*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C_MASK 0x00001000L 4698*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCLK_C__SHIFT 0x0000000c 4699*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_MASK 0x000000c0L 4700*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG_MASK 0x00000003L 4701*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0_REG__SHIFT 0x00000000 4702*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_A0__SHIFT 0x00000006 4703*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_MASK 0x00000c00L 4704*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG_MASK 0x00000030L 4705*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN_REG__SHIFT 0x00000004 4706*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_EN__SHIFT 0x0000000a 4707*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG_MASK 0x0000000cL 4708*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_MASK_REG__SHIFT 0x00000002 4709*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0_MASK 0x00000300L 4710*b843c749SSergey Zigachev #define DCIO_DEBUG1__DOUT_DCIO_MVP_DVOCNTL_SEL0__SHIFT 0x00000008 4711*b843c749SSergey Zigachev #define DCIO_DEBUG2__DCIO_DEBUG2_MASK 0xffffffffL 4712*b843c749SSergey Zigachev #define DCIO_DEBUG2__DCIO_DEBUG2__SHIFT 0x00000000 4713*b843c749SSergey Zigachev #define DCIO_DEBUG3__DCIO_DEBUG3_MASK 0xffffffffL 4714*b843c749SSergey Zigachev #define DCIO_DEBUG3__DCIO_DEBUG3__SHIFT 0x00000000 4715*b843c749SSergey Zigachev #define DCIO_DEBUG4__DCIO_DEBUG4_MASK 0xffffffffL 4716*b843c749SSergey Zigachev #define DCIO_DEBUG4__DCIO_DEBUG4__SHIFT 0x00000000 4717*b843c749SSergey Zigachev #define DCIO_DEBUG5__DCIO_DEBUG5_MASK 0xffffffffL 4718*b843c749SSergey Zigachev #define DCIO_DEBUG5__DCIO_DEBUG5__SHIFT 0x00000000 4719*b843c749SSergey Zigachev #define DCIO_DEBUG6__DCIO_DEBUG6_MASK 0xffffffffL 4720*b843c749SSergey Zigachev #define DCIO_DEBUG6__DCIO_DEBUG6__SHIFT 0x00000000 4721*b843c749SSergey Zigachev #define DCIO_DEBUG7__DCIO_DEBUG7_MASK 0xffffffffL 4722*b843c749SSergey Zigachev #define DCIO_DEBUG7__DCIO_DEBUG7__SHIFT 0x00000000 4723*b843c749SSergey Zigachev #define DCIO_DEBUG8__DCIO_DEBUG8_MASK 0xffffffffL 4724*b843c749SSergey Zigachev #define DCIO_DEBUG8__DCIO_DEBUG8__SHIFT 0x00000000 4725*b843c749SSergey Zigachev #define DCIO_DEBUG9__DCIO_DEBUG9_MASK 0xffffffffL 4726*b843c749SSergey Zigachev #define DCIO_DEBUG9__DCIO_DEBUG9__SHIFT 0x00000000 4727*b843c749SSergey Zigachev #define DCIO_DEBUGA__DCIO_DEBUGA_MASK 0xffffffffL 4728*b843c749SSergey Zigachev #define DCIO_DEBUGA__DCIO_DEBUGA__SHIFT 0x00000000 4729*b843c749SSergey Zigachev #define DCIO_DEBUGB__DCIO_DEBUGB_MASK 0xffffffffL 4730*b843c749SSergey Zigachev #define DCIO_DEBUGB__DCIO_DEBUGB__SHIFT 0x00000000 4731*b843c749SSergey Zigachev #define DCIO_DEBUGC__DCIO_DEBUGC_MASK 0xffffffffL 4732*b843c749SSergey Zigachev #define DCIO_DEBUGC__DCIO_DEBUGC__SHIFT 0x00000000 4733*b843c749SSergey Zigachev #define DCIO_DEBUG__DCIO_DEBUG_MASK 0xffffffffL 4734*b843c749SSergey Zigachev #define DCIO_DEBUG__DCIO_DEBUG__SHIFT 0x00000000 4735*b843c749SSergey Zigachev #define DCIO_DEBUGD__DCIO_DEBUGD_MASK 0xffffffffL 4736*b843c749SSergey Zigachev #define DCIO_DEBUGD__DCIO_DEBUGD__SHIFT 0x00000000 4737*b843c749SSergey Zigachev #define DCIO_DEBUGE__DCIO_DIGA_DEBUG_MASK 0xffffffffL 4738*b843c749SSergey Zigachev #define DCIO_DEBUGE__DCIO_DIGA_DEBUG__SHIFT 0x00000000 4739*b843c749SSergey Zigachev #define DCIO_DEBUGF__DCIO_DIGB_DEBUG_MASK 0xffffffffL 4740*b843c749SSergey Zigachev #define DCIO_DEBUGF__DCIO_DIGB_DEBUG__SHIFT 0x00000000 4741*b843c749SSergey Zigachev #define DCIO_DEBUG_ID__DCIO_DEBUG_ID_MASK 0xffffffffL 4742*b843c749SSergey Zigachev #define DCIO_DEBUG_ID__DCIO_DEBUG_ID__SHIFT 0x00000000 4743*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4744*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4745*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL_MASK 0x00000700L 4746*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_TIMING_SYNC_SEL__SHIFT 0x00000008 4747*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL_MASK 0x00000007L 4748*b843c749SSergey Zigachev #define DCIO_GSL0_CNTL__DCIO_GSL0_VSYNC_SEL__SHIFT 0x00000000 4749*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4750*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4751*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL_MASK 0x00000700L 4752*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_TIMING_SYNC_SEL__SHIFT 0x00000008 4753*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL_MASK 0x00000007L 4754*b843c749SSergey Zigachev #define DCIO_GSL1_CNTL__DCIO_GSL1_VSYNC_SEL__SHIFT 0x00000000 4755*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL_MASK 0x00070000L 4756*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_GLOBAL_UNLOCK_SEL__SHIFT 0x00000010 4757*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL_MASK 0x00000700L 4758*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_TIMING_SYNC_SEL__SHIFT 0x00000008 4759*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL_MASK 0x00000007L 4760*b843c749SSergey Zigachev #define DCIO_GSL2_CNTL__DCIO_GSL2_VSYNC_SEL__SHIFT 0x00000000 4761*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4762*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4763*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK_MASK 0x00000300L 4764*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_MASK__SHIFT 0x00000008 4765*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4766*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_CLK_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4767*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4768*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4769*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK_MASK 0x03000000L 4770*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_MASK__SHIFT 0x00000018 4771*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4772*b843c749SSergey Zigachev #define DCIO_GSL_GENLK_PAD_CNTL__DCIO_GENLK_VSYNC_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4773*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL_MASK 0x00000030L 4774*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_FLIP_LOCK_SEL__SHIFT 0x00000004 4775*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK_MASK 0x00000300L 4776*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_MASK__SHIFT 0x00000008 4777*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL_MASK 0x00000003L 4778*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_A_GSL_TIMING_SYNC_SEL__SHIFT 0x00000000 4779*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL_MASK 0x00300000L 4780*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_FLIP_LOCK_SEL__SHIFT 0x00000014 4781*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK_MASK 0x03000000L 4782*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_MASK__SHIFT 0x00000018 4783*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL_MASK 0x00030000L 4784*b843c749SSergey Zigachev #define DCIO_GSL_SWAPLOCK_PAD_CNTL__DCIO_SWAPLOCK_B_GSL_TIMING_SYNC_SEL__SHIFT 0x00000010 4785*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4786*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4787*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE_MASK 0x00007000L 4788*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4789*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET_MASK 0x00000020L 4790*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4791*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS_MASK 0x00000300L 4792*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_AB__IMPCAL_STATUS__SHIFT 0x00000008 4793*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4794*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4795*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE_MASK 0x00007000L 4796*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4797*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET_MASK 0x00000020L 4798*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4799*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS_MASK 0x00000300L 4800*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_CD__IMPCAL_STATUS__SHIFT 0x00000008 4801*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE_MASK 0x0000000fL 4802*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__CALR_CNTL_OVERRIDE__SHIFT 0x00000000 4803*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE_MASK 0x00007000L 4804*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_ARB_STATE__SHIFT 0x0000000c 4805*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET_MASK 0x00000020L 4806*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_SOFT_RESET__SHIFT 0x00000005 4807*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS_MASK 0x00000300L 4808*b843c749SSergey Zigachev #define DCIO_IMPCAL_CNTL_EF__IMPCAL_STATUS__SHIFT 0x00000008 4809*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA_MASK 0xffffffffL 4810*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_DATA__DCIO_TEST_DEBUG_DATA__SHIFT 0x00000000 4811*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX_MASK 0x000000ffL 4812*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_INDEX__SHIFT 0x00000000 4813*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4814*b843c749SSergey Zigachev #define DCIO_TEST_DEBUG_INDEX__DCIO_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4815*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF0_SOFT_RESET_MASK 0x00000010L 4816*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF0_SOFT_RESET__SHIFT 0x00000004 4817*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF1_SOFT_RESET_MASK 0x00000020L 4818*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF1_SOFT_RESET__SHIFT 0x00000005 4819*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF2_SOFT_RESET_MASK 0x00000040L 4820*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF2_SOFT_RESET__SHIFT 0x00000006 4821*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF3_SOFT_RESET_MASK 0x00000080L 4822*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF3_SOFT_RESET__SHIFT 0x00000007 4823*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF4_SOFT_RESET_MASK 0x00000100L 4824*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF4_SOFT_RESET__SHIFT 0x00000008 4825*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF5_SOFT_RESET_MASK 0x00000200L 4826*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIF5_SOFT_RESET__SHIFT 0x00000009 4827*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET_MASK 0x00001000L 4828*b843c749SSergey Zigachev #define DCI_SOFT_RESET__DMIFARB_SOFT_RESET__SHIFT 0x0000000c 4829*b843c749SSergey Zigachev #define DCI_SOFT_RESET__FBC_SOFT_RESET_MASK 0x00000008L 4830*b843c749SSergey Zigachev #define DCI_SOFT_RESET__FBC_SOFT_RESET__SHIFT 0x00000003 4831*b843c749SSergey Zigachev #define DCI_SOFT_RESET__MCIF_SOFT_RESET_MASK 0x00000004L 4832*b843c749SSergey Zigachev #define DCI_SOFT_RESET__MCIF_SOFT_RESET__SHIFT 0x00000002 4833*b843c749SSergey Zigachev #define DCI_SOFT_RESET__VGA_SOFT_RESET_MASK 0x00000001L 4834*b843c749SSergey Zigachev #define DCI_SOFT_RESET__VGA_SOFT_RESET__SHIFT 0x00000000 4835*b843c749SSergey Zigachev #define DCI_SOFT_RESET__VIP_SOFT_RESET_MASK 0x00000002L 4836*b843c749SSergey Zigachev #define DCI_SOFT_RESET__VIP_SOFT_RESET__SHIFT 0x00000001 4837*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA_MASK 0xffffffffL 4838*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_DATA__DCI_TEST_DEBUG_DATA__SHIFT 0x00000000 4839*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX_MASK 0x000000ffL 4840*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_INDEX__SHIFT 0x00000000 4841*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 4842*b843c749SSergey Zigachev #define DCI_TEST_DEBUG_INDEX__DCI_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 4843*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE_MASK 0x000003ffL 4844*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_BLUE__SHIFT 0x00000000 4845*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN_MASK 0x000ffc00L 4846*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_GREEN__SHIFT 0x0000000a 4847*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED_MASK 0x3ff00000L 4848*b843c749SSergey Zigachev #define DC_LUT_30_COLOR__DC_LUT_COLOR_10_RED__SHIFT 0x00000014 4849*b843c749SSergey Zigachev #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE_MASK 0x00000002L 4850*b843c749SSergey Zigachev #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_DONE__SHIFT 0x00000001 4851*b843c749SSergey Zigachev #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL_MASK 0x00000001L 4852*b843c749SSergey Zigachev #define DC_LUT_AUTOFILL__DC_LUT_AUTOFILL__SHIFT 0x00000000 4853*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE_MASK 0x0000ffffL 4854*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_BLUE__DC_LUT_BLACK_OFFSET_BLUE__SHIFT 0x00000000 4855*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN_MASK 0x0000ffffL 4856*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_GREEN__DC_LUT_BLACK_OFFSET_GREEN__SHIFT 0x00000000 4857*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED_MASK 0x0000ffffL 4858*b843c749SSergey Zigachev #define DC_LUT_BLACK_OFFSET_RED__DC_LUT_BLACK_OFFSET_RED__SHIFT 0x00000000 4859*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN_MASK 0x00000020L 4860*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_FLOAT_POINT_EN__SHIFT 0x00000005 4861*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT_MASK 0x000000c0L 4862*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_FORMAT__SHIFT 0x00000006 4863*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN_MASK 0x00000010L 4864*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_B_SIGNED_EN__SHIFT 0x00000004 4865*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN_MASK 0x00002000L 4866*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_FLOAT_POINT_EN__SHIFT 0x0000000d 4867*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT_MASK 0x0000c000L 4868*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_FORMAT__SHIFT 0x0000000e 4869*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN_MASK 0x00001000L 4870*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_G_SIGNED_EN__SHIFT 0x0000000c 4871*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN_MASK 0x00200000L 4872*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_FLOAT_POINT_EN__SHIFT 0x00000015 4873*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT_MASK 0x00c00000L 4874*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_FORMAT__SHIFT 0x00000016 4875*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN_MASK 0x00100000L 4876*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_DATA_R_SIGNED_EN__SHIFT 0x00000014 4877*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_B_MASK 0x0000000fL 4878*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_B__SHIFT 0x00000000 4879*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_G_MASK 0x00000f00L 4880*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_G__SHIFT 0x00000008 4881*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_R_MASK 0x000f0000L 4882*b843c749SSergey Zigachev #define DC_LUT_CONTROL__DC_LUT_INC_R__SHIFT 0x00000010 4883*b843c749SSergey Zigachev #define DC_LUT_PWL_DATA__DC_LUT_BASE_MASK 0x0000ffffL 4884*b843c749SSergey Zigachev #define DC_LUT_PWL_DATA__DC_LUT_BASE__SHIFT 0x00000000 4885*b843c749SSergey Zigachev #define DC_LUT_PWL_DATA__DC_LUT_DELTA_MASK 0xffff0000L 4886*b843c749SSergey Zigachev #define DC_LUT_PWL_DATA__DC_LUT_DELTA__SHIFT 0x00000010 4887*b843c749SSergey Zigachev #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX_MASK 0x000000ffL 4888*b843c749SSergey Zigachev #define DC_LUT_RW_INDEX__DC_LUT_RW_INDEX__SHIFT 0x00000000 4889*b843c749SSergey Zigachev #define DC_LUT_RW_MODE__DC_LUT_RW_MODE_MASK 0x00000001L 4890*b843c749SSergey Zigachev #define DC_LUT_RW_MODE__DC_LUT_RW_MODE__SHIFT 0x00000000 4891*b843c749SSergey Zigachev #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR_MASK 0x0000ffffL 4892*b843c749SSergey Zigachev #define DC_LUT_SEQ_COLOR__DC_LUT_SEQ_COLOR__SHIFT 0x00000000 4893*b843c749SSergey Zigachev #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE_MASK 0x00000001L 4894*b843c749SSergey Zigachev #define DC_LUT_VGA_ACCESS_ENABLE__DC_LUT_VGA_ACCESS_ENABLE__SHIFT 0x00000000 4895*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE_MASK 0x0000ffffL 4896*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_BLUE__DC_LUT_WHITE_OFFSET_BLUE__SHIFT 0x00000000 4897*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN_MASK 0x0000ffffL 4898*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_GREEN__DC_LUT_WHITE_OFFSET_GREEN__SHIFT 0x00000000 4899*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED_MASK 0x0000ffffL 4900*b843c749SSergey Zigachev #define DC_LUT_WHITE_OFFSET_RED__DC_LUT_WHITE_OFFSET_RED__SHIFT 0x00000000 4901*b843c749SSergey Zigachev #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK_MASK 0x00000007L 4902*b843c749SSergey Zigachev #define DC_LUT_WRITE_EN_MASK__DC_LUT_WRITE_EN_MASK__SHIFT 0x00000000 4903*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS_MASK 0x80000000L 4904*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SPARE_FLOPS__SHIFT 0x0000001f 4905*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP_MASK 0x10000000L 4906*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_IN_CAP__SHIFT 0x0000001c 4907*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE_MASK 0x00001000L 4908*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ONE__SHIFT 0x0000000c 4909*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO_MASK 0x00010000L 4910*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO__SHIFT 0x00000010 4911*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL_MASK 0x00000100L 4912*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_OUT_SEL__SHIFT 0x00000008 4913*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS_MASK 0x00100000L 4914*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__DC_MVP_SWAP_LOCK_STATUS__SHIFT 0x00000014 4915*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE_MASK 0x00000003L 4916*b843c749SSergey Zigachev #define DC_MVP_LB_CONTROL__MVP_SWAP_LOCK_IN_MODE__SHIFT 0x00000000 4917*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL_MASK 0x0000001fL 4918*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DCO_TEST_CLK_SEL__SHIFT 0x00000000 4919*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS_MASK 0x00000040L 4920*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_ABM_GATE_DIS__SHIFT 0x00000006 4921*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS_MASK 0x00000100L 4922*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DACA_GATE_DIS__SHIFT 0x00000008 4923*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS_MASK 0x00000200L 4924*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DACB_GATE_DIS__SHIFT 0x00000009 4925*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS_MASK 0x01000000L 4926*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGA_GATE_DIS__SHIFT 0x00000018 4927*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS_MASK 0x02000000L 4928*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGB_GATE_DIS__SHIFT 0x00000019 4929*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS_MASK 0x04000000L 4930*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGC_GATE_DIS__SHIFT 0x0000001a 4931*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS_MASK 0x08000000L 4932*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGD_GATE_DIS__SHIFT 0x0000001b 4933*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS_MASK 0x10000000L 4934*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGE_GATE_DIS__SHIFT 0x0000001c 4935*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS_MASK 0x20000000L 4936*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DIGF_GATE_DIS__SHIFT 0x0000001d 4937*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS_MASK 0x00000080L 4938*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_DVO_GATE_DIS__SHIFT 0x00000007 4939*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS_MASK 0x00010000L 4940*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT0_GATE_DIS__SHIFT 0x00000010 4941*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS_MASK 0x00020000L 4942*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT1_GATE_DIS__SHIFT 0x00000011 4943*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS_MASK 0x00040000L 4944*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT2_GATE_DIS__SHIFT 0x00000012 4945*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS_MASK 0x00080000L 4946*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT3_GATE_DIS__SHIFT 0x00000013 4947*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS_MASK 0x00100000L 4948*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT4_GATE_DIS__SHIFT 0x00000014 4949*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS_MASK 0x00200000L 4950*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_G_FMT5_GATE_DIS__SHIFT 0x00000015 4951*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS_MASK 0x00001000L 4952*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_R_ABM_GATE_DIS__SHIFT 0x0000000c 4953*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS_MASK 0x00000020L 4954*b843c749SSergey Zigachev #define DCO_CLK_CNTL__DISPCLK_R_DCO_GATE_DIS__SHIFT 0x00000005 4955*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS_MASK 0x00000040L 4956*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_ABM_RAMP_DIS__SHIFT 0x00000006 4957*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS_MASK 0x00000100L 4958*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACA_RAMP_DIS__SHIFT 0x00000008 4959*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS_MASK 0x00000200L 4960*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DACB_RAMP_DIS__SHIFT 0x00000009 4961*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS_MASK 0x01000000L 4962*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGA_RAMP_DIS__SHIFT 0x00000018 4963*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS_MASK 0x02000000L 4964*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGB_RAMP_DIS__SHIFT 0x00000019 4965*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS_MASK 0x04000000L 4966*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGC_RAMP_DIS__SHIFT 0x0000001a 4967*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS_MASK 0x08000000L 4968*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGD_RAMP_DIS__SHIFT 0x0000001b 4969*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS_MASK 0x10000000L 4970*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGE_RAMP_DIS__SHIFT 0x0000001c 4971*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS_MASK 0x20000000L 4972*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DIGF_RAMP_DIS__SHIFT 0x0000001d 4973*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS_MASK 0x00000080L 4974*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_DVO_RAMP_DIS__SHIFT 0x00000007 4975*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS_MASK 0x00010000L 4976*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT0_RAMP_DIS__SHIFT 0x00000010 4977*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS_MASK 0x00020000L 4978*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT1_RAMP_DIS__SHIFT 0x00000011 4979*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS_MASK 0x00040000L 4980*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT2_RAMP_DIS__SHIFT 0x00000012 4981*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS_MASK 0x00080000L 4982*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT3_RAMP_DIS__SHIFT 0x00000013 4983*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS_MASK 0x00100000L 4984*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT4_RAMP_DIS__SHIFT 0x00000014 4985*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS_MASK 0x00200000L 4986*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_G_FMT5_RAMP_DIS__SHIFT 0x00000015 4987*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS_MASK 0x00001000L 4988*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_R_ABM_RAMP_DIS__SHIFT 0x0000000c 4989*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS_MASK 0x00000020L 4990*b843c749SSergey Zigachev #define DCO_CLK_RAMP_CNTL__DISPCLK_R_DCO_RAMP_DIS__SHIFT 0x00000005 4991*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS_MASK 0x00000008L 4992*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPA_LIGHT_SLEEP_DIS__SHIFT 0x00000003 4993*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS_MASK 0x00020000L 4994*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPA_MEM_SHUTDOWN_DIS__SHIFT 0x00000011 4995*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS_MASK 0x00000010L 4996*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPB_LIGHT_SLEEP_DIS__SHIFT 0x00000004 4997*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS_MASK 0x00040000L 4998*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPB_MEM_SHUTDOWN_DIS__SHIFT 0x00000012 4999*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS_MASK 0x00000020L 5000*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPC_LIGHT_SLEEP_DIS__SHIFT 0x00000005 5001*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS_MASK 0x00080000L 5002*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPC_MEM_SHUTDOWN_DIS__SHIFT 0x00000013 5003*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS_MASK 0x00000040L 5004*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPD_LIGHT_SLEEP_DIS__SHIFT 0x00000006 5005*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS_MASK 0x00100000L 5006*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPD_MEM_SHUTDOWN_DIS__SHIFT 0x00000014 5007*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS_MASK 0x00000080L 5008*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPE_LIGHT_SLEEP_DIS__SHIFT 0x00000007 5009*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS_MASK 0x00200000L 5010*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPE_MEM_SHUTDOWN_DIS__SHIFT 0x00000015 5011*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS_MASK 0x00000100L 5012*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPF_LIGHT_SLEEP_DIS__SHIFT 0x00000008 5013*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS_MASK 0x00400000L 5014*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__DPF_MEM_SHUTDOWN_DIS__SHIFT 0x00000016 5015*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS_MASK 0x00000200L 5016*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI0_LIGHT_SLEEP_DIS__SHIFT 0x00000009 5017*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS_MASK 0x00000400L 5018*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI1_LIGHT_SLEEP_DIS__SHIFT 0x0000000a 5019*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS_MASK 0x00000800L 5020*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI2_LIGHT_SLEEP_DIS__SHIFT 0x0000000b 5021*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS_MASK 0x00001000L 5022*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI3_LIGHT_SLEEP_DIS__SHIFT 0x0000000c 5023*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS_MASK 0x00002000L 5024*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI4_LIGHT_SLEEP_DIS__SHIFT 0x0000000d 5025*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS_MASK 0x00004000L 5026*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__HDMI5_LIGHT_SLEEP_DIS__SHIFT 0x0000000e 5027*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE_MASK 0x00000002L 5028*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__I2C_LIGHT_SLEEP_FORCE__SHIFT 0x00000001 5029*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS_MASK 0x00000004L 5030*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__MVP_LIGHT_SLEEP_DIS__SHIFT 0x00000002 5031*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS_MASK 0x00010000L 5032*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__MVP_MEM_SHUTDOWN_DIS__SHIFT 0x00000010 5033*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS_MASK 0x00000001L 5034*b843c749SSergey Zigachev #define DCO_LIGHT_SLEEP_DIS__TVOUT_LIGHT_SLEEP_DIS__SHIFT 0x00000000 5035*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE_MASK 0x000000c0L 5036*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPA_MEM_PWR_STATE__SHIFT 0x00000006 5037*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE_MASK 0x00000300L 5038*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPB_MEM_PWR_STATE__SHIFT 0x00000008 5039*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE_MASK 0x00000c00L 5040*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPC_MEM_PWR_STATE__SHIFT 0x0000000a 5041*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE_MASK 0x00003000L 5042*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPD_MEM_PWR_STATE__SHIFT 0x0000000c 5043*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE_MASK 0x0000c000L 5044*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPE_MEM_PWR_STATE__SHIFT 0x0000000e 5045*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE_MASK 0x00030000L 5046*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__DPF_MEM_PWR_STATE__SHIFT 0x00000010 5047*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE_MASK 0x000c0000L 5048*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI0_MEM_PWR_STATE__SHIFT 0x00000012 5049*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE_MASK 0x00300000L 5050*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI1_MEM_PWR_STATE__SHIFT 0x00000014 5051*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE_MASK 0x00c00000L 5052*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI2_MEM_PWR_STATE__SHIFT 0x00000016 5053*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE_MASK 0x03000000L 5054*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI3_MEM_PWR_STATE__SHIFT 0x00000018 5055*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE_MASK 0x0c000000L 5056*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI4_MEM_PWR_STATE__SHIFT 0x0000001a 5057*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE_MASK 0x30000000L 5058*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__HDMI5_MEM_PWR_STATE__SHIFT 0x0000001c 5059*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE_MASK 0x0000000cL 5060*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__I2C_MEM_PWR_STATE__SHIFT 0x00000002 5061*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE_MASK 0x00000030L 5062*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__MVP_MEM_PWR_STATE__SHIFT 0x00000004 5063*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE_MASK 0x00000003L 5064*b843c749SSergey Zigachev #define DCO_MEM_POWER_STATE__TVOUT_MEM_PWR_STATE__SHIFT 0x00000000 5065*b843c749SSergey Zigachev #define DCO_SOFT_RESET__ABM_SOFT_RESET_MASK 0x02000000L 5066*b843c749SSergey Zigachev #define DCO_SOFT_RESET__ABM_SOFT_RESET__SHIFT 0x00000019 5067*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET_MASK 0x20000000L 5068*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACA_CFG_IF_SOFT_RESET__SHIFT 0x0000001d 5069*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACA_SOFT_RESET_MASK 0x00000001L 5070*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACA_SOFT_RESET__SHIFT 0x00000000 5071*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACB_SOFT_RESET_MASK 0x00000002L 5072*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DACB_SOFT_RESET__SHIFT 0x00000001 5073*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DVO_ENABLE_RST_MASK 0x00000008L 5074*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DVO_ENABLE_RST__SHIFT 0x00000003 5075*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DVO_SOFT_RESET_MASK 0x08000000L 5076*b843c749SSergey Zigachev #define DCO_SOFT_RESET__DVO_SOFT_RESET__SHIFT 0x0000001b 5077*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT0_SOFT_RESET_MASK 0x00010000L 5078*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT0_SOFT_RESET__SHIFT 0x00000010 5079*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT1_SOFT_RESET_MASK 0x00020000L 5080*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT1_SOFT_RESET__SHIFT 0x00000011 5081*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT2_SOFT_RESET_MASK 0x00040000L 5082*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT2_SOFT_RESET__SHIFT 0x00000012 5083*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT3_SOFT_RESET_MASK 0x00080000L 5084*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT3_SOFT_RESET__SHIFT 0x00000013 5085*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT4_SOFT_RESET_MASK 0x00100000L 5086*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT4_SOFT_RESET__SHIFT 0x00000014 5087*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT5_SOFT_RESET_MASK 0x00200000L 5088*b843c749SSergey Zigachev #define DCO_SOFT_RESET__FMT5_SOFT_RESET__SHIFT 0x00000015 5089*b843c749SSergey Zigachev #define DCO_SOFT_RESET__MVP_SOFT_RESET_MASK 0x01000000L 5090*b843c749SSergey Zigachev #define DCO_SOFT_RESET__MVP_SOFT_RESET__SHIFT 0x00000018 5091*b843c749SSergey Zigachev #define DCO_SOFT_RESET__SOFT_RESET_DVO_MASK 0x00000004L 5092*b843c749SSergey Zigachev #define DCO_SOFT_RESET__SOFT_RESET_DVO__SHIFT 0x00000002 5093*b843c749SSergey Zigachev #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE_MASK 0x10000000L 5094*b843c749SSergey Zigachev #define DCO_SOFT_RESET__SRBM_SOFT_RESET_ENABLE__SHIFT 0x0000001c 5095*b843c749SSergey Zigachev #define DCO_SOFT_RESET__TVOUT_SOFT_RESET_MASK 0x04000000L 5096*b843c749SSergey Zigachev #define DCO_SOFT_RESET__TVOUT_SOFT_RESET__SHIFT 0x0000001a 5097*b843c749SSergey Zigachev #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL_MASK 0x0000000fL 5098*b843c749SSergey Zigachev #define DC_PAD_EXTERN_SIG__DC_PAD_EXTERN_SIG_SEL__SHIFT 0x00000000 5099*b843c749SSergey Zigachev #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS_MASK 0x00000030L 5100*b843c749SSergey Zigachev #define DC_PAD_EXTERN_SIG__MVP_PIXEL_SRC_STATUS__SHIFT 0x00000004 5101*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_ENABLE_MASK 0x00000001L 5102*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_ENABLE__SHIFT 0x00000000 5103*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL_MASK 0x00000300L 5104*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_LINE_SEL__SHIFT 0x00000008 5105*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL_MASK 0x0000001cL 5106*b843c749SSergey Zigachev #define DCP_CRC_CONTROL__DCP_CRC_SOURCE_SEL__SHIFT 0x00000002 5107*b843c749SSergey Zigachev #define DCP_CRC_CURRENT__DCP_CRC_CURRENT_MASK 0xffffffffL 5108*b843c749SSergey Zigachev #define DCP_CRC_CURRENT__DCP_CRC_CURRENT__SHIFT 0x00000000 5109*b843c749SSergey Zigachev #define DCP_CRC_LAST__DCP_CRC_LAST_MASK 0xffffffffL 5110*b843c749SSergey Zigachev #define DCP_CRC_LAST__DCP_CRC_LAST__SHIFT 0x00000000 5111*b843c749SSergey Zigachev #define DCP_CRC_MASK__DCP_CRC_MASK_MASK 0xffffffffL 5112*b843c749SSergey Zigachev #define DCP_CRC_MASK__DCP_CRC_MASK__SHIFT 0x00000000 5113*b843c749SSergey Zigachev #define DCP_DEBUG2__DCP_DEBUG2_MASK 0xffffffffL 5114*b843c749SSergey Zigachev #define DCP_DEBUG2__DCP_DEBUG2__SHIFT 0x00000000 5115*b843c749SSergey Zigachev #define DCP_DEBUG__DCP_DEBUG_MASK 0xffffffffL 5116*b843c749SSergey Zigachev #define DCP_DEBUG__DCP_DEBUG__SHIFT 0x00000000 5117*b843c749SSergey Zigachev #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA_MASK 0x0003ffffL 5118*b843c749SSergey Zigachev #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_DATA__SHIFT 0x00000000 5119*b843c749SSergey Zigachev #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX_MASK 0x07f00000L 5120*b843c749SSergey Zigachev #define DCP_FP_CONVERTED_FIELD__DCP_FP_CONVERTED_FIELD_INDEX__SHIFT 0x00000014 5121*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG_MASK 0xffff0000L 5122*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__DCPG_ECO_DEBUG__SHIFT 0x00000010 5123*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS_MASK 0x00000004L 5124*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__IPREQ_IGNORE_STATUS__SHIFT 0x00000002 5125*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY_MASK 0x00000001L 5126*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_BUSY__SHIFT 0x00000000 5127*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE_MASK 0x00000002L 5128*b843c749SSergey Zigachev #define DC_PGCNTL_STATUS_REG__SWREQ_RWOP_FORCE__SHIFT 0x00000001 5129*b843c749SSergey Zigachev #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG_MASK 0xffffffffL 5130*b843c749SSergey Zigachev #define DC_PGFSM_CONFIG_REG__PGFSM_CONFIG_REG__SHIFT 0x00000000 5131*b843c749SSergey Zigachev #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG_MASK 0xffffffffL 5132*b843c749SSergey Zigachev #define DC_PGFSM_WRITE_REG__PGFSM_WRITE_REG__SHIFT 0x00000000 5133*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL0_EN_MASK 0x00000001L 5134*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL0_EN__SHIFT 0x00000000 5135*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL1_EN_MASK 0x00000002L 5136*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL1_EN__SHIFT 0x00000001 5137*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL2_EN_MASK 0x00000004L 5138*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL2_EN__SHIFT 0x00000002 5139*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_MASK 0x08000000L 5140*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_DELAY_SURFACE_UPDATE_PENDING__SHIFT 0x0000001b 5141*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY_MASK 0xf0000000L 5142*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_CHECK_DELAY__SHIFT 0x0000001c 5143*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY_MASK 0x0000f000L 5144*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_HSYNC_FLIP_FORCE_DELAY__SHIFT 0x0000000c 5145*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN_MASK 0x00010000L 5146*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_MASTER_EN__SHIFT 0x00000010 5147*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_MODE_MASK 0x00000300L 5148*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_MODE__SHIFT 0x00000008 5149*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE_MASK 0x03000000L 5150*b843c749SSergey Zigachev #define DCP_GSL_CONTROL__DCP_GSL_SYNC_SOURCE__SHIFT 0x00000018 5151*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA_MASK 0xffffffffL 5152*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_DATA__DCPG_TEST_DEBUG_DATA__SHIFT 0x00000000 5153*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 5154*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 5155*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5156*b843c749SSergey Zigachev #define DCPG_TEST_DEBUG_INDEX__DCPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5157*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO_MASK 0x0000c000L 5158*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_AUDIO__SHIFT 0x0000000e 5159*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS_MASK 0x00000400L 5160*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_BIF_CEC_DIS__SHIFT 0x0000000a 5161*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS_MASK 0x00010000L 5162*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_CCBYPASS__SHIFT 0x00000010 5163*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD_MASK 0x00002000L 5164*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_SMS_EN_HARD__SHIFT 0x0000000d 5165*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE_MASK 0x00000800L 5166*b843c749SSergey Zigachev #define DC_PINSTRAPS__DC_PINSTRAPS_VIP_DEVICE__SHIFT 0x0000000b 5167*b843c749SSergey Zigachev #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP_MASK 0x0000000fL 5168*b843c749SSergey Zigachev #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_20BPP__SHIFT 0x00000000 5169*b843c749SSergey Zigachev #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP_MASK 0x000000f0L 5170*b843c749SSergey Zigachev #define DCP_LB_DATA_GAP_BETWEEN_CHUNK__DCP_LB_GAP_BETWEEN_CHUNK_30BPP__SHIFT 0x00000004 5171*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED_MASK 0x00ff0000L 5172*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_B_SEED__SHIFT 0x00000010 5173*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED_MASK 0x0000ff00L 5174*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_G_SEED__SHIFT 0x00000008 5175*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED_MASK 0x000000ffL 5176*b843c749SSergey Zigachev #define DCP_RANDOM_SEEDS__DCP_RAND_R_SEED__SHIFT 0x00000000 5177*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE_MASK 0x00000100L 5178*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_FRAME_RANDOM_ENABLE__SHIFT 0x00000008 5179*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE_MASK 0x00000400L 5180*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000a 5181*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE_MASK 0x00000200L 5182*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_RGB_RANDOM_ENABLE__SHIFT 0x00000009 5183*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH_MASK 0x00000040L 5184*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_DEPTH__SHIFT 0x00000006 5185*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN_MASK 0x00000001L 5186*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_EN__SHIFT 0x00000000 5187*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE_MASK 0x00000030L 5188*b843c749SSergey Zigachev #define DCP_SPATIAL_DITHER_CNTL__DCP_SPATIAL_DITHER_MODE__SHIFT 0x00000004 5189*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA_MASK 0xffffffffL 5190*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_DATA__DCP_TEST_DEBUG_DATA__SHIFT 0x00000000 5191*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX_MASK 0x000000ffL 5192*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_INDEX__SHIFT 0x00000000 5193*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5194*b843c749SSergey Zigachev #define DCP_TEST_DEBUG_INDEX__DCP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5195*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY_MASK 0x00000007L 5196*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_DELAY__SHIFT 0x00000000 5197*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5198*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT0_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5199*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY_MASK 0x00000070L 5200*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_DELAY__SHIFT 0x00000004 5201*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5202*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT1_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5203*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY_MASK 0x00000700L 5204*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_DELAY__SHIFT 0x00000008 5205*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS_MASK 0x00000800L 5206*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT2_RDWR_TIMEOUT_DIS__SHIFT 0x0000000b 5207*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY_MASK 0x00007000L 5208*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_DELAY__SHIFT 0x0000000c 5209*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS_MASK 0x00008000L 5210*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT3_RDWR_TIMEOUT_DIS__SHIFT 0x0000000f 5211*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY_MASK 0x00070000L 5212*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_DELAY__SHIFT 0x00000010 5213*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS_MASK 0x00080000L 5214*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL1__DC_RBBMIF_CLIENT4_RDWR_TIMEOUT_DIS__SHIFT 0x00000013 5215*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY_MASK 0x00000007L 5216*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_DELAY__SHIFT 0x00000000 5217*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS_MASK 0x00000008L 5218*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT8_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 5219*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY_MASK 0x00000070L 5220*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_DELAY__SHIFT 0x00000004 5221*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS_MASK 0x00000080L 5222*b843c749SSergey Zigachev #define DC_RBBMIF_RDWR_CNTL2__DC_RBBMIF_CLIENT9_RDWR_TIMEOUT_DIS__SHIFT 0x00000007 5223*b843c749SSergey Zigachev #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL_MASK 0x00000300L 5224*b843c749SSergey Zigachev #define DC_REF_CLK_CNTL__GENLK_CLK_OUTPUT_SEL__SHIFT 0x00000008 5225*b843c749SSergey Zigachev #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL_MASK 0x00000003L 5226*b843c749SSergey Zigachev #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 5227*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP_MASK 0x00400000L 5228*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__DC_FLIP_PENDING_TO_DCP__SHIFT 0x00000016 5229*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING_MASK 0x00010000L 5230*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__DC_XDMA_FLIP_PENDING__SHIFT 0x00000010 5231*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP_MASK 0x00100000L 5232*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_M_FLIP_PENDING_TO_DCP__SHIFT 0x00000014 5233*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE_MASK 0x0000003fL 5234*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_ENABLE__SHIFT 0x00000000 5235*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL_MASK 0x00000700L 5236*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_PIPE_SEL__SHIFT 0x00000008 5237*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP_MASK 0x00200000L 5238*b843c749SSergey Zigachev #define DC_XDMA_INTERFACE_CNTL__XDMA_S_FLIP_PENDING_TO_DCP__SHIFT 0x00000015 5239*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE_MASK 0x00003000L 5240*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT 0x0000000c 5241*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE_MASK 0x00000003L 5242*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT 0x00000000 5243*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE_MASK 0x00000030L 5244*b843c749SSergey Zigachev #define DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT 0x00000004 5245*b843c749SSergey Zigachev #define DENORM_CONTROL__DENORM_MODE_MASK 0x00000007L 5246*b843c749SSergey Zigachev #define DENORM_CONTROL__DENORM_MODE__SHIFT 0x00000000 5247*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE_MASK 0x00080000L 5248*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x00000013 5249*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE_MASK 0x00018000L 5250*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0x0000000f 5251*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG_MASK 0x00020000L 5252*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x00000011 5253*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG_MASK 0x00040000L 5254*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x00000012 5255*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER_MASK 0x00007f00L 5256*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x00000008 5257*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER_MASK 0x0000007fL 5258*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x00000000 5259*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE_MASK 0x00100000L 5260*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHG_DONE__SHIFT 0x00000014 5261*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG_MASK 0x00200000L 5262*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_CHGTOG__SHIFT 0x00000015 5263*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG_MASK 0x00400000L 5264*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_DONETOG__SHIFT 0x00000016 5265*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER_MASK 0x7f000000L 5266*b843c749SSergey Zigachev #define DENTIST_DISPCLK_CNTL__DENTIST_DPREFCLK_WDIVIDER__SHIFT 0x00000018 5267*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT_MASK 0x00003f00L 5268*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_FE_SOURCE_SELECT__SHIFT 0x00000008 5269*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_HPD_SELECT_MASK 0x70000000L 5270*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_HPD_SELECT__SHIFT 0x0000001c 5271*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_MODE_MASK 0x00070000L 5272*b843c749SSergey Zigachev #define DIG_BE_CNTL__DIG_MODE__SHIFT 0x00000010 5273*b843c749SSergey Zigachev #define DIG_BE_EN_CNTL__DIG_ENABLE_MASK 0x00000001L 5274*b843c749SSergey Zigachev #define DIG_BE_EN_CNTL__DIG_ENABLE__SHIFT 0x00000000 5275*b843c749SSergey Zigachev #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON_MASK 0x00000100L 5276*b843c749SSergey Zigachev #define DIG_BE_EN_CNTL__DIG_SYMCLK_BE_ON__SHIFT 0x00000008 5277*b843c749SSergey Zigachev #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN_MASK 0x000003ffL 5278*b843c749SSergey Zigachev #define DIG_CLOCK_PATTERN__DIG_CLOCK_PATTERN__SHIFT 0x00000000 5279*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT_MASK 0x00000001L 5280*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_CNTL__DIG_DISPCLK_SWITCH_POINT__SHIFT 0x00000000 5281*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK_MASK 0x00000100L 5282*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK__SHIFT 0x00000008 5283*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK 0x00000010L 5284*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK_MASK 0x00001000L 5285*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK__SHIFT 0x0000000c 5286*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_INT__SHIFT 0x00000004 5287*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED_MASK 0x00000001L 5288*b843c749SSergey Zigachev #define DIG_DISPCLK_SWITCH_STATUS__DIG_DISPCLK_SWITCH_ALLOWED__SHIFT 0x00000000 5289*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE_MASK 0x00010000L 5290*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_DUAL_LINK_ENABLE__SHIFT 0x00000010 5291*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_RB_SWITCH_EN_MASK 0x00100000L 5292*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_RB_SWITCH_EN__SHIFT 0x00000014 5293*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SOURCE_SELECT_MASK 0x00000007L 5294*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SOURCE_SELECT__SHIFT 0x00000000 5295*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_START_MASK 0x00000400L 5296*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_START__SHIFT 0x0000000a 5297*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN_MASK 0x00000100L 5298*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_STEREOSYNC_GATE_EN__SHIFT 0x00000008 5299*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT_MASK 0x00000070L 5300*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_STEREOSYNC_SELECT__SHIFT 0x00000004 5301*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SWAP_MASK 0x00040000L 5302*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SWAP__SHIFT 0x00000012 5303*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON_MASK 0x01000000L 5304*b843c749SSergey Zigachev #define DIG_FE_CNTL__DIG_SYMCLK_FE_ON__SHIFT 0x00000018 5305*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 5306*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 5307*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED_MASK 0x20000000L 5308*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_CALIBRATED__SHIFT 0x0000001d 5309*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK_MASK 0x00000100L 5310*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_ERROR_ACK__SHIFT 0x00000008 5311*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 5312*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 5313*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 5314*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 5315*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR_MASK 0x00000001L 5316*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_LEVEL_ERROR__SHIFT 0x00000000 5317*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL_MASK 0x001f0000L 5318*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 5319*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 5320*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 5321*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 5322*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 5323*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 5324*b843c749SSergey Zigachev #define DIG_FIFO_STATUS__DIG_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 5325*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_CLK_EN_MASK 0x00000100L 5326*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_CLK_EN__SHIFT 0x00000008 5327*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE0EN_MASK 0x00000001L 5328*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE0EN__SHIFT 0x00000000 5329*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE1EN_MASK 0x00000002L 5330*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE1EN__SHIFT 0x00000001 5331*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE2EN_MASK 0x00000004L 5332*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE2EN__SHIFT 0x00000002 5333*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE3EN_MASK 0x00000008L 5334*b843c749SSergey Zigachev #define DIG_LANE_ENABLE__DIG_LANE3EN__SHIFT 0x00000003 5335*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL_MASK 0x00000300L 5336*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_DATA_SEL__SHIFT 0x00000008 5337*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN_MASK 0x00000001L 5338*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_EN__SHIFT 0x00000000 5339*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL_MASK 0x00000010L 5340*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_CNTL__DIG_OUTPUT_CRC_LINK_SEL__SHIFT 0x00000004 5341*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT_MASK 0x3fffffffL 5342*b843c749SSergey Zigachev #define DIG_OUTPUT_CRC_RESULT__DIG_OUTPUT_CRC_RESULT__SHIFT 0x00000000 5343*b843c749SSergey Zigachev #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED_MASK 0x00ffffffL 5344*b843c749SSergey Zigachev #define DIG_RANDOM_PATTERN_SEED__DIG_RANDOM_PATTERN_SEED__SHIFT 0x00000000 5345*b843c749SSergey Zigachev #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY_MASK 0x01000000L 5346*b843c749SSergey Zigachev #define DIG_RANDOM_PATTERN_SEED__DIG_RAN_PAT_DURING_DE_ONLY__SHIFT 0x00000018 5347*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET_MASK 0x00000002L 5348*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGA_BE_SOFT_RESET__SHIFT 0x00000001 5349*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET_MASK 0x00000001L 5350*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGA_FE_SOFT_RESET__SHIFT 0x00000000 5351*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET_MASK 0x00000020L 5352*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGB_BE_SOFT_RESET__SHIFT 0x00000005 5353*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET_MASK 0x00000010L 5354*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGB_FE_SOFT_RESET__SHIFT 0x00000004 5355*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET_MASK 0x00000200L 5356*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGC_BE_SOFT_RESET__SHIFT 0x00000009 5357*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET_MASK 0x00000100L 5358*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGC_FE_SOFT_RESET__SHIFT 0x00000008 5359*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET_MASK 0x00002000L 5360*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGD_BE_SOFT_RESET__SHIFT 0x0000000d 5361*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET_MASK 0x00001000L 5362*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGD_FE_SOFT_RESET__SHIFT 0x0000000c 5363*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET_MASK 0x00020000L 5364*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGE_BE_SOFT_RESET__SHIFT 0x00000011 5365*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET_MASK 0x00010000L 5366*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGE_FE_SOFT_RESET__SHIFT 0x00000010 5367*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET_MASK 0x00200000L 5368*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGF_BE_SOFT_RESET__SHIFT 0x00000015 5369*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET_MASK 0x00100000L 5370*b843c749SSergey Zigachev #define DIG_SOFT_RESET__DIGF_FE_SOFT_RESET__SHIFT 0x00000014 5371*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL_MASK 0x00000002L 5372*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_HALF_CLOCK_PATTERN_SEL__SHIFT 0x00000001 5373*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN_MASK 0x00000010L 5374*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_OUT_EN__SHIFT 0x00000004 5375*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET_MASK 0x00000020L 5376*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_RANDOM_PATTERN_RESET__SHIFT 0x00000005 5377*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN_MASK 0x03ff0000L 5378*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_STATIC_TEST_PATTERN__SHIFT 0x00000010 5379*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN_MASK 0x00000040L 5380*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_EXTERNAL_RESET_EN__SHIFT 0x00000006 5381*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN_MASK 0x00000001L 5382*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__DIG_TEST_PATTERN_OUT_EN__SHIFT 0x00000000 5383*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN_MASK 0x00000100L 5384*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__LVDS_EYE_PATTERN__SHIFT 0x00000008 5385*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA_MASK 0x00000004L 5386*b843c749SSergey Zigachev #define DIG_TEST_PATTERN__LVDS_TEST_CLOCK_DATA__SHIFT 0x00000002 5387*b843c749SSergey Zigachev #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 5388*b843c749SSergey Zigachev #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_OFF_DELAY__SHIFT 0x00000004 5389*b843c749SSergey Zigachev #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY_MASK 0x0000000fL 5390*b843c749SSergey Zigachev #define DISPCLK_CGTT_BLK_CTRL_REG__DISPCLK_TURN_ON_DELAY__SHIFT 0x00000000 5391*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN_MASK 0x40000000L 5392*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_OVR_EN__SHIFT 0x0000001e 5393*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET_MASK 0x10000000L 5394*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_RESET__SHIFT 0x0000001c 5395*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE_MASK 0x20000000L 5396*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DCCG_FIFO_ERRDET_STATE__SHIFT 0x0000001d 5397*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE_MASK 0x80000000L 5398*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_CHG_FWD_CORR_DISABLE__SHIFT 0x0000001f 5399*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE_MASK 0x00100000L 5400*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_FREQ_RAMP_DONE__SHIFT 0x00000014 5401*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES_MASK 0x0e000000L 5402*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_MAX_ERRDET_CYCLES__SHIFT 0x00000019 5403*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY_MASK 0x00003fffL 5404*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_DELAY__SHIFT 0x00000000 5405*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE_MASK 0x000f0000L 5406*b843c749SSergey Zigachev #define DISPCLK_FREQ_CHANGE_CNTL__DISPCLK_STEP_SIZE__SHIFT 0x00000010 5407*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_MASK 0x40000000L 5408*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT__SHIFT 0x0000001e 5409*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT_MASK 0x10000000L 5410*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_HG_READY_INT__SHIFT 0x0000001c 5411*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT_MASK 0x20000000L 5412*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__ABM1_LS_READY_INT__SHIFT 0x0000001d 5413*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT_MASK 0x00100000L 5414*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__AUX1_LS_DONE_INTERRUPT__SHIFT 0x00000014 5415*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT_MASK 0x00080000L 5416*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__AUX1_SW_DONE_INTERRUPT__SHIFT 0x00000013 5417*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT_MASK 0x00100000L 5418*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_LS_DONE_INTERRUPT__SHIFT 0x00000014 5419*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT_MASK 0x00080000L 5420*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__AUX3_SW_DONE_INTERRUPT__SHIFT 0x00000013 5421*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5422*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5423*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5424*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5425*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5426*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5427*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5428*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5429*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT_MASK 0x00000080L 5430*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGA_INTERRUPT__SHIFT 0x00000007 5431*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT_MASK 0x00000100L 5432*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_TRIGB_INTERRUPT__SHIFT 0x00000008 5433*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5434*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__CRTC3_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5435*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 0x00020000L 5436*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT__SHIFT 0x00000011 5437*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT_MASK 0x00040000L 5438*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_RX_INTERRUPT__SHIFT 0x00000012 5439*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5440*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5441*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5442*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DIGC_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5443*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3_MASK 0x80000000L 5444*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__DISP_INTERRUPT_STATUS_CONTINUE3__SHIFT 0x0000001f 5445*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK 0x00000008L 5446*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT__SHIFT 0x00000003 5447*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK 0x00000004L 5448*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT__SHIFT 0x00000002 5449*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5450*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE2__SCL_DISP3_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5451*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT_MASK 0x00100000L 5452*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_LS_DONE_INTERRUPT__SHIFT 0x00000014 5453*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT_MASK 0x00080000L 5454*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__AUX4_SW_DONE_INTERRUPT__SHIFT 0x00000013 5455*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5456*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5457*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5458*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5459*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5460*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5461*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5462*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5463*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT_MASK 0x00000080L 5464*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGA_INTERRUPT__SHIFT 0x00000007 5465*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT_MASK 0x00000100L 5466*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_TRIGB_INTERRUPT__SHIFT 0x00000008 5467*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5468*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__CRTC4_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5469*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 0x00020000L 5470*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT__SHIFT 0x00000011 5471*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT_MASK 0x00040000L 5472*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_RX_INTERRUPT__SHIFT 0x00000012 5473*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5474*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5475*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5476*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DIGD_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5477*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4_MASK 0x80000000L 5478*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__DISP_INTERRUPT_STATUS_CONTINUE4__SHIFT 0x0000001f 5479*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK 0x00000008L 5480*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT__SHIFT 0x00000003 5481*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK 0x00000004L 5482*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT__SHIFT 0x00000002 5483*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5484*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE3__SCL_DISP4_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5485*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT_MASK 0x00100000L 5486*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_LS_DONE_INTERRUPT__SHIFT 0x00000014 5487*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT_MASK 0x00080000L 5488*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__AUX5_SW_DONE_INTERRUPT__SHIFT 0x00000013 5489*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5490*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5491*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5492*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5493*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5494*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5495*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5496*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5497*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT_MASK 0x00000080L 5498*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGA_INTERRUPT__SHIFT 0x00000007 5499*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT_MASK 0x00000100L 5500*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_TRIGB_INTERRUPT__SHIFT 0x00000008 5501*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5502*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__CRTC5_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5503*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 0x00020000L 5504*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT__SHIFT 0x00000011 5505*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT_MASK 0x00040000L 5506*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_RX_INTERRUPT__SHIFT 0x00000012 5507*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5508*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5509*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5510*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DIGE_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5511*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5_MASK 0x80000000L 5512*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__DISP_INTERRUPT_STATUS_CONTINUE5__SHIFT 0x0000001f 5513*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK 0x00000008L 5514*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT__SHIFT 0x00000003 5515*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK 0x00000004L 5516*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT__SHIFT 0x00000002 5517*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5518*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE4__SCL_DISP5_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5519*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT_MASK 0x00100000L 5520*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_LS_DONE_INTERRUPT__SHIFT 0x00000014 5521*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT_MASK 0x00080000L 5522*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__AUX6_SW_DONE_INTERRUPT__SHIFT 0x00000013 5523*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5524*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5525*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5526*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5527*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5528*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5529*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5530*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5531*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT_MASK 0x00000080L 5532*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGA_INTERRUPT__SHIFT 0x00000007 5533*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT_MASK 0x00000100L 5534*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_TRIGB_INTERRUPT__SHIFT 0x00000008 5535*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5536*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__CRTC6_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5537*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 0x00020000L 5538*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT__SHIFT 0x00000011 5539*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT_MASK 0x00040000L 5540*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_RX_INTERRUPT__SHIFT 0x00000012 5541*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5542*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5543*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5544*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__DIGF_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5545*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK 0x00000008L 5546*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT__SHIFT 0x00000003 5547*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK 0x00000004L 5548*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT__SHIFT 0x00000002 5549*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5550*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE5__SCL_DISP6_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5551*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT_MASK 0x00100000L 5552*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_LS_DONE_INTERRUPT__SHIFT 0x00000014 5553*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT_MASK 0x00080000L 5554*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__AUX2_SW_DONE_INTERRUPT__SHIFT 0x00000013 5555*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5556*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5557*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5558*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5559*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5560*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5561*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5562*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5563*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT_MASK 0x00000080L 5564*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGA_INTERRUPT__SHIFT 0x00000007 5565*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT_MASK 0x00000100L 5566*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_TRIGB_INTERRUPT__SHIFT 0x00000008 5567*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5568*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__CRTC2_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5569*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 0x00020000L 5570*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT__SHIFT 0x00000011 5571*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT_MASK 0x00040000L 5572*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_RX_INTERRUPT__SHIFT 0x00000012 5573*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5574*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5575*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5576*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DIGB_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5577*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2_MASK 0x80000000L 5578*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_INTERRUPT_STATUS_CONTINUE2__SHIFT 0x0000001f 5579*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT_MASK 0x01000000L 5580*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__DISP_TIMER_INTERRUPT__SHIFT 0x00000018 5581*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK 0x00000008L 5582*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT__SHIFT 0x00000003 5583*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK 0x00000004L 5584*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT__SHIFT 0x00000002 5585*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5586*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS_CONTINUE__SCL_DISP2_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5587*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT_MASK 0x00000040L 5588*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_COUNT_NOW_INTERRUPT__SHIFT 0x00000006 5589*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT_MASK 0x00000020L 5590*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_FORCE_VSYNC_NEXT_LINE_INTERRUPT__SHIFT 0x00000005 5591*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT_MASK 0x00000400L 5592*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_SET_V_TOTAL_MIN_EVENT_OCCURED_INT__SHIFT 0x0000000a 5593*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT_MASK 0x00000010L 5594*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_SNAPSHOT_INTERRUPT__SHIFT 0x00000004 5595*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT_MASK 0x00000080L 5596*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_TRIGA_INTERRUPT__SHIFT 0x00000007 5597*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT_MASK 0x00000100L 5598*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_TRIGB_INTERRUPT__SHIFT 0x00000008 5599*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT_MASK 0x00000200L 5600*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__CRTC1_VSYNC_NOM_INTERRUPT__SHIFT 0x00000009 5601*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT_MASK 0x00400000L 5602*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DACA_AUTODETECT_INTERRUPT__SHIFT 0x00000016 5603*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT_MASK 0x00800000L 5604*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DACB_AUTODETECT_INTERRUPT__SHIFT 0x00000017 5605*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 0x00020000L 5606*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT__SHIFT 0x00000011 5607*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT_MASK 0x00040000L 5608*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_HPD1_RX_INTERRUPT__SHIFT 0x00000012 5609*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT_MASK 0x02000000L 5610*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_I2C_HW_DONE_INTERRUPT__SHIFT 0x00000019 5611*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT_MASK 0x01000000L 5612*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DC_I2C_SW_DONE_INTERRUPT__SHIFT 0x00000018 5613*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT_MASK 0x00200000L 5614*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DISPCLK_SWITCH_ALLOWED_INTERRUPT__SHIFT 0x00000015 5615*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT_MASK 0x00008000L 5616*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT__SHIFT 0x0000000f 5617*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT_MASK 0x00010000L 5618*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DIGA_DP_VID_STREAM_DISABLE_INTERRUPT__SHIFT 0x00000010 5619*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE_MASK 0x80000000L 5620*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DISP_INTERRUPT_STATUS_CONTINUE__SHIFT 0x0000001f 5621*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT_MASK 0x08000000L 5622*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DMCU_SCP_INT__SHIFT 0x0000001b 5623*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT_MASK 0x04000000L 5624*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__DMCU_UC_INTERNAL_INT__SHIFT 0x0000001a 5625*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK 0x00000008L 5626*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT__SHIFT 0x00000003 5627*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK 0x00000004L 5628*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT__SHIFT 0x00000002 5629*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT_MASK 0x00000001L 5630*b843c749SSergey Zigachev #define DISP_INTERRUPT_STATUS__SCL_DISP1_MODE_CHANGE_INTERRUPT__SHIFT 0x00000000 5631*b843c749SSergey Zigachev #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL_MASK 0x00000007L 5632*b843c749SSergey Zigachev #define DISPOUT_STEREOSYNC_SEL__GENERICA_STEREOSYNC_SEL__SHIFT 0x00000000 5633*b843c749SSergey Zigachev #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL_MASK 0x00070000L 5634*b843c749SSergey Zigachev #define DISPOUT_STEREOSYNC_SEL__GENERICB_STEREOSYNC_SEL__SHIFT 0x00000010 5635*b843c749SSergey Zigachev #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ_MASK 0x000000f0L 5636*b843c749SSergey Zigachev #define DISPPLL_BG_CNTL__DISPPLL_BG_ADJ__SHIFT 0x00000004 5637*b843c749SSergey Zigachev #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN_MASK 0x00000001L 5638*b843c749SSergey Zigachev #define DISPPLL_BG_CNTL__DISPPLL_BG_PDN__SHIFT 0x00000000 5639*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT_MASK 0x01ffffffL 5640*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_COUNT__SHIFT 0x00000000 5641*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE_MASK 0x02000000L 5642*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_ENABLE__SHIFT 0x00000019 5643*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MASK 0x40000000L 5644*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK_MASK 0x08000000L 5645*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_MSK__SHIFT 0x0000001b 5646*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING_MASK 0x04000000L 5647*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_RUNNING__SHIFT 0x0000001a 5648*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT__SHIFT 0x0000001e 5649*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK_MASK 0x20000000L 5650*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_AK__SHIFT 0x0000001d 5651*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT_MASK 0x10000000L 5652*b843c749SSergey Zigachev #define DISP_TIMER_CONTROL__DISP_TIMER_INT_STAT__SHIFT 0x0000001c 5653*b843c749SSergey Zigachev #define DMCU_CTRL__DISABLE_IRQ_TO_UC_MASK 0x00000004L 5654*b843c749SSergey Zigachev #define DMCU_CTRL__DISABLE_IRQ_TO_UC__SHIFT 0x00000002 5655*b843c749SSergey Zigachev #define DMCU_CTRL__DISABLE_XIRQ_TO_UC_MASK 0x00000008L 5656*b843c749SSergey Zigachev #define DMCU_CTRL__DISABLE_XIRQ_TO_UC__SHIFT 0x00000003 5657*b843c749SSergey Zigachev #define DMCU_CTRL__DMCU_ENABLE_MASK 0x00000010L 5658*b843c749SSergey Zigachev #define DMCU_CTRL__DMCU_ENABLE__SHIFT 0x00000004 5659*b843c749SSergey Zigachev #define DMCU_CTRL__IGNORE_PWRMGT_MASK 0x00000002L 5660*b843c749SSergey Zigachev #define DMCU_CTRL__IGNORE_PWRMGT__SHIFT 0x00000001 5661*b843c749SSergey Zigachev #define DMCU_CTRL__RESET_UC_MASK 0x00000001L 5662*b843c749SSergey Zigachev #define DMCU_CTRL__RESET_UC__SHIFT 0x00000000 5663*b843c749SSergey Zigachev #define DMCU_CTRL__UC_REG_RD_TIMEOUT_MASK 0xffc00000L 5664*b843c749SSergey Zigachev #define DMCU_CTRL__UC_REG_RD_TIMEOUT__SHIFT 0x00000016 5665*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR_MASK 0x0000ffffL 5666*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_ADDR__SHIFT 0x00000000 5667*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE_MASK 0x000f0000L 5668*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_BE__SHIFT 0x00000010 5669*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE_MASK 0x00100000L 5670*b843c749SSergey Zigachev #define DMCU_ERAM_RD_CTRL__ERAM_RD_BYTE_MODE__SHIFT 0x00000014 5671*b843c749SSergey Zigachev #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA_MASK 0xffffffffL 5672*b843c749SSergey Zigachev #define DMCU_ERAM_RD_DATA__ERAM_RD_DATA__SHIFT 0x00000000 5673*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR_MASK 0x0000ffffL 5674*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_ADDR__SHIFT 0x00000000 5675*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE_MASK 0x000f0000L 5676*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_BE__SHIFT 0x00000010 5677*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE_MASK 0x00100000L 5678*b843c749SSergey Zigachev #define DMCU_ERAM_WR_CTRL__ERAM_WR_BYTE_MODE__SHIFT 0x00000014 5679*b843c749SSergey Zigachev #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA_MASK 0xffffffffL 5680*b843c749SSergey Zigachev #define DMCU_ERAM_WR_DATA__ERAM_WR_DATA__SHIFT 0x00000000 5681*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC_MASK 0x00000001L 5682*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__GEN_SW_INT_TO_UC__SHIFT 0x00000000 5683*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST_MASK 0x00800000L 5684*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__GEN_UC_INTERNAL_INT_TO_HOST__SHIFT 0x00000017 5685*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE_MASK 0x007f0000L 5686*b843c749SSergey Zigachev #define DMCU_EVENT_TRIGGER__UC_INTERNAL_INT_CODE__SHIFT 0x00000010 5687*b843c749SSergey Zigachev #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS_MASK 0x0000000cL 5688*b843c749SSergey Zigachev #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_HI_SMPL_BYTE_POS__SHIFT 0x00000002 5689*b843c749SSergey Zigachev #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS_MASK 0x00000003L 5690*b843c749SSergey Zigachev #define DMCU_FW_CHECKSUM_SMPL_BYTE_POS__DMCU_FW_CHECKSUM_LO_SMPL_BYTE_POS__SHIFT 0x00000000 5691*b843c749SSergey Zigachev #define DMCU_FW_CS_HI__FW_CHECKSUM_HI_MASK 0xffffffffL 5692*b843c749SSergey Zigachev #define DMCU_FW_CS_HI__FW_CHECKSUM_HI__SHIFT 0x00000000 5693*b843c749SSergey Zigachev #define DMCU_FW_CS_LO__FW_CHECKSUM_LO_MASK 0xffffffffL 5694*b843c749SSergey Zigachev #define DMCU_FW_CS_LO__FW_CHECKSUM_LO__SHIFT 0x00000000 5695*b843c749SSergey Zigachev #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB_MASK 0x000000ffL 5696*b843c749SSergey Zigachev #define DMCU_FW_END_ADDR__FW_END_ADDR_LSB__SHIFT 0x00000000 5697*b843c749SSergey Zigachev #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB_MASK 0x0000ff00L 5698*b843c749SSergey Zigachev #define DMCU_FW_END_ADDR__FW_END_ADDR_MSB__SHIFT 0x00000008 5699*b843c749SSergey Zigachev #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB_MASK 0x000000ffL 5700*b843c749SSergey Zigachev #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_LSB__SHIFT 0x00000000 5701*b843c749SSergey Zigachev #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB_MASK 0x0000ff00L 5702*b843c749SSergey Zigachev #define DMCU_FW_ISR_START_ADDR__FW_ISR_START_ADDR_MSB__SHIFT 0x00000008 5703*b843c749SSergey Zigachev #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB_MASK 0x000000ffL 5704*b843c749SSergey Zigachev #define DMCU_FW_START_ADDR__FW_START_ADDR_LSB__SHIFT 0x00000000 5705*b843c749SSergey Zigachev #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB_MASK 0x0000ff00L 5706*b843c749SSergey Zigachev #define DMCU_FW_START_ADDR__FW_START_ADDR_MSB__SHIFT 0x00000008 5707*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT_MASK 0x00ff0000L 5708*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_BL_UPDATE_INT_CNT__SHIFT 0x00000010 5709*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT_MASK 0x000000ffL 5710*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_HG_READY_INT_CNT__SHIFT 0x00000000 5711*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT_MASK 0x0000ff00L 5712*b843c749SSergey Zigachev #define DMCU_INT_CNT__DMCU_ABM1_LS_READY_INT_CNT__SHIFT 0x00000008 5713*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR_MASK 0x00000004L 5714*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_CLEAR__SHIFT 0x00000002 5715*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED_MASK 0x00000004L 5716*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_BL_UPDATE_INT_OCCURRED__SHIFT 0x00000002 5717*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR_MASK 0x00000001L 5718*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_CLEAR__SHIFT 0x00000000 5719*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED_MASK 0x00000001L 5720*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_HG_READY_INT_OCCURRED__SHIFT 0x00000000 5721*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR_MASK 0x00000002L 5722*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_CLEAR__SHIFT 0x00000001 5723*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED_MASK 0x00000002L 5724*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__ABM1_LS_READY_INT_OCCURRED__SHIFT 0x00000001 5725*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR_MASK 0x00040000L 5726*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_CLEAR__SHIFT 0x00000012 5727*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED_MASK 0x00040000L 5728*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000012 5729*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR_MASK 0x00001000L 5730*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_CLEAR__SHIFT 0x0000000c 5731*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED_MASK 0x00001000L 5732*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE0_POWER_UP_INT_OCCURRED__SHIFT 0x0000000c 5733*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR_MASK 0x00080000L 5734*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_CLEAR__SHIFT 0x00000013 5735*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED_MASK 0x00080000L 5736*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000013 5737*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR_MASK 0x00002000L 5738*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_CLEAR__SHIFT 0x0000000d 5739*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED_MASK 0x00002000L 5740*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE1_POWER_UP_INT_OCCURRED__SHIFT 0x0000000d 5741*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR_MASK 0x00100000L 5742*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_CLEAR__SHIFT 0x00000014 5743*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED_MASK 0x00100000L 5744*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000014 5745*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR_MASK 0x00004000L 5746*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_CLEAR__SHIFT 0x0000000e 5747*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED_MASK 0x00004000L 5748*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE2_POWER_UP_INT_OCCURRED__SHIFT 0x0000000e 5749*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR_MASK 0x00200000L 5750*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_CLEAR__SHIFT 0x00000015 5751*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED_MASK 0x00200000L 5752*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000015 5753*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR_MASK 0x00008000L 5754*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_CLEAR__SHIFT 0x0000000f 5755*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED_MASK 0x00008000L 5756*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE3_POWER_UP_INT_OCCURRED__SHIFT 0x0000000f 5757*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR_MASK 0x00400000L 5758*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_CLEAR__SHIFT 0x00000016 5759*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED_MASK 0x00400000L 5760*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000016 5761*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR_MASK 0x00010000L 5762*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_CLEAR__SHIFT 0x00000010 5763*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED_MASK 0x00010000L 5764*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE4_POWER_UP_INT_OCCURRED__SHIFT 0x00000010 5765*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR_MASK 0x00800000L 5766*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_CLEAR__SHIFT 0x00000017 5767*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED_MASK 0x00800000L 5768*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_DOWN_INT_OCCURRED__SHIFT 0x00000017 5769*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR_MASK 0x00020000L 5770*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_CLEAR__SHIFT 0x00000011 5771*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED_MASK 0x00020000L 5772*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__DCPG_IHC_DCFE5_POWER_UP_INT_OCCURRED__SHIFT 0x00000011 5773*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR_MASK 0x00000100L 5774*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_CLEAR__SHIFT 0x00000008 5775*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED_MASK 0x00000100L 5776*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__EXTERNAL_SW_INT_OCCURRED__SHIFT 0x00000008 5777*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED_MASK 0x00000008L 5778*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__MCP_INT_OCCURRED__SHIFT 0x00000003 5779*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED_MASK 0x00000200L 5780*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__SCP_INT_OCCURRED__SHIFT 0x00000009 5781*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR_MASK 0x00000400L 5782*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_CLEAR__SHIFT 0x0000000a 5783*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED_MASK 0x00000400L 5784*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_INTERNAL_INT_OCCURRED__SHIFT 0x0000000a 5785*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR_MASK 0x00000800L 5786*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_CLEAR__SHIFT 0x0000000b 5787*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED_MASK 0x00000800L 5788*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__UC_REG_RD_TIMEOUT_INT_OCCURRED__SHIFT 0x0000000b 5789*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR_MASK 0x01000000L 5790*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_CLEAR__SHIFT 0x00000018 5791*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED_MASK 0x01000000L 5792*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK1_INT_OCCURRED__SHIFT 0x00000018 5793*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR_MASK 0x02000000L 5794*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_CLEAR__SHIFT 0x00000019 5795*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED_MASK 0x02000000L 5796*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK2_INT_OCCURRED__SHIFT 0x00000019 5797*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR_MASK 0x04000000L 5798*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_CLEAR__SHIFT 0x0000001a 5799*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED_MASK 0x04000000L 5800*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK3_INT_OCCURRED__SHIFT 0x0000001a 5801*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR_MASK 0x08000000L 5802*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_CLEAR__SHIFT 0x0000001b 5803*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED_MASK 0x08000000L 5804*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK4_INT_OCCURRED__SHIFT 0x0000001b 5805*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR_MASK 0x10000000L 5806*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_CLEAR__SHIFT 0x0000001c 5807*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED_MASK 0x10000000L 5808*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK5_INT_OCCURRED__SHIFT 0x0000001c 5809*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR_MASK 0x20000000L 5810*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_CLEAR__SHIFT 0x0000001d 5811*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED_MASK 0x20000000L 5812*b843c749SSergey Zigachev #define DMCU_INTERRUPT_STATUS__VBLANK6_INT_OCCURRED__SHIFT 0x0000001d 5813*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK_MASK 0x00000004L 5814*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_BL_UPDATE_INT_MASK__SHIFT 0x00000002 5815*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK_MASK 0x00000001L 5816*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_HG_READY_INT_MASK__SHIFT 0x00000000 5817*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK_MASK 0x00000002L 5818*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__ABM1_LS_READY_INT_MASK__SHIFT 0x00000001 5819*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK_MASK 0x00040000L 5820*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_MASK__SHIFT 0x00000012 5821*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK_MASK 0x00001000L 5822*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_MASK__SHIFT 0x0000000c 5823*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK_MASK 0x00080000L 5824*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_MASK__SHIFT 0x00000013 5825*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK_MASK 0x00002000L 5826*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_MASK__SHIFT 0x0000000d 5827*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK_MASK 0x00100000L 5828*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_MASK__SHIFT 0x00000014 5829*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK_MASK 0x00004000L 5830*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_MASK__SHIFT 0x0000000e 5831*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK_MASK 0x00200000L 5832*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_MASK__SHIFT 0x00000015 5833*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK_MASK 0x00008000L 5834*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_MASK__SHIFT 0x0000000f 5835*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK_MASK 0x00400000L 5836*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_MASK__SHIFT 0x00000016 5837*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK_MASK 0x00010000L 5838*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_MASK__SHIFT 0x00000010 5839*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK_MASK 0x00800000L 5840*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_MASK__SHIFT 0x00000017 5841*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK_MASK 0x00020000L 5842*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_MASK__SHIFT 0x00000011 5843*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK_MASK 0x00000200L 5844*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__SCP_INT_MASK__SHIFT 0x00000009 5845*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK_MASK 0x00000400L 5846*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_INTERNAL_INT_MASK__SHIFT 0x0000000a 5847*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK_MASK 0x00000800L 5848*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_HOST_EN_MASK__UC_REG_RD_TIMEOUT_INT_MASK__SHIFT 0x0000000b 5849*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN_MASK 0x00000004L 5850*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_BL_UPDATE_INT_TO_UC_EN__SHIFT 0x00000002 5851*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN_MASK 0x00000001L 5852*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_HG_READY_INT_TO_UC_EN__SHIFT 0x00000000 5853*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN_MASK 0x00000002L 5854*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__ABM1_LS_READY_INT_TO_UC_EN__SHIFT 0x00000001 5855*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN_MASK 0x00040000L 5856*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000012 5857*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN_MASK 0x00001000L 5858*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE0_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000c 5859*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN_MASK 0x00080000L 5860*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000013 5861*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN_MASK 0x00002000L 5862*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE1_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000d 5863*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN_MASK 0x00100000L 5864*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000014 5865*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN_MASK 0x00004000L 5866*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE2_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000e 5867*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN_MASK 0x00200000L 5868*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000015 5869*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN_MASK 0x00008000L 5870*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE3_POWER_UP_INT_TO_UC_EN__SHIFT 0x0000000f 5871*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN_MASK 0x00400000L 5872*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000016 5873*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN_MASK 0x00010000L 5874*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE4_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000010 5875*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN_MASK 0x00800000L 5876*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_DOWN_INT_TO_UC_EN__SHIFT 0x00000017 5877*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN_MASK 0x00020000L 5878*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__DCPG_IHC_DCFE5_POWER_UP_INT_TO_UC_EN__SHIFT 0x00000011 5879*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN_MASK 0x00000100L 5880*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__EXTERNAL_SW_INT_TO_UC_EN__SHIFT 0x00000008 5881*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN_MASK 0x00000008L 5882*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__MCP_INT_TO_UC_EN__SHIFT 0x00000003 5883*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN_MASK 0x01000000L 5884*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK1_INT_TO_UC_EN__SHIFT 0x00000018 5885*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN_MASK 0x02000000L 5886*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK2_INT_TO_UC_EN__SHIFT 0x00000019 5887*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN_MASK 0x04000000L 5888*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK3_INT_TO_UC_EN__SHIFT 0x0000001a 5889*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN_MASK 0x08000000L 5890*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK4_INT_TO_UC_EN__SHIFT 0x0000001b 5891*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN_MASK 0x10000000L 5892*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK5_INT_TO_UC_EN__SHIFT 0x0000001c 5893*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN_MASK 0x20000000L 5894*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_EN_MASK__VBLANK6_INT_TO_UC_EN__SHIFT 0x0000001d 5895*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL_MASK 0x00000004L 5896*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_BL_UPDATE_INT_XIRQ_IRQ_SEL__SHIFT 0x00000002 5897*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000001L 5898*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_HG_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000000 5899*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL_MASK 0x00000002L 5900*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__ABM1_LS_READY_INT_XIRQ_IRQ_SEL__SHIFT 0x00000001 5901*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00040000L 5902*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000012 5903*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00001000L 5904*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE0_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000c 5905*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00080000L 5906*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000013 5907*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00002000L 5908*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE1_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000d 5909*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00100000L 5910*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000014 5911*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00004000L 5912*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE2_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000e 5913*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00200000L 5914*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000015 5915*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00008000L 5916*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE3_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x0000000f 5917*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00400000L 5918*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000016 5919*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00010000L 5920*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE4_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000010 5921*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL_MASK 0x00800000L 5922*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_DOWN_INT_XIRQ_IRQ_SEL__SHIFT 0x00000017 5923*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL_MASK 0x00020000L 5924*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__DCPG_IHC_DCFE5_POWER_UP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000011 5925*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL_MASK 0x00000100L 5926*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__EXTERNAL_SW_INT_XIRQ_IRQ_SEL__SHIFT 0x00000008 5927*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL_MASK 0x00000008L 5928*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__MCP_INT_XIRQ_IRQ_SEL__SHIFT 0x00000003 5929*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL_MASK 0x01000000L 5930*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK1_INT_XIRQ_IRQ_SEL__SHIFT 0x00000018 5931*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL_MASK 0x02000000L 5932*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK2_INT_XIRQ_IRQ_SEL__SHIFT 0x00000019 5933*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL_MASK 0x04000000L 5934*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK3_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001a 5935*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL_MASK 0x08000000L 5936*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK4_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001b 5937*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL_MASK 0x10000000L 5938*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK5_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001c 5939*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL_MASK 0x20000000L 5940*b843c749SSergey Zigachev #define DMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL__VBLANK6_INT_XIRQ_IRQ_SEL__SHIFT 0x0000001d 5941*b843c749SSergey Zigachev #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR_MASK 0x000003ffL 5942*b843c749SSergey Zigachev #define DMCU_IRAM_RD_CTRL__IRAM_RD_ADDR__SHIFT 0x00000000 5943*b843c749SSergey Zigachev #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA_MASK 0x000000ffL 5944*b843c749SSergey Zigachev #define DMCU_IRAM_RD_DATA__IRAM_RD_DATA__SHIFT 0x00000000 5945*b843c749SSergey Zigachev #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR_MASK 0x000003ffL 5946*b843c749SSergey Zigachev #define DMCU_IRAM_WR_CTRL__IRAM_WR_ADDR__SHIFT 0x00000000 5947*b843c749SSergey Zigachev #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA_MASK 0x000000ffL 5948*b843c749SSergey Zigachev #define DMCU_IRAM_WR_DATA__IRAM_WR_DATA__SHIFT 0x00000000 5949*b843c749SSergey Zigachev #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB_MASK 0x000000ffL 5950*b843c749SSergey Zigachev #define DMCU_PC_START_ADDR__PC_START_ADDR_LSB__SHIFT 0x00000000 5951*b843c749SSergey Zigachev #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB_MASK 0x0000ff00L 5952*b843c749SSergey Zigachev #define DMCU_PC_START_ADDR__PC_START_ADDR_MSB__SHIFT 0x00000008 5953*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN_MASK 0x00000010L 5954*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_HOST_ACCESS_EN__SHIFT 0x00000004 5955*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC_MASK 0x00000002L 5956*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_RD_ADDR_AUTO_INC__SHIFT 0x00000001 5957*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC_MASK 0x00000001L 5958*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__ERAM_WR_ADDR_AUTO_INC__SHIFT 0x00000000 5959*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN_MASK 0x00000020L 5960*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_HOST_ACCESS_EN__SHIFT 0x00000005 5961*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC_MASK 0x00000008L 5962*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_RD_ADDR_AUTO_INC__SHIFT 0x00000003 5963*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC_MASK 0x00000004L 5964*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__IRAM_WR_ADDR_AUTO_INC__SHIFT 0x00000002 5965*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT_MASK 0x0000ff00L 5966*b843c749SSergey Zigachev #define DMCU_RAM_ACCESS_CTRL__UC_RST_RELEASE_DELAY_CNT__SHIFT 0x00000008 5967*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_RESET_MASK 0x00000001L 5968*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_RESET__SHIFT 0x00000000 5969*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_STOP_MODE_MASK 0x00000004L 5970*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_STOP_MODE__SHIFT 0x00000002 5971*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_WAIT_MODE_MASK 0x00000002L 5972*b843c749SSergey Zigachev #define DMCU_STATUS__UC_IN_WAIT_MODE__SHIFT 0x00000001 5973*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA_MASK 0xffffffffL 5974*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_DATA__DMCU_TEST_DEBUG_DATA__SHIFT 0x00000000 5975*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX_MASK 0x000000ffL 5976*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_INDEX__SHIFT 0x00000000 5977*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 5978*b843c749SSergey Zigachev #define DMCU_TEST_DEBUG_INDEX__DMCU_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 5979*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY_MASK 0x00000700L 5980*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_ERAM_RD_DELAY__SHIFT 0x00000008 5981*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY_MASK 0x00000007L 5982*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_IRAM_RD_DELAY__SHIFT 0x00000000 5983*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN_MASK 0x00010000L 5984*b843c749SSergey Zigachev #define DMCU_UC_CLK_GATING_CNTL__UC_RBBM_RD_CLK_GATING_EN__SHIFT 0x00000010 5985*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP_MASK 0x00000008L 5986*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_ILLEGAL_OPCODE_TRAP__SHIFT 0x00000003 5987*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN_MASK 0x00000001L 5988*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_IRQ_N_PIN__SHIFT 0x00000000 5989*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE_MASK 0x00004000L 5990*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_INPUT_EDGE__SHIFT 0x0000000e 5991*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW_MASK 0x00008000L 5992*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_PULSE_ACCUMULATOR_OVERFLOW__SHIFT 0x0000000f 5993*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT_MASK 0x00000200L 5994*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_REAL_TIME_INTERRUPT__SHIFT 0x00000009 5995*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT_MASK 0x00000004L 5996*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_SOFTWARE_INTERRUPT__SHIFT 0x00000002 5997*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1_MASK 0x00002000L 5998*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_1__SHIFT 0x0000000d 5999*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2_MASK 0x00001000L 6000*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_2__SHIFT 0x0000000c 6001*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3_MASK 0x00000800L 6002*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_3__SHIFT 0x0000000b 6003*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5_MASK 0x00000400L 6004*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_INPUT_CAPTURE_4_OUTPUT_COMPARE_5__SHIFT 0x0000000a 6005*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1_MASK 0x00000080L 6006*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_1__SHIFT 0x00000007 6007*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2_MASK 0x00000040L 6008*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_2__SHIFT 0x00000006 6009*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3_MASK 0x00000020L 6010*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_3__SHIFT 0x00000005 6011*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4_MASK 0x00000010L 6012*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OUTPUT_COMPARE_4__SHIFT 0x00000004 6013*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW_MASK 0x00000100L 6014*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_TIMER_OVERFLOW__SHIFT 0x00000008 6015*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN_MASK 0x00000002L 6016*b843c749SSergey Zigachev #define DMCU_UC_INTERNAL_INT_STATUS__UC_INT_XIRQ_N_PIN__SHIFT 0x00000001 6017*b843c749SSergey Zigachev #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6018*b843c749SSergey Zigachev #define DMIF_ADDR_CALC__ADDR_CONFIG_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6019*b843c749SSergey Zigachev #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE_MASK 0x30000000L 6020*b843c749SSergey Zigachev #define DMIF_ADDR_CALC__ADDR_CONFIG_ROW_SIZE__SHIFT 0x0000001c 6021*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 6022*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x00000008 6023*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 6024*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x0000001e 6025*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 6026*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x00000000 6027*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00003000L 6028*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x0000000c 6029*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000070L 6030*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x00000004 6031*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 6032*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x0000001c 6033*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 6034*b843c749SSergey Zigachev #define DMIF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x00000010 6035*b843c749SSergey Zigachev #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD_MASK 0x0000ffffL 6036*b843c749SSergey Zigachev #define DMIF_ARBITRATION_CONTROL__DMIF_ARBITRATION_REFERENCE_CLOCK_PERIOD__SHIFT 0x00000000 6037*b843c749SSergey Zigachev #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT_MASK 0xffff0000L 6038*b843c749SSergey Zigachev #define DMIF_ARBITRATION_CONTROL__PIPE_SWITCH_EFFICIENCY_WEIGHT__SHIFT 0x00000010 6039*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_BUFF_SIZE_MASK 0x00000003L 6040*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_BUFF_SIZE__SHIFT 0x00000000 6041*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN_MASK 0x60000000L 6042*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_CHUNK_BUFF_MARGIN__SHIFT 0x0000001d 6043*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION_MASK 0x1f000000L 6044*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_DELAY_ARBITRATION__SHIFT 0x00000018 6045*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT_MASK 0x00000010L 6046*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_DISABLE_EARLY_RECEIVED_LEVEL_COUNT__SHIFT 0x00000004 6047*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE_MASK 0x0000f000L 6048*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_FORCE_TOTAL_REQ_BURST_SIZE__SHIFT 0x0000000c 6049*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK_MASK 0x00000004L 6050*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_GROUP_REQUESTS_IN_CHUNK__SHIFT 0x00000002 6051*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS_MASK 0x003f0000L 6052*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_MAX_TOTAL_OUTSTANDING_CHUNK_REQUESTS__SHIFT 0x00000010 6053*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE_MASK 0x00000700L 6054*b843c749SSergey Zigachev #define DMIF_CONTROL__DMIF_REQ_BURST_SIZE__SHIFT 0x00000008 6055*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__DB_DATA_MASK 0x0000ffffL 6056*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__DB_DATA__SHIFT 0x00000000 6057*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN_MASK 0x00010000L 6058*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6059*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6060*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE0__MC_RDRET_COUNTER__SHIFT 0x00000011 6061*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__DB_DATA_MASK 0x0000ffffL 6062*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__DB_DATA__SHIFT 0x00000000 6063*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN_MASK 0x00010000L 6064*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNT_EN__SHIFT 0x00000010 6065*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER_MASK 0x0ffe0000L 6066*b843c749SSergey Zigachev #define DMIF_DEBUG02_CORE1__MC_RDRET_COUNTER__SHIFT 0x00000011 6067*b843c749SSergey Zigachev #define DMIF_HW_DEBUG__DMIF_HW_DEBUG_MASK 0xffffffffL 6068*b843c749SSergey Zigachev #define DMIF_HW_DEBUG__DMIF_HW_DEBUG__SHIFT 0x00000000 6069*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS_MASK 0x00000100L 6070*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_CHUNK_TRACKER_SCLK_STATUS__SHIFT 0x00000008 6071*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS_MASK 0x00000200L 6072*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_FBC_TRACKER_SCLK_STATUS__SHIFT 0x00000009 6073*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS_MASK 0x00000001L 6074*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE0_DISPCLK_STATUS__SHIFT 0x00000000 6075*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS_MASK 0x00000002L 6076*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE1_DISPCLK_STATUS__SHIFT 0x00000001 6077*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS_MASK 0x00000004L 6078*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE2_DISPCLK_STATUS__SHIFT 0x00000002 6079*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS_MASK 0x00000008L 6080*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE3_DISPCLK_STATUS__SHIFT 0x00000003 6081*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS_MASK 0x00000010L 6082*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE4_DISPCLK_STATUS__SHIFT 0x00000004 6083*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS_MASK 0x00000020L 6084*b843c749SSergey Zigachev #define DMIF_STATUS2__DMIF_PIPE5_DISPCLK_STATUS__SHIFT 0x00000005 6085*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE_MASK 0x00003f00L 6086*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_CLEAR_MC_SEND_ON_IDLE__SHIFT 0x00000008 6087*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x00010000L 6088*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x00000010 6089*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT_MASK 0x00700000L 6090*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_SOURCE_SELECT__SHIFT 0x00000014 6091*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x00020000L 6092*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x00000011 6093*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE_MASK 0x0000003fL 6094*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_MC_SEND_ON_IDLE__SHIFT 0x00000000 6095*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT_MASK 0x07000000L 6096*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_PERFORMANCE_COUNTER_SOURCE_SELECT__SHIFT 0x00000018 6097*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_UNDERFLOW_MASK 0x10000000L 6098*b843c749SSergey Zigachev #define DMIF_STATUS__DMIF_UNDERFLOW__SHIFT 0x0000001c 6099*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA_MASK 0xffffffffL 6100*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_DATA__DMIF_TEST_DEBUG_DATA__SHIFT 0x00000000 6101*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 6102*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 6103*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6104*b843c749SSergey Zigachev #define DMIF_TEST_DEBUG_INDEX__DMIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6105*b843c749SSergey Zigachev #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT_MASK 0x00000070L 6106*b843c749SSergey Zigachev #define DOUT_DCE_VCE_CONTROL__DC_VCE_AUDIO_STREAM_SELECT__SHIFT 0x00000004 6107*b843c749SSergey Zigachev #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT_MASK 0x00000007L 6108*b843c749SSergey Zigachev #define DOUT_DCE_VCE_CONTROL__DC_VCE_VIDEO_PIPE_SELECT__SHIFT 0x00000000 6109*b843c749SSergey Zigachev #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF_MASK 0x00000100L 6110*b843c749SSergey Zigachev #define DOUT_POWER_MANAGEMENT_CNTL__PM_ALL_BUSY_OFF__SHIFT 0x00000008 6111*b843c749SSergey Zigachev #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET_MASK 0x00000001L 6112*b843c749SSergey Zigachev #define DOUT_POWER_MANAGEMENT_CNTL__PM_ASSERT_RESET__SHIFT 0x00000000 6113*b843c749SSergey Zigachev #define DOUT_SCRATCH0__DOUT_SCRATCH0_MASK 0xffffffffL 6114*b843c749SSergey Zigachev #define DOUT_SCRATCH0__DOUT_SCRATCH0__SHIFT 0x00000000 6115*b843c749SSergey Zigachev #define DOUT_SCRATCH1__DOUT_SCRATCH1_MASK 0xffffffffL 6116*b843c749SSergey Zigachev #define DOUT_SCRATCH1__DOUT_SCRATCH1__SHIFT 0x00000000 6117*b843c749SSergey Zigachev #define DOUT_SCRATCH2__DOUT_SCRATCH2_MASK 0xffffffffL 6118*b843c749SSergey Zigachev #define DOUT_SCRATCH2__DOUT_SCRATCH2__SHIFT 0x00000000 6119*b843c749SSergey Zigachev #define DOUT_SCRATCH3__DOUT_SCRATCH3_MASK 0xffffffffL 6120*b843c749SSergey Zigachev #define DOUT_SCRATCH3__DOUT_SCRATCH3__SHIFT 0x00000000 6121*b843c749SSergey Zigachev #define DOUT_SCRATCH4__DOUT_SCRATCH4_MASK 0xffffffffL 6122*b843c749SSergey Zigachev #define DOUT_SCRATCH4__DOUT_SCRATCH4__SHIFT 0x00000000 6123*b843c749SSergey Zigachev #define DOUT_SCRATCH5__DOUT_SCRATCH5_MASK 0xffffffffL 6124*b843c749SSergey Zigachev #define DOUT_SCRATCH5__DOUT_SCRATCH5__SHIFT 0x00000000 6125*b843c749SSergey Zigachev #define DOUT_SCRATCH6__DOUT_SCRATCH6_MASK 0xffffffffL 6126*b843c749SSergey Zigachev #define DOUT_SCRATCH6__DOUT_SCRATCH6__SHIFT 0x00000000 6127*b843c749SSergey Zigachev #define DOUT_SCRATCH7__DOUT_SCRATCH7_MASK 0xffffffffL 6128*b843c749SSergey Zigachev #define DOUT_SCRATCH7__DOUT_SCRATCH7__SHIFT 0x00000000 6129*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA_MASK 0xffffffffL 6130*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_DATA__DOUT_TEST_DEBUG_DATA__SHIFT 0x00000000 6131*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX_MASK 0x000000ffL 6132*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_INDEX__SHIFT 0x00000000 6133*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6134*b843c749SSergey Zigachev #define DOUT_TEST_DEBUG_INDEX__DOUT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6135*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A_MASK 0xffffffffL 6136*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_A__DP_AUX1_DEBUG_A__SHIFT 0x00000000 6137*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B_MASK 0xffffffffL 6138*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_B__DP_AUX1_DEBUG_B__SHIFT 0x00000000 6139*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C_MASK 0xffffffffL 6140*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_C__DP_AUX1_DEBUG_C__SHIFT 0x00000000 6141*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D_MASK 0xffffffffL 6142*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_D__DP_AUX1_DEBUG_D__SHIFT 0x00000000 6143*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E_MASK 0xffffffffL 6144*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_E__DP_AUX1_DEBUG_E__SHIFT 0x00000000 6145*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F_MASK 0xffffffffL 6146*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_F__DP_AUX1_DEBUG_F__SHIFT 0x00000000 6147*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G_MASK 0xffffffffL 6148*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_G__DP_AUX1_DEBUG_G__SHIFT 0x00000000 6149*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H_MASK 0xffffffffL 6150*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_H__DP_AUX1_DEBUG_H__SHIFT 0x00000000 6151*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I_MASK 0xffffffffL 6152*b843c749SSergey Zigachev #define DP_AUX1_DEBUG_I__DP_AUX1_DEBUG_I__SHIFT 0x00000000 6153*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A_MASK 0xffffffffL 6154*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_A__DP_AUX2_DEBUG_A__SHIFT 0x00000000 6155*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B_MASK 0xffffffffL 6156*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_B__DP_AUX2_DEBUG_B__SHIFT 0x00000000 6157*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C_MASK 0xffffffffL 6158*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_C__DP_AUX2_DEBUG_C__SHIFT 0x00000000 6159*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D_MASK 0xffffffffL 6160*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_D__DP_AUX2_DEBUG_D__SHIFT 0x00000000 6161*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E_MASK 0xffffffffL 6162*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_E__DP_AUX2_DEBUG_E__SHIFT 0x00000000 6163*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F_MASK 0xffffffffL 6164*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_F__DP_AUX2_DEBUG_F__SHIFT 0x00000000 6165*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G_MASK 0xffffffffL 6166*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_G__DP_AUX2_DEBUG_G__SHIFT 0x00000000 6167*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H_MASK 0xffffffffL 6168*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_H__DP_AUX2_DEBUG_H__SHIFT 0x00000000 6169*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I_MASK 0xffffffffL 6170*b843c749SSergey Zigachev #define DP_AUX2_DEBUG_I__DP_AUX2_DEBUG_I__SHIFT 0x00000000 6171*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A_MASK 0xffffffffL 6172*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_A__DP_AUX3_DEBUG_A__SHIFT 0x00000000 6173*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B_MASK 0xffffffffL 6174*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_B__DP_AUX3_DEBUG_B__SHIFT 0x00000000 6175*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C_MASK 0xffffffffL 6176*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_C__DP_AUX3_DEBUG_C__SHIFT 0x00000000 6177*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D_MASK 0xffffffffL 6178*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_D__DP_AUX3_DEBUG_D__SHIFT 0x00000000 6179*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E_MASK 0xffffffffL 6180*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_E__DP_AUX3_DEBUG_E__SHIFT 0x00000000 6181*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F_MASK 0xffffffffL 6182*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_F__DP_AUX3_DEBUG_F__SHIFT 0x00000000 6183*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G_MASK 0xffffffffL 6184*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_G__DP_AUX3_DEBUG_G__SHIFT 0x00000000 6185*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H_MASK 0xffffffffL 6186*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_H__DP_AUX3_DEBUG_H__SHIFT 0x00000000 6187*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I_MASK 0xffffffffL 6188*b843c749SSergey Zigachev #define DP_AUX3_DEBUG_I__DP_AUX3_DEBUG_I__SHIFT 0x00000000 6189*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A_MASK 0xffffffffL 6190*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_A__DP_AUX4_DEBUG_A__SHIFT 0x00000000 6191*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B_MASK 0xffffffffL 6192*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_B__DP_AUX4_DEBUG_B__SHIFT 0x00000000 6193*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C_MASK 0xffffffffL 6194*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_C__DP_AUX4_DEBUG_C__SHIFT 0x00000000 6195*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D_MASK 0xffffffffL 6196*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_D__DP_AUX4_DEBUG_D__SHIFT 0x00000000 6197*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E_MASK 0xffffffffL 6198*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_E__DP_AUX4_DEBUG_E__SHIFT 0x00000000 6199*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F_MASK 0xffffffffL 6200*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_F__DP_AUX4_DEBUG_F__SHIFT 0x00000000 6201*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G_MASK 0xffffffffL 6202*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_G__DP_AUX4_DEBUG_G__SHIFT 0x00000000 6203*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H_MASK 0xffffffffL 6204*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_H__DP_AUX4_DEBUG_H__SHIFT 0x00000000 6205*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I_MASK 0xffffffffL 6206*b843c749SSergey Zigachev #define DP_AUX4_DEBUG_I__DP_AUX4_DEBUG_I__SHIFT 0x00000000 6207*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A_MASK 0xffffffffL 6208*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_A__DP_AUX5_DEBUG_A__SHIFT 0x00000000 6209*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B_MASK 0xffffffffL 6210*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_B__DP_AUX5_DEBUG_B__SHIFT 0x00000000 6211*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C_MASK 0xffffffffL 6212*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_C__DP_AUX5_DEBUG_C__SHIFT 0x00000000 6213*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D_MASK 0xffffffffL 6214*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_D__DP_AUX5_DEBUG_D__SHIFT 0x00000000 6215*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E_MASK 0xffffffffL 6216*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_E__DP_AUX5_DEBUG_E__SHIFT 0x00000000 6217*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F_MASK 0xffffffffL 6218*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_F__DP_AUX5_DEBUG_F__SHIFT 0x00000000 6219*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G_MASK 0xffffffffL 6220*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_G__DP_AUX5_DEBUG_G__SHIFT 0x00000000 6221*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H_MASK 0xffffffffL 6222*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_H__DP_AUX5_DEBUG_H__SHIFT 0x00000000 6223*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I_MASK 0xffffffffL 6224*b843c749SSergey Zigachev #define DP_AUX5_DEBUG_I__DP_AUX5_DEBUG_I__SHIFT 0x00000000 6225*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A_MASK 0xffffffffL 6226*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_A__DP_AUX6_DEBUG_A__SHIFT 0x00000000 6227*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B_MASK 0xffffffffL 6228*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_B__DP_AUX6_DEBUG_B__SHIFT 0x00000000 6229*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C_MASK 0xffffffffL 6230*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_C__DP_AUX6_DEBUG_C__SHIFT 0x00000000 6231*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D_MASK 0xffffffffL 6232*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_D__DP_AUX6_DEBUG_D__SHIFT 0x00000000 6233*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E_MASK 0xffffffffL 6234*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_E__DP_AUX6_DEBUG_E__SHIFT 0x00000000 6235*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F_MASK 0xffffffffL 6236*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_F__DP_AUX6_DEBUG_F__SHIFT 0x00000000 6237*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G_MASK 0xffffffffL 6238*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_G__DP_AUX6_DEBUG_G__SHIFT 0x00000000 6239*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H_MASK 0xffffffffL 6240*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_H__DP_AUX6_DEBUG_H__SHIFT 0x00000000 6241*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I_MASK 0xffffffffL 6242*b843c749SSergey Zigachev #define DP_AUX6_DEBUG_I__DP_AUX6_DEBUG_I__SHIFT 0x00000000 6243*b843c749SSergey Zigachev #define DP_CONFIG__DP_UDI_LANES_MASK 0x00000003L 6244*b843c749SSergey Zigachev #define DP_CONFIG__DP_UDI_LANES__SHIFT 0x00000000 6245*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP_MASK 0x01000000L 6246*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_CUR_DISP__SHIFT 0x00000018 6247*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP_MASK 0x00010000L 6248*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_EXT_DISP__SHIFT 0x00000010 6249*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET_MASK 0x00000100L 6250*b843c749SSergey Zigachev #define DP_DPHY_8B10B_CNTL__DPHY_8B10B_RESET__SHIFT 0x00000008 6251*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0_MASK 0x00000001L 6252*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE0__SHIFT 0x00000000 6253*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1_MASK 0x00000002L 6254*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE1__SHIFT 0x00000001 6255*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2_MASK 0x00000004L 6256*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE2__SHIFT 0x00000002 6257*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3_MASK 0x00000008L 6258*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_ATEST_SEL_LANE3__SHIFT 0x00000003 6259*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_BYPASS_MASK 0x00010000L 6260*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_BYPASS__SHIFT 0x00000010 6261*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS_MASK 0x01000000L 6262*b843c749SSergey Zigachev #define DP_DPHY_CNTL__DPHY_SKEW_BYPASS__SHIFT 0x00000018 6263*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD_MASK 0x00000001L 6264*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_FIELD__SHIFT 0x00000000 6265*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK_MASK 0x00ff0000L 6266*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_MASK__SHIFT 0x00000010 6267*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL_MASK 0x00000030L 6268*b843c749SSergey Zigachev #define DP_DPHY_CRC_CNTL__DPHY_CRC_SEL__SHIFT 0x00000004 6269*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN_MASK 0x00000010L 6270*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_CONT_EN__SHIFT 0x00000004 6271*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_EN_MASK 0x00000001L 6272*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_EN__SHIFT 0x00000000 6273*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID_MASK 0x00000100L 6274*b843c749SSergey Zigachev #define DP_DPHY_CRC_EN__DPHY_CRC_RESULT_VALID__SHIFT 0x00000008 6275*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT_MASK 0x0000003fL 6276*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_FIRST_SLOT__SHIFT 0x00000000 6277*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT_MASK 0x00003f00L 6278*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_CNTL__DPHY_CRC_MST_LAST_SLOT__SHIFT 0x00000008 6279*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK_MASK 0x00010000L 6280*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_ACK__SHIFT 0x00000010 6281*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR_MASK 0x00000100L 6282*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_ERROR__SHIFT 0x00000008 6283*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK_MASK 0x00000001L 6284*b843c749SSergey Zigachev #define DP_DPHY_CRC_MST_STATUS__DPHY_CRC_MST_PHASE_LOCK__SHIFT 0x00000000 6285*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1_MASK 0x0000ff00L 6286*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT1__SHIFT 0x00000008 6287*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2_MASK 0x00ff0000L 6288*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT2__SHIFT 0x00000010 6289*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3_MASK 0xff000000L 6290*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT3__SHIFT 0x00000018 6291*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT_MASK 0x000000ffL 6292*b843c749SSergey Zigachev #define DP_DPHY_CRC_RESULT__DPHY_CRC_RESULT__SHIFT 0x00000000 6293*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME_MASK 0x000fff00L 6294*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP1_TIME__SHIFT 0x00000008 6295*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME_MASK 0xfff00000L 6296*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_TP2_TIME__SHIFT 0x00000014 6297*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN_MASK 0x00000004L 6298*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN__SHIFT 0x00000002 6299*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE_MASK 0x00000001L 6300*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_RX_FAST_TRAINING_CAPABLE__SHIFT 0x00000000 6301*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START_MASK 0x00000002L 6302*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING__DPHY_SW_FAST_TRAINING_START__SHIFT 0x00000001 6303*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK_MASK 0x00001000L 6304*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_ACK__SHIFT 0x0000000c 6305*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK_MASK 0x00000100L 6306*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_MASK__SHIFT 0x00000008 6307*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED_MASK 0x00000010L 6308*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_COMPLETE_OCCURRED__SHIFT 0x00000004 6309*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE_MASK 0x00000007L 6310*b843c749SSergey Zigachev #define DP_DPHY_FAST_TRAINING_STATUS__DPHY_FAST_TRAINING_STATE__SHIFT 0x00000000 6311*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN_MASK 0x00000001L 6312*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_EN__SHIFT 0x00000000 6313*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED_MASK 0x7fffff00L 6314*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEED__SHIFT 0x00000008 6315*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL_MASK 0x00000030L 6316*b843c749SSergey Zigachev #define DP_DPHY_PRBS_CNTL__DPHY_PRBS_SEL__SHIFT 0x00000004 6317*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM1_MASK 0x000003ffL 6318*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM1__SHIFT 0x00000000 6319*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM2_MASK 0x000ffc00L 6320*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM2__SHIFT 0x0000000a 6321*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM3_MASK 0x3ff00000L 6322*b843c749SSergey Zigachev #define DP_DPHY_SYM0__DPHY_SYM3__SHIFT 0x00000014 6323*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM4_MASK 0x000003ffL 6324*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM4__SHIFT 0x00000000 6325*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM5_MASK 0x000ffc00L 6326*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM5__SHIFT 0x0000000a 6327*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM6_MASK 0x3ff00000L 6328*b843c749SSergey Zigachev #define DP_DPHY_SYM1__DPHY_SYM6__SHIFT 0x00000014 6329*b843c749SSergey Zigachev #define DP_DPHY_SYM2__DPHY_SYM7_MASK 0x000003ffL 6330*b843c749SSergey Zigachev #define DP_DPHY_SYM2__DPHY_SYM7__SHIFT 0x00000000 6331*b843c749SSergey Zigachev #define DP_DPHY_SYM2__DPHY_SYM8_MASK 0x000ffc00L 6332*b843c749SSergey Zigachev #define DP_DPHY_SYM2__DPHY_SYM8__SHIFT 0x0000000a 6333*b843c749SSergey Zigachev #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL_MASK 0x00000003L 6334*b843c749SSergey Zigachev #define DP_DPHY_TRAINING_PATTERN_SEL__DPHY_TRAINING_PATTERN_SEL__SHIFT 0x00000000 6335*b843c749SSergey Zigachev #define DP_DTO0_MODULO__DP_DTO0_MODULO_MASK 0xffffffffL 6336*b843c749SSergey Zigachev #define DP_DTO0_MODULO__DP_DTO0_MODULO__SHIFT 0x00000000 6337*b843c749SSergey Zigachev #define DP_DTO0_PHASE__DP_DTO0_PHASE_MASK 0xffffffffL 6338*b843c749SSergey Zigachev #define DP_DTO0_PHASE__DP_DTO0_PHASE__SHIFT 0x00000000 6339*b843c749SSergey Zigachev #define DP_DTO1_MODULO__DP_DTO1_MODULO_MASK 0xffffffffL 6340*b843c749SSergey Zigachev #define DP_DTO1_MODULO__DP_DTO1_MODULO__SHIFT 0x00000000 6341*b843c749SSergey Zigachev #define DP_DTO1_PHASE__DP_DTO1_PHASE_MASK 0xffffffffL 6342*b843c749SSergey Zigachev #define DP_DTO1_PHASE__DP_DTO1_PHASE__SHIFT 0x00000000 6343*b843c749SSergey Zigachev #define DP_DTO2_MODULO__DP_DTO2_MODULO_MASK 0xffffffffL 6344*b843c749SSergey Zigachev #define DP_DTO2_MODULO__DP_DTO2_MODULO__SHIFT 0x00000000 6345*b843c749SSergey Zigachev #define DP_DTO2_PHASE__DP_DTO2_PHASE_MASK 0xffffffffL 6346*b843c749SSergey Zigachev #define DP_DTO2_PHASE__DP_DTO2_PHASE__SHIFT 0x00000000 6347*b843c749SSergey Zigachev #define DP_DTO3_MODULO__DP_DTO3_MODULO_MASK 0xffffffffL 6348*b843c749SSergey Zigachev #define DP_DTO3_MODULO__DP_DTO3_MODULO__SHIFT 0x00000000 6349*b843c749SSergey Zigachev #define DP_DTO3_PHASE__DP_DTO3_PHASE_MASK 0xffffffffL 6350*b843c749SSergey Zigachev #define DP_DTO3_PHASE__DP_DTO3_PHASE__SHIFT 0x00000000 6351*b843c749SSergey Zigachev #define DP_DTO4_MODULO__DP_DTO4_MODULO_MASK 0xffffffffL 6352*b843c749SSergey Zigachev #define DP_DTO4_MODULO__DP_DTO4_MODULO__SHIFT 0x00000000 6353*b843c749SSergey Zigachev #define DP_DTO4_PHASE__DP_DTO4_PHASE_MASK 0xffffffffL 6354*b843c749SSergey Zigachev #define DP_DTO4_PHASE__DP_DTO4_PHASE__SHIFT 0x00000000 6355*b843c749SSergey Zigachev #define DP_DTO5_MODULO__DP_DTO5_MODULO_MASK 0xffffffffL 6356*b843c749SSergey Zigachev #define DP_DTO5_MODULO__DP_DTO5_MODULO__SHIFT 0x00000000 6357*b843c749SSergey Zigachev #define DP_DTO5_PHASE__DP_DTO5_PHASE_MASK 0xffffffffL 6358*b843c749SSergey Zigachev #define DP_DTO5_PHASE__DP_DTO5_PHASE__SHIFT 0x00000000 6359*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT_MASK 0xffff0000L 6360*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL1__BASE_WEIGHT__SHIFT 0x00000010 6361*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION_MASK 0x0000ffffL 6362*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL1__PIXEL_DURATION__SHIFT 0x00000000 6363*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT_MASK 0x0000ffffL 6364*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL2__TIME_WEIGHT__SHIFT 0x00000000 6365*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT_MASK 0xffff0000L 6366*b843c749SSergey Zigachev #define DPG_PIPE_ARBITRATION_CONTROL2__URGENCY_WEIGHT__SHIFT 0x00000010 6367*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE_MASK 0x00000001L 6368*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__DPM_ENABLE__SHIFT 0x00000000 6369*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE_MASK 0x00000010L 6370*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_ENABLE__SHIFT 0x00000004 6371*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON_MASK 0x00000100L 6372*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_FORCE_ON__SHIFT 0x00000008 6373*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK 0xffff0000L 6374*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK_MASK 0x00003000L 6375*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK_MASK__SHIFT 0x0000000c 6376*b843c749SSergey Zigachev #define DPG_PIPE_DPM_CONTROL__MCLK_CHANGE_WATERMARK__SHIFT 0x00000010 6377*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT_MASK 0x00000400L 6378*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_ALLOW_FOR_URGENT__SHIFT 0x0000000a 6379*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE_MASK 0x00000001L 6380*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_ENABLE__SHIFT 0x00000000 6381*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON_MASK 0x00000200L 6382*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_FORCE_ON__SHIFT 0x00000009 6383*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST_MASK 0x00000100L 6384*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST__SHIFT 0x00000008 6385*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST_MASK 0x00000010L 6386*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_URGENT_DURING_REQUEST__SHIFT 0x00000004 6387*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK_MASK 0xffff0000L 6388*b843c749SSergey Zigachev #define DPG_PIPE_NB_PSTATE_CHANGE_CONTROL__NB_PSTATE_CHANGE_WATERMARK__SHIFT 0x00000010 6389*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH_MASK 0x00000001L 6390*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_ENABLE_NONLPTCH__SHIFT 0x00000000 6391*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH_MASK 0x00000010L 6392*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_CURSOR_NONLPTCH__SHIFT 0x00000004 6393*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH_MASK 0x00000080L 6394*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_FBC_NONLPTCH__SHIFT 0x00000007 6395*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH_MASK 0x00000020L 6396*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_ICON_NONLPTCH__SHIFT 0x00000005 6397*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH_MASK 0x00000040L 6398*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_IGNORE_VGA_NONLPTCH__SHIFT 0x00000006 6399*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH_MASK 0x00000800L 6400*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_SELF_REFRESH_FORCE_ON_NONLPTCH__SHIFT 0x0000000b 6401*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH_MASK 0x00000400L 6402*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_URGENT_IN_NOT_SELF_REFRESH_NONLPTCH__SHIFT 0x0000000a 6403*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH_MASK 0x00000200L 6404*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_EXCLUDES_VBLANK_NONLPTCH__SHIFT 0x00000009 6405*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH_MASK 0x00000100L 6406*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL_NONLPTCH__STUTTER_WM_HIGH_FORCE_ON_NONLPTCH__SHIFT 0x00000008 6407*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE_MASK 0x00000001L 6408*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_ENABLE__SHIFT 0x00000000 6409*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK 0xffff0000L 6410*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_EXIT_SELF_REFRESH_WATERMARK__SHIFT 0x00000010 6411*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR_MASK 0x00000010L 6412*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_CURSOR__SHIFT 0x00000004 6413*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC_MASK 0x00000080L 6414*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_FBC__SHIFT 0x00000007 6415*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON_MASK 0x00000020L 6416*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_ICON__SHIFT 0x00000005 6417*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA_MASK 0x00000040L 6418*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_IGNORE_VGA__SHIFT 0x00000006 6419*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON_MASK 0x00000800L 6420*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_SELF_REFRESH_FORCE_ON__SHIFT 0x0000000b 6421*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH_MASK 0x00000400L 6422*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_URGENT_IN_NOT_SELF_REFRESH__SHIFT 0x0000000a 6423*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK_MASK 0x00000200L 6424*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_EXCLUDES_VBLANK__SHIFT 0x00000009 6425*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON_MASK 0x00000100L 6426*b843c749SSergey Zigachev #define DPG_PIPE_STUTTER_CONTROL__STUTTER_WM_HIGH_FORCE_ON__SHIFT 0x00000008 6427*b843c749SSergey Zigachev #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK_MASK 0xffff0000L 6428*b843c749SSergey Zigachev #define DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT 0x00000010 6429*b843c749SSergey Zigachev #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK_MASK 0x0000ffffL 6430*b843c749SSergey Zigachev #define DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT 0x00000000 6431*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA_MASK 0xffffffffL 6432*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_DATA__DPG_TEST_DEBUG_DATA__SHIFT 0x00000000 6433*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX_MASK 0x000000ffL 6434*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_INDEX__SHIFT 0x00000000 6435*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6436*b843c749SSergey Zigachev #define DPG_TEST_DEBUG_INDEX__DPG_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6437*b843c749SSergey Zigachev #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE_MASK 0x00000001L 6438*b843c749SSergey Zigachev #define DP_HBR2_EYE_PATTERN__DP_HBR2_EYE_PATTERN_ENABLE__SHIFT 0x00000000 6439*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE_MASK 0x00020000L 6440*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_EMBEDDED_PANEL_MODE__SHIFT 0x00000011 6441*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_LINK_STATUS_MASK 0x00000100L 6442*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_LINK_STATUS__SHIFT 0x00000008 6443*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE_MASK 0x00000010L 6444*b843c749SSergey Zigachev #define DP_LINK_CNTL__DP_LINK_TRAINING_COMPLETE__SHIFT 0x00000004 6445*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL_MASK 0x0003ffffL 6446*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_IDLE_BS_INTERVAL__SHIFT 0x00000000 6447*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE_MASK 0x01000000L 6448*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_VBID_DISABLE__SHIFT 0x00000018 6449*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE_MASK 0x10000000L 6450*b843c749SSergey Zigachev #define DP_LINK_FRAMING_CNTL__DP_VID_ENHANCED_FRAME_MODE__SHIFT 0x0000001c 6451*b843c749SSergey Zigachev #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE_MASK 0x00000100L 6452*b843c749SSergey Zigachev #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_ENABLE__SHIFT 0x00000008 6453*b843c749SSergey Zigachev #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE_MASK 0x000000ffL 6454*b843c749SSergey Zigachev #define DP_MSA_COLORIMETRY__DP_MSA_MISC0_OVERRIDE__SHIFT 0x00000000 6455*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC1_MASK 0x000000f8L 6456*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC1__SHIFT 0x00000003 6457*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC2_MASK 0x0000ff00L 6458*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC2__SHIFT 0x00000008 6459*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC3_MASK 0x00ff0000L 6460*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC3__SHIFT 0x00000010 6461*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC4_MASK 0xff000000L 6462*b843c749SSergey Zigachev #define DP_MSA_MISC__DP_MSA_MISC4__SHIFT 0x00000018 6463*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN_MASK 0x00000001L 6464*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TIMING_OVERRIDE_EN__SHIFT 0x00000000 6465*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE_MASK 0x0001fff0L 6466*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE1__DP_MSA_V_TOTAL_OVERRIDE__SHIFT 0x00000004 6467*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE_MASK 0x1fff0000L 6468*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_END_OVERRIDE__SHIFT 0x00000010 6469*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE_MASK 0x00001fffL 6470*b843c749SSergey Zigachev #define DP_MSA_V_TIMING_OVERRIDE2__DP_MSA_V_BLANK_START_OVERRIDE__SHIFT 0x00000000 6471*b843c749SSergey Zigachev #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME_MASK 0x000003ffL 6472*b843c749SSergey Zigachev #define DP_MSE_LINK_TIMING__DP_MSE_LINK_FRAME__SHIFT 0x00000000 6473*b843c749SSergey Zigachev #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE_MASK 0x00030000L 6474*b843c749SSergey Zigachev #define DP_MSE_LINK_TIMING__DP_MSE_LINK_LINE__SHIFT 0x00000010 6475*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE_MASK 0x00000001L 6476*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_BLANK_CODE__SHIFT 0x00000000 6477*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE_MASK 0x00000010L 6478*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_TIMESTAMP_MODE__SHIFT 0x00000004 6479*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER_MASK 0x00000100L 6480*b843c749SSergey Zigachev #define DP_MSE_MISC_CNTL__DP_MSE_ZERO_ENCODER__SHIFT 0x00000008 6481*b843c749SSergey Zigachev #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X_MASK 0xfc000000L 6482*b843c749SSergey Zigachev #define DP_MSE_RATE_CNTL__DP_MSE_RATE_X__SHIFT 0x0000001a 6483*b843c749SSergey Zigachev #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y_MASK 0x03ffffffL 6484*b843c749SSergey Zigachev #define DP_MSE_RATE_CNTL__DP_MSE_RATE_Y__SHIFT 0x00000000 6485*b843c749SSergey Zigachev #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING_MASK 0x00000001L 6486*b843c749SSergey Zigachev #define DP_MSE_RATE_UPDATE__DP_MSE_RATE_UPDATE_PENDING__SHIFT 0x00000000 6487*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0_MASK 0x00003f00L 6488*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT0__SHIFT 0x00000008 6489*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1_MASK 0x3f000000L 6490*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SLOT_COUNT1__SHIFT 0x00000018 6491*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SRC0_MASK 0x00000007L 6492*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SRC0__SHIFT 0x00000000 6493*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SRC1_MASK 0x00070000L 6494*b843c749SSergey Zigachev #define DP_MSE_SAT0__DP_MSE_SAT_SRC1__SHIFT 0x00000010 6495*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2_MASK 0x00003f00L 6496*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT2__SHIFT 0x00000008 6497*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3_MASK 0x3f000000L 6498*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SLOT_COUNT3__SHIFT 0x00000018 6499*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SRC2_MASK 0x00000007L 6500*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SRC2__SHIFT 0x00000000 6501*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SRC3_MASK 0x00070000L 6502*b843c749SSergey Zigachev #define DP_MSE_SAT1__DP_MSE_SAT_SRC3__SHIFT 0x00000010 6503*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4_MASK 0x00003f00L 6504*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT4__SHIFT 0x00000008 6505*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5_MASK 0x3f000000L 6506*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SLOT_COUNT5__SHIFT 0x00000018 6507*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SRC4_MASK 0x00000007L 6508*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SRC4__SHIFT 0x00000000 6509*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SRC5_MASK 0x00070000L 6510*b843c749SSergey Zigachev #define DP_MSE_SAT2__DP_MSE_SAT_SRC5__SHIFT 0x00000010 6511*b843c749SSergey Zigachev #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT_MASK 0x00000100L 6512*b843c749SSergey Zigachev #define DP_MSE_SAT_UPDATE__DP_MSE_16_MTP_KEEPOUT__SHIFT 0x00000008 6513*b843c749SSergey Zigachev #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE_MASK 0x00000003L 6514*b843c749SSergey Zigachev #define DP_MSE_SAT_UPDATE__DP_MSE_SAT_UPDATE__SHIFT 0x00000000 6515*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH_MASK 0x07000000L 6516*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_COMPONENT_DEPTH__SHIFT 0x00000018 6517*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_DYN_RANGE_MASK 0x00000100L 6518*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_DYN_RANGE__SHIFT 0x00000008 6519*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING_MASK 0x00000003L 6520*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_PIXEL_ENCODING__SHIFT 0x00000000 6521*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE_MASK 0x00010000L 6522*b843c749SSergey Zigachev #define DP_PIXEL_FORMAT__DP_YCBCR_RANGE__SHIFT 0x00000010 6523*b843c749SSergey Zigachev #define DP_SEC_AUD_M__DP_SEC_AUD_M_MASK 0x00ffffffL 6524*b843c749SSergey Zigachev #define DP_SEC_AUD_M__DP_SEC_AUD_M__SHIFT 0x00000000 6525*b843c749SSergey Zigachev #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK_MASK 0x00ffffffL 6526*b843c749SSergey Zigachev #define DP_SEC_AUD_M_READBACK__DP_SEC_AUD_M_READBACK__SHIFT 0x00000000 6527*b843c749SSergey Zigachev #define DP_SEC_AUD_N__DP_SEC_AUD_N_MASK 0x00ffffffL 6528*b843c749SSergey Zigachev #define DP_SEC_AUD_N__DP_SEC_AUD_N__SHIFT 0x00000000 6529*b843c749SSergey Zigachev #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK_MASK 0x00ffffffL 6530*b843c749SSergey Zigachev #define DP_SEC_AUD_N_READBACK__DP_SEC_AUD_N_READBACK__SHIFT 0x00000000 6531*b843c749SSergey Zigachev #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE_MASK 0x00000001L 6532*b843c749SSergey Zigachev #define DP_SEC_CNTL1__DP_SEC_ISRC_ENABLE__SHIFT 0x00000000 6533*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE_MASK 0x00010000L 6534*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ACM_ENABLE__SHIFT 0x00000010 6535*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE_MASK 0x00001000L 6536*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_AIP_ENABLE__SHIFT 0x0000000c 6537*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE_MASK 0x00000010L 6538*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ASP_ENABLE__SHIFT 0x00000004 6539*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE_MASK 0x00000100L 6540*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_ATP_ENABLE__SHIFT 0x00000008 6541*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE_MASK 0x01000000L 6542*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_AVI_ENABLE__SHIFT 0x00000018 6543*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE_MASK 0x00100000L 6544*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP0_ENABLE__SHIFT 0x00000014 6545*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE_MASK 0x00200000L 6546*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP1_ENABLE__SHIFT 0x00000015 6547*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE_MASK 0x00400000L 6548*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP2_ENABLE__SHIFT 0x00000016 6549*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE_MASK 0x00800000L 6550*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_GSP3_ENABLE__SHIFT 0x00000017 6551*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE_MASK 0x10000000L 6552*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_MPG_ENABLE__SHIFT 0x0000001c 6553*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE_MASK 0x00000001L 6554*b843c749SSergey Zigachev #define DP_SEC_CNTL__DP_SEC_STREAM_ENABLE__SHIFT 0x00000000 6555*b843c749SSergey Zigachev #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION_MASK 0x00000fffL 6556*b843c749SSergey Zigachev #define DP_SEC_FRAMING1__DP_SEC_FRAME_START_LOCATION__SHIFT 0x00000000 6557*b843c749SSergey Zigachev #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6558*b843c749SSergey Zigachev #define DP_SEC_FRAMING1__DP_SEC_VBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6559*b843c749SSergey Zigachev #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH_MASK 0xffff0000L 6560*b843c749SSergey Zigachev #define DP_SEC_FRAMING2__DP_SEC_HBLANK_TRANSMIT_WIDTH__SHIFT 0x00000010 6561*b843c749SSergey Zigachev #define DP_SEC_FRAMING2__DP_SEC_START_POSITION_MASK 0x0000ffffL 6562*b843c749SSergey Zigachev #define DP_SEC_FRAMING2__DP_SEC_START_POSITION__SHIFT 0x00000000 6563*b843c749SSergey Zigachev #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE_MASK 0x00003fffL 6564*b843c749SSergey Zigachev #define DP_SEC_FRAMING3__DP_SEC_IDLE_FRAME_SIZE__SHIFT 0x00000000 6565*b843c749SSergey Zigachev #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH_MASK 0xffff0000L 6566*b843c749SSergey Zigachev #define DP_SEC_FRAMING3__DP_SEC_IDLE_TRANSMIT_WIDTH__SHIFT 0x00000010 6567*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_MASK 0x10000000L 6568*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE__SHIFT 0x0000001c 6569*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS_MASK 0x20000000L 6570*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_AUDIO_MUTE_STATUS__SHIFT 0x0000001d 6571*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK_MASK 0x01000000L 6572*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_COLLISION_ACK__SHIFT 0x00000018 6573*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS_MASK 0x00100000L 6574*b843c749SSergey Zigachev #define DP_SEC_FRAMING4__DP_SEC_COLLISION_STATUS__SHIFT 0x00000014 6575*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_MASK 0x00010000L 6576*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE__SHIFT 0x00000010 6577*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE_MASK 0x0000000eL 6578*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_CODING_TYPE__SHIFT 0x00000001 6579*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY_MASK 0x00000010L 6580*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_ASP_PRIORITY__SHIFT 0x00000004 6581*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION_MASK 0x00003f00L 6582*b843c749SSergey Zigachev #define DP_SEC_PACKET_CNTL__DP_SEC_VERSION__SHIFT 0x00000008 6583*b843c749SSergey Zigachev #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE_MASK 0x00000001L 6584*b843c749SSergey Zigachev #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__SHIFT 0x00000000 6585*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_FIFO_RESET_MASK 0x00000001L 6586*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_FIFO_RESET__SHIFT 0x00000000 6587*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK_MASK 0x00000040L 6588*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_ACK__SHIFT 0x00000006 6589*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG_MASK 0x00000010L 6590*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_FLAG__SHIFT 0x00000004 6591*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT_MASK 0x00000020L 6592*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_INT__SHIFT 0x00000005 6593*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK_MASK 0x00000080L 6594*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_STEER_OVERFLOW_MASK__SHIFT 0x00000007 6595*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK_MASK 0x00001000L 6596*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_TU_OVERFLOW_ACK__SHIFT 0x0000000c 6597*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG_MASK 0x00000100L 6598*b843c749SSergey Zigachev #define DP_STEER_FIFO__DP_TU_OVERFLOW_FLAG__SHIFT 0x00000008 6599*b843c749SSergey Zigachev #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA_MASK 0xffffffffL 6600*b843c749SSergey Zigachev #define DP_TEST_DEBUG_DATA__DP_TEST_DEBUG_DATA__SHIFT 0x00000000 6601*b843c749SSergey Zigachev #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX_MASK 0x000000ffL 6602*b843c749SSergey Zigachev #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_INDEX__SHIFT 0x00000000 6603*b843c749SSergey Zigachev #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6604*b843c749SSergey Zigachev #define DP_TEST_DEBUG_INDEX__DP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6605*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK_MASK 0x00000002L 6606*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_ACK__SHIFT 0x00000001 6607*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT_MASK 0x00000001L 6608*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_INT__SHIFT 0x00000000 6609*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK_MASK 0x00000004L 6610*b843c749SSergey Zigachev #define DP_VID_INTERRUPT_CNTL__DP_VID_STREAM_DISABLE_MASK__SHIFT 0x00000002 6611*b843c749SSergey Zigachev #define DP_VID_M__DP_VID_M_MASK 0x00ffffffL 6612*b843c749SSergey Zigachev #define DP_VID_M__DP_VID_M__SHIFT 0x00000000 6613*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION_MASK 0x00000fffL 6614*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_MSA_LOCATION__SHIFT 0x00000000 6615*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE_MASK 0x00010000L 6616*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_MSA_TOP_FIELD_MODE__SHIFT 0x00000010 6617*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL_MASK 0x01000000L 6618*b843c749SSergey Zigachev #define DP_VID_MSA_VBID__DP_VID_VBID_FIELD_POL__SHIFT 0x00000018 6619*b843c749SSergey Zigachev #define DP_VID_N__DP_VID_N_MASK 0x00ffffffL 6620*b843c749SSergey Zigachev #define DP_VID_N__DP_VID_N__SHIFT 0x00000000 6621*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT_MASK 0x00100000L 6622*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_CHANGE_KEEPOUT__SHIFT 0x00000014 6623*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER_MASK 0x00000300L 6624*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_DIS_DEFER__SHIFT 0x00000008 6625*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE_MASK 0x00000001L 6626*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_ENABLE__SHIFT 0x00000000 6627*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS_MASK 0x00010000L 6628*b843c749SSergey Zigachev #define DP_VID_STREAM_CNTL__DP_VID_STREAM_STATUS__SHIFT 0x00000010 6629*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_M_N_GEN_EN_MASK 0x00000100L 6630*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_M_N_GEN_EN__SHIFT 0x00000008 6631*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_N_DIV_MASK 0xff000000L 6632*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_N_DIV__SHIFT 0x00000018 6633*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_TIMING_MODE_MASK 0x00000001L 6634*b843c749SSergey Zigachev #define DP_VID_TIMING__DP_VID_TIMING_MODE__SHIFT 0x00000000 6635*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN_MASK 0x00020000L 6636*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_COARSE_ADJUST_EN__SHIFT 0x00000011 6637*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL_MASK 0x00001f00L 6638*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_COARSE_SKEW_CNTL__SHIFT 0x00000008 6639*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN_MASK 0x00010000L 6640*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_FINE_ADJUST_EN__SHIFT 0x00000010 6641*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL_MASK 0x00000007L 6642*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_FINE_SKEW_CNTL__SHIFT 0x00000000 6643*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE_MASK 0x00040000L 6644*b843c749SSergey Zigachev #define DVOACLKC_CNTL__DVOACLKC_IN_PHASE__SHIFT 0x00000012 6645*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN_MASK 0x00020000L 6646*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_ADJUST_EN__SHIFT 0x00000011 6647*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL_MASK 0x00001f00L 6648*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_COARSE_SKEW_CNTL__SHIFT 0x00000008 6649*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN_MASK 0x00010000L 6650*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_ADJUST_EN__SHIFT 0x00000010 6651*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL_MASK 0x00000007L 6652*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_FINE_SKEW_CNTL__SHIFT 0x00000000 6653*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE_MASK 0x00040000L 6654*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_IN_PHASE__SHIFT 0x00000012 6655*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_MASK 0x00100000L 6656*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__DVOACLKC_MVP_SKEW_PHASE_OVERRIDE__SHIFT 0x00000014 6657*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL_MASK 0x03000000L 6658*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__MVP_CLK_A_SRC_SEL__SHIFT 0x00000018 6659*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL_MASK 0x30000000L 6660*b843c749SSergey Zigachev #define DVOACLKC_MVP_CNTL__MVP_CLK_B_SRC_SEL__SHIFT 0x0000001c 6661*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN_MASK 0x00020000L 6662*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_COARSE_ADJUST_EN__SHIFT 0x00000011 6663*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL_MASK 0x00001f00L 6664*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_COARSE_SKEW_CNTL__SHIFT 0x00000008 6665*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN_MASK 0x00010000L 6666*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_FINE_ADJUST_EN__SHIFT 0x00000010 6667*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL_MASK 0x00000007L 6668*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_FINE_SKEW_CNTL__SHIFT 0x00000000 6669*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE_MASK 0x00040000L 6670*b843c749SSergey Zigachev #define DVOACLKD_CNTL__DVOACLKD_IN_PHASE__SHIFT 0x00000012 6671*b843c749SSergey Zigachev #define DVO_CLK_ENABLE__DVO_CLK_ENABLE_MASK 0x00000001L 6672*b843c749SSergey Zigachev #define DVO_CLK_ENABLE__DVO_CLK_ENABLE__SHIFT 0x00000000 6673*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_COLOR_FORMAT_MASK 0x03000000L 6674*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_COLOR_FORMAT__SHIFT 0x00000018 6675*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_CTL3_MASK 0x80000000L 6676*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_CTL3__SHIFT 0x0000001f 6677*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN_MASK 0x00000100L 6678*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_DUAL_CHANNEL_EN__SHIFT 0x00000008 6679*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_INVERT_DVOCLK_MASK 0x00040000L 6680*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_INVERT_DVOCLK__SHIFT 0x00000012 6681*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_RATE_SELECT_MASK 0x00000001L 6682*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_RATE_SELECT__SHIFT 0x00000000 6683*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_RESET_FIFO_MASK 0x00010000L 6684*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_RESET_FIFO__SHIFT 0x00000010 6685*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_SDRCLK_SEL_MASK 0x00000002L 6686*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_SDRCLK_SEL__SHIFT 0x00000001 6687*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_SYNC_PHASE_MASK 0x00020000L 6688*b843c749SSergey Zigachev #define DVO_CONTROL__DVO_SYNC_PHASE__SHIFT 0x00000011 6689*b843c749SSergey Zigachev #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK_MASK 0x07ffffffL 6690*b843c749SSergey Zigachev #define DVO_CRC2_SIG_MASK__DVO_CRC2_SIG_MASK__SHIFT 0x00000000 6691*b843c749SSergey Zigachev #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT_MASK 0x07ffffffL 6692*b843c749SSergey Zigachev #define DVO_CRC2_SIG_RESULT__DVO_CRC2_SIG_RESULT__SHIFT 0x00000000 6693*b843c749SSergey Zigachev #define DVO_CRC_EN__DVO_CRC2_EN_MASK 0x00010000L 6694*b843c749SSergey Zigachev #define DVO_CRC_EN__DVO_CRC2_EN__SHIFT 0x00000010 6695*b843c749SSergey Zigachev #define DVO_ENABLE__DVO_ENABLE_MASK 0x00000001L 6696*b843c749SSergey Zigachev #define DVO_ENABLE__DVO_ENABLE__SHIFT 0x00000000 6697*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL_MASK 0x0000fc00L 6698*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CAL_AVERAGE_LEVEL__SHIFT 0x0000000a 6699*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED_MASK 0x20000000L 6700*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_CALIBRATED__SHIFT 0x0000001d 6701*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK_MASK 0x00000100L 6702*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_ERROR_ACK__SHIFT 0x00000008 6703*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE_MASK 0x40000000L 6704*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECAL_AVERAGE__SHIFT 0x0000001e 6705*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX_MASK 0x80000000L 6706*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_FORCE_RECOMP_MINMAX__SHIFT 0x0000001f 6707*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR_MASK 0x00000001L 6708*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_LEVEL_ERROR__SHIFT 0x00000000 6709*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL_MASK 0x000f0000L 6710*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MAXIMUM_LEVEL__SHIFT 0x00000010 6711*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL_MASK 0x03c00000L 6712*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_MINIMUM_LEVEL__SHIFT 0x00000016 6713*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL_MASK 0x000000fcL 6714*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_OVERWRITE_LEVEL__SHIFT 0x00000002 6715*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL_MASK 0x00000002L 6716*b843c749SSergey Zigachev #define DVO_FIFO_ERROR_STATUS__DVO_FIFO_USE_OVERWRITE_LEVEL__SHIFT 0x00000001 6717*b843c749SSergey Zigachev #define DVO_OUTPUT__DVO_CLOCK_MODE_MASK 0x00000100L 6718*b843c749SSergey Zigachev #define DVO_OUTPUT__DVO_CLOCK_MODE__SHIFT 0x00000008 6719*b843c749SSergey Zigachev #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE_MASK 0x00000003L 6720*b843c749SSergey Zigachev #define DVO_OUTPUT__DVO_OUTPUT_ENABLE_MODE__SHIFT 0x00000000 6721*b843c749SSergey Zigachev #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST_MASK 0xffffffffL 6722*b843c749SSergey Zigachev #define DVO_SKEW_ADJUST__DVO_SKEW_ADJUST__SHIFT 0x00000000 6723*b843c749SSergey Zigachev #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT_MASK 0x00000007L 6724*b843c749SSergey Zigachev #define DVO_SOURCE_SELECT__DVO_SOURCE_SELECT__SHIFT 0x00000000 6725*b843c749SSergey Zigachev #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT_MASK 0x00070000L 6726*b843c749SSergey Zigachev #define DVO_SOURCE_SELECT__DVO_STEREOSYNC_SELECT__SHIFT 0x00000010 6727*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVOCLK_SN_MASK 0x0000f000L 6728*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVOCLK_SN__SHIFT 0x0000000c 6729*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVOCLK_SP_MASK 0x00000f00L 6730*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVOCLK_SP__SHIFT 0x00000008 6731*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE_MASK 0x10000000L 6732*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_LSB_VMODE__SHIFT 0x0000001c 6733*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE_MASK 0x20000000L 6734*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_MSB_VMODE__SHIFT 0x0000001d 6735*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_SN_MASK 0x000000f0L 6736*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_SN__SHIFT 0x00000004 6737*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_SP_MASK 0x0000000fL 6738*b843c749SSergey Zigachev #define DVO_STRENGTH_CONTROL__DVO_SP__SHIFT 0x00000000 6739*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFCAL_MASK 0x000000f0L 6740*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFCAL__SHIFT 0x00000004 6741*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFPON_MASK 0x00000001L 6742*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFPON__SHIFT 0x00000000 6743*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFSEL_MASK 0x00000002L 6744*b843c749SSergey Zigachev #define DVO_VREF_CONTROL__DVO_VREFSEL__SHIFT 0x00000001 6745*b843c749SSergey Zigachev #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x0fff0000L 6746*b843c749SSergey Zigachev #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 6747*b843c749SSergey Zigachev #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00000fffL 6748*b843c749SSergey Zigachev #define EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 6749*b843c749SSergey Zigachev #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00000fffL 6750*b843c749SSergey Zigachev #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 6751*b843c749SSergey Zigachev #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x0fff0000L 6752*b843c749SSergey Zigachev #define EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 6753*b843c749SSergey Zigachev #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK_MASK 0x000f0000L 6754*b843c749SSergey Zigachev #define FBC_CLIENT_REGION_MASK__FBC_MEMORY_REGION_MASK__SHIFT 0x00000010 6755*b843c749SSergey Zigachev #define FBC_CNTL__FBC_COHERENCY_MODE_MASK 0x00030000L 6756*b843c749SSergey Zigachev #define FBC_CNTL__FBC_COHERENCY_MODE__SHIFT 0x00000010 6757*b843c749SSergey Zigachev #define FBC_CNTL__FBC_EN_MASK 0x80000000L 6758*b843c749SSergey Zigachev #define FBC_CNTL__FBC_EN__SHIFT 0x0000001f 6759*b843c749SSergey Zigachev #define FBC_CNTL__FBC_GRPH_COMP_EN_MASK 0x00000001L 6760*b843c749SSergey Zigachev #define FBC_CNTL__FBC_GRPH_COMP_EN__SHIFT 0x00000000 6761*b843c749SSergey Zigachev #define FBC_CNTL__FBC_SOFT_COMPRESS_EN_MASK 0x02000000L 6762*b843c749SSergey Zigachev #define FBC_CNTL__FBC_SOFT_COMPRESS_EN__SHIFT 0x00000019 6763*b843c749SSergey Zigachev #define FBC_CNTL__FBC_SRC_SEL_MASK 0x0000000eL 6764*b843c749SSergey Zigachev #define FBC_CNTL__FBC_SRC_SEL__SHIFT 0x00000001 6765*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN_MASK 0x00010000L 6766*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_MONO08_EN__SHIFT 0x00000010 6767*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN_MASK 0x00020000L 6768*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_MONO16_EN__SHIFT 0x00000011 6769*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN_MASK 0x00040000L 6770*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB04_EN__SHIFT 0x00000012 6771*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN_MASK 0x00080000L 6772*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB08_EN__SHIFT 0x00000013 6773*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN_MASK 0x00100000L 6774*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_DEPTH_RGB16_EN__SHIFT 0x00000014 6775*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION_MASK 0x0000000fL 6776*b843c749SSergey Zigachev #define FBC_COMP_CNTL__FBC_MIN_COMPRESSION__SHIFT 0x00000000 6777*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN_MASK 0x00000100L 6778*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM4_RGB_EN__SHIFT 0x00000008 6779*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN_MASK 0x00000400L 6780*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM4_YUV_EN__SHIFT 0x0000000a 6781*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN_MASK 0x00000200L 6782*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM8_RGB_EN__SHIFT 0x00000009 6783*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN_MASK 0x00000800L 6784*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_DPCM8_YUV_EN__SHIFT 0x0000000b 6785*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_IND_EN_MASK 0x00010000L 6786*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_IND_EN__SHIFT 0x00000010 6787*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_RLE_EN_MASK 0x00000001L 6788*b843c749SSergey Zigachev #define FBC_COMP_MODE__FBC_RLE_EN__SHIFT 0x00000000 6789*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0_MASK 0x000003ffL 6790*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_0__SHIFT 0x00000000 6791*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1_MASK 0x03ff0000L 6792*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_01__FBC_CSM_REGION_OFFSET_1__SHIFT 0x00000010 6793*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2_MASK 0x000003ffL 6794*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_2__SHIFT 0x00000000 6795*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3_MASK 0x03ff0000L 6796*b843c749SSergey Zigachev #define FBC_CSM_REGION_OFFSET_23__FBC_CSM_REGION_OFFSET_3__SHIFT 0x00000010 6797*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_COMP_WAKE_DIS_MASK 0x00010000L 6798*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_COMP_WAKE_DIS__SHIFT 0x00000010 6799*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_DEBUG0_MASK 0x00fe0000L 6800*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_DEBUG0__SHIFT 0x00000011 6801*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_DEBUG_MUX_MASK 0xff000000L 6802*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_DEBUG_MUX__SHIFT 0x00000018 6803*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_PERF_MUX0_MASK 0x000000ffL 6804*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_PERF_MUX0__SHIFT 0x00000000 6805*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_PERF_MUX1_MASK 0x0000ff00L 6806*b843c749SSergey Zigachev #define FBC_DEBUG0__FBC_PERF_MUX1__SHIFT 0x00000008 6807*b843c749SSergey Zigachev #define FBC_DEBUG1__FBC_DEBUG1_MASK 0xffffffffL 6808*b843c749SSergey Zigachev #define FBC_DEBUG1__FBC_DEBUG1__SHIFT 0x00000000 6809*b843c749SSergey Zigachev #define FBC_DEBUG2__FBC_DEBUG2_MASK 0xffffffffL 6810*b843c749SSergey Zigachev #define FBC_DEBUG2__FBC_DEBUG2__SHIFT 0x00000000 6811*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE_MASK 0x00000800L 6812*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x0000000b 6813*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS_MASK 0x000000f0L 6814*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_BUSY_HYSTERESIS__SHIFT 0x00000004 6815*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL_MASK 0x00000300L 6816*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_CLK_CNTL__SHIFT 0x00000008 6817*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE_MASK 0x00000400L 6818*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x0000000a 6819*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_RSIZE_MASK 0x00000008L 6820*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_RSIZE__SHIFT 0x00000003 6821*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_SWAP_MASK 0x00000003L 6822*b843c749SSergey Zigachev #define FBC_DEBUG_COMP__FBC_COMP_SWAP__SHIFT 0x00000000 6823*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR_MASK 0x000003ffL 6824*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_ADDR__SHIFT 0x00000000 6825*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN_MASK 0x80000000L 6826*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_EN__SHIFT 0x0000001f 6827*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA_MASK 0x00020000L 6828*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_RD_DATA__SHIFT 0x00000011 6829*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA_MASK 0x00010000L 6830*b843c749SSergey Zigachev #define FBC_DEBUG_CSR__FBC_DEBUG_CSR_WR_DATA__SHIFT 0x00000010 6831*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA_MASK 0xffffffffL 6832*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_RDATA__FBC_DEBUG_CSR_RDATA__SHIFT 0x00000000 6833*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI_MASK 0x000000ffL 6834*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_RDATA_HI__FBC_DEBUG_CSR_RDATA_HI__SHIFT 0x00000000 6835*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA_MASK 0xffffffffL 6836*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_WDATA__FBC_DEBUG_CSR_WDATA__SHIFT 0x00000000 6837*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI_MASK 0x000000ffL 6838*b843c749SSergey Zigachev #define FBC_DEBUG_CSR_WDATA_HI__FBC_DEBUG_CSR_WDATA_HI__SHIFT 0x00000000 6839*b843c749SSergey Zigachev #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK_MASK 0xffffffffL 6840*b843c749SSergey Zigachev #define FBC_IDLE_FORCE_CLEAR_MASK__FBC_IDLE_FORCE_CLEAR_MASK__SHIFT 0x00000000 6841*b843c749SSergey Zigachev #define FBC_IDLE_MASK__FBC_IDLE_MASK_MASK 0xffffffffL 6842*b843c749SSergey Zigachev #define FBC_IDLE_MASK__FBC_IDLE_MASK__SHIFT 0x00000000 6843*b843c749SSergey Zigachev #define FBC_IND_LUT0__FBC_IND_LUT0_MASK 0x00ffffffL 6844*b843c749SSergey Zigachev #define FBC_IND_LUT0__FBC_IND_LUT0__SHIFT 0x00000000 6845*b843c749SSergey Zigachev #define FBC_IND_LUT10__FBC_IND_LUT10_MASK 0x00ffffffL 6846*b843c749SSergey Zigachev #define FBC_IND_LUT10__FBC_IND_LUT10__SHIFT 0x00000000 6847*b843c749SSergey Zigachev #define FBC_IND_LUT11__FBC_IND_LUT11_MASK 0x00ffffffL 6848*b843c749SSergey Zigachev #define FBC_IND_LUT11__FBC_IND_LUT11__SHIFT 0x00000000 6849*b843c749SSergey Zigachev #define FBC_IND_LUT12__FBC_IND_LUT12_MASK 0x00ffffffL 6850*b843c749SSergey Zigachev #define FBC_IND_LUT12__FBC_IND_LUT12__SHIFT 0x00000000 6851*b843c749SSergey Zigachev #define FBC_IND_LUT13__FBC_IND_LUT13_MASK 0x00ffffffL 6852*b843c749SSergey Zigachev #define FBC_IND_LUT13__FBC_IND_LUT13__SHIFT 0x00000000 6853*b843c749SSergey Zigachev #define FBC_IND_LUT14__FBC_IND_LUT14_MASK 0x00ffffffL 6854*b843c749SSergey Zigachev #define FBC_IND_LUT14__FBC_IND_LUT14__SHIFT 0x00000000 6855*b843c749SSergey Zigachev #define FBC_IND_LUT15__FBC_IND_LUT15_MASK 0x00ffffffL 6856*b843c749SSergey Zigachev #define FBC_IND_LUT15__FBC_IND_LUT15__SHIFT 0x00000000 6857*b843c749SSergey Zigachev #define FBC_IND_LUT1__FBC_IND_LUT1_MASK 0x00ffffffL 6858*b843c749SSergey Zigachev #define FBC_IND_LUT1__FBC_IND_LUT1__SHIFT 0x00000000 6859*b843c749SSergey Zigachev #define FBC_IND_LUT2__FBC_IND_LUT2_MASK 0x00ffffffL 6860*b843c749SSergey Zigachev #define FBC_IND_LUT2__FBC_IND_LUT2__SHIFT 0x00000000 6861*b843c749SSergey Zigachev #define FBC_IND_LUT3__FBC_IND_LUT3_MASK 0x00ffffffL 6862*b843c749SSergey Zigachev #define FBC_IND_LUT3__FBC_IND_LUT3__SHIFT 0x00000000 6863*b843c749SSergey Zigachev #define FBC_IND_LUT4__FBC_IND_LUT4_MASK 0x00ffffffL 6864*b843c749SSergey Zigachev #define FBC_IND_LUT4__FBC_IND_LUT4__SHIFT 0x00000000 6865*b843c749SSergey Zigachev #define FBC_IND_LUT5__FBC_IND_LUT5_MASK 0x00ffffffL 6866*b843c749SSergey Zigachev #define FBC_IND_LUT5__FBC_IND_LUT5__SHIFT 0x00000000 6867*b843c749SSergey Zigachev #define FBC_IND_LUT6__FBC_IND_LUT6_MASK 0x00ffffffL 6868*b843c749SSergey Zigachev #define FBC_IND_LUT6__FBC_IND_LUT6__SHIFT 0x00000000 6869*b843c749SSergey Zigachev #define FBC_IND_LUT7__FBC_IND_LUT7_MASK 0x00ffffffL 6870*b843c749SSergey Zigachev #define FBC_IND_LUT7__FBC_IND_LUT7__SHIFT 0x00000000 6871*b843c749SSergey Zigachev #define FBC_IND_LUT8__FBC_IND_LUT8_MASK 0x00ffffffL 6872*b843c749SSergey Zigachev #define FBC_IND_LUT8__FBC_IND_LUT8__SHIFT 0x00000000 6873*b843c749SSergey Zigachev #define FBC_IND_LUT9__FBC_IND_LUT9_MASK 0x00ffffffL 6874*b843c749SSergey Zigachev #define FBC_IND_LUT9__FBC_IND_LUT9__SHIFT 0x00000000 6875*b843c749SSergey Zigachev #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR_MASK 0x00010000L 6876*b843c749SSergey Zigachev #define FBC_MISC__FBC_DECOMPRESS_ERROR_CLEAR__SHIFT 0x00000010 6877*b843c749SSergey Zigachev #define FBC_MISC__FBC_DECOMPRESS_ERROR_MASK 0x00000003L 6878*b843c749SSergey Zigachev #define FBC_MISC__FBC_DECOMPRESS_ERROR__SHIFT 0x00000000 6879*b843c749SSergey Zigachev #define FBC_MISC__FBC_DIVIDE_X_MASK 0x00000300L 6880*b843c749SSergey Zigachev #define FBC_MISC__FBC_DIVIDE_X__SHIFT 0x00000008 6881*b843c749SSergey Zigachev #define FBC_MISC__FBC_DIVIDE_Y_MASK 0x00000400L 6882*b843c749SSergey Zigachev #define FBC_MISC__FBC_DIVIDE_Y__SHIFT 0x0000000a 6883*b843c749SSergey Zigachev #define FBC_MISC__FBC_ERROR_PIXEL_MASK 0x000000f0L 6884*b843c749SSergey Zigachev #define FBC_MISC__FBC_ERROR_PIXEL__SHIFT 0x00000004 6885*b843c749SSergey Zigachev #define FBC_MISC__FBC_INVALIDATE_ON_ERROR_MASK 0x00000008L 6886*b843c749SSergey Zigachev #define FBC_MISC__FBC_INVALIDATE_ON_ERROR__SHIFT 0x00000003 6887*b843c749SSergey Zigachev #define FBC_MISC__FBC_RESET_AT_DISABLE_MASK 0x00200000L 6888*b843c749SSergey Zigachev #define FBC_MISC__FBC_RESET_AT_DISABLE__SHIFT 0x00000015 6889*b843c749SSergey Zigachev #define FBC_MISC__FBC_RESET_AT_ENABLE_MASK 0x00100000L 6890*b843c749SSergey Zigachev #define FBC_MISC__FBC_RESET_AT_ENABLE__SHIFT 0x00000014 6891*b843c749SSergey Zigachev #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY_MASK 0x00001000L 6892*b843c749SSergey Zigachev #define FBC_MISC__FBC_RSM_UNCOMP_DATA_IMMEDIATELY__SHIFT 0x0000000c 6893*b843c749SSergey Zigachev #define FBC_MISC__FBC_RSM_WRITE_VALUE_MASK 0x00000800L 6894*b843c749SSergey Zigachev #define FBC_MISC__FBC_RSM_WRITE_VALUE__SHIFT 0x0000000b 6895*b843c749SSergey Zigachev #define FBC_MISC__FBC_SLOW_REQ_INTERVAL_MASK 0xf0000000L 6896*b843c749SSergey Zigachev #define FBC_MISC__FBC_SLOW_REQ_INTERVAL__SHIFT 0x0000001c 6897*b843c749SSergey Zigachev #define FBC_MISC__FBC_STOP_ON_ERROR_MASK 0x00000004L 6898*b843c749SSergey Zigachev #define FBC_MISC__FBC_STOP_ON_ERROR__SHIFT 0x00000002 6899*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY_MASK 0x00001f00L 6900*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_COMP_START_DELAY__SHIFT 0x00000008 6901*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY_MASK 0x0000001fL 6902*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_DECOMP_START_DELAY__SHIFT 0x00000000 6903*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY_MASK 0x00000080L 6904*b843c749SSergey Zigachev #define FBC_START_STOP_DELAY__FBC_DECOMP_STOP_DELAY__SHIFT 0x00000007 6905*b843c749SSergey Zigachev #define FBC_STATUS__FBC_ENABLE_STATUS_MASK 0x00000001L 6906*b843c749SSergey Zigachev #define FBC_STATUS__FBC_ENABLE_STATUS__SHIFT 0x00000000 6907*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA_MASK 0xffffffffL 6908*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_DATA__FBC_TEST_DEBUG_DATA__SHIFT 0x00000000 6909*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX_MASK 0x000000ffL 6910*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_INDEX__SHIFT 0x00000000 6911*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 6912*b843c749SSergey Zigachev #define FBC_TEST_DEBUG_INDEX__FBC_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 6913*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL_MASK 0x0c000000L 6914*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_25FRC_SEL__SHIFT 0x0000001a 6915*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL_MASK 0x30000000L 6916*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_50FRC_SEL__SHIFT 0x0000001c 6917*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL_MASK 0xc0000000L 6918*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_75FRC_SEL__SHIFT 0x0000001e 6919*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK 0x00002000L 6920*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d 6921*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000L 6922*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f 6923*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK 0x00004000L 6924*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e 6925*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK 0x00001000L 6926*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000c 6927*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK 0x00000100L 6928*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 6929*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE_MASK 0x00000600L 6930*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 6931*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH_MASK 0x00100000L 6932*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_DEPTH__SHIFT 0x00000014 6933*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN_MASK 0x00010000L 6934*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_EN__SHIFT 0x00000010 6935*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET_MASK 0x00600000L 6936*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_OFFSET__SHIFT 0x00000015 6937*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET_MASK 0x02000000L 6938*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_DITHER_RESET__SHIFT 0x00000019 6939*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL_MASK 0x01000000L 6940*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TEMPORAL_LEVEL__SHIFT 0x00000018 6941*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK 0x00000010L 6942*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT 0x00000004 6943*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK 0x00000001L 6944*b843c749SSergey Zigachev #define FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN__SHIFT 0x00000000 6945*b843c749SSergey Zigachev #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT_MASK 0x00070000L 6946*b843c749SSergey Zigachev #define FMT_CLAMP_CNTL__FMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 6947*b843c749SSergey Zigachev #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN_MASK 0x00000001L 6948*b843c749SSergey Zigachev #define FMT_CLAMP_CNTL__FMT_CLAMP_DATA_EN__SHIFT 0x00000000 6949*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_PIXEL_ENCODING_MASK 0x00010000L 6950*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_PIXEL_ENCODING__SHIFT 0x00000010 6951*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE_MASK 0x00000001L 6952*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_STEREOSYNC_OVERRIDE__SHIFT 0x00000000 6953*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL_MASK 0x00000010L 6954*b843c749SSergey Zigachev #define FMT_CONTROL__FMT_STEREOSYNC_OVR_POL__SHIFT 0x00000004 6955*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_CONT_EN_MASK 0x00000010L 6956*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_CONT_EN__SHIFT 0x00000004 6957*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EN_MASK 0x00000001L 6958*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EN__SHIFT 0x00000000 6959*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE_MASK 0x00100000L 6960*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_ENABLE__SHIFT 0x00000014 6961*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT_MASK 0x01000000L 6962*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_EVEN_ODD_PIX_SELECT__SHIFT 0x00000018 6963*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE_MASK 0x00003000L 6964*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_INTERLACE_MODE__SHIFT 0x0000000c 6965*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb_MASK 0x00000100L 6966*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_ONLY_BLANKb__SHIFT 0x00000008 6967*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS_MASK 0x00010000L 6968*b843c749SSergey Zigachev #define FMT_CRC_CNTL__FMT_CRC_USE_NEW_AND_REPEATED_PIXELS__SHIFT 0x00000010 6969*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE_MASK 0x0000ffffL 6970*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_BLUE__SHIFT 0x00000000 6971*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL_MASK 0xffff0000L 6972*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL__FMT_CRC_SIG_CONTROL__SHIFT 0x00000010 6973*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK_MASK 0x0000ffffL 6974*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_BLUE_MASK__SHIFT 0x00000000 6975*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK_MASK 0xffff0000L 6976*b843c749SSergey Zigachev #define FMT_CRC_SIG_BLUE_CONTROL_MASK__FMT_CRC_SIG_CONTROL_MASK__SHIFT 0x00000010 6977*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN_MASK 0xffff0000L 6978*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_GREEN__SHIFT 0x00000010 6979*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED_MASK 0x0000ffffL 6980*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN__FMT_CRC_SIG_RED__SHIFT 0x00000000 6981*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK_MASK 0xffff0000L 6982*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_GREEN_MASK__SHIFT 0x00000010 6983*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK_MASK 0x0000ffffL 6984*b843c749SSergey Zigachev #define FMT_CRC_SIG_RED_GREEN_MASK__FMT_CRC_SIG_RED_MASK__SHIFT 0x00000000 6985*b843c749SSergey Zigachev #define FMT_DEBUG0__FMT_DEBUG0_MASK 0xffffffffL 6986*b843c749SSergey Zigachev #define FMT_DEBUG0__FMT_DEBUG0__SHIFT 0x00000000 6987*b843c749SSergey Zigachev #define FMT_DEBUG1__FMT_DEBUG1_MASK 0xffffffffL 6988*b843c749SSergey Zigachev #define FMT_DEBUG1__FMT_DEBUG1__SHIFT 0x00000000 6989*b843c749SSergey Zigachev #define FMT_DEBUG2__FMT_DEBUG2_MASK 0xffffffffL 6990*b843c749SSergey Zigachev #define FMT_DEBUG2__FMT_DEBUG2__SHIFT 0x00000000 6991*b843c749SSergey Zigachev #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT_MASK 0x00000003L 6992*b843c749SSergey Zigachev #define FMT_DEBUG_CNTL__FMT_DEBUG_COLOR_SELECT__SHIFT 0x00000000 6993*b843c749SSergey Zigachev #define FMT_DEBUG_ID__FMT_DEBUG_ID_MASK 0xffffffffL 6994*b843c749SSergey Zigachev #define FMT_DEBUG_ID__FMT_DEBUG_ID__SHIFT 0x00000000 6995*b843c749SSergey Zigachev #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED_MASK 0x000000ffL 6996*b843c749SSergey Zigachev #define FMT_DITHER_RAND_B_SEED__FMT_RAND_B_SEED__SHIFT 0x00000000 6997*b843c749SSergey Zigachev #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED_MASK 0x000000ffL 6998*b843c749SSergey Zigachev #define FMT_DITHER_RAND_G_SEED__FMT_RAND_G_SEED__SHIFT 0x00000000 6999*b843c749SSergey Zigachev #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED_MASK 0x000000ffL 7000*b843c749SSergey Zigachev #define FMT_DITHER_RAND_R_SEED__FMT_RAND_R_SEED__SHIFT 0x00000000 7001*b843c749SSergey Zigachev #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN_MASK 0x00000001L 7002*b843c749SSergey Zigachev #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 7003*b843c749SSergey Zigachev #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE_MASK 0x00000010L 7004*b843c749SSergey Zigachev #define FMT_DYNAMIC_EXP_CNTL__FMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 7005*b843c749SSergey Zigachev #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0_MASK 0x0000ffffL 7006*b843c749SSergey Zigachev #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA0__SHIFT 0x00000000 7007*b843c749SSergey Zigachev #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1_MASK 0xffff0000L 7008*b843c749SSergey Zigachev #define FMT_FORCE_DATA_0_1__FMT_FORCE_DATA1__SHIFT 0x00000010 7009*b843c749SSergey Zigachev #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2_MASK 0x0000ffffL 7010*b843c749SSergey Zigachev #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA2__SHIFT 0x00000000 7011*b843c749SSergey Zigachev #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3_MASK 0xffff0000L 7012*b843c749SSergey Zigachev #define FMT_FORCE_DATA_2_3__FMT_FORCE_DATA3__SHIFT 0x00000010 7013*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN_MASK 0x00000001L 7014*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_EN__SHIFT 0x00000000 7015*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY_MASK 0x00010000L 7016*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_ON_BLANKb_ONLY__SHIFT 0x00000010 7017*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR_MASK 0x00000700L 7018*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_COLOR__SHIFT 0x00000008 7019*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT_MASK 0x0000f000L 7020*b843c749SSergey Zigachev #define FMT_FORCE_OUTPUT_CNTL__FMT_FORCE_DATA_SEL_SLOT__SHIFT 0x0000000c 7021*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0_MASK 0x00000010L 7022*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_RGB1_BGR0__SHIFT 0x00000004 7023*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT_MASK 0x00000001L 7024*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PATTERN_CONTROL__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_SELECT__SHIFT 0x00000000 7025*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX_MASK 0xffffffffL 7026*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX__SHIFT 0x00000000 7027*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX_MASK 0xffffffffL 7028*b843c749SSergey Zigachev #define FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX__SHIFT 0x00000000 7029*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA_MASK 0xffffffffL 7030*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_DATA__FMT_TEST_DEBUG_DATA__SHIFT 0x00000000 7031*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX_MASK 0x000000ffL 7032*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_INDEX__SHIFT 0x00000000 7033*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7034*b843c749SSergey Zigachev #define FMT_TEST_DEBUG_INDEX__FMT_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7035*b843c749SSergey Zigachev #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11_MASK 0x0000ffffL 7036*b843c749SSergey Zigachev #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C11__SHIFT 0x00000000 7037*b843c749SSergey Zigachev #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12_MASK 0xffff0000L 7038*b843c749SSergey Zigachev #define GAMUT_REMAP_C11_C12__GAMUT_REMAP_C12__SHIFT 0x00000010 7039*b843c749SSergey Zigachev #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13_MASK 0x0000ffffL 7040*b843c749SSergey Zigachev #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C13__SHIFT 0x00000000 7041*b843c749SSergey Zigachev #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14_MASK 0xffff0000L 7042*b843c749SSergey Zigachev #define GAMUT_REMAP_C13_C14__GAMUT_REMAP_C14__SHIFT 0x00000010 7043*b843c749SSergey Zigachev #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21_MASK 0x0000ffffL 7044*b843c749SSergey Zigachev #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C21__SHIFT 0x00000000 7045*b843c749SSergey Zigachev #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22_MASK 0xffff0000L 7046*b843c749SSergey Zigachev #define GAMUT_REMAP_C21_C22__GAMUT_REMAP_C22__SHIFT 0x00000010 7047*b843c749SSergey Zigachev #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23_MASK 0x0000ffffL 7048*b843c749SSergey Zigachev #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C23__SHIFT 0x00000000 7049*b843c749SSergey Zigachev #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24_MASK 0xffff0000L 7050*b843c749SSergey Zigachev #define GAMUT_REMAP_C23_C24__GAMUT_REMAP_C24__SHIFT 0x00000010 7051*b843c749SSergey Zigachev #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31_MASK 0x0000ffffL 7052*b843c749SSergey Zigachev #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C31__SHIFT 0x00000000 7053*b843c749SSergey Zigachev #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32_MASK 0xffff0000L 7054*b843c749SSergey Zigachev #define GAMUT_REMAP_C31_C32__GAMUT_REMAP_C32__SHIFT 0x00000010 7055*b843c749SSergey Zigachev #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33_MASK 0x0000ffffL 7056*b843c749SSergey Zigachev #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C33__SHIFT 0x00000000 7057*b843c749SSergey Zigachev #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34_MASK 0xffff0000L 7058*b843c749SSergey Zigachev #define GAMUT_REMAP_C33_C34__GAMUT_REMAP_C34__SHIFT 0x00000010 7059*b843c749SSergey Zigachev #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE_MASK 0x00000003L 7060*b843c749SSergey Zigachev #define GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT 0x00000000 7061*b843c749SSergey Zigachev #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE_MASK 0x00000030L 7062*b843c749SSergey Zigachev #define GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT 0x00000004 7063*b843c749SSergey Zigachev #define GENENB__BLK_IO_BASE_MASK 0x000000ffL 7064*b843c749SSergey Zigachev #define GENENB__BLK_IO_BASE__SHIFT 0x00000000 7065*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL_MASK 0x80000000L 7066*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_DBG_REF_SEL__SHIFT 0x0000001f 7067*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE_MASK 0x00000008L 7068*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_ENABLE__SHIFT 0x00000003 7069*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO_MASK 0x00000001L 7070*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_GO__SHIFT 0x00000000 7071*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET_MASK 0x00000004L 7072*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_SEND_RESET__SHIFT 0x00000002 7073*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET_MASK 0x00000002L 7074*b843c749SSergey Zigachev #define GENERIC_I2C_CONTROL__GENERIC_I2C_SOFT_RESET__SHIFT 0x00000001 7075*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_MASK 0x0000ff00L 7076*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW_MASK 0x00000001L 7077*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_DATA_RW__SHIFT 0x00000000 7078*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_DATA__SHIFT 0x00000008 7079*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_MASK 0x000f0000L 7080*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX__SHIFT 0x00000010 7081*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE_MASK 0x80000000L 7082*b843c749SSergey Zigachev #define GENERIC_I2C_DATA__GENERIC_I2C_INDEX_WRITE__SHIFT 0x0000001f 7083*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK_MASK 0x00000002L 7084*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_ACK__SHIFT 0x00000001 7085*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT_MASK 0x00000001L 7086*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_INT__SHIFT 0x00000000 7087*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK_MASK 0x00000004L 7088*b843c749SSergey Zigachev #define GENERIC_I2C_INTERRUPT_CONTROL__GENERIC_I2C_DONE_MASK__SHIFT 0x00000002 7089*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN_MASK 0x00000004L 7090*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_EN__SHIFT 0x00000002 7091*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT_MASK 0x00000002L 7092*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_INPUT__SHIFT 0x00000001 7093*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT_MASK 0x00000001L 7094*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SCL_OUTPUT__SHIFT 0x00000000 7095*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN_MASK 0x00000040L 7096*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_EN__SHIFT 0x00000006 7097*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT_MASK 0x00000020L 7098*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_INPUT__SHIFT 0x00000005 7099*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT_MASK 0x00000010L 7100*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_DEBUG__GENERIC_I2C_SDA_OUTPUT__SHIFT 0x00000004 7101*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL_MASK 0x0000007fL 7102*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SCL_PIN_SEL__SHIFT 0x00000000 7103*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL_MASK 0x00007f00L 7104*b843c749SSergey Zigachev #define GENERIC_I2C_PIN_SELECTION__GENERIC_I2C_SDA_PIN_SEL__SHIFT 0x00000008 7105*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN_MASK 0x00000080L 7106*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_CLK_DRIVE_EN__SHIFT 0x00000007 7107*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN_MASK 0x00000001L 7108*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_EN__SHIFT 0x00000000 7109*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL_MASK 0x00000002L 7110*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_DATA_DRIVE_SEL__SHIFT 0x00000001 7111*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY_MASK 0x0000ff00L 7112*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_INTRA_BYTE_DELAY__SHIFT 0x00000008 7113*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT_MASK 0xff000000L 7114*b843c749SSergey Zigachev #define GENERIC_I2C_SETUP__GENERIC_I2C_TIME_LIMIT__SHIFT 0x00000018 7115*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL_MASK 0x00000010L 7116*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_DISABLE_FILTER_DURING_STALL__SHIFT 0x00000004 7117*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE_MASK 0xffff0000L 7118*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_PRESCALE__SHIFT 0x00000010 7119*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD_MASK 0x00000003L 7120*b843c749SSergey Zigachev #define GENERIC_I2C_SPEED__GENERIC_I2C_THRESHOLD__SHIFT 0x00000000 7121*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED_MASK 0x00000020L 7122*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_ABORTED__SHIFT 0x00000005 7123*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE_MASK 0x00000010L 7124*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_DONE__SHIFT 0x00000004 7125*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK_MASK 0x00000400L 7126*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_NACK__SHIFT 0x0000000a 7127*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS_MASK 0x0000000fL 7128*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_STATUS__SHIFT 0x00000000 7129*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK_MASK 0x00000200L 7130*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_STOPPED_ON_NACK__SHIFT 0x00000009 7131*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT_MASK 0x00000040L 7132*b843c749SSergey Zigachev #define GENERIC_I2C_STATUS__GENERIC_I2C_TIMEOUT__SHIFT 0x00000006 7133*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ_MASK 0x00000200L 7134*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_ACK_ON_READ__SHIFT 0x00000009 7135*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT_MASK 0x000f0000L 7136*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_COUNT__SHIFT 0x00000010 7137*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW_MASK 0x00000001L 7138*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_RW__SHIFT 0x00000000 7139*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START_MASK 0x00001000L 7140*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_START__SHIFT 0x0000000c 7141*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_MASK 0x00002000L 7142*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK_MASK 0x00000100L 7143*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP_ON_NACK__SHIFT 0x00000008 7144*b843c749SSergey Zigachev #define GENERIC_I2C_TRANSACTION__GENERIC_I2C_STOP__SHIFT 0x0000000d 7145*b843c749SSergey Zigachev #define GENFC_RD__VSYNC_SEL_R_MASK 0x00000008L 7146*b843c749SSergey Zigachev #define GENFC_RD__VSYNC_SEL_R__SHIFT 0x00000003 7147*b843c749SSergey Zigachev #define GENFC_WT__VSYNC_SEL_W_MASK 0x00000008L 7148*b843c749SSergey Zigachev #define GENFC_WT__VSYNC_SEL_W__SHIFT 0x00000003 7149*b843c749SSergey Zigachev #define GENMO_RD__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7150*b843c749SSergey Zigachev #define GENMO_RD__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7151*b843c749SSergey Zigachev #define GENMO_RD__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7152*b843c749SSergey Zigachev #define GENMO_RD__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7153*b843c749SSergey Zigachev #define GENMO_RD__VGA_CKSEL_MASK 0x0000000cL 7154*b843c749SSergey Zigachev #define GENMO_RD__VGA_CKSEL__SHIFT 0x00000002 7155*b843c749SSergey Zigachev #define GENMO_RD__VGA_HSYNC_POL_MASK 0x00000040L 7156*b843c749SSergey Zigachev #define GENMO_RD__VGA_HSYNC_POL__SHIFT 0x00000006 7157*b843c749SSergey Zigachev #define GENMO_RD__VGA_RAM_EN_MASK 0x00000002L 7158*b843c749SSergey Zigachev #define GENMO_RD__VGA_RAM_EN__SHIFT 0x00000001 7159*b843c749SSergey Zigachev #define GENMO_RD__VGA_VSYNC_POL_MASK 0x00000080L 7160*b843c749SSergey Zigachev #define GENMO_RD__VGA_VSYNC_POL__SHIFT 0x00000007 7161*b843c749SSergey Zigachev #define GENMO_WT__GENMO_MONO_ADDRESS_B_MASK 0x00000001L 7162*b843c749SSergey Zigachev #define GENMO_WT__GENMO_MONO_ADDRESS_B__SHIFT 0x00000000 7163*b843c749SSergey Zigachev #define GENMO_WT__ODD_EVEN_MD_PGSEL_MASK 0x00000020L 7164*b843c749SSergey Zigachev #define GENMO_WT__ODD_EVEN_MD_PGSEL__SHIFT 0x00000005 7165*b843c749SSergey Zigachev #define GENMO_WT__VGA_CKSEL_MASK 0x0000000cL 7166*b843c749SSergey Zigachev #define GENMO_WT__VGA_CKSEL__SHIFT 0x00000002 7167*b843c749SSergey Zigachev #define GENMO_WT__VGA_HSYNC_POL_MASK 0x00000040L 7168*b843c749SSergey Zigachev #define GENMO_WT__VGA_HSYNC_POL__SHIFT 0x00000006 7169*b843c749SSergey Zigachev #define GENMO_WT__VGA_RAM_EN_MASK 0x00000002L 7170*b843c749SSergey Zigachev #define GENMO_WT__VGA_RAM_EN__SHIFT 0x00000001 7171*b843c749SSergey Zigachev #define GENMO_WT__VGA_VSYNC_POL_MASK 0x00000080L 7172*b843c749SSergey Zigachev #define GENMO_WT__VGA_VSYNC_POL__SHIFT 0x00000007 7173*b843c749SSergey Zigachev #define GENS0__CRT_INTR_MASK 0x00000080L 7174*b843c749SSergey Zigachev #define GENS0__CRT_INTR__SHIFT 0x00000007 7175*b843c749SSergey Zigachev #define GENS0__SENSE_SWITCH_MASK 0x00000010L 7176*b843c749SSergey Zigachev #define GENS0__SENSE_SWITCH__SHIFT 0x00000004 7177*b843c749SSergey Zigachev #define GENS1__NO_DISPLAY_MASK 0x00000001L 7178*b843c749SSergey Zigachev #define GENS1__NO_DISPLAY__SHIFT 0x00000000 7179*b843c749SSergey Zigachev #define GENS1__PIXEL_READ_BACK_MASK 0x00000030L 7180*b843c749SSergey Zigachev #define GENS1__PIXEL_READ_BACK__SHIFT 0x00000004 7181*b843c749SSergey Zigachev #define GENS1__VGA_VSTATUS_MASK 0x00000008L 7182*b843c749SSergey Zigachev #define GENS1__VGA_VSTATUS__SHIFT 0x00000003 7183*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET0_MASK 0x00000001L 7184*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET0__SHIFT 0x00000000 7185*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET1_MASK 0x00000002L 7186*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET1__SHIFT 0x00000001 7187*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET2_MASK 0x00000004L 7188*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET2__SHIFT 0x00000002 7189*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET3_MASK 0x00000008L 7190*b843c749SSergey Zigachev #define GRA00__GRPH_SET_RESET3__SHIFT 0x00000003 7191*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA0_MASK 0x00000001L 7192*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA0__SHIFT 0x00000000 7193*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA1_MASK 0x00000002L 7194*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA1__SHIFT 0x00000001 7195*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA2_MASK 0x00000004L 7196*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA2__SHIFT 0x00000002 7197*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA3_MASK 0x00000008L 7198*b843c749SSergey Zigachev #define GRA01__GRPH_SET_RESET_ENA3__SHIFT 0x00000003 7199*b843c749SSergey Zigachev #define GRA02__GRPH_CCOMP_MASK 0x0000000fL 7200*b843c749SSergey Zigachev #define GRA02__GRPH_CCOMP__SHIFT 0x00000000 7201*b843c749SSergey Zigachev #define GRA03__GRPH_FN_SEL_MASK 0x00000018L 7202*b843c749SSergey Zigachev #define GRA03__GRPH_FN_SEL__SHIFT 0x00000003 7203*b843c749SSergey Zigachev #define GRA03__GRPH_ROTATE_MASK 0x00000007L 7204*b843c749SSergey Zigachev #define GRA03__GRPH_ROTATE__SHIFT 0x00000000 7205*b843c749SSergey Zigachev #define GRA04__GRPH_RMAP_MASK 0x00000003L 7206*b843c749SSergey Zigachev #define GRA04__GRPH_RMAP__SHIFT 0x00000000 7207*b843c749SSergey Zigachev #define GRA05__CGA_ODDEVEN_MASK 0x00000010L 7208*b843c749SSergey Zigachev #define GRA05__CGA_ODDEVEN__SHIFT 0x00000004 7209*b843c749SSergey Zigachev #define GRA05__GRPH_OES_MASK 0x00000020L 7210*b843c749SSergey Zigachev #define GRA05__GRPH_OES__SHIFT 0x00000005 7211*b843c749SSergey Zigachev #define GRA05__GRPH_PACK_MASK 0x00000040L 7212*b843c749SSergey Zigachev #define GRA05__GRPH_PACK__SHIFT 0x00000006 7213*b843c749SSergey Zigachev #define GRA05__GRPH_READ1_MASK 0x00000008L 7214*b843c749SSergey Zigachev #define GRA05__GRPH_READ1__SHIFT 0x00000003 7215*b843c749SSergey Zigachev #define GRA05__GRPH_WRITE_MODE_MASK 0x00000003L 7216*b843c749SSergey Zigachev #define GRA05__GRPH_WRITE_MODE__SHIFT 0x00000000 7217*b843c749SSergey Zigachev #define GRA06__GRPH_ADRSEL_MASK 0x0000000cL 7218*b843c749SSergey Zigachev #define GRA06__GRPH_ADRSEL__SHIFT 0x00000002 7219*b843c749SSergey Zigachev #define GRA06__GRPH_GRAPHICS_MASK 0x00000001L 7220*b843c749SSergey Zigachev #define GRA06__GRPH_GRAPHICS__SHIFT 0x00000000 7221*b843c749SSergey Zigachev #define GRA06__GRPH_ODDEVEN_MASK 0x00000002L 7222*b843c749SSergey Zigachev #define GRA06__GRPH_ODDEVEN__SHIFT 0x00000001 7223*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE0_MASK 0x00000001L 7224*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE0__SHIFT 0x00000000 7225*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE1_MASK 0x00000002L 7226*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE1__SHIFT 0x00000001 7227*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE2_MASK 0x00000004L 7228*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE2__SHIFT 0x00000002 7229*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE3_MASK 0x00000008L 7230*b843c749SSergey Zigachev #define GRA07__GRPH_XCARE3__SHIFT 0x00000003 7231*b843c749SSergey Zigachev #define GRA08__GRPH_BMSK_MASK 0x000000ffL 7232*b843c749SSergey Zigachev #define GRA08__GRPH_BMSK__SHIFT 0x00000000 7233*b843c749SSergey Zigachev #define GRPH8_DATA__GRPH_DATA_MASK 0x000000ffL 7234*b843c749SSergey Zigachev #define GRPH8_DATA__GRPH_DATA__SHIFT 0x00000000 7235*b843c749SSergey Zigachev #define GRPH8_IDX__GRPH_IDX_MASK 0x0000000fL 7236*b843c749SSergey Zigachev #define GRPH8_IDX__GRPH_IDX__SHIFT 0x00000000 7237*b843c749SSergey Zigachev #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH_MASK 0x0001ffc0L 7238*b843c749SSergey Zigachev #define GRPH_COMPRESS_PITCH__GRPH_COMPRESS_PITCH__SHIFT 0x00000006 7239*b843c749SSergey Zigachev #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS_MASK 0xffffff00L 7240*b843c749SSergey Zigachev #define GRPH_COMPRESS_SURFACE_ADDRESS__GRPH_COMPRESS_SURFACE_ADDRESS__SHIFT 0x00000008 7241*b843c749SSergey Zigachev #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7242*b843c749SSergey Zigachev #define GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__GRPH_COMPRESS_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7243*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 7244*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 7245*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_ARRAY_MODE_MASK 0x00f00000L 7246*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT 0x00000014 7247*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_BANK_HEIGHT_MASK 0x00001800L 7248*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT 0x0000000b 7249*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_BANK_WIDTH_MASK 0x000000c0L 7250*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT 0x00000006 7251*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE_MASK 0x80000000L 7252*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_COLOR_EXPANSION_MODE__SHIFT 0x0000001f 7253*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_DEPTH_MASK 0x00000003L 7254*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_DEPTH__SHIFT 0x00000000 7255*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_FORMAT_MASK 0x00000700L 7256*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_FORMAT__SHIFT 0x00000008 7257*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT_MASK 0x000c0000L 7258*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT 0x00000012 7259*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_NUM_BANKS_MASK 0x0000000cL 7260*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT 0x00000002 7261*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_PIPE_CONFIG_MASK 0x1f000000L 7262*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT 0x00000018 7263*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 7264*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 7265*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_TILE_SPLIT_MASK 0x0000e000L 7266*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT 0x0000000d 7267*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_Z_MASK 0x00000030L 7268*b843c749SSergey Zigachev #define GRPH_CONTROL__GRPH_Z__SHIFT 0x00000004 7269*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 7270*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 7271*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET_MASK 0x00000001L 7272*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_RESET__SHIFT 0x00000000 7273*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE_MASK 0x00000070L 7274*b843c749SSergey Zigachev #define GRPH_DFQ_CONTROL__GRPH_DFQ_SIZE__SHIFT 0x00000004 7275*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK_MASK 0x00000200L 7276*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_ACK__SHIFT 0x00000009 7277*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG_MASK 0x00000100L 7278*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_DFQ_RESET_FLAG__SHIFT 0x00000008 7279*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES_MASK 0x0000000fL 7280*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_PRIMARY_DFQ_NUM_ENTRIES__SHIFT 0x00000000 7281*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 7282*b843c749SSergey Zigachev #define GRPH_DFQ_STATUS__GRPH_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 7283*b843c749SSergey Zigachev #define GRPH_ENABLE__GRPH_ENABLE_MASK 0x00000001L 7284*b843c749SSergey Zigachev #define GRPH_ENABLE__GRPH_ENABLE__SHIFT 0x00000000 7285*b843c749SSergey Zigachev #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK 0x00000001L 7286*b843c749SSergey Zigachev #define GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN__SHIFT 0x00000000 7287*b843c749SSergey Zigachev #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK 0x00000001L 7288*b843c749SSergey Zigachev #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK__SHIFT 0x00000000 7289*b843c749SSergey Zigachev #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE_MASK 0x00000100L 7290*b843c749SSergey Zigachev #define GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_TYPE__SHIFT 0x00000008 7291*b843c749SSergey Zigachev #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK 0x00000100L 7292*b843c749SSergey Zigachev #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR__SHIFT 0x00000008 7293*b843c749SSergey Zigachev #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK 0x00000001L 7294*b843c749SSergey Zigachev #define GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED__SHIFT 0x00000000 7295*b843c749SSergey Zigachev #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_MASK 0x00010000L 7296*b843c749SSergey Zigachev #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN__SHIFT 0x00000010 7297*b843c749SSergey Zigachev #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK 0x00000100L 7298*b843c749SSergey Zigachev #define GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN__SHIFT 0x00000008 7299*b843c749SSergey Zigachev #define GRPH_PITCH__GRPH_PITCH_MASK 0x00007fffL 7300*b843c749SSergey Zigachev #define GRPH_PITCH__GRPH_PITCH__SHIFT 0x00000000 7301*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE_MASK 0x00000001L 7302*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_DFQ_ENABLE__SHIFT 0x00000000 7303*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK 0xffffff00L 7304*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS__SHIFT 0x00000008 7305*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7306*b843c749SSergey Zigachev #define GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__GRPH_PRIMARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7307*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 7308*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 7309*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 7310*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 7311*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 7312*b843c749SSergey Zigachev #define GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__GRPH_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 7313*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 7314*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 7315*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 7316*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 7317*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN_MASK 0x00000001L 7318*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 7319*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 7320*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 7321*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 7322*b843c749SSergey Zigachev #define GRPH_STEREOSYNC_FLIP__GRPH_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 7323*b843c749SSergey Zigachev #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 7324*b843c749SSergey Zigachev #define GRPH_SURFACE_ADDRESS_HIGH_INUSE__GRPH_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 7325*b843c749SSergey Zigachev #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 7326*b843c749SSergey Zigachev #define GRPH_SURFACE_ADDRESS_INUSE__GRPH_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 7327*b843c749SSergey Zigachev #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X_MASK 0x00003fffL 7328*b843c749SSergey Zigachev #define GRPH_SURFACE_OFFSET_X__GRPH_SURFACE_OFFSET_X__SHIFT 0x00000000 7329*b843c749SSergey Zigachev #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y_MASK 0x00003fffL 7330*b843c749SSergey Zigachev #define GRPH_SURFACE_OFFSET_Y__GRPH_SURFACE_OFFSET_Y__SHIFT 0x00000000 7331*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR_MASK 0x00000c00L 7332*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_ALPHA_CROSSBAR__SHIFT 0x0000000a 7333*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR_MASK 0x00000300L 7334*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_BLUE_CROSSBAR__SHIFT 0x00000008 7335*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP_MASK 0x00000003L 7336*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT 0x00000000 7337*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR_MASK 0x000000c0L 7338*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_GREEN_CROSSBAR__SHIFT 0x00000006 7339*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR_MASK 0x00000030L 7340*b843c749SSergey Zigachev #define GRPH_SWAP_CNTL__GRPH_RED_CROSSBAR__SHIFT 0x00000004 7341*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 7342*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 7343*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING_MASK 0x00000001L 7344*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_UPDATE_PENDING__SHIFT 0x00000000 7345*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN_MASK 0x00000002L 7346*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_MODE_UPDATE_TAKEN__SHIFT 0x00000001 7347*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_MASK 0x10000000L 7348*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE__SHIFT 0x0000001c 7349*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK 0x00000004L 7350*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING__SHIFT 0x00000002 7351*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN_MASK 0x00000008L 7352*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_UPDATE_TAKEN__SHIFT 0x00000003 7353*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE_MASK 0x00000100L 7354*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_SURFACE_XDMA_PENDING_ENABLE__SHIFT 0x00000008 7355*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK 0x00010000L 7356*b843c749SSergey Zigachev #define GRPH_UPDATE__GRPH_UPDATE_LOCK__SHIFT 0x00000010 7357*b843c749SSergey Zigachev #define GRPH_X_END__GRPH_X_END_MASK 0x00007fffL 7358*b843c749SSergey Zigachev #define GRPH_X_END__GRPH_X_END__SHIFT 0x00000000 7359*b843c749SSergey Zigachev #define GRPH_X_START__GRPH_X_START_MASK 0x00003fffL 7360*b843c749SSergey Zigachev #define GRPH_X_START__GRPH_X_START__SHIFT 0x00000000 7361*b843c749SSergey Zigachev #define GRPH_Y_END__GRPH_Y_END_MASK 0x00007fffL 7362*b843c749SSergey Zigachev #define GRPH_Y_END__GRPH_Y_END__SHIFT 0x00000000 7363*b843c749SSergey Zigachev #define GRPH_Y_START__GRPH_Y_START_MASK 0x00003fffL 7364*b843c749SSergey Zigachev #define GRPH_Y_START__GRPH_Y_START__SHIFT 0x00000000 7365*b843c749SSergey Zigachev #define HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK 0xfffff000L 7366*b843c749SSergey Zigachev #define HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT 0x0000000c 7367*b843c749SSergey Zigachev #define HDMI_ACR_32_1__HDMI_ACR_N_32_MASK 0x000fffffL 7368*b843c749SSergey Zigachev #define HDMI_ACR_32_1__HDMI_ACR_N_32__SHIFT 0x00000000 7369*b843c749SSergey Zigachev #define HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK 0xfffff000L 7370*b843c749SSergey Zigachev #define HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT 0x0000000c 7371*b843c749SSergey Zigachev #define HDMI_ACR_44_1__HDMI_ACR_N_44_MASK 0x000fffffL 7372*b843c749SSergey Zigachev #define HDMI_ACR_44_1__HDMI_ACR_N_44__SHIFT 0x00000000 7373*b843c749SSergey Zigachev #define HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK 0xfffff000L 7374*b843c749SSergey Zigachev #define HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT 0x0000000c 7375*b843c749SSergey Zigachev #define HDMI_ACR_48_1__HDMI_ACR_N_48_MASK 0x000fffffL 7376*b843c749SSergey Zigachev #define HDMI_ACR_48_1__HDMI_ACR_N_48__SHIFT 0x00000000 7377*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY_MASK 0x80000000L 7378*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUDIO_PRIORITY__SHIFT 0x0000001f 7379*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK 0x00001000L 7380*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND__SHIFT 0x0000000c 7381*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT_MASK 0x00000002L 7382*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_CONT__SHIFT 0x00000001 7383*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE_MASK 0x00070000L 7384*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE__SHIFT 0x00000010 7385*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT_MASK 0x00000030L 7386*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SELECT__SHIFT 0x00000004 7387*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND_MASK 0x00000001L 7388*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SEND__SHIFT 0x00000000 7389*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK 0x00000100L 7390*b843c749SSergey Zigachev #define HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE__SHIFT 0x00000008 7391*b843c749SSergey Zigachev #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS_MASK 0xfffff000L 7392*b843c749SSergey Zigachev #define HDMI_ACR_STATUS_0__HDMI_ACR_CTS__SHIFT 0x0000000c 7393*b843c749SSergey Zigachev #define HDMI_ACR_STATUS_1__HDMI_ACR_N_MASK 0x000fffffL 7394*b843c749SSergey Zigachev #define HDMI_ACR_STATUS_1__HDMI_ACR_N__SHIFT 0x00000000 7395*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN_MASK 0x00000030L 7396*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT 0x00000004 7397*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE_MASK 0x001f0000L 7398*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT 0x00000010 7399*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS_MASK 0x00000100L 7400*b843c749SSergey Zigachev #define HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_SEND_MAX_PACKETS__SHIFT 0x00000008 7401*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK 0x30000000L 7402*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT 0x0000001c 7403*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK 0x01000000L 7404*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE__SHIFT 0x00000018 7405*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_ERROR_ACK_MASK 0x00000100L 7406*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_ERROR_ACK__SHIFT 0x00000008 7407*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_ERROR_MASK_MASK 0x00000200L 7408*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_ERROR_MASK__SHIFT 0x00000009 7409*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_KEEPOUT_MODE_MASK 0x00000001L 7410*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_KEEPOUT_MODE__SHIFT 0x00000000 7411*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION_MASK 0x00000010L 7412*b843c749SSergey Zigachev #define HDMI_CONTROL__HDMI_PACKET_GEN_VERSION__SHIFT 0x00000004 7413*b843c749SSergey Zigachev #define HDMI_GC__HDMI_DEFAULT_PHASE_MASK 0x00000010L 7414*b843c749SSergey Zigachev #define HDMI_GC__HDMI_DEFAULT_PHASE__SHIFT 0x00000004 7415*b843c749SSergey Zigachev #define HDMI_GC__HDMI_GC_AVMUTE_CONT_MASK 0x00000004L 7416*b843c749SSergey Zigachev #define HDMI_GC__HDMI_GC_AVMUTE_CONT__SHIFT 0x00000002 7417*b843c749SSergey Zigachev #define HDMI_GC__HDMI_GC_AVMUTE_MASK 0x00000001L 7418*b843c749SSergey Zigachev #define HDMI_GC__HDMI_GC_AVMUTE__SHIFT 0x00000000 7419*b843c749SSergey Zigachev #define HDMI_GC__HDMI_PACKING_PHASE_MASK 0x00000f00L 7420*b843c749SSergey Zigachev #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE_MASK 0x00001000L 7421*b843c749SSergey Zigachev #define HDMI_GC__HDMI_PACKING_PHASE_OVERRIDE__SHIFT 0x0000000c 7422*b843c749SSergey Zigachev #define HDMI_GC__HDMI_PACKING_PHASE__SHIFT 0x00000008 7423*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT_MASK 0x00000002L 7424*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_CONT__SHIFT 0x00000001 7425*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE_MASK 0x003f0000L 7426*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_LINE__SHIFT 0x00000010 7427*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND_MASK 0x00000001L 7428*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC0_SEND__SHIFT 0x00000000 7429*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT_MASK 0x00000020L 7430*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_CONT__SHIFT 0x00000005 7431*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE_MASK 0x3f000000L 7432*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_LINE__SHIFT 0x00000018 7433*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND_MASK 0x00000010L 7434*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL0__HDMI_GENERIC1_SEND__SHIFT 0x00000004 7435*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT_MASK 0x00000002L 7436*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_CONT__SHIFT 0x00000001 7437*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE_MASK 0x003f0000L 7438*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_LINE__SHIFT 0x00000010 7439*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND_MASK 0x00000001L 7440*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC2_SEND__SHIFT 0x00000000 7441*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT_MASK 0x00000020L 7442*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_CONT__SHIFT 0x00000005 7443*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE_MASK 0x3f000000L 7444*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_LINE__SHIFT 0x00000018 7445*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND_MASK 0x00000010L 7446*b843c749SSergey Zigachev #define HDMI_GENERIC_PACKET_CONTROL1__HDMI_GENERIC3_SEND__SHIFT 0x00000004 7447*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK 0x00000020L 7448*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT__SHIFT 0x00000005 7449*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK 0x00000010L 7450*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND__SHIFT 0x00000004 7451*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK 0x00000002L 7452*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT__SHIFT 0x00000001 7453*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK 0x00000001L 7454*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND__SHIFT 0x00000000 7455*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT_MASK 0x00000200L 7456*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_CONT__SHIFT 0x00000009 7457*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND_MASK 0x00000100L 7458*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL0__HDMI_MPEG_INFO_SEND__SHIFT 0x00000008 7459*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE_MASK 0x00003f00L 7460*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT 0x00000008 7461*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK 0x0000003fL 7462*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT 0x00000000 7463*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE_MASK 0x003f0000L 7464*b843c749SSergey Zigachev #define HDMI_INFOFRAME_CONTROL1__HDMI_MPEG_INFO_LINE__SHIFT 0x00000010 7465*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE_MASK 0x00000001L 7466*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_ACTIVE_AVMUTE__SHIFT 0x00000000 7467*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR_MASK 0x00010000L 7468*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_AUDIO_PACKET_ERROR__SHIFT 0x00000010 7469*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_ERROR_INT_MASK 0x08000000L 7470*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_ERROR_INT__SHIFT 0x0000001b 7471*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR_MASK 0x00100000L 7472*b843c749SSergey Zigachev #define HDMI_STATUS__HDMI_VBI_PACKET_ERROR__SHIFT 0x00000014 7473*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK 0x00000020L 7474*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT__SHIFT 0x00000005 7475*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK 0x00000010L 7476*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND__SHIFT 0x00000004 7477*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT_MASK 0x00000200L 7478*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_CONT__SHIFT 0x00000009 7479*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE_MASK 0x003f0000L 7480*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_LINE__SHIFT 0x00000010 7481*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND_MASK 0x00000100L 7482*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_ISRC_SEND__SHIFT 0x00000008 7483*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK 0x00000001L 7484*b843c749SSergey Zigachev #define HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND__SHIFT 0x00000000 7485*b843c749SSergey Zigachev #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 7486*b843c749SSergey Zigachev #define IDDCCIF02_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 7487*b843c749SSergey Zigachev #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E_MASK 0xffffffffL 7488*b843c749SSergey Zigachev #define IDDCCIF04_DBG_DCCIF_E__DBG_DCCIF_E__SHIFT 0x00000000 7489*b843c749SSergey Zigachev #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F_MASK 0xffffffffL 7490*b843c749SSergey Zigachev #define IDDCCIF05_DBG_DCCIF_F__DBG_DCCIF_F__SHIFT 0x00000000 7491*b843c749SSergey Zigachev #define INPUT_CSC_C11_C12__INPUT_CSC_C11_MASK 0x0000ffffL 7492*b843c749SSergey Zigachev #define INPUT_CSC_C11_C12__INPUT_CSC_C11__SHIFT 0x00000000 7493*b843c749SSergey Zigachev #define INPUT_CSC_C11_C12__INPUT_CSC_C12_MASK 0xffff0000L 7494*b843c749SSergey Zigachev #define INPUT_CSC_C11_C12__INPUT_CSC_C12__SHIFT 0x00000010 7495*b843c749SSergey Zigachev #define INPUT_CSC_C13_C14__INPUT_CSC_C13_MASK 0x0000ffffL 7496*b843c749SSergey Zigachev #define INPUT_CSC_C13_C14__INPUT_CSC_C13__SHIFT 0x00000000 7497*b843c749SSergey Zigachev #define INPUT_CSC_C13_C14__INPUT_CSC_C14_MASK 0xffff0000L 7498*b843c749SSergey Zigachev #define INPUT_CSC_C13_C14__INPUT_CSC_C14__SHIFT 0x00000010 7499*b843c749SSergey Zigachev #define INPUT_CSC_C21_C22__INPUT_CSC_C21_MASK 0x0000ffffL 7500*b843c749SSergey Zigachev #define INPUT_CSC_C21_C22__INPUT_CSC_C21__SHIFT 0x00000000 7501*b843c749SSergey Zigachev #define INPUT_CSC_C21_C22__INPUT_CSC_C22_MASK 0xffff0000L 7502*b843c749SSergey Zigachev #define INPUT_CSC_C21_C22__INPUT_CSC_C22__SHIFT 0x00000010 7503*b843c749SSergey Zigachev #define INPUT_CSC_C23_C24__INPUT_CSC_C23_MASK 0x0000ffffL 7504*b843c749SSergey Zigachev #define INPUT_CSC_C23_C24__INPUT_CSC_C23__SHIFT 0x00000000 7505*b843c749SSergey Zigachev #define INPUT_CSC_C23_C24__INPUT_CSC_C24_MASK 0xffff0000L 7506*b843c749SSergey Zigachev #define INPUT_CSC_C23_C24__INPUT_CSC_C24__SHIFT 0x00000010 7507*b843c749SSergey Zigachev #define INPUT_CSC_C31_C32__INPUT_CSC_C31_MASK 0x0000ffffL 7508*b843c749SSergey Zigachev #define INPUT_CSC_C31_C32__INPUT_CSC_C31__SHIFT 0x00000000 7509*b843c749SSergey Zigachev #define INPUT_CSC_C31_C32__INPUT_CSC_C32_MASK 0xffff0000L 7510*b843c749SSergey Zigachev #define INPUT_CSC_C31_C32__INPUT_CSC_C32__SHIFT 0x00000010 7511*b843c749SSergey Zigachev #define INPUT_CSC_C33_C34__INPUT_CSC_C33_MASK 0x0000ffffL 7512*b843c749SSergey Zigachev #define INPUT_CSC_C33_C34__INPUT_CSC_C33__SHIFT 0x00000000 7513*b843c749SSergey Zigachev #define INPUT_CSC_C33_C34__INPUT_CSC_C34_MASK 0xffff0000L 7514*b843c749SSergey Zigachev #define INPUT_CSC_C33_C34__INPUT_CSC_C34__SHIFT 0x00000010 7515*b843c749SSergey Zigachev #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE_MASK 0x00000003L 7516*b843c749SSergey Zigachev #define INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT 0x00000000 7517*b843c749SSergey Zigachev #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE_MASK 0x00000030L 7518*b843c749SSergey Zigachev #define INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT 0x00000004 7519*b843c749SSergey Zigachev #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE_MASK 0x00000003L 7520*b843c749SSergey Zigachev #define INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT 0x00000000 7521*b843c749SSergey Zigachev #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE_MASK 0x00000030L 7522*b843c749SSergey Zigachev #define INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT 0x00000004 7523*b843c749SSergey Zigachev #define KEY_CONTROL__GRPH_OVL_HALF_BLEND_MASK 0x10000000L 7524*b843c749SSergey Zigachev #define KEY_CONTROL__GRPH_OVL_HALF_BLEND__SHIFT 0x0000001c 7525*b843c749SSergey Zigachev #define KEY_CONTROL__KEY_MODE_MASK 0x00000006L 7526*b843c749SSergey Zigachev #define KEY_CONTROL__KEY_MODE__SHIFT 0x00000001 7527*b843c749SSergey Zigachev #define KEY_CONTROL__KEY_SELECT_MASK 0x00000001L 7528*b843c749SSergey Zigachev #define KEY_CONTROL__KEY_SELECT__SHIFT 0x00000000 7529*b843c749SSergey Zigachev #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH_MASK 0xffff0000L 7530*b843c749SSergey Zigachev #define KEY_RANGE_ALPHA__KEY_ALPHA_HIGH__SHIFT 0x00000010 7531*b843c749SSergey Zigachev #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW_MASK 0x0000ffffL 7532*b843c749SSergey Zigachev #define KEY_RANGE_ALPHA__KEY_ALPHA_LOW__SHIFT 0x00000000 7533*b843c749SSergey Zigachev #define KEY_RANGE_BLUE__KEY_BLUE_HIGH_MASK 0xffff0000L 7534*b843c749SSergey Zigachev #define KEY_RANGE_BLUE__KEY_BLUE_HIGH__SHIFT 0x00000010 7535*b843c749SSergey Zigachev #define KEY_RANGE_BLUE__KEY_BLUE_LOW_MASK 0x0000ffffL 7536*b843c749SSergey Zigachev #define KEY_RANGE_BLUE__KEY_BLUE_LOW__SHIFT 0x00000000 7537*b843c749SSergey Zigachev #define KEY_RANGE_GREEN__KEY_GREEN_HIGH_MASK 0xffff0000L 7538*b843c749SSergey Zigachev #define KEY_RANGE_GREEN__KEY_GREEN_HIGH__SHIFT 0x00000010 7539*b843c749SSergey Zigachev #define KEY_RANGE_GREEN__KEY_GREEN_LOW_MASK 0x0000ffffL 7540*b843c749SSergey Zigachev #define KEY_RANGE_GREEN__KEY_GREEN_LOW__SHIFT 0x00000000 7541*b843c749SSergey Zigachev #define KEY_RANGE_RED__KEY_RED_HIGH_MASK 0xffff0000L 7542*b843c749SSergey Zigachev #define KEY_RANGE_RED__KEY_RED_HIGH__SHIFT 0x00000010 7543*b843c749SSergey Zigachev #define KEY_RANGE_RED__KEY_RED_LOW_MASK 0x0000ffffL 7544*b843c749SSergey Zigachev #define KEY_RANGE_RED__KEY_RED_LOW__SHIFT 0x00000000 7545*b843c749SSergey Zigachev #define LB_DEBUG2__LB_DEBUG2_MASK 0xffffffffL 7546*b843c749SSergey Zigachev #define LB_DEBUG2__LB_DEBUG2__SHIFT 0x00000000 7547*b843c749SSergey Zigachev #define LB_DEBUG__LB_DEBUG_MASK 0xffffffffL 7548*b843c749SSergey Zigachev #define LB_DEBUG__LB_DEBUG__SHIFT 0x00000000 7549*b843c749SSergey Zigachev #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT_MASK 0x00000001L 7550*b843c749SSergey Zigachev #define LB_NO_OUTSTANDING_REQ_STATUS__LB_NO_OUTSTANDING_REQ_STAT__SHIFT 0x00000000 7551*b843c749SSergey Zigachev #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2_MASK 0x00000010L 7552*b843c749SSergey Zigachev #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL2__SHIFT 0x00000004 7553*b843c749SSergey Zigachev #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL_MASK 0x00000003L 7554*b843c749SSergey Zigachev #define LB_SYNC_RESET_SEL__LB_SYNC_RESET_SEL__SHIFT 0x00000000 7555*b843c749SSergey Zigachev #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA_MASK 0xffffffffL 7556*b843c749SSergey Zigachev #define LB_TEST_DEBUG_DATA__LB_TEST_DEBUG_DATA__SHIFT 0x00000000 7557*b843c749SSergey Zigachev #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX_MASK 0x000000ffL 7558*b843c749SSergey Zigachev #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_INDEX__SHIFT 0x00000000 7559*b843c749SSergey Zigachev #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7560*b843c749SSergey Zigachev #define LB_TEST_DEBUG_INDEX__LB_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7561*b843c749SSergey Zigachev #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS_MASK 0x00000001L 7562*b843c749SSergey Zigachev #define LIGHT_SLEEP_CNTL__LIGHT_SLEEP_DIS__SHIFT 0x00000000 7563*b843c749SSergey Zigachev #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS_MASK 0x00000100L 7564*b843c749SSergey Zigachev #define LIGHT_SLEEP_CNTL__MEM_SHUTDOWN_DIS__SHIFT 0x00000008 7565*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE_MASK 0x00000001L 7566*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ENABLE__SHIFT 0x00000000 7567*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE_MASK 0x00000018L 7568*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_MODE__SHIFT 0x00000003 7569*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS_MASK 0x00000700L 7570*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_BANKS__SHIFT 0x00000008 7571*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES_MASK 0x000000e0L 7572*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_NUM_PIPES__SHIFT 0x00000005 7573*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE_MASK 0x00000800L 7574*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_PIPE_INTERLEAVE_SIZE__SHIFT 0x0000000b 7575*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE_MASK 0x00007000L 7576*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROW_SIZE__SHIFT 0x0000000c 7577*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN_MASK 0x0fff0000L 7578*b843c749SSergey Zigachev #define LOW_POWER_TILING_CONTROL__LOW_POWER_TILING_ROWS_PER_CHAN__SHIFT 0x00000010 7579*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE_MASK 0x00000001L 7580*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_24BIT_ENABLE__SHIFT 0x00000000 7581*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT_MASK 0x00000010L 7582*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_24BIT_FORMAT__SHIFT 0x00000004 7583*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE_MASK 0x00000100L 7584*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_DE__SHIFT 0x00000008 7585*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS_MASK 0x00000400L 7586*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_HS__SHIFT 0x0000000a 7587*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS_MASK 0x00000200L 7588*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_CHAN_VS__SHIFT 0x00000009 7589*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS_MASK 0x00007000L 7590*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_2ND_LINK_CNTL_BITS__SHIFT 0x0000000c 7591*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_DTMG_POL_MASK 0x00040000L 7592*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_DTMG_POL__SHIFT 0x00000012 7593*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_FP_POL_MASK 0x00010000L 7594*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_FP_POL__SHIFT 0x00000010 7595*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_LP_POL_MASK 0x00020000L 7596*b843c749SSergey Zigachev #define LVDS_DATA_CNTL__LVDS_LP_POL__SHIFT 0x00000011 7597*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_MASK 0x01000000L 7598*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD_MASK 0x02000000L 7599*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_OVRD__SHIFT 0x00000019 7600*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL_MASK 0x04000000L 7601*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON_POL__SHIFT 0x0000001a 7602*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_BLON__SHIFT 0x00000018 7603*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_MASK 0x00010000L 7604*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD_MASK 0x00020000L 7605*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_OVRD__SHIFT 0x00000011 7606*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL_MASK 0x00040000L 7607*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON_POL__SHIFT 0x00000012 7608*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_DIGON__SHIFT 0x00000010 7609*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN_MASK 0x00000002L 7610*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_EN__SHIFT 0x00000001 7611*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN_MASK 0x00000001L 7612*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_EN__SHIFT 0x00000000 7613*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE_MASK 0x00000010L 7614*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_PWRSEQ_TARGET_STATE__SHIFT 0x00000004 7615*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_MASK 0x00000100L 7616*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD_MASK 0x00000200L 7617*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_OVRD__SHIFT 0x00000009 7618*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL_MASK 0x00000400L 7619*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN_POL__SHIFT 0x0000000a 7620*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_CNTL__LVTMA_SYNCEN__SHIFT 0x00000008 7621*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1_MASK 0x00ff0000L 7622*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY1__SHIFT 0x00000010 7623*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2_MASK 0xff000000L 7624*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRDN_DELAY2__SHIFT 0x00000018 7625*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1_MASK 0x000000ffL 7626*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY1__SHIFT 0x00000000 7627*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2_MASK 0x0000ff00L 7628*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY1__LVTMA_PWRUP_DELAY2__SHIFT 0x00000008 7629*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3_MASK 0x00ff0000L 7630*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_DELAY3__SHIFT 0x00000010 7631*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH_MASK 0x000000ffL 7632*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRDN_MIN_LENGTH__SHIFT 0x00000000 7633*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3_MASK 0x0000ff00L 7634*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_PWRUP_DELAY3__SHIFT 0x00000008 7635*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN_MASK 0x01000000L 7636*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_DELAY2__LVTMA_VARY_BL_OVERRIDE_EN__SHIFT 0x00000018 7637*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV_MASK 0xffff0000L 7638*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_REF_DIV__BL_PWM_REF_DIV__SHIFT 0x00000010 7639*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV_MASK 0x00000fffL 7640*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_REF_DIV__LVTMA_PWRSEQ_REF_DIV__SHIFT 0x00000000 7641*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON_MASK 0x00000008L 7642*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_BLON__SHIFT 0x00000003 7643*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON_MASK 0x00000002L 7644*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DIGON__SHIFT 0x00000001 7645*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE_MASK 0x00000010L 7646*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_DONE__SHIFT 0x00000004 7647*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE_MASK 0x00000f00L 7648*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_STATE__SHIFT 0x00000008 7649*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN_MASK 0x00000004L 7650*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_SYNCEN__SHIFT 0x00000002 7651*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R_MASK 0x00000001L 7652*b843c749SSergey Zigachev #define LVTMA_PWRSEQ_STATE__LVTMA_PWRSEQ_TARGET_STATE_R__SHIFT 0x00000000 7653*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 7654*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 7655*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 7656*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 7657*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 7658*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 7659*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3_MASK 0xff000000L 7660*b843c749SSergey Zigachev #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 7661*b843c749SSergey Zigachev #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK 0x00000001L 7662*b843c749SSergey Zigachev #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT__SHIFT 0x00000000 7663*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 7664*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 7665*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 7666*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 7667*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 7668*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 7669*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 7670*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG1__MASTER_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 7671*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 7672*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 7673*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 7674*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 7675*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 7676*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 7677*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 7678*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG2__MASTER_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 7679*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 7680*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 7681*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 7682*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 7683*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 7684*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 7685*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 7686*b843c749SSergey Zigachev #define MASTER_COMM_DATA_REG3__MASTER_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 7687*b843c749SSergey Zigachev #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK_MASK 0x00000100L 7688*b843c749SSergey Zigachev #define MASTER_UPDATE_LOCK__GSL_CONTROL_MASTER_UPDATE_LOCK__SHIFT 0x00000008 7689*b843c749SSergey Zigachev #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK_MASK 0x00000001L 7690*b843c749SSergey Zigachev #define MASTER_UPDATE_LOCK__MASTER_UPDATE_LOCK__SHIFT 0x00000000 7691*b843c749SSergey Zigachev #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE_MASK 0x00030000L 7692*b843c749SSergey Zigachev #define MASTER_UPDATE_MODE__MASTER_UPDATE_INTERLACED_MODE__SHIFT 0x00000010 7693*b843c749SSergey Zigachev #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE_MASK 0x00000007L 7694*b843c749SSergey Zigachev #define MASTER_UPDATE_MODE__MASTER_UPDATE_MODE__SHIFT 0x00000000 7695*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR_MASK 0x00000010L 7696*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_CLEAR__SHIFT 0x00000004 7697*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED_MASK 0x00000001L 7698*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__DMIF_RDRET_NACK_OCCURRED__SHIFT 0x00000000 7699*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR_MASK 0x00100000L 7700*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_CLEAR__SHIFT 0x00000014 7701*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED_MASK 0x00010000L 7702*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_RDRET_NACK_OCCURRED__SHIFT 0x00000010 7703*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR_MASK 0x10000000L 7704*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_CLEAR__SHIFT 0x0000001c 7705*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED_MASK 0x01000000L 7706*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__MCIF_WRRET_NACK_OCCURRED__SHIFT 0x00000018 7707*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR_MASK 0x00001000L 7708*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_CLEAR__SHIFT 0x0000000c 7709*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED_MASK 0x00000100L 7710*b843c749SSergey Zigachev #define MC_DC_INTERFACE_NACK_STATUS__VIP_WRRET_NACK_OCCURRED__SHIFT 0x00000008 7711*b843c749SSergey Zigachev #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE_MASK 0x00000010L 7712*b843c749SSergey Zigachev #define MCIF_CONTROL__ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000004 7713*b843c749SSergey Zigachev #define MCIF_CONTROL__LOW_READ_URG_LEVEL_MASK 0x00ff0000L 7714*b843c749SSergey Zigachev #define MCIF_CONTROL__LOW_READ_URG_LEVEL__SHIFT 0x00000010 7715*b843c749SSergey Zigachev #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY_MASK 0x3f000000L 7716*b843c749SSergey Zigachev #define MCIF_CONTROL__MC_CLEAN_DEASSERT_LATENCY__SHIFT 0x00000018 7717*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_BUFF_SIZE_MASK 0x00000003L 7718*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_BUFF_SIZE__SHIFT 0x00000000 7719*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE_MASK 0x40000000L 7720*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_ENABLE__SHIFT 0x0000001e 7721*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY_MASK 0x80000000L 7722*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_MC_LATENCY_COUNTER_URGENT_ONLY__SHIFT 0x0000001f 7723*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL_MASK 0x0000f000L 7724*b843c749SSergey Zigachev #define MCIF_CONTROL__MCIF_SLOW_REQ_INTERVAL__SHIFT 0x0000000c 7725*b843c749SSergey Zigachev #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE_MASK 0x00000100L 7726*b843c749SSergey Zigachev #define MCIF_CONTROL__PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000008 7727*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS_MASK 0x00000001L 7728*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_DIS__SHIFT 0x00000000 7729*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE_MASK 0x00000030L 7730*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_MODE__SHIFT 0x00000004 7731*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE_MASK 0x00070000L 7732*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_PIPE__SHIFT 0x00000010 7733*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE_MASK 0x00007f00L 7734*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_SIZE__SHIFT 0x00000008 7735*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE_MASK 0x00180000L 7736*b843c749SSergey Zigachev #define MCIF_MEM_CONTROL__MCIFMEM_CACHE_TYPE__SHIFT 0x00000013 7737*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA_MASK 0xffffffffL 7738*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_DATA__MCIF_TEST_DEBUG_DATA__SHIFT 0x00000000 7739*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX_MASK 0x000000ffL 7740*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_INDEX__SHIFT 0x00000000 7741*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 7742*b843c749SSergey Zigachev #define MCIF_TEST_DEBUG_INDEX__MCIF_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 7743*b843c749SSergey Zigachev #define MCIF_VMID__MCIF_WR_VMID_MASK 0x0000000fL 7744*b843c749SSergey Zigachev #define MCIF_VMID__MCIF_WR_VMID__SHIFT 0x00000000 7745*b843c749SSergey Zigachev #define MCIF_VMID__VIP_WR_VMID_MASK 0x000000f0L 7746*b843c749SSergey Zigachev #define MCIF_VMID__VIP_WR_VMID__SHIFT 0x00000004 7747*b843c749SSergey Zigachev #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT_MASK 0x000000ffL 7748*b843c749SSergey Zigachev #define MCIF_WRITE_COMBINE_CONTROL__MCIF_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000000 7749*b843c749SSergey Zigachev #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT_MASK 0x0000ff00L 7750*b843c749SSergey Zigachev #define MCIF_WRITE_COMBINE_CONTROL__VIP_WRITE_COMBINE_TIMEOUT__SHIFT 0x00000008 7751*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7752*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7753*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV_MASK 0x0000007fL 7754*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__MICROSECOND_TIME_BASE_DIV__SHIFT 0x00000000 7755*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL_MASK 0x00020000L 7756*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_CLOCK_SOURCE_SEL__SHIFT 0x00000011 7757*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV_MASK 0x00007f00L 7758*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_DIV__SHIFT 0x00000008 7759*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL_MASK 0x00010000L 7760*b843c749SSergey Zigachev #define MICROSECOND_TIME_BASE_DIV__XTAL_REF_SEL__SHIFT 0x00000010 7761*b843c749SSergey Zigachev #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL_MASK 0x00100000L 7762*b843c749SSergey Zigachev #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL__SHIFT 0x00000014 7763*b843c749SSergey Zigachev #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV_MASK 0x0001ffffL 7764*b843c749SSergey Zigachev #define MILLISECOND_TIME_BASE_DIV__MILLISECOND_TIME_BASE_DIV__SHIFT 0x00000000 7765*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES_MASK 0x0000000fL 7766*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_NUM_ENTRIES__SHIFT 0x00000000 7767*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK_MASK 0x00001000L 7768*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_ACK__SHIFT 0x0000000c 7769*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG_MASK 0x00000100L 7770*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_FLAG__SHIFT 0x00000008 7771*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET_MASK 0x00000010L 7772*b843c749SSergey Zigachev #define MVP_AFR_FLIP_FIFO_CNTL__MVP_AFR_FLIP_FIFO_RESET__SHIFT 0x00000004 7773*b843c749SSergey Zigachev #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE_MASK 0x00000003L 7774*b843c749SSergey Zigachev #define MVP_AFR_FLIP_MODE__MVP_AFR_FLIP_MODE__SHIFT 0x00000000 7775*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B_MASK 0x3ff00000L 7776*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_B__SHIFT 0x00000014 7777*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G_MASK 0x000ffc00L 7778*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_G__SHIFT 0x0000000a 7779*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R_MASK 0x000003ffL 7780*b843c749SSergey Zigachev #define MVP_BLACK_KEYER__MVP_BLACK_KEYER_R__SHIFT 0x00000000 7781*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_30BPP_EN_MASK 0x10000000L 7782*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_30BPP_EN__SHIFT 0x0000001c 7783*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE_MASK 0x00000400L 7784*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_ARBITRATION_MODE_FOR_AFR_MANUAL_SWITCH_MODE__SHIFT 0x0000000a 7785*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_CHANNEL_CONTROL_MASK 0x00010000L 7786*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_CHANNEL_CONTROL__SHIFT 0x00000010 7787*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND_MASK 0x01000000L 7788*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_DISABLE_MSB_EXPAND__SHIFT 0x00000018 7789*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_EN_MASK 0x00000001L 7790*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_EN__SHIFT 0x00000000 7791*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION_MASK 0x00300000L 7792*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000014 7793*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_MODE_MASK 0x00000070L 7794*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_MODE__SHIFT 0x00000004 7795*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK_MASK 0x00000200L 7796*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_DELAY_UNTIL_END_OF_BLANK__SHIFT 0x00000009 7797*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL_MASK 0x00000100L 7798*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_MIXER_SLAVE_SEL__SHIFT 0x00000008 7799*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_RATE_CONTROL_MASK 0x00001000L 7800*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_RATE_CONTROL__SHIFT 0x0000000c 7801*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A_MASK 0x40000000L 7802*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_TERMINATION_CNTL_A__SHIFT 0x0000001e 7803*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B_MASK 0x80000000L 7804*b843c749SSergey Zigachev #define MVP_CONTROL1__MVP_TERMINATION_CNTL_B__SHIFT 0x0000001f 7805*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_DVOCNTL_MUX_MASK 0x00010000L 7806*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_DVOCNTL_MUX__SHIFT 0x00000010 7807*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN_MASK 0x00100000L 7808*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_FLOW_CONTROL_OUT_EN__SHIFT 0x00000014 7809*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUXA_CLK_SEL_MASK 0x00000100L 7810*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUXA_CLK_SEL__SHIFT 0x00000008 7811*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUXB_CLK_SEL_MASK 0x00001000L 7812*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUXB_CLK_SEL__SHIFT 0x0000000c 7813*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL_MASK 0x00000001L 7814*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL0_SEL__SHIFT 0x00000000 7815*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL_MASK 0x00000010L 7816*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_MUX_DE_DVOCNTL2_SEL__SHIFT 0x00000004 7817*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR_MASK 0x10000000L 7818*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_SWAP_AB_IN_DC_DDR__SHIFT 0x0000001c 7819*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN_MASK 0x01000000L 7820*b843c749SSergey Zigachev #define MVP_CONTROL2__MVP_SWAP_LOCK_OUT_EN__SHIFT 0x00000018 7821*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL_MASK 0x00000010L 7822*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_DDR_SC_AB_SEL__SHIFT 0x00000004 7823*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE_MASK 0x00000100L 7824*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_DDR_SC_B_START_MODE__SHIFT 0x00000008 7825*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN_MASK 0x00100000L 7826*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_CASCADE_EN__SHIFT 0x00000014 7827*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP_MASK 0x10000000L 7828*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_IN_CAP__SHIFT 0x0000001c 7829*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE_MASK 0x00001000L 7830*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ONE__SHIFT 0x0000000c 7831*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO_MASK 0x00010000L 7832*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_FLOW_CONTROL_OUT_FORCE_ZERO__SHIFT 0x00000010 7833*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES_MASK 0x00000001L 7834*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_RESET_IN_BETWEEN_FRAMES__SHIFT 0x00000000 7835*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_SWAP_48BIT_EN_MASK 0x01000000L 7836*b843c749SSergey Zigachev #define MVP_CONTROL3__MVP_SWAP_48BIT_EN__SHIFT 0x00000018 7837*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK_MASK 0x000000ffL 7838*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_BLUE_MASK__SHIFT 0x00000000 7839*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_CONT_EN_MASK 0x20000000L 7840*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_CONT_EN__SHIFT 0x0000001d 7841*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_EN_MASK 0x10000000L 7842*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_EN__SHIFT 0x0000001c 7843*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK_MASK 0x0000ff00L 7844*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_GREEN_MASK__SHIFT 0x00000008 7845*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_RED_MASK_MASK 0x00ff0000L 7846*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_CRC_RED_MASK__SHIFT 0x00000010 7847*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL_MASK 0x40000000L 7848*b843c749SSergey Zigachev #define MVP_CRC_CNTL__MVP_DC_DDR_CRC_EVEN_ODD_PIX_SEL__SHIFT 0x0000001e 7849*b843c749SSergey Zigachev #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT_MASK 0x0000ffffL 7850*b843c749SSergey Zigachev #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_BLUE_RESULT__SHIFT 0x00000000 7851*b843c749SSergey Zigachev #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT_MASK 0xffff0000L 7852*b843c749SSergey Zigachev #define MVP_CRC_RESULT_BLUE_GREEN__MVP_CRC_GREEN_RESULT__SHIFT 0x00000010 7853*b843c749SSergey Zigachev #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT_MASK 0x0000ffffL 7854*b843c749SSergey Zigachev #define MVP_CRC_RESULT_RED__MVP_CRC_RED_RESULT__SHIFT 0x00000000 7855*b843c749SSergey Zigachev #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7856*b843c749SSergey Zigachev #define MVP_DEBUG_05__IDE0_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7857*b843c749SSergey Zigachev #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION_MASK 0x00000006L 7858*b843c749SSergey Zigachev #define MVP_DEBUG_09__IDE4_CRTC2_MVP_GPU_CHAIN_LOCATION__SHIFT 0x00000001 7859*b843c749SSergey Zigachev #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H_MASK 0x00000001L 7860*b843c749SSergey Zigachev #define MVP_DEBUG_12__IDEC_MVP_DATA_A_H__SHIFT 0x00000000 7861*b843c749SSergey Zigachev #define MVP_DEBUG_12__IDEC_MVP_DATA_A_MASK 0x01fffffeL 7862*b843c749SSergey Zigachev #define MVP_DEBUG_12__IDEC_MVP_DATA_A__SHIFT 0x00000001 7863*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_MVP_DATA_B_H_MASK 0x00000001L 7864*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_MVP_DATA_B_H__SHIFT 0x00000000 7865*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_MVP_DATA_B_MASK 0x01fffffeL 7866*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_MVP_DATA_B__SHIFT 0x00000001 7867*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B_MASK 0x04000000L 7868*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000001a 7869*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_START_READ_B_MASK 0x02000000L 7870*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_START_READ_B__SHIFT 0x00000019 7871*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_WRITE_ADD_B_MASK 0x38000000L 7872*b843c749SSergey Zigachev #define MVP_DEBUG_13__IDED_WRITE_ADD_B__SHIFT 0x0000001b 7873*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_CRC_PHASE_MASK 0x00100000L 7874*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_CRC_PHASE__SHIFT 0x00000014 7875*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A_MASK 0x00080000L 7876*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_CRTC1_CNTL_CAPTURE_START_A__SHIFT 0x00000013 7877*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_ADD_MASK 0x00000007L 7878*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_ADD__SHIFT 0x00000000 7879*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B_MASK 0x00020000L 7880*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_B__SHIFT 0x00000011 7881*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_DE_MASK 0x00010000L 7882*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_DE__SHIFT 0x00000010 7883*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE_MASK 0x00040000L 7884*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENABLE__SHIFT 0x00000012 7885*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B_MASK 0x00008000L 7886*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_B__SHIFT 0x0000000f 7887*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE_MASK 0x00004000L 7888*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_READ_FIFO_ENTRY_DE__SHIFT 0x0000000e 7889*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_INCR_WR_A_MASK 0x00000800L 7890*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_INCR_WR_A__SHIFT 0x0000000b 7891*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_INCR_WR_B_MASK 0x00001000L 7892*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_INCR_WR_B__SHIFT 0x0000000c 7893*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_READ_B_MASK 0x00000400L 7894*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_READ_B__SHIFT 0x0000000a 7895*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_READ_MASK 0x00000200L 7896*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_START_READ__SHIFT 0x00000009 7897*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE2FIFO_MASK 0x00002000L 7898*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE2FIFO__SHIFT 0x0000000d 7899*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE_ADD_A_MASK 0x00000038L 7900*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE_ADD_A__SHIFT 0x00000003 7901*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE_ADD_B_MASK 0x000001c0L 7902*b843c749SSergey Zigachev #define MVP_DEBUG_14__IDEE_WRITE_ADD_B__SHIFT 0x00000006 7903*b843c749SSergey Zigachev #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA_MASK 0xfffffff0L 7904*b843c749SSergey Zigachev #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WDATA__SHIFT 0x00000004 7905*b843c749SSergey Zigachev #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN_MASK 0x00000001L 7906*b843c749SSergey Zigachev #define MVP_DEBUG_15__IDEF_MVP_ASYNC_FIFO_WEN__SHIFT 0x00000000 7907*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT_MASK 0x00000008L 7908*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_FLOW_CONTROL_OUT__SHIFT 0x00000003 7909*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL_MASK 0x00000004L 7910*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_PAUSE_LEVEL__SHIFT 0x00000002 7911*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL_MASK 0x00000002L 7912*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_EXCEED_STOP_LEVEL__SHIFT 0x00000001 7913*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES_MASK 0x00000ff0L 7914*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_NUM_ENTRIES__SHIFT 0x00000004 7915*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW_MASK 0x00001000L 7916*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_OVERFLOW__SHIFT 0x0000000c 7917*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7918*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7919*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW_MASK 0x00002000L 7920*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_FIFO_UNDERFLOW__SHIFT 0x0000000d 7921*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR_MASK 0x00ff0000L 7922*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_READ_ADDR__SHIFT 0x00000010 7923*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR_MASK 0xff000000L 7924*b843c749SSergey Zigachev #define MVP_DEBUG_16__IDCC_MVP_ASYNC_WRITE_ADDR__SHIFT 0x00000018 7925*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE_MASK 0x00000002L 7926*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_PHASE__SHIFT 0x00000001 7927*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA_MASK 0xfffffffcL 7928*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_DATA__SHIFT 0x00000002 7929*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ_MASK 0x00000001L 7930*b843c749SSergey Zigachev #define MVP_DEBUG_17__IDCD_MVP_ASYNC_FIFO_READ__SHIFT 0x00000000 7931*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DEBUG_BITS_MASK 0xffffff00L 7932*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DEBUG_BITS__SHIFT 0x00000008 7933*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP_MASK 0x00000020L 7934*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_FIX_AFR_AUTO_VSYNC_FLIP__SHIFT 0x00000005 7935*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP_MASK 0x00000010L 7936*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_FIX_AFR_MANUAL_HSYNC_FLIP__SHIFT 0x00000004 7937*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY_MASK 0x00000080L 7938*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_DIS_READ_POINTER_RESET_DELAY__SHIFT 0x00000007 7939*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR_MASK 0x00000040L 7940*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_EN_FIX_AFR_MANUAL_SWITCH_IN_SFR__SHIFT 0x00000006 7941*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN_MASK 0x00000002L 7942*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_EN__SHIFT 0x00000001 7943*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL_MASK 0x00000008L 7944*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_FLOW_CONTROL_IN_SEL__SHIFT 0x00000003 7945*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN_MASK 0x00000001L 7946*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_SWAP_LOCK_IN_EN__SHIFT 0x00000000 7947*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL_MASK 0x00000004L 7948*b843c749SSergey Zigachev #define MVP_DEBUG__MVP_SWAP_LOCK_IN_SEL__SHIFT 0x00000002 7949*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT_MASK 0x00ff0000L 7950*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_CNT__SHIFT 0x00000010 7951*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM_MASK 0x0000ff00L 7952*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_PAUSE_SLAVE_WM__SHIFT 0x00000008 7953*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM_MASK 0x000000ffL 7954*b843c749SSergey Zigachev #define MVP_FIFO_CONTROL__MVP_STOP_SLAVE_WM__SHIFT 0x00000000 7955*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS_MASK 0x80000000L 7956*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_INT_STATUS__SHIFT 0x0000001f 7957*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK_MASK 0x40000000L 7958*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_ERROR_MASK__SHIFT 0x0000001e 7959*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL_MASK 0x000000ffL 7960*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_LEVEL__SHIFT 0x00000000 7961*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK_MASK 0x00010000L 7962*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_ACK__SHIFT 0x00000010 7963*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_MASK 0x00000100L 7964*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED_MASK 0x00001000L 7965*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW_OCCURRED__SHIFT 0x0000000c 7966*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_OVERFLOW__SHIFT 0x00000008 7967*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK_MASK 0x10000000L 7968*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_ACK__SHIFT 0x0000001c 7969*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_MASK 0x00100000L 7970*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED_MASK 0x01000000L 7971*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW_OCCURRED__SHIFT 0x00000018 7972*b843c749SSergey Zigachev #define MVP_FIFO_STATUS__MVP_FIFO_UNDERFLOW__SHIFT 0x00000014 7973*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE_MASK 0x40000000L 7974*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_AUTO_ENABLE__SHIFT 0x0000001e 7975*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MASK 0x007fff00L 7976*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE_MASK 0x00000003L 7977*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT_MODE__SHIFT 0x00000000 7978*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_INSERT__SHIFT 0x00000008 7979*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET_MASK 0x3f000000L 7980*b843c749SSergey Zigachev #define MVP_FLIP_LINE_NUM_INSERT__MVP_FLIP_LINE_NUM_OFFSET__SHIFT 0x00000018 7981*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL_MASK 0x00000001L 7982*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_IGNOR_INBAND_CNTL__SHIFT 0x00000000 7983*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP_MASK 0xffffff00L 7984*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_INBAND_CNTL_CHAR_CAP__SHIFT 0x00000008 7985*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN_MASK 0x00000010L 7986*b843c749SSergey Zigachev #define MVP_INBAND_CNTL_CAP__MVP_PASSING_INBAND_CNTL_EN__SHIFT 0x00000004 7987*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN_MASK 0x80000000L 7988*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_DATA_CHK_EN__SHIFT 0x0000001f 7989*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT_MASK 0x1fff0000L 7990*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_LINE_ERROR_CNT__SHIFT 0x00000010 7991*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT_MASK 0x00001fffL 7992*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL1__MVP_SLAVE_PIXEL_ERROR_CNT__SHIFT 0x00000000 7993*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_MASK 0x00001fffL 7994*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET_MASK 0x80000000L 7995*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT_RESET__SHIFT 0x0000001f 7996*b843c749SSergey Zigachev #define MVP_RECEIVE_CNT_CNTL2__MVP_SLAVE_FRAME_ERROR_CNT__SHIFT 0x00000000 7997*b843c749SSergey Zigachev #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED_MASK 0x1fff0000L 7998*b843c749SSergey Zigachev #define MVP_SLAVE_STATUS__MVP_SLAVE_LINES_PER_FRAME_RCVED__SHIFT 0x00000010 7999*b843c749SSergey Zigachev #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED_MASK 0x00001fffL 8000*b843c749SSergey Zigachev #define MVP_SLAVE_STATUS__MVP_SLAVE_PIXELS_PER_LINE_RCVED__SHIFT 0x00000000 8001*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA_MASK 0xffffffffL 8002*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_DATA__MVP_TEST_DEBUG_DATA__SHIFT 0x00000000 8003*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX_MASK 0x000000ffL 8004*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_INDEX__SHIFT 0x00000000 8005*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8006*b843c749SSergey Zigachev #define MVP_TEST_DEBUG_INDEX__MVP_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8007*b843c749SSergey Zigachev #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11_MASK 0x0000ffffL 8008*b843c749SSergey Zigachev #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C11__SHIFT 0x00000000 8009*b843c749SSergey Zigachev #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12_MASK 0xffff0000L 8010*b843c749SSergey Zigachev #define OUTPUT_CSC_C11_C12__OUTPUT_CSC_C12__SHIFT 0x00000010 8011*b843c749SSergey Zigachev #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13_MASK 0x0000ffffL 8012*b843c749SSergey Zigachev #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C13__SHIFT 0x00000000 8013*b843c749SSergey Zigachev #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14_MASK 0xffff0000L 8014*b843c749SSergey Zigachev #define OUTPUT_CSC_C13_C14__OUTPUT_CSC_C14__SHIFT 0x00000010 8015*b843c749SSergey Zigachev #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21_MASK 0x0000ffffL 8016*b843c749SSergey Zigachev #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C21__SHIFT 0x00000000 8017*b843c749SSergey Zigachev #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22_MASK 0xffff0000L 8018*b843c749SSergey Zigachev #define OUTPUT_CSC_C21_C22__OUTPUT_CSC_C22__SHIFT 0x00000010 8019*b843c749SSergey Zigachev #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23_MASK 0x0000ffffL 8020*b843c749SSergey Zigachev #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C23__SHIFT 0x00000000 8021*b843c749SSergey Zigachev #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24_MASK 0xffff0000L 8022*b843c749SSergey Zigachev #define OUTPUT_CSC_C23_C24__OUTPUT_CSC_C24__SHIFT 0x00000010 8023*b843c749SSergey Zigachev #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31_MASK 0x0000ffffL 8024*b843c749SSergey Zigachev #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C31__SHIFT 0x00000000 8025*b843c749SSergey Zigachev #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32_MASK 0xffff0000L 8026*b843c749SSergey Zigachev #define OUTPUT_CSC_C31_C32__OUTPUT_CSC_C32__SHIFT 0x00000010 8027*b843c749SSergey Zigachev #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33_MASK 0x0000ffffL 8028*b843c749SSergey Zigachev #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C33__SHIFT 0x00000000 8029*b843c749SSergey Zigachev #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34_MASK 0xffff0000L 8030*b843c749SSergey Zigachev #define OUTPUT_CSC_C33_C34__OUTPUT_CSC_C34__SHIFT 0x00000010 8031*b843c749SSergey Zigachev #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE_MASK 0x00000007L 8032*b843c749SSergey Zigachev #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT 0x00000000 8033*b843c749SSergey Zigachev #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE_MASK 0x00000070L 8034*b843c749SSergey Zigachev #define OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT 0x00000004 8035*b843c749SSergey Zigachev #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE_MASK 0x0000000fL 8036*b843c749SSergey Zigachev #define OUT_ROUND_CONTROL__OUT_ROUND_TRUNC_MODE__SHIFT 0x00000000 8037*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE_MASK 0x00010000L 8038*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_ADDRESS_TRANSLATION_ENABLE__SHIFT 0x00000010 8039*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_ARRAY_MODE_MASK 0x00f00000L 8040*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_ARRAY_MODE__SHIFT 0x00000014 8041*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_BANK_HEIGHT_MASK 0x00001800L 8042*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_BANK_HEIGHT__SHIFT 0x0000000b 8043*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_BANK_WIDTH_MASK 0x000000c0L 8044*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_BANK_WIDTH__SHIFT 0x00000006 8045*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE_MASK 0x01000000L 8046*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_COLOR_EXPANSION_MODE__SHIFT 0x00000018 8047*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_DEPTH_MASK 0x00000003L 8048*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_DEPTH__SHIFT 0x00000000 8049*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_FORMAT_MASK 0x00000700L 8050*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_FORMAT__SHIFT 0x00000008 8051*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT_MASK 0x000c0000L 8052*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_MACRO_TILE_ASPECT__SHIFT 0x00000012 8053*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_NUM_BANKS_MASK 0x0000000cL 8054*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_NUM_BANKS__SHIFT 0x00000002 8055*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_PIPE_CONFIG_MASK 0x3e000000L 8056*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_PIPE_CONFIG__SHIFT 0x00000019 8057*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE_MASK 0x00020000L 8058*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_PRIVILEGED_ACCESS_ENABLE__SHIFT 0x00000011 8059*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_TILE_SPLIT_MASK 0x0000e000L 8060*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_TILE_SPLIT__SHIFT 0x0000000d 8061*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_Z_MASK 0x00000030L 8062*b843c749SSergey Zigachev #define OVL_CONTROL1__OVL_Z__SHIFT 0x00000004 8063*b843c749SSergey Zigachev #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE_MASK 0x00000001L 8064*b843c749SSergey Zigachev #define OVL_CONTROL2__OVL_HALF_RESOLUTION_ENABLE__SHIFT 0x00000000 8065*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES_MASK 0x00000700L 8066*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_MIN_FREE_ENTRIES__SHIFT 0x00000008 8067*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_RESET_MASK 0x00000001L 8068*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_RESET__SHIFT 0x00000000 8069*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE_MASK 0x00000070L 8070*b843c749SSergey Zigachev #define OVL_DFQ_CONTROL__OVL_DFQ_SIZE__SHIFT 0x00000004 8071*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES_MASK 0x0000000fL 8072*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_NUM_ENTRIES__SHIFT 0x00000000 8073*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK_MASK 0x00000200L 8074*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_RESET_ACK__SHIFT 0x00000009 8075*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG_MASK 0x00000100L 8076*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_DFQ_RESET_FLAG__SHIFT 0x00000008 8077*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES_MASK 0x000000f0L 8078*b843c749SSergey Zigachev #define OVL_DFQ_STATUS__OVL_SECONDARY_DFQ_NUM_ENTRIES__SHIFT 0x00000004 8079*b843c749SSergey Zigachev #define OVL_ENABLE__OVL_ENABLE_MASK 0x00000001L 8080*b843c749SSergey Zigachev #define OVL_ENABLE__OVL_ENABLE__SHIFT 0x00000000 8081*b843c749SSergey Zigachev #define OVL_ENABLE__OVLSCL_EN_MASK 0x00000100L 8082*b843c749SSergey Zigachev #define OVL_ENABLE__OVLSCL_EN__SHIFT 0x00000008 8083*b843c749SSergey Zigachev #define OVL_END__OVL_X_END_MASK 0x7fff0000L 8084*b843c749SSergey Zigachev #define OVL_END__OVL_X_END__SHIFT 0x00000010 8085*b843c749SSergey Zigachev #define OVL_END__OVL_Y_END_MASK 0x00007fffL 8086*b843c749SSergey Zigachev #define OVL_END__OVL_Y_END__SHIFT 0x00000000 8087*b843c749SSergey Zigachev #define OVL_PITCH__OVL_PITCH_MASK 0x00007fffL 8088*b843c749SSergey Zigachev #define OVL_PITCH__OVL_PITCH__SHIFT 0x00000000 8089*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB_MASK 0x000003ffL 8090*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_BCB__SHIFT 0x00000000 8091*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY_MASK 0x000ffc00L 8092*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_GY__SHIFT 0x0000000a 8093*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR_MASK 0x3ff00000L 8094*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_BLACK_COLOR_RCR__SHIFT 0x00000014 8095*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL_MASK 0x80000000L 8096*b843c749SSergey Zigachev #define OVLSCL_EDGE_PIXEL_CNTL__OVLSCL_EDGE_PIXEL_SEL__SHIFT 0x0000001f 8097*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8098*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS_HIGH__OVL_SECONDARY_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8099*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE_MASK 0x00000001L 8100*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_DFQ_ENABLE__SHIFT 0x00000000 8101*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS_MASK 0xffffff00L 8102*b843c749SSergey Zigachev #define OVL_SECONDARY_SURFACE_ADDRESS__OVL_SECONDARY_SURFACE_ADDRESS__SHIFT 0x00000008 8103*b843c749SSergey Zigachev #define OVL_START__OVL_X_START_MASK 0x3fff0000L 8104*b843c749SSergey Zigachev #define OVL_START__OVL_X_START__SHIFT 0x00000010 8105*b843c749SSergey Zigachev #define OVL_START__OVL_Y_START_MASK 0x00003fffL 8106*b843c749SSergey Zigachev #define OVL_START__OVL_Y_START__SHIFT 0x00000000 8107*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING_MASK 0x00010000L 8108*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_PRIMARY_SURFACE_PENDING__SHIFT 0x00000010 8109*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING_MASK 0x00020000L 8110*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_SECONDARY_SURFACE_PENDING__SHIFT 0x00000011 8111*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN_MASK 0x00000001L 8112*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_EN__SHIFT 0x00000000 8113*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE_MASK 0x00000300L 8114*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_FLIP_MODE__SHIFT 0x00000008 8115*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE_MASK 0x10000000L 8116*b843c749SSergey Zigachev #define OVL_STEREOSYNC_FLIP__OVL_STEREOSYNC_SELECT_DISABLE__SHIFT 0x0000001c 8117*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE_MASK 0x000000ffL 8118*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_HIGH_INUSE__OVL_SURFACE_ADDRESS_HIGH_INUSE__SHIFT 0x00000000 8119*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH_MASK 0x000000ffL 8120*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_HIGH__OVL_SURFACE_ADDRESS_HIGH__SHIFT 0x00000000 8121*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE_MASK 0xffffff00L 8122*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS_INUSE__OVL_SURFACE_ADDRESS_INUSE__SHIFT 0x00000008 8123*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE_MASK 0x00000001L 8124*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS__OVL_DFQ_ENABLE__SHIFT 0x00000000 8125*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS_MASK 0xffffff00L 8126*b843c749SSergey Zigachev #define OVL_SURFACE_ADDRESS__OVL_SURFACE_ADDRESS__SHIFT 0x00000008 8127*b843c749SSergey Zigachev #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X_MASK 0x00003fffL 8128*b843c749SSergey Zigachev #define OVL_SURFACE_OFFSET_X__OVL_SURFACE_OFFSET_X__SHIFT 0x00000000 8129*b843c749SSergey Zigachev #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y_MASK 0x00003fffL 8130*b843c749SSergey Zigachev #define OVL_SURFACE_OFFSET_Y__OVL_SURFACE_OFFSET_Y__SHIFT 0x00000000 8131*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR_MASK 0x00000c00L 8132*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_ALPHA_CROSSBAR__SHIFT 0x0000000a 8133*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR_MASK 0x00000300L 8134*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_BLUE_CROSSBAR__SHIFT 0x00000008 8135*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP_MASK 0x00000003L 8136*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_ENDIAN_SWAP__SHIFT 0x00000000 8137*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR_MASK 0x000000c0L 8138*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_GREEN_CROSSBAR__SHIFT 0x00000006 8139*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR_MASK 0x00000030L 8140*b843c749SSergey Zigachev #define OVL_SWAP_CNTL__OVL_RED_CROSSBAR__SHIFT 0x00000004 8141*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE_MASK 0x01000000L 8142*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_DISABLE_MULTIPLE_UPDATE__SHIFT 0x00000018 8143*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_LOCK_MASK 0x00010000L 8144*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_LOCK__SHIFT 0x00000010 8145*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_PENDING_MASK 0x00000001L 8146*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_PENDING__SHIFT 0x00000000 8147*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_TAKEN_MASK 0x00000002L 8148*b843c749SSergey Zigachev #define OVL_UPDATE__OVL_UPDATE_TAKEN__SHIFT 0x00000001 8149*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_RXSEL_MASK 0x00010000L 8150*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_RXSEL__SHIFT 0x00000010 8151*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_SLEWN_MASK 0x00001000L 8152*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_SLEWN__SHIFT 0x0000000c 8153*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_WAKE_MASK 0x00004000L 8154*b843c749SSergey Zigachev #define PHY_AUX_CNTL__AUX_PAD_WAKE__SHIFT 0x0000000e 8155*b843c749SSergey Zigachev #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8156*b843c749SSergey Zigachev #define PIPE0_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8157*b843c749SSergey Zigachev #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8158*b843c749SSergey Zigachev #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8159*b843c749SSergey Zigachev #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8160*b843c749SSergey Zigachev #define PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8161*b843c749SSergey Zigachev #define PIPE0_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8162*b843c749SSergey Zigachev #define PIPE0_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8163*b843c749SSergey Zigachev #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x00000001L 8164*b843c749SSergey Zigachev #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x00000000 8165*b843c749SSergey Zigachev #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x00000001L 8166*b843c749SSergey Zigachev #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x00000000 8167*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L 8168*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x0000001c 8169*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS_MASK 0xc0000000L 8170*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8171*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0x00ffffffL 8172*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x00000000 8173*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE_MASK 0x20000000L 8174*b843c749SSergey Zigachev #define PIPE0_PG_STATUS__PIPE0_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8175*b843c749SSergey Zigachev #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8176*b843c749SSergey Zigachev #define PIPE1_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8177*b843c749SSergey Zigachev #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8178*b843c749SSergey Zigachev #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8179*b843c749SSergey Zigachev #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8180*b843c749SSergey Zigachev #define PIPE1_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8181*b843c749SSergey Zigachev #define PIPE1_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8182*b843c749SSergey Zigachev #define PIPE1_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8183*b843c749SSergey Zigachev #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON_MASK 0x00000001L 8184*b843c749SSergey Zigachev #define PIPE1_PG_CONFIG__PIPE1_POWER_FORCEON__SHIFT 0x00000000 8185*b843c749SSergey Zigachev #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE_MASK 0x00000001L 8186*b843c749SSergey Zigachev #define PIPE1_PG_ENABLE__PIPE1_POWER_GATE__SHIFT 0x00000000 8187*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE_MASK 0x10000000L 8188*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_DESIRED_PWR_STATE__SHIFT 0x0000001c 8189*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS_MASK 0xc0000000L 8190*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8191*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA_MASK 0x00ffffffL 8192*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_PGFSM_READ_DATA__SHIFT 0x00000000 8193*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE_MASK 0x20000000L 8194*b843c749SSergey Zigachev #define PIPE1_PG_STATUS__PIPE1_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8195*b843c749SSergey Zigachev #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8196*b843c749SSergey Zigachev #define PIPE2_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8197*b843c749SSergey Zigachev #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8198*b843c749SSergey Zigachev #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8199*b843c749SSergey Zigachev #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8200*b843c749SSergey Zigachev #define PIPE2_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8201*b843c749SSergey Zigachev #define PIPE2_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8202*b843c749SSergey Zigachev #define PIPE2_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8203*b843c749SSergey Zigachev #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON_MASK 0x00000001L 8204*b843c749SSergey Zigachev #define PIPE2_PG_CONFIG__PIPE2_POWER_FORCEON__SHIFT 0x00000000 8205*b843c749SSergey Zigachev #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE_MASK 0x00000001L 8206*b843c749SSergey Zigachev #define PIPE2_PG_ENABLE__PIPE2_POWER_GATE__SHIFT 0x00000000 8207*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE_MASK 0x10000000L 8208*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_DESIRED_PWR_STATE__SHIFT 0x0000001c 8209*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS_MASK 0xc0000000L 8210*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8211*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA_MASK 0x00ffffffL 8212*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_PGFSM_READ_DATA__SHIFT 0x00000000 8213*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE_MASK 0x20000000L 8214*b843c749SSergey Zigachev #define PIPE2_PG_STATUS__PIPE2_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8215*b843c749SSergey Zigachev #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8216*b843c749SSergey Zigachev #define PIPE3_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8217*b843c749SSergey Zigachev #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8218*b843c749SSergey Zigachev #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8219*b843c749SSergey Zigachev #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8220*b843c749SSergey Zigachev #define PIPE3_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8221*b843c749SSergey Zigachev #define PIPE3_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8222*b843c749SSergey Zigachev #define PIPE3_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8223*b843c749SSergey Zigachev #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON_MASK 0x00000001L 8224*b843c749SSergey Zigachev #define PIPE3_PG_CONFIG__PIPE3_POWER_FORCEON__SHIFT 0x00000000 8225*b843c749SSergey Zigachev #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE_MASK 0x00000001L 8226*b843c749SSergey Zigachev #define PIPE3_PG_ENABLE__PIPE3_POWER_GATE__SHIFT 0x00000000 8227*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE_MASK 0x10000000L 8228*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_DESIRED_PWR_STATE__SHIFT 0x0000001c 8229*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS_MASK 0xc0000000L 8230*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8231*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA_MASK 0x00ffffffL 8232*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_PGFSM_READ_DATA__SHIFT 0x00000000 8233*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE_MASK 0x20000000L 8234*b843c749SSergey Zigachev #define PIPE3_PG_STATUS__PIPE3_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8235*b843c749SSergey Zigachev #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8236*b843c749SSergey Zigachev #define PIPE4_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8237*b843c749SSergey Zigachev #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8238*b843c749SSergey Zigachev #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8239*b843c749SSergey Zigachev #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8240*b843c749SSergey Zigachev #define PIPE4_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8241*b843c749SSergey Zigachev #define PIPE4_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8242*b843c749SSergey Zigachev #define PIPE4_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8243*b843c749SSergey Zigachev #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON_MASK 0x00000001L 8244*b843c749SSergey Zigachev #define PIPE4_PG_CONFIG__PIPE4_POWER_FORCEON__SHIFT 0x00000000 8245*b843c749SSergey Zigachev #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE_MASK 0x00000001L 8246*b843c749SSergey Zigachev #define PIPE4_PG_ENABLE__PIPE4_POWER_GATE__SHIFT 0x00000000 8247*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE_MASK 0x10000000L 8248*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_DESIRED_PWR_STATE__SHIFT 0x0000001c 8249*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS_MASK 0xc0000000L 8250*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8251*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA_MASK 0x00ffffffL 8252*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_PGFSM_READ_DATA__SHIFT 0x00000000 8253*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE_MASK 0x20000000L 8254*b843c749SSergey Zigachev #define PIPE4_PG_STATUS__PIPE4_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8255*b843c749SSergey Zigachev #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT_MASK 0x0000ffffL 8256*b843c749SSergey Zigachev #define PIPE5_ARBITRATION_CONTROL3__EFFICIENCY_WEIGHT__SHIFT 0x00000000 8257*b843c749SSergey Zigachev #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED_MASK 0x00000007L 8258*b843c749SSergey Zigachev #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT 0x00000000 8259*b843c749SSergey Zigachev #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK 0x00000010L 8260*b843c749SSergey Zigachev #define PIPE5_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED__SHIFT 0x00000004 8261*b843c749SSergey Zigachev #define PIPE5_MAX_REQUESTS__MAX_REQUESTS_MASK 0x000003ffL 8262*b843c749SSergey Zigachev #define PIPE5_MAX_REQUESTS__MAX_REQUESTS__SHIFT 0x00000000 8263*b843c749SSergey Zigachev #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON_MASK 0x00000001L 8264*b843c749SSergey Zigachev #define PIPE5_PG_CONFIG__PIPE5_POWER_FORCEON__SHIFT 0x00000000 8265*b843c749SSergey Zigachev #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE_MASK 0x00000001L 8266*b843c749SSergey Zigachev #define PIPE5_PG_ENABLE__PIPE5_POWER_GATE__SHIFT 0x00000000 8267*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE_MASK 0x10000000L 8268*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_DESIRED_PWR_STATE__SHIFT 0x0000001c 8269*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L 8270*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS__SHIFT 0x0000001e 8271*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA_MASK 0x00ffffffL 8272*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_PGFSM_READ_DATA__SHIFT 0x00000000 8273*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE_MASK 0x20000000L 8274*b843c749SSergey Zigachev #define PIPE5_PG_STATUS__PIPE5_REQUESTED_PWR_STATE__SHIFT 0x0000001d 8275*b843c749SSergey Zigachev #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0_MASK 0x00000030L 8276*b843c749SSergey Zigachev #define PIXCLK0_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL0__SHIFT 0x00000004 8277*b843c749SSergey Zigachev #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE_MASK 0x00000001L 8278*b843c749SSergey Zigachev #define PIXCLK0_RESYNC_CNTL__PIXCLK0_RESYNC_ENABLE__SHIFT 0x00000000 8279*b843c749SSergey Zigachev #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1_MASK 0x00000030L 8280*b843c749SSergey Zigachev #define PIXCLK1_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL1__SHIFT 0x00000004 8281*b843c749SSergey Zigachev #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE_MASK 0x00000001L 8282*b843c749SSergey Zigachev #define PIXCLK1_RESYNC_CNTL__PIXCLK1_RESYNC_ENABLE__SHIFT 0x00000000 8283*b843c749SSergey Zigachev #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2_MASK 0x00000030L 8284*b843c749SSergey Zigachev #define PIXCLK2_RESYNC_CNTL__DCCG_DEEP_COLOR_CNTL2__SHIFT 0x00000004 8285*b843c749SSergey Zigachev #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE_MASK 0x00000001L 8286*b843c749SSergey Zigachev #define PIXCLK2_RESYNC_CNTL__PIXCLK2_RESYNC_ENABLE__SHIFT 0x00000000 8287*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_CAL_MODE_MASK 0x0000001fL 8288*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_CAL_MODE__SHIFT 0x00000000 8289*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_CP_MASK 0x00000f00L 8290*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_CP__SHIFT 0x00000008 8291*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_IBIAS_MASK 0xff000000L 8292*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_IBIAS__SHIFT 0x00000018 8293*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_LF_MODE_MASK 0x001ff000L 8294*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_LF_MODE__SHIFT 0x0000000c 8295*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_PFD_PULSE_SEL_MASK 0x00000060L 8296*b843c749SSergey Zigachev #define PLL_ANALOG__PLL_PFD_PULSE_SEL__SHIFT 0x00000005 8297*b843c749SSergey Zigachev #define PLL_CNTL__PLL_ANTIGLITCH_RESETB_MASK 0x00000080L 8298*b843c749SSergey Zigachev #define PLL_CNTL__PLL_ANTIGLITCH_RESETB__SHIFT 0x00000007 8299*b843c749SSergey Zigachev #define PLL_CNTL__PLL_ANTI_GLITCH_RESET_MASK 0x00002000L 8300*b843c749SSergey Zigachev #define PLL_CNTL__PLL_ANTI_GLITCH_RESET__SHIFT 0x0000000d 8301*b843c749SSergey Zigachev #define PLL_CNTL__PLL_BYPASS_CAL_MASK 0x00000004L 8302*b843c749SSergey Zigachev #define PLL_CNTL__PLL_BYPASS_CAL__SHIFT 0x00000002 8303*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV_MASK 0x00000400L 8304*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CAL_BYPASS_REFDIV__SHIFT 0x0000000a 8305*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CALIB_DONE_MASK 0x00100000L 8306*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CALIB_DONE__SHIFT 0x00000014 8307*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CALREF_MASK 0x00000300L 8308*b843c749SSergey Zigachev #define PLL_CNTL__PLL_CALREF__SHIFT 0x00000008 8309*b843c749SSergey Zigachev #define PLL_CNTL__PLL_DIG_SPARE_MASK 0xfc000000L 8310*b843c749SSergey Zigachev #define PLL_CNTL__PLL_DIG_SPARE__SHIFT 0x0000001a 8311*b843c749SSergey Zigachev #define PLL_CNTL__PLL_LOCKED_MASK 0x00200000L 8312*b843c749SSergey Zigachev #define PLL_CNTL__PLL_LOCKED__SHIFT 0x00000015 8313*b843c749SSergey Zigachev #define PLL_CNTL__PLL_LOCK_FREQ_SEL_MASK 0x00080000L 8314*b843c749SSergey Zigachev #define PLL_CNTL__PLL_LOCK_FREQ_SEL__SHIFT 0x00000013 8315*b843c749SSergey Zigachev #define PLL_CNTL__PLL_PCIE_REFCLK_SEL_MASK 0x00000040L 8316*b843c749SSergey Zigachev #define PLL_CNTL__PLL_PCIE_REFCLK_SEL__SHIFT 0x00000006 8317*b843c749SSergey Zigachev #define PLL_CNTL__PLL_POST_DIV_SRC_MASK 0x00000008L 8318*b843c749SSergey Zigachev #define PLL_CNTL__PLL_POST_DIV_SRC__SHIFT 0x00000003 8319*b843c749SSergey Zigachev #define PLL_CNTL__PLL_POWER_DOWN_MASK 0x00000002L 8320*b843c749SSergey Zigachev #define PLL_CNTL__PLL_POWER_DOWN__SHIFT 0x00000001 8321*b843c749SSergey Zigachev #define PLL_CNTL__PLL_REFCLK_SEL_MASK 0x00001800L 8322*b843c749SSergey Zigachev #define PLL_CNTL__PLL_REFCLK_SEL__SHIFT 0x0000000b 8323*b843c749SSergey Zigachev #define PLL_CNTL__PLL_REF_DIV_SRC_MASK 0x00070000L 8324*b843c749SSergey Zigachev #define PLL_CNTL__PLL_REF_DIV_SRC__SHIFT 0x00000010 8325*b843c749SSergey Zigachev #define PLL_CNTL__PLL_RESET_MASK 0x00000001L 8326*b843c749SSergey Zigachev #define PLL_CNTL__PLL_RESET__SHIFT 0x00000000 8327*b843c749SSergey Zigachev #define PLL_CNTL__PLL_TIMING_MODE_STATUS_MASK 0x03000000L 8328*b843c749SSergey Zigachev #define PLL_CNTL__PLL_TIMING_MODE_STATUS__SHIFT 0x00000018 8329*b843c749SSergey Zigachev #define PLL_CNTL__PLL_VCOREF_MASK 0x00000030L 8330*b843c749SSergey Zigachev #define PLL_CNTL__PLL_VCOREF__SHIFT 0x00000004 8331*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL_MASK 0x00000f00L 8332*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_CLK_SEL__SHIFT 0x00000008 8333*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL_MASK 0x000000f0L 8334*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_MUXOUT_SEL__SHIFT 0x00000004 8335*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE_MASK 0x00000001L 8336*b843c749SSergey Zigachev #define PLL_DEBUG_CNTL__PLL_DEBUG_SIGNALS_ENABLE__SHIFT 0x00000000 8337*b843c749SSergey Zigachev #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE_MASK 0x000001ffL 8338*b843c749SSergey Zigachev #define PLL_DISPCLK_CURRENT_DTO_PHASE__PLL_DISPCLK_CURRENT_DTO_PHASE__SHIFT 0x00000000 8339*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY_MASK 0xff000000L 8340*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_COMPL_DELAY__SHIFT 0x00000018 8341*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS_MASK 0x00010000L 8342*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_DIS__SHIFT 0x00000010 8343*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE_MASK 0x000001ffL 8344*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_PHASE__SHIFT 0x00000000 8345*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK_MASK 0x00400000L 8346*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_ACK__SHIFT 0x00000016 8347*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE_MASK 0x00060000L 8348*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_MODE__SHIFT 0x00000011 8349*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING_MASK 0x00100000L 8350*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_PENDING__SHIFT 0x00000014 8351*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ_MASK 0x00200000L 8352*b843c749SSergey Zigachev #define PLL_DISPCLK_DTO_CNTL__PLL_DISPCLK_DTO_UPDATE_REQ__SHIFT 0x00000015 8353*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_FRAC_MASK 0x0000ffffL 8354*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_FRAC__SHIFT 0x00000000 8355*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_MODE_MASK 0x00040000L 8356*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_MODE__SHIFT 0x00000012 8357*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_ORDER_MASK 0x00030000L 8358*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_ORDER__SHIFT 0x00000010 8359*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_PRBS_EN_MASK 0x00080000L 8360*b843c749SSergey Zigachev #define PLL_DS_CNTL__PLL_DS_PRBS_EN__SHIFT 0x00000013 8361*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 8362*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 8363*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV_FRACTION_MASK 0x0000000fL 8364*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV_FRACTION__SHIFT 0x00000000 8365*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV_MASK 0x0fff0000L 8366*b843c749SSergey Zigachev #define PLL_FB_DIV__PLL_FB_DIV__SHIFT 0x00000010 8367*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_MASK 0x000f0000L 8368*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET_MASK 0x00000100L 8369*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_RESET__SHIFT 0x00000008 8370*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT_MASK 0x00001000L 8371*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV_SELECT__SHIFT 0x0000000c 8372*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_DIFF_POST_DIV__SHIFT 0x00000010 8373*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN_MASK 0x00000002L 8374*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_DIFF_EN__SHIFT 0x00000001 8375*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN_MASK 0x00000001L 8376*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_LTDP_IDCLK_EN__SHIFT 0x00000000 8377*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN_MASK 0x00000008L 8378*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_DIFF_EN__SHIFT 0x00000003 8379*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN_MASK 0x00000004L 8380*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_TMDP_IDCLK_EN__SHIFT 0x00000002 8381*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN_MASK 0x00000010L 8382*b843c749SSergey Zigachev #define PLL_IDCLK_CNTL__PLL_UNIPHY_IDCLK_DIFF_EN__SHIFT 0x00000004 8383*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK_MASK 0x00000080L 8384*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV1P5_DISPCLK__SHIFT 0x00000007 8385*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK_MASK 0x00008000L 8386*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV1P5_DPREFCLK__SHIFT 0x0000000f 8387*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK_MASK 0x00007f00L 8388*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_DVOCLK__SHIFT 0x00000008 8389*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_IDCLK_MASK 0x007f0000L 8390*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_IDCLK__SHIFT 0x00000010 8391*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK_MASK 0x0000007fL 8392*b843c749SSergey Zigachev #define PLL_POST_DIV__PLL_POST_DIV_PIXCLK__SHIFT 0x00000000 8393*b843c749SSergey Zigachev #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV_MASK 0x0000f000L 8394*b843c749SSergey Zigachev #define PLL_REF_DIV__PLL_CALIBRATION_REF_DIV__SHIFT 0x0000000c 8395*b843c749SSergey Zigachev #define PLL_REF_DIV__PLL_REF_DIV_MASK 0x000003ffL 8396*b843c749SSergey Zigachev #define PLL_REF_DIV__PLL_REF_DIV__SHIFT 0x00000000 8397*b843c749SSergey Zigachev #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC_MASK 0x0000ffffL 8398*b843c749SSergey Zigachev #define PLL_SS_AMOUNT_DSFRAC__PLL_SS_AMOUNT_DSFRAC__SHIFT 0x00000000 8399*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV_MASK 0x000000ffL 8400*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_AMOUNT_FBDIV__SHIFT 0x00000000 8401*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP_MASK 0x00000f00L 8402*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_AMOUNT_NFRAC_SLIP__SHIFT 0x00000008 8403*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_EN_MASK 0x00001000L 8404*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_EN__SHIFT 0x0000000c 8405*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_MODE_MASK 0x00002000L 8406*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_MODE__SHIFT 0x0000000d 8407*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC_MASK 0xffff0000L 8408*b843c749SSergey Zigachev #define PLL_SS_CNTL__PLL_SS_STEP_SIZE_DSFRAC__SHIFT 0x00000010 8409*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT_MASK 0x00000070L 8410*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_COUNT__SHIFT 0x00000004 8411*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE_MASK 0x00000001L 8412*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DETECT_ENABLE__SHIFT 0x00000000 8413*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT_MASK 0x00000002L 8414*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_DET_RES100_SELECT__SHIFT 0x00000001 8415*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR_MASK 0x00000008L 8416*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_CLEAR__SHIFT 0x00000003 8417*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS_MASK 0x00000004L 8418*b843c749SSergey Zigachev #define PLL_UNLOCK_DETECT_CNTL__PLL_UNLOCK_STICKY_STATUS__SHIFT 0x00000002 8419*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE_MASK 0x00010000L 8420*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_AUTO_RESET_DISABLE__SHIFT 0x00000010 8421*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING_MASK 0x00000001L 8422*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_UPDATE_PENDING__SHIFT 0x00000000 8423*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT_MASK 0x00000100L 8424*b843c749SSergey Zigachev #define PLL_UPDATE_CNTL__PLL_UPDATE_POINT__SHIFT 0x00000008 8425*b843c749SSergey Zigachev #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK_MASK 0x00000001L 8426*b843c749SSergey Zigachev #define PLL_UPDATE_LOCK__PLL_UPDATE_LOCK__SHIFT 0x00000000 8427*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREF_SEL_MASK 0x04000000L 8428*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREF_SEL__SHIFT 0x0000001a 8429*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREG_BIAS_MASK 0xf0000000L 8430*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREG_BIAS__SHIFT 0x0000001c 8431*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREG_CNTL_MASK 0x000fffffL 8432*b843c749SSergey Zigachev #define PLL_VREG_CNTL__PLL_VREG_CNTL__SHIFT 0x00000000 8433*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN_MASK 0x00000008L 8434*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_B_SIGN__SHIFT 0x00000003 8435*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK 0x00000010L 8436*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS__SHIFT 0x00000004 8437*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN_MASK 0x00000004L 8438*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_G_SIGN__SHIFT 0x00000002 8439*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN_MASK 0x00000002L 8440*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_R_SIGN__SHIFT 0x00000001 8441*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT_MASK 0x00000001L 8442*b843c749SSergey Zigachev #define PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_SELECT__SHIFT 0x00000000 8443*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK 0x00000010L 8444*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS__SHIFT 0x00000004 8445*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN_MASK 0x00000002L 8446*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CB_SIGN__SHIFT 0x00000001 8447*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN_MASK 0x00000008L 8448*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_CR_SIGN__SHIFT 0x00000003 8449*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT_MASK 0x00000001L 8450*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_SELECT__SHIFT 0x00000000 8451*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN_MASK 0x00000004L 8452*b843c749SSergey Zigachev #define PRESCALE_OVL_CONTROL__OVL_PRESCALE_Y_SIGN__SHIFT 0x00000002 8453*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B_MASK 0x0000ffffL 8454*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_BIAS_B__SHIFT 0x00000000 8455*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B_MASK 0xffff0000L 8456*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_B__GRPH_PRESCALE_SCALE_B__SHIFT 0x00000010 8457*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G_MASK 0x0000ffffL 8458*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_BIAS_G__SHIFT 0x00000000 8459*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G_MASK 0xffff0000L 8460*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_G__GRPH_PRESCALE_SCALE_G__SHIFT 0x00000010 8461*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R_MASK 0x0000ffffL 8462*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_BIAS_R__SHIFT 0x00000000 8463*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R_MASK 0xffff0000L 8464*b843c749SSergey Zigachev #define PRESCALE_VALUES_GRPH_R__GRPH_PRESCALE_SCALE_R__SHIFT 0x00000010 8465*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB_MASK 0x0000ffffL 8466*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_BIAS_CB__SHIFT 0x00000000 8467*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB_MASK 0xffff0000L 8468*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CB__OVL_PRESCALE_SCALE_CB__SHIFT 0x00000010 8469*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR_MASK 0x0000ffffL 8470*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_BIAS_CR__SHIFT 0x00000000 8471*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR_MASK 0xffff0000L 8472*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_CR__OVL_PRESCALE_SCALE_CR__SHIFT 0x00000010 8473*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y_MASK 0x0000ffffL 8474*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_BIAS_Y__SHIFT 0x00000000 8475*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y_MASK 0xffff0000L 8476*b843c749SSergey Zigachev #define PRESCALE_VALUES_OVL_Y__OVL_PRESCALE_SCALE_Y__SHIFT 0x00000010 8477*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END_MASK 0x0000ffffL 8478*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL1__REGAMMA_CNTLA_EXP_REGION_END__SHIFT 0x00000000 8479*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE_MASK 0xffff0000L 8480*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_BASE__SHIFT 0x00000010 8481*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8482*b843c749SSergey Zigachev #define REGAMMA_CNTLA_END_CNTL2__REGAMMA_CNTLA_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8483*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8484*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8485*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8486*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8487*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8488*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8489*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8490*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_0_1__REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8491*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8492*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8493*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8494*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8495*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8496*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8497*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8498*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_10_11__REGAMMA_CNTLA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8499*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8500*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8501*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8502*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8503*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8504*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8505*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8506*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_12_13__REGAMMA_CNTLA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8507*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8508*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8509*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8510*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8511*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8512*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8513*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8514*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_14_15__REGAMMA_CNTLA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8515*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8516*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8517*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8518*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8519*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8520*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8521*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8522*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_2_3__REGAMMA_CNTLA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8523*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8524*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8525*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8526*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8527*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8528*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8529*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8530*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_4_5__REGAMMA_CNTLA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8531*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8532*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8533*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8534*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8535*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8536*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8537*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8538*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_6_7__REGAMMA_CNTLA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8539*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8540*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8541*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8542*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8543*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8544*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8545*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8546*b843c749SSergey Zigachev #define REGAMMA_CNTLA_REGION_8_9__REGAMMA_CNTLA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8547*b843c749SSergey Zigachev #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8548*b843c749SSergey Zigachev #define REGAMMA_CNTLA_SLOPE_CNTL__REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8549*b843c749SSergey Zigachev #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_MASK 0x0003ffffL 8550*b843c749SSergey Zigachev #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8551*b843c749SSergey Zigachev #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8552*b843c749SSergey Zigachev #define REGAMMA_CNTLA_START_CNTL__REGAMMA_CNTLA_EXP_REGION_START__SHIFT 0x00000000 8553*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END_MASK 0x0000ffffL 8554*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL1__REGAMMA_CNTLB_EXP_REGION_END__SHIFT 0x00000000 8555*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE_MASK 0xffff0000L 8556*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_BASE__SHIFT 0x00000010 8557*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE_MASK 0x0000ffffL 8558*b843c749SSergey Zigachev #define REGAMMA_CNTLB_END_CNTL2__REGAMMA_CNTLB_EXP_REGION_END_SLOPE__SHIFT 0x00000000 8559*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffL 8560*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 8561*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000L 8562*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c 8563*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000L 8564*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 8565*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000L 8566*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_0_1__REGAMMA_CNTLB_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c 8567*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffL 8568*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 8569*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000L 8570*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c 8571*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000L 8572*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 8573*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000L 8574*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_10_11__REGAMMA_CNTLB_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c 8575*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffL 8576*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 8577*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000L 8578*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c 8579*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000L 8580*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 8581*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000L 8582*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_12_13__REGAMMA_CNTLB_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c 8583*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffL 8584*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 8585*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000L 8586*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c 8587*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000L 8588*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 8589*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000L 8590*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_14_15__REGAMMA_CNTLB_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c 8591*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffL 8592*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 8593*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000L 8594*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c 8595*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000L 8596*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 8597*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000L 8598*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_2_3__REGAMMA_CNTLB_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c 8599*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffL 8600*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 8601*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000L 8602*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c 8603*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000L 8604*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 8605*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000L 8606*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_4_5__REGAMMA_CNTLB_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c 8607*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffL 8608*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 8609*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000L 8610*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c 8611*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000L 8612*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 8613*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000L 8614*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_6_7__REGAMMA_CNTLB_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c 8615*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffL 8616*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 8617*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000L 8618*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c 8619*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000L 8620*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 8621*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000L 8622*b843c749SSergey Zigachev #define REGAMMA_CNTLB_REGION_8_9__REGAMMA_CNTLB_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c 8623*b843c749SSergey Zigachev #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE_MASK 0x0003ffffL 8624*b843c749SSergey Zigachev #define REGAMMA_CNTLB_SLOPE_CNTL__REGAMMA_CNTLB_EXP_REGION_LINEAR_SLOPE__SHIFT 0x00000000 8625*b843c749SSergey Zigachev #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_MASK 0x0003ffffL 8626*b843c749SSergey Zigachev #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT_MASK 0x07f00000L 8627*b843c749SSergey Zigachev #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START_SEGMENT__SHIFT 0x00000014 8628*b843c749SSergey Zigachev #define REGAMMA_CNTLB_START_CNTL__REGAMMA_CNTLB_EXP_REGION_START__SHIFT 0x00000000 8629*b843c749SSergey Zigachev #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE_MASK 0x00000007L 8630*b843c749SSergey Zigachev #define REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT 0x00000000 8631*b843c749SSergey Zigachev #define REGAMMA_CONTROL__OVL_REGAMMA_MODE_MASK 0x00000070L 8632*b843c749SSergey Zigachev #define REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT 0x00000004 8633*b843c749SSergey Zigachev #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA_MASK 0x0007ffffL 8634*b843c749SSergey Zigachev #define REGAMMA_LUT_DATA__REGAMMA_LUT_DATA__SHIFT 0x00000000 8635*b843c749SSergey Zigachev #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX_MASK 0x000001ffL 8636*b843c749SSergey Zigachev #define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000 8637*b843c749SSergey Zigachev #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L 8638*b843c749SSergey Zigachev #define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000 8639*b843c749SSergey Zigachev #define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L 8640*b843c749SSergey Zigachev #define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000 8641*b843c749SSergey Zigachev #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L 8642*b843c749SSergey Zigachev #define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE__SHIFT 0x00000000 8643*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK_MASK 0x00000100L 8644*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_ACK__SHIFT 0x00000008 8645*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG_MASK 0x00000001L 8646*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_FLAG__SHIFT 0x00000000 8647*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS_MASK 0x00010000L 8648*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_INT_STATUS__SHIFT 0x00000010 8649*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK_MASK 0x00001000L 8650*b843c749SSergey Zigachev #define SCL_COEF_RAM_CONFLICT_STATUS__SCL_HOST_CONFLICT_MASK__SHIFT 0x0000000c 8651*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE_MASK 0x00030000L 8652*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_FILTER_TYPE__SHIFT 0x00000010 8653*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE_MASK 0x00000f00L 8654*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_PHASE__SHIFT 0x00000008 8655*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX_MASK 0x0000000fL 8656*b843c749SSergey Zigachev #define SCL_COEF_RAM_SELECT__SCL_C_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 8657*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000L 8658*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f 8659*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF_MASK 0x00003fffL 8660*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 8661*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN_MASK 0x80000000L 8662*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f 8663*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF_MASK 0x3fff0000L 8664*b843c749SSergey Zigachev #define SCL_COEF_RAM_TAP_DATA__SCL_C_RAM_ODD_TAP_COEF__SHIFT 0x00000010 8665*b843c749SSergey Zigachev #define SCL_DEBUG2__SCL_DEBUG2_MASK 0xffffffffL 8666*b843c749SSergey Zigachev #define SCL_DEBUG2__SCL_DEBUG2__SHIFT 0x00000000 8667*b843c749SSergey Zigachev #define SCL_DEBUG__SCL_DEBUG_MASK 0xffffffffL 8668*b843c749SSergey Zigachev #define SCL_DEBUG__SCL_DEBUG__SHIFT 0x00000000 8669*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN_MASK 0x00000010L 8670*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_EN__SHIFT 0x00000004 8671*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR_MASK 0x00000007L 8672*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_HF_SHARP_SCALE_FACTOR__SHIFT 0x00000000 8673*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN_MASK 0x00001000L 8674*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_EN__SHIFT 0x0000000c 8675*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR_MASK 0x00000700L 8676*b843c749SSergey Zigachev #define SCL_F_SHARP_CONTROL__SCL_VF_SHARP_SCALE_FACTOR__SHIFT 0x00000008 8677*b843c749SSergey Zigachev #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST_MASK 0x00000001L 8678*b843c749SSergey Zigachev #define SCL_HORZ_FILTER_CONTROL__SCL_H_FILTER_PICK_NEAREST__SHIFT 0x00000000 8679*b843c749SSergey Zigachev #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x03ffffffL 8680*b843c749SSergey Zigachev #define SCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 8681*b843c749SSergey Zigachev #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 8682*b843c749SSergey Zigachev #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 8683*b843c749SSergey Zigachev #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY_MASK 0x0000000fL 8684*b843c749SSergey Zigachev #define SCLK_CGTT_BLK_CTRL_REG__SCLK_TURN_ON_DELAY__SHIFT 0x00000000 8685*b843c749SSergey Zigachev #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00L 8686*b843c749SSergey Zigachev #define SCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 8687*b843c749SSergey Zigachev #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fL 8688*b843c749SSergey Zigachev #define SCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 8689*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO_MASK 0x0fffff80L 8690*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_ALU_H_SCALE_RATIO__SHIFT 0x00000007 8691*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK_MASK 0x00000010L 8692*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_ACK__SHIFT 0x00000004 8693*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE_MASK 0x00000001L 8694*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET1__SCL_MODE_CHANGE__SHIFT 0x00000000 8695*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO_MASK 0x001fffffL 8696*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET2__SCL_ALU_V_SCALE_RATIO__SHIFT 0x00000000 8697*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT_MASK 0x00003fffL 8698*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_HEIGHT__SHIFT 0x00000000 8699*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH_MASK 0x3fff0000L 8700*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_DET3__SCL_ALU_SOURCE_WIDTH__SHIFT 0x00000010 8701*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK_MASK 0x00000001L 8702*b843c749SSergey Zigachev #define SCL_MODE_CHANGE_MASK__SCL_MODE_CHANGE_MASK__SHIFT 0x00000000 8703*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA_MASK 0xffffffffL 8704*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_DATA__SCL_TEST_DEBUG_DATA__SHIFT 0x00000000 8705*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX_MASK 0x000000ffL 8706*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_INDEX__SHIFT 0x00000000 8707*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 8708*b843c749SSergey Zigachev #define SCL_TEST_DEBUG_INDEX__SCL_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 8709*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_LOCK_MASK 0x00010000L 8710*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_LOCK__SHIFT 0x00000010 8711*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001L 8712*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 8713*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_TAKEN_MASK 0x00000100L 8714*b843c749SSergey Zigachev #define SCL_UPDATE__SCL_UPDATE_TAKEN__SHIFT 0x00000008 8715*b843c749SSergey Zigachev #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST_MASK 0x00000001L 8716*b843c749SSergey Zigachev #define SCL_VERT_FILTER_CONTROL__SCL_V_FILTER_PICK_NEAREST__SHIFT 0x00000000 8717*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x0000ffffL 8718*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 8719*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x00070000L 8720*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000010 8721*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x0000ffffL 8722*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 8723*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x00070000L 8724*b843c749SSergey Zigachev #define SCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000010 8725*b843c749SSergey Zigachev #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x03ffffffL 8726*b843c749SSergey Zigachev #define SCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 8727*b843c749SSergey Zigachev #define SEQ00__SEQ_RST0B_MASK 0x00000001L 8728*b843c749SSergey Zigachev #define SEQ00__SEQ_RST0B__SHIFT 0x00000000 8729*b843c749SSergey Zigachev #define SEQ00__SEQ_RST1B_MASK 0x00000002L 8730*b843c749SSergey Zigachev #define SEQ00__SEQ_RST1B__SHIFT 0x00000001 8731*b843c749SSergey Zigachev #define SEQ01__SEQ_DOT8_MASK 0x00000001L 8732*b843c749SSergey Zigachev #define SEQ01__SEQ_DOT8__SHIFT 0x00000000 8733*b843c749SSergey Zigachev #define SEQ01__SEQ_MAXBW_MASK 0x00000020L 8734*b843c749SSergey Zigachev #define SEQ01__SEQ_MAXBW__SHIFT 0x00000005 8735*b843c749SSergey Zigachev #define SEQ01__SEQ_PCLKBY2_MASK 0x00000008L 8736*b843c749SSergey Zigachev #define SEQ01__SEQ_PCLKBY2__SHIFT 0x00000003 8737*b843c749SSergey Zigachev #define SEQ01__SEQ_SHIFT2_MASK 0x00000004L 8738*b843c749SSergey Zigachev #define SEQ01__SEQ_SHIFT2__SHIFT 0x00000002 8739*b843c749SSergey Zigachev #define SEQ01__SEQ_SHIFT4_MASK 0x00000010L 8740*b843c749SSergey Zigachev #define SEQ01__SEQ_SHIFT4__SHIFT 0x00000004 8741*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP0_EN_MASK 0x00000001L 8742*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP0_EN__SHIFT 0x00000000 8743*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP1_EN_MASK 0x00000002L 8744*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP1_EN__SHIFT 0x00000001 8745*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP2_EN_MASK 0x00000004L 8746*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP2_EN__SHIFT 0x00000002 8747*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP3_EN_MASK 0x00000008L 8748*b843c749SSergey Zigachev #define SEQ02__SEQ_MAP3_EN__SHIFT 0x00000003 8749*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A0_MASK 0x00000020L 8750*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A0__SHIFT 0x00000005 8751*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A1_MASK 0x00000004L 8752*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A1__SHIFT 0x00000002 8753*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A2_MASK 0x00000008L 8754*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_A2__SHIFT 0x00000003 8755*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B0_MASK 0x00000010L 8756*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B0__SHIFT 0x00000004 8757*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B1_MASK 0x00000001L 8758*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B1__SHIFT 0x00000000 8759*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B2_MASK 0x00000002L 8760*b843c749SSergey Zigachev #define SEQ03__SEQ_FONT_B2__SHIFT 0x00000001 8761*b843c749SSergey Zigachev #define SEQ04__SEQ_256K_MASK 0x00000002L 8762*b843c749SSergey Zigachev #define SEQ04__SEQ_256K__SHIFT 0x00000001 8763*b843c749SSergey Zigachev #define SEQ04__SEQ_CHAIN_MASK 0x00000008L 8764*b843c749SSergey Zigachev #define SEQ04__SEQ_CHAIN__SHIFT 0x00000003 8765*b843c749SSergey Zigachev #define SEQ04__SEQ_ODDEVEN_MASK 0x00000004L 8766*b843c749SSergey Zigachev #define SEQ04__SEQ_ODDEVEN__SHIFT 0x00000002 8767*b843c749SSergey Zigachev #define SEQ8_DATA__SEQ_DATA_MASK 0x000000ffL 8768*b843c749SSergey Zigachev #define SEQ8_DATA__SEQ_DATA__SHIFT 0x00000000 8769*b843c749SSergey Zigachev #define SEQ8_IDX__SEQ_IDX_MASK 0x00000007L 8770*b843c749SSergey Zigachev #define SEQ8_IDX__SEQ_IDX__SHIFT 0x00000000 8771*b843c749SSergey Zigachev #define SINK_DESCRIPTION0__DESCRIPTION_MASK 0x000000ffL 8772*b843c749SSergey Zigachev #define SINK_DESCRIPTION0__DESCRIPTION__SHIFT 0x00000000 8773*b843c749SSergey Zigachev #define SINK_DESCRIPTION10__DESCRIPTION_MASK 0x000000ffL 8774*b843c749SSergey Zigachev #define SINK_DESCRIPTION10__DESCRIPTION__SHIFT 0x00000000 8775*b843c749SSergey Zigachev #define SINK_DESCRIPTION11__DESCRIPTION_MASK 0x000000ffL 8776*b843c749SSergey Zigachev #define SINK_DESCRIPTION11__DESCRIPTION__SHIFT 0x00000000 8777*b843c749SSergey Zigachev #define SINK_DESCRIPTION12__DESCRIPTION_MASK 0x000000ffL 8778*b843c749SSergey Zigachev #define SINK_DESCRIPTION12__DESCRIPTION__SHIFT 0x00000000 8779*b843c749SSergey Zigachev #define SINK_DESCRIPTION13__DESCRIPTION_MASK 0x000000ffL 8780*b843c749SSergey Zigachev #define SINK_DESCRIPTION13__DESCRIPTION__SHIFT 0x00000000 8781*b843c749SSergey Zigachev #define SINK_DESCRIPTION14__DESCRIPTION_MASK 0x000000ffL 8782*b843c749SSergey Zigachev #define SINK_DESCRIPTION14__DESCRIPTION__SHIFT 0x00000000 8783*b843c749SSergey Zigachev #define SINK_DESCRIPTION15__DESCRIPTION_MASK 0x000000ffL 8784*b843c749SSergey Zigachev #define SINK_DESCRIPTION15__DESCRIPTION__SHIFT 0x00000000 8785*b843c749SSergey Zigachev #define SINK_DESCRIPTION16__DESCRIPTION_MASK 0x000000ffL 8786*b843c749SSergey Zigachev #define SINK_DESCRIPTION16__DESCRIPTION__SHIFT 0x00000000 8787*b843c749SSergey Zigachev #define SINK_DESCRIPTION17__DESCRIPTION_MASK 0x000000ffL 8788*b843c749SSergey Zigachev #define SINK_DESCRIPTION17__DESCRIPTION__SHIFT 0x00000000 8789*b843c749SSergey Zigachev #define SINK_DESCRIPTION1__DESCRIPTION_MASK 0x000000ffL 8790*b843c749SSergey Zigachev #define SINK_DESCRIPTION1__DESCRIPTION__SHIFT 0x00000000 8791*b843c749SSergey Zigachev #define SINK_DESCRIPTION2__DESCRIPTION_MASK 0x000000ffL 8792*b843c749SSergey Zigachev #define SINK_DESCRIPTION2__DESCRIPTION__SHIFT 0x00000000 8793*b843c749SSergey Zigachev #define SINK_DESCRIPTION3__DESCRIPTION_MASK 0x000000ffL 8794*b843c749SSergey Zigachev #define SINK_DESCRIPTION3__DESCRIPTION__SHIFT 0x00000000 8795*b843c749SSergey Zigachev #define SINK_DESCRIPTION4__DESCRIPTION_MASK 0x000000ffL 8796*b843c749SSergey Zigachev #define SINK_DESCRIPTION4__DESCRIPTION__SHIFT 0x00000000 8797*b843c749SSergey Zigachev #define SINK_DESCRIPTION5__DESCRIPTION_MASK 0x000000ffL 8798*b843c749SSergey Zigachev #define SINK_DESCRIPTION5__DESCRIPTION__SHIFT 0x00000000 8799*b843c749SSergey Zigachev #define SINK_DESCRIPTION6__DESCRIPTION_MASK 0x000000ffL 8800*b843c749SSergey Zigachev #define SINK_DESCRIPTION6__DESCRIPTION__SHIFT 0x00000000 8801*b843c749SSergey Zigachev #define SINK_DESCRIPTION7__DESCRIPTION_MASK 0x000000ffL 8802*b843c749SSergey Zigachev #define SINK_DESCRIPTION7__DESCRIPTION__SHIFT 0x00000000 8803*b843c749SSergey Zigachev #define SINK_DESCRIPTION8__DESCRIPTION_MASK 0x000000ffL 8804*b843c749SSergey Zigachev #define SINK_DESCRIPTION8__DESCRIPTION__SHIFT 0x00000000 8805*b843c749SSergey Zigachev #define SINK_DESCRIPTION9__DESCRIPTION_MASK 0x000000ffL 8806*b843c749SSergey Zigachev #define SINK_DESCRIPTION9__DESCRIPTION__SHIFT 0x00000000 8807*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0_MASK 0x000000ffL 8808*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE0__SHIFT 0x00000000 8809*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1_MASK 0x0000ff00L 8810*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE1__SHIFT 0x00000008 8811*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2_MASK 0x00ff0000L 8812*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 8813*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3_MASK 0xff000000L 8814*b843c749SSergey Zigachev #define SLAVE_COMM_CMD_REG__SLAVE_COMM_CMD_REG_BYTE3__SHIFT 0x00000018 8815*b843c749SSergey Zigachev #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS_MASK 0x00000100L 8816*b843c749SSergey Zigachev #define SLAVE_COMM_CNTL_REG__COMM_PORT_MSG_TO_HOST_IN_PROGRESS__SHIFT 0x00000008 8817*b843c749SSergey Zigachev #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT_MASK 0x00000001L 8818*b843c749SSergey Zigachev #define SLAVE_COMM_CNTL_REG__SLAVE_COMM_INTERRUPT__SHIFT 0x00000000 8819*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0_MASK 0x000000ffL 8820*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE0__SHIFT 0x00000000 8821*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1_MASK 0x0000ff00L 8822*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE1__SHIFT 0x00000008 8823*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2_MASK 0x00ff0000L 8824*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE2__SHIFT 0x00000010 8825*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3_MASK 0xff000000L 8826*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG1__SLAVE_COMM_DATA_REG1_BYTE3__SHIFT 0x00000018 8827*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0_MASK 0x000000ffL 8828*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE0__SHIFT 0x00000000 8829*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1_MASK 0x0000ff00L 8830*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE1__SHIFT 0x00000008 8831*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2_MASK 0x00ff0000L 8832*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE2__SHIFT 0x00000010 8833*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3_MASK 0xff000000L 8834*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG2__SLAVE_COMM_DATA_REG2_BYTE3__SHIFT 0x00000018 8835*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0_MASK 0x000000ffL 8836*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE0__SHIFT 0x00000000 8837*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1_MASK 0x0000ff00L 8838*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE1__SHIFT 0x00000008 8839*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2_MASK 0x00ff0000L 8840*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE2__SHIFT 0x00000010 8841*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3_MASK 0xff000000L 8842*b843c749SSergey Zigachev #define SLAVE_COMM_DATA_REG3__SLAVE_COMM_DATA_REG3_BYTE3__SHIFT 0x00000018 8843*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE_MASK 0x00000001L 8844*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_CLOCK_ENABLE__SHIFT 0x00000000 8845*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN_MASK 0x00000010L 8846*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_EN__SHIFT 0x00000004 8847*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC_MASK 0x00000700L 8848*b843c749SSergey Zigachev #define SYMCLKA_CLOCK_ENABLE__SYMCLKA_FE_FORCE_SRC__SHIFT 0x00000008 8849*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE_MASK 0x00000001L 8850*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_CLOCK_ENABLE__SHIFT 0x00000000 8851*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN_MASK 0x00000010L 8852*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_EN__SHIFT 0x00000004 8853*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC_MASK 0x00000700L 8854*b843c749SSergey Zigachev #define SYMCLKB_CLOCK_ENABLE__SYMCLKB_FE_FORCE_SRC__SHIFT 0x00000008 8855*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE_MASK 0x00000001L 8856*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_CLOCK_ENABLE__SHIFT 0x00000000 8857*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN_MASK 0x00000010L 8858*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_EN__SHIFT 0x00000004 8859*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC_MASK 0x00000700L 8860*b843c749SSergey Zigachev #define SYMCLKC_CLOCK_ENABLE__SYMCLKC_FE_FORCE_SRC__SHIFT 0x00000008 8861*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE_MASK 0x00000001L 8862*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_CLOCK_ENABLE__SHIFT 0x00000000 8863*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN_MASK 0x00000010L 8864*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_EN__SHIFT 0x00000004 8865*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC_MASK 0x00000700L 8866*b843c749SSergey Zigachev #define SYMCLKD_CLOCK_ENABLE__SYMCLKD_FE_FORCE_SRC__SHIFT 0x00000008 8867*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE_MASK 0x00000001L 8868*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_CLOCK_ENABLE__SHIFT 0x00000000 8869*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN_MASK 0x00000010L 8870*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_EN__SHIFT 0x00000004 8871*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC_MASK 0x00000700L 8872*b843c749SSergey Zigachev #define SYMCLKE_CLOCK_ENABLE__SYMCLKE_FE_FORCE_SRC__SHIFT 0x00000008 8873*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE_MASK 0x00000001L 8874*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_CLOCK_ENABLE__SHIFT 0x00000000 8875*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN_MASK 0x00000010L 8876*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_EN__SHIFT 0x00000004 8877*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC_MASK 0x00000700L 8878*b843c749SSergey Zigachev #define SYMCLKF_CLOCK_ENABLE__SYMCLKF_FE_FORCE_SRC__SHIFT 0x00000008 8879*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 8880*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 8881*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 8882*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 8883*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_SYNC_PHASE_MASK 0x00000001L 8884*b843c749SSergey Zigachev #define TMDS_CNTL__TMDS_SYNC_PHASE__SHIFT 0x00000000 8885*b843c749SSergey Zigachev #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY_MASK 0x00000300L 8886*b843c749SSergey Zigachev #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_DELAY__SHIFT 0x00000008 8887*b843c749SSergey Zigachev #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT_MASK 0x00000003L 8888*b843c749SSergey Zigachev #define TMDS_CONTROL0_FEEDBACK__TMDS_CONTROL0_FEEDBACK_SELECT__SHIFT 0x00000000 8889*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN_MASK 0x00000001L 8890*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR0_OUT_EN__SHIFT 0x00000000 8891*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN_MASK 0x00000002L 8892*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR1_OUT_EN__SHIFT 0x00000001 8893*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN_MASK 0x00000004L 8894*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR2_OUT_EN__SHIFT 0x00000002 8895*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN_MASK 0x00000008L 8896*b843c749SSergey Zigachev #define TMDS_CONTROL_CHAR__TMDS_CONTROL_CHAR3_OUT_EN__SHIFT 0x00000003 8897*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN_MASK 0x80000000L 8898*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_2BIT_COUNTER_EN__SHIFT 0x0000001f 8899*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY_MASK 0x00000070L 8900*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_DELAY__SHIFT 0x00000004 8901*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT_MASK 0x00000080L 8902*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_INVERT__SHIFT 0x00000007 8903*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION_MASK 0x00000300L 8904*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_MODULATION__SHIFT 0x00000008 8905*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL_MASK 0x0000000fL 8906*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_DATA_SEL__SHIFT 0x00000000 8907*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT_MASK 0x00000800L 8908*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_FB_SYNC_CONT__SHIFT 0x0000000b 8909*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN_MASK 0x00001000L 8910*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_PATTERN_OUT_EN__SHIFT 0x0000000c 8911*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH_MASK 0x00000400L 8912*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL0_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8913*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY_MASK 0x00700000L 8914*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_DELAY__SHIFT 0x00000014 8915*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT_MASK 0x00800000L 8916*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_INVERT__SHIFT 0x00000017 8917*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION_MASK 0x03000000L 8918*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_MODULATION__SHIFT 0x00000018 8919*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL_MASK 0x000f0000L 8920*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_DATA_SEL__SHIFT 0x00000010 8921*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT_MASK 0x08000000L 8922*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_FB_SYNC_CONT__SHIFT 0x0000001b 8923*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN_MASK 0x10000000L 8924*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_PATTERN_OUT_EN__SHIFT 0x0000001c 8925*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH_MASK 0x04000000L 8926*b843c749SSergey Zigachev #define TMDS_CTL0_1_GEN_CNTL__TMDS_CTL1_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8927*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY_MASK 0x00000070L 8928*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_DELAY__SHIFT 0x00000004 8929*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT_MASK 0x00000080L 8930*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_INVERT__SHIFT 0x00000007 8931*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION_MASK 0x00000300L 8932*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_MODULATION__SHIFT 0x00000008 8933*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL_MASK 0x0000000fL 8934*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_DATA_SEL__SHIFT 0x00000000 8935*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT_MASK 0x00000800L 8936*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_FB_SYNC_CONT__SHIFT 0x0000000b 8937*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN_MASK 0x00001000L 8938*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_PATTERN_OUT_EN__SHIFT 0x0000000c 8939*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH_MASK 0x00000400L 8940*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL2_USE_FEEDBACK_PATH__SHIFT 0x0000000a 8941*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY_MASK 0x00700000L 8942*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_DELAY__SHIFT 0x00000014 8943*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT_MASK 0x00800000L 8944*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_INVERT__SHIFT 0x00000017 8945*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION_MASK 0x03000000L 8946*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_MODULATION__SHIFT 0x00000018 8947*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL_MASK 0x000f0000L 8948*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_DATA_SEL__SHIFT 0x00000010 8949*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT_MASK 0x08000000L 8950*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_FB_SYNC_CONT__SHIFT 0x0000001b 8951*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN_MASK 0x10000000L 8952*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_PATTERN_OUT_EN__SHIFT 0x0000001c 8953*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH_MASK 0x04000000L 8954*b843c749SSergey Zigachev #define TMDS_CTL2_3_GEN_CNTL__TMDS_CTL3_USE_FEEDBACK_PATH__SHIFT 0x0000001a 8955*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL0_MASK 0x00000001L 8956*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL0__SHIFT 0x00000000 8957*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL1_MASK 0x00000100L 8958*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL1__SHIFT 0x00000008 8959*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL2_MASK 0x00010000L 8960*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL2__SHIFT 0x00000010 8961*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL3_MASK 0x01000000L 8962*b843c749SSergey Zigachev #define TMDS_CTL_BITS__TMDS_CTL3__SHIFT 0x00000018 8963*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN_MASK 0x00000001L 8964*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_EN__SHIFT 0x00000000 8965*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE_MASK 0x01000000L 8966*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_FORCE__SHIFT 0x00000018 8967*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN_MASK 0x00000100L 8968*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_EN__SHIFT 0x00000008 8969*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN_MASK 0x000f0000L 8970*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_DCBALANCER_TEST_IN__SHIFT 0x00000010 8971*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN_MASK 0x00000070L 8972*b843c749SSergey Zigachev #define TMDS_DCBALANCER_CONTROL__TMDS_SYNC_DCBAL_EN__SHIFT 0x00000004 8973*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_DE_EN_MASK 0x02000000L 8974*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_DE_EN__SHIFT 0x00000019 8975*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_DE_MASK 0x01000000L 8976*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_DE__SHIFT 0x00000018 8977*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_EN_MASK 0x00000001L 8978*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_EN__SHIFT 0x00000000 8979*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN_MASK 0x00000200L 8980*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_EN__SHIFT 0x00000009 8981*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_HSYNC_MASK 0x00000100L 8982*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_HSYNC__SHIFT 0x00000008 8983*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN_MASK 0x00020000L 8984*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_EN__SHIFT 0x00000011 8985*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_VSYNC_MASK 0x00010000L 8986*b843c749SSergey Zigachev #define TMDS_DEBUG__TMDS_DEBUG_VSYNC__SHIFT 0x00000010 8987*b843c749SSergey Zigachev #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL_MASK 0x00000003L 8988*b843c749SSergey Zigachev #define TMDS_STEREOSYNC_CTL_SEL__TMDS_STEREOSYNC_CTL_SEL__SHIFT 0x00000000 8989*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0_MASK 0x000003ffL 8990*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN0__SHIFT 0x00000000 8991*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1_MASK 0x03ff0000L 8992*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_0_1__TMDS_SYNC_CHAR_PATTERN1__SHIFT 0x00000010 8993*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2_MASK 0x000003ffL 8994*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN2__SHIFT 0x00000000 8995*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3_MASK 0x03ff0000L 8996*b843c749SSergey Zigachev #define TMDS_SYNC_CHAR_PATTERN_2_3__TMDS_SYNC_CHAR_PATTERN3__SHIFT 0x00000010 8997*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN_MASK 0x000003ffL 8998*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_STATIC_TEST_PATTERN__SHIFT 0x00000000 8999*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN_MASK 0x00010000L 9000*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_EN__SHIFT 0x00000010 9001*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL_MASK 0x000e0000L 9002*b843c749SSergey Zigachev #define UNIPHYAB_TPG_CONTROL__UNIPHYAB_TPG_SEL__SHIFT 0x00000011 9003*b843c749SSergey Zigachev #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED_MASK 0x007fffffL 9004*b843c749SSergey Zigachev #define UNIPHYAB_TPG_SEED__UNIPHYAB_TPG_SEED__SHIFT 0x00000000 9005*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR_MASK 0x001f0000L 9006*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_ERROR__SHIFT 0x00000010 9007*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET_MASK 0x00000002L 9008*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_ANG_BIST_RESET__SHIFT 0x00000001 9009*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB_MASK 0x01000000L 9010*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_PRESETB__SHIFT 0x00000018 9011*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS_MASK 0x00000f00L 9012*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_RX_BIAS__SHIFT 0x00000008 9013*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN_MASK 0x00000001L 9014*b843c749SSergey Zigachev #define UNIPHY_ANG_BIST_CNTL__UNIPHY_TEST_RX_EN__SHIFT 0x00000000 9015*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN_MASK 0x000003ffL 9016*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_STATIC_TEST_PATTERN__SHIFT 0x00000000 9017*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN_MASK 0x00010000L 9018*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_EN__SHIFT 0x00000010 9019*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL_MASK 0x000e0000L 9020*b843c749SSergey Zigachev #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 9021*b843c749SSergey Zigachev #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED_MASK 0x007fffffL 9022*b843c749SSergey Zigachev #define UNIPHYCD_TPG_SEED__UNIPHYCD_TPG_SEED__SHIFT 0x00000000 9023*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE_MASK 0x00000003L 9024*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL0_XBAR_SOURCE__SHIFT 0x00000000 9025*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE_MASK 0x00000300L 9026*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL1_XBAR_SOURCE__SHIFT 0x00000008 9027*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE_MASK 0x00030000L 9028*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL2_XBAR_SOURCE__SHIFT 0x00000010 9029*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE_MASK 0x03000000L 9030*b843c749SSergey Zigachev #define UNIPHY_CHANNEL_XBAR_CNTL__UNIPHY_CHANNEL3_XBAR_SOURCE__SHIFT 0x00000018 9031*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR_MASK 0x00000040L 9032*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_ERROR__SHIFT 0x00000006 9033*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL_MASK 0x00000030L 9034*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYN_LEVEL__SHIFT 0x00000004 9035*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL_MASK 0x00000001L 9036*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DSYNSEL__SHIFT 0x00000000 9037*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE_MASK 0x00010000L 9038*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_DUAL_LINK_PHASE__SHIFT 0x00000010 9039*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE_MASK 0x00001000L 9040*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_LINK_ENABLE__SHIFT 0x0000000c 9041*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT_MASK 0x00000100L 9042*b843c749SSergey Zigachev #define UNIPHY_DATA_SYNCHRONIZATION__UNIPHY_SOURCE_SELECT__SHIFT 0x00000008 9043*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN_MASK 0x000003ffL 9044*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_STATIC_TEST_PATTERN__SHIFT 0x00000000 9045*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN_MASK 0x00010000L 9046*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_EN__SHIFT 0x00000010 9047*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL_MASK 0x000e0000L 9048*b843c749SSergey Zigachev #define UNIPHYEF_TPG_CONTROL__UNIPHYEF_TPG_SEL__SHIFT 0x00000011 9049*b843c749SSergey Zigachev #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED_MASK 0x007fffffL 9050*b843c749SSergey Zigachev #define UNIPHYEF_TPG_SEED__UNIPHYEF_TPG_SEED__SHIFT 0x00000000 9051*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK_MASK 0x00000400L 9052*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_AK__SHIFT 0x0000000a 9053*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA_MASK 0x00000200L 9054*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_CALOUT_ERROR_LINKA__SHIFT 0x00000009 9055*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA_MASK 0x00000100L 9056*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_CALOUT_LINKA__SHIFT 0x00000008 9057*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA_MASK 0x00000001L 9058*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_ENABLE_LINKA__SHIFT 0x00000000 9059*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA_MASK 0x10000000L 9060*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKA__SHIFT 0x0000001c 9061*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA_MASK 0x0f000000L 9062*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_OVERRIDE_LINKA__SHIFT 0x00000018 9063*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA_MASK 0x40000000L 9064*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_SEL_LINKA__SHIFT 0x0000001e 9065*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA_MASK 0x00f00000L 9066*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_STEP_DELAY_LINKA__SHIFT 0x00000014 9067*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA_MASK 0x000f0000L 9068*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKA__UNIPHY_IMPCAL_VALUE_LINKA__SHIFT 0x00000010 9069*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK_MASK 0x00000400L 9070*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_AK__SHIFT 0x0000000a 9071*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB_MASK 0x00000200L 9072*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_CALOUT_ERROR_LINKB__SHIFT 0x00000009 9073*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB_MASK 0x00000100L 9074*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_CALOUT_LINKB__SHIFT 0x00000008 9075*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB_MASK 0x00000001L 9076*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_ENABLE_LINKB__SHIFT 0x00000000 9077*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB_MASK 0x10000000L 9078*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKB__SHIFT 0x0000001c 9079*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB_MASK 0x0f000000L 9080*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_OVERRIDE_LINKB__SHIFT 0x00000018 9081*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB_MASK 0x40000000L 9082*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_SEL_LINKB__SHIFT 0x0000001e 9083*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB_MASK 0x00f00000L 9084*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_STEP_DELAY_LINKB__SHIFT 0x00000014 9085*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB_MASK 0x000f0000L 9086*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKB__UNIPHY_IMPCAL_VALUE_LINKB__SHIFT 0x00000010 9087*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK_MASK 0x00000400L 9088*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_AK__SHIFT 0x0000000a 9089*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC_MASK 0x00000200L 9090*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_CALOUT_ERROR_LINKC__SHIFT 0x00000009 9091*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC_MASK 0x00000100L 9092*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_CALOUT_LINKC__SHIFT 0x00000008 9093*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC_MASK 0x00000001L 9094*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_ENABLE_LINKC__SHIFT 0x00000000 9095*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC_MASK 0x10000000L 9096*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKC__SHIFT 0x0000001c 9097*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC_MASK 0x0f000000L 9098*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_OVERRIDE_LINKC__SHIFT 0x00000018 9099*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC_MASK 0x40000000L 9100*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_SEL_LINKC__SHIFT 0x0000001e 9101*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC_MASK 0x00f00000L 9102*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_STEP_DELAY_LINKC__SHIFT 0x00000014 9103*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC_MASK 0x000f0000L 9104*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKC__UNIPHY_IMPCAL_VALUE_LINKC__SHIFT 0x00000010 9105*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK_MASK 0x00000400L 9106*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_AK__SHIFT 0x0000000a 9107*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD_MASK 0x00000200L 9108*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_CALOUT_ERROR_LINKD__SHIFT 0x00000009 9109*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD_MASK 0x00000100L 9110*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_CALOUT_LINKD__SHIFT 0x00000008 9111*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD_MASK 0x00000001L 9112*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_ENABLE_LINKD__SHIFT 0x00000000 9113*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD_MASK 0x10000000L 9114*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKD__SHIFT 0x0000001c 9115*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD_MASK 0x0f000000L 9116*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_OVERRIDE_LINKD__SHIFT 0x00000018 9117*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD_MASK 0x40000000L 9118*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_SEL_LINKD__SHIFT 0x0000001e 9119*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD_MASK 0x00f00000L 9120*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_STEP_DELAY_LINKD__SHIFT 0x00000014 9121*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD_MASK 0x000f0000L 9122*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKD__UNIPHY_IMPCAL_VALUE_LINKD__SHIFT 0x00000010 9123*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK_MASK 0x00000400L 9124*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_AK__SHIFT 0x0000000a 9125*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE_MASK 0x00000200L 9126*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_CALOUT_ERROR_LINKE__SHIFT 0x00000009 9127*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE_MASK 0x00000100L 9128*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_CALOUT_LINKE__SHIFT 0x00000008 9129*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE_MASK 0x00000001L 9130*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_ENABLE_LINKE__SHIFT 0x00000000 9131*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE_MASK 0x10000000L 9132*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKE__SHIFT 0x0000001c 9133*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE_MASK 0x0f000000L 9134*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_OVERRIDE_LINKE__SHIFT 0x00000018 9135*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE_MASK 0x40000000L 9136*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_SEL_LINKE__SHIFT 0x0000001e 9137*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE_MASK 0x00f00000L 9138*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_STEP_DELAY_LINKE__SHIFT 0x00000014 9139*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE_MASK 0x000f0000L 9140*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKE__UNIPHY_IMPCAL_VALUE_LINKE__SHIFT 0x00000010 9141*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK_MASK 0x00000400L 9142*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_AK__SHIFT 0x0000000a 9143*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF_MASK 0x00000200L 9144*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_CALOUT_ERROR_LINKF__SHIFT 0x00000009 9145*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF_MASK 0x00000100L 9146*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_CALOUT_LINKF__SHIFT 0x00000008 9147*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF_MASK 0x00000001L 9148*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_ENABLE_LINKF__SHIFT 0x00000000 9149*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF_MASK 0x10000000L 9150*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_ENABLE_LINKF__SHIFT 0x0000001c 9151*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF_MASK 0x0f000000L 9152*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_OVERRIDE_LINKF__SHIFT 0x00000018 9153*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF_MASK 0x40000000L 9154*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_SEL_LINKF__SHIFT 0x0000001e 9155*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF_MASK 0x00f00000L 9156*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_STEP_DELAY_LINKF__SHIFT 0x00000014 9157*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF_MASK 0x000f0000L 9158*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_LINKF__UNIPHY_IMPCAL_VALUE_LINKF__SHIFT 0x00000010 9159*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD_MASK 0xffffffffL 9160*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PERIOD__UNIPHY_IMPCAL_PERIOD__SHIFT 0x00000000 9161*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA_MASK 0x00007fffL 9162*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKA__SHIFT 0x00000000 9163*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB_MASK 0x7fff0000L 9164*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_AB__UNIPHY_IMPCAL_PSW_LINKB__SHIFT 0x00000010 9165*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC_MASK 0x00007fffL 9166*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKC__SHIFT 0x00000000 9167*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD_MASK 0x7fff0000L 9168*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_CD__UNIPHY_IMPCAL_PSW_LINKD__SHIFT 0x00000010 9169*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE_MASK 0x00007fffL 9170*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKE__SHIFT 0x00000000 9171*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF_MASK 0x7fff0000L 9172*b843c749SSergey Zigachev #define UNIPHY_IMPCAL_PSW_EF__UNIPHY_IMPCAL_PSW_LINKF__SHIFT 0x00000010 9173*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT_MASK 0x00001000L 9174*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL0_INVERT__SHIFT 0x0000000c 9175*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT_MASK 0x00002000L 9176*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL1_INVERT__SHIFT 0x0000000d 9177*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT_MASK 0x00004000L 9178*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL2_INVERT__SHIFT 0x0000000e 9179*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT_MASK 0x00008000L 9180*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_CHANNEL3_INVERT__SHIFT 0x0000000f 9181*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY_MASK 0x00700000L 9182*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_LANE_STAGGER_DELAY__SHIFT 0x00000014 9183*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK_MASK 0x00030000L 9184*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_LINK_ENABLE_HPD_MASK__SHIFT 0x00000010 9185*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_MASK 0x00000700L 9186*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_MINIMUM_PIXVLD_LOW_DURATION__SHIFT 0x00000008 9187*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG_MASK 0x00000001L 9188*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_PFREQCHG__SHIFT 0x00000000 9189*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET_MASK 0x00000010L 9190*b843c749SSergey Zigachev #define UNIPHY_LINK_CNTL__UNIPHY_PIXVLD_RESET__SHIFT 0x00000004 9191*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL_MASK 0x00ff0000L 9192*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_BW_CNTL__SHIFT 0x00000010 9193*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN_MASK 0x00000008L 9194*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLK_EN__SHIFT 0x00000003 9195*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN_MASK 0x000000f0L 9196*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_CLKPH_EN__SHIFT 0x00000004 9197*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE_MASK 0x00000001L 9198*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_ENABLE__SHIFT 0x00000000 9199*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN_MASK 0x00000004L 9200*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_EXT_RESET_EN__SHIFT 0x00000002 9201*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL_MASK 0x00007f00L 9202*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_LF_CNTL__SHIFT 0x00000008 9203*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET_MASK 0x00000002L 9204*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_RESET__SHIFT 0x00000001 9205*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN_MASK 0x02000000L 9206*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_EN__SHIFT 0x00000019 9207*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC_MASK 0x01000000L 9208*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_BYPCLK_SRC__SHIFT 0x00000018 9209*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN_MASK 0x04000000L 9210*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_PLL_TEST_VCTL_ADC_EN__SHIFT 0x0000001a 9211*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE_MASK 0x30000000L 9212*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL1__UNIPHY_VCO_MODE__SHIFT 0x0000001c 9213*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV_MASK 0x00002000L 9214*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_CLKINV__SHIFT 0x0000000d 9215*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL_MASK 0x0000000cL 9216*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_DPLLSEL__SHIFT 0x00000002 9217*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN_MASK 0x00001000L 9218*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_EN__SHIFT 0x0000000c 9219*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL_MASK 0x00000010L 9220*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IDCLK_SEL__SHIFT 0x00000004 9221*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL_MASK 0x00000020L 9222*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IPCIE_REFCLK_SEL__SHIFT 0x00000005 9223*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL_MASK 0x00000040L 9224*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_IXTALIN_SEL__SHIFT 0x00000006 9225*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN_MASK 0x00000800L 9226*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PCIEREF_CLK_EN__SHIFT 0x0000000b 9227*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL_MASK 0x00100000L 9228*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIVFRAC_SEL__SHIFT 0x00000014 9229*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL_MASK 0xe0000000L 9230*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PDIV_SEL__SHIFT 0x0000001d 9231*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE_MASK 0x00000003L 9232*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_DISPCLK_MODE__SHIFT 0x00000000 9233*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC_MASK 0x00000700L 9234*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFCLK_SRC__SHIFT 0x00000008 9235*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV_MASK 0x1f000000L 9236*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_REFDIV__SHIFT 0x00000018 9237*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS_MASK 0x00080000L 9238*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_TEST_FBDIV_FRAC_BYPASS__SHIFT 0x00000013 9239*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL_MASK 0x00010000L 9240*b843c749SSergey Zigachev #define UNIPHY_PLL_CONTROL2__UNIPHY_PLL_VTOI_BIAS_CNTL__SHIFT 0x00000010 9241*b843c749SSergey Zigachev #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION_MASK 0x0000fffcL 9242*b843c749SSergey Zigachev #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_FRACTION__SHIFT 0x00000002 9243*b843c749SSergey Zigachev #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV_MASK 0x0fff0000L 9244*b843c749SSergey Zigachev #define UNIPHY_PLL_FBDIV__UNIPHY_PLL_FBDIV__SHIFT 0x00000010 9245*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN_MASK 0x00001000L 9246*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_DSMOD_EN__SHIFT 0x0000000c 9247*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN_MASK 0x00002000L 9248*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_EN__SHIFT 0x0000000d 9249*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM_MASK 0x00000fffL 9250*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_CNTL__UNIPHY_PLL_SS_STEP_NUM__SHIFT 0x00000000 9251*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE_MASK 0x03ffffffL 9252*b843c749SSergey Zigachev #define UNIPHY_PLL_SS_STEP_SIZE__UNIPHY_PLL_SS_STEP_SIZE__SHIFT 0x00000000 9253*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45_MASK 0x000f0000L 9254*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ0P45__SHIFT 0x00000010 9255*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00_MASK 0x00000f00L 9256*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P00__SHIFT 0x00000008 9257*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25_MASK 0x0000f000L 9258*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGADJ1P25__SHIFT 0x0000000c 9259*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN_MASK 0x00000001L 9260*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BGPDN__SHIFT 0x00000000 9261*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL_MASK 0x00000004L 9262*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_BIASREF_SEL__SHIFT 0x00000002 9263*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC_MASK 0x00000002L 9264*b843c749SSergey Zigachev #define UNIPHY_POWER_CONTROL__UNIPHY_RST_LOGIC__SHIFT 0x00000001 9265*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR_MASK 0x01f00000L 9266*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_ERROR__SHIFT 0x00000014 9267*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET_MASK 0x00008000L 9268*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_RESET__SHIFT 0x0000000f 9269*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL_MASK 0x00010000L 9270*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_DIG_BIST_SEL__SHIFT 0x00000010 9271*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET_MASK 0x20000000L 9272*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_INTRESET__SHIFT 0x0000001d 9273*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK_MASK 0x10000000L 9274*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_FREQ_LOCK__SHIFT 0x0000001c 9275*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC_MASK 0x0e000000L 9276*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_PLL_TEST_VCTL_ADC__SHIFT 0x00000019 9277*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL_MASK 0x0000001fL 9278*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_CNTL__SHIFT 0x00000000 9279*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN_MASK 0x00020000L 9280*b843c749SSergey Zigachev #define UNIPHY_REG_TEST_OUTPUT__UNIPHY_TEST_VCTL_EN__SHIFT 0x00000011 9281*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET_MASK 0x00000001L 9282*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCA_SOFT_RESET__SHIFT 0x00000000 9283*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET_MASK 0x00000002L 9284*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCB_SOFT_RESET__SHIFT 0x00000001 9285*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET_MASK 0x00000004L 9286*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCC_SOFT_RESET__SHIFT 0x00000002 9287*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET_MASK 0x00000008L 9288*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCD_SOFT_RESET__SHIFT 0x00000003 9289*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET_MASK 0x00000010L 9290*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCE_SOFT_RESET__SHIFT 0x00000004 9291*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET_MASK 0x00000020L 9292*b843c749SSergey Zigachev #define UNIPHY_SOFT_RESET__DSYNCF_SOFT_RESET__SHIFT 0x00000005 9293*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0_MASK 0x00000007L 9294*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR0__SHIFT 0x00000000 9295*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1_MASK 0x00000070L 9296*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR1__SHIFT 0x00000004 9297*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2_MASK 0x00000700L 9298*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR2__SHIFT 0x00000008 9299*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3_MASK 0x00007000L 9300*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR3__SHIFT 0x0000000c 9301*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4_MASK 0x00070000L 9302*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_PREMPH_STR4__SHIFT 0x00000010 9303*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0_MASK 0x00300000L 9304*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS0__SHIFT 0x00000014 9305*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1_MASK 0x00c00000L 9306*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS1__SHIFT 0x00000016 9307*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2_MASK 0x03000000L 9308*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS2__SHIFT 0x00000018 9309*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3_MASK 0x0c000000L 9310*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS3__SHIFT 0x0000001a 9311*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4_MASK 0x30000000L 9312*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL1__UNIPHY_TX_VS4__SHIFT 0x0000001c 9313*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC_MASK 0x00000003L 9314*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH0_PC__SHIFT 0x00000000 9315*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC_MASK 0x00000030L 9316*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH1_PC__SHIFT 0x00000004 9317*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC_MASK 0x00000300L 9318*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH2_PC__SHIFT 0x00000008 9319*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC_MASK 0x00003000L 9320*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH3_PC__SHIFT 0x0000000c 9321*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC_MASK 0x00030000L 9322*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH4_PC__SHIFT 0x00000010 9323*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL_MASK 0x00100000L 9324*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_PREMPH_SEL__SHIFT 0x00000014 9325*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL_MASK 0x00600000L 9326*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT0_CPSEL__SHIFT 0x00000015 9327*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL_MASK 0x01800000L 9328*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT1_CPSEL__SHIFT 0x00000017 9329*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL_MASK 0x06000000L 9330*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT2_CPSEL__SHIFT 0x00000019 9331*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL_MASK 0x18000000L 9332*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT3_CPSEL__SHIFT 0x0000001b 9333*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL_MASK 0x60000000L 9334*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL2__UNIPHY_RT4_CPSEL__SHIFT 0x0000001d 9335*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN_MASK 0x80000000L 9336*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_LVDS_PULLDWN__SHIFT 0x0000001f 9337*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0_MASK 0x00100000L 9338*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL0__SHIFT 0x00000014 9339*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1_MASK 0x00200000L 9340*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL1__SHIFT 0x00000015 9341*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2_MASK 0x00400000L 9342*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL2__SHIFT 0x00000016 9343*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3_MASK 0x00800000L 9344*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PESEL3__SHIFT 0x00000017 9345*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK_MASK 0x000000f0L 9346*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_CLK__SHIFT 0x00000004 9347*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT_MASK 0x00000f00L 9348*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_CS_DAT__SHIFT 0x00000008 9349*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK_MASK 0x00000003L 9350*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_CLK__SHIFT 0x00000000 9351*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT_MASK 0x0000000cL 9352*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_PW_DAT__SHIFT 0x00000002 9353*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK_MASK 0x00007000L 9354*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_CLK__SHIFT 0x0000000c 9355*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT_MASK 0x00070000L 9356*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_PREMPH_STR_DAT__SHIFT 0x00000010 9357*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ_MASK 0x1f000000L 9358*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL3__UNIPHY_TX_VS_ADJ__SHIFT 0x00000018 9359*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK_MASK 0x0000001fL 9360*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_CLK__SHIFT 0x00000000 9361*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT_MASK 0x000003e0L 9362*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_NVS_DAT__SHIFT 0x00000005 9363*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK_MASK 0x07000000L 9364*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_CLK__SHIFT 0x00000018 9365*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT_MASK 0x70000000L 9366*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_OP_DAT__SHIFT 0x0000001c 9367*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK_MASK 0x0001f000L 9368*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_CLK__SHIFT 0x0000000c 9369*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT_MASK 0x003e0000L 9370*b843c749SSergey Zigachev #define UNIPHY_TX_CONTROL4__UNIPHY_TX_PVS_DAT__SHIFT 0x00000011 9371*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE_MASK 0x0000001fL 9372*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_CAL_MODE__SHIFT 0x00000000 9373*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP_MASK 0x00000f00L 9374*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_CP__SHIFT 0x00000008 9375*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS_MASK 0xff000000L 9376*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_IBIAS__SHIFT 0x00000018 9377*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE_MASK 0x001ff000L 9378*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_LF_MODE__SHIFT 0x0000000c 9379*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9380*b843c749SSergey Zigachev #define VGA25_PPLL_ANALOG__VGA25_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9381*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9382*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9383*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9384*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9385*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV_MASK 0x07ff0000L 9386*b843c749SSergey Zigachev #define VGA25_PPLL_FB_DIV__VGA25_PPLL_FB_DIV__SHIFT 0x00000010 9387*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9388*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9389*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9390*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9391*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9392*b843c749SSergey Zigachev #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9393*b843c749SSergey Zigachev #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV_MASK 0x000003ffL 9394*b843c749SSergey Zigachev #define VGA25_PPLL_REF_DIV__VGA25_PPLL_REF_DIV__SHIFT 0x00000000 9395*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE_MASK 0x0000001fL 9396*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_CAL_MODE__SHIFT 0x00000000 9397*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP_MASK 0x00000f00L 9398*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_CP__SHIFT 0x00000008 9399*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS_MASK 0xff000000L 9400*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_IBIAS__SHIFT 0x00000018 9401*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE_MASK 0x001ff000L 9402*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_LF_MODE__SHIFT 0x0000000c 9403*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9404*b843c749SSergey Zigachev #define VGA28_PPLL_ANALOG__VGA28_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9405*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9406*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9407*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9408*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9409*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV_MASK 0x07ff0000L 9410*b843c749SSergey Zigachev #define VGA28_PPLL_FB_DIV__VGA28_PPLL_FB_DIV__SHIFT 0x00000010 9411*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9412*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9413*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9414*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9415*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9416*b843c749SSergey Zigachev #define VGA28_PPLL_POST_DIV__VGA28_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9417*b843c749SSergey Zigachev #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV_MASK 0x000003ffL 9418*b843c749SSergey Zigachev #define VGA28_PPLL_REF_DIV__VGA28_PPLL_REF_DIV__SHIFT 0x00000000 9419*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE_MASK 0x0000001fL 9420*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_CAL_MODE__SHIFT 0x00000000 9421*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP_MASK 0x00000f00L 9422*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_CP__SHIFT 0x00000008 9423*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS_MASK 0xff000000L 9424*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_IBIAS__SHIFT 0x00000018 9425*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE_MASK 0x001ff000L 9426*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_LF_MODE__SHIFT 0x0000000c 9427*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL_MASK 0x00000060L 9428*b843c749SSergey Zigachev #define VGA41_PPLL_ANALOG__VGA41_PPLL_PFD_PULSE_SEL__SHIFT 0x00000005 9429*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL_MASK 0x00000030L 9430*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_CNTL__SHIFT 0x00000004 9431*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION_MASK 0x0000000fL 9432*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_FRACTION__SHIFT 0x00000000 9433*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV_MASK 0x07ff0000L 9434*b843c749SSergey Zigachev #define VGA41_PPLL_FB_DIV__VGA41_PPLL_FB_DIV__SHIFT 0x00000010 9435*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK_MASK 0x00007f00L 9436*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_DVOCLK__SHIFT 0x00000008 9437*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK_MASK 0x007f0000L 9438*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_IDCLK__SHIFT 0x00000010 9439*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL 9440*b843c749SSergey Zigachev #define VGA41_PPLL_POST_DIV__VGA41_PPLL_POST_DIV_PIXCLK__SHIFT 0x00000000 9441*b843c749SSergey Zigachev #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV_MASK 0x000003ffL 9442*b843c749SSergey Zigachev #define VGA41_PPLL_REF_DIV__VGA41_PPLL_REF_DIV__SHIFT 0x00000000 9443*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY_MASK 0x00100000L 9444*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_DCCIF_W256ONLY__SHIFT 0x00000014 9445*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT_MASK 0x3f000000L 9446*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_DCCIF_WC_TIMEOUT__SHIFT 0x00000018 9447*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE_MASK 0x00010000L 9448*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_READ_BUFFER_INVALIDATE__SHIFT 0x00000010 9449*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE_MASK 0x00000100L 9450*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_READ_CACHE_DISABLE__SHIFT 0x00000008 9451*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS_MASK 0x00000001L 9452*b843c749SSergey Zigachev #define VGA_CACHE_CONTROL__VGA_WRITE_THROUGH_CACHE_DIS__SHIFT 0x00000000 9453*b843c749SSergey Zigachev #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C_MASK 0xffffffffL 9454*b843c749SSergey Zigachev #define VGADCC_DBG_DCCIF_C__DBG_DCCIF_C__SHIFT 0x00000000 9455*b843c749SSergey Zigachev #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA_MASK 0xffffffffL 9456*b843c749SSergey Zigachev #define VGA_DEBUG_READBACK_DATA__VGA_DEBUG_READBACK_DATA__SHIFT 0x00000000 9457*b843c749SSergey Zigachev #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX_MASK 0x000000ffL 9458*b843c749SSergey Zigachev #define VGA_DEBUG_READBACK_INDEX__VGA_DEBUG_READBACK_INDEX__SHIFT 0x00000000 9459*b843c749SSergey Zigachev #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR_MASK 0x01ffffffL 9460*b843c749SSergey Zigachev #define VGA_DISPBUF1_SURFACE_ADDR__VGA_DISPBUF1_SURFACE_ADDR__SHIFT 0x00000000 9461*b843c749SSergey Zigachev #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR_MASK 0x01ffffffL 9462*b843c749SSergey Zigachev #define VGA_DISPBUF2_SURFACE_ADDR__VGA_DISPBUF2_SURFACE_ADDR__SHIFT 0x00000000 9463*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK 0x00000010L 9464*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_MEMORY_DISABLE__SHIFT 0x00000004 9465*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN_MASK 0x00000001L 9466*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_MEM_PAGE_SELECT_EN__SHIFT 0x00000000 9467*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE_MASK 0x00000100L 9468*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_RBBM_LOCK_DISABLE__SHIFT 0x00000008 9469*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_SOFT_RESET_MASK 0x00010000L 9470*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_SOFT_RESET__SHIFT 0x00000010 9471*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL_MASK 0x01000000L 9472*b843c749SSergey Zigachev #define VGA_HDP_CONTROL__VGA_TEST_RESET_CONTROL__SHIFT 0x00000018 9473*b843c749SSergey Zigachev #define VGA_HW_DEBUG__VGA_HW_DEBUG_MASK 0xffffffffL 9474*b843c749SSergey Zigachev #define VGA_HW_DEBUG__VGA_HW_DEBUG__SHIFT 0x00000000 9475*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK_MASK 0x00010000L 9476*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_DISPLAY_SWITCH_INT_MASK__SHIFT 0x00000010 9477*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK_MASK 0x00000001L 9478*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_MEM_ACCESS_INT_MASK__SHIFT 0x00000000 9479*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK_MASK 0x01000000L 9480*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_MODE_AUTO_TRIGGER_INT_MASK__SHIFT 0x00000018 9481*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK_MASK 0x00000100L 9482*b843c749SSergey Zigachev #define VGA_INTERRUPT_CONTROL__VGA_REG_ACCESS_INT_MASK__SHIFT 0x00000008 9483*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS_MASK 0x00000004L 9484*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_DISPLAY_SWITCH_INT_STATUS__SHIFT 0x00000002 9485*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS_MASK 0x00000001L 9486*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_MEM_ACCESS_INT_STATUS__SHIFT 0x00000000 9487*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS_MASK 0x00000008L 9488*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_MODE_AUTO_TRIGGER_INT_STATUS__SHIFT 0x00000003 9489*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L 9490*b843c749SSergey Zigachev #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS__SHIFT 0x00000001 9491*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT_MASK 0x00000003L 9492*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_CRTC_TIMEOUT__SHIFT 0x00000000 9493*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE_MASK 0x20000000L 9494*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_EXTERNAL_DAC_SENSE__SHIFT 0x0000001d 9495*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT_MASK 0x80000000L 9496*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_MAIN_TEST_VSTATUS_NO_DISPLAY_CRTC_TIMEOUT__SHIFT 0x0000001f 9497*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT_MASK 0x03000000L 9498*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_CRT_INTR_SOURCE_SELECT__SHIFT 0x00000018 9499*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT_MASK 0x00030000L 9500*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_NO_DISPLAY_SOURCE_SELECT__SHIFT 0x00000010 9501*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT_MASK 0x04000000L 9502*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_SENSE_SWITCH_SELECT__SHIFT 0x0000001a 9503*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT_MASK 0x00000300L 9504*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READBACK_VGA_VSTATUS_SOURCE_SELECT__SHIFT 0x00000008 9505*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE_MASK 0x08000000L 9506*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_READ_URGENT_ENABLE__SHIFT 0x0000001b 9507*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT_MASK 0x00000018L 9508*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_RENDER_TIMEOUT_COUNT__SHIFT 0x00000003 9509*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION_MASK 0x000000e0L 9510*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_VIRTUAL_VERTICAL_RETRACE_DURATION__SHIFT 0x00000005 9511*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE_MASK 0x10000000L 9512*b843c749SSergey Zigachev #define VGA_MAIN_CONTROL__VGA_WRITES_URGENT_ENABLE__SHIFT 0x0000001c 9513*b843c749SSergey Zigachev #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH_MASK 0x000000ffL 9514*b843c749SSergey Zigachev #define VGA_MEMORY_BASE_ADDRESS_HIGH__VGA_MEMORY_BASE_ADDRESS_HIGH__SHIFT 0x00000000 9515*b843c749SSergey Zigachev #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS_MASK 0xffffffffL 9516*b843c749SSergey Zigachev #define VGA_MEMORY_BASE_ADDRESS__VGA_MEMORY_BASE_ADDRESS__SHIFT 0x00000000 9517*b843c749SSergey Zigachev #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003ffL 9518*b843c749SSergey Zigachev #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x00000000 9519*b843c749SSergey Zigachev #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03ff0000L 9520*b843c749SSergey Zigachev #define VGA_MEM_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x00000010 9521*b843c749SSergey Zigachev #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003ffL 9522*b843c749SSergey Zigachev #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x00000000 9523*b843c749SSergey Zigachev #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03ff0000L 9524*b843c749SSergey Zigachev #define VGA_MEM_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x00000010 9525*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING_MASK 0x00000100L 9526*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_128K_APERTURE_PAGING__SHIFT 0x00000008 9527*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_ATI_LINEAR_MASK 0x00000001L 9528*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_ATI_LINEAR__SHIFT 0x00000000 9529*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE_MASK 0x00000030L 9530*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_LUT_PALETTE_UPDATE_MODE__SHIFT 0x00000004 9531*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN_MASK 0x00010000L 9532*b843c749SSergey Zigachev #define VGA_MODE_CONTROL__VGA_TEXT_132_COLUMNS_EN__SHIFT 0x00000010 9533*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_BLINK_MODE_MASK 0x00000060L 9534*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x00000005 9535*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_BLINK_RATE_MASK 0x0000001fL 9536*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x00000000 9537*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT_MASK 0x00000080L 9538*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_CURSOR_BLINK_INVERT__SHIFT 0x00000007 9539*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE_MASK 0x00000100L 9540*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_EXTD_ADDR_COUNT_ENABLE__SHIFT 0x00000008 9541*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT_MASK 0x01000000L 9542*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_LOCK_8DOT__SHIFT 0x00000018 9543*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL_MASK 0x02000000L 9544*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGAREG_LINECMP_COMPATIBILITY_SEL__SHIFT 0x00000019 9545*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK 0x00030000L 9546*b843c749SSergey Zigachev #define VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL__SHIFT 0x00000010 9547*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000001L 9548*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D1_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000000 9549*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000100L 9550*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D1_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000008 9551*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000002L 9552*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D2_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000001 9553*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000200L 9554*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D2_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x00000009 9555*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000004L 9556*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D3_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000002 9557*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000400L 9558*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D3_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000a 9559*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000008L 9560*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D4_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000003 9561*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00000800L 9562*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D4_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000b 9563*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000010L 9564*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D5_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000004 9565*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00001000L 9566*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D5_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000c 9567*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET_MASK 0x00000020L 9568*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D6_BLANK_DISPLAY_WHEN_SEQUENCER_RESET__SHIFT 0x00000005 9569*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET_MASK 0x00002000L 9570*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__D6_DISABLE_SYNCS_AND_DE_WHEN_SEQUENCER_RESET__SHIFT 0x0000000d 9571*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE_MASK 0x00010000L 9572*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_ENABLE__SHIFT 0x00000010 9573*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT_MASK 0x00fc0000L 9574*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_INDEX_SELECT__SHIFT 0x00000012 9575*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT_MASK 0x00020000L 9576*b843c749SSergey Zigachev #define VGA_SEQUENCER_RESET_CONTROL__VGA_MODE_AUTO_TRIGGER_REGISTER_SELECT__SHIFT 0x00000011 9577*b843c749SSergey Zigachev #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A_MASK 0x00000007L 9578*b843c749SSergey Zigachev #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_A__SHIFT 0x00000000 9579*b843c749SSergey Zigachev #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B_MASK 0x00000700L 9580*b843c749SSergey Zigachev #define VGA_SOURCE_SELECT__VGA_SOURCE_SEL_B__SHIFT 0x00000008 9581*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR_MASK 0x00010000L 9582*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_DISPLAY_SWITCH_INT_CLEAR__SHIFT 0x00000010 9583*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR_MASK 0x00000001L 9584*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_MEM_ACCESS_INT_CLEAR__SHIFT 0x00000000 9585*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR_MASK 0x01000000L 9586*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_MODE_AUTO_TRIGGER_INT_CLEAR__SHIFT 0x00000018 9587*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR_MASK 0x00000100L 9588*b843c749SSergey Zigachev #define VGA_STATUS_CLEAR__VGA_REG_ACCESS_INT_CLEAR__SHIFT 0x00000008 9589*b843c749SSergey Zigachev #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS_MASK 0x00000004L 9590*b843c749SSergey Zigachev #define VGA_STATUS__VGA_DISPLAY_SWITCH_STATUS__SHIFT 0x00000002 9591*b843c749SSergey Zigachev #define VGA_STATUS__VGA_MEM_ACCESS_STATUS_MASK 0x00000001L 9592*b843c749SSergey Zigachev #define VGA_STATUS__VGA_MEM_ACCESS_STATUS__SHIFT 0x00000000 9593*b843c749SSergey Zigachev #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS_MASK 0x00000008L 9594*b843c749SSergey Zigachev #define VGA_STATUS__VGA_MODE_AUTO_TRIGGER_STATUS__SHIFT 0x00000003 9595*b843c749SSergey Zigachev #define VGA_STATUS__VGA_REG_ACCESS_STATUS_MASK 0x00000002L 9596*b843c749SSergey Zigachev #define VGA_STATUS__VGA_REG_ACCESS_STATUS__SHIFT 0x00000001 9597*b843c749SSergey Zigachev #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT_MASK 0x00000300L 9598*b843c749SSergey Zigachev #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_HEIGHT_SELECT__SHIFT 0x00000008 9599*b843c749SSergey Zigachev #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT_MASK 0x00000003L 9600*b843c749SSergey Zigachev #define VGA_SURFACE_PITCH_SELECT__VGA_SURFACE_PITCH_SELECT__SHIFT 0x00000000 9601*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_ENABLE_MASK 0x00000001L 9602*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_ENABLE__SHIFT 0x00000000 9603*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT_MASK 0x01000000L 9604*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DISPBUF_SELECT__SHIFT 0x00000018 9605*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE_MASK 0x00010000L 9606*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_DONE__SHIFT 0x00000010 9607*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START_MASK 0x00000100L 9608*b843c749SSergey Zigachev #define VGA_TEST_CONTROL__VGA_TEST_RENDER_START__SHIFT 0x00000008 9609*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA_MASK 0xffffffffL 9610*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_DATA__VGA_TEST_DEBUG_DATA__SHIFT 0x00000000 9611*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9612*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9613*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9614*b843c749SSergey Zigachev #define VGA_TEST_DEBUG_INDEX__VGA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9615*b843c749SSergey Zigachev #define VIEWPORT_SIZE__VIEWPORT_HEIGHT_MASK 0x00003fffL 9616*b843c749SSergey Zigachev #define VIEWPORT_SIZE__VIEWPORT_HEIGHT__SHIFT 0x00000000 9617*b843c749SSergey Zigachev #define VIEWPORT_SIZE__VIEWPORT_WIDTH_MASK 0x3fff0000L 9618*b843c749SSergey Zigachev #define VIEWPORT_SIZE__VIEWPORT_WIDTH__SHIFT 0x00000010 9619*b843c749SSergey Zigachev #define VIEWPORT_START__VIEWPORT_X_START_MASK 0x3fff0000L 9620*b843c749SSergey Zigachev #define VIEWPORT_START__VIEWPORT_X_START__SHIFT 0x00000010 9621*b843c749SSergey Zigachev #define VIEWPORT_START__VIEWPORT_Y_START_MASK 0x00003fffL 9622*b843c749SSergey Zigachev #define VIEWPORT_START__VIEWPORT_Y_START__SHIFT 0x00000000 9623*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS_MASK 0x00008000L 9624*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_GATE_DIS__SHIFT 0x0000000f 9625*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS_MASK 0x00080000L 9626*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_MSTAT_GATE_DIS__SHIFT 0x00000013 9627*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS_MASK 0x00040000L 9628*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SDYN_GATE_DIS__SHIFT 0x00000012 9629*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS_MASK 0x00100000L 9630*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_G_SSTAT_GATE_DIS__SHIFT 0x00000014 9631*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS_MASK 0x00010000L 9632*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_REG_GATE_DIS__SHIFT 0x00000010 9633*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY_MASK 0x00000ff0L 9634*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_OFF_DELAY__SHIFT 0x00000004 9635*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY_MASK 0x0000000fL 9636*b843c749SSergey Zigachev #define XDMA_CLOCK_GATING_CNTL__XDMA_SCLK_TURN_ON_DELAY__SHIFT 0x00000000 9637*b843c749SSergey Zigachev #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR_MASK 0x00000100L 9638*b843c749SSergey Zigachev #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_CLEAR__SHIFT 0x00000008 9639*b843c749SSergey Zigachev #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS_MASK 0x0000000fL 9640*b843c749SSergey Zigachev #define XDMA_IF_BIF_STATUS__XDMA_IF_BIF_ERROR_STATUS__SHIFT 0x00000000 9641*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK_MASK 0x00000400L 9642*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_ACK__SHIFT 0x0000000a 9643*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK_MASK 0x00000200L 9644*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_MASK__SHIFT 0x00000009 9645*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT_MASK 0x00000100L 9646*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_MEM_URGENT_STAT__SHIFT 0x00000008 9647*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK_MASK 0x00004000L 9648*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_ACK__SHIFT 0x0000000e 9649*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK_MASK 0x00002000L 9650*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_MASK__SHIFT 0x0000000d 9651*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT_MASK 0x00001000L 9652*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_MSTR_UNDERFLOW_STAT__SHIFT 0x0000000c 9653*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK_MASK 0x00040000L 9654*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_ACK__SHIFT 0x00000012 9655*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK_MASK 0x00020000L 9656*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_MASK__SHIFT 0x00000011 9657*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT_MASK 0x00010000L 9658*b843c749SSergey Zigachev #define XDMA_INTERRUPT__XDMA_SLV_READ_URGENT_STAT__SHIFT 0x00000010 9659*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE_MASK 0x0000000fL 9660*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_ARRAY_MODE__SHIFT 0x00000000 9661*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT_MASK 0x00000c00L 9662*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_HEIGHT__SHIFT 0x0000000a 9663*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH_MASK 0x00000300L 9664*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_BANK_WIDTH__SHIFT 0x00000008 9665*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT_MASK 0x00003000L 9666*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_MACRO_TILE_ASPECT__SHIFT 0x0000000c 9667*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS_MASK 0x00300000L 9668*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_NUM_BANKS__SHIFT 0x00000014 9669*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT_MASK 0x00000070L 9670*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING1__XDMA_LOCAL_TILE_SPLIT__SHIFT 0x00000004 9671*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE_MASK 0x00c00000L 9672*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_MICRO_TILE_MODE__SHIFT 0x00000016 9673*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG_MASK 0xf8000000L 9674*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_CONFIG__SHIFT 0x0000001b 9675*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE_MASK 0x00000007L 9676*b843c749SSergey Zigachev #define XDMA_LOCAL_SURFACE_TILING2__XDMA_LOCAL_PIPE_INTERLEAVE_SIZE__SHIFT 0x00000000 9677*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV_MASK 0x00010000L 9678*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_PRIV__SHIFT 0x00000010 9679*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP_MASK 0x00000300L 9680*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_SWAP__SHIFT 0x00000008 9681*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID_MASK 0x0000f000L 9682*b843c749SSergey Zigachev #define XDMA_MC_PCIE_CLIENT_CONFIG__XDMA_MC_PCIE_VMID__SHIFT 0x0000000c 9683*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS_MASK 0x00000001L 9684*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_DIS__SHIFT 0x00000000 9685*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE_MASK 0x00010000L 9686*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_LIGHT_SLEEP_MODE_FORCE__SHIFT 0x00000010 9687*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE_MASK 0xc0000000L 9688*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_POWER_STATE__SHIFT 0x0000001e 9689*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS_MASK 0x00000100L 9690*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_DIS__SHIFT 0x00000008 9691*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE_MASK 0x01000000L 9692*b843c749SSergey Zigachev #define XDMA_MEM_POWER_CNTL__XDMA_MEM_SHUTDOWN_MODE_FORCE__SHIFT 0x00000018 9693*b843c749SSergey Zigachev #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL_MASK 0x00000f00L 9694*b843c749SSergey Zigachev #define XDMA_MSTR_CMD_URGENT_CNTL__XDMA_MSTR_CMD_URGENT_LEVEL__SHIFT 0x00000008 9695*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE_MASK 0x00040000L 9696*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_DEBUG_MODE__SHIFT 0x00000012 9697*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE_MASK 0x00010000L 9698*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_ENABLE__SHIFT 0x00000010 9699*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY_MASK 0x00000200L 9700*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_MEM_READY__SHIFT 0x00000009 9701*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET_MASK 0x00100000L 9702*b843c749SSergey Zigachev #define XDMA_MSTR_CNTL__XDMA_MSTR_SOFT_RESET__SHIFT 0x00000014 9703*b843c749SSergey Zigachev #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT_MASK 0x00003fffL 9704*b843c749SSergey Zigachev #define XDMA_MSTR_HEIGHT__XDMA_MSTR_ACTIVE_HEIGHT__SHIFT 0x00000000 9705*b843c749SSergey Zigachev #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT_MASK 0x3fff0000L 9706*b843c749SSergey Zigachev #define XDMA_MSTR_HEIGHT__XDMA_MSTR_FRAME_HEIGHT__SHIFT 0x00000010 9707*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH_MASK 0x000000ffL 9708*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH__SHIFT 0x00000000 9709*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_MASK 0xffffffffL 9710*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__XDMA_MSTR_LOCAL_SURFACE_BASE_ADDR__SHIFT 0x00000000 9711*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH_MASK 0x00003fffL 9712*b843c749SSergey Zigachev #define XDMA_MSTR_LOCAL_SURFACE_PITCH__XDMA_MSTR_LOCAL_SURFACE_PITCH__SHIFT 0x00000000 9713*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV_MASK 0x00010000L 9714*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_PRIV__SHIFT 0x00000010 9715*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP_MASK 0x00000300L 9716*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_SWAP__SHIFT 0x00000008 9717*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID_MASK 0x0000f000L 9718*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_CLIENT_CONFIG__XDMA_MSTR_MEM_CLIENT_VMID__SHIFT 0x0000000c 9719*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR_MASK 0x00010000L 9720*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_CLR__SHIFT 0x00000010 9721*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_MASK 0x00003000L 9722*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK__SHIFT 0x0000000c 9723*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG_MASK 0x000003ffL 9724*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_NACK_STATUS__XDMA_MSTR_MEM_NACK_TAG__SHIFT 0x00000000 9725*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL_MASK 0x00000001L 9726*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_CLIENT_STALL__SHIFT 0x00000000 9727*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY_MASK 0x0000f000L 9728*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_STALL_DELAY__SHIFT 0x0000000c 9729*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL_MASK 0x00000f00L 9730*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LEVEL__SHIFT 0x00000008 9731*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT_MASK 0x000000f0L 9732*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_LIMIT__SHIFT 0x00000004 9733*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER_MASK 0xffff0000L 9734*b843c749SSergey Zigachev #define XDMA_MSTR_MEM_URGENT_CNTL__XDMA_MSTR_MEM_URGENT_TIMER__SHIFT 0x00000010 9735*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR_MASK 0x00010000L 9736*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_CLR__SHIFT 0x00000010 9737*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_MASK 0x00003000L 9738*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK__SHIFT 0x0000000c 9739*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG_MASK 0x000003ffL 9740*b843c749SSergey Zigachev #define XDMA_MSTR_PCIE_NACK_STATUS__XDMA_MSTR_PCIE_NACK_TAG__SHIFT 0x00000000 9741*b843c749SSergey Zigachev #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH_MASK 0x3fff0000L 9742*b843c749SSergey Zigachev #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_PREFETCH__SHIFT 0x00000010 9743*b843c749SSergey Zigachev #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE_MASK 0x00003fffL 9744*b843c749SSergey Zigachev #define XDMA_MSTR_READ_COMMAND__XDMA_MSTR_REQUEST_SIZE__SHIFT 0x00000000 9745*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9746*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__XDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9747*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9748*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_GPU_ADDRESS__XDMA_MSTR_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9749*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH_MASK 0x000000ffL 9750*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__XDMA_MSTR_REMOTE_SURFACE_BASE_HIGH__SHIFT 0x00000000 9751*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE_MASK 0xffffffffL 9752*b843c749SSergey Zigachev #define XDMA_MSTR_REMOTE_SURFACE_BASE__XDMA_MSTR_REMOTE_SURFACE_BASE__SHIFT 0x00000000 9753*b843c749SSergey Zigachev #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT_MASK 0x00003fffL 9754*b843c749SSergey Zigachev #define XDMA_MSTR_STATUS__XDMA_MSTR_VCOUNT_CURRENT__SHIFT 0x00000000 9755*b843c749SSergey Zigachev #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT_MASK 0x3fff0000L 9756*b843c749SSergey Zigachev #define XDMA_MSTR_STATUS__XDMA_MSTR_WRITE_LINE_CURRENT__SHIFT 0x00000010 9757*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY_MASK 0x00000007L 9758*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_DELAY__SHIFT 0x00000000 9759*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS_MASK 0x00000008L 9760*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_RDWR_TIMEOUT_DIS__SHIFT 0x00000003 9761*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY_MASK 0xffff8000L 9762*b843c749SSergey Zigachev #define XDMA_RBBMIF_RDWR_CNTL__XDMA_RBBMIF_TIMEOUT_DELAY__SHIFT 0x0000000f 9763*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE_MASK 0x00000100L 9764*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_ACTIVE__SHIFT 0x00000008 9765*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE_MASK 0x00010000L 9766*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_ENABLE__SHIFT 0x00000010 9767*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY_MASK 0x00000200L 9768*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_MEM_READY__SHIFT 0x00000009 9769*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN_MASK 0x00080000L 9770*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_READ_LAT_TEST_EN__SHIFT 0x00000013 9771*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET_MASK 0x00100000L 9772*b843c749SSergey Zigachev #define XDMA_SLV_CNTL__XDMA_SLV_SOFT_RESET__SHIFT 0x00000014 9773*b843c749SSergey Zigachev #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING_MASK 0x00000001L 9774*b843c749SSergey Zigachev #define XDMA_SLV_FLIP_PENDING__XDMA_SLV_FLIP_PENDING__SHIFT 0x00000000 9775*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV_MASK 0x00010000L 9776*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_PRIV__SHIFT 0x00000010 9777*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP_MASK 0x00000300L 9778*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_SWAP__SHIFT 0x00000008 9779*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID_MASK 0x0000f000L 9780*b843c749SSergey Zigachev #define XDMA_SLV_MEM_CLIENT_CONFIG__XDMA_SLV_MEM_CLIENT_VMID__SHIFT 0x0000000c 9781*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR_MASK 0x80000000L 9782*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_CLR__SHIFT 0x0000001f 9783*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_MASK 0x00030000L 9784*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK__SHIFT 0x00000010 9785*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG_MASK 0x0000ffffL 9786*b843c749SSergey Zigachev #define XDMA_SLV_MEM_NACK_STATUS__XDMA_SLV_MEM_NACK_TAG__SHIFT 0x00000000 9787*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR_MASK 0x00010000L 9788*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_CLR__SHIFT 0x00000010 9789*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_MASK 0x00003000L 9790*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK__SHIFT 0x0000000c 9791*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG_MASK 0x000003ffL 9792*b843c749SSergey Zigachev #define XDMA_SLV_PCIE_NACK_STATUS__XDMA_SLV_PCIE_NACK_TAG__SHIFT 0x00000000 9793*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC_MASK 0x000fffffL 9794*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_ACC__SHIFT 0x00000000 9795*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT_MASK 0xfff00000L 9796*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_AVE__XDMA_SLV_READ_LATENCY_COUNT__SHIFT 0x00000014 9797*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX_MASK 0xffff0000L 9798*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MAX__SHIFT 0x00000010 9799*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN_MASK 0x0000ffffL 9800*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_MINMAX__XDMA_SLV_READ_LATENCY_MIN__SHIFT 0x00000000 9801*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER_MASK 0x0000ffffL 9802*b843c749SSergey Zigachev #define XDMA_SLV_READ_LATENCY_TIMER__XDMA_SLV_READ_LATENCY_TIMER__SHIFT 0x00000000 9803*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL_MASK 0x00000001L 9804*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_CLIENT_STALL__SHIFT 0x00000000 9805*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY_MASK 0x0000f000L 9806*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_STALL_DELAY__SHIFT 0x0000000c 9807*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL_MASK 0x00000f00L 9808*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LEVEL__SHIFT 0x00000008 9809*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT_MASK 0x000000f0L 9810*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_LIMIT__SHIFT 0x00000004 9811*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER_MASK 0xffff0000L 9812*b843c749SSergey Zigachev #define XDMA_SLV_READ_URGENT_CNTL__XDMA_SLV_READ_URGENT_TIMER__SHIFT 0x00000010 9813*b843c749SSergey Zigachev #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH_MASK 0x000000ffL 9814*b843c749SSergey Zigachev #define XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__XDMA_SLV_REMOTE_GPU_ADDRESS_HIGH__SHIFT 0x00000000 9815*b843c749SSergey Zigachev #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS_MASK 0xffffffffL 9816*b843c749SSergey Zigachev #define XDMA_SLV_REMOTE_GPU_ADDRESS__XDMA_SLV_REMOTE_GPU_ADDRESS__SHIFT 0x00000000 9817*b843c749SSergey Zigachev #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH_MASK 0x00003fffL 9818*b843c749SSergey Zigachev #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_PITCH__SHIFT 0x00000000 9819*b843c749SSergey Zigachev #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH_MASK 0x3fff0000L 9820*b843c749SSergey Zigachev #define XDMA_SLV_SLS_PITCH__XDMA_SLV_SLS_WIDTH__SHIFT 0x00000010 9821*b843c749SSergey Zigachev #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD_MASK 0xffff0000L 9822*b843c749SSergey Zigachev #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_PERIOD__SHIFT 0x00000010 9823*b843c749SSergey Zigachev #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE_MASK 0x000001ffL 9824*b843c749SSergey Zigachev #define XDMA_SLV_WB_RATE_CNTL__XDMA_SLV_WB_BURST_SIZE__SHIFT 0x00000000 9825*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY_MASK 0x0000f000L 9826*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_DELAY__SHIFT 0x0000000c 9827*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL_MASK 0x00000001L 9828*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_STALL__SHIFT 0x00000000 9829*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL_MASK 0x00000f00L 9830*b843c749SSergey Zigachev #define XDMA_SLV_WRITE_URGENT_CNTL__XDMA_SLV_WRITE_URGENT_LEVEL__SHIFT 0x00000008 9831*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA_MASK 0xffffffffL 9832*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_DATA__XDMA_TEST_DEBUG_DATA__SHIFT 0x00000000 9833*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX_MASK 0x000000ffL 9834*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_INDEX__SHIFT 0x00000000 9835*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 9836*b843c749SSergey Zigachev #define XDMA_TEST_DEBUG_INDEX__XDMA_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 9837*b843c749SSergey Zigachev 9838*b843c749SSergey Zigachev #endif 9839