1 /*
2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20  */
21 #ifndef _df_1_7_SH_MASK_HEADER
22 #define _df_1_7_SH_MASK_HEADER
23 
24 /* FabricConfigAccessControl */
25 #define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT						0x0
26 #define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT						0x1
27 #define FabricConfigAccessControl__CfgRegInstID__SHIFT							0x10
28 #define FabricConfigAccessControl__CfgRegInstAccEn_MASK							0x00000001L
29 #define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK						0x00000002L
30 #define FabricConfigAccessControl__CfgRegInstID_MASK							0x00FF0000L
31 
32 /* DF_PIE_AON0_DfGlobalClkGater */
33 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT							0x0
34 #define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK							0x0000000FL
35 
36 /* DF_CS_AON0_DramBaseAddress0 */
37 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal__SHIFT							0x0
38 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT						0x1
39 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT						0x4
40 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT						0x8
41 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr__SHIFT						0xc
42 #define DF_CS_AON0_DramBaseAddress0__AddrRngVal_MASK							0x00000001L
43 #define DF_CS_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK						0x00000002L
44 #define DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK							0x000000F0L
45 #define DF_CS_AON0_DramBaseAddress0__IntLvAddrSel_MASK							0x00000700L
46 #define DF_CS_AON0_DramBaseAddress0__DramBaseAddr_MASK							0xFFFFF000L
47 
48 //DF_CS_AON0_CoherentSlaveModeCtrlA0
49 #define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW__SHIFT					0x3
50 #define DF_CS_AON0_CoherentSlaveModeCtrlA0__ForceParWrRMW_MASK						0x00000008L
51 
52 #endif
53