xref: /dragonfly/sys/dev/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h (revision 655933d6)

/*
 * GFX_8_0 Register documentation
 *
 * Copyright (C) 2014  Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef GFX_8_0_SH_MASK_H
#define GFX_8_0_SH_MASK_H

#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c
#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
#define CB_COLOR_CONTROL__MODE_MASK 0x70
#define CB_COLOR_CONTROL__MODE__SHIFT 0x4
#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000
#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f
#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0
#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00
#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000
#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000
#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000
#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000
#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d
#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000
#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e
#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000
#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f
#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff
#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000
#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14
#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff
#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0
#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000
#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd
#define CB_COLOR0_INFO__ENDIAN_MASK 0x3
#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR0_INFO__FORMAT_MASK 0x7c
#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR1_INFO__ENDIAN_MASK 0x3
#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR1_INFO__FORMAT_MASK 0x7c
#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR2_INFO__ENDIAN_MASK 0x3
#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR2_INFO__FORMAT_MASK 0x7c
#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR3_INFO__ENDIAN_MASK 0x3
#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR3_INFO__FORMAT_MASK 0x7c
#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR4_INFO__ENDIAN_MASK 0x3
#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR4_INFO__FORMAT_MASK 0x7c
#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR5_INFO__ENDIAN_MASK 0x3
#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR5_INFO__FORMAT_MASK 0x7c
#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR6_INFO__ENDIAN_MASK 0x3
#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR6_INFO__FORMAT_MASK 0x7c
#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR7_INFO__ENDIAN_MASK 0x3
#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0
#define CB_COLOR7_INFO__FORMAT_MASK 0x7c
#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2
#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80
#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7
#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700
#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8
#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800
#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb
#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000
#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd
#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000
#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe
#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000
#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf
#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000
#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10
#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000
#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11
#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000
#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12
#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000
#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000
#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000
#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000
#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000
#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b
#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000
#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000
#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f
#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0
#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00
#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa
#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000
#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000
#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000
#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2
#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc
#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10
#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60
#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180
#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200
#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00
#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000
#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe
#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff
#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0
#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff
#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff
#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0
#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff
#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0
#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf
#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0
#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0
#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4
#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00
#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8
#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000
#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc
#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000
#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10
#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000
#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14
#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000
#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18
#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000
#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c
#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf
#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0
#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0
#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4
#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00
#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8
#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000
#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc
#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000
#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10
#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000
#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14
#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000
#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18
#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000
#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf
#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0
#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000
#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000
#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000
#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12
#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000
#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000
#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000
#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000
#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000
#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000
#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000
#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000
#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000
#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f
#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0
#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800
#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000
#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11
#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000
#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff
#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00
#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000
#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000
#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18
#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000
#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1
#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2
#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4
#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8
#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD_MASK 0x40
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_KEY_MOD__SHIFT 0x6
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80
#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100
#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40
#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00
#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000
#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000
#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000
#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1
#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe
#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0
#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800
#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000
#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000
#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000
#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16
#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00
#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1
#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2
#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4
#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8
#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10
#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20
#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40
#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6
#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80
#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7
#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100
#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8
#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200
#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400
#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa
#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800
#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1
#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2
#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4
#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8
#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10
#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20
#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40
#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80
#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100
#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200
#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400
#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800
#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000
#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000
#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000
#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000
#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000
#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000
#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000
#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000
#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000
#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000
#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3
#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0
#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4
#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2
#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8
#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10
#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20
#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5
#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40
#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6
#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80
#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7
#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100
#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8
#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200
#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9
#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400
#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa
#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800
#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb
#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000
#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc
#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000
#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000
#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000
#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf
#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000
#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10
#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000
#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11
#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000
#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f
#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0
#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000
#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000
#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000
#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000
#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000
#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000
#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000
#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000
#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000
#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000
#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17
#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1
#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0
#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2
#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1
#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4
#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2
#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8
#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3
#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10
#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20
#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40
#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80
#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000
#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc
#define CP_DFY_CNTL__POLICY_MASK 0x1
#define CP_DFY_CNTL__POLICY__SHIFT 0x0
#define CP_DFY_CNTL__MTYPE_MASK 0xc
#define CP_DFY_CNTL__MTYPE__SHIFT 0x2
#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000
#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c
#define CP_DFY_CNTL__MODE_MASK 0x60000000
#define CP_DFY_CNTL__MODE__SHIFT 0x1d
#define CP_DFY_CNTL__ENABLE_MASK 0x80000000
#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f
#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff
#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0
#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000
#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10
#define CP_DFY_STAT__BUSY_MASK 0x80000000
#define CP_DFY_STAT__BUSY__SHIFT 0x1f
#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff
#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0
#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5
#define CP_DFY_DATA_0__DATA_MASK 0xffffffff
#define CP_DFY_DATA_0__DATA__SHIFT 0x0
#define CP_DFY_DATA_1__DATA_MASK 0xffffffff
#define CP_DFY_DATA_1__DATA__SHIFT 0x0
#define CP_DFY_DATA_2__DATA_MASK 0xffffffff
#define CP_DFY_DATA_2__DATA__SHIFT 0x0
#define CP_DFY_DATA_3__DATA_MASK 0xffffffff
#define CP_DFY_DATA_3__DATA__SHIFT 0x0
#define CP_DFY_DATA_4__DATA_MASK 0xffffffff
#define CP_DFY_DATA_4__DATA__SHIFT 0x0
#define CP_DFY_DATA_5__DATA_MASK 0xffffffff
#define CP_DFY_DATA_5__DATA__SHIFT 0x0
#define CP_DFY_DATA_6__DATA_MASK 0xffffffff
#define CP_DFY_DATA_6__DATA__SHIFT 0x0
#define CP_DFY_DATA_7__DATA_MASK 0xffffffff
#define CP_DFY_DATA_7__DATA__SHIFT 0x0
#define CP_DFY_DATA_8__DATA_MASK 0xffffffff
#define CP_DFY_DATA_8__DATA__SHIFT 0x0
#define CP_DFY_DATA_9__DATA_MASK 0xffffffff
#define CP_DFY_DATA_9__DATA__SHIFT 0x0
#define CP_DFY_DATA_10__DATA_MASK 0xffffffff
#define CP_DFY_DATA_10__DATA__SHIFT 0x0
#define CP_DFY_DATA_11__DATA_MASK 0xffffffff
#define CP_DFY_DATA_11__DATA__SHIFT 0x0
#define CP_DFY_DATA_12__DATA_MASK 0xffffffff
#define CP_DFY_DATA_12__DATA__SHIFT 0x0
#define CP_DFY_DATA_13__DATA_MASK 0xffffffff
#define CP_DFY_DATA_13__DATA__SHIFT 0x0
#define CP_DFY_DATA_14__DATA_MASK 0xffffffff
#define CP_DFY_DATA_14__DATA__SHIFT 0x0
#define CP_DFY_DATA_15__DATA_MASK 0xffffffff
#define CP_DFY_DATA_15__DATA__SHIFT 0x0
#define CP_DFY_CMD__OFFSET_MASK 0x1ff
#define CP_DFY_CMD__OFFSET__SHIFT 0x0
#define CP_DFY_CMD__SIZE_MASK 0xffff0000
#define CP_DFY_CMD__SIZE__SHIFT 0x10
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff
#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00
#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8
#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB0_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB1_BASE__RB_BASE__SHIFT 0x0
#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff
#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0
#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff
#define CP_RB2_BASE__RB_BASE__SHIFT 0x0
#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB0_CNTL__MTYPE_MASK 0x18000
#define CP_RB0_CNTL__MTYPE__SHIFT 0xf
#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB_CNTL__MTYPE_MASK 0x18000
#define CP_RB_CNTL__MTYPE__SHIFT 0xf
#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000
#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11
#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB1_CNTL__MTYPE_MASK 0x18000
#define CP_RB1_CNTL__MTYPE__SHIFT 0xf
#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f
#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0
#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00
#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8
#define CP_RB2_CNTL__MTYPE_MASK 0x18000
#define CP_RB2_CNTL__MTYPE__SHIFT 0xf
#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000
#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14
#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000
#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16
#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000
#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b
#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000
#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f
#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff
#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3
#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc
#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff
#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0
#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff
#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc
#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff
#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800
#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000
#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000
#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000
#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000
#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000
#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800
#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000
#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000
#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000
#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000
#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000
#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000
#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000
#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000
#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000
#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000
#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000
#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000
#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000
#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000
#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f
#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff
#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3
#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3
#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0
#define CP_RB_VMID__RB0_VMID_MASK 0xf
#define CP_RB_VMID__RB0_VMID__SHIFT 0x0
#define CP_RB_VMID__RB1_VMID_MASK 0xf00
#define CP_RB_VMID__RB1_VMID__SHIFT 0x8
#define CP_RB_VMID__RB2_VMID_MASK 0xf0000
#define CP_RB_VMID__RB2_VMID__SHIFT 0x10
#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0
#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf
#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc
#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2
#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff
#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff
#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0
#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff
#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0
#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff
#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff
#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1
#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2
#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4
#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8
#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10
#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20
#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40
#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80
#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100
#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200
#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9
#define CP_VIRT_STATUS__VIRT_STATUS_MASK 0xffffffff
#define CP_VIRT_STATUS__VIRT_STATUS__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2
#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800
#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000
#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1
#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2
#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1
#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c
#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80
#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00
#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000
#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10
#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3
#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0
#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4
#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300
#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8
#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00
#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa
#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000
#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc
#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000
#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff
#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff
#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000
#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e
#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000
#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff
#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000
#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000
#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000
#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000
#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000
#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000
#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000
#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000
#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000
#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000
#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000
#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000
#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000
#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000
#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000
#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000
#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000
#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000
#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000
#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000
#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000
#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000
#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000
#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18
#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3
#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0
#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff
#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff
#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff
#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0
#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff
#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff
#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff
#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70
#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000
#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14
#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7
#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff
#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00
#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000
#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10
#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000
#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18
#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff
#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0
#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00
#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8
#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000
#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10
#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000
#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18
#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff
#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0
#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000
#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10
#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff
#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0
#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000
#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10
#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff
#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0
#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000
#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10
#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000
#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c
#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1
#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0
#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2
#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1
#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000
#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc
#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff
#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf
#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0
#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000
#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000
#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18
#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000
#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1
#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10
#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20
#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5
#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1
#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0
#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2
#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1
#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4
#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2
#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8
#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3
#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10
#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4
#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20
#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5
#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40
#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6
#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80
#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7
#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400
#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800
#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb
#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000
#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc
#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000
#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd
#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000
#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d
#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000
#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e
#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000
#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1
#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2
#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4
#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8
#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10
#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20
#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40
#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80
#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100
#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200
#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400
#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800
#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000
#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000
#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000
#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000
#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000
#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000
#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000
#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000
#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000
#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000
#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000
#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000
#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000
#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8
#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10
#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40
#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100
#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000
#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000
#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000
#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000
#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000
#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1
#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0
#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2
#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10
#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4
#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20
#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40
#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80
#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7
#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100
#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200
#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400
#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800
#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb
#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000
#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc
#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000
#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd
#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000
#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe
#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000
#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf
#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000
#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10
#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000
#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11
#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000
#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a
#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000
#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000
#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c
#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000
#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e
#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000
#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2
#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4
#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8
#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10
#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20
#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40
#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80
#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100
#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200
#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800
#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000
#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000
#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000
#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000
#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000
#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000
#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000
#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000
#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000
#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000
#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000
#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000
#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000
#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000
#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000
#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000
#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1
#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2
#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4
#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8
#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40
#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100
#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200
#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10
#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000
#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000
#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000
#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000
#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000
#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000
#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15
#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000
#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c
#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000
#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d
#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000
#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e
#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000
#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff
#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff
#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00
#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf
#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0
#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff
#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0
#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff
#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff
#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff
#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0
#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000
#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4
#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2
#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100
#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff
#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3
#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc
#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00
#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000
#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000
#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000
#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000
#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c
#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000
#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff
#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff
#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff
#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f
#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000
#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000
#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19
#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000
#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff
#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000
#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10
#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000
#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000
#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d
#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff
#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0
#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc
#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2
#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff
#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0
#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff
#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff
#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc
#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff
#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff
#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc
#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff
#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff
#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff
#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff
#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff
#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0
#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000
#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19
#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000
#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b
#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000
#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19
#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000
#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1
#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0
#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff
#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0
#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000
#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10
#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff
#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc
#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff
#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0
#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000
#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10
#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000
#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19
#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000
#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b
#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000
#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d
#define CP_APPEND_DATA__DATA_MASK 0xffffffff
#define CP_APPEND_DATA__DATA__SHIFT 0x0
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff
#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff
#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff
#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0
#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000
#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14
#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000
#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff
#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff
#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc
#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff
#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0
#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000
#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14
#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000
#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff
#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8
#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff
#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000
#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000
#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000
#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000
#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff
#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0
#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f
#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1
#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0
#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2
#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1
#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4
#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2
#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8
#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40
#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80
#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100
#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200
#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400
#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800
#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000
#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000
#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd
#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000
#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000
#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf
#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000
#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12
#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000
#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13
#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000
#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15
#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000
#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16
#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000
#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17
#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000
#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19
#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000
#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000
#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000
#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000
#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000
#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e
#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000
#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f
#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff
#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff
#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0
#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff
#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff
#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0
#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff
#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0
#define CP_COHER_STATUS__MEID_MASK 0x3000000
#define CP_COHER_STATUS__MEID__SHIFT 0x18
#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000
#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e
#define CP_COHER_STATUS__STATUS_MASK 0x80000000
#define CP_COHER_STATUS__STATUS__SHIFT 0x1f
#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff
#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff
#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00
#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa
#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000
#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16
#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff
#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff
#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0
#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00
#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa
#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000
#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000
#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd
#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000
#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14
#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000
#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16
#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000
#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000
#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19
#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000
#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff
#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0
#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000
#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15
#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000
#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16
#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000
#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18
#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000
#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a
#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000
#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b
#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000
#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c
#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000
#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d
#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000
#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e
#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30
#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4
#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000
#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10
#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000
#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c
#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000
#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d
#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000
#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e
#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff
#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000
#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c
#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff
#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1
#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2
#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000
#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000
#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18
#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff
#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0
#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff
#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0
#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff
#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff
#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff
#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff
#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0
#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff
#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0
#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff
#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0
#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff
#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0
#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff
#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0
#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3
#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3
#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1
#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff
#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1
#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2
#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4
#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8
#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10
#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20
#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40
#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80
#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10
#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000
#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000
#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000
#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000
#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000
#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000
#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000
#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4
#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10
#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20
#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100
#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200
#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400
#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800
#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000
#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000
#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000
#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000
#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000
#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000
#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000
#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000
#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000
#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000
#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000
#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000
#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000
#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000
#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000
#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000
#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1
#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4
#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8
#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10
#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20
#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40
#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80
#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400
#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800
#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000
#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000
#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000
#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000
#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000
#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13
#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000
#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1
#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40
#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6
#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80
#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7
#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100
#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8
#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200
#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9
#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400
#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000
#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000
#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000
#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000
#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf
#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000
#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11
#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000
#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12
#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000
#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13
#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000
#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14
#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000
#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15
#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000
#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16
#define CP_STAT__ROQ_RING_BUSY_MASK 0x200
#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9
#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400
#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa
#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800
#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb
#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000
#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc
#define CP_STAT__DC_BUSY_MASK 0x2000
#define CP_STAT__DC_BUSY__SHIFT 0xd
#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000
#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe
#define CP_STAT__PFP_BUSY_MASK 0x8000
#define CP_STAT__PFP_BUSY__SHIFT 0xf
#define CP_STAT__MEQ_BUSY_MASK 0x10000
#define CP_STAT__MEQ_BUSY__SHIFT 0x10
#define CP_STAT__ME_BUSY_MASK 0x20000
#define CP_STAT__ME_BUSY__SHIFT 0x11
#define CP_STAT__QUERY_BUSY_MASK 0x40000
#define CP_STAT__QUERY_BUSY__SHIFT 0x12
#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000
#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13
#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000
#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14
#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000
#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15
#define CP_STAT__DMA_BUSY_MASK 0x400000
#define CP_STAT__DMA_BUSY__SHIFT 0x16
#define CP_STAT__RCIU_BUSY_MASK 0x800000
#define CP_STAT__RCIU_BUSY__SHIFT 0x17
#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000
#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18
#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000
#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19
#define CP_STAT__CE_BUSY_MASK 0x4000000
#define CP_STAT__CE_BUSY__SHIFT 0x1a
#define CP_STAT__TCIU_BUSY_MASK 0x8000000
#define CP_STAT__TCIU_BUSY__SHIFT 0x1b
#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000
#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000
#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000
#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e
#define CP_STAT__CP_BUSY_MASK 0x80000000
#define CP_STAT__CP_BUSY__SHIFT 0x1f
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff
#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff
#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f
#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00
#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000
#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff
#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf
#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00
#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf
#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10
#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40
#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100
#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8
#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000
#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10
#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000
#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12
#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000
#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14
#define CP_ME_CNTL__CE_HALT_MASK 0x1000000
#define CP_ME_CNTL__CE_HALT__SHIFT 0x18
#define CP_ME_CNTL__CE_STEP_MASK 0x2000000
#define CP_ME_CNTL__CE_STEP__SHIFT 0x19
#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000
#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a
#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000
#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b
#define CP_ME_CNTL__ME_HALT_MASK 0x10000000
#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c
#define CP_ME_CNTL__ME_STEP_MASK 0x20000000
#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff
#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700
#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000
#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000
#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c
#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1
#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0
#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff
#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff
#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000
#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff
#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000
#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0
#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff
#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff
#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc
#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2
#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff
#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0
#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff
#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0
#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc
#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2
#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff
#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0
#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff
#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0
#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc
#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2
#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff
#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0
#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff
#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff
#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0
#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00
#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8
#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff
#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff
#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0
#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00
#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8
#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000
#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10
#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000
#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18
#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff
#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0
#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00
#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8
#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000
#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10
#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000
#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18
#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff
#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0
#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00
#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8
#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000
#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f
#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00
#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8
#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff
#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0
#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00
#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8
#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff
#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0
#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000
#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10
#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff
#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff
#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0
#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff
#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0
#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff
#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0
#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000
#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc
#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000
#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10
#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff
#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff
#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000
#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff
#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000
#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff
#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000
#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff
#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0
#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff
#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff
#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0
#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000
#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10
#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff
#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000
#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff
#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff
#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000
#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff
#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000
#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff
#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000
#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800
#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000
#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000
#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000
#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000
#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000
#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000
#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000
#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000
#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000
#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000
#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000
#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000
#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000
#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000
#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000
#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f
#define CP_RINGID__RINGID_MASK 0x3
#define CP_RINGID__RINGID__SHIFT 0x0
#define CP_PIPEID__PIPE_ID_MASK 0x3
#define CP_PIPEID__PIPE_ID__SHIFT 0x0
#define CP_VMID__VMID_MASK 0xf
#define CP_VMID__VMID__SHIFT 0x0
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7
#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00
#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000
#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10
#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f
#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0
#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0
#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5
#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00
#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8
#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc
#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff
#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1
#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0
#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2
#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1
#define CP_HQD_VMID__VMID_MASK 0xf
#define CP_HQD_VMID__VMID__SHIFT 0x0
#define CP_HQD_VMID__IB_VMID_MASK 0xf00
#define CP_HQD_VMID__IB_VMID__SHIFT 0x8
#define CP_HQD_VMID__VQID_MASK 0x3ff0000
#define CP_HQD_VMID__VQID__SHIFT 0x10
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1
#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00
#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000
#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000
#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000
#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000
#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3
#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf
#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0
#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1
#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0
#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10
#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4
#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00
#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000
#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f
#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff
#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0
#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff
#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff
#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc
#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff
#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc
#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff
#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000
#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f
#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff
#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f
#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00
#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8
#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000
#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000
#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000
#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000
#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17
#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000
#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000
#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000
#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000
#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d
#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000
#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e
#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000
#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc
#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff
#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff
#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0
#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff
#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000
#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14
#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000
#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000
#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000
#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b
#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000
#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f
#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff
#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0
#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700
#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800
#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000
#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc
#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000
#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000
#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000
#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16
#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000
#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17
#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000
#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000
#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d
#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000
#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e
#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000
#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f
#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f
#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200
#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400
#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1
#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1
#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2
#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10
#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20
#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5
#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1
#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0
#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6
#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1
#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7
#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0
#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70
#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff
#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff
#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff
#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff
#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff
#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3
#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc
#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2
#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70
#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80
#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100
#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200
#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9
#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00
#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff
#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0
#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff
#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0
#define CP_MQD_CONTROL__VMID_MASK 0xf
#define CP_MQD_CONTROL__VMID__SHIFT 0x0
#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000
#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc
#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000
#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd
#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000
#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17
#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000
#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b
#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff
#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0
#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff
#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff
#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff
#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0
#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f
#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100
#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000
#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000
#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000
#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe
#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000
#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf
#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000
#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17
#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000
#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000
#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000
#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f
#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff
#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000
#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e
#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000
#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f
#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff
#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0
#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000
#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10
#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff
#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000
#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000
#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff
#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0
#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1
#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0
#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6
#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1
#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8
#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc
#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000
#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc
#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2
#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000
#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1
#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2
#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0
#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000
#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc
#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf
#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0
#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10
#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4
#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff
#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0
#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff
#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0
#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff
#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff
#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0
#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff
#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff
#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0
#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf
#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0
#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0
#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4
#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00
#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8
#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000
#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd
#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000
#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf
#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000
#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11
#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000
#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13
#define DB_Z_INFO__FORMAT_MASK 0x3
#define DB_Z_INFO__FORMAT__SHIFT 0x0
#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc
#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2
#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000
#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd
#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000
#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000
#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17
#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_Z_INFO__READ_SIZE_MASK 0x10000000
#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c
#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000
#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d
#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000
#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000
#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f
#define DB_STENCIL_INFO__FORMAT_MASK 0x1
#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0
#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000
#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd
#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000
#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000
#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000
#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d
#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000
#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e
#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff
#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0
#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800
#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb
#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff
#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0
#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff
#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0
#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000
#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd
#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000
#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000
#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1
#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2
#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1
#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4
#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2
#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8
#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10
#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20
#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40
#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6
#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80
#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7
#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00
#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000
#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1
#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2
#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1
#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70
#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4
#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00
#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8
#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000
#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc
#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000
#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10
#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000
#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000
#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000
#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3
#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30
#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40
#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80
#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100
#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200
#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400
#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa
#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800
#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000
#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000
#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000
#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000
#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000
#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000
#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000
#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000
#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000
#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000
#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000
#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000
#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c
#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20
#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40
#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80
#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100
#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200
#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400
#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800
#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000
#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000
#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000
#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000
#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000
#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17
#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7
#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0
#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70
#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700
#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000
#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000
#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10
#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000
#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11
#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000
#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12
#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000
#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000
#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000
#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15
#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000
#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000
#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1
#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2
#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4
#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2
#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30
#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4
#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40
#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80
#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100
#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200
#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9
#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400
#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800
#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000
#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000
#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd
#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff
#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0
#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff
#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0
#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff
#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0
#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff
#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0
#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff
#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0
#define DB_HTILE_SURFACE__LINEAR_MASK 0x1
#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0
#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2
#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4
#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2
#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8
#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3
#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0
#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00
#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000
#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10
#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000
#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11
#define DB_PRELOAD_CONTROL__START_X_MASK 0xff
#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0
#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00
#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8
#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000
#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10
#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000
#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18
#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff
#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0
#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00
#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8
#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000
#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10
#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000
#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff
#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0
#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00
#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000
#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000
#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7
#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0
#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000
#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000
#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7
#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0
#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000
#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000
#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18
#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1
#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0
#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2
#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4
#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8
#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3
#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70
#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80
#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7
#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700
#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8
#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000
#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000
#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000
#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f
#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf
#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0
#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0
#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4
#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00
#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8
#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000
#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc
#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000
#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000
#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000
#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe
#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000
#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10
#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000
#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18
#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1
#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2
#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1
#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4
#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8
#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3
#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30
#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40
#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80
#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300
#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000
#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000
#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000
#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000
#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10
#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000
#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000
#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000
#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13
#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000
#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000
#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000
#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000
#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18
#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000
#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000
#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000
#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000
#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1
#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2
#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4
#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8
#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10
#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5
#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40
#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80
#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7
#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100
#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8
#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00
#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000
#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000
#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000
#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000
#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000
#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000
#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000
#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000
#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000
#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000
#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f
#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4
#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8
#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10
#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20
#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40
#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80
#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100
#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200
#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400
#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800
#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000
#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000
#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000
#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000
#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000
#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000
#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000
#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000
#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000
#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000
#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000
#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000
#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000
#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18
#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000
#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000
#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000
#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000
#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000
#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000
#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000
#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1
#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2
#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4
#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8
#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3
#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xfffffff0
#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x4
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f
#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0
#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00
#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000
#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18
#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f
#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0
#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0
#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5
#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800
#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb
#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000
#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000
#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14
#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000
#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b
#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000
#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c
#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000
#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d
#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000
#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e
#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000
#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f
#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3
#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0
#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc
#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2
#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30
#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4
#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0
#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6
#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300
#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8
#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00
#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa
#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000
#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc
#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000
#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe
#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000
#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10
#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000
#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f
#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80
#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7
#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000
#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000
#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15
#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000
#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f
#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0
#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5
#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00
#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa
#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000
#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000
#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff
#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00
#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000
#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000
#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19
#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf
#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0
#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4
#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000
#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000
#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f
#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0
#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff
#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0
#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3
#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0
#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff
#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0
#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff
#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0
#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff
#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0
#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0
#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff
#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff
#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff
#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0
#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00
#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc
#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000
#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000
#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000
#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10
#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff
#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0
#define GB_GPU_ID__GPU_ID_MASK 0xf
#define GB_GPU_ID__GPU_ID__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf
#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0
#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0
#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4
#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00
#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8
#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000
#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc
#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000
#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10
#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000
#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14
#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000
#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18
#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000
#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c
#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19
#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c
#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2
#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0
#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6
#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800
#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000
#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16
#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000
#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19
#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6
#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3
#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0
#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc
#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30
#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4
#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0
#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6
#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000
#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10
#define GB_EDC_MODE__DED_MODE_MASK 0x300000
#define GB_EDC_MODE__DED_MODE__SHIFT 0x14
#define GB_EDC_MODE__PROP_FED_MASK 0x20000000
#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d
#define GB_EDC_MODE__BYPASS_MASK 0x80000000
#define GB_EDC_MODE__BYPASS__SHIFT 0x1f
#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2
#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1
#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1
#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff
#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0
#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff
#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SQ_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SQ_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0
#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff
#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff
#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0
#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff
#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0
#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7
#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7
#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0
#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff
#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff
#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0
#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000
#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10
#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff
#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0
#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000
#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f
#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0
#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6
#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3
#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0
#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc
#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2
#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30
#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4
#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0
#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6
#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000
#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe
#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000
#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf
#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20
#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80
#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100
#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200
#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS__DB_CLEAN_MASK 0x1000
#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc
#define GRBM_STATUS__CB_CLEAN_MASK 0x2000
#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd
#define GRBM_STATUS__TA_BUSY_MASK 0x4000
#define GRBM_STATUS__TA_BUSY__SHIFT 0xe
#define GRBM_STATUS__GDS_BUSY_MASK 0x8000
#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf
#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000
#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10
#define GRBM_STATUS__VGT_BUSY_MASK 0x20000
#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11
#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000
#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12
#define GRBM_STATUS__IA_BUSY_MASK 0x80000
#define GRBM_STATUS__IA_BUSY__SHIFT 0x13
#define GRBM_STATUS__SX_BUSY_MASK 0x100000
#define GRBM_STATUS__SX_BUSY__SHIFT 0x14
#define GRBM_STATUS__WD_BUSY_MASK 0x200000
#define GRBM_STATUS__WD_BUSY__SHIFT 0x15
#define GRBM_STATUS__SPI_BUSY_MASK 0x400000
#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16
#define GRBM_STATUS__BCI_BUSY_MASK 0x800000
#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17
#define GRBM_STATUS__SC_BUSY_MASK 0x1000000
#define GRBM_STATUS__SC_BUSY__SHIFT 0x18
#define GRBM_STATUS__PA_BUSY_MASK 0x2000000
#define GRBM_STATUS__PA_BUSY__SHIFT 0x19
#define GRBM_STATUS__DB_BUSY_MASK 0x4000000
#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a
#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000
#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c
#define GRBM_STATUS__CP_BUSY_MASK 0x20000000
#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d
#define GRBM_STATUS__CB_BUSY_MASK 0x40000000
#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e
#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf
#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10
#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20
#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40
#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80
#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100
#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200
#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400
#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800
#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000
#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000
#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd
#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000
#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe
#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000
#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18
#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000
#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19
#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000
#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a
#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000
#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c
#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000
#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d
#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000
#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f
#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2
#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1
#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4
#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2
#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000
#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16
#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000
#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17
#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000
#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18
#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000
#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19
#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000
#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a
#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000
#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b
#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000
#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d
#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000
#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e
#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000
#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f
#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1
#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0
#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4
#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2
#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000
#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10
#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000
#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11
#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000
#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12
#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000
#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13
#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000
#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14
#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f
#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0
#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff
#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0
#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff
#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0
#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00
#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8
#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000
#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000
#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000
#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000
#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf
#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00
#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff
#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0
#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2
#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1
#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20
#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5
#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40
#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6
#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80
#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7
#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00
#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8
#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000
#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc
#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000
#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd
#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000
#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f
#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1
#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0
#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2
#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1
#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4
#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10
#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4
#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20
#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000
#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000
#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000
#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000
#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15
#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc
#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2
#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000
#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14
#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000
#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16
#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000
#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f
#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000
#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000
#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000
#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000
#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f
#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1
#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000
#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13
#define GRBM_TRAP_OP__RW_MASK 0x1
#define GRBM_TRAP_OP__RW__SHIFT 0x0
#define GRBM_TRAP_ADDR__DATA_MASK 0xffff
#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0
#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff
#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0
#define GRBM_TRAP_WD__DATA_MASK 0xffffffff
#define GRBM_TRAP_WD__DATA__SHIFT 0x0
#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff
#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3
#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0
#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4
#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2
#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1
#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c
#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2
#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0
#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5
#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000
#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc
#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000
#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd
#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000
#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14
#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000
#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16
#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000
#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000
#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000
#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000
#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000
#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000
#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000
#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000
#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000
#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f
#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000
#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000
#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000
#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000
#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000
#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000
#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000
#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000
#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000
#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff
#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0
#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff
#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0
#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff
#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0
#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff
#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0
#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff
#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0
#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff
#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0
#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff
#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0
#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff
#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0
#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff
#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0
#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff
#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0
#define GRBM_NOWHERE__DATA_MASK 0xffffffff
#define GRBM_NOWHERE__DATA__SHIFT 0x0
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff
#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff
#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff
#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff
#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1
#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2
#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4
#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8
#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10
#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20
#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5
#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100
#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8
#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200
#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9
#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400
#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800
#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80
#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000
#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000
#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000
#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000
#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000
#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000
#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000
#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000
#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000
#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000
#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1
#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2
#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4
#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8
#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10
#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20
#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40
#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80
#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100
#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200
#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400
#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800
#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000
#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000
#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000
#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000
#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14
#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0
#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1
#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2
#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8
#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3
#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10
#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4
#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20
#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000
#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd
#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000
#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe
#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000
#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000
#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000
#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000
#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000
#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14
#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000
#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000
#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000
#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000
#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000
#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000
#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0
#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff
#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1
#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0
#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6
#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8
#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10
#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20
#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5
#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000
#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c
#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000
#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d
#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000
#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000
#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1
#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0
#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1
#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0
#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6
#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1
#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38
#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3
#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff
#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0
#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000
#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10
#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff
#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0
#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000
#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10
#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff
#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3
#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4
#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8
#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10
#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff
#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2
#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4
#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10
#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20
#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40
#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80
#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00
#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000
#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000
#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f
#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1
#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0
#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2
#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1
#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4
#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2
#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18
#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0
#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700
#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000
#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000
#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000
#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000
#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000
#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100
#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff
#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000
#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff
#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff
#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7
#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10
#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000
#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000
#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000
#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000
#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000
#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000
#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000
#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000
#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c
#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff
#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff
#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0
#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff
#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0
#define PA_SC_EDGERULE__ER_TRI_MASK 0xf
#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0
#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0
#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4
#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00
#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8
#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000
#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc
#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000
#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12
#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000
#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18
#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000
#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200
#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9
#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400
#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800
#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000
#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc
#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff
#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000
#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000
#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000
#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1
#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2
#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4
#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8
#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3
#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1
#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2
#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4
#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8
#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70
#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80
#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100
#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200
#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400
#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800
#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000
#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000
#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000
#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000
#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000
#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000
#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000
#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000
#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000
#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000
#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000
#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc
#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2
#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30
#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4
#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40
#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6
#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80
#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7
#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300
#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8
#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00
#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa
#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000
#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc
#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000
#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe
#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000
#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10
#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000
#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12
#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000
#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14
#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000
#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18
#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000
#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a
#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000
#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30
#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc
#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2
#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff
#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff
#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff
#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000
#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff
#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000
#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff
#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000
#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff
#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff
#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000
#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff
#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000
#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff
#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff
#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1
#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2
#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4
#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10
#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20
#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5
#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0
#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100
#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200
#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000
#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000
#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000
#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000
#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000
#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000
#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000
#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000
#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000
#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000
#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000
#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d
#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000
#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e
#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000
#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f
#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0
#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000
#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000
#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f
#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0
#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000
#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000
#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000
#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00
#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8
#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10
#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff
#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0
#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000
#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff
#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1
#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2
#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1
#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff
#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff
#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff
#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff
#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1
#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0
#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000
#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f
#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000
#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff
#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0
#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000
#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000
#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000
#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f
#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f
#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0
#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff
#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0
#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f
#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0
#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff
#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100
#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600
#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000
#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000
#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000
#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000
#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000
#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000
#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000
#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000
#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700
#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800
#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000
#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000
#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000
#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000
#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7
#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38
#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000
#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000
#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000
#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000
#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000
#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000
#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000
#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000
#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000
#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000
#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000
#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000
#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000
#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff
#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00
#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000
#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000
#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000
#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000
#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000
#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7
#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0
#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8
#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3
#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10
#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20
#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40
#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6
#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80
#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00
#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000
#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000
#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000
#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000
#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000
#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000
#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000
#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000
#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000
#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000
#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000
#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000
#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18
#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000
#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e
#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff
#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f
#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0
#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80
#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00
#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000
#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000
#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13
#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000
#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000
#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000
#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000
#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000
#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000
#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f
#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f
#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0
#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0
#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000
#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f
#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f
#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0
#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380
#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7
#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00
#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa
#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000
#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf
#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000
#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10
#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000
#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000
#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000
#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f
#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0
#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180
#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7
#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00
#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9
#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000
#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf
#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000
#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000
#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff
#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0
#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00
#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000
#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd
#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000
#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe
#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000
#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15
#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000
#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17
#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000
#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000
#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000
#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000
#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f
#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3
#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0
#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c
#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2
#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00
#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8
#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000
#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe
#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000
#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf
#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000
#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10
#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000
#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12
#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000
#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13
#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000
#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14
#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000
#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15
#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000
#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16
#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000
#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c
#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000
#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d
#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000
#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e
#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000
#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f
#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff
#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0
#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000
#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10
#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff
#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0
#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000
#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe
#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000
#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf
#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000
#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10
#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000
#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13
#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000
#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14
#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000
#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17
#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000
#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18
#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000
#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a
#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000
#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d
#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000
#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f
#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff
#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0
#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000
#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe
#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000
#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c
#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000
#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e
#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000
#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f
#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3
#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0
#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc
#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2
#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3
#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0
#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc
#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1
#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2
#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4
#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10
#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20
#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40
#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380
#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400
#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800
#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000
#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc
#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000
#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe
#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_X__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0
#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff
#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0
#define COMPUTE_START_X__START_MASK 0xffffffff
#define COMPUTE_START_X__START__SHIFT 0x0
#define COMPUTE_START_Y__START_MASK 0xffffffff
#define COMPUTE_START_Y__START__SHIFT 0x0
#define COMPUTE_START_Z__START_MASK 0xffffffff
#define COMPUTE_START_Z__START__SHIFT 0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000
#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1
#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1
#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0
#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff
#define COMPUTE_PGM_LO__DATA__SHIFT 0x0
#define COMPUTE_PGM_HI__DATA_MASK 0xff
#define COMPUTE_PGM_HI__DATA__SHIFT 0x0
#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100
#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8
#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff
#define COMPUTE_TBA_LO__DATA__SHIFT 0x0
#define COMPUTE_TBA_HI__DATA_MASK 0xff
#define COMPUTE_TBA_HI__DATA__SHIFT 0x0
#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff
#define COMPUTE_TMA_LO__DATA__SHIFT 0x0
#define COMPUTE_TMA_HI__DATA_MASK 0xff
#define COMPUTE_TMA_HI__DATA__SHIFT 0x0
#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f
#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0
#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0
#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6
#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00
#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa
#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000
#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc
#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000
#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14
#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000
#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15
#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000
#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16
#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000
#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17
#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000
#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18
#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000
#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19
#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1
#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0
#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e
#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40
#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6
#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80
#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7
#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100
#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8
#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200
#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400
#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800
#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000
#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd
#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000
#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf
#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000
#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18
#define COMPUTE_VMID__DATA_MASK 0xf
#define COMPUTE_VMID__DATA__SHIFT 0x0
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff
#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000
#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000
#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000
#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000
#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000
#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff
#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0
#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000
#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10
#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0
#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff
#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1
#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0
#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3
#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0
#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4
#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2
#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8
#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3
#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10
#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0
#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5
#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff
#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff
#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0
#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff
#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0
#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000
#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e
#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000
#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff
#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff
#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1
#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0
#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6
#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1
#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0
#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff
#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0
#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff
#define COMPUTE_NOWHERE__DATA__SHIFT 0x0
#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff
#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0
#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000
#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15
#define CSPRIV_CONNECT__VMID_MASK 0x3c000000
#define CSPRIV_CONNECT__VMID__SHIFT 0x1a
#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000
#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f
#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff
#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff
#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0
#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000
#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000
#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a
#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000
#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b
#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000
#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c
#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f
#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0
#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1
#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0
#define RLC_CNTL__FORCE_RETRY_MASK 0x2
#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1
#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4
#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2
#define RLC_CNTL__RLC_STEP_F32_MASK 0x8
#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3
#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10
#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4
#define RLC_CNTL__RESERVED_MASK 0xffffff00
#define RLC_CNTL__RESERVED__SHIFT 0x8
#define RLC_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00
#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_DEBUG__DATA_MASK 0xffffffff
#define RLC_DEBUG__DATA__SHIFT 0x0
#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3
#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0
#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4
#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2
#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8
#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3
#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10
#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4
#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0
#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5
#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00
#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9
#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000
#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd
#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000
#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14
#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000
#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18
#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000
#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a
#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000
#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b
#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000
#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c
#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000
#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d
#define RLC_STAT__RLC_BUSY_MASK 0x1
#define RLC_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2
#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1
#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4
#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2
#define RLC_STAT__RESERVED_MASK 0xfffffff8
#define RLC_STAT__RESERVED__SHIFT 0x3
#define RLC_SAFE_MODE__CMD_MASK 0x1
#define RLC_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU_MASK 0x1
#define RLC_SOFT_RESET_GPU__SOFT_RESET_GPU__SHIFT 0x0
#define RLC_SOFT_RESET_GPU__RESERVED_MASK 0xfffffffe
#define RLC_SOFT_RESET_GPU__RESERVED__SHIFT 0x1
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2
#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1
#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c
#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80
#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000
#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10
#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000
#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff
#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0
#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1
#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1
#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0
#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e
#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1
#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0
#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5
#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00
#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8
#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000
#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc
#define RLC_RLCV_COMMAND__CMD_MASK 0xf
#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0
#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0
#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1
#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0
#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7
#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400
#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff
#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff
#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000
#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1
#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0
#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2
#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4
#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2
#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8
#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0
#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4
#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000
#define RLC_LB_CNTL__RESERVED__SHIFT 0xc
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff
#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff
#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff
#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0
#define RLC_SAVE_AND_RESTORE_BASE__BASE_MASK 0xffffffff
#define RLC_SAVE_AND_RESTORE_BASE__BASE__SHIFT 0x0
#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff
#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST_MASK 0x1
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_REQUEST__SHIFT 0x0
#define RLC_DRIVER_CPDMA_STATUS__RESERVED1_MASK 0xe
#define RLC_DRIVER_CPDMA_STATUS__RESERVED1__SHIFT 0x1
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK_MASK 0x10
#define RLC_DRIVER_CPDMA_STATUS__DRIVER_ACK__SHIFT 0x4
#define RLC_DRIVER_CPDMA_STATUS__RESERVED_MASK 0xffffffe0
#define RLC_DRIVER_CPDMA_STATUS__RESERVED__SHIFT 0x5
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff
#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00
#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000
#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10
#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300
#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8
#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00
#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa
#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff
#define RLC_GPM_DEBUG__DATA__SHIFT 0x0
#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_HYP_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_HYP_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_HYP_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_HYP_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1
#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0
#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2
#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1
#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c
#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2
#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80
#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7
#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000
#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18
#define RLC_ROM_CNTL__USE_ROM_MASK 0x1
#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0
#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2
#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1
#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4
#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2
#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8
#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3
#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10
#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4
#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0
#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff
#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff
#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1
#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe
#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff
#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0
#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1
#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0
#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2
#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1
#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4
#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2
#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8
#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10
#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20
#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40
#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80
#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100
#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8
#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200
#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9
#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400
#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800
#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000
#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000
#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000
#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe
#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000
#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000
#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000
#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11
#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000
#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f
#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0
#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff
#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1
#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2
#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4
#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8
#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10
#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4
#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0
#define RLC_PG_CNTL__RESERVED__SHIFT 0x5
#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000
#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe
#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000
#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000
#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000
#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000
#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13
#define RLC_PG_CNTL__QUICK_PG_ENABLE_MASK 0x100000
#define RLC_PG_CNTL__QUICK_PG_ENABLE__SHIFT 0x14
#define RLC_PG_CNTL__RESERVED1_MASK 0xe00000
#define RLC_PG_CNTL__RESERVED1__SHIFT 0x15
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff
#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00
#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000
#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000
#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1
#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2
#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4
#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8
#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3
#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0
#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4
#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb
#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb
#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff
#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1
#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0
#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2
#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc
#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00
#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000
#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000
#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000
#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000
#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0
#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00
#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000
#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000
#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff
#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0
#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff
#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0
#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00
#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000
#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10
#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000
#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18
#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff
#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff
#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff
#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0
#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1
#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0
#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe
#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00
#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000
#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff
#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00
#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000
#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10
#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000
#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff
#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff
#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0
#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00
#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1
#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2
#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4
#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8
#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000
#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1
#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1
#define RLC_SMU_PG_CTRL__START_PG_MASK 0x1
#define RLC_SMU_PG_CTRL__START_PG__SHIFT 0x0
#define RLC_SMU_PG_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_PG_CTRL__SPARE__SHIFT 0x1
#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP_MASK 0x1
#define RLC_SMU_PG_WAKE_UP_CTRL__START_PG_WAKE_UP__SHIFT 0x0
#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE_MASK 0xfffffffe
#define RLC_SMU_PG_WAKE_UP_CTRL__SPARE__SHIFT 0x1
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf
#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30
#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0
#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400
#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800
#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000
#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf
#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000
#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11
#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0
#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff
#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff
#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000
#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18
#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff
#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0
#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100
#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8
#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200
#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9
#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400
#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa
#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800
#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000
#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc
#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000
#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd
#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000
#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000
#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf
#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000
#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000
#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000
#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b
#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000
#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c
#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff
#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff
#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff
#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000
#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000
#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000
#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000
#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000
#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18
#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0
#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff
#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0
#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT_MASK 0xffffffff
#define RLC_GPM_CU_PD_TIMEOUT__TIMEOUT__SHIFT 0x0
#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff
#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff
#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff
#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf
#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0
#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00
#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000
#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000
#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000
#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000
#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000
#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf
#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0
#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4
#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00
#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8
#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000
#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000
#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10
#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000
#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12
#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000
#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14
#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000
#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15
#define RLC_GPR_REG1__DATA_MASK 0xffffffff
#define RLC_GPR_REG1__DATA__SHIFT 0x0
#define RLC_GPR_REG2__DATA_MASK 0xffffffff
#define RLC_GPR_REG2__DATA__SHIFT 0x0
#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1
#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0
#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2
#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1
#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4
#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2
#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78
#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3
#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80
#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7
#define RLC_MGCG_CTRL__SPARE_MASK 0xffff8000
#define RLC_MGCG_CTRL__SPARE__SHIFT 0xf
#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1
#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0
#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2
#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1
#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4
#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2
#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8
#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3
#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0
#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4
#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf
#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0
#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0
#define RLC_SPM_VMID__RESERVED__SHIFT 0x4
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1
#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0
#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe
#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1
#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0
#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe
#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1
#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00
#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000
#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10
#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff
#define RLC_SPM_DEBUG__DATA__SHIFT 0x0
#define RLC_GPM_LOG_ADDR__ADDR_MASK 0xffffffff
#define RLC_GPM_LOG_ADDR__ADDR__SHIFT 0x0
#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff
#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0
#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff
#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0
#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff
#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff
#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff
#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff
#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff
#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0
#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff
#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0
#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1
#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0
#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2
#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1
#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc
#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2
#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff
#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0
#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00
#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8
#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff
#define RLC_SRM_DEBUG__DATA__SHIFT 0x0
#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff
#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00
#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa
#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff
#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1
#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c
#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2
#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0
#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5
#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000
#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11
#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000
#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000
#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2
#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1
#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe
#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0
#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4
#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000
#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10
#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000
#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000
#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2
#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc
#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff
#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000
#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff
#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0
#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1
#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0
#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe
#define RLC_SRM_STAT__RESERVED__SHIFT 0x1
#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1
#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0
#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe
#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1
#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff
#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0
#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff
#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0
#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff
#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0
#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0
#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff
#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0
#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff
#define RLC_SMU_COMMAND__CMD__SHIFT 0x0
#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff
#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0
#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00
#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8
#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000
#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10
#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000
#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18
#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff
#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000
#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc
#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000
#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000
#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff
#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff
#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000
#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff
#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff
#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800
#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000
#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff
#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff
#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff
#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff
#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_DBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CBR0_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00
#define RLC_SPM_CBR1_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe
#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000
#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE_MASK 0xf
#define RLC_GPU_IOV_CFG_REG1__CMD_TYPE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_MASK 0x10
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN_MASK 0x20
#define RLC_GPU_IOV_CFG_REG1__CMD_EXECUTE_INTR_EN__SHIFT 0x5
#define RLC_GPU_IOV_CFG_REG1__RESERVED_MASK 0xc0
#define RLC_GPU_IOV_CFG_REG1__RESERVED__SHIFT 0x6
#define RLC_GPU_IOV_CFG_REG1__FCN_ID_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG1__FCN_ID__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG1__NEXT_FCN_ID__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG1__RESERVED1_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG1__RESERVED1__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS_MASK 0xf
#define RLC_GPU_IOV_CFG_REG2__CMD_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG2__RESERVED_MASK 0xfffffff0
#define RLC_GPU_IOV_CFG_REG2__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE_MASK 0x7f
#define RLC_GPU_IOV_CFG_REG6__CNTXT_SIZE__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION_MASK 0x80
#define RLC_GPU_IOV_CFG_REG6__CNTXT_LOCATION__SHIFT 0x7
#define RLC_GPU_IOV_CFG_REG6__RESERVED_MASK 0x300
#define RLC_GPU_IOV_CFG_REG6__RESERVED__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET_MASK 0xfffffc00
#define RLC_GPU_IOV_CFG_REG6__CNTXT_OFFSET__SHIFT 0xa
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_CFG_REG8__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_MASK 0xff
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS_MASK 0xf00
#define RLC_GPU_IOV_CFG_REG9__ACTIVE_FCN_ID_STATUS__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG9__RESERVED_MASK 0xfffff000
#define RLC_GPU_IOV_CFG_REG9__RESERVED__SHIFT 0xc
#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF_MASK 0xffff
#define RLC_GPU_IOV_CFG_REG10__TIME_QUANTA_PF__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG10__RESERVED_MASK 0xffff0000
#define RLC_GPU_IOV_CFG_REG10__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG11__YIELD_MASK 0xffffffff
#define RLC_GPU_IOV_CFG_REG11__YIELD__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0_MASK 0xff
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF0__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF1__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF2__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG12__TIME_QUANTA_VF3__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4_MASK 0xff
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF4__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF5__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF6__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG13__TIME_QUANTA_VF7__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8_MASK 0xff
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF8__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF9__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF10__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG14__TIME_QUANTA_VF11__SHIFT 0x18
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12_MASK 0xff
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF12__SHIFT 0x0
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13_MASK 0xff00
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF13__SHIFT 0x8
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14_MASK 0xff0000
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF14__SHIFT 0x10
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15_MASK 0xff000000
#define RLC_GPU_IOV_CFG_REG15__TIME_QUANTA_VF15__SHIFT 0x18
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf
#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0
#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000
#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f
#define RLC_GPM_VMID_THREAD2__RLC_VMID_MASK 0xf
#define RLC_GPM_VMID_THREAD2__RLC_VMID__SHIFT 0x0
#define RLC_GPM_VMID_THREAD2__RESERVED0_MASK 0xf0
#define RLC_GPM_VMID_THREAD2__RESERVED0__SHIFT 0x4
#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID_MASK 0x700
#define RLC_GPM_VMID_THREAD2__RLC_QUEUEID__SHIFT 0x8
#define RLC_GPM_VMID_THREAD2__RESERVED1_MASK 0xfffff800
#define RLC_GPM_VMID_THREAD2__RESERVED1__SHIFT 0xb
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR_MASK 0xfff
#define RLC_GPU_IOV_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED_MASK 0xfffff000
#define RLC_GPU_IOV_UCODE_ADDR__RESERVED__SHIFT 0xc
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA_MASK 0xffffffff
#define RLC_GPU_IOV_UCODE_DATA__UCODE_DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR_MASK 0x1ff
#define RLC_GPU_IOV_SCRATCH_ADDR__ADDR__SHIFT 0x0
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00
#define RLC_GPU_IOV_SCRATCH_ADDR__RESERVED__SHIFT 0x9
#define RLC_GPU_IOV_SCRATCH_DATA__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCRATCH_DATA__DATA__SHIFT 0x0
#define RLC_GPU_IOV_F32_CNTL__ENABLE_MASK 0x1
#define RLC_GPU_IOV_F32_CNTL__ENABLE__SHIFT 0x0
#define RLC_GPU_IOV_F32_CNTL__RESERVED_MASK 0xfffffffe
#define RLC_GPU_IOV_F32_CNTL__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_F32_RESET__RESET_MASK 0x1
#define RLC_GPU_IOV_F32_RESET__RESET__SHIFT 0x0
#define RLC_GPU_IOV_F32_RESET__RESERVED_MASK 0xfffffffe
#define RLC_GPU_IOV_F32_RESET__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED_MASK 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED_MASK 0xfe
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED_MASK 0x100
#define RLC_GPU_IOV_SDMA0_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1_MASK 0xe00
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED_MASK 0x1000
#define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2_MASK 0xffffe000
#define RLC_GPU_IOV_SDMA0_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED_MASK 0x1
#define RLC_GPU_IOV_SDMA1_STATUS__PREEMPTED__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED_MASK 0xfe
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED__SHIFT 0x1
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED_MASK 0x100
#define RLC_GPU_IOV_SDMA1_STATUS__SAVED__SHIFT 0x8
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1_MASK 0xe00
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED1__SHIFT 0x9
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED_MASK 0x1000
#define RLC_GPU_IOV_SDMA1_STATUS__RESTORED__SHIFT 0xc
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2_MASK 0xffffe000
#define RLC_GPU_IOV_SDMA1_STATUS__RESERVED2__SHIFT 0xd
#define RLC_GPU_IOV_SMU_RESPONSE__RESP_MASK 0xffffffff
#define RLC_GPU_IOV_SMU_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR_MASK 0xffff
#define RLC_GPU_IOV_VIRT_RESET_REQ__VF_FLR__SHIFT 0x0
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED_MASK 0x7fff0000
#define RLC_GPU_IOV_VIRT_RESET_REQ__RESERVED__SHIFT 0x10
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR_MASK 0x80000000
#define RLC_GPU_IOV_VIRT_RESET_REQ__SOFT_PF_FLR__SHIFT 0x1f
#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff
#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0
#define RLC_GPU_IOV_INT_DISABLE__DISABLE_MASK 0xffffffff
#define RLC_GPU_IOV_INT_DISABLE__DISABLE__SHIFT 0x0
#define RLC_GPU_IOV_INT_FORCE__FORCE_MASK 0xffffffff
#define RLC_GPU_IOV_INT_FORCE__FORCE__SHIFT 0x0
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_SDMA0_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS_MASK 0xffffffff
#define RLC_GPU_IOV_SDMA1_BUSY_STATUS__VM_BUSY_STATUS__SHIFT 0x0
#define RLC_GPU_IOV_SCH_0__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_0__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_1__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_1__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_2__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_2__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_3__DATA_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_3__DATA__SHIFT 0x0
#define RLC_GPU_IOV_SCH_INT__interrupt_MASK 0xffffffff
#define RLC_GPU_IOV_SCH_INT__interrupt__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000
#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11
#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000
#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19
#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f
#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400
#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa
#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000
#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000
#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000
#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000
#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000
#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000
#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e
#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40
#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1
#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2
#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4
#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8
#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10
#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20
#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40
#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80
#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100
#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200
#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400
#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800
#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000
#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000
#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000
#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000
#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1
#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2
#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4
#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8
#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10
#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20
#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40
#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80
#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100
#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200
#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400
#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800
#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000
#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000
#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000
#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000
#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1
#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000
#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe
#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f
#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0
#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40
#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000
#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1
#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10
#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100
#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000
#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000
#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10
#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000
#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000
#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18
#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff
#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0
#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000
#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0
#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00
#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000
#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf
#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0
#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00
#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000
#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000
#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000
#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000
#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000
#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00
#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9
#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000
#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc
#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000
#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe
#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000
#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10
#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000
#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12
#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff
#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000
#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10
#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff
#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0
#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000
#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10
#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1
#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2
#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4
#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8
#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10
#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20
#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40
#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6
#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1
#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0
#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2
#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1
#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4
#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2
#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8
#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3
#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10
#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4
#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20
#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5
#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff
#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00
#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000
#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000
#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18
#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff
#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0
#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00
#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8
#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000
#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10
#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000
#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80
#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000
#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000
#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000
#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80
#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000
#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc
#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000
#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000
#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f
#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1
#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0
#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe
#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1
#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3
#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc
#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70
#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80
#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100
#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200
#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000
#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000
#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10
#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff
#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0
#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200
#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9
#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff
#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff
#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff
#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0
#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff
#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10
#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4
#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1
#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf
#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0
#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4
#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00
#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8
#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000
#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000
#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe
#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000
#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000
#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1
#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4
#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000
#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000
#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3
#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0
#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc
#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2
#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30
#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4
#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1
#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff
#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000
#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000
#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000
#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000
#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000
#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b
#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1
#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0
#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe
#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1
#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0
#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4
#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00
#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa
#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000
#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000
#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18
#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000
#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19
#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000
#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f
#define SPI_DEBUG_READ__DATA_MASK 0xffffff
#define SPI_DEBUG_READ__DATA__SHIFT 0x0
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2
#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1
#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4
#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2
#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8
#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3
#define SPI_EDC_CNT__SED_MASK 0xff
#define SPI_EDC_CNT__SED__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00
#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00
#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff
#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff
#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf
#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0
#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4
#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00
#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8
#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000
#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc
#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000
#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10
#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000
#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14
#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000
#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18
#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000
#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf
#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10
#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40
#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80
#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100
#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00
#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000
#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10
#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1
#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0
#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2
#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1
#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4
#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2
#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8
#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3
#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10
#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4
#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20
#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5
#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40
#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6
#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80
#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7
#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100
#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8
#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200
#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9
#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400
#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa
#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800
#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb
#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000
#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc
#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000
#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd
#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000
#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe
#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000
#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000
#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000
#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000
#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000
#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000
#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000
#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15
#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000
#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16
#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000
#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0
#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf
#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0
#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4
#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000
#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc
#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000
#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10
#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000
#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000
#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14
#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000
#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15
#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000
#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000
#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f
#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0
#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00
#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8
#define CGTS_RD_REG__READ_DATA_MASK 0x3fff
#define CGTS_RD_REG__READ_DATA__SHIFT 0x0
#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000
#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10
#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f
#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80
#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000
#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000
#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f
#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0
#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80
#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f
#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80
#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000
#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000
#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f
#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800
#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000
#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b
#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000
#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000
#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000
#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000
#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000
#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000
#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000
#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000
#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000
#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000
#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000
#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000
#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000
#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000
#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000
#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000
#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000
#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf
#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0
#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10
#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000
#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff
#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000
#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f
#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff
#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000
#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f
#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1
#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0
#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2
#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1
#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4
#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2
#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8
#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3
#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10
#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100
#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000
#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000
#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000
#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14
#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000
#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15
#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000
#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16
#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1
#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0
#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff
#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff
#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff
#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff
#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0
#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00
#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8
#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000
#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff
#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000
#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000
#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff
#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff
#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0
#define BCI_DEBUG_READ__DATA_MASK 0xffffff
#define BCI_DEBUG_READ__DATA__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff
#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff
#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff
#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f
#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0
#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6
#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000
#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000
#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00
#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0
#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000
#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000
#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000
#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800
#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000
#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000
#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f
#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000
#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000
#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000
#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000
#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000
#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000
#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e
#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00
#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000
#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000
#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000
#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80
#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100
#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00
#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f
#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00
#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa
#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff
#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff
#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f
#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0
#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00
#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa
#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000
#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc
#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000
#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14
#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000
#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15
#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000
#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000
#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17
#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000
#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18
#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000
#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a
#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000
#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d
#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1
#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e
#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1
#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40
#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6
#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80
#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7
#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000
#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff
#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0
#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000
#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10
#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000
#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16
#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000
#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a
#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0
#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff
#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0
#define SQ_CONFIG__UNUSED_MASK 0xff
#define SQ_CONFIG__UNUSED__SHIFT 0x0
#define SQ_CONFIG__DEBUG_EN_MASK 0x100
#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200
#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400
#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000
#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000
#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000
#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000
#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000
#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000
#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000
#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000
#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13
#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000
#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15
#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3
#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0
#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc
#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2
#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30
#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4
#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40
#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6
#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80
#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7
#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100
#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8
#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200
#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9
#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400
#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa
#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800
#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb
#define SQC_CONFIG__EVICT_LRU_MASK 0x3000
#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc
#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000
#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe
#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000
#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf
#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000
#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10
#define SQC_CACHES__TARGET_INST_MASK 0x1
#define SQC_CACHES__TARGET_INST__SHIFT 0x0
#define SQC_CACHES__TARGET_DATA_MASK 0x2
#define SQC_CACHES__TARGET_DATA__SHIFT 0x1
#define SQC_CACHES__INVALIDATE_MASK 0x4
#define SQC_CACHES__INVALIDATE__SHIFT 0x2
#define SQC_CACHES__WRITEBACK_MASK 0x8
#define SQC_CACHES__WRITEBACK__SHIFT 0x3
#define SQC_CACHES__VOL_MASK 0x10
#define SQC_CACHES__VOL__SHIFT 0x4
#define SQC_CACHES__COMPLETE_MASK 0x10000
#define SQC_CACHES__COMPLETE__SHIFT 0x10
#define SQC_WRITEBACK__DWB_MASK 0x1
#define SQC_WRITEBACK__DWB__SHIFT 0x0
#define SQC_WRITEBACK__DIRTY_MASK 0x2
#define SQC_WRITEBACK__DIRTY__SHIFT 0x1
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000
#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000
#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000
#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000
#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d
#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f
#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0
#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380
#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7
#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00
#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa
#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f
#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0
#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00
#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8
#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000
#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c
#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000
#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d
#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000
#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e
#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000
#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf
#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00
#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000
#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000
#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1
#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2
#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8
#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200
#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400
#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000
#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000
#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000
#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000
#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6
#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8
#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10
#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4
#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff
#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0
#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1
#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1
#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0
#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2
#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1
#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4
#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2
#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8
#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3
#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10
#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4
#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20
#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5
#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40
#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00
#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000
#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd
#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff
#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0
#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000
#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1
#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000
#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10
#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000
#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14
#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000
#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18
#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000
#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff
#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000
#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000
#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000
#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000
#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000
#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c
#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000
#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000
#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000
#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10
#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff
#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0
#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000
#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10
#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000
#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff
#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000
#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f
#define SQ_TIME_HI__TIME_MASK 0xffffffff
#define SQ_TIME_HI__TIME__SHIFT 0x0
#define SQ_TIME_LO__TIME_MASK 0xffffffff
#define SQ_TIME_LO__TIME__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff
#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0
#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf
#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff
#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f
#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0
#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20
#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80
#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7
#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00
#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000
#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000
#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000
#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf
#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7
#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0
#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38
#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3
#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0
#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6
#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00
#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9
#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000
#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc
#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000
#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf
#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000
#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12
#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000
#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000
#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000
#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19
#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000
#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000
#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b
#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000
#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000
#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e
#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000
#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000
#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff
#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000
#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff
#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff
#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000
#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10
#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff
#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000
#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff
#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000
#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10
#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000
#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d
#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000
#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e
#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000
#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f
#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff
#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0
#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7
#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0
#define SQ_LB_CTR_CTRL__START_MASK 0x1
#define SQ_LB_CTR_CTRL__START__SHIFT 0x0
#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2
#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1
#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4
#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2
#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff
#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0
#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff
#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0
#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff
#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0
#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff
#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0
#define SQC_EDC_CNT__INST_SEC_MASK 0xff
#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0
#define SQC_EDC_CNT__INST_DED_MASK 0xff00
#define SQC_EDC_CNT__INST_DED__SHIFT 0x8
#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000
#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10
#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000
#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18
#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff
#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0
#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00
#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8
#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000
#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10
#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff
#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0
#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00
#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8
#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000
#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10
#define SQ_EDC_INFO__WAVE_ID_MASK 0xf
#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0
#define SQ_EDC_INFO__SIMD_ID_MASK 0x30
#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4
#define SQ_EDC_INFO__SOURCE_MASK 0x1c0
#define SQ_EDC_INFO__SOURCE__SHIFT 0x6
#define SQ_EDC_INFO__VM_ID_MASK 0x1e00
#define SQ_EDC_INFO__VM_ID__SHIFT 0x9
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff
#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000
#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000
#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000
#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff
#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0
#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7
#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38
#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00
#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000
#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000
#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf
#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000
#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000
#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000
#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17
#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000
#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18
#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000
#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19
#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000
#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a
#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000
#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b
#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000
#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff
#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff
#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0
#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00
#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000
#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000
#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000
#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e
#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff
#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000
#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe
#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000
#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000
#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f
#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7
#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38
#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0
#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6
#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00
#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000
#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000
#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10
#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000
#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14
#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000
#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19
#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000
#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a
#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000
#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b
#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000
#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff
#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0
#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000
#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff
#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0
#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000
#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff
#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000
#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000
#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000
#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000
#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000
#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000
#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000
#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff
#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0
#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7
#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0
#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38
#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3
#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0
#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00
#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000
#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000
#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000
#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000
#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000
#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000
#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000
#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000
#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000
#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000
#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff
#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0
#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000
#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc
#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000
#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18
#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000
#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff
#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000
#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000
#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000
#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16
#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000
#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18
#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000
#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000
#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c
#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000
#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000
#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000
#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000
#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e
#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff
#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0
#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff
#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0
#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff
#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000
#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000
#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000
#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe
#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000
#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf
#define SQ_IND_INDEX__WAVE_ID_MASK 0xf
#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0
#define SQ_IND_INDEX__SIMD_ID_MASK 0x30
#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4
#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0
#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6
#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000
#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc
#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000
#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd
#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000
#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe
#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000
#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf
#define SQ_IND_INDEX__INDEX_MASK 0xffff0000
#define SQ_IND_INDEX__INDEX__SHIFT 0x10
#define SQ_CMD__CMD_MASK 0x7
#define SQ_CMD__CMD__SHIFT 0x0
#define SQ_CMD__MODE_MASK 0x70
#define SQ_CMD__MODE__SHIFT 0x4
#define SQ_CMD__CHECK_VMID_MASK 0x80
#define SQ_CMD__CHECK_VMID__SHIFT 0x7
#define SQ_CMD__DATA_MASK 0x700
#define SQ_CMD__DATA__SHIFT 0x8
#define SQ_CMD__WAVE_ID_MASK 0xf0000
#define SQ_CMD__WAVE_ID__SHIFT 0x10
#define SQ_CMD__SIMD_ID_MASK 0x300000
#define SQ_CMD__SIMD_ID__SHIFT 0x14
#define SQ_CMD__QUEUE_ID_MASK 0x7000000
#define SQ_CMD__QUEUE_ID__SHIFT 0x18
#define SQ_CMD__VM_ID_MASK 0xf0000000
#define SQ_CMD__VM_ID__SHIFT 0x1c
#define SQ_IND_DATA__DATA_MASK 0xffffffff
#define SQ_IND_DATA__DATA__SHIFT 0x0
#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff
#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff
#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0
#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf
#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0
#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0
#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4
#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff
#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0
#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff
#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0
#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff
#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0
#define SQ_WAVE_PC_HI__PC_HI_MASK 0xff
#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0
#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7
#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0
#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8
#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10
#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0
#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5
#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300
#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8
#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00
#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa
#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000
#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10
#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000
#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14
#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000
#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18
#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000
#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a
#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000
#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b
#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000
#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000
#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e
#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1
#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0
#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2
#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4
#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2
#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0
#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4
#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00
#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8
#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff
#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0
#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff
#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0
#define SQ_WAVE_STATUS__SCC_MASK 0x1
#define SQ_WAVE_STATUS__SCC__SHIFT 0x0
#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6
#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1
#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18
#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3
#define SQ_WAVE_STATUS__PRIV_MASK 0x20
#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5
#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40
#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6
#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80
#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7
#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100
#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8
#define SQ_WAVE_STATUS__EXECZ_MASK 0x200
#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9
#define SQ_WAVE_STATUS__VCCZ_MASK 0x400
#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa
#define SQ_WAVE_STATUS__IN_TG_MASK 0x800
#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb
#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000
#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc
#define SQ_WAVE_STATUS__HALT_MASK 0x2000
#define SQ_WAVE_STATUS__HALT__SHIFT 0xd
#define SQ_WAVE_STATUS__TRAP_MASK 0x4000
#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe
#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000
#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf
#define SQ_WAVE_STATUS__VALID_MASK 0x10000
#define SQ_WAVE_STATUS__VALID__SHIFT 0x10
#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000
#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11
#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000
#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12
#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000
#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13
#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000
#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14
#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000
#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15
#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000
#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16
#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000
#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17
#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000
#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b
#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf
#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0
#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0
#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4
#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100
#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8
#define SQ_WAVE_MODE__IEEE_MASK 0x200
#define SQ_WAVE_MODE__IEEE__SHIFT 0x9
#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400
#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa
#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800
#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb
#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000
#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc
#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000
#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b
#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000
#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c
#define SQ_WAVE_MODE__CSP_MASK 0xe0000000
#define SQ_WAVE_MODE__CSP__SHIFT 0x1d
#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff
#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0
#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400
#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000
#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10
#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000
#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d
#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf
#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0
#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30
#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4
#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0
#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6
#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00
#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8
#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000
#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc
#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000
#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd
#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000
#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10
#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000
#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14
#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000
#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18
#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000
#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b
#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000
#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f
#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00
#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000
#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000
#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18
#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff
#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000
#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc
#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf
#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0
#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70
#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4
#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00
#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8
#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000
#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc
#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000
#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf
#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000
#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10
#define SQ_WAVE_M0__M0_MASK 0xffffffff
#define SQ_WAVE_M0__M0__SHIFT 0x0
#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0
#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff
#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0
#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0
#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff
#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0
#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0
#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff
#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1
#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2
#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000
#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000
#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0
#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4
#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1
#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0
#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4
#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff
#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0
#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff
#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0
#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000
#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10
#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff
#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0
#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff
#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0
#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3
#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0
#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4
#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2
#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18
#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3
#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0
#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5
#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700
#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8
#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800
#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0
#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600
#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800
#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff
#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff
#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff
#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0
#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000
#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000
#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00
#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000
#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000
#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000
#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000
#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff
#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000
#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff
#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0
#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00
#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60
#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300
#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00
#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000
#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000
#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000
#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13
#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff
#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff
#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000
#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a
#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000
#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b
#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000
#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c
#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000
#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f
#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff
#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0
#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000
#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12
#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000
#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13
#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000
#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000
#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17
#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000
#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19
#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000
#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a
#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000
#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff
#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0
#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000
#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10
#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0
#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2
#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4
#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2
#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8
#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3
#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10
#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4
#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20
#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5
#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40
#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6
#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80
#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7
#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a
#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff
#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0
#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100
#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8
#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200
#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9
#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00
#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000
#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000
#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12
#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000
#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14
#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000
#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18
#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000
#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a
#define SQ_SOP2__SSRC0_MASK 0xff
#define SQ_SOP2__SSRC0__SHIFT 0x0
#define SQ_SOP2__SSRC1_MASK 0xff00
#define SQ_SOP2__SSRC1__SHIFT 0x8
#define SQ_SOP2__SDST_MASK 0x7f0000
#define SQ_SOP2__SDST__SHIFT 0x10
#define SQ_SOP2__OP_MASK 0x3f800000
#define SQ_SOP2__OP__SHIFT 0x17
#define SQ_SOP2__ENCODING_MASK 0xc0000000
#define SQ_SOP2__ENCODING__SHIFT 0x1e
#define SQ_VOP1__SRC0_MASK 0x1ff
#define SQ_VOP1__SRC0__SHIFT 0x0
#define SQ_VOP1__OP_MASK 0x1fe00
#define SQ_VOP1__OP__SHIFT 0x9
#define SQ_VOP1__VDST_MASK 0x1fe0000
#define SQ_VOP1__VDST__SHIFT 0x11
#define SQ_VOP1__ENCODING_MASK 0xfe000000
#define SQ_VOP1__ENCODING__SHIFT 0x19
#define SQ_MTBUF_1__VADDR_MASK 0xff
#define SQ_MTBUF_1__VADDR__SHIFT 0x0
#define SQ_MTBUF_1__VDATA_MASK 0xff00
#define SQ_MTBUF_1__VDATA__SHIFT 0x8
#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000
#define SQ_MTBUF_1__SRSRC__SHIFT 0x10
#define SQ_MTBUF_1__SLC_MASK 0x400000
#define SQ_MTBUF_1__SLC__SHIFT 0x16
#define SQ_MTBUF_1__TFE_MASK 0x800000
#define SQ_MTBUF_1__TFE__SHIFT 0x17
#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000
#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18
#define SQ_EXP_1__VSRC0_MASK 0xff
#define SQ_EXP_1__VSRC0__SHIFT 0x0
#define SQ_EXP_1__VSRC1_MASK 0xff00
#define SQ_EXP_1__VSRC1__SHIFT 0x8
#define SQ_EXP_1__VSRC2_MASK 0xff0000
#define SQ_EXP_1__VSRC2__SHIFT 0x10
#define SQ_EXP_1__VSRC3_MASK 0xff000000
#define SQ_EXP_1__VSRC3__SHIFT 0x18
#define SQ_MUBUF_1__VADDR_MASK 0xff
#define SQ_MUBUF_1__VADDR__SHIFT 0x0
#define SQ_MUBUF_1__VDATA_MASK 0xff00
#define SQ_MUBUF_1__VDATA__SHIFT 0x8
#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000
#define SQ_MUBUF_1__SRSRC__SHIFT 0x10
#define SQ_MUBUF_1__TFE_MASK 0x800000
#define SQ_MUBUF_1__TFE__SHIFT 0x17
#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000
#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18
#define SQ_SMEM_1__OFFSET_MASK 0xfffff
#define SQ_SMEM_1__OFFSET__SHIFT 0x0
#define SQ_INST__ENCODING_MASK 0xffffffff
#define SQ_INST__ENCODING__SHIFT 0x0
#define SQ_EXP_0__EN_MASK 0xf
#define SQ_EXP_0__EN__SHIFT 0x0
#define SQ_EXP_0__TGT_MASK 0x3f0
#define SQ_EXP_0__TGT__SHIFT 0x4
#define SQ_EXP_0__COMPR_MASK 0x400
#define SQ_EXP_0__COMPR__SHIFT 0xa
#define SQ_EXP_0__DONE_MASK 0x800
#define SQ_EXP_0__DONE__SHIFT 0xb
#define SQ_EXP_0__VM_MASK 0x1000
#define SQ_EXP_0__VM__SHIFT 0xc
#define SQ_EXP_0__ENCODING_MASK 0xfc000000
#define SQ_EXP_0__ENCODING__SHIFT 0x1a
#define SQ_MUBUF_0__OFFSET_MASK 0xfff
#define SQ_MUBUF_0__OFFSET__SHIFT 0x0
#define SQ_MUBUF_0__OFFEN_MASK 0x1000
#define SQ_MUBUF_0__OFFEN__SHIFT 0xc
#define SQ_MUBUF_0__IDXEN_MASK 0x2000
#define SQ_MUBUF_0__IDXEN__SHIFT 0xd
#define SQ_MUBUF_0__GLC_MASK 0x4000
#define SQ_MUBUF_0__GLC__SHIFT 0xe
#define SQ_MUBUF_0__LDS_MASK 0x10000
#define SQ_MUBUF_0__LDS__SHIFT 0x10
#define SQ_MUBUF_0__SLC_MASK 0x20000
#define SQ_MUBUF_0__SLC__SHIFT 0x11
#define SQ_MUBUF_0__OP_MASK 0x1fc0000
#define SQ_MUBUF_0__OP__SHIFT 0x12
#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000
#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a
#define SQ_VOP_SDWA__SRC0_MASK 0xff
#define SQ_VOP_SDWA__SRC0__SHIFT 0x0
#define SQ_VOP_SDWA__DST_SEL_MASK 0x700
#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8
#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800
#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb
#define SQ_VOP_SDWA__CLAMP_MASK 0x2000
#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd
#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000
#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10
#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000
#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13
#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000
#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000
#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000
#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18
#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000
#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b
#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000
#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c
#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000
#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d
#define SQ_VOP3_0__VDST_MASK 0xff
#define SQ_VOP3_0__VDST__SHIFT 0x0
#define SQ_VOP3_0__ABS_MASK 0x700
#define SQ_VOP3_0__ABS__SHIFT 0x8
#define SQ_VOP3_0__CLAMP_MASK 0x8000
#define SQ_VOP3_0__CLAMP__SHIFT 0xf
#define SQ_VOP3_0__OP_MASK 0x3ff0000
#define SQ_VOP3_0__OP__SHIFT 0x10
#define SQ_VOP3_0__ENCODING_MASK 0xfc000000
#define SQ_VOP3_0__ENCODING__SHIFT 0x1a
#define SQ_VOP2__SRC0_MASK 0x1ff
#define SQ_VOP2__SRC0__SHIFT 0x0
#define SQ_VOP2__VSRC1_MASK 0x1fe00
#define SQ_VOP2__VSRC1__SHIFT 0x9
#define SQ_VOP2__VDST_MASK 0x1fe0000
#define SQ_VOP2__VDST__SHIFT 0x11
#define SQ_VOP2__OP_MASK 0x7e000000
#define SQ_VOP2__OP__SHIFT 0x19
#define SQ_VOP2__ENCODING_MASK 0x80000000
#define SQ_VOP2__ENCODING__SHIFT 0x1f
#define SQ_MTBUF_0__OFFSET_MASK 0xfff
#define SQ_MTBUF_0__OFFSET__SHIFT 0x0
#define SQ_MTBUF_0__OFFEN_MASK 0x1000
#define SQ_MTBUF_0__OFFEN__SHIFT 0xc
#define SQ_MTBUF_0__IDXEN_MASK 0x2000
#define SQ_MTBUF_0__IDXEN__SHIFT 0xd
#define SQ_MTBUF_0__GLC_MASK 0x4000
#define SQ_MTBUF_0__GLC__SHIFT 0xe
#define SQ_MTBUF_0__OP_MASK 0x78000
#define SQ_MTBUF_0__OP__SHIFT 0xf
#define SQ_MTBUF_0__DFMT_MASK 0x780000
#define SQ_MTBUF_0__DFMT__SHIFT 0x13
#define SQ_MTBUF_0__NFMT_MASK 0x3800000
#define SQ_MTBUF_0__NFMT__SHIFT 0x17
#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000
#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a
#define SQ_SOPP__SIMM16_MASK 0xffff
#define SQ_SOPP__SIMM16__SHIFT 0x0
#define SQ_SOPP__OP_MASK 0x7f0000
#define SQ_SOPP__OP__SHIFT 0x10
#define SQ_SOPP__ENCODING_MASK 0xff800000
#define SQ_SOPP__ENCODING__SHIFT 0x17
#define SQ_FLAT_0__GLC_MASK 0x10000
#define SQ_FLAT_0__GLC__SHIFT 0x10
#define SQ_FLAT_0__SLC_MASK 0x20000
#define SQ_FLAT_0__SLC__SHIFT 0x11
#define SQ_FLAT_0__OP_MASK 0x1fc0000
#define SQ_FLAT_0__OP__SHIFT 0x12
#define SQ_FLAT_0__ENCODING_MASK 0xfc000000
#define SQ_FLAT_0__ENCODING__SHIFT 0x1a
#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff
#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0
#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00
#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8
#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000
#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf
#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000
#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10
#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000
#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a
#define SQ_MIMG_1__VADDR_MASK 0xff
#define SQ_MIMG_1__VADDR__SHIFT 0x0
#define SQ_MIMG_1__VDATA_MASK 0xff00
#define SQ_MIMG_1__VDATA__SHIFT 0x8
#define SQ_MIMG_1__SRSRC_MASK 0x1f0000
#define SQ_MIMG_1__SRSRC__SHIFT 0x10
#define SQ_MIMG_1__SSAMP_MASK 0x3e00000
#define SQ_MIMG_1__SSAMP__SHIFT 0x15
#define SQ_MIMG_1__D16_MASK 0x80000000
#define SQ_MIMG_1__D16__SHIFT 0x1f
#define SQ_SOP1__SSRC0_MASK 0xff
#define SQ_SOP1__SSRC0__SHIFT 0x0
#define SQ_SOP1__OP_MASK 0xff00
#define SQ_SOP1__OP__SHIFT 0x8
#define SQ_SOP1__SDST_MASK 0x7f0000
#define SQ_SOP1__SDST__SHIFT 0x10
#define SQ_SOP1__ENCODING_MASK 0xff800000
#define SQ_SOP1__ENCODING__SHIFT 0x17
#define SQ_SOPC__SSRC0_MASK 0xff
#define SQ_SOPC__SSRC0__SHIFT 0x0
#define SQ_SOPC__SSRC1_MASK 0xff00
#define SQ_SOPC__SSRC1__SHIFT 0x8
#define SQ_SOPC__OP_MASK 0x7f0000
#define SQ_SOPC__OP__SHIFT 0x10
#define SQ_SOPC__ENCODING_MASK 0xff800000
#define SQ_SOPC__ENCODING__SHIFT 0x17
#define SQ_FLAT_1__ADDR_MASK 0xff
#define SQ_FLAT_1__ADDR__SHIFT 0x0
#define SQ_FLAT_1__DATA_MASK 0xff00
#define SQ_FLAT_1__DATA__SHIFT 0x8
#define SQ_FLAT_1__TFE_MASK 0x800000
#define SQ_FLAT_1__TFE__SHIFT 0x17
#define SQ_FLAT_1__VDST_MASK 0xff000000
#define SQ_FLAT_1__VDST__SHIFT 0x18
#define SQ_DS_1__ADDR_MASK 0xff
#define SQ_DS_1__ADDR__SHIFT 0x0
#define SQ_DS_1__DATA0_MASK 0xff00
#define SQ_DS_1__DATA0__SHIFT 0x8
#define SQ_DS_1__DATA1_MASK 0xff0000
#define SQ_DS_1__DATA1__SHIFT 0x10
#define SQ_DS_1__VDST_MASK 0xff000000
#define SQ_DS_1__VDST__SHIFT 0x18
#define SQ_VOP3_1__SRC0_MASK 0x1ff
#define SQ_VOP3_1__SRC0__SHIFT 0x0
#define SQ_VOP3_1__SRC1_MASK 0x3fe00
#define SQ_VOP3_1__SRC1__SHIFT 0x9
#define SQ_VOP3_1__SRC2_MASK 0x7fc0000
#define SQ_VOP3_1__SRC2__SHIFT 0x12
#define SQ_VOP3_1__OMOD_MASK 0x18000000
#define SQ_VOP3_1__OMOD__SHIFT 0x1b
#define SQ_VOP3_1__NEG_MASK 0xe0000000
#define SQ_VOP3_1__NEG__SHIFT 0x1d
#define SQ_SMEM_0__SBASE_MASK 0x3f
#define SQ_SMEM_0__SBASE__SHIFT 0x0
#define SQ_SMEM_0__SDATA_MASK 0x1fc0
#define SQ_SMEM_0__SDATA__SHIFT 0x6
#define SQ_SMEM_0__GLC_MASK 0x10000
#define SQ_SMEM_0__GLC__SHIFT 0x10
#define SQ_SMEM_0__IMM_MASK 0x20000
#define SQ_SMEM_0__IMM__SHIFT 0x11
#define SQ_SMEM_0__OP_MASK 0x3fc0000
#define SQ_SMEM_0__OP__SHIFT 0x12
#define SQ_SMEM_0__ENCODING_MASK 0xfc000000
#define SQ_SMEM_0__ENCODING__SHIFT 0x1a
#define SQ_MIMG_0__DMASK_MASK 0xf00
#define SQ_MIMG_0__DMASK__SHIFT 0x8
#define SQ_MIMG_0__UNORM_MASK 0x1000
#define SQ_MIMG_0__UNORM__SHIFT 0xc
#define SQ_MIMG_0__GLC_MASK 0x2000
#define SQ_MIMG_0__GLC__SHIFT 0xd
#define SQ_MIMG_0__DA_MASK 0x4000
#define SQ_MIMG_0__DA__SHIFT 0xe
#define SQ_MIMG_0__R128_MASK 0x8000
#define SQ_MIMG_0__R128__SHIFT 0xf
#define SQ_MIMG_0__TFE_MASK 0x10000
#define SQ_MIMG_0__TFE__SHIFT 0x10
#define SQ_MIMG_0__LWE_MASK 0x20000
#define SQ_MIMG_0__LWE__SHIFT 0x11
#define SQ_MIMG_0__OP_MASK 0x1fc0000
#define SQ_MIMG_0__OP__SHIFT 0x12
#define SQ_MIMG_0__SLC_MASK 0x2000000
#define SQ_MIMG_0__SLC__SHIFT 0x19
#define SQ_MIMG_0__ENCODING_MASK 0xfc000000
#define SQ_MIMG_0__ENCODING__SHIFT 0x1a
#define SQ_SOPK__SIMM16_MASK 0xffff
#define SQ_SOPK__SIMM16__SHIFT 0x0
#define SQ_SOPK__SDST_MASK 0x7f0000
#define SQ_SOPK__SDST__SHIFT 0x10
#define SQ_SOPK__OP_MASK 0xf800000
#define SQ_SOPK__OP__SHIFT 0x17
#define SQ_SOPK__ENCODING_MASK 0xf0000000
#define SQ_SOPK__ENCODING__SHIFT 0x1c
#define SQ_DS_0__OFFSET0_MASK 0xff
#define SQ_DS_0__OFFSET0__SHIFT 0x0
#define SQ_DS_0__OFFSET1_MASK 0xff00
#define SQ_DS_0__OFFSET1__SHIFT 0x8
#define SQ_DS_0__GDS_MASK 0x10000
#define SQ_DS_0__GDS__SHIFT 0x10
#define SQ_DS_0__OP_MASK 0x1fe0000
#define SQ_DS_0__OP__SHIFT 0x11
#define SQ_DS_0__ENCODING_MASK 0xfc000000
#define SQ_DS_0__ENCODING__SHIFT 0x1a
#define SQ_VOP_DPP__SRC0_MASK 0xff
#define SQ_VOP_DPP__SRC0__SHIFT 0x0
#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00
#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8
#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000
#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13
#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000
#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14
#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000
#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15
#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000
#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16
#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000
#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17
#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000
#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18
#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000
#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c
#define SQ_VOPC__SRC0_MASK 0x1ff
#define SQ_VOPC__SRC0__SHIFT 0x0
#define SQ_VOPC__VSRC1_MASK 0x1fe00
#define SQ_VOPC__VSRC1__SHIFT 0x9
#define SQ_VOPC__OP_MASK 0x1fe0000
#define SQ_VOPC__OP__SHIFT 0x11
#define SQ_VOPC__ENCODING_MASK 0xfe000000
#define SQ_VOPC__ENCODING__SHIFT 0x19
#define SQ_VINTRP__VSRC_MASK 0xff
#define SQ_VINTRP__VSRC__SHIFT 0x0
#define SQ_VINTRP__ATTRCHAN_MASK 0x300
#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8
#define SQ_VINTRP__ATTR_MASK 0xfc00
#define SQ_VINTRP__ATTR__SHIFT 0xa
#define SQ_VINTRP__OP_MASK 0x30000
#define SQ_VINTRP__OP__SHIFT 0x10
#define SQ_VINTRP__VDST_MASK 0x3fc0000
#define SQ_VINTRP__VDST__SHIFT 0x12
#define SQ_VINTRP__ENCODING_MASK 0xfc000000
#define SQ_VINTRP__ENCODING__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf
#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000
#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1
#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2
#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4
#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8
#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10
#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20
#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40
#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80
#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100
#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200
#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400
#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800
#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000
#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000
#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000
#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a
#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000
#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b
#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000
#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c
#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000
#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d
#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000
#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000
#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f
#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2
#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1
#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4
#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2
#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10
#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4
#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20
#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5
#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80
#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7
#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100
#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8
#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400
#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa
#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800
#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb
#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000
#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf
#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000
#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12
#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000
#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15
#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000
#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000
#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100
#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000
#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000
#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100
#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000
#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18
#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000
#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f
#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0
#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffff80
#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0x7
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_CTRL__CACHE_SIZE_MASK 0x3
#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0
#define TCC_CTRL__RATE_MASK 0xc
#define TCC_CTRL__RATE__SHIFT 0x2
#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0
#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00
#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8
#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000
#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc
#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000
#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10
#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000
#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14
#define TCC_CTRL__MDC_SIZE_MASK 0x3000000
#define TCC_CTRL__MDC_SIZE__SHIFT 0x18
#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000
#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000
#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c
#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff
#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0
#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000
#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10
#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1
#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0
#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2
#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1
#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2
#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf
#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf
#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000
#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3
#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0
#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30
#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4
#define TD_CNTL__PAD_STALL_EN_MASK 0x100
#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8
#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600
#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9
#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800
#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb
#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000
#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf
#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000
#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10
#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000
#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12
#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000
#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13
#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000
#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14
#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000
#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15
#define TD_STATUS__BUSY_MASK 0x80000000
#define TD_STATUS__BUSY__SHIFT 0x1f
#define TD_DEBUG_INDEX__INDEX_MASK 0x1f
#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0
#define TD_DEBUG_DATA__DATA_MASK 0xffffffff
#define TD_DEBUG_DATA__DATA__SHIFT 0x0
#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1
#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0
#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2
#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1
#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4
#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2
#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TD_SCRATCH__SCRATCH_MASK 0xffffffff
#define TD_SCRATCH__SCRATCH__SHIFT 0x0
#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000
#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd
#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000
#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10
#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000
#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1
#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0
#define TA_CNTL_AUX__RESERVED_MASK 0xe
#define TA_CNTL_AUX__RESERVED__SHIFT 0x1
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000
#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10
#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000
#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11
#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000
#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000
#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13
#define TA_RESERVED_010C__Unused_MASK 0xffffffff
#define TA_RESERVED_010C__Unused__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff
#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff
#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0
#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000
#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc
#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000
#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd
#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000
#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe
#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000
#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10
#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000
#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11
#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000
#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12
#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000
#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14
#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000
#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15
#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000
#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16
#define TA_STATUS__IN_BUSY_MASK 0x1000000
#define TA_STATUS__IN_BUSY__SHIFT 0x18
#define TA_STATUS__FG_BUSY_MASK 0x2000000
#define TA_STATUS__FG_BUSY__SHIFT 0x19
#define TA_STATUS__LA_BUSY_MASK 0x4000000
#define TA_STATUS__LA_BUSY__SHIFT 0x1a
#define TA_STATUS__FL_BUSY_MASK 0x8000000
#define TA_STATUS__FL_BUSY__SHIFT 0x1b
#define TA_STATUS__TA_BUSY_MASK 0x10000000
#define TA_STATUS__TA_BUSY__SHIFT 0x1c
#define TA_STATUS__FA_BUSY_MASK 0x20000000
#define TA_STATUS__FA_BUSY__SHIFT 0x1d
#define TA_STATUS__AL_BUSY_MASK 0x40000000
#define TA_STATUS__AL_BUSY__SHIFT 0x1e
#define TA_STATUS__BUSY_MASK 0x80000000
#define TA_STATUS__BUSY__SHIFT 0x1f
#define TA_DEBUG_INDEX__INDEX_MASK 0x1f
#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0
#define TA_DEBUG_DATA__DATA_MASK 0xffffffff
#define TA_DEBUG_DATA__DATA__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00
#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00
#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00
#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TA_SCRATCH__SCRATCH_MASK 0xffffffff
#define TA_SCRATCH__SCRATCH__SHIFT 0x0
#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff
#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0
#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1
#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0
#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6
#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1
#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18
#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3
#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0
#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5
#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00
#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8
#define TCP_INVALIDATE__START_MASK 0x1
#define TCP_INVALIDATE__START__SHIFT 0x0
#define TCP_STATUS__TCP_BUSY_MASK 0x1
#define TCP_STATUS__TCP_BUSY__SHIFT 0x0
#define TCP_STATUS__INPUT_BUSY_MASK 0x2
#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1
#define TCP_STATUS__ADRS_BUSY_MASK 0x4
#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2
#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8
#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3
#define TCP_STATUS__CNTRL_BUSY_MASK 0x10
#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4
#define TCP_STATUS__LFIFO_BUSY_MASK 0x20
#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5
#define TCP_STATUS__READ_BUSY_MASK 0x40
#define TCP_STATUS__READ_BUSY__SHIFT 0x6
#define TCP_STATUS__FORMAT_BUSY_MASK 0x80
#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7
#define TCP_CNTL__FORCE_HIT_MASK 0x1
#define TCP_CNTL__FORCE_HIT__SHIFT 0x0
#define TCP_CNTL__FORCE_MISS_MASK 0x2
#define TCP_CNTL__FORCE_MISS__SHIFT 0x1
#define TCP_CNTL__L1_SIZE_MASK 0xc
#define TCP_CNTL__L1_SIZE__SHIFT 0x2
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10
#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20
#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000
#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000
#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16
#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000
#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c
#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000
#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d
#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf
#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0
#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0
#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4
#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00
#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8
#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000
#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc
#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000
#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10
#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000
#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14
#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000
#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18
#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000
#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c
#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf
#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0
#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0
#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4
#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00
#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8
#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000
#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc
#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000
#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10
#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000
#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14
#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000
#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18
#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000
#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf
#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0
#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30
#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4
#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0
#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200
#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9
#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff
#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0
#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000
#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10
#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000
#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff
#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000
#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000
#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18
#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff
#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0
#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00
#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8
#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000
#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10
#define TCP_EDC_CNT__UNUSED_MASK 0xff000000
#define TCP_EDC_CNT__UNUSED__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1
#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2
#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1
#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4
#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2
#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8
#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3
#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10
#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4
#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20
#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5
#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40
#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6
#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80
#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7
#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100
#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8
#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200
#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9
#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400
#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa
#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800
#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb
#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000
#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc
#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000
#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd
#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000
#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe
#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000
#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf
#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000
#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10
#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000
#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11
#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000
#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12
#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000
#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13
#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000
#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14
#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000
#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15
#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000
#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16
#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000
#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17
#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000
#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18
#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000
#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19
#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000
#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a
#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000
#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b
#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000
#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c
#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000
#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d
#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000
#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e
#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000
#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3
#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc
#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30
#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0
#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300
#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00
#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000
#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000
#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000
#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000
#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e
#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3
#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0
#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc
#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2
#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30
#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4
#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0
#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6
#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300
#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8
#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00
#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa
#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000
#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc
#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000
#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe
#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000
#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10
#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000
#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12
#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000
#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14
#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000
#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16
#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18
#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a
#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c
#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000
#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000
#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e
#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf
#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0
#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf
#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0
#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff
#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0
#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0
#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6
#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f
#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff
#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0
#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000
#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18
#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000
#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d
#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000
#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000
#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19
#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000
#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000
#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000
#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000
#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff
#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2
#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4
#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4
#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20
#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5
#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff
#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0
#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf
#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf
#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0
#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define TCI_STATUS__TCI_BUSY_MASK 0x1
#define TCI_STATUS__TCI_BUSY__SHIFT 0x0
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff
#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0
#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000
#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10
#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000
#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1
#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0
#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe
#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1
#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6
#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1
#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18
#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3
#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60
#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5
#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180
#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7
#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1
#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2
#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1
#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4
#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8
#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10
#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4
#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20
#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5
#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40
#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80
#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7
#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100
#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8
#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200
#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400
#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa
#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800
#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb
#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000
#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc
#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000
#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd
#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000
#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe
#define GDS_ENHANCE2__MISC_MASK 0xffff
#define GDS_ENHANCE2__MISC__SHIFT 0x0
#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000
#define GDS_ENHANCE2__UNUSED__SHIFT 0x10
#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4
#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2
#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38
#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3
#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0
#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6
#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00
#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa
#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000
#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc
#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1
#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2
#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1
#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4
#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2
#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8
#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3
#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10
#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4
#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00
#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8
#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000
#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10
#define GDS_EDC_CNT__DED_MASK 0xff
#define GDS_EDC_CNT__DED__SHIFT 0x0
#define GDS_EDC_CNT__SED_MASK 0xff00
#define GDS_EDC_CNT__SED__SHIFT 0x8
#define GDS_EDC_CNT__SEC_MASK 0xff0000
#define GDS_EDC_CNT__SEC__SHIFT 0x10
#define GDS_EDC_GRBM_CNT__DED_MASK 0xff
#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0
#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000
#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1
#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2
#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1
#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4
#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2
#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8
#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3
#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10
#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4
#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20
#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5
#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40
#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6
#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80
#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7
#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100
#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8
#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200
#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9
#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400
#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa
#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800
#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb
#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000
#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc
#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f
#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0
#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0
#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5
#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff
#define GDS_DEBUG_DATA__DATA__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10
#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20
#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5
#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0
#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6
#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000
#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f
#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff
#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0
#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff
#define GDS_RD_DATA__READ_DATA__SHIFT 0x0
#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff
#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0
#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff
#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0
#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff
#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0
#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff
#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff
#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff
#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0
#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff
#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff
#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0
#define GDS_ATOM_CNTL__AINC_MASK 0x3f
#define GDS_ATOM_CNTL__AINC__SHIFT 0x0
#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0
#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6
#define GDS_ATOM_CNTL__DMODE_MASK 0x300
#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8
#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00
#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa
#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1
#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0
#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe
#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1
#define GDS_ATOM_BASE__BASE_MASK 0xffff
#define GDS_ATOM_BASE__BASE__SHIFT 0x0
#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000
#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10
#define GDS_ATOM_SIZE__SIZE_MASK 0xffff
#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0
#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000
#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10
#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff
#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0
#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8
#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff
#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0
#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8
#define GDS_ATOM_DST__DST_MASK 0xffffffff
#define GDS_ATOM_DST__DST__SHIFT 0x0
#define GDS_ATOM_OP__OP_MASK 0xff
#define GDS_ATOM_OP__OP__SHIFT 0x0
#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00
#define GDS_ATOM_OP__UNUSED__SHIFT 0x8
#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC0__DATA__SHIFT 0x0
#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC1__DATA__SHIFT 0x0
#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff
#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ0__DATA_MASK 0xffffffff
#define GDS_ATOM_READ0__DATA__SHIFT 0x0
#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff
#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0
#define GDS_ATOM_READ1__DATA_MASK 0xffffffff
#define GDS_ATOM_READ1__DATA__SHIFT 0x0
#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff
#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f
#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0
#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6
#define GDS_GWS_RESOURCE__FLAG_MASK 0x1
#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0
#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe
#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1
#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000
#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd
#define GDS_GWS_RESOURCE__DED_MASK 0x4000
#define GDS_GWS_RESOURCE__DED__SHIFT 0xe
#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000
#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf
#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0x7ff0000
#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10
#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x8000000
#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1b
#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x10000000
#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1c
#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xe0000000
#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1d
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff
#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0
#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000
#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10
#define GDS_OA_CNTL__INDEX_MASK 0xf
#define GDS_OA_CNTL__INDEX__SHIFT 0x0
#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0
#define GDS_OA_CNTL__UNUSED__SHIFT 0x4
#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff
#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0
#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff
#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0
#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000
#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10
#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000
#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14
#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000
#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16
#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000
#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e
#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000
#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f
#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff
#define GDS_OA_INCDEC__VALUE__SHIFT 0x0
#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000
#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f
#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff
#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0
#define GDS_DEBUG_REG0__spare1_MASK 0x3f
#define GDS_DEBUG_REG0__spare1__SHIFT 0x0
#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40
#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6
#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80
#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7
#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000
#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc
#define GDS_DEBUG_REG0__cstate_MASK 0x1e000
#define GDS_DEBUG_REG0__cstate__SHIFT 0xd
#define GDS_DEBUG_REG0__buff_write_MASK 0x20000
#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11
#define GDS_DEBUG_REG0__flush_request_MASK 0x40000
#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12
#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000
#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13
#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000
#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14
#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000
#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15
#define GDS_DEBUG_REG0__spare_MASK 0xffc00000
#define GDS_DEBUG_REG0__spare__SHIFT 0x16
#define GDS_DEBUG_REG1__tag_hit_MASK 0x1
#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0
#define GDS_DEBUG_REG1__tag_miss_MASK 0x2
#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1
#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc
#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2
#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000
#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11
#define GDS_DEBUG_REG1__data_ready_MASK 0x40000
#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12
#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000
#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13
#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000
#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14
#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000
#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15
#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000
#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16
#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000
#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17
#define GDS_DEBUG_REG1__spare_MASK 0xff000000
#define GDS_DEBUG_REG1__spare__SHIFT 0x18
#define GDS_DEBUG_REG2__ds_full_MASK 0x1
#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0
#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2
#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1
#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4
#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2
#define GDS_DEBUG_REG2__cmd_write_MASK 0x8
#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3
#define GDS_DEBUG_REG2__app_sel_MASK 0xf0
#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4
#define GDS_DEBUG_REG2__req_MASK 0x7fff00
#define GDS_DEBUG_REG2__req__SHIFT 0x8
#define GDS_DEBUG_REG2__spare_MASK 0xff800000
#define GDS_DEBUG_REG2__spare__SHIFT 0x17
#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff
#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0
#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800
#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb
#define GDS_DEBUG_REG3__spare_MASK 0xffff8000
#define GDS_DEBUG_REG3__spare__SHIFT 0xf
#define GDS_DEBUG_REG4__gws_busy_MASK 0x1
#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0
#define GDS_DEBUG_REG4__gws_req_MASK 0x2
#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1
#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4
#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2
#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8
#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3
#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200
#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9
#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400
#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa
#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800
#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb
#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000
#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc
#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000
#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd
#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000
#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe
#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000
#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf
#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000
#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10
#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000
#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11
#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000
#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12
#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000
#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13
#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000
#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14
#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000
#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15
#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000
#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16
#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000
#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17
#define GDS_DEBUG_REG4__spare_MASK 0xff000000
#define GDS_DEBUG_REG4__spare__SHIFT 0x18
#define GDS_DEBUG_REG5__write_dis_MASK 0x1
#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0
#define GDS_DEBUG_REG5__dec_error_MASK 0x2
#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1
#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4
#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2
#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8
#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3
#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10
#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4
#define GDS_DEBUG_REG5__spare_MASK 0xe0
#define GDS_DEBUG_REG5__spare__SHIFT 0x5
#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00
#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8
#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000
#define GDS_DEBUG_REG5__spare1__SHIFT 0x16
#define GDS_DEBUG_REG6__oa_busy_MASK 0x1
#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0
#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e
#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1
#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0
#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5
#define GDS_DEBUG_REG6__spare_MASK 0xffe00000
#define GDS_DEBUG_REG6__spare__SHIFT 0x15
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00
#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000
#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00
#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa
#define GDS_VMID0_BASE__BASE_MASK 0xffff
#define GDS_VMID0_BASE__BASE__SHIFT 0x0
#define GDS_VMID1_BASE__BASE_MASK 0xffff
#define GDS_VMID1_BASE__BASE__SHIFT 0x0
#define GDS_VMID2_BASE__BASE_MASK 0xffff
#define GDS_VMID2_BASE__BASE__SHIFT 0x0
#define GDS_VMID3_BASE__BASE_MASK 0xffff
#define GDS_VMID3_BASE__BASE__SHIFT 0x0
#define GDS_VMID4_BASE__BASE_MASK 0xffff
#define GDS_VMID4_BASE__BASE__SHIFT 0x0
#define GDS_VMID5_BASE__BASE_MASK 0xffff
#define GDS_VMID5_BASE__BASE__SHIFT 0x0
#define GDS_VMID6_BASE__BASE_MASK 0xffff
#define GDS_VMID6_BASE__BASE__SHIFT 0x0
#define GDS_VMID7_BASE__BASE_MASK 0xffff
#define GDS_VMID7_BASE__BASE__SHIFT 0x0
#define GDS_VMID8_BASE__BASE_MASK 0xffff
#define GDS_VMID8_BASE__BASE__SHIFT 0x0
#define GDS_VMID9_BASE__BASE_MASK 0xffff
#define GDS_VMID9_BASE__BASE__SHIFT 0x0
#define GDS_VMID10_BASE__BASE_MASK 0xffff
#define GDS_VMID10_BASE__BASE__SHIFT 0x0
#define GDS_VMID11_BASE__BASE_MASK 0xffff
#define GDS_VMID11_BASE__BASE__SHIFT 0x0
#define GDS_VMID12_BASE__BASE_MASK 0xffff
#define GDS_VMID12_BASE__BASE__SHIFT 0x0
#define GDS_VMID13_BASE__BASE_MASK 0xffff
#define GDS_VMID13_BASE__BASE__SHIFT 0x0
#define GDS_VMID14_BASE__BASE_MASK 0xffff
#define GDS_VMID14_BASE__BASE__SHIFT 0x0
#define GDS_VMID15_BASE__BASE_MASK 0xffff
#define GDS_VMID15_BASE__BASE__SHIFT 0x0
#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0
#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff
#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0
#define GDS_GWS_VMID0__BASE_MASK 0x3f
#define GDS_GWS_VMID0__BASE__SHIFT 0x0
#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID0__SIZE__SHIFT 0x10
#define GDS_GWS_VMID1__BASE_MASK 0x3f
#define GDS_GWS_VMID1__BASE__SHIFT 0x0
#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID1__SIZE__SHIFT 0x10
#define GDS_GWS_VMID2__BASE_MASK 0x3f
#define GDS_GWS_VMID2__BASE__SHIFT 0x0
#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID2__SIZE__SHIFT 0x10
#define GDS_GWS_VMID3__BASE_MASK 0x3f
#define GDS_GWS_VMID3__BASE__SHIFT 0x0
#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID3__SIZE__SHIFT 0x10
#define GDS_GWS_VMID4__BASE_MASK 0x3f
#define GDS_GWS_VMID4__BASE__SHIFT 0x0
#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID4__SIZE__SHIFT 0x10
#define GDS_GWS_VMID5__BASE_MASK 0x3f
#define GDS_GWS_VMID5__BASE__SHIFT 0x0
#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID5__SIZE__SHIFT 0x10
#define GDS_GWS_VMID6__BASE_MASK 0x3f
#define GDS_GWS_VMID6__BASE__SHIFT 0x0
#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID6__SIZE__SHIFT 0x10
#define GDS_GWS_VMID7__BASE_MASK 0x3f
#define GDS_GWS_VMID7__BASE__SHIFT 0x0
#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID7__SIZE__SHIFT 0x10
#define GDS_GWS_VMID8__BASE_MASK 0x3f
#define GDS_GWS_VMID8__BASE__SHIFT 0x0
#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID8__SIZE__SHIFT 0x10
#define GDS_GWS_VMID9__BASE_MASK 0x3f
#define GDS_GWS_VMID9__BASE__SHIFT 0x0
#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID9__SIZE__SHIFT 0x10
#define GDS_GWS_VMID10__BASE_MASK 0x3f
#define GDS_GWS_VMID10__BASE__SHIFT 0x0
#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID10__SIZE__SHIFT 0x10
#define GDS_GWS_VMID11__BASE_MASK 0x3f
#define GDS_GWS_VMID11__BASE__SHIFT 0x0
#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID11__SIZE__SHIFT 0x10
#define GDS_GWS_VMID12__BASE_MASK 0x3f
#define GDS_GWS_VMID12__BASE__SHIFT 0x0
#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID12__SIZE__SHIFT 0x10
#define GDS_GWS_VMID13__BASE_MASK 0x3f
#define GDS_GWS_VMID13__BASE__SHIFT 0x0
#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID13__SIZE__SHIFT 0x10
#define GDS_GWS_VMID14__BASE_MASK 0x3f
#define GDS_GWS_VMID14__BASE__SHIFT 0x0
#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID14__SIZE__SHIFT 0x10
#define GDS_GWS_VMID15__BASE_MASK 0x3f
#define GDS_GWS_VMID15__BASE__SHIFT 0x0
#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000
#define GDS_GWS_VMID15__SIZE__SHIFT 0x10
#define GDS_OA_VMID0__MASK_MASK 0xffff
#define GDS_OA_VMID0__MASK__SHIFT 0x0
#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID0__UNUSED__SHIFT 0x10
#define GDS_OA_VMID1__MASK_MASK 0xffff
#define GDS_OA_VMID1__MASK__SHIFT 0x0
#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID1__UNUSED__SHIFT 0x10
#define GDS_OA_VMID2__MASK_MASK 0xffff
#define GDS_OA_VMID2__MASK__SHIFT 0x0
#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID2__UNUSED__SHIFT 0x10
#define GDS_OA_VMID3__MASK_MASK 0xffff
#define GDS_OA_VMID3__MASK__SHIFT 0x0
#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID3__UNUSED__SHIFT 0x10
#define GDS_OA_VMID4__MASK_MASK 0xffff
#define GDS_OA_VMID4__MASK__SHIFT 0x0
#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID4__UNUSED__SHIFT 0x10
#define GDS_OA_VMID5__MASK_MASK 0xffff
#define GDS_OA_VMID5__MASK__SHIFT 0x0
#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID5__UNUSED__SHIFT 0x10
#define GDS_OA_VMID6__MASK_MASK 0xffff
#define GDS_OA_VMID6__MASK__SHIFT 0x0
#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID6__UNUSED__SHIFT 0x10
#define GDS_OA_VMID7__MASK_MASK 0xffff
#define GDS_OA_VMID7__MASK__SHIFT 0x0
#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID7__UNUSED__SHIFT 0x10
#define GDS_OA_VMID8__MASK_MASK 0xffff
#define GDS_OA_VMID8__MASK__SHIFT 0x0
#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID8__UNUSED__SHIFT 0x10
#define GDS_OA_VMID9__MASK_MASK 0xffff
#define GDS_OA_VMID9__MASK__SHIFT 0x0
#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID9__UNUSED__SHIFT 0x10
#define GDS_OA_VMID10__MASK_MASK 0xffff
#define GDS_OA_VMID10__MASK__SHIFT 0x0
#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID10__UNUSED__SHIFT 0x10
#define GDS_OA_VMID11__MASK_MASK 0xffff
#define GDS_OA_VMID11__MASK__SHIFT 0x0
#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID11__UNUSED__SHIFT 0x10
#define GDS_OA_VMID12__MASK_MASK 0xffff
#define GDS_OA_VMID12__MASK__SHIFT 0x0
#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID12__UNUSED__SHIFT 0x10
#define GDS_OA_VMID13__MASK_MASK 0xffff
#define GDS_OA_VMID13__MASK__SHIFT 0x0
#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID13__UNUSED__SHIFT 0x10
#define GDS_OA_VMID14__MASK_MASK 0xffff
#define GDS_OA_VMID14__MASK__SHIFT 0x0
#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID14__UNUSED__SHIFT 0x10
#define GDS_OA_VMID15__MASK_MASK 0xffff
#define GDS_OA_VMID15__MASK__SHIFT 0x0
#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000
#define GDS_OA_VMID15__UNUSED__SHIFT 0x10
#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1
#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0
#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2
#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1
#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4
#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2
#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8
#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3
#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10
#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4
#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20
#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5
#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40
#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6
#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80
#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7
#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100
#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8
#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200
#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9
#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400
#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa
#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800
#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb
#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000
#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc
#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000
#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd
#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000
#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe
#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000
#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf
#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000
#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10
#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000
#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11
#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000
#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12
#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000
#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13
#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000
#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14
#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000
#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15
#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000
#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16
#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000
#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17
#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000
#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18
#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000
#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19
#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000
#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a
#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000
#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b
#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000
#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c
#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000
#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d
#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000
#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e
#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000
#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f
#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1
#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0
#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2
#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1
#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4
#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2
#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8
#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3
#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10
#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4
#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20
#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5
#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40
#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6
#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80
#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7
#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100
#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8
#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200
#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9
#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400
#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa
#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800
#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb
#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000
#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc
#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000
#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd
#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000
#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe
#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000
#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf
#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000
#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10
#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000
#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11
#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000
#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12
#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000
#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13
#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000
#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14
#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000
#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15
#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000
#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16
#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000
#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17
#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000
#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18
#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000
#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19
#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000
#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a
#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000
#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b
#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000
#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c
#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000
#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d
#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000
#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e
#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000
#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f
#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1
#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00
#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2
#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1
#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4
#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2
#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8
#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10
#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20
#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40
#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80
#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100
#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200
#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400
#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800
#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb
#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000
#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc
#define GDS_OA_RESET__RESET_MASK 0x1
#define GDS_OA_RESET__RESET__SHIFT 0x0
#define GDS_OA_RESET__PIPE_ID_MASK 0xff00
#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8
#define GDS_ENHANCE__MISC_MASK 0xffff
#define GDS_ENHANCE__MISC__SHIFT 0x0
#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000
#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10
#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000
#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11
#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000
#define GDS_ENHANCE__UNUSED__SHIFT 0x12
#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff
#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0
#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00
#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8
#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000
#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc
#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000
#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10
#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000
#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14
#define GDS_CS_CTXSW_STATUS__R_MASK 0x1
#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_CS_CTXSW_STATUS__W_MASK 0x2
#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1
#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0
#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2
#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1
#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc
#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2
#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10
#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10
#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff
#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0
#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000
#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10
#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3
#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0
#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc
#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10
#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4
#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20
#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5
#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40
#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6
#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f
#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0
#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000
#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000
#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff
#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0
#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff
#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff
#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc
#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2
#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30
#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40
#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6
#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200
#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9
#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400
#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa
#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800
#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define IA_ENHANCE__MISC_MASK 0xffffffff
#define IA_ENHANCE__MISC__SHIFT 0x0
#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff
#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0
#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff
#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff
#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000
#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000
#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14
#define VGT_IMMED_DATA__DATA_MASK 0xffffffff
#define VGT_IMMED_DATA__DATA__SHIFT 0x0
#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3
#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0
#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff
#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0
#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff
#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f
#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1
#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2
#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1
#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff
#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0
#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1
#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0
#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1
#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff
#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff
#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0
#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff
#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0
#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff
#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0
#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff
#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff
#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f
#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff
#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1
#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0
#define VGT_ENHANCE__MISC_MASK 0xffffffff
#define VGT_ENHANCE__MISC__SHIFT 0x0
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7
#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0
#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3
#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff
#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff
#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff
#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f
#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000
#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000
#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000
#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10
#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf
#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0
#define VGT_GROUP_DECR__DECR_MASK 0xf
#define VGT_GROUP_DECR__DECR__SHIFT 0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4
#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8
#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00
#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000
#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4
#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8
#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3
#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00
#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8
#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000
#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf
#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0
#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000
#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000
#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000
#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000
#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf
#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0
#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000
#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000
#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000
#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000
#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff
#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff
#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f
#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f
#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0
#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7
#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0
#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000
#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000
#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10
#define VGT_GS_MODE__MODE_MASK 0x7
#define VGT_GS_MODE__MODE__SHIFT 0x0
#define VGT_GS_MODE__RESERVED_0_MASK 0x8
#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3
#define VGT_GS_MODE__CUT_MODE_MASK 0x30
#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4
#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0
#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6
#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800
#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb
#define VGT_GS_MODE__RESERVED_2_MASK 0x1000
#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc
#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000
#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd
#define VGT_GS_MODE__RESERVED_3_MASK 0x4000
#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe
#define VGT_GS_MODE__RESERVED_4_MASK 0x8000
#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf
#define VGT_GS_MODE__RESERVED_5_MASK 0x10000
#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000
#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11
#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000
#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000
#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000
#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14
#define VGT_GS_MODE__ONCHIP_MASK 0x600000
#define VGT_GS_MODE__ONCHIP__SHIFT 0x15
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff
#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800
#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000
#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000
#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3
#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10
#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20
#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0
#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6
#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200
#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800
#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000
#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000
#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd
#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000
#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10
#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1
#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0
#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2
#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1
#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4
#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2
#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff
#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700
#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800
#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000
#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000
#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f
#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0
#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80
#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00
#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000
#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16
#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff
#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0
#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff
#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0
#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf
#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0
#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f
#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3
#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0
#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1
#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0
#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2
#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4
#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2
#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8
#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3
#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10
#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4
#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8
#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70
#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00
#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000
#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff
#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000
#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff
#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff
#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff
#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff
#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0
#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3
#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0
#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4
#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2
#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18
#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3
#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20
#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5
#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0
#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100
#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200
#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800
#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000
#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff
#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0
#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff
#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000
#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00
#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8
#define VGT_TF_PARAM__TYPE_MASK 0x3
#define VGT_TF_PARAM__TYPE__SHIFT 0x0
#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c
#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2
#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0
#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100
#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8
#define VGT_TF_PARAM__DEPRECATED_MASK 0x200
#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00
#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa
#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000
#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe
#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000
#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf
#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000
#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11
#define VGT_TF_PARAM__MTYPE_MASK 0x180000
#define VGT_TF_PARAM__MTYPE__SHIFT 0x13
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff
#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00
#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000
#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10
#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff
#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0
#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1
#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e
#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80
#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600
#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9
#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff
#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0
#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1
#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0
#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc
#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff
#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000
#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000
#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000
#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000
#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14
#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000
#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff
#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0
#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff
#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0
#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff
#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff
#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0
#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1
#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2
#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4
#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2
#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8
#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3
#define WD_ENHANCE__MISC_MASK 0xffffffff
#define WD_ENHANCE__MISC__SHIFT 0x0
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff
#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0
#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000
#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000
#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT_MASK 0x1
#define GFX_PIPE_PRIORITY__HP_PIPE_SELECT__SHIFT 0x0
#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000
#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000
#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000
#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf
#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0
#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18
#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000
#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19
#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000
#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000
#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b
#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE_MASK 0x10000000
#define CGTT_WD_CLK_CTRL__ADC_OVERRIDE__SHIFT 0x1c
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000
#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000
#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000
#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f
#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f
#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0
#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40
#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6
#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff
#define VGT_DEBUG_DATA__DATA__SHIFT 0x0
#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f
#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0
#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40
#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6
#define IA_DEBUG_DATA__DATA_MASK 0xffffffff
#define IA_DEBUG_DATA__DATA__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1
#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2
#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1
#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4
#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2
#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8
#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3
#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10
#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4
#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20
#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5
#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40
#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6
#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80
#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7
#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100
#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8
#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200
#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9
#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f
#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0
#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40
#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6
#define WD_DEBUG_DATA__DATA_MASK 0xffffffff
#define WD_DEBUG_DATA__DATA__SHIFT 0x0
#define WD_QOS__DRAW_STALL_MASK 0x1
#define WD_QOS__DRAW_STALL__SHIFT 0x0
#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000
#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000
#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18
#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1
#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0
#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2
#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1
#define WD_DEBUG_REG0__wd_busy_MASK 0x4
#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2
#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8
#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3
#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10
#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4
#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20
#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5
#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40
#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6
#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80
#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7
#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100
#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8
#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200
#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9
#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400
#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa
#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800
#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb
#define WD_DEBUG_REG0__SPARE2_MASK 0x1000
#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc
#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000
#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd
#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000
#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe
#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000
#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf
#define WD_DEBUG_REG0__SPARE3_MASK 0x10000
#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10
#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000
#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11
#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000
#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12
#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000
#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13
#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000
#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14
#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000
#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15
#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000
#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16
#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000
#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17
#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000
#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19
#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000
#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000
#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b
#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000
#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d
#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000
#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e
#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000
#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f
#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1
#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0
#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2
#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1
#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4
#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2
#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8
#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3
#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10
#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4
#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20
#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5
#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40
#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6
#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80
#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7
#define WD_DEBUG_REG1__SPARE0_MASK 0x100
#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8
#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200
#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9
#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400
#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa
#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800
#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb
#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000
#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc
#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000
#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11
#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000
#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000
#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a
#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b
#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000
#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c
#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000
#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d
#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1
#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0
#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2
#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1
#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4
#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2
#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8
#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3
#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10
#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4
#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20
#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5
#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40
#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6
#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80
#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7
#define WD_DEBUG_REG2__SPARE0_MASK 0x100
#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8
#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200
#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9
#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400
#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa
#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800
#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000
#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11
#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000
#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000
#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1
#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0
#define WD_DEBUG_REG3__SPARE0_MASK 0x2
#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1
#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4
#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2
#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8
#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3
#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10
#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4
#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40
#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6
#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80
#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7
#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300
#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8
#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400
#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa
#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800
#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb
#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000
#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc
#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000
#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd
#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000
#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe
#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000
#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf
#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000
#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10
#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000
#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11
#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000
#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12
#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000
#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13
#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000
#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14
#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000
#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15
#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000
#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16
#define WD_DEBUG_REG3__SPARE1_MASK 0x800000
#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17
#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000
#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18
#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000
#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19
#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000
#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a
#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000
#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000
#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c
#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000
#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d
#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1
#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0
#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2
#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1
#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4
#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2
#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8
#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3
#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10
#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4
#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20
#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5
#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40
#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6
#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80
#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7
#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100
#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8
#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200
#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9
#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400
#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa
#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800
#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000
#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc
#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000
#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd
#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000
#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe
#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000
#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10
#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000
#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13
#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000
#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14
#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000
#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15
#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000
#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16
#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000
#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17
#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000
#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18
#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000
#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19
#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000
#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a
#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000
#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b
#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000
#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c
#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000
#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d
#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000
#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e
#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000
#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f
#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1
#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0
#define WD_DEBUG_REG5__SPARE0_MASK 0x2
#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1
#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4
#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2
#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8
#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3
#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10
#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4
#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80
#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7
#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300
#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8
#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400
#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa
#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800
#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb
#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000
#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc
#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000
#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd
#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000
#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe
#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000
#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf
#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000
#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10
#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000
#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11
#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12
#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13
#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000
#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14
#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000
#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15
#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000
#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16
#define WD_DEBUG_REG5__SPARE1_MASK 0x800000
#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17
#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000
#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18
#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000
#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19
#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000
#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a
#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000
#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b
#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000
#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c
#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000
#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000
#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f
#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff
#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0
#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1
#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8
#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3
#define WD_DEBUG_REG7__SPARE0_MASK 0xf0
#define WD_DEBUG_REG7__SPARE0__SHIFT 0x4
#define WD_DEBUG_REG7__SPARE1_MASK 0xf00
#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8
#define WD_DEBUG_REG7__SPARE2_MASK 0xf000
#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc
#define WD_DEBUG_REG7__SPARE3_MASK 0xf0000
#define WD_DEBUG_REG7__SPARE3__SHIFT 0x10
#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000
#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14
#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000
#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15
#define WD_DEBUG_REG7__SPARE4_MASK 0xfc00000
#define WD_DEBUG_REG7__SPARE4__SHIFT 0x16
#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000
#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c
#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000
#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d
#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000
#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e
#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000
#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f
#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1
#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0
#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2
#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1
#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4
#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2
#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8
#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3
#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10
#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4
#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20
#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5
#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40
#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6
#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80
#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7
#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100
#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8
#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200
#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9
#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400
#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa
#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800
#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb
#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000
#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc
#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000
#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12
#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000
#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13
#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000
#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14
#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000
#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b
#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000
#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c
#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000
#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d
#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000
#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e
#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000
#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f
#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1
#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0
#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2
#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1
#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4
#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2
#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8
#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3
#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10
#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4
#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20
#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5
#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40
#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6
#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80
#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7
#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100
#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8
#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200
#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9
#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400
#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa
#define WD_DEBUG_REG9__SPARE0_MASK 0xf800
#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb
#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000
#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10
#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000
#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13
#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000
#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14
#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000
#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18
#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000
#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19
#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000
#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a
#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000
#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b
#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000
#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c
#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000
#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e
#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000
#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f
#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1
#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0
#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2
#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1
#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4
#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2
#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8
#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3
#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10
#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4
#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20
#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5
#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40
#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6
#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80
#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7
#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100
#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8
#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200
#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9
#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400
#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa
#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800
#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb
#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000
#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc
#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000
#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd
#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000
#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe
#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000
#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf
#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000
#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000
#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000
#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000
#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000
#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f
#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1
#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0
#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2
#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1
#define IA_DEBUG_REG0__ia_busy_MASK 0x4
#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2
#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8
#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3
#define IA_DEBUG_REG0__SPARE0_MASK 0x10
#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4
#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20
#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5
#define IA_DEBUG_REG0__dma_busy_MASK 0x40
#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6
#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80
#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7
#define IA_DEBUG_REG0__grp_busy_MASK 0x100
#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8
#define IA_DEBUG_REG0__SPARE1_MASK 0x200
#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9
#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400
#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa
#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800
#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb
#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000
#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc
#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000
#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd
#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000
#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe
#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000
#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19
#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000
#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a
#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000
#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b
#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000
#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c
#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000
#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e
#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000
#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f
#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1
#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0
#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2
#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1
#define IA_DEBUG_REG1__start_new_packet_MASK 0x4
#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2
#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8
#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3
#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10
#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4
#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60
#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5
#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80
#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7
#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100
#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8
#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200
#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9
#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400
#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa
#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800
#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb
#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000
#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc
#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000
#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd
#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000
#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe
#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000
#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf
#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000
#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10
#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000
#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11
#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000
#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12
#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000
#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13
#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000
#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14
#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000
#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15
#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000
#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16
#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000
#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17
#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000
#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18
#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000
#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19
#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000
#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a
#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000
#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b
#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000
#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c
#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000
#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d
#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000
#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e
#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000
#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f
#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1
#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0
#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2
#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1
#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4
#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2
#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8
#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3
#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10
#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4
#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60
#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5
#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80
#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7
#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100
#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8
#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200
#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9
#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400
#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa
#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800
#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb
#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000
#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc
#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000
#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd
#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000
#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe
#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000
#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf
#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000
#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10
#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000
#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11
#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000
#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12
#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000
#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13
#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000
#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14
#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000
#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15
#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000
#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16
#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000
#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17
#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000
#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18
#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000
#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19
#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000
#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a
#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000
#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b
#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000
#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c
#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000
#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d
#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000
#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e
#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000
#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f
#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1
#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0
#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2
#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1
#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4
#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2
#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8
#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3
#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10
#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4
#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20
#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5
#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40
#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6
#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80
#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7
#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100
#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8
#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200
#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9
#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400
#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa
#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800
#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb
#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000
#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc
#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000
#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd
#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000
#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe
#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000
#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf
#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000
#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10
#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000
#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11
#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000
#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12
#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000
#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13
#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000
#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14
#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000
#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15
#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000
#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16
#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000
#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17
#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000
#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18
#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000
#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a
#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000
#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b
#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000
#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c
#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000
#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d
#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000
#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e
#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000
#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f
#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1
#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0
#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2
#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1
#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4
#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2
#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8
#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3
#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10
#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4
#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20
#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5
#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40
#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6
#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80
#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7
#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100
#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8
#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200
#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9
#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400
#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa
#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800
#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb
#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000
#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc
#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000
#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd
#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000
#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe
#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000
#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf
#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000
#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10
#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000
#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11
#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000
#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14
#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000
#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15
#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000
#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18
#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000
#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19
#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000
#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a
#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000
#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c
#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000
#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d
#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000
#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e
#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000
#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f
#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff
#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0
#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000
#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10
#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000
#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e
#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000
#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f
#define IA_DEBUG_REG6__current_shift_q_MASK 0xf
#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0
#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0
#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4
#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00
#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8
#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000
#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd
#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000
#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe
#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000
#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf
#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000
#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10
#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000
#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15
#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000
#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16
#define IA_DEBUG_REG6__extract_group_MASK 0x800000
#define IA_DEBUG_REG6__extract_group__SHIFT 0x17
#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000
#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18
#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf
#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0
#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0
#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4
#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00
#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8
#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000
#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc
#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000
#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10
#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000
#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14
#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000
#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17
#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000
#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18
#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000
#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19
#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000
#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a
#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000
#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b
#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000
#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c
#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000
#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d
#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000
#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e
#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000
#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f
#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f
#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0
#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20
#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5
#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40
#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6
#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80
#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7
#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100
#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8
#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200
#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9
#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400
#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa
#define IA_DEBUG_REG8__grp_continued_MASK 0x800
#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb
#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000
#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc
#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000
#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf
#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000
#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15
#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000
#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18
#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000
#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19
#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000
#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a
#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000
#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b
#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000
#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c
#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1
#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0
#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2
#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1
#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4
#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2
#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8
#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3
#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10
#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4
#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20
#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5
#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40
#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6
#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80
#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7
#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100
#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8
#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200
#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9
#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400
#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa
#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800
#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb
#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000
#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc
#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000
#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd
#define IA_DEBUG_REG9__SPARE0_MASK 0x4000
#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe
#define IA_DEBUG_REG9__SPARE1_MASK 0x8000
#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf
#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000
#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10
#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000
#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11
#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000
#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12
#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000
#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13
#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000
#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14
#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1
#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0
#define VGT_DEBUG_REG0__SPARE9_MASK 0x2
#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1
#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4
#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2
#define VGT_DEBUG_REG0__SPARE8_MASK 0x8
#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3
#define VGT_DEBUG_REG0__SPARE7_MASK 0x10
#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4
#define VGT_DEBUG_REG0__SPARE6_MASK 0x20
#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5
#define VGT_DEBUG_REG0__SPARE5_MASK 0x40
#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6
#define VGT_DEBUG_REG0__SPARE4_MASK 0x80
#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7
#define VGT_DEBUG_REG0__pi_busy_MASK 0x100
#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8
#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200
#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9
#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400
#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa
#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800
#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb
#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000
#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc
#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000
#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd
#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000
#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe
#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000
#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf
#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000
#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10
#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000
#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11
#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000
#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12
#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000
#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13
#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000
#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14
#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000
#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15
#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000
#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16
#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000
#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17
#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000
#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18
#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000
#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19
#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000
#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a
#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000
#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b
#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000
#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c
#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000
#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d
#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000
#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e
#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000
#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f
#define VGT_DEBUG_REG1__SPARE9_MASK 0x1
#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0
#define VGT_DEBUG_REG1__SPARE8_MASK 0x2
#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1
#define VGT_DEBUG_REG1__SPARE7_MASK 0x4
#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2
#define VGT_DEBUG_REG1__SPARE6_MASK 0x8
#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3
#define VGT_DEBUG_REG1__SPARE5_MASK 0x10
#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4
#define VGT_DEBUG_REG1__SPARE4_MASK 0x20
#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5
#define VGT_DEBUG_REG1__SPARE3_MASK 0x40
#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6
#define VGT_DEBUG_REG1__SPARE2_MASK 0x80
#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7
#define VGT_DEBUG_REG1__SPARE1_MASK 0x100
#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8
#define VGT_DEBUG_REG1__SPARE0_MASK 0x200
#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9
#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400
#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa
#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800
#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb
#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000
#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc
#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000
#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd
#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000
#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe
#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000
#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf
#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000
#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10
#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000
#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11
#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000
#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12
#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000
#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13
#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000
#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14
#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000
#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15
#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000
#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16
#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000
#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17
#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000
#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18
#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000
#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19
#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000
#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a
#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000
#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b
#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000
#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c
#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000
#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d
#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000
#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e
#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000
#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f
#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1
#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0
#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2
#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1
#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4
#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2
#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8
#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3
#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10
#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4
#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20
#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5
#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40
#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6
#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80
#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7
#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100
#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8
#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200
#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9
#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400
#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa
#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800
#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb
#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000
#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc
#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000
#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd
#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000
#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe
#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000
#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf
#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000
#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10
#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000
#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11
#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000
#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12
#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000
#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13
#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000
#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14
#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000
#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15
#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000
#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16
#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000
#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17
#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000
#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18
#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000
#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19
#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000
#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a
#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000
#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b
#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000
#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c
#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000
#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d
#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff
#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0
#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000
#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc
#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000
#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12
#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000
#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a
#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff
#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0
#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00
#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8
#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000
#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18
#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000
#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d
#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000
#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e
#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000
#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f
#define VGT_DEBUG_REG5__SPARE4_MASK 0x7
#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0
#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8
#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3
#define VGT_DEBUG_REG5__SPARE3_MASK 0x700
#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8
#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800
#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb
#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000
#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10
#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000
#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13
#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000
#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18
#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000
#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b
#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff
#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0
#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000
#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10
#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1
#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0
#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2
#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1
#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4
#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2
#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8
#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3
#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10
#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4
#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0
#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5
#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000
#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10
#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1
#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2
#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4
#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2
#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8
#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3
#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10
#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4
#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20
#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5
#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40
#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80
#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7
#define VGT_DEBUG_REG8__valid_r2_MASK 0x100
#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8
#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200
#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9
#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400
#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa
#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800
#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb
#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000
#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc
#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000
#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd
#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000
#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe
#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000
#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf
#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000
#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10
#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000
#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11
#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000
#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12
#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000
#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13
#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000
#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14
#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000
#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15
#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000
#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16
#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000
#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17
#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000
#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18
#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000
#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a
#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000
#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b
#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000
#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c
#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000
#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d
#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000
#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e
#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000
#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f
#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3
#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0
#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4
#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2
#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8
#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3
#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10
#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4
#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20
#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5
#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40
#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6
#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80
#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7
#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100
#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8
#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200
#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9
#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400
#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa
#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800
#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb
#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000
#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12
#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000
#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13
#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000
#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16
#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000
#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17
#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000
#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18
#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000
#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19
#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000
#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a
#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000
#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000
#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c
#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000
#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d
#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000
#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e
#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000
#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f
#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f
#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0
#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20
#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5
#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40
#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6
#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180
#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7
#define VGT_DEBUG_REG10__SPARE2_MASK 0x600
#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000
#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc
#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000
#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd
#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000
#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17
#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1
#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2
#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4
#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3
#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10
#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4
#define VGT_DEBUG_REG11__SPARE1_MASK 0x20
#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5
#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40
#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6
#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80
#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7
#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100
#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8
#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200
#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9
#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400
#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa
#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800
#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb
#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000
#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc
#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000
#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd
#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000
#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe
#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000
#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf
#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000
#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10
#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000
#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11
#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000
#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12
#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000
#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13
#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000
#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14
#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000
#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15
#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000
#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16
#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000
#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17
#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000
#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18
#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000
#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000
#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b
#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000
#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c
#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000
#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d
#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000
#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e
#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000
#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f
#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7
#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0
#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38
#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3
#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0
#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00
#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9
#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000
#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc
#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000
#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf
#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000
#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12
#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000
#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000
#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18
#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000
#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000
#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e
#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000
#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f
#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7
#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0
#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38
#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3
#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0
#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6
#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00
#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9
#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000
#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc
#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000
#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf
#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000
#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12
#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000
#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16
#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000
#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17
#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000
#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18
#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000
#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19
#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000
#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a
#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000
#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG14__SPARE3_MASK 0xf
#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0
#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10
#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4
#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20
#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5
#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40
#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6
#define VGT_DEBUG_REG14__SPARE8_MASK 0x180
#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7
#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200
#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9
#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400
#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa
#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800
#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb
#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000
#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc
#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000
#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15
#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000
#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16
#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000
#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19
#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000
#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a
#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000
#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b
#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000
#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c
#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000
#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d
#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000
#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e
#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000
#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f
#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1
#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2
#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4
#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2
#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8
#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3
#define VGT_DEBUG_REG15__counters_full_MASK 0x10
#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4
#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0
#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5
#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00
#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa
#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000
#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf
#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000
#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14
#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000
#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a
#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000
#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c
#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000
#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d
#define VGT_DEBUG_REG16__gog_busy_MASK 0x1
#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0
#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe
#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1
#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10
#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20
#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5
#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40
#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6
#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80
#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7
#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100
#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8
#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200
#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9
#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400
#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa
#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800
#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb
#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000
#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc
#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000
#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd
#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000
#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe
#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000
#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf
#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000
#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10
#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000
#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11
#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000
#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12
#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000
#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13
#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000
#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14
#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000
#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000
#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16
#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000
#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17
#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000
#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18
#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000
#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19
#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000
#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c
#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000
#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d
#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000
#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e
#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000
#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000
#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc
#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000
#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12
#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1
#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0
#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2
#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1
#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8
#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3
#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10
#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20
#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5
#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40
#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6
#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80
#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7
#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700
#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8
#define VGT_DEBUG_REG18__valid_indices_MASK 0x800
#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb
#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000
#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc
#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000
#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd
#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000
#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe
#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000
#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf
#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000
#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10
#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000
#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11
#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000
#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12
#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000
#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13
#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000
#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14
#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000
#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15
#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000
#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16
#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000
#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17
#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000
#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18
#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000
#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b
#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000
#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c
#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000
#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d
#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1
#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0
#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2
#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1
#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4
#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2
#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8
#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3
#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10
#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4
#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20
#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5
#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40
#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6
#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80
#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7
#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100
#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8
#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200
#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9
#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400
#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa
#define VGT_DEBUG_REG19__hold_prim_MASK 0x800
#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb
#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000
#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc
#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000
#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd
#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000
#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe
#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000
#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf
#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000
#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10
#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000
#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11
#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000
#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12
#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000
#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13
#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000
#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14
#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000
#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a
#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000
#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b
#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000
#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c
#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000
#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e
#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000
#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000
#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10
#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000
#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11
#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000
#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12
#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000
#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16
#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000
#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d
#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000
#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e
#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000
#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f
#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1
#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0
#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2
#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1
#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4
#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2
#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8
#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3
#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10
#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4
#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20
#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5
#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40
#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6
#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80
#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7
#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100
#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8
#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200
#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9
#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400
#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa
#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800
#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb
#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000
#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc
#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000
#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd
#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000
#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe
#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000
#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf
#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000
#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10
#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000
#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000
#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000
#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15
#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000
#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16
#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000
#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17
#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000
#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18
#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000
#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19
#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000
#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a
#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000
#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b
#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000
#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c
#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000
#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000
#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e
#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000
#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f
#define VGT_DEBUG_REG22__cm_state16_MASK 0x3
#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0
#define VGT_DEBUG_REG22__cm_state17_MASK 0xc
#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2
#define VGT_DEBUG_REG22__cm_state18_MASK 0x30
#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4
#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0
#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6
#define VGT_DEBUG_REG22__cm_state20_MASK 0x300
#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8
#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00
#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa
#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000
#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc
#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000
#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe
#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000
#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10
#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000
#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12
#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000
#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14
#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000
#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16
#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000
#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18
#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000
#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a
#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000
#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c
#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000
#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e
#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1
#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0
#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2
#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1
#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4
#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2
#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8
#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3
#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10
#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4
#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20
#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5
#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40
#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6
#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80
#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7
#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100
#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8
#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200
#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9
#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400
#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa
#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800
#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb
#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000
#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc
#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000
#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd
#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000
#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe
#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000
#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf
#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000
#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11
#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000
#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15
#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000
#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18
#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff
#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0
#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000
#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18
#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000
#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a
#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff
#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0
#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000
#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a
#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000
#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e
#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000
#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f
#define VGT_DEBUG_REG26__cm_state0_MASK 0x3
#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0
#define VGT_DEBUG_REG26__cm_state1_MASK 0xc
#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2
#define VGT_DEBUG_REG26__cm_state2_MASK 0x30
#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4
#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0
#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6
#define VGT_DEBUG_REG26__cm_state4_MASK 0x300
#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8
#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00
#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa
#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000
#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc
#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000
#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe
#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000
#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10
#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000
#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12
#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000
#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14
#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000
#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16
#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000
#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18
#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000
#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a
#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000
#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c
#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000
#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e
#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1
#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0
#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2
#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1
#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8
#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3
#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10
#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4
#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20
#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5
#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40
#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6
#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80
#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7
#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300
#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8
#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400
#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa
#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800
#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb
#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000
#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc
#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000
#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000
#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000
#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10
#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000
#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000
#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12
#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000
#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13
#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000
#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000
#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f
#define VGT_DEBUG_REG28__con_state_q_MASK 0xf
#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000
#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f
#define VGT_DEBUG_REG29__con_state_q_MASK 0xf
#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000
#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f
#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1
#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0
#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2
#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1
#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4
#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2
#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8
#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3
#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10
#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4
#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20
#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5
#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40
#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6
#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80
#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7
#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100
#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8
#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200
#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9
#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400
#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa
#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800
#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb
#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000
#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc
#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000
#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd
#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000
#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe
#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000
#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf
#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000
#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10
#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000
#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11
#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000
#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12
#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000
#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13
#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000
#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14
#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000
#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15
#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000
#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16
#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000
#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17
#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000
#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18
#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000
#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19
#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000
#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a
#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000
#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b
#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000
#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c
#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000
#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d
#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000
#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e
#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000
#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f
#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1
#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0
#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2
#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1
#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4
#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2
#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8
#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3
#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10
#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4
#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20
#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5
#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40
#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80
#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100
#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8
#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200
#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9
#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400
#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa
#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800
#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb
#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000
#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc
#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000
#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe
#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000
#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf
#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000
#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10
#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000
#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11
#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000
#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12
#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000
#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13
#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000
#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14
#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000
#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15
#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000
#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16
#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000
#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17
#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000
#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18
#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000
#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19
#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000
#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000
#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000
#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c
#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1
#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0
#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2
#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1
#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4
#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2
#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8
#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3
#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10
#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4
#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20
#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5
#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40
#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6
#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80
#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7
#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100
#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8
#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200
#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9
#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400
#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa
#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800
#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb
#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000
#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc
#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000
#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd
#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000
#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe
#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000
#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf
#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000
#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10
#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000
#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11
#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000
#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12
#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000
#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13
#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000
#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14
#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000
#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15
#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000
#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16
#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000
#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17
#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000
#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000
#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a
#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000
#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c
#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000
#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d
#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000
#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e
#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000
#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f
#define VGT_DEBUG_REG34__con_state_q_MASK 0xf
#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0
#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10
#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4
#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20
#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5
#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40
#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6
#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80
#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7
#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100
#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8
#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200
#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9
#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400
#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa
#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800
#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb
#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000
#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc
#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000
#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd
#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000
#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe
#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000
#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf
#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000
#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10
#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000
#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11
#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000
#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12
#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000
#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13
#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000
#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14
#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000
#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15
#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000
#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16
#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000
#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17
#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000
#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18
#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000
#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19
#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000
#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a
#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000
#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b
#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000
#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c
#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000
#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d
#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000
#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e
#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000
#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f
#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff
#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff
#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00
#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000
#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00
#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000
#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff
#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00
#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000
#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000
#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00
#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000
#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff
#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0
#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000
#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff
#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff
#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0
#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff
#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0
#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff
#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1
#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0
#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2
#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1
#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc
#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10
#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20
#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5
#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff
#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0
#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000
#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff
#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0
#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000
#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000
#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10
#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000
#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000
#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b
#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000
#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f
#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff
#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0
#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000
#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10
#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff
#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0
#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00
#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8
#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000
#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10
#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000
#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18
#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff
#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0
#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00
#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8
#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000
#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10
#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000
#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18
#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff
#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0
#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00
#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8
#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000
#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10
#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000
#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18

#define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK    0x00000001
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT  0x00000000

#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK       0x0000007e
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK       0x00001f80L
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT     0x00000001
#define DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT     0x00000007

#define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK   0x1fffe000L
#define DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d

#define DIDT_SQ_STALL_CTRL__UNUSED_0_MASK                  0xe0000000L
#define DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT                0x0000001d

#define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK       0x00000001L
#define DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT     0x00000000

#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK       0x00007ffeL
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT     0x00000001
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK       0x1fff8000L
#define DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT     0x0000000f

#define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK    0x00000001L
#define DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT  0x00000000

#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK       0x0000007eL
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK       0x00001f80L
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT     0x00000001
#define DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT     0x00000007

#define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK   0x1fffe000L
#define DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d

#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK     0x00000fc0L
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK     0x0003f000L
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT   0x00000006
#define DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT   0x0000000c

#define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK       0x00000001L
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK       0x00007ffeL
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK       0x1fff8000L

#define DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT     0x00000000
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT     0x00000001
#define DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT     0x0000000f

#define DIDT_TD_STALL_CTRL__UNUSED_0_MASK                  0xe0000000L
#define DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT                0x0000001d

#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK     0x00000fc0L
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK     0x0003f000L
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT   0x00000006
#define DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT   0x0000000c

#define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK   0x00000001L
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT 0x00000000

#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK      0x0000007eL
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK      0x00001f80L
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT    0x00000001
#define DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT    0x00000007

#define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK  0x1fffe000L
#define DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT 0x0000000d

#define DIDT_TCP_STALL_CTRL__UNUSED_0_MASK                 0xe0000000L
#define DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT               0x0000001d

#define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK      0x00000001L
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK      0x00007ffeL
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK      0x1fff8000L
#define DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT    0x00000000
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT    0x00000001
#define DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT    0x0000000f

#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK    0x00000fc0L
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK    0x0003f000L
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT  0x00000006
#define DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT  0x0000000c

#endif /* GFX_8_0_SH_MASK_H */