1 /*
2  * GMC_7_1 Register documentation
3  *
4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef GMC_7_1_SH_MASK_H
25 #define GMC_7_1_SH_MASK_H
26 
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
37 #define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
38 #define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
39 #define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
40 #define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
41 #define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
42 #define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
43 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
45 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
46 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
47 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
48 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
49 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
50 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
51 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
52 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
53 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
54 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
55 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
56 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
57 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
58 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
59 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
60 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
61 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
62 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
63 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
64 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
65 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
66 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
67 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
68 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
69 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
70 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
71 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
72 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
73 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
74 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
75 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
76 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
77 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
78 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
79 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
80 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
81 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
82 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
83 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
84 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
85 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
86 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
87 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
88 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
89 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
90 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
91 #define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
92 #define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
93 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
94 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
95 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
96 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
97 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
98 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
99 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
100 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
101 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
102 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
103 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
104 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
105 #define MC_ARB_FED_CNTL__MODE_MASK 0x3
106 #define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
107 #define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
108 #define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
109 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
110 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
111 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
112 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
113 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
114 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
115 #define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
116 #define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
117 #define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
118 #define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
119 #define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
120 #define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
121 #define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
122 #define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
123 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
124 #define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
125 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
126 #define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
127 #define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
128 #define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
129 #define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
130 #define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
131 #define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
132 #define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
133 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
134 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
135 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
136 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
137 #define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
138 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
139 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
140 #define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
141 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
142 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
143 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
144 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
145 #define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
146 #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
147 #define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
148 #define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
149 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
150 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
151 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
152 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
153 #define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
154 #define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
155 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
156 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
157 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
158 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
159 #define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
160 #define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
161 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
162 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
163 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
164 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
165 #define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
166 #define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
167 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
168 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
169 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
170 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
171 #define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
172 #define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
173 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
174 #define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
175 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
176 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
177 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
178 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
179 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
180 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
181 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
182 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
183 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
184 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
185 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
186 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
187 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
188 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
189 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
190 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
191 #define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
192 #define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
193 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
194 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
195 #define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
196 #define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
197 #define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
198 #define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
199 #define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
200 #define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
201 #define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
202 #define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
203 #define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
204 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
205 #define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
206 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
207 #define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
208 #define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
209 #define MC_ARB_PERF_CID__CH0_MASK 0xff
210 #define MC_ARB_PERF_CID__CH0__SHIFT 0x0
211 #define MC_ARB_PERF_CID__CH1_MASK 0xff00
212 #define MC_ARB_PERF_CID__CH1__SHIFT 0x8
213 #define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
214 #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
215 #define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
216 #define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
217 #define MC_ARB_GECC2__ENABLE_MASK 0x1
218 #define MC_ARB_GECC2__ENABLE__SHIFT 0x0
219 #define MC_ARB_GECC2__ECC_MODE_MASK 0x6
220 #define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
221 #define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
222 #define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
223 #define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
224 #define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
225 #define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
226 #define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
227 #define MC_ARB_GECC2__READ_ERR_MASK 0x3800
228 #define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
229 #define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
230 #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
231 #define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
232 #define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
233 #define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
234 #define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
235 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
236 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
237 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
238 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
239 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
240 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
241 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
242 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
243 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
244 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
245 #define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
246 #define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
247 #define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
248 #define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
249 #define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
250 #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
251 #define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
252 #define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
253 #define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
254 #define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
255 #define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
256 #define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
257 #define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
258 #define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
259 #define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
260 #define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
261 #define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
262 #define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
263 #define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
264 #define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
265 #define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
266 #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
267 #define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
268 #define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
269 #define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
270 #define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
271 #define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
272 #define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
273 #define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
274 #define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
275 #define MC_ARB_MISC3__TBD_FIELD_MASK 0xfffffff8
276 #define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x3
277 #define MC_ARB_WCDR_2__WPRE_INC_STEP_MASK 0xf
278 #define MC_ARB_WCDR_2__WPRE_INC_STEP__SHIFT 0x0
279 #define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD_MASK 0x1f0
280 #define MC_ARB_WCDR_2__WPRE_MIN_THRESHOLD__SHIFT 0x4
281 #define MC_ARB_WCDR_2__DEBUG_0_MASK 0x200
282 #define MC_ARB_WCDR_2__DEBUG_0__SHIFT 0x9
283 #define MC_ARB_WCDR_2__DEBUG_1_MASK 0x400
284 #define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
285 #define MC_ARB_WCDR_2__DEBUG_2_MASK 0x800
286 #define MC_ARB_WCDR_2__DEBUG_2__SHIFT 0xb
287 #define MC_ARB_WCDR_2__DEBUG_3_MASK 0x1000
288 #define MC_ARB_WCDR_2__DEBUG_3__SHIFT 0xc
289 #define MC_ARB_WCDR_2__DEBUG_4_MASK 0x2000
290 #define MC_ARB_WCDR_2__DEBUG_4__SHIFT 0xd
291 #define MC_ARB_WCDR_2__DEBUG_5_MASK 0x4000
292 #define MC_ARB_WCDR_2__DEBUG_5__SHIFT 0xe
293 #define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
294 #define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
295 #define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
296 #define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
297 #define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
298 #define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
299 #define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
300 #define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
301 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
302 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
303 #define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
304 #define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
305 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
306 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
307 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
308 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
309 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
310 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
311 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
312 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
313 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
314 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
315 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
316 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
317 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
318 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
319 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
320 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
321 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
322 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
323 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
324 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
325 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
326 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
327 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
328 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
329 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
330 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
331 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
332 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
333 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
334 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
335 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
336 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
337 #define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
338 #define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
339 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
340 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
341 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
342 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
343 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
344 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
345 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
346 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
347 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
348 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
349 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
350 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
351 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
352 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
353 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
354 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
355 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
356 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
357 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
358 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
359 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
360 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
361 #define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
362 #define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
363 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
364 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
365 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
366 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
367 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
368 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
369 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
370 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
371 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
372 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
373 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
374 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
375 #define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
376 #define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
377 #define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
378 #define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
379 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
380 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
381 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
382 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
383 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
384 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
385 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
386 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
387 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
388 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
389 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
390 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
391 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
392 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
393 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
394 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
395 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
396 #define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
397 #define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
398 #define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
399 #define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
400 #define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
401 #define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
402 #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
403 #define MC_ARB_MISC2__GECC_MASK 0x40000
404 #define MC_ARB_MISC2__GECC__SHIFT 0x12
405 #define MC_ARB_MISC2__GECC_RST_MASK 0x80000
406 #define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
407 #define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
408 #define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
409 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
410 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
411 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
412 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
413 #define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
414 #define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
415 #define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
416 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
417 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
418 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
419 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
420 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
421 #define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
422 #define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
423 #define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
424 #define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
425 #define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
426 #define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
427 #define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
428 #define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
429 #define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
430 #define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
431 #define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
432 #define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
433 #define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
434 #define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
435 #define MC_ARB_MISC__CALI_RATES_MASK 0x600000
436 #define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
437 #define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
438 #define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
439 #define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
440 #define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
441 #define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
442 #define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
443 #define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
444 #define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
445 #define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
446 #define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
447 #define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
448 #define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
449 #define MC_ARB_BANKMAP__BANK0_MASK 0xf
450 #define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
451 #define MC_ARB_BANKMAP__BANK1_MASK 0xf0
452 #define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
453 #define MC_ARB_BANKMAP__BANK2_MASK 0xf00
454 #define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
455 #define MC_ARB_BANKMAP__BANK3_MASK 0xf000
456 #define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
457 #define MC_ARB_BANKMAP__RANK_MASK 0xf0000
458 #define MC_ARB_BANKMAP__RANK__SHIFT 0x10
459 #define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
460 #define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
461 #define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
462 #define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
463 #define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
464 #define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
465 #define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
466 #define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
467 #define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
468 #define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
469 #define MC_ARB_RAMCFG__RSV_1_MASK 0x200
470 #define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
471 #define MC_ARB_RAMCFG__RSV_2_MASK 0x400
472 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
473 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800
474 #define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
475 #define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
476 #define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
477 #define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
478 #define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
479 #define MC_ARB_POP__ENABLE_ARB_MASK 0x1
480 #define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
481 #define MC_ARB_POP__SPEC_OPEN_MASK 0x2
482 #define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
483 #define MC_ARB_POP__POP_DEPTH_MASK 0x3c
484 #define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
485 #define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
486 #define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
487 #define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
488 #define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
489 #define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
490 #define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
491 #define MC_ARB_POP__QUICK_STOP_MASK 0x20000
492 #define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
493 #define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
494 #define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
495 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
496 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
497 #define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
498 #define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
499 #define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
500 #define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
501 #define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
502 #define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
503 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
504 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
505 #define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
506 #define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
507 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
508 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
509 #define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
510 #define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
511 #define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
512 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
513 #define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
514 #define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
515 #define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
516 #define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
517 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
518 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
519 #define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
520 #define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
521 #define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
522 #define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
523 #define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
524 #define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
525 #define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
526 #define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
527 #define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
528 #define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
529 #define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
530 #define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
531 #define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
532 #define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
533 #define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
534 #define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
535 #define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
536 #define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
537 #define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
538 #define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
539 #define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
540 #define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
541 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
542 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
543 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
544 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
545 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
546 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
547 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
548 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
549 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
550 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
551 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
552 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
553 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
554 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
555 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
556 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
557 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
558 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
559 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
560 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
561 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
562 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
563 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
564 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
565 #define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
566 #define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
567 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
568 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
569 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
570 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
571 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
572 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
573 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
574 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
575 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
576 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
577 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
578 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
579 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
580 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
581 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
582 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
583 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
584 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
585 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
586 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
587 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
588 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
589 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
590 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
591 #define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
592 #define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
593 #define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
594 #define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
595 #define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
596 #define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
597 #define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
598 #define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
599 #define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
600 #define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
601 #define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
602 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
603 #define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
604 #define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
605 #define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
606 #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
607 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
608 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
609 #define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
610 #define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
611 #define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
612 #define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
613 #define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
614 #define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
615 #define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
616 #define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
617 #define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
618 #define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
619 #define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
620 #define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
621 #define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
622 #define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
623 #define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
624 #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
625 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
626 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
627 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
628 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
629 #define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
630 #define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
631 #define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
632 #define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
633 #define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
634 #define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
635 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
636 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
637 #define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
638 #define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
639 #define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
640 #define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
641 #define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
642 #define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
643 #define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
644 #define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
645 #define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
646 #define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
647 #define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
648 #define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
649 #define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
650 #define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
651 #define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
652 #define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
653 #define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
654 #define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
655 #define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
656 #define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
657 #define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
658 #define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
659 #define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
660 #define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
661 #define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
662 #define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
663 #define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
664 #define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
665 #define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
666 #define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
667 #define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
668 #define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
669 #define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
670 #define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
671 #define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
672 #define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
673 #define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
674 #define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
675 #define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
676 #define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
677 #define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
678 #define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
679 #define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
680 #define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
681 #define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
682 #define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
683 #define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
684 #define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
685 #define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
686 #define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
687 #define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
688 #define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
689 #define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
690 #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
691 #define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
692 #define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
693 #define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
694 #define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
695 #define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
696 #define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
697 #define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
698 #define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
699 #define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
700 #define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
701 #define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
702 #define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
703 #define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
704 #define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
705 #define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
706 #define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
707 #define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
708 #define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
709 #define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
710 #define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
711 #define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
712 #define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
713 #define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
714 #define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
715 #define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
716 #define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
717 #define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
718 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
719 #define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
720 #define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
721 #define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
722 #define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
723 #define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
724 #define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
725 #define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
726 #define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
727 #define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
728 #define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
729 #define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
730 #define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
731 #define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
732 #define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
733 #define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
734 #define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
735 #define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
736 #define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
737 #define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
738 #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
739 #define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
740 #define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
741 #define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
742 #define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
743 #define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
744 #define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
745 #define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
746 #define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
747 #define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
748 #define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
749 #define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
750 #define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
751 #define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
752 #define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
753 #define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
754 #define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
755 #define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
756 #define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
757 #define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
758 #define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
759 #define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
760 #define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
761 #define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
762 #define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
763 #define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
764 #define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
765 #define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
766 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
767 #define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
768 #define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
769 #define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
770 #define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
771 #define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
772 #define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
773 #define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
774 #define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
775 #define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
776 #define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
777 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
778 #define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
779 #define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
780 #define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
781 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
782 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
783 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
784 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
785 #define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
786 #define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
787 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
788 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
789 #define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
790 #define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
791 #define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
792 #define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
793 #define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
794 #define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
795 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
796 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
797 #define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
798 #define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
799 #define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
800 #define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
801 #define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
802 #define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
803 #define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
804 #define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
805 #define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
806 #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
807 #define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
808 #define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
809 #define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
810 #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
811 #define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
812 #define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
813 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
814 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
815 #define MC_ARB_PM_CNTL__RSV_0_MASK 0x30000
816 #define MC_ARB_PM_CNTL__RSV_0__SHIFT 0x10
817 #define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
818 #define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
819 #define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
820 #define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
821 #define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
822 #define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
823 #define MC_ARB_PM_CNTL__RSV_1_MASK 0x1000000
824 #define MC_ARB_PM_CNTL__RSV_1__SHIFT 0x18
825 #define MC_ARB_PM_CNTL__RSV_2_MASK 0x2000000
826 #define MC_ARB_PM_CNTL__RSV_2__SHIFT 0x19
827 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
828 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
829 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
830 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
831 #define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
832 #define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
833 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
834 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
835 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
836 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
837 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
838 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
839 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
840 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
841 #define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
842 #define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
843 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
844 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
845 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
846 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
847 #define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
848 #define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
849 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
850 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
851 #define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
852 #define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
853 #define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
854 #define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
855 #define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
856 #define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
857 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
858 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
859 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
860 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
861 #define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
862 #define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
863 #define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
864 #define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
865 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
866 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
867 #define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
868 #define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
869 #define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
870 #define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
871 #define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
872 #define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
873 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
874 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
875 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
876 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
877 #define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
878 #define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
879 #define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
880 #define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
881 #define MC_ARB_REMREQ__RD_WATER_MASK 0xff
882 #define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
883 #define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
884 #define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
885 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
886 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
887 #define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
888 #define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
889 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
890 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
891 #define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
892 #define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
893 #define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
894 #define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
895 #define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
896 #define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
897 #define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
898 #define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
899 #define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
900 #define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
901 #define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
902 #define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
903 #define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
904 #define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
905 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
906 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
907 #define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
908 #define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
909 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
910 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
911 #define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
912 #define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
913 #define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
914 #define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
915 #define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
916 #define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
917 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
918 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
919 #define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
920 #define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
921 #define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
922 #define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
923 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
924 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
925 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
926 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
927 #define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
928 #define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
929 #define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
930 #define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
931 #define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
932 #define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
933 #define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
934 #define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
935 #define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
936 #define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
937 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
938 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
939 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
940 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
941 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
942 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
943 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
944 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
945 #define MC_ARB_SSM__FORMAT_MASK 0x1f
946 #define MC_ARB_SSM__FORMAT__SHIFT 0x0
947 #define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
948 #define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
949 #define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
950 #define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
951 #define MC_ARB_CG__RSV_0_MASK 0xff0000
952 #define MC_ARB_CG__RSV_0__SHIFT 0x10
953 #define MC_ARB_CG__RSV_1_MASK 0xff000000
954 #define MC_ARB_CG__RSV_1__SHIFT 0x18
955 #define MC_ARB_WCDR__IDLE_ENABLE_MASK 0x1
956 #define MC_ARB_WCDR__IDLE_ENABLE__SHIFT 0x0
957 #define MC_ARB_WCDR__SEQ_IDLE_MASK 0x2
958 #define MC_ARB_WCDR__SEQ_IDLE__SHIFT 0x1
959 #define MC_ARB_WCDR__IDLE_PERIOD_MASK 0x7c
960 #define MC_ARB_WCDR__IDLE_PERIOD__SHIFT 0x2
961 #define MC_ARB_WCDR__IDLE_BURST_MASK 0x1f80
962 #define MC_ARB_WCDR__IDLE_BURST__SHIFT 0x7
963 #define MC_ARB_WCDR__IDLE_BURST_MODE_MASK 0x2000
964 #define MC_ARB_WCDR__IDLE_BURST_MODE__SHIFT 0xd
965 #define MC_ARB_WCDR__IDLE_WAKEUP_MASK 0xc000
966 #define MC_ARB_WCDR__IDLE_WAKEUP__SHIFT 0xe
967 #define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE_MASK 0x10000
968 #define MC_ARB_WCDR__IDLE_DEGLITCH_ENABLE__SHIFT 0x10
969 #define MC_ARB_WCDR__WPRE_ENABLE_MASK 0x20000
970 #define MC_ARB_WCDR__WPRE_ENABLE__SHIFT 0x11
971 #define MC_ARB_WCDR__WPRE_THRESHOLD_MASK 0x3c0000
972 #define MC_ARB_WCDR__WPRE_THRESHOLD__SHIFT 0x12
973 #define MC_ARB_WCDR__WPRE_MAX_BURST_MASK 0x1c00000
974 #define MC_ARB_WCDR__WPRE_MAX_BURST__SHIFT 0x16
975 #define MC_ARB_WCDR__WPRE_INC_READ_MASK 0x2000000
976 #define MC_ARB_WCDR__WPRE_INC_READ__SHIFT 0x19
977 #define MC_ARB_WCDR__WPRE_INC_SKIDIDLE_MASK 0x4000000
978 #define MC_ARB_WCDR__WPRE_INC_SKIDIDLE__SHIFT 0x1a
979 #define MC_ARB_WCDR__WPRE_INC_SEQIDLE_MASK 0x8000000
980 #define MC_ARB_WCDR__WPRE_INC_SEQIDLE__SHIFT 0x1b
981 #define MC_ARB_WCDR__WPRE_TWOPAGE_MASK 0x10000000
982 #define MC_ARB_WCDR__WPRE_TWOPAGE__SHIFT 0x1c
983 #define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
984 #define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
985 #define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
986 #define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
987 #define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
988 #define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
989 #define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
990 #define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
991 #define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
992 #define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
993 #define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
994 #define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
995 #define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
996 #define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
997 #define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
998 #define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
999 #define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
1000 #define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
1001 #define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
1002 #define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
1003 #define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
1004 #define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
1005 #define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
1006 #define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
1007 #define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
1008 #define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
1009 #define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
1010 #define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
1011 #define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
1012 #define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
1013 #define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
1014 #define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
1015 #define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
1016 #define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
1017 #define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
1018 #define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
1019 #define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
1020 #define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
1021 #define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
1022 #define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
1023 #define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
1024 #define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
1025 #define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
1026 #define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
1027 #define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
1028 #define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
1029 #define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
1030 #define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
1031 #define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
1032 #define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
1033 #define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
1034 #define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
1035 #define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
1036 #define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
1037 #define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
1038 #define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
1039 #define MC_ARB_BUSY_STATUS__WCDR0_MASK 0x1000000
1040 #define MC_ARB_BUSY_STATUS__WCDR0__SHIFT 0x18
1041 #define MC_ARB_BUSY_STATUS__WCDR1_MASK 0x2000000
1042 #define MC_ARB_BUSY_STATUS__WCDR1__SHIFT 0x19
1043 #define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
1044 #define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
1045 #define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
1046 #define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
1047 #define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
1048 #define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
1049 #define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
1050 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1051 #define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
1052 #define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
1053 #define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
1054 #define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
1055 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
1056 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
1057 #define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
1058 #define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
1059 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
1060 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
1061 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
1062 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
1063 #define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
1064 #define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
1065 #define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
1066 #define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
1067 #define MC_ARB_BURST_TIME__STATE2_MASK 0x7c00
1068 #define MC_ARB_BURST_TIME__STATE2__SHIFT 0xa
1069 #define MC_ARB_BURST_TIME__STATE3_MASK 0xf8000
1070 #define MC_ARB_BURST_TIME__STATE3__SHIFT 0xf
1071 #define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
1072 #define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
1073 #define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
1074 #define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
1075 #define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
1076 #define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
1077 #define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
1078 #define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
1079 #define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
1080 #define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
1081 #define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
1082 #define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
1083 #define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
1084 #define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
1085 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
1086 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
1087 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
1088 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
1089 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
1090 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
1091 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
1092 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
1093 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
1094 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
1095 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
1096 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
1097 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
1098 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
1099 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
1100 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
1101 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
1102 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
1103 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
1104 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
1105 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
1106 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
1107 #define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
1108 #define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
1109 #define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
1110 #define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
1111 #define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
1112 #define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
1113 #define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
1114 #define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
1115 #define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
1116 #define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
1117 #define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
1118 #define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
1119 #define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
1120 #define MC_CG_CONFIG__INDEX__SHIFT 0x6
1121 #define MC_CITF_CNTL__IGNOREPM_MASK 0x4
1122 #define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
1123 #define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
1124 #define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
1125 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
1126 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
1127 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
1128 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
1129 #define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
1130 #define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
1131 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
1132 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
1133 #define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
1134 #define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
1135 #define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
1136 #define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
1137 #define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
1138 #define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
1139 #define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
1140 #define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
1141 #define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
1142 #define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
1143 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
1144 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
1145 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
1146 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
1147 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
1148 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
1149 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
1150 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
1151 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
1152 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
1153 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
1154 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
1155 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
1156 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
1157 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
1158 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
1159 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
1160 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
1161 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
1162 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
1163 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
1164 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
1165 #define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
1166 #define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
1167 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
1168 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
1169 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
1170 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
1171 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
1172 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
1173 #define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
1174 #define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
1175 #define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
1176 #define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
1177 #define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
1178 #define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
1179 #define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
1180 #define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
1181 #define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
1182 #define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
1183 #define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
1184 #define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
1185 #define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
1186 #define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
1187 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
1188 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
1189 #define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
1190 #define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
1191 #define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
1192 #define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
1193 #define MC_CITF_DAGB_DLY__POS_MASK 0x1f000000
1194 #define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
1195 #define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
1196 #define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
1197 #define MC_RD_GRP_EXT__TC0_MASK 0xf0
1198 #define MC_RD_GRP_EXT__TC0__SHIFT 0x4
1199 #define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
1200 #define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
1201 #define MC_WR_GRP_EXT__TC0_MASK 0xf0
1202 #define MC_WR_GRP_EXT__TC0__SHIFT 0x4
1203 #define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
1204 #define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
1205 #define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
1206 #define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
1207 #define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
1208 #define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
1209 #define MC_WR_TC0__ENABLE_MASK 0x1
1210 #define MC_WR_TC0__ENABLE__SHIFT 0x0
1211 #define MC_WR_TC0__PRESCALE_MASK 0x6
1212 #define MC_WR_TC0__PRESCALE__SHIFT 0x1
1213 #define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
1214 #define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1215 #define MC_WR_TC0__STALL_MODE_MASK 0x30
1216 #define MC_WR_TC0__STALL_MODE__SHIFT 0x4
1217 #define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
1218 #define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
1219 #define MC_WR_TC0__MAX_BURST_MASK 0x780
1220 #define MC_WR_TC0__MAX_BURST__SHIFT 0x7
1221 #define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
1222 #define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
1223 #define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1224 #define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1225 #define MC_WR_TC1__ENABLE_MASK 0x1
1226 #define MC_WR_TC1__ENABLE__SHIFT 0x0
1227 #define MC_WR_TC1__PRESCALE_MASK 0x6
1228 #define MC_WR_TC1__PRESCALE__SHIFT 0x1
1229 #define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
1230 #define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1231 #define MC_WR_TC1__STALL_MODE_MASK 0x30
1232 #define MC_WR_TC1__STALL_MODE__SHIFT 0x4
1233 #define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
1234 #define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
1235 #define MC_WR_TC1__MAX_BURST_MASK 0x780
1236 #define MC_WR_TC1__MAX_BURST__SHIFT 0x7
1237 #define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
1238 #define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
1239 #define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1240 #define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1241 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
1242 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
1243 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
1244 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
1245 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
1246 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1247 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
1248 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1249 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1250 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1251 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
1252 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1253 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
1254 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1255 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
1256 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1257 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1258 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1259 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1260 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1261 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
1262 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
1263 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
1264 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
1265 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
1266 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1267 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
1268 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1269 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1270 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1271 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
1272 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1273 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
1274 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1275 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
1276 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1277 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1278 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1279 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1280 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1281 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
1282 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
1283 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
1284 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
1285 #define MC_RD_CB__ENABLE_MASK 0x1
1286 #define MC_RD_CB__ENABLE__SHIFT 0x0
1287 #define MC_RD_CB__PRESCALE_MASK 0x6
1288 #define MC_RD_CB__PRESCALE__SHIFT 0x1
1289 #define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
1290 #define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1291 #define MC_RD_CB__STALL_MODE_MASK 0x30
1292 #define MC_RD_CB__STALL_MODE__SHIFT 0x4
1293 #define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
1294 #define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
1295 #define MC_RD_CB__MAX_BURST_MASK 0x780
1296 #define MC_RD_CB__MAX_BURST__SHIFT 0x7
1297 #define MC_RD_CB__LAZY_TIMER_MASK 0x7800
1298 #define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
1299 #define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1300 #define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1301 #define MC_RD_DB__ENABLE_MASK 0x1
1302 #define MC_RD_DB__ENABLE__SHIFT 0x0
1303 #define MC_RD_DB__PRESCALE_MASK 0x6
1304 #define MC_RD_DB__PRESCALE__SHIFT 0x1
1305 #define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
1306 #define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1307 #define MC_RD_DB__STALL_MODE_MASK 0x30
1308 #define MC_RD_DB__STALL_MODE__SHIFT 0x4
1309 #define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
1310 #define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
1311 #define MC_RD_DB__MAX_BURST_MASK 0x780
1312 #define MC_RD_DB__MAX_BURST__SHIFT 0x7
1313 #define MC_RD_DB__LAZY_TIMER_MASK 0x7800
1314 #define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
1315 #define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1316 #define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1317 #define MC_RD_TC0__ENABLE_MASK 0x1
1318 #define MC_RD_TC0__ENABLE__SHIFT 0x0
1319 #define MC_RD_TC0__PRESCALE_MASK 0x6
1320 #define MC_RD_TC0__PRESCALE__SHIFT 0x1
1321 #define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
1322 #define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1323 #define MC_RD_TC0__STALL_MODE_MASK 0x30
1324 #define MC_RD_TC0__STALL_MODE__SHIFT 0x4
1325 #define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
1326 #define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
1327 #define MC_RD_TC0__MAX_BURST_MASK 0x780
1328 #define MC_RD_TC0__MAX_BURST__SHIFT 0x7
1329 #define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
1330 #define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
1331 #define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1332 #define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1333 #define MC_RD_TC1__ENABLE_MASK 0x1
1334 #define MC_RD_TC1__ENABLE__SHIFT 0x0
1335 #define MC_RD_TC1__PRESCALE_MASK 0x6
1336 #define MC_RD_TC1__PRESCALE__SHIFT 0x1
1337 #define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
1338 #define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1339 #define MC_RD_TC1__STALL_MODE_MASK 0x30
1340 #define MC_RD_TC1__STALL_MODE__SHIFT 0x4
1341 #define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
1342 #define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
1343 #define MC_RD_TC1__MAX_BURST_MASK 0x780
1344 #define MC_RD_TC1__MAX_BURST__SHIFT 0x7
1345 #define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
1346 #define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
1347 #define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1348 #define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1349 #define MC_RD_HUB__ENABLE_MASK 0x1
1350 #define MC_RD_HUB__ENABLE__SHIFT 0x0
1351 #define MC_RD_HUB__PRESCALE_MASK 0x6
1352 #define MC_RD_HUB__PRESCALE__SHIFT 0x1
1353 #define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
1354 #define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1355 #define MC_RD_HUB__STALL_MODE_MASK 0x30
1356 #define MC_RD_HUB__STALL_MODE__SHIFT 0x4
1357 #define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
1358 #define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
1359 #define MC_RD_HUB__MAX_BURST_MASK 0x780
1360 #define MC_RD_HUB__MAX_BURST__SHIFT 0x7
1361 #define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
1362 #define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
1363 #define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1364 #define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1365 #define MC_WR_CB__ENABLE_MASK 0x1
1366 #define MC_WR_CB__ENABLE__SHIFT 0x0
1367 #define MC_WR_CB__PRESCALE_MASK 0x6
1368 #define MC_WR_CB__PRESCALE__SHIFT 0x1
1369 #define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
1370 #define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1371 #define MC_WR_CB__STALL_MODE_MASK 0x30
1372 #define MC_WR_CB__STALL_MODE__SHIFT 0x4
1373 #define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
1374 #define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
1375 #define MC_WR_CB__MAX_BURST_MASK 0x780
1376 #define MC_WR_CB__MAX_BURST__SHIFT 0x7
1377 #define MC_WR_CB__LAZY_TIMER_MASK 0x7800
1378 #define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
1379 #define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1380 #define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1381 #define MC_WR_DB__ENABLE_MASK 0x1
1382 #define MC_WR_DB__ENABLE__SHIFT 0x0
1383 #define MC_WR_DB__PRESCALE_MASK 0x6
1384 #define MC_WR_DB__PRESCALE__SHIFT 0x1
1385 #define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
1386 #define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1387 #define MC_WR_DB__STALL_MODE_MASK 0x30
1388 #define MC_WR_DB__STALL_MODE__SHIFT 0x4
1389 #define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
1390 #define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
1391 #define MC_WR_DB__MAX_BURST_MASK 0x780
1392 #define MC_WR_DB__MAX_BURST__SHIFT 0x7
1393 #define MC_WR_DB__LAZY_TIMER_MASK 0x7800
1394 #define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
1395 #define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1396 #define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1397 #define MC_WR_HUB__ENABLE_MASK 0x1
1398 #define MC_WR_HUB__ENABLE__SHIFT 0x0
1399 #define MC_WR_HUB__PRESCALE_MASK 0x6
1400 #define MC_WR_HUB__PRESCALE__SHIFT 0x1
1401 #define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
1402 #define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1403 #define MC_WR_HUB__STALL_MODE_MASK 0x30
1404 #define MC_WR_HUB__STALL_MODE__SHIFT 0x4
1405 #define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
1406 #define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
1407 #define MC_WR_HUB__MAX_BURST_MASK 0x780
1408 #define MC_WR_HUB__MAX_BURST__SHIFT 0x7
1409 #define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
1410 #define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
1411 #define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1412 #define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1413 #define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
1414 #define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
1415 #define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
1416 #define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
1417 #define MC_RD_GRP_LCL__CB0_MASK 0xf000
1418 #define MC_RD_GRP_LCL__CB0__SHIFT 0xc
1419 #define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
1420 #define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
1421 #define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
1422 #define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
1423 #define MC_RD_GRP_LCL__DB0_MASK 0xf000000
1424 #define MC_RD_GRP_LCL__DB0__SHIFT 0x18
1425 #define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
1426 #define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
1427 #define MC_WR_GRP_LCL__CB0_MASK 0xf
1428 #define MC_WR_GRP_LCL__CB0__SHIFT 0x0
1429 #define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
1430 #define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
1431 #define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
1432 #define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
1433 #define MC_WR_GRP_LCL__DB0_MASK 0xf000
1434 #define MC_WR_GRP_LCL__DB0__SHIFT 0xc
1435 #define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
1436 #define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
1437 #define MC_WR_GRP_LCL__SX0_MASK 0xf00000
1438 #define MC_WR_GRP_LCL__SX0__SHIFT 0x14
1439 #define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
1440 #define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
1441 #define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
1442 #define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
1443 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x40
1444 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x6
1445 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x80
1446 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x7
1447 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x100
1448 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x8
1449 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x200
1450 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x9
1451 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x400
1452 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0xa
1453 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x800
1454 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0xb
1455 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x1000
1456 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0xc
1457 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x2000
1458 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0xd
1459 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x4000
1460 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0xe
1461 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x8000
1462 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xf
1463 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x10000
1464 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0x10
1465 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x20000
1466 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0x11
1467 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x40000
1468 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0x12
1469 #define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
1470 #define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
1471 #define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
1472 #define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
1473 #define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
1474 #define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
1475 #define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
1476 #define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
1477 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
1478 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
1479 #define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
1480 #define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
1481 #define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
1482 #define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
1483 #define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
1484 #define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
1485 #define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
1486 #define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
1487 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
1488 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
1489 #define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
1490 #define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
1491 #define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
1492 #define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
1493 #define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
1494 #define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
1495 #define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
1496 #define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
1497 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1498 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1499 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
1500 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
1501 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
1502 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
1503 #define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
1504 #define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
1505 #define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
1506 #define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
1507 #define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
1508 #define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
1509 #define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
1510 #define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
1511 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
1512 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
1513 #define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
1514 #define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
1515 #define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
1516 #define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
1517 #define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
1518 #define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
1519 #define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
1520 #define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
1521 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1522 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1523 #define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
1524 #define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
1525 #define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
1526 #define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
1527 #define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
1528 #define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
1529 #define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
1530 #define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
1531 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
1532 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
1533 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
1534 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
1535 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
1536 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
1537 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x4
1538 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x2
1539 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x8
1540 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x3
1541 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x10
1542 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x4
1543 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x20
1544 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x5
1545 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x40
1546 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x6
1547 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x80
1548 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0x7
1549 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x100
1550 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0x8
1551 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x200
1552 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0x9
1553 #define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x400
1554 #define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xa
1555 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x800
1556 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0xb
1557 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x1000
1558 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0xc
1559 #define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x2000
1560 #define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0xd
1561 #define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
1562 #define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
1563 #define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
1564 #define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
1565 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
1566 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
1567 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
1568 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
1569 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
1570 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
1571 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1572 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1573 #define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
1574 #define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
1575 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
1576 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
1577 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
1578 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
1579 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
1580 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
1581 #define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
1582 #define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
1583 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
1584 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
1585 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
1586 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
1587 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
1588 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
1589 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
1590 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
1591 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
1592 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
1593 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
1594 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
1595 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
1596 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
1597 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
1598 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
1599 #define MC_HUB_WDP_BP__ENABLE_MASK 0x1
1600 #define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
1601 #define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
1602 #define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
1603 #define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
1604 #define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
1605 #define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
1606 #define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
1607 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
1608 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1609 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
1610 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1611 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
1612 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1613 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1614 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1615 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
1616 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1617 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
1618 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1619 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
1620 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1621 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
1622 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1623 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
1624 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
1625 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
1626 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
1627 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
1628 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
1629 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
1630 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
1631 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
1632 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
1633 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
1634 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
1635 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
1636 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
1637 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
1638 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
1639 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
1640 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
1641 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
1642 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
1643 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
1644 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
1645 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
1646 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
1647 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
1648 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
1649 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
1650 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
1651 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
1652 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
1653 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
1654 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1655 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
1656 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1657 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
1658 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1659 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1660 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1661 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
1662 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1663 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
1664 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1665 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
1666 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1667 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
1668 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1669 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
1670 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
1671 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
1672 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
1673 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
1674 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
1675 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
1676 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
1677 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
1678 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
1679 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
1680 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
1681 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
1682 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
1683 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
1684 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
1685 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
1686 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
1687 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
1688 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
1689 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
1690 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
1691 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
1692 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
1693 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
1694 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
1695 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
1696 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
1697 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
1698 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
1699 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
1700 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
1701 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
1702 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
1703 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
1704 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
1705 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1706 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1707 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
1708 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
1709 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
1710 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
1711 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
1712 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
1713 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
1714 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
1715 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
1716 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
1717 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
1718 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
1719 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
1720 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
1721 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
1722 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
1723 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
1724 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
1725 #define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
1726 #define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
1727 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
1728 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
1729 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
1730 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
1731 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
1732 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
1733 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
1734 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
1735 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
1736 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
1737 #define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
1738 #define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
1739 #define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
1740 #define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
1741 #define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
1742 #define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
1743 #define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
1744 #define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
1745 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
1746 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
1747 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
1748 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
1749 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1750 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1751 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1752 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1753 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1754 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1755 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1756 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1757 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1758 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1759 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1760 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1761 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1762 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1763 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1764 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1765 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1766 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1767 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1768 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1769 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1770 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1771 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1772 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1773 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1774 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1775 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1776 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1777 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1778 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1779 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1780 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1781 #define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
1782 #define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
1783 #define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
1784 #define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
1785 #define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
1786 #define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
1787 #define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
1788 #define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
1789 #define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
1790 #define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
1791 #define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
1792 #define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
1793 #define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
1794 #define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
1795 #define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
1796 #define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
1797 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
1798 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
1799 #define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
1800 #define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
1801 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
1802 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
1803 #define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
1804 #define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
1805 #define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
1806 #define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
1807 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
1808 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
1809 #define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
1810 #define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
1811 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
1812 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
1813 #define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
1814 #define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
1815 #define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
1816 #define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
1817 #define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
1818 #define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
1819 #define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
1820 #define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
1821 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
1822 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
1823 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
1824 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
1825 #define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
1826 #define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
1827 #define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
1828 #define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
1829 #define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
1830 #define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
1831 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
1832 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
1833 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
1834 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
1835 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
1836 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
1837 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
1838 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
1839 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
1840 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
1841 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
1842 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
1843 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
1844 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
1845 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
1846 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
1847 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
1848 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
1849 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
1850 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
1851 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
1852 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
1853 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
1854 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
1855 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
1856 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
1857 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
1858 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
1859 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
1860 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
1861 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
1862 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
1863 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
1864 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
1865 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
1866 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
1867 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
1868 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
1869 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
1870 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
1871 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ_MASK 0x100000
1872 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_READ__SHIFT 0x14
1873 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE_MASK 0x200000
1874 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_IA_WRITE__SHIFT 0x15
1875 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x400000
1876 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x16
1877 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x800000
1878 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x17
1879 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x1000000
1880 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x18
1881 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x2000000
1882 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x19
1883 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ_MASK 0x4000000
1884 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_READ__SHIFT 0x1a
1885 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE_MASK 0x8000000
1886 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_CP_WRITE__SHIFT 0x1b
1887 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x10000000
1888 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1c
1889 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x20000000
1890 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1d
1891 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x40000000
1892 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1e
1893 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x80000000
1894 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1f
1895 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
1896 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
1897 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
1898 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
1899 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
1900 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
1901 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
1902 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
1903 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
1904 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
1905 #define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
1906 #define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
1907 #define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
1908 #define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
1909 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
1910 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
1911 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
1912 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
1913 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
1914 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
1915 #define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
1916 #define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
1917 #define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
1918 #define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
1919 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
1920 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
1921 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
1922 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
1923 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
1924 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
1925 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
1926 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
1927 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
1928 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
1929 #define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
1930 #define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
1931 #define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
1932 #define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
1933 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
1934 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
1935 #define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
1936 #define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
1937 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
1938 #define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
1939 #define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
1940 #define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
1941 #define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
1942 #define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
1943 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
1944 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
1945 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1946 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1947 #define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
1948 #define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
1949 #define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
1950 #define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
1951 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
1952 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
1953 #define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
1954 #define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
1955 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
1956 #define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
1957 #define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
1958 #define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
1959 #define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
1960 #define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
1961 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
1962 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
1963 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1964 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1965 #define MC_HUB_RDREQ_IA0__ENABLE_MASK 0x1
1966 #define MC_HUB_RDREQ_IA0__ENABLE__SHIFT 0x0
1967 #define MC_HUB_RDREQ_IA0__PRESCALE_MASK 0x6
1968 #define MC_HUB_RDREQ_IA0__PRESCALE__SHIFT 0x1
1969 #define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT_MASK 0x8
1970 #define MC_HUB_RDREQ_IA0__BLACKOUT_EXEMPT__SHIFT 0x3
1971 #define MC_HUB_RDREQ_IA0__STALL_MODE_MASK 0x30
1972 #define MC_HUB_RDREQ_IA0__STALL_MODE__SHIFT 0x4
1973 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_MASK 0x40
1974 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE__SHIFT 0x6
1975 #define MC_HUB_RDREQ_IA0__MAXBURST_MASK 0x780
1976 #define MC_HUB_RDREQ_IA0__MAXBURST__SHIFT 0x7
1977 #define MC_HUB_RDREQ_IA0__LAZY_TIMER_MASK 0x7800
1978 #define MC_HUB_RDREQ_IA0__LAZY_TIMER__SHIFT 0xb
1979 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM_MASK 0x8000
1980 #define MC_HUB_RDREQ_IA0__STALL_OVERRIDE_WTM__SHIFT 0xf
1981 #define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
1982 #define MC_HUB_RDREQ_IA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
1983 #define MC_HUB_RDREQ_IA1__ENABLE_MASK 0x1
1984 #define MC_HUB_RDREQ_IA1__ENABLE__SHIFT 0x0
1985 #define MC_HUB_RDREQ_IA1__PRESCALE_MASK 0x6
1986 #define MC_HUB_RDREQ_IA1__PRESCALE__SHIFT 0x1
1987 #define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT_MASK 0x8
1988 #define MC_HUB_RDREQ_IA1__BLACKOUT_EXEMPT__SHIFT 0x3
1989 #define MC_HUB_RDREQ_IA1__STALL_MODE_MASK 0x30
1990 #define MC_HUB_RDREQ_IA1__STALL_MODE__SHIFT 0x4
1991 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_MASK 0x40
1992 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE__SHIFT 0x6
1993 #define MC_HUB_RDREQ_IA1__MAXBURST_MASK 0x780
1994 #define MC_HUB_RDREQ_IA1__MAXBURST__SHIFT 0x7
1995 #define MC_HUB_RDREQ_IA1__LAZY_TIMER_MASK 0x7800
1996 #define MC_HUB_RDREQ_IA1__LAZY_TIMER__SHIFT 0xb
1997 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM_MASK 0x8000
1998 #define MC_HUB_RDREQ_IA1__STALL_OVERRIDE_WTM__SHIFT 0xf
1999 #define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2000 #define MC_HUB_RDREQ_IA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2001 #define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
2002 #define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
2003 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2004 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2005 #define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
2006 #define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
2007 #define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
2008 #define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
2009 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
2010 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
2011 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
2012 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
2013 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
2014 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
2015 #define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD_MASK 0xfe000000
2016 #define MC_HUB_RDREQ_MCDW__STALL_THRESHOLD__SHIFT 0x19
2017 #define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
2018 #define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
2019 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2020 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2021 #define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
2022 #define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
2023 #define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
2024 #define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
2025 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
2026 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
2027 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
2028 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
2029 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
2030 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
2031 #define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD_MASK 0xfe000000
2032 #define MC_HUB_RDREQ_MCDX__STALL_THRESHOLD__SHIFT 0x19
2033 #define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
2034 #define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
2035 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2036 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2037 #define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
2038 #define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
2039 #define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
2040 #define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
2041 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
2042 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
2043 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
2044 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
2045 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
2046 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
2047 #define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD_MASK 0xfe000000
2048 #define MC_HUB_RDREQ_MCDY__STALL_THRESHOLD__SHIFT 0x19
2049 #define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
2050 #define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
2051 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2052 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2053 #define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
2054 #define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
2055 #define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
2056 #define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
2057 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
2058 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
2059 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
2060 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
2061 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
2062 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
2063 #define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD_MASK 0xfe000000
2064 #define MC_HUB_RDREQ_MCDZ__STALL_THRESHOLD__SHIFT 0x19
2065 #define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
2066 #define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
2067 #define MC_HUB_RDREQ_SIP__DUMMY_MASK 0x80
2068 #define MC_HUB_RDREQ_SIP__DUMMY__SHIFT 0x7
2069 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
2070 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
2071 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
2072 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
2073 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
2074 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
2075 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
2076 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
2077 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
2078 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
2079 #define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
2080 #define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
2081 #define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
2082 #define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
2083 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
2084 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2085 #define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
2086 #define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
2087 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
2088 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
2089 #define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
2090 #define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
2091 #define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
2092 #define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
2093 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2094 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2095 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2096 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2097 #define MC_HUB_RDREQ_CPG__ENABLE_MASK 0x1
2098 #define MC_HUB_RDREQ_CPG__ENABLE__SHIFT 0x0
2099 #define MC_HUB_RDREQ_CPG__PRESCALE_MASK 0x6
2100 #define MC_HUB_RDREQ_CPG__PRESCALE__SHIFT 0x1
2101 #define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT_MASK 0x8
2102 #define MC_HUB_RDREQ_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
2103 #define MC_HUB_RDREQ_CPG__STALL_MODE_MASK 0x30
2104 #define MC_HUB_RDREQ_CPG__STALL_MODE__SHIFT 0x4
2105 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_MASK 0x40
2106 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE__SHIFT 0x6
2107 #define MC_HUB_RDREQ_CPG__MAXBURST_MASK 0x780
2108 #define MC_HUB_RDREQ_CPG__MAXBURST__SHIFT 0x7
2109 #define MC_HUB_RDREQ_CPG__LAZY_TIMER_MASK 0x7800
2110 #define MC_HUB_RDREQ_CPG__LAZY_TIMER__SHIFT 0xb
2111 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
2112 #define MC_HUB_RDREQ_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2113 #define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2114 #define MC_HUB_RDREQ_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2115 #define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
2116 #define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
2117 #define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
2118 #define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
2119 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2120 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2121 #define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
2122 #define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
2123 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
2124 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2125 #define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
2126 #define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
2127 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
2128 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
2129 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2130 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2131 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2132 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2133 #define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
2134 #define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
2135 #define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
2136 #define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
2137 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
2138 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2139 #define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
2140 #define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
2141 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
2142 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
2143 #define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
2144 #define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
2145 #define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
2146 #define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
2147 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2148 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2149 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2150 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2151 #define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
2152 #define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
2153 #define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
2154 #define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
2155 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2156 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2157 #define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
2158 #define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
2159 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
2160 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2161 #define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
2162 #define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
2163 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
2164 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
2165 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2166 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2167 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2168 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2169 #define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
2170 #define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
2171 #define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
2172 #define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
2173 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
2174 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2175 #define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
2176 #define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
2177 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
2178 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
2179 #define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
2180 #define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
2181 #define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
2182 #define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
2183 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2184 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2185 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2186 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2187 #define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
2188 #define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
2189 #define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
2190 #define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
2191 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
2192 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2193 #define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
2194 #define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
2195 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
2196 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
2197 #define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
2198 #define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
2199 #define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
2200 #define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
2201 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2202 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2203 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2204 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2205 #define MC_HUB_RDREQ_VCE__ENABLE_MASK 0x1
2206 #define MC_HUB_RDREQ_VCE__ENABLE__SHIFT 0x0
2207 #define MC_HUB_RDREQ_VCE__PRESCALE_MASK 0x6
2208 #define MC_HUB_RDREQ_VCE__PRESCALE__SHIFT 0x1
2209 #define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT_MASK 0x8
2210 #define MC_HUB_RDREQ_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2211 #define MC_HUB_RDREQ_VCE__STALL_MODE_MASK 0x30
2212 #define MC_HUB_RDREQ_VCE__STALL_MODE__SHIFT 0x4
2213 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_MASK 0x40
2214 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE__SHIFT 0x6
2215 #define MC_HUB_RDREQ_VCE__MAXBURST_MASK 0x780
2216 #define MC_HUB_RDREQ_VCE__MAXBURST__SHIFT 0x7
2217 #define MC_HUB_RDREQ_VCE__LAZY_TIMER_MASK 0x7800
2218 #define MC_HUB_RDREQ_VCE__LAZY_TIMER__SHIFT 0xb
2219 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2220 #define MC_HUB_RDREQ_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2221 #define MC_HUB_RDREQ_VCE__VM_BYPASS_MASK 0x10000
2222 #define MC_HUB_RDREQ_VCE__VM_BYPASS__SHIFT 0x10
2223 #define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2224 #define MC_HUB_RDREQ_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2225 #define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
2226 #define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
2227 #define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
2228 #define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
2229 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
2230 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2231 #define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
2232 #define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
2233 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
2234 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
2235 #define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
2236 #define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
2237 #define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
2238 #define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
2239 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2240 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2241 #define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
2242 #define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
2243 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2244 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2245 #define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
2246 #define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
2247 #define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
2248 #define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
2249 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
2250 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2251 #define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
2252 #define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
2253 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
2254 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
2255 #define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
2256 #define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
2257 #define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
2258 #define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
2259 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2260 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2261 #define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
2262 #define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
2263 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2264 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2265 #define MC_HUB_RDREQ_IA__ENABLE_MASK 0x1
2266 #define MC_HUB_RDREQ_IA__ENABLE__SHIFT 0x0
2267 #define MC_HUB_RDREQ_IA__PRESCALE_MASK 0x6
2268 #define MC_HUB_RDREQ_IA__PRESCALE__SHIFT 0x1
2269 #define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT_MASK 0x8
2270 #define MC_HUB_RDREQ_IA__BLACKOUT_EXEMPT__SHIFT 0x3
2271 #define MC_HUB_RDREQ_IA__STALL_MODE_MASK 0x30
2272 #define MC_HUB_RDREQ_IA__STALL_MODE__SHIFT 0x4
2273 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_MASK 0x40
2274 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE__SHIFT 0x6
2275 #define MC_HUB_RDREQ_IA__MAXBURST_MASK 0x780
2276 #define MC_HUB_RDREQ_IA__MAXBURST__SHIFT 0x7
2277 #define MC_HUB_RDREQ_IA__LAZY_TIMER_MASK 0x7800
2278 #define MC_HUB_RDREQ_IA__LAZY_TIMER__SHIFT 0xb
2279 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM_MASK 0x8000
2280 #define MC_HUB_RDREQ_IA__STALL_OVERRIDE_WTM__SHIFT 0xf
2281 #define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2282 #define MC_HUB_RDREQ_IA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2283 #define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
2284 #define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
2285 #define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
2286 #define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
2287 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
2288 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
2289 #define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
2290 #define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
2291 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
2292 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
2293 #define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
2294 #define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
2295 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
2296 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
2297 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
2298 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2299 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2300 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2301 #define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
2302 #define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
2303 #define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
2304 #define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
2305 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2306 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2307 #define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
2308 #define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
2309 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
2310 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
2311 #define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
2312 #define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
2313 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
2314 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
2315 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2316 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2317 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2318 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2319 #define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
2320 #define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
2321 #define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
2322 #define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
2323 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
2324 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
2325 #define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
2326 #define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
2327 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
2328 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
2329 #define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
2330 #define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
2331 #define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
2332 #define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
2333 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
2334 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2335 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2336 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2337 #define MC_HUB_RDREQ_VCEU__ENABLE_MASK 0x1
2338 #define MC_HUB_RDREQ_VCEU__ENABLE__SHIFT 0x0
2339 #define MC_HUB_RDREQ_VCEU__PRESCALE_MASK 0x6
2340 #define MC_HUB_RDREQ_VCEU__PRESCALE__SHIFT 0x1
2341 #define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2342 #define MC_HUB_RDREQ_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2343 #define MC_HUB_RDREQ_VCEU__STALL_MODE_MASK 0x30
2344 #define MC_HUB_RDREQ_VCEU__STALL_MODE__SHIFT 0x4
2345 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_MASK 0x40
2346 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE__SHIFT 0x6
2347 #define MC_HUB_RDREQ_VCEU__MAXBURST_MASK 0x780
2348 #define MC_HUB_RDREQ_VCEU__MAXBURST__SHIFT 0x7
2349 #define MC_HUB_RDREQ_VCEU__LAZY_TIMER_MASK 0x7800
2350 #define MC_HUB_RDREQ_VCEU__LAZY_TIMER__SHIFT 0xb
2351 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2352 #define MC_HUB_RDREQ_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2353 #define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2354 #define MC_HUB_RDREQ_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2355 #define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
2356 #define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
2357 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2358 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2359 #define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
2360 #define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
2361 #define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
2362 #define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
2363 #define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
2364 #define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
2365 #define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
2366 #define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
2367 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
2368 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
2369 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
2370 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
2371 #define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
2372 #define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
2373 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2374 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2375 #define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
2376 #define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
2377 #define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
2378 #define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
2379 #define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
2380 #define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
2381 #define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
2382 #define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
2383 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
2384 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
2385 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
2386 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
2387 #define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
2388 #define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
2389 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2390 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2391 #define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
2392 #define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
2393 #define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
2394 #define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
2395 #define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
2396 #define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
2397 #define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
2398 #define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
2399 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
2400 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
2401 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
2402 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
2403 #define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
2404 #define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
2405 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2406 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2407 #define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
2408 #define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
2409 #define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
2410 #define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
2411 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
2412 #define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
2413 #define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
2414 #define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
2415 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
2416 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
2417 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
2418 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
2419 #define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
2420 #define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
2421 #define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
2422 #define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
2423 #define MC_HUB_WDP_CPG__ENABLE_MASK 0x1
2424 #define MC_HUB_WDP_CPG__ENABLE__SHIFT 0x0
2425 #define MC_HUB_WDP_CPG__PRESCALE_MASK 0x6
2426 #define MC_HUB_WDP_CPG__PRESCALE__SHIFT 0x1
2427 #define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT_MASK 0x8
2428 #define MC_HUB_WDP_CPG__BLACKOUT_EXEMPT__SHIFT 0x3
2429 #define MC_HUB_WDP_CPG__STALL_MODE_MASK 0x30
2430 #define MC_HUB_WDP_CPG__STALL_MODE__SHIFT 0x4
2431 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_MASK 0x40
2432 #define MC_HUB_WDP_CPG__STALL_OVERRIDE__SHIFT 0x6
2433 #define MC_HUB_WDP_CPG__MAXBURST_MASK 0x780
2434 #define MC_HUB_WDP_CPG__MAXBURST__SHIFT 0x7
2435 #define MC_HUB_WDP_CPG__LAZY_TIMER_MASK 0x7800
2436 #define MC_HUB_WDP_CPG__LAZY_TIMER__SHIFT 0xb
2437 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM_MASK 0x8000
2438 #define MC_HUB_WDP_CPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2439 #define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2440 #define MC_HUB_WDP_CPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2441 #define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
2442 #define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
2443 #define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
2444 #define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
2445 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2446 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2447 #define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
2448 #define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
2449 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
2450 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2451 #define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
2452 #define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
2453 #define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
2454 #define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
2455 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2456 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2457 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2458 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2459 #define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
2460 #define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
2461 #define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
2462 #define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
2463 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
2464 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
2465 #define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
2466 #define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
2467 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
2468 #define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
2469 #define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
2470 #define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
2471 #define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
2472 #define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
2473 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
2474 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
2475 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2476 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2477 #define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
2478 #define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
2479 #define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
2480 #define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
2481 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2482 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2483 #define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
2484 #define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
2485 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
2486 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
2487 #define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
2488 #define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
2489 #define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
2490 #define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
2491 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2492 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2493 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2494 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2495 #define MC_HUB_WDP_VCE__ENABLE_MASK 0x1
2496 #define MC_HUB_WDP_VCE__ENABLE__SHIFT 0x0
2497 #define MC_HUB_WDP_VCE__PRESCALE_MASK 0x6
2498 #define MC_HUB_WDP_VCE__PRESCALE__SHIFT 0x1
2499 #define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT_MASK 0x8
2500 #define MC_HUB_WDP_VCE__BLACKOUT_EXEMPT__SHIFT 0x3
2501 #define MC_HUB_WDP_VCE__STALL_MODE_MASK 0x30
2502 #define MC_HUB_WDP_VCE__STALL_MODE__SHIFT 0x4
2503 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_MASK 0x40
2504 #define MC_HUB_WDP_VCE__STALL_OVERRIDE__SHIFT 0x6
2505 #define MC_HUB_WDP_VCE__MAXBURST_MASK 0x780
2506 #define MC_HUB_WDP_VCE__MAXBURST__SHIFT 0x7
2507 #define MC_HUB_WDP_VCE__LAZY_TIMER_MASK 0x7800
2508 #define MC_HUB_WDP_VCE__LAZY_TIMER__SHIFT 0xb
2509 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM_MASK 0x8000
2510 #define MC_HUB_WDP_VCE__STALL_OVERRIDE_WTM__SHIFT 0xf
2511 #define MC_HUB_WDP_VCE__VM_BYPASS_MASK 0x10000
2512 #define MC_HUB_WDP_VCE__VM_BYPASS__SHIFT 0x10
2513 #define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2514 #define MC_HUB_WDP_VCE__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2515 #define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
2516 #define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
2517 #define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
2518 #define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
2519 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
2520 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
2521 #define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
2522 #define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
2523 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
2524 #define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
2525 #define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
2526 #define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
2527 #define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
2528 #define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
2529 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
2530 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2531 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2532 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2533 #define MC_HUB_WDP_IH__ENABLE_MASK 0x1
2534 #define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
2535 #define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
2536 #define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
2537 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
2538 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
2539 #define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
2540 #define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
2541 #define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
2542 #define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
2543 #define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
2544 #define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
2545 #define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
2546 #define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
2547 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
2548 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
2549 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2550 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2551 #define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
2552 #define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
2553 #define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
2554 #define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
2555 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
2556 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2557 #define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
2558 #define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
2559 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
2560 #define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
2561 #define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
2562 #define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
2563 #define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
2564 #define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
2565 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2566 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2567 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2568 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2569 #define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
2570 #define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
2571 #define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
2572 #define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
2573 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
2574 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2575 #define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
2576 #define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
2577 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
2578 #define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
2579 #define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
2580 #define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
2581 #define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
2582 #define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
2583 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2584 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2585 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2586 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2587 #define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
2588 #define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
2589 #define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
2590 #define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
2591 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
2592 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2593 #define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
2594 #define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
2595 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
2596 #define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
2597 #define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
2598 #define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
2599 #define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
2600 #define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
2601 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2602 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2603 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2604 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2605 #define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
2606 #define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
2607 #define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
2608 #define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
2609 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
2610 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
2611 #define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
2612 #define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
2613 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
2614 #define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
2615 #define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
2616 #define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
2617 #define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
2618 #define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
2619 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
2620 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
2621 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2622 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2623 #define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
2624 #define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
2625 #define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
2626 #define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
2627 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
2628 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2629 #define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
2630 #define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
2631 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
2632 #define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
2633 #define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
2634 #define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
2635 #define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
2636 #define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
2637 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2638 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2639 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2640 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2641 #define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
2642 #define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
2643 #define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
2644 #define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
2645 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
2646 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2647 #define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
2648 #define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
2649 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
2650 #define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
2651 #define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
2652 #define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
2653 #define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
2654 #define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
2655 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2656 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2657 #define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
2658 #define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
2659 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2660 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2661 #define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
2662 #define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
2663 #define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
2664 #define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
2665 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
2666 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2667 #define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
2668 #define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
2669 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
2670 #define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
2671 #define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
2672 #define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
2673 #define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
2674 #define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
2675 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2676 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2677 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2678 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2679 #define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
2680 #define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
2681 #define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
2682 #define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
2683 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2684 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2685 #define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
2686 #define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
2687 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
2688 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2689 #define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
2690 #define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
2691 #define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
2692 #define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
2693 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2694 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2695 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2696 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2697 #define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
2698 #define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
2699 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
2700 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
2701 #define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
2702 #define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
2703 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
2704 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
2705 #define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
2706 #define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
2707 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
2708 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
2709 #define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
2710 #define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
2711 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
2712 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
2713 #define MC_HUB_WDP_VCEU__ENABLE_MASK 0x1
2714 #define MC_HUB_WDP_VCEU__ENABLE__SHIFT 0x0
2715 #define MC_HUB_WDP_VCEU__PRESCALE_MASK 0x6
2716 #define MC_HUB_WDP_VCEU__PRESCALE__SHIFT 0x1
2717 #define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT_MASK 0x8
2718 #define MC_HUB_WDP_VCEU__BLACKOUT_EXEMPT__SHIFT 0x3
2719 #define MC_HUB_WDP_VCEU__STALL_MODE_MASK 0x30
2720 #define MC_HUB_WDP_VCEU__STALL_MODE__SHIFT 0x4
2721 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_MASK 0x40
2722 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE__SHIFT 0x6
2723 #define MC_HUB_WDP_VCEU__MAXBURST_MASK 0x780
2724 #define MC_HUB_WDP_VCEU__MAXBURST__SHIFT 0x7
2725 #define MC_HUB_WDP_VCEU__LAZY_TIMER_MASK 0x7800
2726 #define MC_HUB_WDP_VCEU__LAZY_TIMER__SHIFT 0xb
2727 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM_MASK 0x8000
2728 #define MC_HUB_WDP_VCEU__STALL_OVERRIDE_WTM__SHIFT 0xf
2729 #define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2730 #define MC_HUB_WDP_VCEU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2731 #define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
2732 #define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
2733 #define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
2734 #define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
2735 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2736 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2737 #define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
2738 #define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
2739 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
2740 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2741 #define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
2742 #define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
2743 #define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
2744 #define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
2745 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2746 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2747 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2748 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2749 #define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
2750 #define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
2751 #define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
2752 #define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
2753 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
2754 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
2755 #define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
2756 #define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
2757 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
2758 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
2759 #define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
2760 #define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
2761 #define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
2762 #define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
2763 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
2764 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
2765 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2766 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2767 #define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
2768 #define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
2769 #define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
2770 #define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
2771 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2772 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2773 #define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
2774 #define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
2775 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
2776 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2777 #define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
2778 #define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
2779 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
2780 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
2781 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2782 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2783 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2784 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2785 #define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
2786 #define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
2787 #define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
2788 #define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
2789 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2790 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2791 #define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
2792 #define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
2793 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
2794 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
2795 #define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
2796 #define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
2797 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
2798 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
2799 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2800 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2801 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2802 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2803 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
2804 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2805 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2806 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2807 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2808 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
2809 #define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
2810 #define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
2811 #define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
2812 #define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
2813 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2814 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2815 #define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
2816 #define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
2817 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
2818 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
2819 #define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
2820 #define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
2821 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
2822 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
2823 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2824 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2825 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2826 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2827 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
2828 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2829 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2830 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2831 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2832 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
2833 #define MC_HUB_RDREQ_SAM__ENABLE_MASK 0x1
2834 #define MC_HUB_RDREQ_SAM__ENABLE__SHIFT 0x0
2835 #define MC_HUB_RDREQ_SAM__PRESCALE_MASK 0x6
2836 #define MC_HUB_RDREQ_SAM__PRESCALE__SHIFT 0x1
2837 #define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT_MASK 0x8
2838 #define MC_HUB_RDREQ_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2839 #define MC_HUB_RDREQ_SAM__STALL_MODE_MASK 0x30
2840 #define MC_HUB_RDREQ_SAM__STALL_MODE__SHIFT 0x4
2841 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_MASK 0x40
2842 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE__SHIFT 0x6
2843 #define MC_HUB_RDREQ_SAM__MAXBURST_MASK 0x780
2844 #define MC_HUB_RDREQ_SAM__MAXBURST__SHIFT 0x7
2845 #define MC_HUB_RDREQ_SAM__LAZY_TIMER_MASK 0x7800
2846 #define MC_HUB_RDREQ_SAM__LAZY_TIMER__SHIFT 0xb
2847 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2848 #define MC_HUB_RDREQ_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2849 #define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2850 #define MC_HUB_RDREQ_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2851 #define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
2852 #define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
2853 #define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
2854 #define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
2855 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
2856 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
2857 #define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
2858 #define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
2859 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
2860 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
2861 #define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
2862 #define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
2863 #define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
2864 #define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
2865 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
2866 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
2867 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2868 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2869 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x20000
2870 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x11
2871 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
2872 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
2873 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x1f80000
2874 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x13
2875 #define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
2876 #define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
2877 #define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
2878 #define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
2879 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
2880 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
2881 #define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
2882 #define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
2883 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
2884 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
2885 #define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
2886 #define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
2887 #define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
2888 #define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
2889 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
2890 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
2891 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2892 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2893 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x20000
2894 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x11
2895 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
2896 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
2897 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x1f80000
2898 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x13
2899 #define MC_HUB_WDP_SAM__ENABLE_MASK 0x1
2900 #define MC_HUB_WDP_SAM__ENABLE__SHIFT 0x0
2901 #define MC_HUB_WDP_SAM__PRESCALE_MASK 0x6
2902 #define MC_HUB_WDP_SAM__PRESCALE__SHIFT 0x1
2903 #define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT_MASK 0x8
2904 #define MC_HUB_WDP_SAM__BLACKOUT_EXEMPT__SHIFT 0x3
2905 #define MC_HUB_WDP_SAM__STALL_MODE_MASK 0x30
2906 #define MC_HUB_WDP_SAM__STALL_MODE__SHIFT 0x4
2907 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_MASK 0x40
2908 #define MC_HUB_WDP_SAM__STALL_OVERRIDE__SHIFT 0x6
2909 #define MC_HUB_WDP_SAM__MAXBURST_MASK 0x780
2910 #define MC_HUB_WDP_SAM__MAXBURST__SHIFT 0x7
2911 #define MC_HUB_WDP_SAM__LAZY_TIMER_MASK 0x7800
2912 #define MC_HUB_WDP_SAM__LAZY_TIMER__SHIFT 0xb
2913 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM_MASK 0x8000
2914 #define MC_HUB_WDP_SAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2915 #define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2916 #define MC_HUB_WDP_SAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2917 #define MC_HUB_RDREQ_CPC__ENABLE_MASK 0x1
2918 #define MC_HUB_RDREQ_CPC__ENABLE__SHIFT 0x0
2919 #define MC_HUB_RDREQ_CPC__PRESCALE_MASK 0x6
2920 #define MC_HUB_RDREQ_CPC__PRESCALE__SHIFT 0x1
2921 #define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT_MASK 0x8
2922 #define MC_HUB_RDREQ_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2923 #define MC_HUB_RDREQ_CPC__STALL_MODE_MASK 0x30
2924 #define MC_HUB_RDREQ_CPC__STALL_MODE__SHIFT 0x4
2925 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_MASK 0x40
2926 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE__SHIFT 0x6
2927 #define MC_HUB_RDREQ_CPC__MAXBURST_MASK 0x780
2928 #define MC_HUB_RDREQ_CPC__MAXBURST__SHIFT 0x7
2929 #define MC_HUB_RDREQ_CPC__LAZY_TIMER_MASK 0x7800
2930 #define MC_HUB_RDREQ_CPC__LAZY_TIMER__SHIFT 0xb
2931 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2932 #define MC_HUB_RDREQ_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2933 #define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2934 #define MC_HUB_RDREQ_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2935 #define MC_HUB_RDREQ_CPF__ENABLE_MASK 0x1
2936 #define MC_HUB_RDREQ_CPF__ENABLE__SHIFT 0x0
2937 #define MC_HUB_RDREQ_CPF__PRESCALE_MASK 0x6
2938 #define MC_HUB_RDREQ_CPF__PRESCALE__SHIFT 0x1
2939 #define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT_MASK 0x8
2940 #define MC_HUB_RDREQ_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2941 #define MC_HUB_RDREQ_CPF__STALL_MODE_MASK 0x30
2942 #define MC_HUB_RDREQ_CPF__STALL_MODE__SHIFT 0x4
2943 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_MASK 0x40
2944 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE__SHIFT 0x6
2945 #define MC_HUB_RDREQ_CPF__MAXBURST_MASK 0x780
2946 #define MC_HUB_RDREQ_CPF__MAXBURST__SHIFT 0x7
2947 #define MC_HUB_RDREQ_CPF__LAZY_TIMER_MASK 0x7800
2948 #define MC_HUB_RDREQ_CPF__LAZY_TIMER__SHIFT 0xb
2949 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2950 #define MC_HUB_RDREQ_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2951 #define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2952 #define MC_HUB_RDREQ_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2953 #define MC_HUB_WDP_CPC__ENABLE_MASK 0x1
2954 #define MC_HUB_WDP_CPC__ENABLE__SHIFT 0x0
2955 #define MC_HUB_WDP_CPC__PRESCALE_MASK 0x6
2956 #define MC_HUB_WDP_CPC__PRESCALE__SHIFT 0x1
2957 #define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT_MASK 0x8
2958 #define MC_HUB_WDP_CPC__BLACKOUT_EXEMPT__SHIFT 0x3
2959 #define MC_HUB_WDP_CPC__STALL_MODE_MASK 0x30
2960 #define MC_HUB_WDP_CPC__STALL_MODE__SHIFT 0x4
2961 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_MASK 0x40
2962 #define MC_HUB_WDP_CPC__STALL_OVERRIDE__SHIFT 0x6
2963 #define MC_HUB_WDP_CPC__MAXBURST_MASK 0x780
2964 #define MC_HUB_WDP_CPC__MAXBURST__SHIFT 0x7
2965 #define MC_HUB_WDP_CPC__LAZY_TIMER_MASK 0x7800
2966 #define MC_HUB_WDP_CPC__LAZY_TIMER__SHIFT 0xb
2967 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM_MASK 0x8000
2968 #define MC_HUB_WDP_CPC__STALL_OVERRIDE_WTM__SHIFT 0xf
2969 #define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2970 #define MC_HUB_WDP_CPC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2971 #define MC_HUB_WDP_CPF__ENABLE_MASK 0x1
2972 #define MC_HUB_WDP_CPF__ENABLE__SHIFT 0x0
2973 #define MC_HUB_WDP_CPF__PRESCALE_MASK 0x6
2974 #define MC_HUB_WDP_CPF__PRESCALE__SHIFT 0x1
2975 #define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT_MASK 0x8
2976 #define MC_HUB_WDP_CPF__BLACKOUT_EXEMPT__SHIFT 0x3
2977 #define MC_HUB_WDP_CPF__STALL_MODE_MASK 0x30
2978 #define MC_HUB_WDP_CPF__STALL_MODE__SHIFT 0x4
2979 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_MASK 0x40
2980 #define MC_HUB_WDP_CPF__STALL_OVERRIDE__SHIFT 0x6
2981 #define MC_HUB_WDP_CPF__MAXBURST_MASK 0x780
2982 #define MC_HUB_WDP_CPF__MAXBURST__SHIFT 0x7
2983 #define MC_HUB_WDP_CPF__LAZY_TIMER_MASK 0x7800
2984 #define MC_HUB_WDP_CPF__LAZY_TIMER__SHIFT 0xb
2985 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM_MASK 0x8000
2986 #define MC_HUB_WDP_CPF__STALL_OVERRIDE_WTM__SHIFT 0xf
2987 #define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2988 #define MC_HUB_WDP_CPF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2989 #define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
2990 #define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
2991 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
2992 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
2993 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
2994 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
2995 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
2996 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
2997 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
2998 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
2999 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
3000 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
3001 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
3002 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3003 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3004 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3005 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3006 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3007 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3008 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3009 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3010 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3011 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3012 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3013 #define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
3014 #define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
3015 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
3016 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
3017 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3018 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3019 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
3020 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
3021 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3022 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3023 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
3024 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
3025 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
3026 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3027 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3028 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3029 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3030 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3031 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3032 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3033 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3034 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3035 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3036 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3037 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
3038 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
3039 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
3040 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
3041 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3042 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3043 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
3044 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
3045 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3046 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3047 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
3048 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
3049 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3050 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3051 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3052 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3053 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3054 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3055 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3056 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3057 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3058 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3059 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3060 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3061 #define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
3062 #define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
3063 #define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
3064 #define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
3065 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3066 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3067 #define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
3068 #define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
3069 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3070 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3071 #define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
3072 #define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
3073 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
3074 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3075 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3076 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3077 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3078 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3079 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3080 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3081 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3082 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3083 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3084 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3085 #define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
3086 #define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
3087 #define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
3088 #define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
3089 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
3090 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
3091 #define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
3092 #define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
3093 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
3094 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
3095 #define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
3096 #define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
3097 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
3098 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
3099 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
3100 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
3101 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3102 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3103 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x20000
3104 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x11
3105 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x40000
3106 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x12
3107 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x1f80000
3108 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x13
3109 #define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
3110 #define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
3111 #define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
3112 #define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
3113 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3114 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3115 #define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
3116 #define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
3117 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3118 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3119 #define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
3120 #define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
3121 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
3122 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3123 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3124 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3125 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3126 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3127 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3128 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3129 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3130 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3131 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3132 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3133 #define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
3134 #define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
3135 #define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
3136 #define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
3137 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3138 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3139 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
3140 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
3141 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3142 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3143 #define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
3144 #define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
3145 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3146 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3147 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3148 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3149 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3150 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3151 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3152 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3153 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3154 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3155 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3156 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3157 #define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
3158 #define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
3159 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3160 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3161 #define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
3162 #define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
3163 #define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
3164 #define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
3165 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
3166 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
3167 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
3168 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
3169 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
3170 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
3171 #define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD_MASK 0xfe000000
3172 #define MC_HUB_RDREQ_MCDS__STALL_THRESHOLD__SHIFT 0x19
3173 #define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
3174 #define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
3175 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3176 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3177 #define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
3178 #define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
3179 #define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
3180 #define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
3181 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
3182 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
3183 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
3184 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
3185 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
3186 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
3187 #define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD_MASK 0xfe000000
3188 #define MC_HUB_RDREQ_MCDT__STALL_THRESHOLD__SHIFT 0x19
3189 #define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
3190 #define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
3191 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3192 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3193 #define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
3194 #define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
3195 #define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
3196 #define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
3197 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
3198 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
3199 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
3200 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
3201 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
3202 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
3203 #define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD_MASK 0xfe000000
3204 #define MC_HUB_RDREQ_MCDU__STALL_THRESHOLD__SHIFT 0x19
3205 #define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
3206 #define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
3207 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3208 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3209 #define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
3210 #define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
3211 #define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
3212 #define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
3213 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
3214 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
3215 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
3216 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
3217 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
3218 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
3219 #define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD_MASK 0xfe000000
3220 #define MC_HUB_RDREQ_MCDV__STALL_THRESHOLD__SHIFT 0x19
3221 #define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
3222 #define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
3223 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3224 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3225 #define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
3226 #define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
3227 #define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
3228 #define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
3229 #define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
3230 #define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
3231 #define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
3232 #define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
3233 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
3234 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
3235 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
3236 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
3237 #define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
3238 #define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
3239 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3240 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3241 #define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
3242 #define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
3243 #define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
3244 #define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
3245 #define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
3246 #define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
3247 #define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
3248 #define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
3249 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
3250 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
3251 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
3252 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
3253 #define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
3254 #define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
3255 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3256 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3257 #define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
3258 #define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
3259 #define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
3260 #define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
3261 #define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
3262 #define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
3263 #define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
3264 #define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
3265 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
3266 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
3267 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
3268 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
3269 #define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
3270 #define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
3271 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3272 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3273 #define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
3274 #define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
3275 #define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
3276 #define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
3277 #define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
3278 #define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
3279 #define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
3280 #define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
3281 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
3282 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
3283 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
3284 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
3285 #define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
3286 #define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
3287 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
3288 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
3289 #define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
3290 #define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
3291 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
3292 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
3293 #define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
3294 #define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
3295 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
3296 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
3297 #define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
3298 #define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
3299 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
3300 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
3301 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
3302 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
3303 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3304 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3305 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
3306 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
3307 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3308 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3309 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
3310 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
3311 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3312 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3313 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
3314 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
3315 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3316 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3317 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
3318 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
3319 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3320 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3321 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
3322 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
3323 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3324 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3325 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
3326 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
3327 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3328 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3329 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
3330 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
3331 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3332 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3333 #define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
3334 #define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
3335 #define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
3336 #define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
3337 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
3338 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
3339 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
3340 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
3341 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
3342 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
3343 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
3344 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
3345 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
3346 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
3347 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
3348 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
3349 #define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
3350 #define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
3351 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
3352 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
3353 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
3354 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
3355 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
3356 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
3357 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
3358 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
3359 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
3360 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
3361 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
3362 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
3363 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
3364 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
3365 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3366 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3367 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3368 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3369 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3370 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3371 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3372 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3373 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
3374 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
3375 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
3376 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
3377 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
3378 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
3379 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
3380 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
3381 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3382 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3383 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3384 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3385 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3386 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3387 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3388 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3389 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
3390 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
3391 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
3392 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
3393 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
3394 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
3395 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
3396 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
3397 #define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
3398 #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
3399 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
3400 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
3401 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
3402 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
3403 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
3404 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
3405 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
3406 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
3407 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
3408 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
3409 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
3410 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
3411 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
3412 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
3413 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
3414 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
3415 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
3416 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
3417 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
3418 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
3419 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
3420 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
3421 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
3422 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
3423 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
3424 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
3425 #define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
3426 #define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
3427 #define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
3428 #define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
3429 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
3430 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
3431 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
3432 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
3433 #define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
3434 #define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
3435 #define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
3436 #define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
3437 #define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
3438 #define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
3439 #define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
3440 #define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
3441 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
3442 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
3443 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
3444 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
3445 #define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
3446 #define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
3447 #define MC_SHARED_CHMAP__CHAN0_MASK 0xf
3448 #define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
3449 #define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
3450 #define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
3451 #define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
3452 #define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
3453 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
3454 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
3455 #define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
3456 #define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
3457 #define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
3458 #define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
3459 #define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
3460 #define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
3461 #define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
3462 #define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
3463 #define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
3464 #define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
3465 #define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
3466 #define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
3467 #define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
3468 #define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
3469 #define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
3470 #define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
3471 #define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
3472 #define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
3473 #define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
3474 #define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
3475 #define MC_RD_GRP_GFX__CP_MASK 0xf
3476 #define MC_RD_GRP_GFX__CP__SHIFT 0x0
3477 #define MC_RD_GRP_GFX__SH_MASK 0xf0
3478 #define MC_RD_GRP_GFX__SH__SHIFT 0x4
3479 #define MC_RD_GRP_GFX__IA_MASK 0xf00
3480 #define MC_RD_GRP_GFX__IA__SHIFT 0x8
3481 #define MC_RD_GRP_GFX__ACPG_MASK 0xf000
3482 #define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
3483 #define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
3484 #define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
3485 #define MC_RD_GRP_GFX__ISP_MASK 0xf00000
3486 #define MC_RD_GRP_GFX__ISP__SHIFT 0x14
3487 #define MC_RD_GRP_GFX__XDMAM_MASK 0xf000000
3488 #define MC_RD_GRP_GFX__XDMAM__SHIFT 0x18
3489 #define MC_WR_GRP_GFX__CP_MASK 0xf
3490 #define MC_WR_GRP_GFX__CP__SHIFT 0x0
3491 #define MC_WR_GRP_GFX__SH_MASK 0xf0
3492 #define MC_WR_GRP_GFX__SH__SHIFT 0x4
3493 #define MC_WR_GRP_GFX__ACPG_MASK 0xf00
3494 #define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
3495 #define MC_WR_GRP_GFX__ACPO_MASK 0xf000
3496 #define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
3497 #define MC_WR_GRP_GFX__ISP_MASK 0xf0000
3498 #define MC_WR_GRP_GFX__ISP__SHIFT 0x10
3499 #define MC_WR_GRP_GFX__XDMA_MASK 0xf00000
3500 #define MC_WR_GRP_GFX__XDMA__SHIFT 0x14
3501 #define MC_WR_GRP_GFX__XDMAM_MASK 0xf000000
3502 #define MC_WR_GRP_GFX__XDMAM__SHIFT 0x18
3503 #define MC_RD_GRP_SYS__RLC_MASK 0xf
3504 #define MC_RD_GRP_SYS__RLC__SHIFT 0x0
3505 #define MC_RD_GRP_SYS__VMC_MASK 0xf0
3506 #define MC_RD_GRP_SYS__VMC__SHIFT 0x4
3507 #define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
3508 #define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
3509 #define MC_RD_GRP_SYS__DMIF_MASK 0xf000
3510 #define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
3511 #define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
3512 #define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
3513 #define MC_RD_GRP_SYS__SMU_MASK 0xf00000
3514 #define MC_RD_GRP_SYS__SMU__SHIFT 0x14
3515 #define MC_RD_GRP_SYS__VCE_MASK 0xf000000
3516 #define MC_RD_GRP_SYS__VCE__SHIFT 0x18
3517 #define MC_RD_GRP_SYS__VCEU_MASK 0xf0000000
3518 #define MC_RD_GRP_SYS__VCEU__SHIFT 0x1c
3519 #define MC_WR_GRP_SYS__IH_MASK 0xf
3520 #define MC_WR_GRP_SYS__IH__SHIFT 0x0
3521 #define MC_WR_GRP_SYS__MCIF_MASK 0xf0
3522 #define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
3523 #define MC_WR_GRP_SYS__RLC_MASK 0xf00
3524 #define MC_WR_GRP_SYS__RLC__SHIFT 0x8
3525 #define MC_WR_GRP_SYS__SAM_MASK 0xf000
3526 #define MC_WR_GRP_SYS__SAM__SHIFT 0xc
3527 #define MC_WR_GRP_SYS__SMU_MASK 0xf0000
3528 #define MC_WR_GRP_SYS__SMU__SHIFT 0x10
3529 #define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
3530 #define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
3531 #define MC_WR_GRP_SYS__VCE_MASK 0xf000000
3532 #define MC_WR_GRP_SYS__VCE__SHIFT 0x18
3533 #define MC_WR_GRP_SYS__VCEU_MASK 0xf0000000
3534 #define MC_WR_GRP_SYS__VCEU__SHIFT 0x1c
3535 #define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
3536 #define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
3537 #define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
3538 #define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
3539 #define MC_RD_GRP_OTH__HDP_MASK 0xf00
3540 #define MC_RD_GRP_OTH__HDP__SHIFT 0x8
3541 #define MC_RD_GRP_OTH__SEM_MASK 0xf000
3542 #define MC_RD_GRP_OTH__SEM__SHIFT 0xc
3543 #define MC_RD_GRP_OTH__UMC_MASK 0xf0000
3544 #define MC_RD_GRP_OTH__UMC__SHIFT 0x10
3545 #define MC_RD_GRP_OTH__UVD_MASK 0xf00000
3546 #define MC_RD_GRP_OTH__UVD__SHIFT 0x14
3547 #define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
3548 #define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
3549 #define MC_RD_GRP_OTH__SAM_MASK 0xf0000000
3550 #define MC_RD_GRP_OTH__SAM__SHIFT 0x1c
3551 #define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
3552 #define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
3553 #define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
3554 #define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
3555 #define MC_WR_GRP_OTH__HDP_MASK 0xf00
3556 #define MC_WR_GRP_OTH__HDP__SHIFT 0x8
3557 #define MC_WR_GRP_OTH__SEM_MASK 0xf000
3558 #define MC_WR_GRP_OTH__SEM__SHIFT 0xc
3559 #define MC_WR_GRP_OTH__UMC_MASK 0xf0000
3560 #define MC_WR_GRP_OTH__UMC__SHIFT 0x10
3561 #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
3562 #define MC_WR_GRP_OTH__UVD__SHIFT 0x14
3563 #define MC_WR_GRP_OTH__XDP_MASK 0xf000000
3564 #define MC_WR_GRP_OTH__XDP__SHIFT 0x18
3565 #define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
3566 #define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
3567 #define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
3568 #define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
3569 #define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
3570 #define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
3571 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
3572 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
3573 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
3574 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
3575 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
3576 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
3577 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3578 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3579 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3580 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3581 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
3582 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
3583 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
3584 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
3585 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
3586 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
3587 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
3588 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
3589 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
3590 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
3591 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
3592 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
3593 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
3594 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
3595 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3596 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3597 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3598 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3599 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3600 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3601 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3602 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3603 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3604 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3605 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3606 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3607 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3608 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3609 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3610 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3611 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
3612 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
3613 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
3614 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
3615 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
3616 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
3617 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
3618 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
3619 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
3620 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
3621 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
3622 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
3623 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
3624 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
3625 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
3626 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
3627 #define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
3628 #define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
3629 #define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
3630 #define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
3631 #define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
3632 #define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
3633 #define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
3634 #define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
3635 #define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
3636 #define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
3637 #define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
3638 #define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
3639 #define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
3640 #define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
3641 #define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
3642 #define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
3643 #define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3644 #define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3645 #define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3646 #define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3647 #define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3648 #define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3649 #define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3650 #define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3651 #define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3652 #define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3653 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3654 #define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3655 #define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
3656 #define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
3657 #define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
3658 #define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
3659 #define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3660 #define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3661 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
3662 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
3663 #define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
3664 #define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
3665 #define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
3666 #define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
3667 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
3668 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
3669 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
3670 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
3671 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
3672 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
3673 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
3674 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
3675 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
3676 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
3677 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
3678 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
3679 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
3680 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
3681 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
3682 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
3683 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
3684 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
3685 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
3686 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
3687 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
3688 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
3689 #define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
3690 #define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
3691 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
3692 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
3693 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
3694 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
3695 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
3696 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
3697 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3698 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3699 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3700 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3701 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3702 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3703 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3704 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3705 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3706 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3707 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3708 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3709 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3710 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3711 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3712 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3713 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3714 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3715 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3716 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3717 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3718 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3719 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3720 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3721 #define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
3722 #define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3723 #define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
3724 #define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3725 #define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
3726 #define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3727 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3728 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3729 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3730 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3731 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3732 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3733 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3734 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3735 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3736 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3737 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3738 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3739 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3740 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3741 #define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
3742 #define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3743 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3744 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3745 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3746 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3747 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3748 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3749 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3750 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3751 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3752 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3753 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3754 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3755 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3756 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3757 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3758 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3759 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3760 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3761 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3762 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3763 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3764 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3765 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3766 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3767 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3768 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3769 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3770 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3771 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3772 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3773 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3774 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3775 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3776 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3777 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3778 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3779 #define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
3780 #define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
3781 #define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
3782 #define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
3783 #define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
3784 #define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
3785 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
3786 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
3787 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
3788 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
3789 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
3790 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
3791 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
3792 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
3793 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
3794 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
3795 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
3796 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
3797 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
3798 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
3799 #define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
3800 #define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
3801 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3802 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3803 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3804 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3805 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3806 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3807 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3808 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3809 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
3810 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
3811 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
3812 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
3813 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
3814 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
3815 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
3816 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
3817 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
3818 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
3819 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
3820 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
3821 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
3822 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
3823 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
3824 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
3825 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
3826 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
3827 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
3828 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
3829 #define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
3830 #define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
3831 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3832 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3833 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3834 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3835 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3836 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3837 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3838 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3839 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3840 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3841 #define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
3842 #define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
3843 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3844 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3845 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3846 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3847 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3848 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3849 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3850 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3851 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3852 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3853 #define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
3854 #define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
3855 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3856 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3857 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3858 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3859 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3860 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3861 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3862 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3863 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3864 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3865 #define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
3866 #define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
3867 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3868 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3869 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3870 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3871 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3872 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3873 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3874 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3875 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3876 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3877 #define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
3878 #define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
3879 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
3880 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
3881 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
3882 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
3883 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
3884 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
3885 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
3886 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
3887 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
3888 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
3889 #define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
3890 #define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
3891 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
3892 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
3893 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
3894 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
3895 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
3896 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
3897 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
3898 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
3899 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
3900 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
3901 #define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
3902 #define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
3903 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
3904 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
3905 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
3906 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
3907 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
3908 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
3909 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
3910 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
3911 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
3912 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
3913 #define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
3914 #define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
3915 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
3916 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
3917 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
3918 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
3919 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
3920 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
3921 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
3922 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
3923 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
3924 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
3925 #define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
3926 #define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
3927 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
3928 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
3929 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
3930 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
3931 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
3932 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
3933 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
3934 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
3935 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
3936 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
3937 #define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
3938 #define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
3939 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
3940 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
3941 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
3942 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
3943 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
3944 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
3945 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
3946 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
3947 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
3948 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
3949 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
3950 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
3951 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
3952 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
3953 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
3954 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
3955 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
3956 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
3957 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
3958 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
3959 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
3960 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
3961 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
3962 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
3963 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
3964 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
3965 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
3966 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
3967 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
3968 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
3969 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
3970 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
3971 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
3972 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
3973 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
3974 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
3975 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
3976 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
3977 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
3978 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
3979 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
3980 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
3981 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
3982 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
3983 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
3984 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
3985 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
3986 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
3987 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
3988 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
3989 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
3990 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
3991 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
3992 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
3993 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
3994 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
3995 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
3996 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
3997 #define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
3998 #define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
3999 #define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
4000 #define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
4001 #define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
4002 #define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
4003 #define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
4004 #define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
4005 #define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
4006 #define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
4007 #define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
4008 #define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
4009 #define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
4010 #define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
4011 #define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
4012 #define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
4013 #define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
4014 #define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
4015 #define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
4016 #define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
4017 #define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
4018 #define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
4019 #define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
4020 #define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
4021 #define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
4022 #define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
4023 #define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
4024 #define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
4025 #define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
4026 #define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
4027 #define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
4028 #define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
4029 #define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
4030 #define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
4031 #define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
4032 #define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
4033 #define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
4034 #define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
4035 #define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
4036 #define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
4037 #define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
4038 #define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
4039 #define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
4040 #define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
4041 #define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
4042 #define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
4043 #define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
4044 #define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
4045 #define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
4046 #define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
4047 #define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
4048 #define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
4049 #define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
4050 #define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
4051 #define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
4052 #define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
4053 #define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
4054 #define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
4055 #define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
4056 #define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
4057 #define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
4058 #define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
4059 #define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
4060 #define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
4061 #define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
4062 #define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
4063 #define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
4064 #define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
4065 #define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
4066 #define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
4067 #define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
4068 #define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
4069 #define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
4070 #define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
4071 #define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
4072 #define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
4073 #define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
4074 #define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
4075 #define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
4076 #define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
4077 #define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
4078 #define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
4079 #define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
4080 #define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
4081 #define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
4082 #define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
4083 #define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
4084 #define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
4085 #define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
4086 #define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
4087 #define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
4088 #define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
4089 #define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
4090 #define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
4091 #define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
4092 #define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
4093 #define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
4094 #define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
4095 #define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
4096 #define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
4097 #define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
4098 #define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
4099 #define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
4100 #define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
4101 #define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
4102 #define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
4103 #define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
4104 #define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
4105 #define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
4106 #define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
4107 #define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
4108 #define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
4109 #define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
4110 #define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
4111 #define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
4112 #define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
4113 #define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
4114 #define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
4115 #define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
4116 #define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
4117 #define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
4118 #define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
4119 #define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
4120 #define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
4121 #define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
4122 #define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
4123 #define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
4124 #define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
4125 #define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
4126 #define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
4127 #define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
4128 #define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
4129 #define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
4130 #define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
4131 #define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
4132 #define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
4133 #define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
4134 #define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
4135 #define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
4136 #define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
4137 #define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
4138 #define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
4139 #define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
4140 #define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
4141 #define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
4142 #define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
4143 #define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
4144 #define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
4145 #define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
4146 #define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
4147 #define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
4148 #define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
4149 #define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
4150 #define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
4151 #define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
4152 #define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
4153 #define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
4154 #define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
4155 #define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
4156 #define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
4157 #define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
4158 #define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
4159 #define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
4160 #define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
4161 #define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
4162 #define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
4163 #define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
4164 #define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
4165 #define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
4166 #define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
4167 #define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
4168 #define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
4169 #define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
4170 #define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
4171 #define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
4172 #define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
4173 #define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
4174 #define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
4175 #define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
4176 #define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
4177 #define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
4178 #define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
4179 #define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
4180 #define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
4181 #define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
4182 #define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
4183 #define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
4184 #define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
4185 #define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
4186 #define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
4187 #define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
4188 #define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
4189 #define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
4190 #define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
4191 #define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
4192 #define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
4193 #define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
4194 #define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
4195 #define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
4196 #define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
4197 #define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
4198 #define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
4199 #define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
4200 #define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
4201 #define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
4202 #define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
4203 #define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
4204 #define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
4205 #define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
4206 #define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
4207 #define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
4208 #define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
4209 #define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
4210 #define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
4211 #define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
4212 #define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
4213 #define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
4214 #define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
4215 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
4216 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
4217 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
4218 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
4219 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
4220 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
4221 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
4222 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
4223 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
4224 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
4225 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
4226 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
4227 #define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
4228 #define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
4229 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
4230 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
4231 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
4232 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
4233 #define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
4234 #define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
4235 #define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
4236 #define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
4237 #define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
4238 #define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
4239 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
4240 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
4241 #define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
4242 #define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
4243 #define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
4244 #define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
4245 #define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
4246 #define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
4247 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
4248 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
4249 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
4250 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
4251 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
4252 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
4253 #define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
4254 #define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
4255 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
4256 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
4257 #define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
4258 #define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
4259 #define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
4260 #define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
4261 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
4262 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
4263 #define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
4264 #define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
4265 #define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
4266 #define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
4267 #define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
4268 #define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
4269 #define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
4270 #define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
4271 #define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
4272 #define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
4273 #define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
4274 #define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
4275 #define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
4276 #define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
4277 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
4278 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
4279 #define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
4280 #define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
4281 #define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
4282 #define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
4283 #define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
4284 #define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
4285 #define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
4286 #define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
4287 #define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
4288 #define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
4289 #define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
4290 #define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
4291 #define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
4292 #define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
4293 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
4294 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
4295 #define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
4296 #define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
4297 #define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
4298 #define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
4299 #define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
4300 #define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
4301 #define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
4302 #define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
4303 #define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
4304 #define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
4305 #define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
4306 #define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
4307 #define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
4308 #define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
4309 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
4310 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
4311 #define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
4312 #define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
4313 #define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
4314 #define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
4315 #define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
4316 #define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
4317 #define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
4318 #define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
4319 #define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
4320 #define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
4321 #define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
4322 #define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
4323 #define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
4324 #define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
4325 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
4326 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
4327 #define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
4328 #define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
4329 #define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
4330 #define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
4331 #define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
4332 #define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
4333 #define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
4334 #define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
4335 #define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
4336 #define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
4337 #define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
4338 #define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
4339 #define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
4340 #define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
4341 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
4342 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
4343 #define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
4344 #define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
4345 #define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
4346 #define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
4347 #define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
4348 #define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
4349 #define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
4350 #define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
4351 #define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
4352 #define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
4353 #define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
4354 #define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
4355 #define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
4356 #define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
4357 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
4358 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
4359 #define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
4360 #define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
4361 #define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
4362 #define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
4363 #define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
4364 #define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
4365 #define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
4366 #define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
4367 #define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
4368 #define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
4369 #define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
4370 #define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
4371 #define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
4372 #define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
4373 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
4374 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
4375 #define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
4376 #define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
4377 #define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
4378 #define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
4379 #define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
4380 #define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
4381 #define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
4382 #define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
4383 #define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
4384 #define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
4385 #define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
4386 #define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
4387 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
4388 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
4389 #define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
4390 #define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
4391 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
4392 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
4393 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
4394 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
4395 #define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
4396 #define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
4397 #define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
4398 #define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
4399 #define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
4400 #define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
4401 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
4402 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
4403 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
4404 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
4405 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
4406 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
4407 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
4408 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
4409 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
4410 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
4411 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
4412 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
4413 #define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
4414 #define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
4415 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4416 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4417 #define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4418 #define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4419 #define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
4420 #define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
4421 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4422 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4423 #define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4424 #define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4425 #define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
4426 #define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
4427 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4428 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4429 #define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4430 #define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4431 #define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
4432 #define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
4433 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4434 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4435 #define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4436 #define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4437 #define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
4438 #define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
4439 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
4440 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
4441 #define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
4442 #define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
4443 #define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
4444 #define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
4445 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
4446 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
4447 #define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
4448 #define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
4449 #define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
4450 #define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
4451 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
4452 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
4453 #define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
4454 #define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
4455 #define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
4456 #define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
4457 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
4458 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
4459 #define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
4460 #define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
4461 #define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
4462 #define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
4463 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
4464 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
4465 #define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
4466 #define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
4467 #define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
4468 #define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
4469 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
4470 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
4471 #define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
4472 #define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
4473 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
4474 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
4475 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4476 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4477 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4478 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4479 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
4480 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
4481 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4482 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4483 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4484 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4485 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
4486 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
4487 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4488 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4489 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4490 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4491 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
4492 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
4493 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4494 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4495 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4496 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4497 #define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
4498 #define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
4499 #define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
4500 #define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
4501 #define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
4502 #define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
4503 #define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
4504 #define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
4505 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
4506 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
4507 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
4508 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
4509 #define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
4510 #define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
4511 #define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
4512 #define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
4513 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
4514 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
4515 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
4516 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
4517 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
4518 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
4519 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
4520 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
4521 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
4522 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
4523 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
4524 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
4525 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
4526 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
4527 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
4528 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
4529 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
4530 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
4531 #define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
4532 #define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
4533 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
4534 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
4535 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
4536 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
4537 #define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
4538 #define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
4539 #define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
4540 #define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
4541 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
4542 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
4543 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
4544 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
4545 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
4546 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
4547 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
4548 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
4549 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
4550 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
4551 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
4552 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
4553 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
4554 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
4555 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
4556 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
4557 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
4558 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
4559 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
4560 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
4561 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
4562 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
4563 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
4564 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
4565 #define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
4566 #define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
4567 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
4568 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
4569 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
4570 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
4571 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
4572 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
4573 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
4574 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
4575 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
4576 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
4577 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
4578 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
4579 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
4580 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
4581 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
4582 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
4583 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
4584 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
4585 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
4586 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
4587 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
4588 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
4589 #define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
4590 #define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
4591 #define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
4592 #define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
4593 #define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
4594 #define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
4595 #define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
4596 #define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
4597 #define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
4598 #define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
4599 #define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
4600 #define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
4601 #define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
4602 #define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
4603 #define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
4604 #define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
4605 #define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
4606 #define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
4607 #define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
4608 #define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
4609 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
4610 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
4611 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
4612 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
4613 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
4614 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
4615 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
4616 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
4617 #define MC_XPB_STICKY__BITS_MASK 0xffffffff
4618 #define MC_XPB_STICKY__BITS__SHIFT 0x0
4619 #define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
4620 #define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
4621 #define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
4622 #define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
4623 #define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
4624 #define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
4625 #define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
4626 #define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
4627 #define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
4628 #define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
4629 #define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
4630 #define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
4631 #define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
4632 #define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
4633 #define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
4634 #define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
4635 #define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
4636 #define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
4637 #define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
4638 #define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
4639 #define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
4640 #define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
4641 #define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
4642 #define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
4643 #define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
4644 #define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
4645 #define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
4646 #define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
4647 #define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
4648 #define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
4649 #define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
4650 #define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
4651 #define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
4652 #define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
4653 #define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
4654 #define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
4655 #define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
4656 #define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
4657 #define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
4658 #define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
4659 #define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
4660 #define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
4661 #define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
4662 #define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
4663 #define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
4664 #define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
4665 #define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
4666 #define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
4667 #define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
4668 #define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
4669 #define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
4670 #define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
4671 #define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
4672 #define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
4673 #define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
4674 #define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
4675 #define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
4676 #define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
4677 #define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
4678 #define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
4679 #define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
4680 #define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
4681 #define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
4682 #define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
4683 #define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
4684 #define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
4685 #define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
4686 #define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
4687 #define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
4688 #define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
4689 #define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
4690 #define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
4691 #define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
4692 #define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
4693 #define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
4694 #define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
4695 #define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
4696 #define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
4697 #define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
4698 #define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
4699 #define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
4700 #define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
4701 #define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
4702 #define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
4703 #define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
4704 #define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
4705 #define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
4706 #define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
4707 #define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
4708 #define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
4709 #define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
4710 #define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
4711 #define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
4712 #define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
4713 #define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
4714 #define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
4715 #define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
4716 #define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
4717 #define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
4718 #define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
4719 #define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
4720 #define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
4721 #define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
4722 #define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
4723 #define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
4724 #define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
4725 #define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
4726 #define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
4727 #define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
4728 #define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
4729 #define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
4730 #define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
4731 #define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
4732 #define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
4733 #define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
4734 #define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
4735 #define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
4736 #define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
4737 #define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
4738 #define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
4739 #define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
4740 #define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
4741 #define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
4742 #define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
4743 #define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
4744 #define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
4745 #define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
4746 #define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
4747 #define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
4748 #define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
4749 #define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
4750 #define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
4751 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
4752 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
4753 #define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
4754 #define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
4755 #define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
4756 #define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
4757 #define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
4758 #define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
4759 #define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
4760 #define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
4761 #define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
4762 #define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
4763 #define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
4764 #define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
4765 #define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
4766 #define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
4767 #define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
4768 #define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
4769 #define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
4770 #define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
4771 #define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
4772 #define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
4773 #define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
4774 #define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
4775 #define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
4776 #define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
4777 #define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
4778 #define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
4779 #define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
4780 #define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
4781 #define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
4782 #define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
4783 #define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
4784 #define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
4785 #define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
4786 #define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
4787 #define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
4788 #define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
4789 #define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
4790 #define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
4791 #define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
4792 #define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
4793 #define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
4794 #define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
4795 #define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
4796 #define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
4797 #define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
4798 #define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
4799 #define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
4800 #define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
4801 #define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
4802 #define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
4803 #define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
4804 #define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
4805 #define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
4806 #define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
4807 #define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
4808 #define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
4809 #define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
4810 #define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
4811 #define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
4812 #define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
4813 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
4814 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
4815 #define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
4816 #define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
4817 #define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
4818 #define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
4819 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
4820 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
4821 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
4822 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
4823 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
4824 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
4825 #define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
4826 #define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
4827 #define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
4828 #define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
4829 #define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
4830 #define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
4831 #define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
4832 #define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
4833 #define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
4834 #define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
4835 #define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
4836 #define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
4837 #define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
4838 #define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
4839 #define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
4840 #define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
4841 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
4842 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
4843 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
4844 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
4845 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
4846 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
4847 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
4848 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
4849 #define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
4850 #define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
4851 #define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
4852 #define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
4853 #define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
4854 #define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
4855 #define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
4856 #define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
4857 #define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
4858 #define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
4859 #define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
4860 #define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
4861 #define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
4862 #define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
4863 #define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
4864 #define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
4865 #define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
4866 #define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
4867 #define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
4868 #define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
4869 #define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
4870 #define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
4871 #define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
4872 #define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
4873 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
4874 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
4875 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
4876 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
4877 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
4878 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
4879 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
4880 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
4881 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
4882 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
4883 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
4884 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
4885 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
4886 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
4887 #define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
4888 #define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
4889 #define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
4890 #define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
4891 #define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
4892 #define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
4893 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
4894 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
4895 #define MC_XBAR_TWOCHAN__CH0_MASK 0x6
4896 #define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
4897 #define MC_XBAR_TWOCHAN__CH1_MASK 0x18
4898 #define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
4899 #define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
4900 #define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
4901 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
4902 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
4903 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
4904 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
4905 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
4906 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
4907 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
4908 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
4909 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
4910 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
4911 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
4912 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
4913 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
4914 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
4915 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
4916 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
4917 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
4918 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
4919 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
4920 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
4921 #define MC_XBAR_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
4922 #define MC_XBAR_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
4923 #define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
4924 #define MC_XBAR_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
4925 #define MC_XBAR_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
4926 #define MC_XBAR_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
4927 #define MC_XBAR_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
4928 #define MC_XBAR_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
4929 #define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
4930 #define MC_XBAR_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
4931 #define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
4932 #define MC_XBAR_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
4933 #define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xff00
4934 #define MC_XBAR_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
4935 #define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
4936 #define MC_XBAR_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
4937 #define MC_XBAR_PERF_MON_CNTL2__MON0_ID_MASK 0xff
4938 #define MC_XBAR_PERF_MON_CNTL2__MON0_ID__SHIFT 0x0
4939 #define MC_XBAR_PERF_MON_CNTL2__MON1_ID_MASK 0xff00
4940 #define MC_XBAR_PERF_MON_CNTL2__MON1_ID__SHIFT 0x8
4941 #define MC_XBAR_PERF_MON_CNTL2__MON2_ID_MASK 0xff0000
4942 #define MC_XBAR_PERF_MON_CNTL2__MON2_ID__SHIFT 0x10
4943 #define MC_XBAR_PERF_MON_CNTL2__MON3_ID_MASK 0xff000000
4944 #define MC_XBAR_PERF_MON_CNTL2__MON3_ID__SHIFT 0x18
4945 #define MC_XBAR_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
4946 #define MC_XBAR_PERF_MON_RSLT0__COUNT__SHIFT 0x0
4947 #define MC_XBAR_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
4948 #define MC_XBAR_PERF_MON_RSLT1__COUNT__SHIFT 0x0
4949 #define MC_XBAR_PERF_MON_RSLT2__COUNT_MASK 0xffffffff
4950 #define MC_XBAR_PERF_MON_RSLT2__COUNT__SHIFT 0x0
4951 #define MC_XBAR_PERF_MON_RSLT3__COUNT_MASK 0xffffffff
4952 #define MC_XBAR_PERF_MON_RSLT3__COUNT__SHIFT 0x0
4953 #define MC_XBAR_PERF_MON_MAX_THSH__MON0_MASK 0xff
4954 #define MC_XBAR_PERF_MON_MAX_THSH__MON0__SHIFT 0x0
4955 #define MC_XBAR_PERF_MON_MAX_THSH__MON1_MASK 0xff00
4956 #define MC_XBAR_PERF_MON_MAX_THSH__MON1__SHIFT 0x8
4957 #define MC_XBAR_PERF_MON_MAX_THSH__MON2_MASK 0xff0000
4958 #define MC_XBAR_PERF_MON_MAX_THSH__MON2__SHIFT 0x10
4959 #define MC_XBAR_PERF_MON_MAX_THSH__MON3_MASK 0xff000000
4960 #define MC_XBAR_PERF_MON_MAX_THSH__MON3__SHIFT 0x18
4961 #define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
4962 #define MC_XBAR_SPARE0__BIT__SHIFT 0x0
4963 #define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
4964 #define MC_XBAR_SPARE1__BIT__SHIFT 0x0
4965 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4966 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4967 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4968 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4969 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4970 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4971 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4972 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4973 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4974 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4975 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4976 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4977 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4978 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4979 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
4980 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
4981 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4982 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4983 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4984 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4985 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4986 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4987 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4988 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4989 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4990 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4991 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4992 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4993 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4994 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4995 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
4996 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
4997 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
4998 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
4999 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5000 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5001 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5002 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5003 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5004 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5005 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5006 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5007 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5008 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5009 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5010 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5011 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5012 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5013 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5014 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5015 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5016 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5017 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5018 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5019 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5020 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5021 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5022 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5023 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5024 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5025 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5026 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5027 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5028 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5029 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5030 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5031 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5032 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5033 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5034 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5035 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5036 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5037 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5038 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5039 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5040 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5041 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5042 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5043 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5044 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5045 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5046 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5047 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5048 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5049 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5050 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5051 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5052 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5053 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5054 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5055 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5056 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5057 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5058 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5059 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5060 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5061 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5062 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5063 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5064 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5065 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5066 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5067 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5068 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5069 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5070 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5071 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5072 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5073 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5074 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5075 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5076 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5077 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5078 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5079 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5080 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5081 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5082 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5083 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5084 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5085 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5086 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5087 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5088 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5089 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5090 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5091 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5092 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5093 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5094 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5095 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5096 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5097 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5098 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5099 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5100 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5101 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5102 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5103 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5104 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5105 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5106 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5107 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5108 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5109 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5110 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5111 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5112 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5113 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5114 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5115 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5116 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5117 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5118 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5119 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5120 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5121 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5122 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5123 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5124 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5125 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5126 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5127 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5128 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5129 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5130 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5131 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5132 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5133 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5134 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5135 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5136 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5137 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5138 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5139 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5140 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5141 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5142 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5143 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5144 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5145 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5146 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5147 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5148 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5149 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5150 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5151 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5152 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5153 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5154 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5155 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5156 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5157 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5158 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5159 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5160 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5161 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5162 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5163 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5164 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5165 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5166 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5167 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5168 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5169 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5170 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5171 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5172 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5173 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5174 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5175 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5176 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5177 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5178 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5179 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5180 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5181 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5182 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5183 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5184 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5185 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5186 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5187 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5188 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5189 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5190 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5191 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5192 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5193 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5194 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5195 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5196 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5197 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5198 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5199 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5200 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5201 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5202 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5203 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5204 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5205 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5206 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5207 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5208 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5209 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5210 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5211 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5212 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5213 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5214 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5215 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5216 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5217 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5218 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5219 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5220 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5221 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5222 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5223 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5224 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5225 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5226 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5227 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5228 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5229 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5230 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5231 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5232 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5233 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5234 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5235 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5236 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5237 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5238 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5239 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5240 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5241 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5242 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5243 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5244 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5245 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5246 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5247 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5248 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5249 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5250 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5251 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5252 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5253 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5254 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5255 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5256 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5257 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5258 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5259 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5260 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5261 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5262 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5263 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5264 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5265 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5266 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5267 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5268 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5269 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5270 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5271 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5272 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5273 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5274 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5275 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5276 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5277 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5278 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5279 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5280 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5281 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5282 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5283 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5284 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5285 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5286 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5287 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5288 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5289 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5290 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5291 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5292 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5293 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5294 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5295 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5296 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5297 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5298 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5299 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5300 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5301 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5302 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5303 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5304 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5305 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5306 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5307 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5308 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5309 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5310 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5311 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5312 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5313 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5314 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5315 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5316 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5317 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5318 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5319 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5320 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5321 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5322 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5323 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5324 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5325 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5326 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5327 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5328 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5329 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5330 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5331 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5332 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5333 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5334 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5335 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5336 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5337 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5338 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5339 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5340 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5341 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5342 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5343 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5344 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5345 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5346 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5347 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5348 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5349 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5350 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5351 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5352 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5353 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5354 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5355 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5356 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5357 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5358 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5359 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5360 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5361 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5362 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5363 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5364 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5365 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5366 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5367 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5368 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5369 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5370 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5371 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5372 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5373 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5374 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5375 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5376 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5377 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5378 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5379 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5380 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5381 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5382 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5383 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5384 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5385 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5386 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5387 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5388 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5389 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5390 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5391 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5392 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5393 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5394 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5395 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5396 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5397 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5398 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5399 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5400 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5401 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5402 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5403 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5404 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5405 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5406 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5407 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5408 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5409 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5410 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5411 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5412 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5413 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5414 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5415 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5416 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5417 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5418 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5419 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5420 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5421 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5422 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5423 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5424 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5425 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5426 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5427 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5428 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5429 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5430 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5431 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5432 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5433 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5434 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5435 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5436 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5437 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5438 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5439 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5440 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5441 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5442 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5443 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5444 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5445 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5446 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5447 #define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP_MASK 0x1
5448 #define MC_ARB_PERF_MON_CNTL0_ECC__ALLOW_WRAP__SHIFT 0x0
5449 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5450 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5451 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5452 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5453 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5454 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5455 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5456 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5457 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
5458 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
5459 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
5460 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
5461 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
5462 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
5463 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
5464 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
5465 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
5466 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
5467 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
5468 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
5469 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
5470 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
5471 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
5472 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
5473 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
5474 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
5475 #define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
5476 #define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
5477 #define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
5478 #define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
5479 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
5480 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
5481 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
5482 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
5483 #define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
5484 #define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
5485 #define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
5486 #define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
5487 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
5488 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
5489 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
5490 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
5491 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
5492 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
5493 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
5494 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
5495 #define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
5496 #define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
5497 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
5498 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
5499 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
5500 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
5501 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
5502 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
5503 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
5504 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
5505 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
5506 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
5507 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
5508 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
5509 #define ATC_ATS_STATUS__BUSY_MASK 0x1
5510 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0
5511 #define ATC_ATS_STATUS__CRASHED_MASK 0x2
5512 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
5513 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
5514 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
5515 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x3f
5516 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
5517 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0xfc00
5518 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
5519 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x3f00000
5520 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
5521 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x3f
5522 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
5523 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
5524 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
5525 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
5526 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
5527 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
5528 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
5529 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
5530 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
5531 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
5532 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
5533 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
5534 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
5535 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
5536 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
5537 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
5538 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
5539 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xffffffff
5540 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
5541 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
5542 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
5543 #define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH_MASK 0x3c
5544 #define ATC_ATS_DEFAULT_PAGE_CNTL__DEFAULT_PAGE_HIGH__SHIFT 0x2
5545 #define ATC_MISC_CG__OFFDLY_MASK 0xfc0
5546 #define ATC_MISC_CG__OFFDLY__SHIFT 0x6
5547 #define ATC_MISC_CG__ENABLE_MASK 0x40000
5548 #define ATC_MISC_CG__ENABLE__SHIFT 0x12
5549 #define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
5550 #define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
5551 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
5552 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
5553 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
5554 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
5555 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
5556 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
5557 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
5558 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
5559 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
5560 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
5561 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
5562 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
5563 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
5564 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
5565 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
5566 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
5567 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
5568 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
5569 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
5570 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
5571 #define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
5572 #define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
5573 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
5574 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
5575 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
5576 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
5577 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
5578 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
5579 #define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
5580 #define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
5581 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS_MASK 0x800
5582 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_READ_RETURNS__SHIFT 0xb
5583 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS_MASK 0x1000
5584 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_WRITE_RETURNS__SHIFT 0xc
5585 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
5586 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
5587 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
5588 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
5589 #define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
5590 #define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
5591 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
5592 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
5593 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
5594 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
5595 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
5596 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
5597 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
5598 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
5599 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
5600 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
5601 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
5602 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
5603 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
5604 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
5605 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
5606 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
5607 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
5608 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
5609 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
5610 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
5611 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
5612 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
5613 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
5614 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
5615 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
5616 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
5617 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
5618 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
5619 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
5620 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
5621 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
5622 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
5623 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
5624 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
5625 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
5626 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
5627 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
5628 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
5629 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
5630 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
5631 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
5632 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
5633 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
5634 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
5635 #define ATC_L1RD_STATUS__BUSY_MASK 0x1
5636 #define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
5637 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
5638 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
5639 #define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
5640 #define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
5641 #define ATC_L1WR_STATUS__BUSY_MASK 0x1
5642 #define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
5643 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
5644 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
5645 #define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
5646 #define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
5647 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
5648 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
5649 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
5650 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
5651 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
5652 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
5653 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
5654 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
5655 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
5656 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
5657 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
5658 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
5659 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
5660 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
5661 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
5662 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
5663 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
5664 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
5665 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
5666 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
5667 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
5668 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
5669 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
5670 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
5671 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
5672 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
5673 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
5674 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
5675 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
5676 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
5677 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
5678 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
5679 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
5680 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
5681 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
5682 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
5683 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
5684 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
5685 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
5686 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
5687 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
5688 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
5689 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
5690 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
5691 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
5692 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
5693 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
5694 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
5695 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
5696 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
5697 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
5698 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
5699 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
5700 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
5701 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
5702 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
5703 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
5704 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
5705 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
5706 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
5707 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
5708 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
5709 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
5710 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
5711 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
5712 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
5713 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
5714 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
5715 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
5716 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
5717 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
5718 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
5719 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
5720 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
5721 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
5722 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
5723 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
5724 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
5725 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
5726 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
5727 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
5728 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
5729 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
5730 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
5731 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
5732 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
5733 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
5734 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
5735 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
5736 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
5737 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
5738 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
5739 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
5740 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
5741 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
5742 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
5743 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
5744 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
5745 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
5746 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
5747 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
5748 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
5749 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
5750 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
5751 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
5752 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
5753 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
5754 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
5755 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
5756 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
5757 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
5758 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
5759 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
5760 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
5761 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
5762 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
5763 #define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
5764 #define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
5765 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
5766 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
5767 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
5768 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
5769 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
5770 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
5771 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
5772 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
5773 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
5774 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
5775 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
5776 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
5777 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
5778 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
5779 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
5780 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
5781 #define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
5782 #define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
5783 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
5784 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
5785 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
5786 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
5787 #define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
5788 #define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
5789 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
5790 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
5791 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
5792 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
5793 #define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
5794 #define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
5795 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
5796 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
5797 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
5798 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
5799 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
5800 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
5801 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
5802 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
5803 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
5804 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
5805 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
5806 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
5807 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
5808 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
5809 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
5810 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
5811 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
5812 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
5813 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
5814 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
5815 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
5816 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
5817 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
5818 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
5819 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
5820 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
5821 #define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
5822 #define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
5823 #define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
5824 #define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
5825 #define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
5826 #define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
5827 #define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
5828 #define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
5829 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
5830 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
5831 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
5832 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
5833 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
5834 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
5835 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
5836 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
5837 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
5838 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
5839 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
5840 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
5841 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
5842 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
5843 #define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
5844 #define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
5845 #define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
5846 #define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
5847 #define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
5848 #define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
5849 #define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
5850 #define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
5851 #define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
5852 #define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
5853 #define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
5854 #define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
5855 #define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
5856 #define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
5857 #define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
5858 #define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
5859 #define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
5860 #define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
5861 #define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
5862 #define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
5863 #define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
5864 #define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
5865 #define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
5866 #define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
5867 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
5868 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
5869 #define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
5870 #define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
5871 #define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
5872 #define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
5873 #define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
5874 #define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
5875 #define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
5876 #define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
5877 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
5878 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
5879 #define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
5880 #define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
5881 #define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
5882 #define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
5883 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
5884 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
5885 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
5886 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
5887 #define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
5888 #define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
5889 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
5890 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
5891 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
5892 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
5893 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
5894 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
5895 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
5896 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
5897 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
5898 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
5899 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
5900 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
5901 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
5902 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
5903 #define GMCON_DEBUG__GFX_STALL_MASK 0x1
5904 #define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
5905 #define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
5906 #define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
5907 #define GMCON_DEBUG__MISC_FLAGS_MASK 0x3ffffffc
5908 #define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x2
5909 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
5910 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
5911 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
5912 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
5913 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
5914 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
5915 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
5916 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
5917 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
5918 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
5919 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
5920 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
5921 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
5922 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
5923 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
5924 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
5925 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
5926 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
5927 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
5928 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
5929 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
5930 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
5931 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
5932 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
5933 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
5934 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
5935 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
5936 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
5937 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
5938 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
5939 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
5940 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
5941 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
5942 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
5943 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
5944 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
5945 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
5946 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
5947 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
5948 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
5949 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
5950 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
5951 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
5952 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
5953 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
5954 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
5955 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
5956 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
5957 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
5958 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
5959 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
5960 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
5961 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
5962 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
5963 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
5964 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
5965 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
5966 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
5967 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
5968 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
5969 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
5970 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
5971 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
5972 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
5973 #define VM_L2_STATUS__L2_BUSY_MASK 0x1
5974 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
5975 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
5976 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
5977 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
5978 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
5979 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
5980 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
5981 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
5982 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
5983 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
5984 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
5985 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
5986 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
5987 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
5988 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
5989 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
5990 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
5991 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
5992 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
5993 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
5994 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
5995 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
5996 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
5997 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
5998 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
5999 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
6000 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
6001 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
6002 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6003 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
6004 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6005 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
6006 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
6007 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
6008 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
6009 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
6010 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
6011 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
6012 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
6013 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
6014 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6015 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
6016 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6017 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
6018 #define VM_CONTEXT0_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
6019 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
6020 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
6021 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
6022 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6023 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
6024 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6025 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
6026 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
6027 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
6028 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
6029 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
6030 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
6031 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
6032 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
6033 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
6034 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6035 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
6036 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6037 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
6038 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
6039 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
6040 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
6041 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
6042 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
6043 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
6044 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
6045 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
6046 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6047 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
6048 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6049 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
6050 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
6051 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
6052 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
6053 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
6054 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
6055 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
6056 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
6057 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
6058 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6059 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
6060 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6061 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
6062 #define VM_CONTEXT1_CNTL__PRIVILEGED_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
6063 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
6064 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
6065 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
6066 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
6067 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
6068 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
6069 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
6070 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
6071 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
6072 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
6073 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
6074 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6075 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
6076 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
6077 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
6078 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
6079 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
6080 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
6081 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
6082 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
6083 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
6084 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6085 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
6086 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
6087 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
6088 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
6089 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
6090 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
6091 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
6092 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
6093 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6094 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6095 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6096 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6097 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6098 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6099 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6100 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6101 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6102 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6103 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6104 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6105 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6106 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6107 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6108 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6109 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
6110 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
6111 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
6112 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
6113 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
6114 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
6115 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
6116 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
6117 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
6118 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
6119 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
6120 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
6121 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
6122 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
6123 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
6124 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
6125 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
6126 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
6127 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
6128 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
6129 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
6130 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
6131 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
6132 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
6133 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
6134 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
6135 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
6136 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
6137 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
6138 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
6139 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
6140 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
6141 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
6142 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
6143 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
6144 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
6145 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
6146 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
6147 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
6148 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
6149 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
6150 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
6151 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
6152 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
6153 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
6154 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
6155 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
6156 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
6157 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
6158 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
6159 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
6160 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
6161 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
6162 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
6163 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
6164 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
6165 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
6166 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
6167 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
6168 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
6169 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
6170 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
6171 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
6172 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
6173 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6174 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6175 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6176 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6177 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6178 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6179 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6180 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6181 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6182 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6183 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6184 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6185 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6186 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6187 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6188 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6189 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
6190 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
6191 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
6192 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
6193 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
6194 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
6195 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
6196 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
6197 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
6198 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
6199 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
6200 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
6201 #define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
6202 #define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
6203 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
6204 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
6205 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
6206 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
6207 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
6208 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
6209 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
6210 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
6211 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
6212 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
6213 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
6214 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
6215 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
6216 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
6217 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
6218 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
6219 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
6220 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
6221 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
6222 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
6223 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
6224 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
6225 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
6226 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
6227 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
6228 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
6229 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
6230 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
6231 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
6232 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
6233 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
6234 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
6235 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
6236 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
6237 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
6238 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
6239 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
6240 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
6241 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
6242 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
6243 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
6244 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
6245 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
6246 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
6247 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
6248 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
6249 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
6250 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
6251 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
6252 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
6253 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
6254 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
6255 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
6256 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
6257 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
6258 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
6259 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
6260 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
6261 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
6262 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
6263 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
6264 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
6265 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
6266 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
6267 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6268 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6269 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6270 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6271 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6272 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6273 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6274 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6275 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6276 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6277 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6278 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6279 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6280 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6281 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6282 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6283 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6284 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6285 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6286 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6287 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6288 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6289 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6290 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6291 #define VM_DEBUG__FLAGS_MASK 0xffffffff
6292 #define VM_DEBUG__FLAGS__SHIFT 0x0
6293 #define VM_L2_CG__OFFDLY_MASK 0xfc0
6294 #define VM_L2_CG__OFFDLY__SHIFT 0x6
6295 #define VM_L2_CG__ENABLE_MASK 0x40000
6296 #define VM_L2_CG__ENABLE__SHIFT 0x12
6297 #define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
6298 #define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
6299 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
6300 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
6301 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0x1ff
6302 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
6303 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6304 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6305 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6306 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6307 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
6308 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
6309 #define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
6310 #define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
6311 #define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
6312 #define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
6313 #define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
6314 #define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
6315 #define MC_SEQ_CNTL__DAT_INV_MASK 0x40
6316 #define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
6317 #define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
6318 #define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
6319 #define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
6320 #define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
6321 #define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
6322 #define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
6323 #define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
6324 #define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
6325 #define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
6326 #define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
6327 #define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
6328 #define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
6329 #define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
6330 #define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
6331 #define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
6332 #define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
6333 #define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
6334 #define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
6335 #define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
6336 #define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
6337 #define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
6338 #define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
6339 #define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
6340 #define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
6341 #define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
6342 #define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
6343 #define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
6344 #define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
6345 #define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
6346 #define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
6347 #define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
6348 #define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
6349 #define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
6350 #define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
6351 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
6352 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
6353 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
6354 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
6355 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
6356 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
6357 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
6358 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
6359 #define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
6360 #define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
6361 #define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
6362 #define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
6363 #define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
6364 #define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
6365 #define MC_SEQ_DRAM__AP8_MASK 0x8
6366 #define MC_SEQ_DRAM__AP8__SHIFT 0x3
6367 #define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
6368 #define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
6369 #define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
6370 #define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
6371 #define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
6372 #define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
6373 #define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
6374 #define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
6375 #define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
6376 #define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
6377 #define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
6378 #define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
6379 #define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
6380 #define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
6381 #define MC_SEQ_DRAM__BO4_MASK 0x4000
6382 #define MC_SEQ_DRAM__BO4__SHIFT 0xe
6383 #define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
6384 #define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
6385 #define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
6386 #define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
6387 #define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
6388 #define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
6389 #define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
6390 #define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
6391 #define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
6392 #define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
6393 #define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
6394 #define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
6395 #define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
6396 #define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
6397 #define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
6398 #define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
6399 #define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
6400 #define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
6401 #define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
6402 #define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
6403 #define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
6404 #define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
6405 #define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
6406 #define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
6407 #define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
6408 #define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
6409 #define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
6410 #define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
6411 #define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
6412 #define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
6413 #define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
6414 #define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
6415 #define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
6416 #define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
6417 #define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
6418 #define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
6419 #define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
6420 #define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
6421 #define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
6422 #define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
6423 #define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
6424 #define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
6425 #define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
6426 #define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
6427 #define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
6428 #define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
6429 #define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
6430 #define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
6431 #define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
6432 #define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
6433 #define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
6434 #define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
6435 #define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
6436 #define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
6437 #define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
6438 #define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
6439 #define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
6440 #define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
6441 #define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
6442 #define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
6443 #define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
6444 #define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
6445 #define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
6446 #define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
6447 #define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
6448 #define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
6449 #define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
6450 #define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
6451 #define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
6452 #define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
6453 #define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
6454 #define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
6455 #define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
6456 #define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
6457 #define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
6458 #define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
6459 #define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
6460 #define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
6461 #define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
6462 #define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
6463 #define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
6464 #define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
6465 #define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
6466 #define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
6467 #define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
6468 #define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
6469 #define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
6470 #define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
6471 #define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
6472 #define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
6473 #define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
6474 #define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
6475 #define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
6476 #define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
6477 #define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
6478 #define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
6479 #define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
6480 #define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
6481 #define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
6482 #define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
6483 #define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
6484 #define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
6485 #define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
6486 #define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
6487 #define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
6488 #define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
6489 #define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
6490 #define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
6491 #define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
6492 #define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
6493 #define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
6494 #define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
6495 #define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
6496 #define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
6497 #define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
6498 #define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
6499 #define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
6500 #define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
6501 #define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
6502 #define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
6503 #define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
6504 #define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
6505 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
6506 #define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
6507 #define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
6508 #define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
6509 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
6510 #define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
6511 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
6512 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
6513 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
6514 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
6515 #define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
6516 #define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
6517 #define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
6518 #define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
6519 #define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
6520 #define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
6521 #define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
6522 #define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
6523 #define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
6524 #define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
6525 #define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
6526 #define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
6527 #define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
6528 #define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
6529 #define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
6530 #define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
6531 #define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
6532 #define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
6533 #define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
6534 #define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
6535 #define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
6536 #define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
6537 #define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
6538 #define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
6539 #define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
6540 #define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
6541 #define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
6542 #define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
6543 #define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
6544 #define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
6545 #define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
6546 #define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
6547 #define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
6548 #define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
6549 #define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
6550 #define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
6551 #define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
6552 #define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
6553 #define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
6554 #define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
6555 #define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
6556 #define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
6557 #define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
6558 #define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
6559 #define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
6560 #define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
6561 #define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
6562 #define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
6563 #define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
6564 #define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
6565 #define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
6566 #define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
6567 #define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
6568 #define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
6569 #define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
6570 #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
6571 #define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
6572 #define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
6573 #define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
6574 #define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
6575 #define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
6576 #define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
6577 #define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
6578 #define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
6579 #define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
6580 #define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
6581 #define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
6582 #define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
6583 #define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
6584 #define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
6585 #define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
6586 #define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
6587 #define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
6588 #define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
6589 #define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
6590 #define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
6591 #define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
6592 #define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
6593 #define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
6594 #define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
6595 #define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
6596 #define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
6597 #define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
6598 #define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
6599 #define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
6600 #define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
6601 #define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
6602 #define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
6603 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
6604 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
6605 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
6606 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
6607 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
6608 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
6609 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
6610 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
6611 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
6612 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
6613 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
6614 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
6615 #define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
6616 #define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
6617 #define MC_SEQ_CMD__ADR_MASK 0xffff
6618 #define MC_SEQ_CMD__ADR__SHIFT 0x0
6619 #define MC_SEQ_CMD__MOP_MASK 0xf0000
6620 #define MC_SEQ_CMD__MOP__SHIFT 0x10
6621 #define MC_SEQ_CMD__END_MASK 0x100000
6622 #define MC_SEQ_CMD__END__SHIFT 0x14
6623 #define MC_SEQ_CMD__CSB_MASK 0x600000
6624 #define MC_SEQ_CMD__CSB__SHIFT 0x15
6625 #define MC_SEQ_CMD__CHAN0_MASK 0x1000000
6626 #define MC_SEQ_CMD__CHAN0__SHIFT 0x18
6627 #define MC_SEQ_CMD__CHAN1_MASK 0x2000000
6628 #define MC_SEQ_CMD__CHAN1__SHIFT 0x19
6629 #define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
6630 #define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
6631 #define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
6632 #define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
6633 #define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
6634 #define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
6635 #define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
6636 #define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
6637 #define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
6638 #define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
6639 #define MC_PMG_CMD_EMRS__END_MASK 0x100000
6640 #define MC_PMG_CMD_EMRS__END__SHIFT 0x14
6641 #define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
6642 #define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
6643 #define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
6644 #define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
6645 #define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
6646 #define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
6647 #define MC_PMG_CMD_MRS__ADR_MASK 0xffff
6648 #define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
6649 #define MC_PMG_CMD_MRS__MOP_MASK 0x70000
6650 #define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
6651 #define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
6652 #define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
6653 #define MC_PMG_CMD_MRS__END_MASK 0x100000
6654 #define MC_PMG_CMD_MRS__END__SHIFT 0x14
6655 #define MC_PMG_CMD_MRS__CSB_MASK 0x600000
6656 #define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
6657 #define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
6658 #define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
6659 #define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
6660 #define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
6661 #define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
6662 #define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
6663 #define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
6664 #define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
6665 #define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
6666 #define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
6667 #define MC_PMG_CMD_MRS1__END_MASK 0x100000
6668 #define MC_PMG_CMD_MRS1__END__SHIFT 0x14
6669 #define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
6670 #define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
6671 #define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
6672 #define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
6673 #define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
6674 #define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
6675 #define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
6676 #define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
6677 #define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
6678 #define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
6679 #define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
6680 #define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
6681 #define MC_PMG_CMD_MRS2__END_MASK 0x100000
6682 #define MC_PMG_CMD_MRS2__END__SHIFT 0x14
6683 #define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
6684 #define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
6685 #define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
6686 #define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
6687 #define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
6688 #define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
6689 #define MC_PMG_CFG__SYC_CLK_MASK 0x1
6690 #define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
6691 #define MC_PMG_CFG__RST_MRS_MASK 0x2
6692 #define MC_PMG_CFG__RST_MRS__SHIFT 0x1
6693 #define MC_PMG_CFG__RST_EMRS_MASK 0x4
6694 #define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
6695 #define MC_PMG_CFG__TRI_MIO_MASK 0x8
6696 #define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
6697 #define MC_PMG_CFG__XSR_TMR_MASK 0xf0
6698 #define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
6699 #define MC_PMG_CFG__RST_MRS1_MASK 0x100
6700 #define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
6701 #define MC_PMG_CFG__RST_MRS2_MASK 0x200
6702 #define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
6703 #define MC_PMG_CFG__DPM_WAKE_MASK 0x400
6704 #define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
6705 #define MC_PMG_CFG__RFS_SRX_MASK 0x1000
6706 #define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
6707 #define MC_PMG_CFG__PREA_SRX_MASK 0x2000
6708 #define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
6709 #define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
6710 #define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
6711 #define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
6712 #define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
6713 #define MC_PMG_CFG__YCLK_ON_MASK 0x200000
6714 #define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
6715 #define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
6716 #define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
6717 #define MC_PMG_CFG__RXPDNB_MASK 0x2000000
6718 #define MC_PMG_CFG__RXPDNB__SHIFT 0x19
6719 #define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
6720 #define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
6721 #define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
6722 #define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
6723 #define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
6724 #define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
6725 #define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
6726 #define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
6727 #define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
6728 #define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
6729 #define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
6730 #define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
6731 #define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
6732 #define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
6733 #define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
6734 #define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
6735 #define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
6736 #define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
6737 #define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
6738 #define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
6739 #define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
6740 #define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
6741 #define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
6742 #define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
6743 #define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
6744 #define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
6745 #define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
6746 #define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
6747 #define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
6748 #define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
6749 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
6750 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
6751 #define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
6752 #define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
6753 #define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
6754 #define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
6755 #define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
6756 #define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
6757 #define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
6758 #define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
6759 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
6760 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
6761 #define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
6762 #define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
6763 #define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
6764 #define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
6765 #define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
6766 #define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
6767 #define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
6768 #define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
6769 #define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
6770 #define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
6771 #define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
6772 #define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
6773 #define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
6774 #define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
6775 #define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
6776 #define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
6777 #define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
6778 #define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
6779 #define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
6780 #define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
6781 #define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
6782 #define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
6783 #define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
6784 #define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
6785 #define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
6786 #define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
6787 #define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
6788 #define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
6789 #define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
6790 #define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
6791 #define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
6792 #define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
6793 #define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
6794 #define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
6795 #define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
6796 #define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
6797 #define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
6798 #define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
6799 #define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
6800 #define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
6801 #define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
6802 #define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
6803 #define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
6804 #define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
6805 #define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
6806 #define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
6807 #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
6808 #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
6809 #define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
6810 #define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
6811 #define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
6812 #define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
6813 #define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
6814 #define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
6815 #define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
6816 #define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
6817 #define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
6818 #define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
6819 #define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
6820 #define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
6821 #define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
6822 #define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
6823 #define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
6824 #define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
6825 #define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
6826 #define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
6827 #define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
6828 #define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
6829 #define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
6830 #define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
6831 #define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
6832 #define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
6833 #define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
6834 #define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
6835 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
6836 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
6837 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
6838 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
6839 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
6840 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
6841 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
6842 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
6843 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
6844 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
6845 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
6846 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
6847 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
6848 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
6849 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
6850 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
6851 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
6852 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
6853 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
6854 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
6855 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
6856 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
6857 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
6858 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
6859 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
6860 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
6861 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
6862 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
6863 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
6864 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
6865 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
6866 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
6867 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
6868 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
6869 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
6870 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
6871 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
6872 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
6873 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
6874 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
6875 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
6876 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
6877 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
6878 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
6879 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
6880 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
6881 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
6882 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
6883 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
6884 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
6885 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
6886 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
6887 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
6888 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
6889 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
6890 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
6891 #define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
6892 #define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
6893 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
6894 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
6895 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
6896 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
6897 #define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
6898 #define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
6899 #define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
6900 #define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
6901 #define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
6902 #define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
6903 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
6904 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
6905 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
6906 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
6907 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
6908 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
6909 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
6910 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
6911 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
6912 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
6913 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
6914 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
6915 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
6916 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
6917 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
6918 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
6919 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
6920 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
6921 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
6922 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
6923 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
6924 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
6925 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
6926 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
6927 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
6928 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
6929 #define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
6930 #define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
6931 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
6932 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
6933 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
6934 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
6935 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
6936 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
6937 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
6938 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
6939 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
6940 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
6941 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
6942 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
6943 #define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
6944 #define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
6945 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
6946 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
6947 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
6948 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
6949 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
6950 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
6951 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
6952 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
6953 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
6954 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
6955 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
6956 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
6957 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
6958 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
6959 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
6960 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
6961 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
6962 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
6963 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
6964 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
6965 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
6966 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
6967 #define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
6968 #define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
6969 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
6970 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
6971 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
6972 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
6973 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
6974 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
6975 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
6976 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
6977 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
6978 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
6979 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
6980 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
6981 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
6982 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
6983 #define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
6984 #define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
6985 #define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
6986 #define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
6987 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
6988 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
6989 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
6990 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
6991 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
6992 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
6993 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
6994 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
6995 #define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
6996 #define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
6997 #define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
6998 #define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
6999 #define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
7000 #define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
7001 #define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
7002 #define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
7003 #define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
7004 #define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
7005 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
7006 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7007 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
7008 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7009 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
7010 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
7011 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7012 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7013 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7014 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7015 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
7016 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
7017 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
7018 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
7019 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
7020 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
7021 #define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
7022 #define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
7023 #define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
7024 #define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
7025 #define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
7026 #define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
7027 #define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
7028 #define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
7029 #define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
7030 #define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
7031 #define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
7032 #define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
7033 #define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
7034 #define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
7035 #define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
7036 #define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
7037 #define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
7038 #define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
7039 #define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
7040 #define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
7041 #define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
7042 #define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
7043 #define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
7044 #define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
7045 #define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
7046 #define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
7047 #define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
7048 #define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
7049 #define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
7050 #define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
7051 #define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
7052 #define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
7053 #define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
7054 #define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
7055 #define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
7056 #define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
7057 #define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
7058 #define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
7059 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
7060 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7061 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
7062 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7063 #define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
7064 #define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
7065 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7066 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7067 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7068 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7069 #define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
7070 #define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
7071 #define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
7072 #define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
7073 #define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
7074 #define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
7075 #define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
7076 #define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
7077 #define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
7078 #define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
7079 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
7080 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
7081 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
7082 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
7083 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
7084 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
7085 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
7086 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
7087 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
7088 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
7089 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
7090 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
7091 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
7092 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
7093 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
7094 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
7095 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
7096 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
7097 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
7098 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
7099 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
7100 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
7101 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
7102 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
7103 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
7104 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
7105 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
7106 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
7107 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
7108 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
7109 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
7110 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
7111 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
7112 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
7113 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
7114 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
7115 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
7116 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7117 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
7118 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7119 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
7120 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
7121 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7122 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7123 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7124 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7125 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
7126 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
7127 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
7128 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
7129 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
7130 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
7131 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
7132 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
7133 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
7134 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
7135 #define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
7136 #define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
7137 #define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
7138 #define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
7139 #define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
7140 #define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
7141 #define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
7142 #define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
7143 #define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
7144 #define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
7145 #define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
7146 #define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
7147 #define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
7148 #define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
7149 #define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
7150 #define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
7151 #define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
7152 #define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
7153 #define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
7154 #define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
7155 #define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
7156 #define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
7157 #define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
7158 #define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
7159 #define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
7160 #define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
7161 #define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
7162 #define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
7163 #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
7164 #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
7165 #define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
7166 #define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
7167 #define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
7168 #define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
7169 #define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
7170 #define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
7171 #define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
7172 #define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
7173 #define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
7174 #define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
7175 #define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
7176 #define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
7177 #define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
7178 #define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
7179 #define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
7180 #define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
7181 #define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
7182 #define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
7183 #define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
7184 #define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
7185 #define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
7186 #define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
7187 #define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
7188 #define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
7189 #define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
7190 #define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
7191 #define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
7192 #define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
7193 #define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
7194 #define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
7195 #define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
7196 #define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
7197 #define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
7198 #define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
7199 #define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
7200 #define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
7201 #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
7202 #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
7203 #define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
7204 #define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
7205 #define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
7206 #define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
7207 #define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
7208 #define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
7209 #define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
7210 #define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
7211 #define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
7212 #define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
7213 #define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
7214 #define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
7215 #define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
7216 #define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
7217 #define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
7218 #define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
7219 #define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
7220 #define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
7221 #define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
7222 #define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
7223 #define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
7224 #define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
7225 #define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
7226 #define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
7227 #define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
7228 #define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
7229 #define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
7230 #define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
7231 #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
7232 #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
7233 #define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
7234 #define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
7235 #define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
7236 #define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
7237 #define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
7238 #define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
7239 #define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
7240 #define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
7241 #define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
7242 #define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
7243 #define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
7244 #define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
7245 #define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
7246 #define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
7247 #define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
7248 #define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
7249 #define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
7250 #define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
7251 #define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
7252 #define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
7253 #define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
7254 #define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
7255 #define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
7256 #define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
7257 #define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
7258 #define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
7259 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
7260 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
7261 #define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
7262 #define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
7263 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
7264 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
7265 #define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
7266 #define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
7267 #define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
7268 #define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
7269 #define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
7270 #define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
7271 #define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
7272 #define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
7273 #define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
7274 #define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
7275 #define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
7276 #define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
7277 #define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
7278 #define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
7279 #define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
7280 #define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
7281 #define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
7282 #define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
7283 #define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
7284 #define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
7285 #define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
7286 #define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
7287 #define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
7288 #define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
7289 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
7290 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
7291 #define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
7292 #define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
7293 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
7294 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
7295 #define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
7296 #define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
7297 #define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
7298 #define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
7299 #define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
7300 #define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
7301 #define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
7302 #define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
7303 #define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
7304 #define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
7305 #define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
7306 #define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
7307 #define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
7308 #define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
7309 #define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
7310 #define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
7311 #define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
7312 #define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
7313 #define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
7314 #define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
7315 #define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
7316 #define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
7317 #define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
7318 #define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
7319 #define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
7320 #define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
7321 #define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
7322 #define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
7323 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
7324 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
7325 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
7326 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
7327 #define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
7328 #define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
7329 #define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
7330 #define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
7331 #define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
7332 #define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
7333 #define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
7334 #define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
7335 #define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
7336 #define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
7337 #define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
7338 #define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
7339 #define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
7340 #define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
7341 #define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
7342 #define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
7343 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
7344 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
7345 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
7346 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
7347 #define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
7348 #define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
7349 #define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
7350 #define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
7351 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
7352 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
7353 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
7354 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
7355 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
7356 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
7357 #define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
7358 #define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
7359 #define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
7360 #define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
7361 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
7362 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
7363 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
7364 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
7365 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
7366 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
7367 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
7368 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
7369 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
7370 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
7371 #define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
7372 #define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
7373 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
7374 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
7375 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
7376 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
7377 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
7378 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
7379 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
7380 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
7381 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
7382 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
7383 #define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
7384 #define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
7385 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
7386 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
7387 #define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
7388 #define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
7389 #define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
7390 #define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
7391 #define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
7392 #define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
7393 #define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
7394 #define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
7395 #define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
7396 #define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
7397 #define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
7398 #define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
7399 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
7400 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
7401 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
7402 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
7403 #define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
7404 #define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
7405 #define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
7406 #define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
7407 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
7408 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
7409 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
7410 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
7411 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
7412 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
7413 #define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
7414 #define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
7415 #define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
7416 #define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
7417 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
7418 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
7419 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
7420 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
7421 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
7422 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
7423 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
7424 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
7425 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
7426 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
7427 #define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
7428 #define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
7429 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
7430 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
7431 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
7432 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
7433 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
7434 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
7435 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
7436 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
7437 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
7438 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
7439 #define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
7440 #define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
7441 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
7442 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
7443 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
7444 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
7445 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
7446 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
7447 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
7448 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
7449 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
7450 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
7451 #define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
7452 #define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
7453 #define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
7454 #define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
7455 #define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
7456 #define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
7457 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
7458 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
7459 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
7460 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
7461 #define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
7462 #define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
7463 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
7464 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
7465 #define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
7466 #define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
7467 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
7468 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
7469 #define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
7470 #define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
7471 #define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
7472 #define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
7473 #define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
7474 #define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
7475 #define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
7476 #define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
7477 #define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
7478 #define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
7479 #define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
7480 #define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
7481 #define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
7482 #define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
7483 #define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
7484 #define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
7485 #define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
7486 #define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
7487 #define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
7488 #define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
7489 #define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
7490 #define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
7491 #define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
7492 #define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
7493 #define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
7494 #define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
7495 #define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
7496 #define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
7497 #define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
7498 #define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
7499 #define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
7500 #define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
7501 #define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
7502 #define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
7503 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
7504 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
7505 #define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
7506 #define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
7507 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
7508 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
7509 #define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
7510 #define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
7511 #define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
7512 #define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
7513 #define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
7514 #define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
7515 #define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
7516 #define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
7517 #define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
7518 #define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
7519 #define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
7520 #define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
7521 #define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
7522 #define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
7523 #define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
7524 #define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
7525 #define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
7526 #define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
7527 #define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
7528 #define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
7529 #define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
7530 #define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
7531 #define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
7532 #define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
7533 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
7534 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
7535 #define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
7536 #define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
7537 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
7538 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
7539 #define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
7540 #define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
7541 #define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
7542 #define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
7543 #define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
7544 #define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
7545 #define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
7546 #define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
7547 #define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
7548 #define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
7549 #define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
7550 #define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
7551 #define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
7552 #define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
7553 #define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
7554 #define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
7555 #define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
7556 #define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
7557 #define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
7558 #define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
7559 #define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
7560 #define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
7561 #define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
7562 #define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
7563 #define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
7564 #define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
7565 #define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
7566 #define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
7567 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
7568 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
7569 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
7570 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
7571 #define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
7572 #define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
7573 #define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
7574 #define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
7575 #define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
7576 #define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
7577 #define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
7578 #define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
7579 #define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
7580 #define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
7581 #define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
7582 #define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
7583 #define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
7584 #define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
7585 #define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
7586 #define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
7587 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
7588 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
7589 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
7590 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
7591 #define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
7592 #define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
7593 #define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
7594 #define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
7595 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
7596 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
7597 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
7598 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
7599 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
7600 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
7601 #define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
7602 #define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
7603 #define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
7604 #define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
7605 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
7606 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
7607 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
7608 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
7609 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
7610 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
7611 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
7612 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
7613 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
7614 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
7615 #define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
7616 #define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
7617 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
7618 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
7619 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
7620 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
7621 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
7622 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
7623 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
7624 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
7625 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
7626 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
7627 #define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
7628 #define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
7629 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
7630 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
7631 #define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
7632 #define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
7633 #define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
7634 #define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
7635 #define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
7636 #define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
7637 #define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
7638 #define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
7639 #define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
7640 #define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
7641 #define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
7642 #define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
7643 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
7644 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
7645 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
7646 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
7647 #define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
7648 #define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
7649 #define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
7650 #define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
7651 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
7652 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
7653 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
7654 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
7655 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
7656 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
7657 #define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
7658 #define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
7659 #define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
7660 #define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
7661 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
7662 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
7663 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
7664 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
7665 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
7666 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
7667 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
7668 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
7669 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
7670 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
7671 #define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
7672 #define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
7673 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
7674 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
7675 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
7676 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
7677 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
7678 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
7679 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
7680 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
7681 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
7682 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
7683 #define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
7684 #define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
7685 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
7686 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
7687 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
7688 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
7689 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
7690 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
7691 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
7692 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
7693 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
7694 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
7695 #define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
7696 #define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
7697 #define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
7698 #define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
7699 #define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
7700 #define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
7701 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
7702 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
7703 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
7704 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
7705 #define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
7706 #define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
7707 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
7708 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
7709 #define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
7710 #define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
7711 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
7712 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
7713 #define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
7714 #define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
7715 #define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
7716 #define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
7717 #define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
7718 #define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
7719 #define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
7720 #define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
7721 #define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
7722 #define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
7723 #define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
7724 #define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
7725 #define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
7726 #define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
7727 #define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
7728 #define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
7729 #define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
7730 #define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
7731 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
7732 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
7733 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
7734 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
7735 #define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
7736 #define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
7737 #define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
7738 #define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
7739 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
7740 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
7741 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
7742 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
7743 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
7744 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
7745 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
7746 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
7747 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
7748 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
7749 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
7750 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
7751 #define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
7752 #define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
7753 #define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
7754 #define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
7755 #define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
7756 #define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
7757 #define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
7758 #define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
7759 #define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
7760 #define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
7761 #define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
7762 #define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
7763 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
7764 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
7765 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
7766 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
7767 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
7768 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
7769 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
7770 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
7771 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
7772 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
7773 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
7774 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
7775 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
7776 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
7777 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
7778 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
7779 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
7780 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
7781 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
7782 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
7783 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
7784 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
7785 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
7786 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
7787 #define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
7788 #define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
7789 #define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
7790 #define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
7791 #define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
7792 #define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
7793 #define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
7794 #define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
7795 #define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
7796 #define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
7797 #define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
7798 #define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
7799 #define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
7800 #define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
7801 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
7802 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
7803 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
7804 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
7805 #define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
7806 #define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
7807 #define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
7808 #define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
7809 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
7810 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
7811 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
7812 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
7813 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
7814 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
7815 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
7816 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
7817 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
7818 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
7819 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
7820 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
7821 #define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
7822 #define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
7823 #define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
7824 #define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
7825 #define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
7826 #define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
7827 #define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
7828 #define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
7829 #define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
7830 #define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
7831 #define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
7832 #define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
7833 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
7834 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
7835 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
7836 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
7837 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
7838 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
7839 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
7840 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
7841 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
7842 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
7843 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
7844 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
7845 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
7846 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
7847 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
7848 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
7849 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
7850 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
7851 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
7852 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
7853 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
7854 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
7855 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
7856 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
7857 #define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
7858 #define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
7859 #define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
7860 #define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
7861 #define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
7862 #define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
7863 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
7864 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
7865 #define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
7866 #define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
7867 #define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
7868 #define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
7869 #define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
7870 #define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
7871 #define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
7872 #define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
7873 #define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
7874 #define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
7875 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
7876 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
7877 #define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
7878 #define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
7879 #define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
7880 #define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
7881 #define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
7882 #define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
7883 #define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
7884 #define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
7885 #define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
7886 #define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
7887 #define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
7888 #define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
7889 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
7890 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
7891 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
7892 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
7893 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
7894 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
7895 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
7896 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
7897 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
7898 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
7899 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
7900 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
7901 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
7902 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
7903 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
7904 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
7905 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
7906 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
7907 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
7908 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
7909 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
7910 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
7911 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
7912 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
7913 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
7914 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
7915 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
7916 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
7917 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
7918 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
7919 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
7920 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
7921 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
7922 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
7923 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
7924 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
7925 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
7926 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
7927 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
7928 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
7929 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
7930 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
7931 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
7932 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
7933 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
7934 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
7935 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
7936 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
7937 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
7938 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
7939 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
7940 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
7941 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
7942 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
7943 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
7944 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
7945 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
7946 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
7947 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
7948 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
7949 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
7950 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
7951 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
7952 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
7953 #define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
7954 #define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
7955 #define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
7956 #define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
7957 #define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
7958 #define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
7959 #define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
7960 #define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
7961 #define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
7962 #define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
7963 #define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
7964 #define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
7965 #define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
7966 #define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
7967 #define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
7968 #define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
7969 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
7970 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
7971 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
7972 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
7973 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
7974 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
7975 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
7976 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
7977 #define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
7978 #define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
7979 #define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
7980 #define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
7981 #define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
7982 #define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
7983 #define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
7984 #define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
7985 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
7986 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
7987 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
7988 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
7989 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
7990 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
7991 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
7992 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
7993 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
7994 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
7995 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
7996 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
7997 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
7998 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
7999 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
8000 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
8001 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
8002 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
8003 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
8004 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
8005 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
8006 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
8007 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
8008 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
8009 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
8010 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
8011 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
8012 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
8013 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
8014 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
8015 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
8016 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
8017 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
8018 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
8019 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
8020 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
8021 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
8022 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
8023 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
8024 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
8025 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
8026 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
8027 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
8028 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
8029 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
8030 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
8031 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
8032 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
8033 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
8034 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
8035 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
8036 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
8037 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
8038 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
8039 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
8040 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
8041 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
8042 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
8043 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
8044 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
8045 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
8046 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
8047 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
8048 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
8049 #define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
8050 #define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
8051 #define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
8052 #define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
8053 #define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
8054 #define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
8055 #define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
8056 #define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
8057 #define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
8058 #define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
8059 #define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
8060 #define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
8061 #define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
8062 #define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
8063 #define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
8064 #define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
8065 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
8066 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
8067 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
8068 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
8069 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
8070 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
8071 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
8072 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
8073 #define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
8074 #define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
8075 #define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
8076 #define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
8077 #define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
8078 #define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
8079 #define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
8080 #define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
8081 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
8082 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
8083 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
8084 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
8085 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
8086 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
8087 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
8088 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
8089 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
8090 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
8091 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
8092 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
8093 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
8094 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
8095 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
8096 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
8097 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
8098 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
8099 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
8100 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
8101 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
8102 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
8103 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
8104 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
8105 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
8106 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
8107 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
8108 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
8109 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
8110 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
8111 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
8112 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
8113 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
8114 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
8115 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
8116 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
8117 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
8118 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
8119 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
8120 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
8121 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
8122 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
8123 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
8124 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
8125 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
8126 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
8127 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
8128 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
8129 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
8130 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
8131 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
8132 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
8133 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
8134 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
8135 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
8136 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
8137 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
8138 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
8139 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
8140 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
8141 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
8142 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
8143 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
8144 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
8145 #define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
8146 #define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
8147 #define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
8148 #define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
8149 #define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
8150 #define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
8151 #define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
8152 #define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
8153 #define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
8154 #define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
8155 #define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
8156 #define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
8157 #define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
8158 #define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
8159 #define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
8160 #define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
8161 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
8162 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
8163 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
8164 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
8165 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
8166 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
8167 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
8168 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
8169 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
8170 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
8171 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
8172 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
8173 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
8174 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
8175 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
8176 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
8177 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
8178 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
8179 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
8180 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
8181 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
8182 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
8183 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
8184 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
8185 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
8186 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
8187 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
8188 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
8189 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
8190 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
8191 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
8192 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
8193 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
8194 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
8195 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
8196 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
8197 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
8198 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
8199 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
8200 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
8201 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
8202 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
8203 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
8204 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
8205 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
8206 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
8207 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
8208 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
8209 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
8210 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
8211 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
8212 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
8213 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
8214 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
8215 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
8216 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
8217 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
8218 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
8219 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
8220 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
8221 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
8222 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
8223 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
8224 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
8225 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
8226 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
8227 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
8228 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
8229 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
8230 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
8231 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
8232 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
8233 #define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
8234 #define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
8235 #define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
8236 #define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
8237 #define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
8238 #define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
8239 #define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
8240 #define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
8241 #define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
8242 #define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
8243 #define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
8244 #define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
8245 #define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
8246 #define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
8247 #define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
8248 #define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
8249 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
8250 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
8251 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
8252 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
8253 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
8254 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
8255 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
8256 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
8257 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
8258 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
8259 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
8260 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
8261 #define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
8262 #define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
8263 #define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
8264 #define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
8265 #define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
8266 #define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
8267 #define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
8268 #define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
8269 #define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
8270 #define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
8271 #define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
8272 #define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
8273 #define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
8274 #define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
8275 #define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
8276 #define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
8277 #define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
8278 #define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
8279 #define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
8280 #define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
8281 #define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
8282 #define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
8283 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
8284 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
8285 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
8286 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
8287 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
8288 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
8289 #define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
8290 #define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
8291 #define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
8292 #define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
8293 #define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
8294 #define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
8295 #define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
8296 #define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
8297 #define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
8298 #define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
8299 #define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
8300 #define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
8301 #define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
8302 #define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
8303 #define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
8304 #define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
8305 #define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
8306 #define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
8307 #define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
8308 #define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
8309 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
8310 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
8311 #define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
8312 #define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
8313 #define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
8314 #define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
8315 #define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
8316 #define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
8317 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
8318 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
8319 #define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
8320 #define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
8321 #define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
8322 #define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
8323 #define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
8324 #define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
8325 #define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
8326 #define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
8327 #define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
8328 #define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
8329 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
8330 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
8331 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
8332 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
8333 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
8334 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
8335 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
8336 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
8337 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
8338 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
8339 #define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
8340 #define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
8341 #define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
8342 #define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
8343 #define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
8344 #define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
8345 #define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
8346 #define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
8347 #define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
8348 #define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
8349 #define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
8350 #define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
8351 #define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
8352 #define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
8353 #define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
8354 #define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
8355 #define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
8356 #define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
8357 #define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
8358 #define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
8359 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
8360 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
8361 #define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
8362 #define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
8363 #define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
8364 #define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
8365 #define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
8366 #define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
8367 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
8368 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
8369 #define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
8370 #define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
8371 #define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
8372 #define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
8373 #define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
8374 #define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
8375 #define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
8376 #define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
8377 #define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
8378 #define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
8379 #define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
8380 #define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
8381 #define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
8382 #define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
8383 #define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
8384 #define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
8385 #define MC_BIST_CMD_CNTL__RESET_MASK 0x1
8386 #define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
8387 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
8388 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
8389 #define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
8390 #define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
8391 #define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
8392 #define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
8393 #define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
8394 #define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
8395 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
8396 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
8397 #define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
8398 #define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
8399 #define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
8400 #define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
8401 #define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
8402 #define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
8403 #define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
8404 #define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
8405 #define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
8406 #define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
8407 #define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
8408 #define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
8409 #define MC_BIST_CNTL__RESET_MASK 0x1
8410 #define MC_BIST_CNTL__RESET__SHIFT 0x0
8411 #define MC_BIST_CNTL__RUN_MASK 0x2
8412 #define MC_BIST_CNTL__RUN__SHIFT 0x1
8413 #define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
8414 #define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
8415 #define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
8416 #define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
8417 #define MC_BIST_CNTL__MOP_MODE_MASK 0x10
8418 #define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
8419 #define MC_BIST_CNTL__ADR_MODE_MASK 0x20
8420 #define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
8421 #define MC_BIST_CNTL__DAT_MODE_MASK 0x40
8422 #define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
8423 #define MC_BIST_CNTL__LOOP_MASK 0xc00
8424 #define MC_BIST_CNTL__LOOP__SHIFT 0xa
8425 #define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
8426 #define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
8427 #define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
8428 #define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
8429 #define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
8430 #define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
8431 #define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
8432 #define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
8433 #define MC_BIST_CNTL__DONE_MASK 0x40000000
8434 #define MC_BIST_CNTL__DONE__SHIFT 0x1e
8435 #define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
8436 #define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
8437 #define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
8438 #define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
8439 #define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
8440 #define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
8441 #define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
8442 #define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
8443 #define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
8444 #define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
8445 #define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
8446 #define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
8447 #define MC_BIST_DIR_CNTL__MOP_MASK 0x7
8448 #define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
8449 #define MC_BIST_DIR_CNTL__EOB_MASK 0x8
8450 #define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
8451 #define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
8452 #define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
8453 #define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
8454 #define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
8455 #define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
8456 #define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
8457 #define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
8458 #define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
8459 #define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
8460 #define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
8461 #define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
8462 #define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
8463 #define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
8464 #define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
8465 #define MC_BIST_SADDR__COL_MASK 0x3ff
8466 #define MC_BIST_SADDR__COL__SHIFT 0x0
8467 #define MC_BIST_SADDR__ROW_MASK 0xfffc00
8468 #define MC_BIST_SADDR__ROW__SHIFT 0xa
8469 #define MC_BIST_SADDR__BANK_MASK 0xf000000
8470 #define MC_BIST_SADDR__BANK__SHIFT 0x18
8471 #define MC_BIST_SADDR__RANK_MASK 0x10000000
8472 #define MC_BIST_SADDR__RANK__SHIFT 0x1c
8473 #define MC_BIST_SADDR__COLH_MASK 0x20000000
8474 #define MC_BIST_SADDR__COLH__SHIFT 0x1d
8475 #define MC_BIST_SADDR__ROWH_MASK 0xc0000000
8476 #define MC_BIST_SADDR__ROWH__SHIFT 0x1e
8477 #define MC_BIST_EADDR__COL_MASK 0x3ff
8478 #define MC_BIST_EADDR__COL__SHIFT 0x0
8479 #define MC_BIST_EADDR__ROW_MASK 0xfffc00
8480 #define MC_BIST_EADDR__ROW__SHIFT 0xa
8481 #define MC_BIST_EADDR__BANK_MASK 0xf000000
8482 #define MC_BIST_EADDR__BANK__SHIFT 0x18
8483 #define MC_BIST_EADDR__RANK_MASK 0x10000000
8484 #define MC_BIST_EADDR__RANK__SHIFT 0x1c
8485 #define MC_BIST_EADDR__COLH_MASK 0x20000000
8486 #define MC_BIST_EADDR__COLH__SHIFT 0x1d
8487 #define MC_BIST_EADDR__ROWH_MASK 0xc0000000
8488 #define MC_BIST_EADDR__ROWH__SHIFT 0x1e
8489 #define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
8490 #define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
8491 #define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
8492 #define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
8493 #define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
8494 #define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
8495 #define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
8496 #define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
8497 #define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
8498 #define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
8499 #define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
8500 #define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
8501 #define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
8502 #define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
8503 #define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
8504 #define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
8505 #define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
8506 #define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
8507 #define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
8508 #define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
8509 #define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
8510 #define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
8511 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
8512 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
8513 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
8514 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
8515 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
8516 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
8517 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
8518 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
8519 #define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
8520 #define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
8521 #define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
8522 #define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
8523 #define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
8524 #define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
8525 #define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
8526 #define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
8527 #define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
8528 #define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
8529 #define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
8530 #define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
8531 #define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
8532 #define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
8533 #define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
8534 #define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
8535 #define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
8536 #define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
8537 #define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
8538 #define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
8539 #define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
8540 #define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
8541 #define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
8542 #define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
8543 #define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
8544 #define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
8545 #define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
8546 #define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
8547 #define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
8548 #define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
8549 #define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
8550 #define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
8551 #define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
8552 #define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
8553 #define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
8554 #define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
8555 #define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
8556 #define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
8557 #define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
8558 #define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
8559 #define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
8560 #define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
8561 #define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
8562 #define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
8563 #define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
8564 #define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
8565 #define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
8566 #define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
8567 #define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
8568 #define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
8569 #define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
8570 #define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
8571 #define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
8572 #define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
8573 #define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
8574 #define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
8575 #define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
8576 #define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
8577 #define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
8578 #define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
8579 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
8580 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
8581 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
8582 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
8583 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
8584 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
8585 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
8586 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
8587 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
8588 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
8589 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
8590 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
8591 #define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
8592 #define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
8593 #define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
8594 #define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
8595 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
8596 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
8597 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
8598 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
8599 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
8600 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
8601 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
8602 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
8603 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
8604 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
8605 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
8606 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
8607 #define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
8608 #define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
8609 #define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
8610 #define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
8611 #define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
8612 #define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
8613 #define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
8614 #define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
8615 #define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
8616 #define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
8617 #define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
8618 #define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
8619 #define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
8620 #define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
8621 #define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
8622 #define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
8623 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
8624 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
8625 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
8626 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
8627 #define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
8628 #define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
8629 #define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
8630 #define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
8631 #define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
8632 #define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
8633 #define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
8634 #define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
8635 #define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
8636 #define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
8637 #define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
8638 #define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
8639 #define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
8640 #define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
8641 #define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
8642 #define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
8643 #define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
8644 #define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
8645 #define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
8646 #define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
8647 #define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
8648 #define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
8649 #define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
8650 #define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
8651 #define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
8652 #define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
8653 #define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
8654 #define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
8655 #define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
8656 #define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
8657 #define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
8658 #define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
8659 #define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
8660 #define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
8661 #define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
8662 #define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
8663 #define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
8664 #define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
8665 #define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
8666 #define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
8667 #define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
8668 #define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
8669 #define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
8670 #define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
8671 #define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
8672 #define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
8673 #define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
8674 #define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
8675 #define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
8676 #define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
8677 #define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
8678 #define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
8679 #define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
8680 #define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
8681 #define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
8682 #define MC_SEQ_MISC0__VALUE__SHIFT 0x0
8683 #define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
8684 #define MC_SEQ_MISC1__VALUE__SHIFT 0x0
8685 #define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL_MASK 0x1
8686 #define MC_SEQ_RESERVE_0_S__MCLK_GCK_SEL__SHIFT 0x0
8687 #define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xfffffffe
8688 #define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x1
8689 #define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
8690 #define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
8691 #define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
8692 #define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
8693 #define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
8694 #define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
8695 #define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
8696 #define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
8697 #define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
8698 #define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
8699 #define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
8700 #define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
8701 #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
8702 #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
8703 #define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
8704 #define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
8705 #define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
8706 #define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
8707 #define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
8708 #define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
8709 #define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
8710 #define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
8711 #define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
8712 #define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
8713 #define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
8714 #define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
8715 #define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
8716 #define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
8717 #define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
8718 #define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
8719 #define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
8720 #define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
8721 #define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
8722 #define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
8723 #define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
8724 #define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
8725 #define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
8726 #define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
8727 #define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
8728 #define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
8729 #define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
8730 #define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
8731 #define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
8732 #define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
8733 #define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
8734 #define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
8735 #define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
8736 #define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
8737 #define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
8738 #define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
8739 #define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
8740 #define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
8741 #define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
8742 #define MC_SEQ_MISC3__VALUE__SHIFT 0x0
8743 #define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
8744 #define MC_SEQ_MISC4__VALUE__SHIFT 0x0
8745 #define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
8746 #define MC_SEQ_MISC5__VALUE__SHIFT 0x0
8747 #define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
8748 #define MC_SEQ_MISC6__VALUE__SHIFT 0x0
8749 #define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
8750 #define MC_SEQ_MISC7__VALUE__SHIFT 0x0
8751 #define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
8752 #define MC_SEQ_MISC8__VALUE__SHIFT 0x0
8753 #define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
8754 #define MC_SEQ_MISC9__VALUE__SHIFT 0x0
8755 #define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
8756 #define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
8757 #define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
8758 #define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
8759 #define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
8760 #define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
8761 #define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
8762 #define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
8763 #define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
8764 #define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
8765 #define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
8766 #define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
8767 #define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
8768 #define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
8769 #define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
8770 #define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
8771 #define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
8772 #define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
8773 #define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
8774 #define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
8775 #define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
8776 #define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
8777 #define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
8778 #define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
8779 #define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
8780 #define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
8781 #define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
8782 #define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
8783 #define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
8784 #define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
8785 #define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
8786 #define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
8787 #define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
8788 #define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
8789 #define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
8790 #define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
8791 #define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
8792 #define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
8793 #define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
8794 #define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
8795 #define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
8796 #define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
8797 #define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
8798 #define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
8799 #define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
8800 #define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
8801 #define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
8802 #define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
8803 #define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
8804 #define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
8805 #define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
8806 #define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
8807 #define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
8808 #define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
8809 #define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
8810 #define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
8811 #define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
8812 #define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
8813 #define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
8814 #define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
8815 #define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
8816 #define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
8817 #define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
8818 #define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
8819 #define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
8820 #define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
8821 #define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
8822 #define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
8823 #define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
8824 #define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
8825 #define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
8826 #define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
8827 #define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
8828 #define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
8829 #define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
8830 #define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
8831 #define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
8832 #define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
8833 #define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
8834 #define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
8835 #define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
8836 #define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
8837 #define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
8838 #define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
8839 #define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
8840 #define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
8841 #define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
8842 #define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
8843 #define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
8844 #define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
8845 #define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
8846 #define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
8847 #define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
8848 #define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
8849 #define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
8850 #define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
8851 #define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
8852 #define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
8853 #define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
8854 #define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
8855 #define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
8856 #define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
8857 #define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
8858 #define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
8859 #define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
8860 #define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
8861 #define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
8862 #define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
8863 #define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
8864 #define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
8865 #define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
8866 #define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
8867 #define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
8868 #define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
8869 #define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
8870 #define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
8871 #define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
8872 #define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
8873 #define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
8874 #define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
8875 #define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
8876 #define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
8877 #define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
8878 #define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
8879 #define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
8880 #define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
8881 #define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
8882 #define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
8883 #define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
8884 #define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
8885 #define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
8886 #define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
8887 #define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
8888 #define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
8889 #define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
8890 #define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
8891 #define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
8892 #define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
8893 #define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
8894 #define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
8895 #define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
8896 #define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
8897 #define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
8898 #define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
8899 #define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
8900 #define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
8901 #define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
8902 #define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
8903 #define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
8904 #define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
8905 #define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
8906 #define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
8907 #define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
8908 #define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
8909 #define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
8910 #define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
8911 #define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
8912 #define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
8913 #define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
8914 #define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
8915 #define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
8916 #define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
8917 #define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
8918 #define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
8919 #define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
8920 #define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
8921 #define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
8922 #define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
8923 #define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
8924 #define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
8925 #define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
8926 #define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
8927 #define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
8928 #define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
8929 #define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
8930 #define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
8931 #define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
8932 #define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
8933 #define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
8934 #define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
8935 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
8936 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
8937 #define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
8938 #define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
8939 #define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
8940 #define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
8941 #define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
8942 #define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
8943 #define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
8944 #define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
8945 #define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
8946 #define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
8947 #define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
8948 #define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
8949 #define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
8950 #define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
8951 #define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
8952 #define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
8953 #define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
8954 #define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
8955 #define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
8956 #define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
8957 #define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
8958 #define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
8959 #define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
8960 #define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
8961 #define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
8962 #define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
8963 #define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
8964 #define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
8965 #define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
8966 #define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
8967 #define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
8968 #define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
8969 #define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
8970 #define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
8971 #define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
8972 #define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
8973 #define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
8974 #define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
8975 #define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
8976 #define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
8977 #define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
8978 #define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
8979 #define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
8980 #define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
8981 #define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
8982 #define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
8983 #define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
8984 #define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
8985 #define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
8986 #define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
8987 #define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
8988 #define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
8989 #define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
8990 #define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
8991 #define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
8992 #define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
8993 #define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
8994 #define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
8995 #define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
8996 #define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
8997 #define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
8998 #define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
8999 #define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
9000 #define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
9001 #define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
9002 #define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
9003 #define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
9004 #define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
9005 #define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
9006 #define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
9007 #define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
9008 #define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
9009 #define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
9010 #define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
9011 #define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
9012 #define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
9013 #define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
9014 #define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
9015 #define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
9016 #define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
9017 #define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
9018 #define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
9019 #define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
9020 #define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
9021 #define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
9022 #define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
9023 #define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
9024 #define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
9025 #define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
9026 #define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
9027 #define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
9028 #define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
9029 #define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
9030 #define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
9031 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
9032 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
9033 #define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
9034 #define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
9035 #define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
9036 #define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
9037 #define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
9038 #define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
9039 #define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
9040 #define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
9041 #define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
9042 #define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
9043 #define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
9044 #define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
9045 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
9046 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
9047 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
9048 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
9049 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
9050 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
9051 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
9052 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
9053 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
9054 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
9055 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
9056 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
9057 #define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
9058 #define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
9059 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
9060 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
9061 #define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
9062 #define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
9063 #define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
9064 #define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
9065 #define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
9066 #define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
9067 #define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
9068 #define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
9069 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
9070 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
9071 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
9072 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
9073 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
9074 #define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
9075 #define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
9076 #define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
9077 #define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
9078 #define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
9079 #define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
9080 #define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
9081 #define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
9082 #define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
9083 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
9084 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
9085 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
9086 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
9087 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
9088 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
9089 #define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
9090 #define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
9091 #define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
9092 #define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
9093 #define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
9094 #define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
9095 #define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
9096 #define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
9097 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
9098 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
9099 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
9100 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
9101 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
9102 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
9103 #define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
9104 #define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
9105 #define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
9106 #define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
9107 #define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
9108 #define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
9109 #define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
9110 #define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
9111 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
9112 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
9113 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
9114 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
9115 #define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
9116 #define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
9117 #define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
9118 #define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
9119 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
9120 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
9121 #define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
9122 #define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
9123 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
9124 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
9125 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
9126 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
9127 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
9128 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
9129 #define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
9130 #define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
9131 #define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
9132 #define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
9133 #define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
9134 #define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
9135 #define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
9136 #define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
9137 #define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
9138 #define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
9139 #define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
9140 #define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
9141 #define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
9142 #define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
9143 #define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
9144 #define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
9145 #define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
9146 #define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
9147 #define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
9148 #define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
9149 #define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
9150 #define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
9151 #define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
9152 #define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
9153 #define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
9154 #define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
9155 #define MC_SEQ_TCG_CNTL__START_MASK 0x8
9156 #define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
9157 #define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
9158 #define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
9159 #define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
9160 #define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
9161 #define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
9162 #define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
9163 #define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
9164 #define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
9165 #define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
9166 #define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
9167 #define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
9168 #define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
9169 #define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
9170 #define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
9171 #define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
9172 #define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
9173 #define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
9174 #define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
9175 #define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
9176 #define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
9177 #define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
9178 #define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
9179 #define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
9180 #define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
9181 #define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
9182 #define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
9183 #define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
9184 #define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
9185 #define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
9186 #define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
9187 #define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
9188 #define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
9189 #define MC_SEQ_TSM_CTRL__START_MASK 0x1
9190 #define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
9191 #define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
9192 #define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
9193 #define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
9194 #define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
9195 #define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
9196 #define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
9197 #define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
9198 #define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
9199 #define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
9200 #define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
9201 #define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
9202 #define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
9203 #define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
9204 #define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
9205 #define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
9206 #define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
9207 #define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
9208 #define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
9209 #define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
9210 #define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
9211 #define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
9212 #define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
9213 #define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
9214 #define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
9215 #define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
9216 #define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
9217 #define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
9218 #define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
9219 #define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
9220 #define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
9221 #define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
9222 #define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
9223 #define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
9224 #define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
9225 #define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
9226 #define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
9227 #define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
9228 #define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
9229 #define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
9230 #define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
9231 #define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
9232 #define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
9233 #define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
9234 #define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
9235 #define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
9236 #define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
9237 #define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
9238 #define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
9239 #define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
9240 #define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
9241 #define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
9242 #define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
9243 #define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
9244 #define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
9245 #define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
9246 #define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
9247 #define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
9248 #define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
9249 #define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
9250 #define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
9251 #define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
9252 #define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
9253 #define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
9254 #define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
9255 #define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
9256 #define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
9257 #define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
9258 #define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
9259 #define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
9260 #define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
9261 #define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
9262 #define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
9263 #define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
9264 #define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
9265 #define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
9266 #define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
9267 #define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
9268 #define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
9269 #define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
9270 #define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
9271 #define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
9272 #define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
9273 #define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
9274 #define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
9275 #define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
9276 #define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
9277 #define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
9278 #define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
9279 #define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
9280 #define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
9281 #define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
9282 #define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
9283 #define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
9284 #define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
9285 #define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
9286 #define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
9287 #define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
9288 #define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
9289 #define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
9290 #define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
9291 #define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
9292 #define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
9293 #define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
9294 #define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
9295 #define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
9296 #define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
9297 #define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
9298 #define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
9299 #define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
9300 #define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
9301 #define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
9302 #define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
9303 #define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
9304 #define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
9305 #define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
9306 #define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
9307 #define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
9308 #define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
9309 #define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
9310 #define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
9311 #define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
9312 #define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
9313 #define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
9314 #define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
9315 #define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
9316 #define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
9317 #define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
9318 #define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
9319 #define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
9320 #define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
9321 #define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
9322 #define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
9323 #define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
9324 #define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
9325 #define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
9326 #define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
9327 #define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
9328 #define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
9329 #define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
9330 #define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
9331 #define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
9332 #define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
9333 #define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
9334 #define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
9335 #define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
9336 #define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
9337 #define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
9338 #define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
9339 #define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
9340 #define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
9341 #define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
9342 #define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
9343 #define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
9344 #define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
9345 #define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
9346 #define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
9347 #define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
9348 #define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
9349 #define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
9350 #define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
9351 #define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
9352 #define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
9353 #define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
9354 #define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
9355 #define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
9356 #define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
9357 #define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
9358 #define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
9359 #define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
9360 #define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
9361 #define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
9362 #define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
9363 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
9364 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
9365 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
9366 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
9367 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
9368 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
9369 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
9370 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
9371 #define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
9372 #define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
9373 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
9374 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
9375 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
9376 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
9377 #define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
9378 #define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
9379 #define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
9380 #define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
9381 #define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
9382 #define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
9383 #define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
9384 #define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
9385 #define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
9386 #define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
9387 #define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
9388 #define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
9389 #define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
9390 #define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
9391 #define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
9392 #define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
9393 #define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
9394 #define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
9395 #define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
9396 #define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
9397 #define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
9398 #define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
9399 #define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
9400 #define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
9401 #define DLL_CNTL__PWR2_MODE_MASK 0x4000000
9402 #define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
9403 #define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
9404 #define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
9405 #define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
9406 #define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
9407 #define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
9408 #define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
9409 #define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
9410 #define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
9411 #define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
9412 #define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
9413 #define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
9414 #define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
9415 #define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
9416 #define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
9417 #define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
9418 #define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
9419 #define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
9420 #define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
9421 #define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
9422 #define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
9423 #define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
9424 #define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
9425 #define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
9426 #define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
9427 #define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
9428 #define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
9429 #define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
9430 #define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
9431 #define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
9432 #define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
9433 #define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
9434 #define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
9435 #define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
9436 #define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
9437 #define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
9438 #define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
9439 #define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
9440 #define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
9441 #define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
9442 #define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
9443 #define MPLL_CNTL_MODE__QDR_MASK 0x2000
9444 #define MPLL_CNTL_MODE__QDR__SHIFT 0xd
9445 #define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
9446 #define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
9447 #define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
9448 #define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
9449 #define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
9450 #define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
9451 #define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
9452 #define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
9453 #define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
9454 #define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
9455 #define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
9456 #define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
9457 #define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
9458 #define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
9459 #define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
9460 #define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
9461 #define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
9462 #define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
9463 #define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
9464 #define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
9465 #define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
9466 #define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
9467 #define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
9468 #define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
9469 #define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
9470 #define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
9471 #define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
9472 #define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
9473 #define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
9474 #define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
9475 #define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
9476 #define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
9477 #define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
9478 #define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
9479 #define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
9480 #define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
9481 #define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
9482 #define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
9483 #define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
9484 #define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
9485 #define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
9486 #define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
9487 #define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
9488 #define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
9489 #define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
9490 #define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
9491 #define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
9492 #define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
9493 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
9494 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
9495 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
9496 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
9497 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
9498 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
9499 #define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
9500 #define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
9501 #define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
9502 #define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
9503 #define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
9504 #define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
9505 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
9506 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
9507 #define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
9508 #define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
9509 #define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
9510 #define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
9511 #define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
9512 #define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
9513 #define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
9514 #define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
9515 #define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
9516 #define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
9517 #define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
9518 #define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
9519 #define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
9520 #define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
9521 #define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
9522 #define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
9523 #define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
9524 #define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
9525 #define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
9526 #define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
9527 #define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
9528 #define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
9529 #define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
9530 #define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
9531 #define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
9532 #define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
9533 #define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
9534 #define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
9535 #define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
9536 #define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
9537 #define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
9538 #define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
9539 #define MPLL_SS1__CLKV_MASK 0x3ffffff
9540 #define MPLL_SS1__CLKV__SHIFT 0x0
9541 #define MPLL_SS1__SPARE_MASK 0xfc000000
9542 #define MPLL_SS1__SPARE__SHIFT 0x1a
9543 #define MPLL_SS2__CLKS_MASK 0xfff
9544 #define MPLL_SS2__CLKS__SHIFT 0x0
9545 #define MPLL_SS2__SPARE_MASK 0xfffff000
9546 #define MPLL_SS2__SPARE__SHIFT 0xc
9547 #define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
9548 #define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
9549 #define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
9550 #define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
9551 #define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
9552 #define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
9553 #define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
9554 #define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
9555 #define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
9556 #define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
9557 #define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
9558 #define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
9559 #define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
9560 #define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
9561 #define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
9562 #define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
9563 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
9564 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
9565 #define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
9566 #define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
9567 #define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
9568 #define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
9569 #define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
9570 #define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
9571 #define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
9572 #define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
9573 #define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
9574 #define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
9575 #define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
9576 #define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
9577 #define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
9578 #define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
9579 #define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
9580 #define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
9581 #define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
9582 #define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
9583 #define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
9584 #define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
9585 #define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
9586 #define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
9587 #define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
9588 #define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
9589 #define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
9590 #define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
9591 #define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
9592 #define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
9593 #define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
9594 #define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
9595 #define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
9596 #define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
9597 #define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
9598 #define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
9599 #define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
9600 #define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
9601 #define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
9602 #define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
9603 #define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
9604 #define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
9605 #define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
9606 #define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
9607 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
9608 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
9609 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
9610 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
9611 #define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
9612 #define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
9613 #define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
9614 #define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
9615 #define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
9616 #define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
9617 #define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
9618 #define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
9619 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
9620 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
9621 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
9622 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
9623 #define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
9624 #define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
9625 #define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
9626 #define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
9627 #define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
9628 #define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
9629 #define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
9630 #define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
9631 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
9632 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
9633 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
9634 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
9635 #define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
9636 #define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
9637 #define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
9638 #define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
9639 #define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
9640 #define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
9641 #define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
9642 #define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
9643 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
9644 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
9645 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
9646 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
9647 #define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
9648 #define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
9649 #define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
9650 #define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
9651 #define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
9652 #define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
9653 #define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
9654 #define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
9655 #define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
9656 #define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
9657 #define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
9658 #define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
9659 #define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
9660 #define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
9661 #define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
9662 #define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
9663 #define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
9664 #define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
9665 #define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
9666 #define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
9667 #define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
9668 #define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
9669 #define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
9670 #define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
9671 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
9672 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
9673 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
9674 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
9675 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
9676 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
9677 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
9678 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
9679 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
9680 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
9681 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
9682 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
9683 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
9684 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
9685 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
9686 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
9687 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
9688 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
9689 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
9690 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
9691 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
9692 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
9693 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
9694 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
9695 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
9696 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
9697 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
9698 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
9699 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
9700 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
9701 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
9702 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
9703 #define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
9704 #define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
9705 #define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
9706 #define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
9707 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
9708 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
9709 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
9710 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
9711 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
9712 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
9713 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
9714 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
9715 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
9716 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
9717 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
9718 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
9719 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
9720 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
9721 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
9722 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
9723 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
9724 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
9725 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
9726 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
9727 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
9728 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
9729 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
9730 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
9731 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
9732 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
9733 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
9734 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
9735 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
9736 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
9737 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
9738 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
9739 #define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
9740 #define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
9741 #define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
9742 #define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
9743 #define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
9744 #define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
9745 #define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
9746 #define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
9747 #define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
9748 #define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
9749 #define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
9750 #define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
9751 #define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
9752 #define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
9753 #define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
9754 #define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
9755 #define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
9756 #define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
9757 #define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
9758 #define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
9759 #define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
9760 #define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
9761 #define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
9762 #define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
9763 #define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
9764 #define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
9765 #define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
9766 #define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
9767 #define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
9768 #define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
9769 #define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
9770 #define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
9771 #define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
9772 #define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
9773 #define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
9774 #define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
9775 #define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
9776 #define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
9777 #define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
9778 #define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
9779 #define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
9780 #define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
9781 #define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
9782 #define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
9783 #define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
9784 #define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
9785 #define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
9786 #define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
9787 #define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
9788 #define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
9789 #define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
9790 #define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
9791 #define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
9792 #define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
9793 #define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
9794 #define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
9795 #define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
9796 #define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
9797 #define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
9798 #define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
9799 #define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
9800 #define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
9801 #define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
9802 #define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
9803 #define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
9804 #define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
9805 #define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
9806 #define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
9807 #define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
9808 #define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
9809 #define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
9810 #define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
9811 #define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
9812 #define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
9813 #define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
9814 #define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
9815 #define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
9816 #define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
9817 #define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
9818 #define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
9819 #define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
9820 #define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
9821 #define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
9822 #define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
9823 #define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
9824 #define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
9825 #define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
9826 #define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
9827 #define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
9828 #define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
9829 #define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
9830 #define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
9831 #define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
9832 #define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
9833 #define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
9834 #define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
9835 #define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
9836 #define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
9837 #define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
9838 #define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
9839 #define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
9840 #define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
9841 #define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
9842 #define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
9843 #define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
9844 #define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
9845 #define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
9846 #define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
9847 #define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
9848 #define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
9849 #define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
9850 #define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
9851 #define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
9852 #define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
9853 #define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
9854 #define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
9855 #define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
9856 #define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
9857 #define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
9858 #define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
9859 #define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
9860 #define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
9861 #define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
9862 #define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
9863 #define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
9864 #define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
9865 #define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
9866 #define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
9867 #define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
9868 #define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
9869 #define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
9870 #define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
9871 #define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
9872 #define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
9873 #define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
9874 #define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
9875 #define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
9876 #define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
9877 #define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
9878 #define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
9879 #define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
9880 #define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
9881 #define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
9882 #define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
9883 #define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
9884 #define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
9885 #define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
9886 #define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
9887 #define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
9888 #define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
9889 #define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
9890 #define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
9891 #define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
9892 #define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
9893 #define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
9894 #define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
9895 #define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
9896 #define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
9897 #define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
9898 #define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
9899 #define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
9900 #define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
9901 #define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
9902 #define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
9903 #define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
9904 #define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
9905 #define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
9906 #define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
9907 #define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
9908 #define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
9909 #define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
9910 #define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
9911 #define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
9912 #define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
9913 #define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
9914 #define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
9915 #define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
9916 #define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
9917 #define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
9918 #define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
9919 #define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
9920 #define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
9921 #define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
9922 #define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
9923 #define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
9924 #define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
9925 #define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
9926 #define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
9927 #define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
9928 #define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
9929 #define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
9930 #define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
9931 #define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
9932 #define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
9933 #define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
9934 #define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
9935 #define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
9936 #define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
9937 #define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
9938 #define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
9939 #define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
9940 #define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
9941 #define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
9942 #define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
9943 #define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
9944 #define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
9945 #define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
9946 #define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
9947 #define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
9948 #define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
9949 #define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
9950 #define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
9951 #define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
9952 #define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
9953 #define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
9954 #define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
9955 #define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
9956 #define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
9957 #define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
9958 #define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
9959 #define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
9960 #define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
9961 #define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
9962 #define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
9963 #define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
9964 #define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
9965 #define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
9966 #define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
9967 #define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
9968 #define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
9969 #define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
9970 #define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
9971 #define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
9972 #define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
9973 #define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
9974 #define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
9975 #define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
9976 #define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
9977 #define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
9978 #define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
9979 #define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
9980 #define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
9981 #define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
9982 #define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
9983 #define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
9984 #define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
9985 #define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
9986 #define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
9987 #define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
9988 #define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
9989 #define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
9990 #define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
9991 #define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
9992 #define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
9993 #define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
9994 #define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
9995 #define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
9996 #define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
9997 #define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
9998 #define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
9999 #define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
10000 #define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
10001 #define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
10002 #define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
10003 #define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
10004 #define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
10005 #define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
10006 #define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
10007 #define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
10008 #define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
10009 #define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
10010 #define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
10011 #define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
10012 #define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
10013 #define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
10014 #define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
10015 #define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
10016 #define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
10017 #define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
10018 #define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
10019 #define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
10020 #define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
10021 #define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
10022 #define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
10023 #define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
10024 #define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
10025 #define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
10026 #define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
10027 #define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
10028 #define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
10029 #define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
10030 #define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
10031 #define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
10032 #define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
10033 #define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
10034 #define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
10035 #define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
10036 #define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
10037 #define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
10038 #define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
10039 #define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
10040 #define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
10041 #define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
10042 #define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
10043 #define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
10044 #define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
10045 #define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
10046 #define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
10047 #define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
10048 #define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
10049 #define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
10050 #define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
10051 #define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
10052 #define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
10053 #define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
10054 #define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
10055 #define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
10056 #define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
10057 #define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
10058 #define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
10059 #define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
10060 #define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
10061 #define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
10062 #define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
10063 #define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
10064 #define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
10065 #define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
10066 #define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
10067 #define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
10068 #define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
10069 #define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
10070 #define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
10071 #define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
10072 #define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
10073 #define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
10074 #define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
10075 #define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
10076 #define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
10077 #define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
10078 #define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
10079 #define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
10080 #define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
10081 #define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
10082 #define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
10083 #define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
10084 #define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
10085 #define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
10086 #define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
10087 #define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
10088 #define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
10089 #define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
10090 #define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
10091 #define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
10092 #define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
10093 #define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
10094 #define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
10095 #define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
10096 #define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
10097 #define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
10098 #define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
10099 #define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
10100 #define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
10101 #define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
10102 #define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
10103 #define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
10104 #define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
10105 #define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
10106 #define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
10107 #define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
10108 #define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
10109 #define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
10110 #define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
10111 #define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
10112 #define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
10113 #define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
10114 #define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
10115 #define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
10116 #define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
10117 #define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
10118 #define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
10119 #define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
10120 #define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
10121 #define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
10122 #define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
10123 #define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
10124 #define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
10125 #define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
10126 #define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
10127 #define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
10128 #define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
10129 #define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
10130 #define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
10131 #define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
10132 #define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
10133 #define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
10134 #define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
10135 #define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
10136 #define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
10137 #define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
10138 #define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
10139 #define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
10140 #define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
10141 #define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
10142 #define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
10143 #define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
10144 #define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
10145 #define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
10146 #define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
10147 #define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
10148 #define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
10149 #define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
10150 #define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
10151 #define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
10152 #define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
10153 #define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
10154 #define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
10155 #define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
10156 #define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
10157 #define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
10158 #define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
10159 #define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
10160 #define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
10161 #define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
10162 #define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
10163 #define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
10164 #define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
10165 #define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
10166 #define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
10167 #define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
10168 #define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
10169 #define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
10170 #define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
10171 #define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
10172 #define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
10173 #define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
10174 #define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
10175 #define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
10176 #define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
10177 #define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
10178 #define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
10179 #define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
10180 #define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
10181 #define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
10182 #define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
10183 #define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
10184 #define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
10185 #define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
10186 #define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
10187 #define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
10188 #define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
10189 #define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
10190 #define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
10191 #define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
10192 #define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
10193 #define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
10194 #define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
10195 #define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
10196 #define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
10197 #define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
10198 #define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
10199 #define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
10200 #define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
10201 #define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
10202 #define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
10203 #define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
10204 #define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
10205 #define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
10206 #define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
10207 #define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
10208 #define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
10209 #define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
10210 #define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
10211 #define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
10212 #define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
10213 #define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
10214 #define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
10215 #define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
10216 #define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
10217 #define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
10218 #define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
10219 #define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
10220 #define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
10221 #define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
10222 #define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
10223 #define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
10224 #define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
10225 #define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
10226 #define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
10227 #define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
10228 #define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
10229 #define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
10230 #define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
10231 #define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
10232 #define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
10233 #define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
10234 #define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
10235 #define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
10236 #define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
10237 #define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
10238 #define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
10239 #define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
10240 #define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
10241 #define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
10242 #define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
10243 #define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
10244 #define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
10245 #define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
10246 #define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
10247 #define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
10248 #define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
10249 #define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
10250 #define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
10251 #define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
10252 #define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
10253 #define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
10254 #define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
10255 #define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
10256 #define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
10257 #define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
10258 #define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
10259 #define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
10260 #define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
10261 #define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
10262 #define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
10263 #define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
10264 #define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
10265 #define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
10266 #define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
10267 #define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
10268 #define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
10269 #define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
10270 #define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
10271 #define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
10272 #define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
10273 #define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
10274 #define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
10275 #define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
10276 #define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
10277 #define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
10278 #define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
10279 #define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
10280 #define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
10281 #define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
10282 #define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
10283 #define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
10284 #define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
10285 #define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
10286 #define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
10287 #define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
10288 #define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
10289 #define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
10290 #define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
10291 #define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
10292 #define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
10293 #define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
10294 #define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
10295 #define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
10296 #define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
10297 #define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
10298 #define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
10299 #define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
10300 #define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
10301 #define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
10302 #define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
10303 #define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
10304 #define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
10305 #define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
10306 #define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
10307 #define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
10308 #define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
10309 #define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
10310 #define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
10311 #define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
10312 #define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
10313 #define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
10314 #define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
10315 #define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
10316 #define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
10317 #define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
10318 #define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
10319 #define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
10320 #define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
10321 #define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
10322 #define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
10323 #define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
10324 #define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
10325 #define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
10326 #define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
10327 #define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
10328 #define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
10329 #define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
10330 #define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
10331 #define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
10332 #define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
10333 #define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
10334 #define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
10335 #define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
10336 #define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
10337 #define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
10338 #define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
10339 #define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
10340 #define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
10341 #define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
10342 #define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
10343 #define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
10344 #define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
10345 #define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
10346 #define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
10347 #define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
10348 #define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
10349 #define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
10350 #define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
10351 #define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
10352 #define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
10353 #define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
10354 #define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
10355 #define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
10356 #define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
10357 #define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
10358 #define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
10359 #define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
10360 #define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
10361 #define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
10362 #define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
10363 #define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
10364 #define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
10365 #define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
10366 #define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
10367 #define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
10368 #define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
10369 #define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
10370 #define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
10371 #define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
10372 #define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
10373 #define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
10374 #define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
10375 #define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
10376 #define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
10377 #define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
10378 #define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
10379 #define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
10380 #define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
10381 #define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
10382 #define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
10383 #define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
10384 #define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
10385 #define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
10386 #define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
10387 #define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
10388 #define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
10389 #define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
10390 #define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
10391 #define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
10392 #define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
10393 #define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
10394 #define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
10395 #define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
10396 #define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
10397 #define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
10398 #define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
10399 #define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
10400 #define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
10401 #define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
10402 #define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
10403 #define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
10404 #define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
10405 #define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
10406 #define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
10407 #define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
10408 #define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
10409 #define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
10410 #define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
10411 #define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
10412 #define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
10413 #define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
10414 #define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
10415 #define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
10416 #define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
10417 #define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
10418 #define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
10419 #define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
10420 #define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
10421 #define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
10422 #define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
10423 #define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
10424 #define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
10425 #define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
10426 #define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
10427 #define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
10428 #define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
10429 #define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
10430 #define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
10431 #define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
10432 #define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
10433 #define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
10434 #define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
10435 #define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
10436 #define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
10437 #define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
10438 #define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
10439 #define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
10440 #define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
10441 #define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
10442 #define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
10443 #define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
10444 #define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
10445 #define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
10446 #define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
10447 #define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
10448 #define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
10449 #define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
10450 #define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
10451 #define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
10452 #define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
10453 #define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
10454 #define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
10455 #define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
10456 #define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
10457 #define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
10458 #define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
10459 #define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
10460 #define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
10461 #define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
10462 #define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
10463 #define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
10464 #define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
10465 #define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
10466 #define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
10467 #define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
10468 #define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
10469 #define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
10470 #define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
10471 #define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
10472 #define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
10473 #define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
10474 #define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
10475 #define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
10476 #define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
10477 #define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
10478 #define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
10479 #define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
10480 #define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
10481 #define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
10482 #define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
10483 #define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
10484 #define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
10485 #define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
10486 #define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
10487 #define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
10488 #define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
10489 #define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
10490 #define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
10491 #define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
10492 #define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
10493 #define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
10494 #define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
10495 #define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
10496 #define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
10497 #define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
10498 #define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
10499 #define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
10500 #define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
10501 #define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
10502 #define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
10503 #define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
10504 #define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
10505 #define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
10506 #define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
10507 #define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
10508 #define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
10509 #define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
10510 #define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
10511 #define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
10512 #define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
10513 #define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
10514 #define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
10515 #define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
10516 #define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
10517 #define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
10518 #define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
10519 #define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
10520 #define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
10521 #define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
10522 #define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
10523 #define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
10524 #define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
10525 #define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
10526 #define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
10527 #define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
10528 #define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
10529 #define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
10530 #define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
10531 #define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
10532 #define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
10533 #define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
10534 #define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
10535 #define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
10536 #define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
10537 #define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
10538 #define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
10539 #define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
10540 #define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
10541 #define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
10542 #define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
10543 #define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
10544 #define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
10545 #define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
10546 #define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
10547 #define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
10548 #define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
10549 #define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
10550 #define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
10551 #define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
10552 #define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
10553 #define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
10554 #define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
10555 #define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
10556 #define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
10557 #define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
10558 #define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
10559 #define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
10560 #define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
10561 #define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
10562 #define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
10563 #define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
10564 #define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
10565 #define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
10566 #define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
10567 #define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
10568 #define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
10569 #define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
10570 #define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
10571 #define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
10572 #define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
10573 #define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
10574 #define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
10575 #define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
10576 #define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
10577 #define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
10578 #define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
10579 #define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
10580 #define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
10581 #define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
10582 #define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
10583 #define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
10584 #define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
10585 #define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
10586 #define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
10587 #define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
10588 #define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
10589 #define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
10590 #define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
10591 #define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
10592 #define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
10593 #define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
10594 #define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
10595 #define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
10596 #define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
10597 #define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
10598 #define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
10599 #define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
10600 #define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
10601 #define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
10602 #define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
10603 #define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
10604 #define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
10605 #define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
10606 #define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
10607 #define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
10608 #define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
10609 #define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
10610 #define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
10611 #define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
10612 #define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
10613 #define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
10614 #define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
10615 #define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
10616 #define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
10617 #define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
10618 #define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
10619 #define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
10620 #define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
10621 #define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
10622 #define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
10623 #define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
10624 #define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
10625 #define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
10626 #define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
10627 #define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
10628 #define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
10629 #define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
10630 #define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
10631 #define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
10632 #define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
10633 #define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
10634 #define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
10635 #define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
10636 #define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
10637 #define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
10638 #define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
10639 #define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
10640 #define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
10641 #define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
10642 #define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
10643 #define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
10644 #define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
10645 #define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
10646 #define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
10647 #define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
10648 #define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
10649 #define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
10650 #define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
10651 #define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
10652 #define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
10653 #define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
10654 #define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
10655 #define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
10656 #define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
10657 #define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
10658 #define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
10659 #define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
10660 #define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
10661 #define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
10662 #define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
10663 #define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
10664 #define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
10665 #define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
10666 #define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
10667 #define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
10668 #define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
10669 #define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
10670 #define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
10671 #define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
10672 #define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
10673 #define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
10674 #define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
10675 #define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
10676 #define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
10677 #define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
10678 #define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
10679 #define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
10680 #define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
10681 #define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
10682 #define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
10683 #define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
10684 #define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
10685 #define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
10686 #define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
10687 #define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
10688 #define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
10689 #define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
10690 #define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
10691 #define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
10692 #define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
10693 #define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
10694 #define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
10695 #define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
10696 #define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
10697 #define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
10698 #define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
10699 #define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
10700 #define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
10701 #define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
10702 #define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
10703 #define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
10704 #define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
10705 #define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
10706 #define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
10707 #define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
10708 #define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
10709 #define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
10710 #define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
10711 #define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
10712 #define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
10713 #define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
10714 #define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
10715 #define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
10716 #define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
10717 #define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
10718 #define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
10719 #define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
10720 #define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
10721 #define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
10722 #define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
10723 #define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
10724 #define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
10725 #define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
10726 #define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
10727 #define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
10728 #define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
10729 #define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
10730 #define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
10731 #define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
10732 #define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
10733 #define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
10734 #define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
10735 #define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
10736 #define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
10737 #define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
10738 #define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
10739 #define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
10740 #define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
10741 #define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
10742 #define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
10743 #define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
10744 #define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
10745 #define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
10746 #define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
10747 #define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
10748 #define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
10749 #define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
10750 #define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
10751 #define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
10752 #define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
10753 #define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
10754 #define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
10755 #define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
10756 #define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
10757 #define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
10758 #define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
10759 #define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
10760 #define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
10761 #define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
10762 #define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
10763 #define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
10764 #define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
10765 #define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
10766 #define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
10767 #define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
10768 #define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
10769 #define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
10770 #define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
10771 #define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
10772 #define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
10773 #define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
10774 #define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
10775 #define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
10776 #define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
10777 #define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
10778 #define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
10779 #define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
10780 #define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
10781 #define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
10782 #define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
10783 #define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
10784 #define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
10785 #define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
10786 #define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
10787 #define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
10788 #define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
10789 #define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
10790 #define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
10791 #define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
10792 #define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
10793 #define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
10794 #define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
10795 #define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
10796 #define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
10797 #define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
10798 #define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
10799 #define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
10800 #define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
10801 #define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
10802 #define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
10803 #define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
10804 #define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
10805 #define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
10806 #define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
10807 #define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
10808 #define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
10809 #define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
10810 #define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
10811 #define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
10812 #define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
10813 #define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
10814 #define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
10815 #define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
10816 #define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
10817 #define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
10818 #define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
10819 #define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
10820 #define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
10821 #define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
10822 #define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
10823 #define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
10824 #define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
10825 #define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
10826 #define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
10827 #define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
10828 #define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
10829 #define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
10830 #define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
10831 #define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
10832 #define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
10833 #define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
10834 #define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
10835 #define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
10836 #define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
10837 #define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
10838 #define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
10839 #define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
10840 #define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
10841 #define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
10842 #define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
10843 #define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
10844 #define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
10845 #define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
10846 #define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
10847 #define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
10848 #define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
10849 #define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
10850 #define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
10851 #define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
10852 #define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
10853 #define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
10854 #define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
10855 #define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
10856 #define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
10857 #define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
10858 #define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
10859 #define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
10860 #define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
10861 #define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
10862 #define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
10863 #define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
10864 #define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
10865 #define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
10866 #define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
10867 #define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
10868 #define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
10869 #define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
10870 #define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
10871 #define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
10872 #define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
10873 #define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
10874 #define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
10875 #define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
10876 #define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
10877 #define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
10878 #define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
10879 #define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
10880 #define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
10881 #define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
10882 #define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
10883 #define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
10884 #define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
10885 #define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
10886 #define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
10887 #define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
10888 #define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
10889 #define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
10890 #define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
10891 #define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
10892 #define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
10893 #define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
10894 #define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
10895 #define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
10896 #define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
10897 #define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
10898 #define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
10899 #define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
10900 #define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
10901 #define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
10902 #define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
10903 #define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
10904 #define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
10905 #define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
10906 #define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
10907 #define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
10908 #define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
10909 #define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
10910 #define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
10911 #define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
10912 #define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
10913 #define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
10914 #define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
10915 #define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
10916 #define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
10917 #define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
10918 #define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
10919 #define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
10920 #define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
10921 #define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
10922 #define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
10923 #define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
10924 #define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
10925 #define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
10926 #define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
10927 #define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
10928 #define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
10929 #define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
10930 #define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
10931 #define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
10932 #define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
10933 #define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
10934 #define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
10935 #define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
10936 #define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
10937 #define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
10938 #define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
10939 #define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
10940 #define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
10941 #define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
10942 #define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
10943 #define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
10944 #define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
10945 #define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
10946 #define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
10947 #define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
10948 #define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
10949 #define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
10950 #define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
10951 #define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
10952 #define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
10953 #define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
10954 #define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
10955 #define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
10956 #define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
10957 #define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
10958 #define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
10959 #define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
10960 #define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
10961 #define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
10962 #define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
10963 #define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
10964 #define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
10965 #define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
10966 #define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
10967 #define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
10968 #define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
10969 #define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
10970 #define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
10971 #define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
10972 #define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
10973 #define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
10974 #define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
10975 #define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
10976 #define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
10977 #define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
10978 #define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
10979 #define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
10980 #define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
10981 #define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
10982 #define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
10983 #define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
10984 #define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
10985 #define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
10986 #define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
10987 #define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
10988 #define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
10989 #define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
10990 #define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
10991 #define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
10992 #define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
10993 #define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
10994 #define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
10995 #define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
10996 #define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
10997 #define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
10998 #define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
10999 #define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
11000 #define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
11001 #define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
11002 #define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
11003 #define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
11004 #define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
11005 #define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
11006 #define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
11007 #define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
11008 #define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
11009 #define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
11010 #define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
11011 #define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
11012 #define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
11013 #define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
11014 #define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
11015 #define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
11016 #define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
11017 #define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
11018 #define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
11019 #define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
11020 #define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
11021 #define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
11022 #define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
11023 #define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
11024 #define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
11025 #define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
11026 #define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
11027 #define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
11028 #define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
11029 #define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
11030 #define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
11031 #define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
11032 #define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
11033 #define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
11034 #define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
11035 #define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
11036 #define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
11037 #define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
11038 #define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
11039 #define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
11040 #define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
11041 #define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
11042 #define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
11043 #define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
11044 #define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
11045 #define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
11046 #define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
11047 #define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
11048 #define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
11049 #define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
11050 #define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
11051 #define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
11052 #define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
11053 #define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
11054 #define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
11055 #define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
11056 #define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
11057 #define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
11058 #define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
11059 #define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
11060 #define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
11061 #define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
11062 #define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
11063 #define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
11064 #define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
11065 #define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
11066 #define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
11067 #define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
11068 #define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
11069 #define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
11070 #define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
11071 #define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
11072 #define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
11073 #define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
11074 #define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
11075 #define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
11076 #define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
11077 #define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
11078 #define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
11079 #define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
11080 #define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
11081 #define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
11082 #define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
11083 #define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
11084 #define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
11085 #define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
11086 #define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
11087 #define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
11088 #define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
11089 #define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
11090 #define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
11091 #define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
11092 #define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
11093 #define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
11094 #define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
11095 #define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
11096 #define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
11097 #define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
11098 #define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
11099 #define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
11100 #define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
11101 #define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
11102 #define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
11103 #define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
11104 #define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
11105 #define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
11106 #define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
11107 #define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
11108 #define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
11109 #define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
11110 #define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
11111 #define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
11112 #define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
11113 #define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
11114 #define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
11115 #define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
11116 #define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
11117 #define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
11118 #define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
11119 #define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
11120 #define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
11121 #define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
11122 #define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
11123 #define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
11124 #define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
11125 #define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
11126 #define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
11127 #define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
11128 #define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
11129 #define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
11130 #define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
11131 #define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
11132 #define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
11133 #define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
11134 #define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
11135 #define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
11136 #define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
11137 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
11138 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
11139 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
11140 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
11141 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
11142 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
11143 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
11144 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
11145 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
11146 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
11147 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
11148 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
11149 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
11150 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
11151 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
11152 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
11153 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
11154 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
11155 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
11156 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
11157 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
11158 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
11159 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
11160 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
11161 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
11162 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
11163 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
11164 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
11165 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
11166 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
11167 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
11168 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
11169 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
11170 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
11171 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
11172 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
11173 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
11174 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
11175 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
11176 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
11177 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
11178 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
11179 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
11180 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
11181 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
11182 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
11183 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
11184 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
11185 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
11186 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
11187 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
11188 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
11189 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
11190 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
11191 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
11192 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
11193 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
11194 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
11195 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
11196 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
11197 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
11198 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
11199 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
11200 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
11201 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
11202 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
11203 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
11204 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
11205 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
11206 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
11207 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
11208 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
11209 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
11210 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
11211 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
11212 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
11213 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
11214 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
11215 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
11216 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
11217 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
11218 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
11219 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
11220 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
11221 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
11222 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
11223 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
11224 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
11225 #define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
11226 #define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
11227 #define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
11228 #define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
11229 #define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
11230 #define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
11231 #define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
11232 #define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
11233 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
11234 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
11235 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
11236 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
11237 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
11238 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
11239 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
11240 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
11241 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
11242 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
11243 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
11244 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
11245 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
11246 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
11247 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
11248 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
11249 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
11250 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
11251 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
11252 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
11253 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
11254 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
11255 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
11256 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
11257 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
11258 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
11259 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
11260 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
11261 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
11262 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
11263 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
11264 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
11265 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
11266 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
11267 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
11268 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
11269 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
11270 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
11271 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
11272 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
11273 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
11274 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
11275 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
11276 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
11277 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
11278 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
11279 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
11280 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
11281 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
11282 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
11283 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
11284 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
11285 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
11286 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
11287 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
11288 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
11289 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
11290 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
11291 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
11292 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
11293 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
11294 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
11295 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
11296 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
11297 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
11298 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
11299 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
11300 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
11301 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
11302 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
11303 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
11304 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
11305 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
11306 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
11307 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
11308 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
11309 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
11310 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
11311 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
11312 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
11313 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
11314 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
11315 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
11316 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
11317 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
11318 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
11319 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
11320 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
11321 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
11322 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
11323 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
11324 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
11325 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
11326 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
11327 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
11328 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
11329 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
11330 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
11331 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
11332 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
11333 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
11334 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
11335 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
11336 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
11337 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
11338 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
11339 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
11340 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
11341 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
11342 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
11343 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
11344 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
11345 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
11346 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
11347 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
11348 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
11349 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
11350 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
11351 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
11352 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
11353 #define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
11354 #define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
11355 #define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
11356 #define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
11357 #define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
11358 #define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
11359 #define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
11360 #define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
11361 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
11362 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
11363 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
11364 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
11365 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
11366 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
11367 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
11368 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
11369 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
11370 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
11371 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
11372 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
11373 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
11374 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
11375 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
11376 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
11377 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
11378 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
11379 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
11380 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
11381 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
11382 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
11383 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
11384 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
11385 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
11386 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
11387 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
11388 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
11389 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
11390 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
11391 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
11392 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
11393 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
11394 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
11395 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
11396 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
11397 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
11398 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
11399 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
11400 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
11401 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
11402 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
11403 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
11404 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
11405 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
11406 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
11407 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
11408 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
11409 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
11410 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
11411 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
11412 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
11413 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
11414 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
11415 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
11416 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
11417 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
11418 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
11419 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
11420 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
11421 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
11422 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
11423 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
11424 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
11425 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
11426 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
11427 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
11428 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
11429 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
11430 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
11431 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
11432 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
11433 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
11434 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
11435 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
11436 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
11437 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
11438 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
11439 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
11440 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
11441 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
11442 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
11443 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
11444 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
11445 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
11446 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
11447 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
11448 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
11449 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
11450 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
11451 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
11452 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
11453 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
11454 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
11455 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
11456 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
11457 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
11458 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
11459 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
11460 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
11461 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
11462 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
11463 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
11464 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
11465 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
11466 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
11467 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
11468 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
11469 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
11470 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
11471 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
11472 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
11473 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
11474 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
11475 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
11476 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
11477 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
11478 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
11479 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
11480 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
11481 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
11482 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
11483 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
11484 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
11485 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
11486 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
11487 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
11488 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
11489 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
11490 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
11491 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
11492 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
11493 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
11494 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
11495 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
11496 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
11497 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
11498 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
11499 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
11500 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
11501 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
11502 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
11503 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
11504 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
11505 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
11506 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
11507 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
11508 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
11509 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
11510 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
11511 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
11512 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
11513 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
11514 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
11515 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
11516 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
11517 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
11518 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
11519 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
11520 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
11521 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
11522 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
11523 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
11524 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
11525 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
11526 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
11527 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
11528 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
11529 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
11530 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
11531 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
11532 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
11533 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
11534 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
11535 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
11536 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
11537 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
11538 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
11539 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
11540 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
11541 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
11542 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
11543 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
11544 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
11545 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
11546 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
11547 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
11548 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
11549 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
11550 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
11551 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
11552 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
11553 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
11554 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
11555 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
11556 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
11557 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
11558 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
11559 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
11560 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
11561 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
11562 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
11563 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
11564 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
11565 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
11566 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
11567 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
11568 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
11569 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
11570 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
11571 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
11572 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
11573 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
11574 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
11575 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
11576 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
11577 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
11578 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
11579 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
11580 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
11581 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
11582 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
11583 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
11584 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
11585 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
11586 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
11587 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
11588 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
11589 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
11590 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
11591 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
11592 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
11593 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
11594 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
11595 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
11596 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
11597 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
11598 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
11599 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
11600 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
11601 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
11602 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
11603 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
11604 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
11605 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
11606 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
11607 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
11608 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
11609 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
11610 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
11611 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
11612 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
11613 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
11614 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
11615 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
11616 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
11617 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
11618 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
11619 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
11620 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
11621 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
11622 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
11623 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
11624 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
11625 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
11626 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
11627 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
11628 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
11629 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
11630 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
11631 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
11632 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
11633 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
11634 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
11635 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
11636 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
11637 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
11638 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
11639 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
11640 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
11641 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
11642 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
11643 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
11644 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
11645 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
11646 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
11647 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
11648 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
11649 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
11650 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
11651 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
11652 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
11653 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
11654 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
11655 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
11656 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
11657 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
11658 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
11659 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
11660 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
11661 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
11662 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
11663 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
11664 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
11665 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
11666 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
11667 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
11668 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
11669 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
11670 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
11671 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
11672 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
11673 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
11674 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
11675 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
11676 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
11677 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
11678 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
11679 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
11680 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
11681 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
11682 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
11683 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
11684 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
11685 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
11686 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
11687 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
11688 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
11689 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
11690 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
11691 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
11692 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
11693 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
11694 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
11695 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
11696 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
11697 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
11698 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
11699 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
11700 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
11701 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
11702 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
11703 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
11704 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
11705 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
11706 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
11707 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
11708 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
11709 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
11710 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
11711 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
11712 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
11713 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
11714 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
11715 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
11716 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
11717 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
11718 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
11719 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
11720 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
11721 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
11722 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
11723 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
11724 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
11725 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
11726 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
11727 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
11728 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
11729 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
11730 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
11731 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
11732 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
11733 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
11734 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
11735 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
11736 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
11737 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
11738 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
11739 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
11740 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
11741 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
11742 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
11743 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
11744 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
11745 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
11746 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
11747 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
11748 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
11749 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
11750 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
11751 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
11752 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
11753 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
11754 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
11755 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
11756 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
11757 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
11758 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
11759 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
11760 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
11761 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
11762 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
11763 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
11764 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
11765 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
11766 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
11767 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
11768 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
11769 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
11770 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
11771 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
11772 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
11773 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
11774 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
11775 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
11776 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
11777 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
11778 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
11779 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
11780 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
11781 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
11782 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
11783 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
11784 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
11785 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
11786 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
11787 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
11788 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
11789 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
11790 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
11791 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
11792 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
11793 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
11794 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
11795 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
11796 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
11797 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
11798 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
11799 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
11800 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
11801 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
11802 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
11803 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
11804 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
11805 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
11806 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
11807 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
11808 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
11809 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
11810 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
11811 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
11812 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
11813 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
11814 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
11815 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
11816 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
11817 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
11818 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
11819 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
11820 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
11821 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
11822 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
11823 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
11824 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
11825 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
11826 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
11827 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
11828 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
11829 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
11830 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
11831 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
11832 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
11833 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
11834 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
11835 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
11836 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
11837 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
11838 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
11839 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
11840 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
11841 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
11842 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
11843 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
11844 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
11845 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
11846 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
11847 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
11848 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
11849 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
11850 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
11851 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
11852 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
11853 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
11854 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
11855 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
11856 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
11857 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
11858 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
11859 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
11860 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
11861 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
11862 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
11863 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
11864 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
11865 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
11866 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
11867 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
11868 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
11869 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
11870 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
11871 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
11872 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
11873 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
11874 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
11875 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
11876 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
11877 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
11878 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
11879 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
11880 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
11881 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
11882 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
11883 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
11884 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
11885 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
11886 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
11887 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
11888 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
11889 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
11890 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
11891 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
11892 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
11893 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
11894 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
11895 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
11896 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
11897 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
11898 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
11899 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
11900 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
11901 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
11902 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
11903 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
11904 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
11905 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
11906 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
11907 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
11908 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
11909 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
11910 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
11911 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
11912 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
11913 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
11914 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
11915 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
11916 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
11917 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
11918 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
11919 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
11920 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
11921 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
11922 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
11923 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
11924 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
11925 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
11926 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
11927 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
11928 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
11929 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
11930 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
11931 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
11932 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
11933 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
11934 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
11935 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
11936 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
11937 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
11938 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
11939 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
11940 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
11941 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
11942 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
11943 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
11944 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
11945 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
11946 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
11947 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
11948 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
11949 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
11950 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
11951 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
11952 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
11953 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
11954 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
11955 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
11956 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
11957 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
11958 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
11959 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
11960 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
11961 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
11962 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
11963 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
11964 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
11965 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
11966 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
11967 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
11968 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
11969 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
11970 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
11971 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
11972 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
11973 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
11974 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
11975 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
11976 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
11977 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
11978 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
11979 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
11980 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
11981 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
11982 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
11983 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
11984 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
11985 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
11986 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
11987 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
11988 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
11989 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
11990 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
11991 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
11992 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
11993 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
11994 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
11995 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
11996 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
11997 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
11998 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
11999 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
12000 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
12001 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
12002 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
12003 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
12004 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
12005 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
12006 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
12007 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
12008 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
12009 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
12010 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
12011 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
12012 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
12013 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
12014 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
12015 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
12016 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
12017 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
12018 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
12019 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
12020 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
12021 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
12022 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
12023 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
12024 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
12025 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
12026 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
12027 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
12028 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
12029 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
12030 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
12031 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
12032 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
12033 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
12034 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
12035 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
12036 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
12037 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
12038 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
12039 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
12040 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
12041 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
12042 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
12043 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
12044 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
12045 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
12046 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
12047 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
12048 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
12049 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
12050 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
12051 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
12052 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
12053 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
12054 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
12055 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
12056 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
12057 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
12058 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
12059 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
12060 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
12061 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
12062 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
12063 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
12064 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
12065 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
12066 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
12067 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
12068 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
12069 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
12070 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
12071 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
12072 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
12073 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
12074 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
12075 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
12076 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
12077 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
12078 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
12079 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
12080 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
12081 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
12082 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
12083 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
12084 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
12085 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
12086 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
12087 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
12088 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
12089 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
12090 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
12091 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
12092 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
12093 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
12094 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
12095 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
12096 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
12097 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
12098 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
12099 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
12100 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
12101 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
12102 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
12103 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
12104 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
12105 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
12106 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
12107 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
12108 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
12109 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
12110 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
12111 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
12112 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
12113 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
12114 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
12115 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
12116 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
12117 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
12118 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
12119 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
12120 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
12121 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
12122 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
12123 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
12124 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
12125 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
12126 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
12127 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
12128 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
12129 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
12130 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
12131 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
12132 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
12133 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
12134 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
12135 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
12136 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
12137 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
12138 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
12139 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
12140 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
12141 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
12142 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
12143 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
12144 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
12145 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
12146 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
12147 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
12148 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
12149 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
12150 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
12151 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
12152 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
12153 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
12154 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
12155 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
12156 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
12157 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
12158 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
12159 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
12160 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
12161 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
12162 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
12163 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
12164 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
12165 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
12166 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
12167 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
12168 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
12169 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
12170 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
12171 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
12172 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
12173 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
12174 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
12175 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
12176 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
12177 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
12178 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
12179 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
12180 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
12181 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
12182 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
12183 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
12184 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
12185 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
12186 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
12187 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
12188 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
12189 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
12190 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
12191 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
12192 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
12193 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
12194 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
12195 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
12196 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
12197 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
12198 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
12199 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
12200 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
12201 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
12202 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
12203 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
12204 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
12205 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
12206 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
12207 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
12208 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
12209 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
12210 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
12211 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
12212 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
12213 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
12214 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
12215 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
12216 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
12217 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
12218 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
12219 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
12220 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
12221 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
12222 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
12223 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
12224 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
12225 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
12226 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
12227 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
12228 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
12229 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
12230 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
12231 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
12232 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
12233 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
12234 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
12235 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
12236 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
12237 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
12238 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
12239 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
12240 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
12241 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
12242 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
12243 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
12244 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
12245 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
12246 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
12247 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
12248 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
12249 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
12250 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
12251 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
12252 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
12253 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
12254 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
12255 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
12256 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
12257 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
12258 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
12259 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
12260 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
12261 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
12262 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
12263 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
12264 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
12265 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
12266 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
12267 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
12268 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
12269 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
12270 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
12271 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
12272 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
12273 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
12274 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
12275 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
12276 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
12277 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
12278 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
12279 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
12280 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
12281 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
12282 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
12283 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
12284 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
12285 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
12286 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
12287 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
12288 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
12289 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
12290 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
12291 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
12292 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
12293 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
12294 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
12295 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
12296 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
12297 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
12298 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
12299 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
12300 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
12301 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
12302 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
12303 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
12304 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
12305 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
12306 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
12307 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
12308 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
12309 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
12310 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
12311 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
12312 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
12313 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
12314 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
12315 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
12316 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
12317 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
12318 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
12319 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
12320 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
12321 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
12322 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
12323 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
12324 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
12325 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
12326 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
12327 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
12328 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
12329 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
12330 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
12331 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
12332 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
12333 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
12334 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
12335 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
12336 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
12337 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
12338 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
12339 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
12340 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
12341 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
12342 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
12343 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
12344 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
12345 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
12346 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
12347 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
12348 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
12349 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
12350 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
12351 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
12352 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
12353 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
12354 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
12355 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
12356 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
12357 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
12358 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
12359 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
12360 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
12361 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
12362 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
12363 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
12364 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
12365 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
12366 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
12367 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
12368 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
12369 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
12370 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
12371 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
12372 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
12373 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
12374 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
12375 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
12376 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
12377 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
12378 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
12379 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
12380 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
12381 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
12382 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
12383 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
12384 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
12385 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
12386 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
12387 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
12388 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
12389 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
12390 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
12391 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
12392 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
12393 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
12394 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
12395 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
12396 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
12397 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
12398 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
12399 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
12400 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
12401 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
12402 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
12403 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
12404 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
12405 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
12406 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
12407 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
12408 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
12409 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
12410 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
12411 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
12412 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
12413 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
12414 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
12415 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
12416 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
12417 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12418 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12419 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12420 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12421 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12422 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12423 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12424 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12425 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12426 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12427 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12428 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12429 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12430 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12431 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12432 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12433 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12434 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12435 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12436 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12437 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12438 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12439 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12440 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12441 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12442 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12443 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12444 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12445 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12446 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12447 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12448 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12449 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12450 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12451 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12452 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12453 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12454 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12455 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12456 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12457 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12458 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12459 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12460 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12461 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12462 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12463 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12464 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12465 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12466 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12467 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12468 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12469 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12470 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12471 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12472 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12473 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12474 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12475 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12476 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12477 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12478 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12479 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12480 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12481 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12482 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12483 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12484 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12485 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12486 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12487 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12488 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12489 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12490 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12491 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12492 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12493 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12494 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12495 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12496 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12497 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
12498 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
12499 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
12500 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
12501 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
12502 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
12503 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
12504 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
12505 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12506 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12507 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12508 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12509 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12510 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12511 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12512 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12513 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12514 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12515 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12516 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12517 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12518 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12519 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12520 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12521 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12522 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12523 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12524 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12525 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12526 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12527 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12528 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12529 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12530 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12531 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12532 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12533 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12534 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12535 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12536 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12537 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12538 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12539 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12540 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12541 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12542 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12543 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12544 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12545 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12546 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12547 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12548 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12549 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12550 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12551 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12552 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12553 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12554 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12555 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12556 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12557 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12558 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12559 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12560 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12561 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12562 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12563 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12564 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12565 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12566 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12567 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12568 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12569 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12570 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12571 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12572 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12573 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12574 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12575 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12576 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12577 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12578 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12579 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12580 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12581 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12582 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12583 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12584 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12585 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12586 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12587 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12588 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12589 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12590 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12591 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12592 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12593 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12594 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12595 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12596 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12597 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12598 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12599 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12600 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12601 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12602 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12603 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12604 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12605 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12606 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12607 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12608 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12609 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12610 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12611 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12612 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12613 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12614 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12615 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12616 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12617 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12618 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12619 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12620 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12621 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12622 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12623 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12624 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12625 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
12626 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
12627 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
12628 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
12629 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
12630 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
12631 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
12632 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
12633 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12634 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12635 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12636 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12637 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12638 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12639 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12640 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12641 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12642 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12643 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12644 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12645 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12646 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12647 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12648 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12649 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12650 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12651 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12652 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12653 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12654 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12655 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12656 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12657 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12658 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12659 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12660 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12661 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12662 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12663 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12664 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12665 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12666 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12667 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12668 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12669 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12670 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12671 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12672 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12673 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
12674 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
12675 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
12676 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
12677 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
12678 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
12679 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
12680 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
12681 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
12682 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
12683 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
12684 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
12685 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
12686 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
12687 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
12688 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
12689 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
12690 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
12691 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
12692 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
12693 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
12694 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
12695 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
12696 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
12697 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
12698 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
12699 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
12700 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
12701 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
12702 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
12703 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
12704 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
12705 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
12706 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
12707 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
12708 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
12709 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
12710 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
12711 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
12712 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
12713 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
12714 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
12715 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
12716 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
12717 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
12718 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
12719 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
12720 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
12721 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
12722 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
12723 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
12724 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
12725 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
12726 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
12727 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
12728 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
12729 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
12730 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
12731 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
12732 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
12733 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
12734 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
12735 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
12736 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
12737 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
12738 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
12739 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
12740 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
12741 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
12742 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
12743 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
12744 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
12745 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
12746 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
12747 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
12748 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
12749 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
12750 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
12751 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
12752 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
12753 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
12754 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
12755 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
12756 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
12757 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
12758 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
12759 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
12760 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
12761 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
12762 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
12763 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
12764 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
12765 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
12766 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
12767 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
12768 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
12769 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
12770 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
12771 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
12772 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
12773 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
12774 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
12775 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
12776 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
12777 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
12778 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
12779 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
12780 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
12781 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
12782 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
12783 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
12784 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
12785 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
12786 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
12787 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
12788 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
12789 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
12790 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
12791 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
12792 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
12793 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
12794 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
12795 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
12796 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
12797 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
12798 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
12799 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
12800 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
12801 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
12802 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
12803 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
12804 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
12805 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
12806 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
12807 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
12808 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
12809 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
12810 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
12811 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
12812 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
12813 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
12814 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
12815 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
12816 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
12817 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
12818 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
12819 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
12820 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
12821 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
12822 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
12823 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
12824 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
12825 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
12826 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
12827 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
12828 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
12829 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
12830 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
12831 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
12832 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
12833 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
12834 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
12835 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
12836 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
12837 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
12838 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
12839 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
12840 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
12841 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
12842 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
12843 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
12844 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
12845 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
12846 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
12847 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
12848 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
12849 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
12850 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
12851 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
12852 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
12853 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
12854 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
12855 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
12856 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
12857 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
12858 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
12859 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
12860 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
12861 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
12862 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
12863 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
12864 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
12865 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
12866 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
12867 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
12868 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
12869 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
12870 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
12871 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
12872 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
12873 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
12874 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
12875 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
12876 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
12877 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
12878 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
12879 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
12880 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
12881 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
12882 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
12883 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
12884 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
12885 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
12886 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
12887 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
12888 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
12889 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
12890 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
12891 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
12892 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
12893 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
12894 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
12895 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
12896 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
12897 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
12898 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
12899 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
12900 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
12901 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
12902 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
12903 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
12904 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
12905 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
12906 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
12907 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
12908 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
12909 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
12910 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
12911 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
12912 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
12913 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
12914 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
12915 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
12916 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
12917 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
12918 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
12919 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
12920 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
12921 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
12922 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
12923 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
12924 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
12925 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
12926 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
12927 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
12928 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
12929 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
12930 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
12931 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
12932 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
12933 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
12934 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
12935 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
12936 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
12937 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
12938 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
12939 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
12940 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
12941 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
12942 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
12943 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
12944 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
12945 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
12946 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
12947 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
12948 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
12949 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
12950 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
12951 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
12952 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
12953 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
12954 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
12955 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
12956 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
12957 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
12958 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
12959 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
12960 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
12961 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
12962 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
12963 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
12964 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
12965 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
12966 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
12967 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
12968 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
12969 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
12970 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
12971 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
12972 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
12973 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
12974 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
12975 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
12976 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
12977 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
12978 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
12979 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
12980 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
12981 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
12982 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
12983 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
12984 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
12985 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
12986 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
12987 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
12988 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
12989 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
12990 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
12991 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
12992 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
12993 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
12994 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
12995 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
12996 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
12997 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
12998 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
12999 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
13000 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
13001 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
13002 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
13003 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
13004 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
13005 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
13006 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
13007 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
13008 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
13009 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
13010 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
13011 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
13012 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
13013 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
13014 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
13015 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
13016 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
13017 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
13018 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
13019 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
13020 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
13021 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
13022 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
13023 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
13024 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
13025 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
13026 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
13027 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
13028 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
13029 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
13030 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
13031 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
13032 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
13033 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
13034 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
13035 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
13036 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
13037 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
13038 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
13039 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
13040 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
13041 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
13042 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
13043 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
13044 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
13045 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
13046 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
13047 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
13048 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
13049 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
13050 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
13051 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
13052 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
13053 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
13054 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
13055 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
13056 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
13057 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
13058 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13059 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
13060 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13061 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13062 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13063 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13064 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13065 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
13066 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13067 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
13068 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13069 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
13070 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
13071 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
13072 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
13073 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
13074 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13075 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
13076 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13077 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13078 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13079 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13080 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13081 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
13082 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13083 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
13084 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13085 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
13086 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
13087 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
13088 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
13089 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
13090 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13091 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
13092 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13093 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13094 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13095 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13096 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13097 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
13098 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13099 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
13100 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13101 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
13102 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
13103 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
13104 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
13105 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
13106 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13107 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
13108 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13109 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13110 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13111 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13112 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13113 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
13114 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13115 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
13116 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13117 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
13118 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
13119 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
13120 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
13121 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
13122 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
13123 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
13124 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
13125 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
13126 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
13127 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
13128 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
13129 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
13130 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
13131 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
13132 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
13133 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
13134 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
13135 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
13136 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
13137 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
13138 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
13139 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
13140 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
13141 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
13142 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
13143 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
13144 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
13145 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
13146 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
13147 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
13148 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
13149 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
13150 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
13151 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
13152 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
13153 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
13154 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
13155 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
13156 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
13157 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
13158 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
13159 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
13160 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
13161 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
13162 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
13163 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
13164 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
13165 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
13166 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
13167 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
13168 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
13169 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
13170 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
13171 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
13172 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
13173 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
13174 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
13175 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
13176 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
13177 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
13178 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
13179 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
13180 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
13181 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
13182 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
13183 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
13184 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
13185 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
13186 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
13187 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
13188 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
13189 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
13190 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
13191 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
13192 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
13193 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
13194 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
13195 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
13196 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
13197 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
13198 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
13199 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
13200 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
13201 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
13202 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
13203 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
13204 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
13205 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
13206 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
13207 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
13208 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
13209 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
13210 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
13211 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
13212 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
13213 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
13214 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
13215 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
13216 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
13217 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
13218 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
13219 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
13220 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
13221 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
13222 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
13223 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
13224 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
13225 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
13226 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
13227 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
13228 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
13229 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
13230 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
13231 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
13232 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
13233 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
13234 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
13235 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
13236 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
13237 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
13238 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
13239 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
13240 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
13241 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
13242 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
13243 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
13244 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
13245 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
13246 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
13247 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
13248 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
13249 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
13250 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
13251 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
13252 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
13253 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
13254 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
13255 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
13256 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
13257 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
13258 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
13259 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
13260 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
13261 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
13262 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
13263 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
13264 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
13265 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
13266 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
13267 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
13268 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
13269 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
13270 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
13271 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
13272 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
13273 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
13274 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
13275 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
13276 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
13277 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
13278 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
13279 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
13280 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
13281 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
13282 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
13283 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
13284 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
13285 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
13286 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
13287 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
13288 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
13289 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
13290 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
13291 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
13292 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
13293 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
13294 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
13295 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
13296 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
13297 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
13298 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
13299 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
13300 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
13301 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
13302 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
13303 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
13304 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
13305 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
13306 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
13307 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
13308 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
13309 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
13310 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
13311 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
13312 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
13313 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
13314 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
13315 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
13316 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
13317 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
13318 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
13319 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
13320 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
13321 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
13322 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
13323 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
13324 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
13325 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
13326 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
13327 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
13328 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
13329 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
13330 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
13331 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
13332 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
13333 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
13334 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
13335 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
13336 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
13337 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
13338 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
13339 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
13340 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
13341 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
13342 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
13343 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
13344 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
13345 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
13346 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
13347 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
13348 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
13349 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
13350 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
13351 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
13352 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
13353 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
13354 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
13355 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
13356 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
13357 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
13358 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
13359 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
13360 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
13361 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
13362 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
13363 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
13364 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
13365 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
13366 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
13367 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
13368 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
13369 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
13370 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
13371 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
13372 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
13373 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
13374 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
13375 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
13376 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
13377 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
13378 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
13379 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
13380 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
13381 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
13382 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
13383 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
13384 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
13385 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
13386 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
13387 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
13388 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
13389 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
13390 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
13391 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
13392 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
13393 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
13394 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
13395 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
13396 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
13397 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
13398 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
13399 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
13400 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
13401 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
13402 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
13403 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
13404 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
13405 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
13406 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
13407 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
13408 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
13409 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
13410 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
13411 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
13412 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
13413 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
13414 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
13415 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
13416 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
13417 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
13418 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
13419 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
13420 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
13421 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
13422 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
13423 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
13424 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
13425 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
13426 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
13427 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
13428 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
13429 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
13430 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
13431 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
13432 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
13433 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
13434 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
13435 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
13436 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
13437 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
13438 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
13439 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
13440 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
13441 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
13442 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
13443 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
13444 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
13445 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
13446 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
13447 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
13448 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
13449 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
13450 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
13451 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
13452 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
13453 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
13454 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
13455 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
13456 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
13457 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
13458 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
13459 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
13460 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
13461 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
13462 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
13463 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
13464 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
13465 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
13466 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
13467 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
13468 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
13469 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
13470 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
13471 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
13472 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
13473 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
13474 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
13475 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
13476 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
13477 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
13478 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
13479 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
13480 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
13481 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
13482 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
13483 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
13484 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
13485 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
13486 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
13487 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
13488 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
13489 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
13490 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
13491 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
13492 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
13493 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
13494 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
13495 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
13496 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
13497 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
13498 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
13499 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
13500 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
13501 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
13502 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
13503 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
13504 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
13505 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
13506 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
13507 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
13508 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
13509 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
13510 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
13511 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
13512 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
13513 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
13514 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
13515 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
13516 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
13517 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
13518 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
13519 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
13520 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
13521 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
13522 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
13523 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
13524 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
13525 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
13526 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
13527 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
13528 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
13529 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
13530 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
13531 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
13532 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
13533 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
13534 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
13535 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
13536 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
13537 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
13538 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
13539 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
13540 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
13541 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
13542 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
13543 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
13544 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
13545 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
13546 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
13547 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
13548 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
13549 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
13550 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
13551 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
13552 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
13553 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
13554 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
13555 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
13556 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
13557 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
13558 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
13559 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
13560 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
13561 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
13562 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
13563 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
13564 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
13565 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
13566 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
13567 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
13568 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
13569 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
13570 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
13571 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
13572 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
13573 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
13574 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
13575 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
13576 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
13577 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
13578 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
13579 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
13580 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
13581 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
13582 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
13583 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
13584 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
13585 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
13586 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
13587 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
13588 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
13589 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
13590 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
13591 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
13592 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
13593 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
13594 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
13595 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
13596 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
13597 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
13598 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
13599 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
13600 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
13601 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
13602 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
13603 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
13604 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
13605 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
13606 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
13607 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
13608 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
13609 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
13610 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
13611 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
13612 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
13613 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
13614 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
13615 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
13616 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
13617 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
13618 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
13619 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
13620 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
13621 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
13622 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
13623 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
13624 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
13625 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
13626 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
13627 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
13628 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
13629 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
13630 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
13631 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
13632 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
13633 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
13634 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
13635 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
13636 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
13637 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
13638 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
13639 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
13640 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
13641 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
13642 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
13643 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
13644 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
13645 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
13646 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
13647 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
13648 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
13649 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
13650 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
13651 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
13652 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
13653 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
13654 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
13655 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
13656 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
13657 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
13658 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
13659 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
13660 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
13661 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
13662 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
13663 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
13664 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
13665 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
13666 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
13667 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
13668 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
13669 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
13670 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
13671 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
13672 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
13673 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
13674 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
13675 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
13676 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
13677 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
13678 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
13679 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
13680 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
13681 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
13682 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
13683 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
13684 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
13685 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
13686 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
13687 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
13688 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
13689 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
13690 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
13691 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
13692 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
13693 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
13694 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
13695 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
13696 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
13697 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
13698 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
13699 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
13700 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
13701 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
13702 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
13703 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
13704 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
13705 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
13706 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
13707 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
13708 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
13709 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
13710 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
13711 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
13712 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
13713 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
13714 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
13715 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
13716 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
13717 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
13718 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
13719 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
13720 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
13721 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
13722 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
13723 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
13724 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
13725 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
13726 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
13727 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
13728 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
13729 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
13730 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
13731 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
13732 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
13733 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
13734 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
13735 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
13736 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
13737 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13738 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13739 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13740 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13741 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13742 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13743 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13744 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13745 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
13746 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
13747 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
13748 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
13749 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
13750 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
13751 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
13752 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
13753 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
13754 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
13755 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
13756 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
13757 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
13758 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
13759 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
13760 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
13761 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
13762 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
13763 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
13764 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
13765 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
13766 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
13767 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
13768 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
13769 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
13770 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
13771 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
13772 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
13773 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
13774 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
13775 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
13776 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
13777 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13778 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13779 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13780 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13781 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13782 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13783 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13784 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13785 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
13786 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
13787 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
13788 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
13789 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
13790 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
13791 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
13792 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
13793 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
13794 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
13795 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
13796 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
13797 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
13798 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
13799 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
13800 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
13801 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
13802 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
13803 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
13804 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
13805 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
13806 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
13807 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
13808 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
13809 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
13810 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
13811 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
13812 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
13813 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
13814 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
13815 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
13816 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
13817 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
13818 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
13819 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
13820 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
13821 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
13822 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
13823 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
13824 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
13825 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
13826 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
13827 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
13828 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
13829 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
13830 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
13831 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
13832 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
13833 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
13834 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
13835 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
13836 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
13837 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
13838 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
13839 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
13840 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
13841 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13842 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13843 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13844 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13845 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13846 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13847 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13848 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13849 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
13850 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
13851 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
13852 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
13853 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
13854 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
13855 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
13856 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
13857 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
13858 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
13859 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
13860 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
13861 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
13862 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
13863 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
13864 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
13865 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
13866 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
13867 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
13868 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
13869 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
13870 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
13871 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
13872 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
13873 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
13874 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
13875 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
13876 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
13877 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
13878 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
13879 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
13880 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
13881 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13882 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13883 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13884 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13885 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13886 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13887 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13888 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13889 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
13890 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
13891 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
13892 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
13893 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
13894 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
13895 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
13896 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
13897 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
13898 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
13899 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
13900 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
13901 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
13902 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
13903 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
13904 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
13905 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
13906 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
13907 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
13908 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
13909 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
13910 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
13911 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
13912 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
13913 #define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
13914 #define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
13915 #define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
13916 #define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
13917 #define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
13918 #define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
13919 #define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
13920 #define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
13921 #define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
13922 #define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
13923 #define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
13924 #define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
13925 #define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
13926 #define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
13927 #define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
13928 #define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
13929 #define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
13930 #define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
13931 #define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
13932 #define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
13933 #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
13934 #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
13935 #define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
13936 #define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
13937 #define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
13938 #define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
13939 #define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
13940 #define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
13941 #define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
13942 #define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
13943 #define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
13944 #define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
13945 #define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
13946 #define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
13947 #define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
13948 #define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
13949 #define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
13950 #define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
13951 #define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
13952 #define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
13953 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
13954 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
13955 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
13956 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
13957 #define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
13958 #define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
13959 #define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
13960 #define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
13961 #define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
13962 #define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
13963 #define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
13964 #define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
13965 #define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
13966 #define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
13967 #define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
13968 #define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
13969 #define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
13970 #define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
13971 #define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
13972 #define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
13973 #define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
13974 #define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
13975 #define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
13976 #define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
13977 #define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
13978 #define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
13979 #define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
13980 #define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
13981 #define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
13982 #define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
13983 #define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
13984 #define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
13985 #define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
13986 #define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
13987 #define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
13988 #define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
13989 #define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
13990 #define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
13991 #define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
13992 #define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
13993 #define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
13994 #define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
13995 #define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
13996 #define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
13997 #define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
13998 #define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
13999 #define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
14000 #define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
14001 #define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
14002 #define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
14003 #define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
14004 #define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
14005 #define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
14006 #define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
14007 #define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
14008 #define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
14009 #define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
14010 #define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
14011 #define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
14012 #define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
14013 #define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
14014 #define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
14015 #define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
14016 #define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
14017 #define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
14018 #define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
14019 #define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
14020 #define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
14021 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
14022 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
14023 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
14024 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
14025 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
14026 #define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
14027 #define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
14028 #define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
14029 #define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
14030 #define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
14031 #define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
14032 #define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
14033 #define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
14034 #define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
14035 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
14036 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
14037 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
14038 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
14039 #define MC_SEQ_DLL_STBY__EN_MASK 0x1
14040 #define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
14041 #define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
14042 #define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
14043 #define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
14044 #define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
14045 #define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
14046 #define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
14047 #define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
14048 #define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
14049 #define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
14050 #define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
14051 #define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
14052 #define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
14053 #define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
14054 #define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
14055 #define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
14056 #define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
14057 #define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
14058 #define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
14059 #define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
14060 #define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
14061 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
14062 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
14063 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
14064 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
14065 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
14066 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
14067 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
14068 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
14069 #define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
14070 #define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
14071 #define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
14072 #define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
14073 #define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
14074 #define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
14075 #define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
14076 #define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
14077 #define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
14078 #define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
14079 #define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
14080 #define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
14081 #define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
14082 #define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
14083 #define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
14084 #define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
14085 #define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
14086 #define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
14087 #define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
14088 #define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
14089 #define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
14090 #define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
14091 #define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
14092 #define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
14093 #define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
14094 #define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
14095 #define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
14096 #define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
14097 #define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
14098 #define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
14099 #define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
14100 #define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
14101 #define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
14102 #define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
14103 #define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
14104 #define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
14105 #define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
14106 #define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
14107 #define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
14108 #define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
14109 #define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
14110 #define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
14111 #define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
14112 #define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
14113 #define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
14114 #define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
14115 #define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
14116 #define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
14117 #define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
14118 #define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
14119 #define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
14120 #define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
14121 #define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
14122 #define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
14123 #define MC_DLB_CONFIG0__MASK_MASK 0xf0
14124 #define MC_DLB_CONFIG0__MASK__SHIFT 0x4
14125 #define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
14126 #define MC_DLB_CONFIG0__PTR__SHIFT 0x8
14127 #define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
14128 #define MC_DLB_CONFIG1__DATA__SHIFT 0x0
14129 #define MC_DLB_SETUP__DLB_EN_MASK 0x1
14130 #define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
14131 #define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
14132 #define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
14133 #define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
14134 #define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
14135 #define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
14136 #define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
14137 #define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
14138 #define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
14139 #define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
14140 #define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
14141 #define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
14142 #define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
14143 #define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
14144 #define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
14145 #define MC_DLB_SETUP__QDR_MODE_MASK 0x100
14146 #define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
14147 #define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
14148 #define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
14149 #define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
14150 #define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
14151 #define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
14152 #define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
14153 #define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
14154 #define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
14155 #define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
14156 #define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
14157 #define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
14158 #define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
14159 #define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
14160 #define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
14161 #define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
14162 #define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
14163 #define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
14164 #define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
14165 #define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
14166 #define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
14167 #define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
14168 #define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
14169 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
14170 #define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
14171 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
14172 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
14173 #define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
14174 #define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
14175 #define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
14176 #define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
14177 #define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
14178 #define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
14179 #define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
14180 #define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
14181 #define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
14182 #define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
14183 #define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
14184 #define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
14185 #define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
14186 #define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
14187 #define MC_DLB_STATUS__LOCK_MASK 0xf0
14188 #define MC_DLB_STATUS__LOCK__SHIFT 0x4
14189 #define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
14190 #define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
14191 #define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
14192 #define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
14193 #define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
14194 #define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
14195 #define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
14196 #define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
14197 #define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
14198 #define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
14199 #define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
14200 #define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
14201 #define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
14202 #define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
14203 #define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
14204 #define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
14205 #define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
14206 #define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
14207 #define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
14208 #define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
14209 #define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
14210 #define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
14211 #define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
14212 #define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
14213 #define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
14214 #define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
14215 #define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
14216 #define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
14217 #define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
14218 #define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
14219 #define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
14220 #define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
14221 #define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
14222 #define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
14223 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
14224 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
14225 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
14226 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
14227 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
14228 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
14229 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
14230 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
14231 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
14232 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
14233 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
14234 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
14235 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
14236 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
14237 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
14238 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
14239 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
14240 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
14241 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
14242 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
14243 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
14244 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
14245 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
14246 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
14247 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
14248 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
14249 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
14250 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
14251 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
14252 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
14253 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
14254 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
14255 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
14256 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
14257 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
14258 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
14259 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
14260 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
14261 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
14262 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
14263 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
14264 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
14265 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
14266 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
14267 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
14268 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
14269 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
14270 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
14271 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
14272 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
14273 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
14274 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
14275 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
14276 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
14277 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
14278 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
14279 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
14280 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
14281 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
14282 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
14283 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
14284 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
14285 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
14286 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
14287 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
14288 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
14289 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
14290 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
14291 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
14292 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
14293 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
14294 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
14295 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
14296 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
14297 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
14298 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
14299 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
14300 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
14301 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
14302 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
14303 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
14304 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
14305 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
14306 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
14307 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
14308 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
14309 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
14310 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
14311 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
14312 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
14313 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
14314 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
14315 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
14316 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
14317 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
14318 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
14319 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
14320 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
14321 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
14322 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
14323 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
14324 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
14325 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
14326 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
14327 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
14328 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
14329 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
14330 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
14331 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
14332 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
14333 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
14334 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
14335 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
14336 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
14337 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
14338 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
14339 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
14340 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
14341 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
14342 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
14343 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
14344 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
14345 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
14346 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
14347 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
14348 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
14349 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
14350 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
14351 #define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
14352 #define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
14353 #define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
14354 #define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
14355 #define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
14356 #define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
14357 #define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
14358 #define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
14359 #define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
14360 #define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
14361 #define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
14362 #define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
14363 #define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
14364 #define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
14365 #define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
14366 #define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
14367 #define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
14368 #define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
14369 #define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
14370 #define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
14371 #define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
14372 #define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
14373 #define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
14374 #define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
14375 #define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
14376 #define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
14377 #define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
14378 #define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
14379 #define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
14380 #define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
14381 #define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
14382 #define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
14383 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
14384 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
14385 #define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
14386 #define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
14387 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
14388 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
14389 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
14390 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
14391 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
14392 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
14393 #define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
14394 #define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
14395 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
14396 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
14397 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
14398 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
14399 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
14400 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
14401 #define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
14402 #define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
14403 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
14404 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
14405 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
14406 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
14407 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
14408 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
14409 #define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
14410 #define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
14411 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
14412 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
14413 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
14414 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
14415 
14416 #endif /* GMC_7_1_SH_MASK_H */
14417