1 /*
2  * GMC_8_1 Register documentation
3  *
4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef GMC_8_1_SH_MASK_H
25 #define GMC_8_1_SH_MASK_H
26 
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
37 #define MC_CONFIG__MCDT_WR_ENABLE_MASK 0x20
38 #define MC_CONFIG__MCDT_WR_ENABLE__SHIFT 0x5
39 #define MC_CONFIG__MCDU_WR_ENABLE_MASK 0x40
40 #define MC_CONFIG__MCDU_WR_ENABLE__SHIFT 0x6
41 #define MC_CONFIG__MCDV_WR_ENABLE_MASK 0x80
42 #define MC_CONFIG__MCDV_WR_ENABLE__SHIFT 0x7
43 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x700
44 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x8
45 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE_MASK 0x80000000
46 #define MC_CONFIG__MCC_INDEX_MODE_ENABLE__SHIFT 0x1f
47 #define MC_ARB_ATOMIC__TC_GRP_MASK 0x7
48 #define MC_ARB_ATOMIC__TC_GRP__SHIFT 0x0
49 #define MC_ARB_ATOMIC__TC_GRP_EN_MASK 0x8
50 #define MC_ARB_ATOMIC__TC_GRP_EN__SHIFT 0x3
51 #define MC_ARB_ATOMIC__SDMA_GRP_MASK 0x70
52 #define MC_ARB_ATOMIC__SDMA_GRP__SHIFT 0x4
53 #define MC_ARB_ATOMIC__SDMA_GRP_EN_MASK 0x80
54 #define MC_ARB_ATOMIC__SDMA_GRP_EN__SHIFT 0x7
55 #define MC_ARB_ATOMIC__OUTSTANDING_MASK 0xff00
56 #define MC_ARB_ATOMIC__OUTSTANDING__SHIFT 0x8
57 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP_MASK 0xff0000
58 #define MC_ARB_ATOMIC__ATOMIC_RTN_GRP__SHIFT 0x10
59 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0_MASK 0x1
60 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP0__SHIFT 0x0
61 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1_MASK 0x2
62 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP1__SHIFT 0x1
63 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2_MASK 0x4
64 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP2__SHIFT 0x2
65 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3_MASK 0x8
66 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP3__SHIFT 0x3
67 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4_MASK 0x10
68 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP4__SHIFT 0x4
69 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5_MASK 0x20
70 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP5__SHIFT 0x5
71 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6_MASK 0x40
72 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP6__SHIFT 0x6
73 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7_MASK 0x80
74 #define MC_ARB_AGE_CNTL__RESET_RD_GROUP7__SHIFT 0x7
75 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0_MASK 0x100
76 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP0__SHIFT 0x8
77 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1_MASK 0x200
78 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP1__SHIFT 0x9
79 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2_MASK 0x400
80 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
81 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3_MASK 0x800
82 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP3__SHIFT 0xb
83 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4_MASK 0x1000
84 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP4__SHIFT 0xc
85 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5_MASK 0x2000
86 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP5__SHIFT 0xd
87 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6_MASK 0x4000
88 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP6__SHIFT 0xe
89 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7_MASK 0x8000
90 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP7__SHIFT 0xf
91 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD_MASK 0x70000
92 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_RD__SHIFT 0x10
93 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR_MASK 0x380000
94 #define MC_ARB_AGE_CNTL__AGE_LOW_RATE_WR__SHIFT 0x13
95 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD_MASK 0x400000
96 #define MC_ARB_AGE_CNTL__TIMER_STALL_RD__SHIFT 0x16
97 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR_MASK 0x800000
98 #define MC_ARB_AGE_CNTL__TIMER_STALL_WR__SHIFT 0x17
99 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD_MASK 0x1000000
100 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_RD__SHIFT 0x18
101 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR_MASK 0x2000000
102 #define MC_ARB_AGE_CNTL__EXTEND_WEIGHT_WR__SHIFT 0x19
103 #define MC_ARB_RET_CREDITS2__ACP_WR_MASK 0xff
104 #define MC_ARB_RET_CREDITS2__ACP_WR__SHIFT 0x0
105 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD_MASK 0x100
106 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_RD__SHIFT 0x8
107 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR_MASK 0x200
108 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_EN_WR__SHIFT 0x9
109 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG_MASK 0x400
110 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
111 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG_MASK 0x800
112 #define MC_ARB_RET_CREDITS2__HDP_RDRET_URG__SHIFT 0xb
113 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD_MASK 0x1000
114 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_RD__SHIFT 0xc
115 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR_MASK 0x2000
116 #define MC_ARB_RET_CREDITS2__NECKDOWN_CNTR_MONITOR_WR__SHIFT 0xd
117 #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD_MASK 0x4000
118 #define MC_ARB_RET_CREDITS2__DISABLE_DISP_RDY_RD__SHIFT 0xe
119 #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR_MASK 0x8000
120 #define MC_ARB_RET_CREDITS2__DISABLE_ACP_RDY_WR__SHIFT 0xf
121 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED_MASK 0xff0000
122 #define MC_ARB_RET_CREDITS2__RDRET_CREDIT_MED__SHIFT 0x10
123 #define MC_ARB_FED_CNTL__MODE_MASK 0x3
124 #define MC_ARB_FED_CNTL__MODE__SHIFT 0x0
125 #define MC_ARB_FED_CNTL__WR_ERR_MASK 0xc
126 #define MC_ARB_FED_CNTL__WR_ERR__SHIFT 0x2
127 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE_MASK 0x10
128 #define MC_ARB_FED_CNTL__KEEP_POISON_IN_PAGE__SHIFT 0x4
129 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK_MASK 0x20
130 #define MC_ARB_FED_CNTL__RDRET_PARITY_NACK__SHIFT 0x5
131 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK_MASK 0x40
132 #define MC_ARB_FED_CNTL__USE_LEGACY_NACK__SHIFT 0x6
133 #define MC_ARB_FED_CNTL__DEBUG_RSV_MASK 0xffffff80
134 #define MC_ARB_FED_CNTL__DEBUG_RSV__SHIFT 0x7
135 #define MC_ARB_GECC2_STATUS__CORR_STS0_MASK 0x1
136 #define MC_ARB_GECC2_STATUS__CORR_STS0__SHIFT 0x0
137 #define MC_ARB_GECC2_STATUS__UNCORR_STS0_MASK 0x2
138 #define MC_ARB_GECC2_STATUS__UNCORR_STS0__SHIFT 0x1
139 #define MC_ARB_GECC2_STATUS__FED_STS0_MASK 0x4
140 #define MC_ARB_GECC2_STATUS__FED_STS0__SHIFT 0x2
141 #define MC_ARB_GECC2_STATUS__RSVD0_MASK 0x8
142 #define MC_ARB_GECC2_STATUS__RSVD0__SHIFT 0x3
143 #define MC_ARB_GECC2_STATUS__CORR_STS1_MASK 0x10
144 #define MC_ARB_GECC2_STATUS__CORR_STS1__SHIFT 0x4
145 #define MC_ARB_GECC2_STATUS__UNCORR_STS1_MASK 0x20
146 #define MC_ARB_GECC2_STATUS__UNCORR_STS1__SHIFT 0x5
147 #define MC_ARB_GECC2_STATUS__FED_STS1_MASK 0x40
148 #define MC_ARB_GECC2_STATUS__FED_STS1__SHIFT 0x6
149 #define MC_ARB_GECC2_STATUS__RSVD1_MASK 0x80
150 #define MC_ARB_GECC2_STATUS__RSVD1__SHIFT 0x7
151 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0_MASK 0x100
152 #define MC_ARB_GECC2_STATUS__CORR_CLEAR0__SHIFT 0x8
153 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0_MASK 0x200
154 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR0__SHIFT 0x9
155 #define MC_ARB_GECC2_STATUS__FED_CLEAR0_MASK 0x400
156 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
157 #define MC_ARB_GECC2_STATUS__RSVD2_MASK 0x800
158 #define MC_ARB_GECC2_STATUS__RSVD2__SHIFT 0xb
159 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1_MASK 0x1000
160 #define MC_ARB_GECC2_STATUS__CORR_CLEAR1__SHIFT 0xc
161 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1_MASK 0x2000
162 #define MC_ARB_GECC2_STATUS__UNCORR_CLEAR1__SHIFT 0xd
163 #define MC_ARB_GECC2_STATUS__FED_CLEAR1_MASK 0x4000
164 #define MC_ARB_GECC2_STATUS__FED_CLEAR1__SHIFT 0xe
165 #define MC_ARB_GECC2_STATUS__RSVD3_MASK 0x8000
166 #define MC_ARB_GECC2_STATUS__RSVD3__SHIFT 0xf
167 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0_MASK 0x10000
168 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS0__SHIFT 0x10
169 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0_MASK 0x20000
170 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS0__SHIFT 0x11
171 #define MC_ARB_GECC2_STATUS__RSVD4_MASK 0xc0000
172 #define MC_ARB_GECC2_STATUS__RSVD4__SHIFT 0x12
173 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1_MASK 0x100000
174 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_STS1__SHIFT 0x14
175 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1_MASK 0x200000
176 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_STS1__SHIFT 0x15
177 #define MC_ARB_GECC2_STATUS__RSVD5_MASK 0xc00000
178 #define MC_ARB_GECC2_STATUS__RSVD5__SHIFT 0x16
179 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0_MASK 0x1000000
180 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR0__SHIFT 0x18
181 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0_MASK 0x2000000
182 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR0__SHIFT 0x19
183 #define MC_ARB_GECC2_STATUS__RSVD6_MASK 0xc000000
184 #define MC_ARB_GECC2_STATUS__RSVD6__SHIFT 0x1a
185 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1_MASK 0x10000000
186 #define MC_ARB_GECC2_STATUS__RMWRD_CORR_CLEAR1__SHIFT 0x1c
187 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1_MASK 0x20000000
188 #define MC_ARB_GECC2_STATUS__RMWRD_UNCORR_CLEAR1__SHIFT 0x1d
189 #define MC_ARB_GECC2_MISC__STREAK_BREAK_MASK 0xf
190 #define MC_ARB_GECC2_MISC__STREAK_BREAK__SHIFT 0x0
191 #define MC_ARB_GECC2_MISC__COL10_HACK_MASK 0x10
192 #define MC_ARB_GECC2_MISC__COL10_HACK__SHIFT 0x4
193 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY_MASK 0x20
194 #define MC_ARB_GECC2_MISC__CWRD_IN_REPLAY__SHIFT 0x5
195 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY_MASK 0x40
196 #define MC_ARB_GECC2_MISC__NO_EOB_ALL_WR_IN_REPLAY__SHIFT 0x6
197 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL_MASK 0x80
198 #define MC_ARB_GECC2_MISC__RMW_LM_WR_STALL__SHIFT 0x7
199 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE_MASK 0x100
200 #define MC_ARB_GECC2_MISC__RMW_STALL_RELEASE__SHIFT 0x8
201 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY_MASK 0x200
202 #define MC_ARB_GECC2_MISC__WR_EDC_MASK_REPLAY__SHIFT 0x9
203 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN_MASK 0x400
204 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
205 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN_MASK 0x800
206 #define MC_ARB_GECC2_MISC__WRRDWR_REPLAY_AGAIN__SHIFT 0xb
207 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY_MASK 0x1000
208 #define MC_ARB_GECC2_MISC__ALLOW_RMW_ERR_AFTER_REPLAY__SHIFT 0xc
209 #define MC_ARB_GECC2_MISC__DEBUG_RSV_MASK 0xffffe000
210 #define MC_ARB_GECC2_MISC__DEBUG_RSV__SHIFT 0xd
211 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS_MASK 0x3
212 #define MC_ARB_GECC2_DEBUG__NUM_ERR_BITS__SHIFT 0x0
213 #define MC_ARB_GECC2_DEBUG__DIRECTION_MASK 0x4
214 #define MC_ARB_GECC2_DEBUG__DIRECTION__SHIFT 0x2
215 #define MC_ARB_GECC2_DEBUG__DATA_FIELD_MASK 0x18
216 #define MC_ARB_GECC2_DEBUG__DATA_FIELD__SHIFT 0x3
217 #define MC_ARB_GECC2_DEBUG__SW_INJECTION_MASK 0x20
218 #define MC_ARB_GECC2_DEBUG__SW_INJECTION__SHIFT 0x5
219 #define MC_ARB_GECC2_DEBUG2__PERIOD_MASK 0xff
220 #define MC_ARB_GECC2_DEBUG2__PERIOD__SHIFT 0x0
221 #define MC_ARB_GECC2_DEBUG2__ERR0_START_MASK 0xff00
222 #define MC_ARB_GECC2_DEBUG2__ERR0_START__SHIFT 0x8
223 #define MC_ARB_GECC2_DEBUG2__ERR1_START_MASK 0xff0000
224 #define MC_ARB_GECC2_DEBUG2__ERR1_START__SHIFT 0x10
225 #define MC_ARB_GECC2_DEBUG2__ERR2_START_MASK 0xff000000
226 #define MC_ARB_GECC2_DEBUG2__ERR2_START__SHIFT 0x18
227 #define MC_ARB_PERF_CID__CH0_MASK 0xff
228 #define MC_ARB_PERF_CID__CH0__SHIFT 0x0
229 #define MC_ARB_PERF_CID__CH1_MASK 0xff00
230 #define MC_ARB_PERF_CID__CH1__SHIFT 0x8
231 #define MC_ARB_PERF_CID__CH0_EN_MASK 0x10000
232 #define MC_ARB_PERF_CID__CH0_EN__SHIFT 0x10
233 #define MC_ARB_PERF_CID__CH1_EN_MASK 0x20000
234 #define MC_ARB_PERF_CID__CH1_EN__SHIFT 0x11
235 #define MC_ARB_SNOOP__TC_GRP_RD_MASK 0x7
236 #define MC_ARB_SNOOP__TC_GRP_RD__SHIFT 0x0
237 #define MC_ARB_SNOOP__TC_GRP_RD_EN_MASK 0x8
238 #define MC_ARB_SNOOP__TC_GRP_RD_EN__SHIFT 0x3
239 #define MC_ARB_SNOOP__TC_GRP_WR_MASK 0x70
240 #define MC_ARB_SNOOP__TC_GRP_WR__SHIFT 0x4
241 #define MC_ARB_SNOOP__TC_GRP_WR_EN_MASK 0x80
242 #define MC_ARB_SNOOP__TC_GRP_WR_EN__SHIFT 0x7
243 #define MC_ARB_SNOOP__SDMA_GRP_RD_MASK 0x700
244 #define MC_ARB_SNOOP__SDMA_GRP_RD__SHIFT 0x8
245 #define MC_ARB_SNOOP__SDMA_GRP_RD_EN_MASK 0x800
246 #define MC_ARB_SNOOP__SDMA_GRP_RD_EN__SHIFT 0xb
247 #define MC_ARB_SNOOP__SDMA_GRP_WR_MASK 0x7000
248 #define MC_ARB_SNOOP__SDMA_GRP_WR__SHIFT 0xc
249 #define MC_ARB_SNOOP__SDMA_GRP_WR_EN_MASK 0x8000
250 #define MC_ARB_SNOOP__SDMA_GRP_WR_EN__SHIFT 0xf
251 #define MC_ARB_SNOOP__OUTSTANDING_RD_MASK 0xff0000
252 #define MC_ARB_SNOOP__OUTSTANDING_RD__SHIFT 0x10
253 #define MC_ARB_SNOOP__OUTSTANDING_WR_MASK 0xff000000
254 #define MC_ARB_SNOOP__OUTSTANDING_WR__SHIFT 0x18
255 #define MC_ARB_GRUB__GRUB_WATERMARK_MASK 0xff
256 #define MC_ARB_GRUB__GRUB_WATERMARK__SHIFT 0x0
257 #define MC_ARB_GRUB__GRUB_WATERMARK_PRI_MASK 0xff00
258 #define MC_ARB_GRUB__GRUB_WATERMARK_PRI__SHIFT 0x8
259 #define MC_ARB_GRUB__GRUB_WATERMARK_MED_MASK 0xff0000
260 #define MC_ARB_GRUB__GRUB_WATERMARK_MED__SHIFT 0x10
261 #define MC_ARB_GRUB__REG_WR_EN_MASK 0x3000000
262 #define MC_ARB_GRUB__REG_WR_EN__SHIFT 0x18
263 #define MC_ARB_GRUB__REG_RD_SEL_MASK 0x4000000
264 #define MC_ARB_GRUB__REG_RD_SEL__SHIFT 0x1a
265 #define MC_ARB_GECC2__ENABLE_MASK 0x1
266 #define MC_ARB_GECC2__ENABLE__SHIFT 0x0
267 #define MC_ARB_GECC2__ECC_MODE_MASK 0x6
268 #define MC_ARB_GECC2__ECC_MODE__SHIFT 0x1
269 #define MC_ARB_GECC2__PAGE_BIT0_MASK 0x18
270 #define MC_ARB_GECC2__PAGE_BIT0__SHIFT 0x3
271 #define MC_ARB_GECC2__EXOR_BANK_SEL_MASK 0x60
272 #define MC_ARB_GECC2__EXOR_BANK_SEL__SHIFT 0x5
273 #define MC_ARB_GECC2__NO_GECC_CLI_MASK 0x780
274 #define MC_ARB_GECC2__NO_GECC_CLI__SHIFT 0x7
275 #define MC_ARB_GECC2__READ_ERR_MASK 0x3800
276 #define MC_ARB_GECC2__READ_ERR__SHIFT 0xb
277 #define MC_ARB_GECC2__CLOSE_BANK_RMW_MASK 0x4000
278 #define MC_ARB_GECC2__CLOSE_BANK_RMW__SHIFT 0xe
279 #define MC_ARB_GECC2__COLFIFO_WATER_MASK 0x1f8000
280 #define MC_ARB_GECC2__COLFIFO_WATER__SHIFT 0xf
281 #define MC_ARB_GECC2__WRADDR_CONV_MASK 0x200000
282 #define MC_ARB_GECC2__WRADDR_CONV__SHIFT 0x15
283 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON_MASK 0x400000
284 #define MC_ARB_GECC2__RMWRD_UNCOR_POISON__SHIFT 0x16
285 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0_MASK 0xff
286 #define MC_ARB_GECC2_CLI__NO_GECC_CLI0__SHIFT 0x0
287 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1_MASK 0xff00
288 #define MC_ARB_GECC2_CLI__NO_GECC_CLI1__SHIFT 0x8
289 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2_MASK 0xff0000
290 #define MC_ARB_GECC2_CLI__NO_GECC_CLI2__SHIFT 0x10
291 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3_MASK 0xff000000
292 #define MC_ARB_GECC2_CLI__NO_GECC_CLI3__SHIFT 0x18
293 #define MC_ARB_ADDR_SWIZ0__A8_MASK 0xf
294 #define MC_ARB_ADDR_SWIZ0__A8__SHIFT 0x0
295 #define MC_ARB_ADDR_SWIZ0__A9_MASK 0xf0
296 #define MC_ARB_ADDR_SWIZ0__A9__SHIFT 0x4
297 #define MC_ARB_ADDR_SWIZ0__A10_MASK 0xf00
298 #define MC_ARB_ADDR_SWIZ0__A10__SHIFT 0x8
299 #define MC_ARB_ADDR_SWIZ0__A11_MASK 0xf000
300 #define MC_ARB_ADDR_SWIZ0__A11__SHIFT 0xc
301 #define MC_ARB_ADDR_SWIZ0__A12_MASK 0xf0000
302 #define MC_ARB_ADDR_SWIZ0__A12__SHIFT 0x10
303 #define MC_ARB_ADDR_SWIZ0__A13_MASK 0xf00000
304 #define MC_ARB_ADDR_SWIZ0__A13__SHIFT 0x14
305 #define MC_ARB_ADDR_SWIZ0__A14_MASK 0xf000000
306 #define MC_ARB_ADDR_SWIZ0__A14__SHIFT 0x18
307 #define MC_ARB_ADDR_SWIZ0__A15_MASK 0xf0000000
308 #define MC_ARB_ADDR_SWIZ0__A15__SHIFT 0x1c
309 #define MC_ARB_ADDR_SWIZ1__A16_MASK 0xf
310 #define MC_ARB_ADDR_SWIZ1__A16__SHIFT 0x0
311 #define MC_ARB_ADDR_SWIZ1__A17_MASK 0xf0
312 #define MC_ARB_ADDR_SWIZ1__A17__SHIFT 0x4
313 #define MC_ARB_ADDR_SWIZ1__A18_MASK 0xf00
314 #define MC_ARB_ADDR_SWIZ1__A18__SHIFT 0x8
315 #define MC_ARB_ADDR_SWIZ1__A19_MASK 0xf000
316 #define MC_ARB_ADDR_SWIZ1__A19__SHIFT 0xc
317 #define MC_ARB_MISC3__NO_GECC_EXT_EOB_MASK 0x1
318 #define MC_ARB_MISC3__NO_GECC_EXT_EOB__SHIFT 0x0
319 #define MC_ARB_MISC3__CHAN4_EN_MASK 0x2
320 #define MC_ARB_MISC3__CHAN4_EN__SHIFT 0x1
321 #define MC_ARB_MISC3__CHAN4_ARB_SEL_MASK 0x4
322 #define MC_ARB_MISC3__CHAN4_ARB_SEL__SHIFT 0x2
323 #define MC_ARB_MISC3__UVD_URG_MODE_MASK 0x8
324 #define MC_ARB_MISC3__UVD_URG_MODE__SHIFT 0x3
325 #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN_MASK 0x10
326 #define MC_ARB_MISC3__UVD_DMIF_HARSH_WT_EN__SHIFT 0x4
327 #define MC_ARB_MISC3__TBD_FIELD_MASK 0xffffffe0
328 #define MC_ARB_MISC3__TBD_FIELD__SHIFT 0x5
329 #define MC_ARB_GRUB_PROMOTE__URGENT_RD_MASK 0xff
330 #define MC_ARB_GRUB_PROMOTE__URGENT_RD__SHIFT 0x0
331 #define MC_ARB_GRUB_PROMOTE__URGENT_WR_MASK 0xff00
332 #define MC_ARB_GRUB_PROMOTE__URGENT_WR__SHIFT 0x8
333 #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD_MASK 0xff0000
334 #define MC_ARB_GRUB_PROMOTE__PROMOTE_RD__SHIFT 0x10
335 #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR_MASK 0xff000000
336 #define MC_ARB_GRUB_PROMOTE__PROMOTE_WR__SHIFT 0x18
337 #define MC_ARB_RTT_DATA__PATTERN_MASK 0xff
338 #define MC_ARB_RTT_DATA__PATTERN__SHIFT 0x0
339 #define MC_ARB_RTT_CNTL0__ENABLE_MASK 0x1
340 #define MC_ARB_RTT_CNTL0__ENABLE__SHIFT 0x0
341 #define MC_ARB_RTT_CNTL0__START_IDLE_MASK 0x2
342 #define MC_ARB_RTT_CNTL0__START_IDLE__SHIFT 0x1
343 #define MC_ARB_RTT_CNTL0__START_R2W_MASK 0xc
344 #define MC_ARB_RTT_CNTL0__START_R2W__SHIFT 0x2
345 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER_MASK 0x10
346 #define MC_ARB_RTT_CNTL0__FLUSH_ON_ENTER__SHIFT 0x4
347 #define MC_ARB_RTT_CNTL0__HARSH_START_MASK 0x20
348 #define MC_ARB_RTT_CNTL0__HARSH_START__SHIFT 0x5
349 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY_MASK 0x40
350 #define MC_ARB_RTT_CNTL0__TPS_HARSH_PRIORITY__SHIFT 0x6
351 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY_MASK 0x80
352 #define MC_ARB_RTT_CNTL0__TWRT_HARSH_PRIORITY__SHIFT 0x7
353 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH_MASK 0x100
354 #define MC_ARB_RTT_CNTL0__BREAK_ON_HARSH__SHIFT 0x8
355 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD_MASK 0x200
356 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTRD__SHIFT 0x9
357 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR_MASK 0x400
358 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
359 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD_MASK 0x3800
360 #define MC_ARB_RTT_CNTL0__TRAIN_PERIOD__SHIFT 0xb
361 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH_MASK 0x4000
362 #define MC_ARB_RTT_CNTL0__START_R2W_RFSH__SHIFT 0xe
363 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0_MASK 0x8000
364 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_0__SHIFT 0xf
365 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1_MASK 0x10000
366 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_1__SHIFT 0x10
367 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2_MASK 0x20000
368 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_2__SHIFT 0x11
369 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3_MASK 0x40000
370 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_3__SHIFT 0x12
371 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4_MASK 0x80000
372 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_4__SHIFT 0x13
373 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5_MASK 0x100000
374 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_5__SHIFT 0x14
375 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6_MASK 0x200000
376 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_6__SHIFT 0x15
377 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7_MASK 0x400000
378 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_7__SHIFT 0x16
379 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8_MASK 0x800000
380 #define MC_ARB_RTT_CNTL0__DEBUG_RSV_8__SHIFT 0x17
381 #define MC_ARB_RTT_CNTL0__DATA_CNTL_MASK 0x1000000
382 #define MC_ARB_RTT_CNTL0__DATA_CNTL__SHIFT 0x18
383 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT_MASK 0x2000000
384 #define MC_ARB_RTT_CNTL0__NEIGHBOR_BIT__SHIFT 0x19
385 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MASK 0x1f
386 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE__SHIFT 0x0
387 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_MASK 0x20
388 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE__SHIFT 0x5
389 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD_MASK 0x1fc0
390 #define MC_ARB_RTT_CNTL1__WINDOW_INC_THRESHOLD__SHIFT 0x6
391 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD_MASK 0xfe000
392 #define MC_ARB_RTT_CNTL1__WINDOW_DEC_THRESHOLD__SHIFT 0xd
393 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX_MASK 0x1f00000
394 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MAX__SHIFT 0x14
395 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN_MASK 0x3e000000
396 #define MC_ARB_RTT_CNTL1__WINDOW_SIZE_MIN__SHIFT 0x19
397 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT_MASK 0xc0000000
398 #define MC_ARB_RTT_CNTL1__WINDOW_UPDATE_COUNT__SHIFT 0x1e
399 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT_MASK 0x3f
400 #define MC_ARB_RTT_CNTL2__SAMPLE_CNT__SHIFT 0x0
401 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD_MASK 0xfc0
402 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_THRESHOLD__SHIFT 0x6
403 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE_MASK 0x1000
404 #define MC_ARB_RTT_CNTL2__PHASE_ADJUST_SIZE__SHIFT 0xc
405 #define MC_ARB_RTT_CNTL2__FILTER_CNTL_MASK 0x2000
406 #define MC_ARB_RTT_CNTL2__FILTER_CNTL__SHIFT 0xd
407 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0_MASK 0x3
408 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH0__SHIFT 0x0
409 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1_MASK 0xc
410 #define MC_ARB_RTT_DEBUG__DEBUG_BYTE_CH1__SHIFT 0x2
411 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0_MASK 0xff0
412 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH0__SHIFT 0x4
413 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0_MASK 0x1f000
414 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH0__SHIFT 0xc
415 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1_MASK 0x1fe0000
416 #define MC_ARB_RTT_DEBUG__SHIFTED_PHASE_CH1__SHIFT 0x11
417 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1_MASK 0x3e000000
418 #define MC_ARB_RTT_DEBUG__WINDOW_SIZE_CH1__SHIFT 0x19
419 #define MC_ARB_CAC_CNTL__ENABLE_MASK 0x1
420 #define MC_ARB_CAC_CNTL__ENABLE__SHIFT 0x0
421 #define MC_ARB_CAC_CNTL__READ_WEIGHT_MASK 0x7e
422 #define MC_ARB_CAC_CNTL__READ_WEIGHT__SHIFT 0x1
423 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT_MASK 0x1f80
424 #define MC_ARB_CAC_CNTL__WRITE_WEIGHT__SHIFT 0x7
425 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW_MASK 0x2000
426 #define MC_ARB_CAC_CNTL__ALLOW_OVERFLOW__SHIFT 0xd
427 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE_MASK 0x20
428 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_ENABLE__SHIFT 0x5
429 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4_MASK 0x40
430 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT4__SHIFT 0x6
431 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5_MASK 0x80
432 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT5__SHIFT 0x7
433 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6_MASK 0x100
434 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT6__SHIFT 0x8
435 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7_MASK 0x200
436 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT7__SHIFT 0x9
437 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8_MASK 0x400
438 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
439 #define MC_ARB_MISC2__POP_IDLE_REPLAY_MASK 0x800
440 #define MC_ARB_MISC2__POP_IDLE_REPLAY__SHIFT 0xb
441 #define MC_ARB_MISC2__RDRET_NO_REORDERING_MASK 0x1000
442 #define MC_ARB_MISC2__RDRET_NO_REORDERING__SHIFT 0xc
443 #define MC_ARB_MISC2__RDRET_NO_BP_MASK 0x2000
444 #define MC_ARB_MISC2__RDRET_NO_BP__SHIFT 0xd
445 #define MC_ARB_MISC2__RDRET_SEQ_SKID_MASK 0x3c000
446 #define MC_ARB_MISC2__RDRET_SEQ_SKID__SHIFT 0xe
447 #define MC_ARB_MISC2__GECC_MASK 0x40000
448 #define MC_ARB_MISC2__GECC__SHIFT 0x12
449 #define MC_ARB_MISC2__GECC_RST_MASK 0x80000
450 #define MC_ARB_MISC2__GECC_RST__SHIFT 0x13
451 #define MC_ARB_MISC2__GECC_STATUS_MASK 0x100000
452 #define MC_ARB_MISC2__GECC_STATUS__SHIFT 0x14
453 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD_MASK 0x1e00000
454 #define MC_ARB_MISC2__TAGFIFO_THRESHOLD__SHIFT 0x15
455 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT_MASK 0xe000000
456 #define MC_ARB_MISC2__WCDR_REPLAY_MASKCNT__SHIFT 0x19
457 #define MC_ARB_MISC2__REPLAY_DEBUG_MASK 0x10000000
458 #define MC_ARB_MISC2__REPLAY_DEBUG__SHIFT 0x1c
459 #define MC_ARB_MISC2__ARB_DEBUG29_MASK 0x20000000
460 #define MC_ARB_MISC2__ARB_DEBUG29__SHIFT 0x1d
461 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE_MASK 0x40000000
462 #define MC_ARB_MISC2__SEQ_RDY_POP_IDLE__SHIFT 0x1e
463 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB_MASK 0x80000000
464 #define MC_ARB_MISC2__TCCDL4_REPLAY_EOB__SHIFT 0x1f
465 #define MC_ARB_MISC__STICKY_RFSH_MASK 0x1
466 #define MC_ARB_MISC__STICKY_RFSH__SHIFT 0x0
467 #define MC_ARB_MISC__IDLE_RFSH_MASK 0x2
468 #define MC_ARB_MISC__IDLE_RFSH__SHIFT 0x1
469 #define MC_ARB_MISC__STUTTER_RFSH_MASK 0x4
470 #define MC_ARB_MISC__STUTTER_RFSH__SHIFT 0x2
471 #define MC_ARB_MISC__CHAN_COUPLE_MASK 0x7f8
472 #define MC_ARB_MISC__CHAN_COUPLE__SHIFT 0x3
473 #define MC_ARB_MISC__HARSHNESS_MASK 0x7f800
474 #define MC_ARB_MISC__HARSHNESS__SHIFT 0xb
475 #define MC_ARB_MISC__SMART_RDWR_SW_MASK 0x80000
476 #define MC_ARB_MISC__SMART_RDWR_SW__SHIFT 0x13
477 #define MC_ARB_MISC__CALI_ENABLE_MASK 0x100000
478 #define MC_ARB_MISC__CALI_ENABLE__SHIFT 0x14
479 #define MC_ARB_MISC__CALI_RATES_MASK 0x600000
480 #define MC_ARB_MISC__CALI_RATES__SHIFT 0x15
481 #define MC_ARB_MISC__DISPURGVLD_NOWRT_MASK 0x800000
482 #define MC_ARB_MISC__DISPURGVLD_NOWRT__SHIFT 0x17
483 #define MC_ARB_MISC__DISPURG_NOSW2WR_MASK 0x1000000
484 #define MC_ARB_MISC__DISPURG_NOSW2WR__SHIFT 0x18
485 #define MC_ARB_MISC__DISPURG_STALL_MASK 0x2000000
486 #define MC_ARB_MISC__DISPURG_STALL__SHIFT 0x19
487 #define MC_ARB_MISC__DISPURG_THROTTLE_MASK 0x3c000000
488 #define MC_ARB_MISC__DISPURG_THROTTLE__SHIFT 0x1a
489 #define MC_ARB_MISC__EXTEND_WEIGHT_MASK 0x40000000
490 #define MC_ARB_MISC__EXTEND_WEIGHT__SHIFT 0x1e
491 #define MC_ARB_MISC__ACPURG_STALL_MASK 0x80000000
492 #define MC_ARB_MISC__ACPURG_STALL__SHIFT 0x1f
493 #define MC_ARB_BANKMAP__BANK0_MASK 0xf
494 #define MC_ARB_BANKMAP__BANK0__SHIFT 0x0
495 #define MC_ARB_BANKMAP__BANK1_MASK 0xf0
496 #define MC_ARB_BANKMAP__BANK1__SHIFT 0x4
497 #define MC_ARB_BANKMAP__BANK2_MASK 0xf00
498 #define MC_ARB_BANKMAP__BANK2__SHIFT 0x8
499 #define MC_ARB_BANKMAP__BANK3_MASK 0xf000
500 #define MC_ARB_BANKMAP__BANK3__SHIFT 0xc
501 #define MC_ARB_BANKMAP__RANK_MASK 0xf0000
502 #define MC_ARB_BANKMAP__RANK__SHIFT 0x10
503 #define MC_ARB_RAMCFG__NOOFBANK_MASK 0x3
504 #define MC_ARB_RAMCFG__NOOFBANK__SHIFT 0x0
505 #define MC_ARB_RAMCFG__NOOFRANKS_MASK 0x4
506 #define MC_ARB_RAMCFG__NOOFRANKS__SHIFT 0x2
507 #define MC_ARB_RAMCFG__NOOFROWS_MASK 0x38
508 #define MC_ARB_RAMCFG__NOOFROWS__SHIFT 0x3
509 #define MC_ARB_RAMCFG__NOOFCOLS_MASK 0xc0
510 #define MC_ARB_RAMCFG__NOOFCOLS__SHIFT 0x6
511 #define MC_ARB_RAMCFG__CHANSIZE_MASK 0x100
512 #define MC_ARB_RAMCFG__CHANSIZE__SHIFT 0x8
513 #define MC_ARB_RAMCFG__RSV_1_MASK 0x200
514 #define MC_ARB_RAMCFG__RSV_1__SHIFT 0x9
515 #define MC_ARB_RAMCFG__RSV_2_MASK 0x400
516 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
517 #define MC_ARB_RAMCFG__RSV_3_MASK 0x800
518 #define MC_ARB_RAMCFG__RSV_3__SHIFT 0xb
519 #define MC_ARB_RAMCFG__NOOFGROUPS_MASK 0x1000
520 #define MC_ARB_RAMCFG__NOOFGROUPS__SHIFT 0xc
521 #define MC_ARB_RAMCFG__RSV_4_MASK 0x3e000
522 #define MC_ARB_RAMCFG__RSV_4__SHIFT 0xd
523 #define MC_ARB_POP__ENABLE_ARB_MASK 0x1
524 #define MC_ARB_POP__ENABLE_ARB__SHIFT 0x0
525 #define MC_ARB_POP__SPEC_OPEN_MASK 0x2
526 #define MC_ARB_POP__SPEC_OPEN__SHIFT 0x1
527 #define MC_ARB_POP__POP_DEPTH_MASK 0x3c
528 #define MC_ARB_POP__POP_DEPTH__SHIFT 0x2
529 #define MC_ARB_POP__WRDATAINDEX_DEPTH_MASK 0xfc0
530 #define MC_ARB_POP__WRDATAINDEX_DEPTH__SHIFT 0x6
531 #define MC_ARB_POP__SKID_DEPTH_MASK 0x7000
532 #define MC_ARB_POP__SKID_DEPTH__SHIFT 0xc
533 #define MC_ARB_POP__WAIT_AFTER_RFSH_MASK 0x18000
534 #define MC_ARB_POP__WAIT_AFTER_RFSH__SHIFT 0xf
535 #define MC_ARB_POP__QUICK_STOP_MASK 0x20000
536 #define MC_ARB_POP__QUICK_STOP__SHIFT 0x11
537 #define MC_ARB_POP__ENABLE_TWO_PAGE_MASK 0x40000
538 #define MC_ARB_POP__ENABLE_TWO_PAGE__SHIFT 0x12
539 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL_MASK 0x80000
540 #define MC_ARB_POP__ALLOW_EOB_BY_WRRET_STALL__SHIFT 0x13
541 #define MC_ARB_MINCLKS__READ_CLKS_MASK 0xff
542 #define MC_ARB_MINCLKS__READ_CLKS__SHIFT 0x0
543 #define MC_ARB_MINCLKS__WRITE_CLKS_MASK 0xff00
544 #define MC_ARB_MINCLKS__WRITE_CLKS__SHIFT 0x8
545 #define MC_ARB_MINCLKS__ARB_RW_SWITCH_MASK 0x10000
546 #define MC_ARB_MINCLKS__ARB_RW_SWITCH__SHIFT 0x10
547 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH_MASK 0x60000
548 #define MC_ARB_MINCLKS__RW_SWITCH_HARSH__SHIFT 0x11
549 #define MC_ARB_SQM_CNTL__MIN_PENAL_MASK 0xff
550 #define MC_ARB_SQM_CNTL__MIN_PENAL__SHIFT 0x0
551 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE_MASK 0x100
552 #define MC_ARB_SQM_CNTL__DYN_SQM_ENABLE__SHIFT 0x8
553 #define MC_ARB_SQM_CNTL__SQM_RDY16_MASK 0x200
554 #define MC_ARB_SQM_CNTL__SQM_RDY16__SHIFT 0x9
555 #define MC_ARB_SQM_CNTL__SQM_RESERVE_MASK 0xfc00
556 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
557 #define MC_ARB_SQM_CNTL__RATIO_MASK 0xff0000
558 #define MC_ARB_SQM_CNTL__RATIO__SHIFT 0x10
559 #define MC_ARB_SQM_CNTL__RATIO_DEBUG_MASK 0xff000000
560 #define MC_ARB_SQM_CNTL__RATIO_DEBUG__SHIFT 0x18
561 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE_MASK 0xf
562 #define MC_ARB_ADDR_HASH__BANK_XOR_ENABLE__SHIFT 0x0
563 #define MC_ARB_ADDR_HASH__COL_XOR_MASK 0xff0
564 #define MC_ARB_ADDR_HASH__COL_XOR__SHIFT 0x4
565 #define MC_ARB_ADDR_HASH__ROW_XOR_MASK 0xffff000
566 #define MC_ARB_ADDR_HASH__ROW_XOR__SHIFT 0xc
567 #define MC_ARB_DRAM_TIMING__ACTRD_MASK 0xff
568 #define MC_ARB_DRAM_TIMING__ACTRD__SHIFT 0x0
569 #define MC_ARB_DRAM_TIMING__ACTWR_MASK 0xff00
570 #define MC_ARB_DRAM_TIMING__ACTWR__SHIFT 0x8
571 #define MC_ARB_DRAM_TIMING__RASMACTRD_MASK 0xff0000
572 #define MC_ARB_DRAM_TIMING__RASMACTRD__SHIFT 0x10
573 #define MC_ARB_DRAM_TIMING__RASMACTWR_MASK 0xff000000
574 #define MC_ARB_DRAM_TIMING__RASMACTWR__SHIFT 0x18
575 #define MC_ARB_DRAM_TIMING2__RAS2RAS_MASK 0xff
576 #define MC_ARB_DRAM_TIMING2__RAS2RAS__SHIFT 0x0
577 #define MC_ARB_DRAM_TIMING2__RP_MASK 0xff00
578 #define MC_ARB_DRAM_TIMING2__RP__SHIFT 0x8
579 #define MC_ARB_DRAM_TIMING2__WRPLUSRP_MASK 0xff0000
580 #define MC_ARB_DRAM_TIMING2__WRPLUSRP__SHIFT 0x10
581 #define MC_ARB_DRAM_TIMING2__BUS_TURN_MASK 0x1f000000
582 #define MC_ARB_DRAM_TIMING2__BUS_TURN__SHIFT 0x18
583 #define MC_ARB_WTM_CNTL_RD__WTMODE_MASK 0x3
584 #define MC_ARB_WTM_CNTL_RD__WTMODE__SHIFT 0x0
585 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI_MASK 0x4
586 #define MC_ARB_WTM_CNTL_RD__HARSH_PRI__SHIFT 0x2
587 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0_MASK 0x8
588 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP0__SHIFT 0x3
589 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1_MASK 0x10
590 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP1__SHIFT 0x4
591 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2_MASK 0x20
592 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP2__SHIFT 0x5
593 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3_MASK 0x40
594 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP3__SHIFT 0x6
595 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4_MASK 0x80
596 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP4__SHIFT 0x7
597 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5_MASK 0x100
598 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP5__SHIFT 0x8
599 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6_MASK 0x200
600 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP6__SHIFT 0x9
601 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7_MASK 0x400
602 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
603 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI_MASK 0x800
604 #define MC_ARB_WTM_CNTL_RD__ACP_HARSH_PRI__SHIFT 0xb
605 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP_MASK 0x1000
606 #define MC_ARB_WTM_CNTL_RD__ACP_OVER_DISP__SHIFT 0xc
607 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG_MASK 0x2000
608 #define MC_ARB_WTM_CNTL_RD__FORCE_ACP_URG__SHIFT 0xd
609 #define MC_ARB_WTM_CNTL_WR__WTMODE_MASK 0x3
610 #define MC_ARB_WTM_CNTL_WR__WTMODE__SHIFT 0x0
611 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI_MASK 0x4
612 #define MC_ARB_WTM_CNTL_WR__HARSH_PRI__SHIFT 0x2
613 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0_MASK 0x8
614 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP0__SHIFT 0x3
615 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1_MASK 0x10
616 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP1__SHIFT 0x4
617 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2_MASK 0x20
618 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP2__SHIFT 0x5
619 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3_MASK 0x40
620 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP3__SHIFT 0x6
621 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4_MASK 0x80
622 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP4__SHIFT 0x7
623 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5_MASK 0x100
624 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP5__SHIFT 0x8
625 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6_MASK 0x200
626 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP6__SHIFT 0x9
627 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7_MASK 0x400
628 #define MC_ARB_WTM_CNTL_WR__ALLOW_STUTTER_GRP7__SHIFT 0xa
629 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI_MASK 0x800
630 #define MC_ARB_WTM_CNTL_WR__ACP_HARSH_PRI__SHIFT 0xb
631 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP_MASK 0x1000
632 #define MC_ARB_WTM_CNTL_WR__ACP_OVER_DISP__SHIFT 0xc
633 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG_MASK 0x2000
634 #define MC_ARB_WTM_CNTL_WR__FORCE_ACP_URG__SHIFT 0xd
635 #define MC_ARB_WTM_GRPWT_RD__GRP0_MASK 0x3
636 #define MC_ARB_WTM_GRPWT_RD__GRP0__SHIFT 0x0
637 #define MC_ARB_WTM_GRPWT_RD__GRP1_MASK 0xc
638 #define MC_ARB_WTM_GRPWT_RD__GRP1__SHIFT 0x2
639 #define MC_ARB_WTM_GRPWT_RD__GRP2_MASK 0x30
640 #define MC_ARB_WTM_GRPWT_RD__GRP2__SHIFT 0x4
641 #define MC_ARB_WTM_GRPWT_RD__GRP3_MASK 0xc0
642 #define MC_ARB_WTM_GRPWT_RD__GRP3__SHIFT 0x6
643 #define MC_ARB_WTM_GRPWT_RD__GRP4_MASK 0x300
644 #define MC_ARB_WTM_GRPWT_RD__GRP4__SHIFT 0x8
645 #define MC_ARB_WTM_GRPWT_RD__GRP5_MASK 0xc00
646 #define MC_ARB_WTM_GRPWT_RD__GRP5__SHIFT 0xa
647 #define MC_ARB_WTM_GRPWT_RD__GRP6_MASK 0x3000
648 #define MC_ARB_WTM_GRPWT_RD__GRP6__SHIFT 0xc
649 #define MC_ARB_WTM_GRPWT_RD__GRP7_MASK 0xc000
650 #define MC_ARB_WTM_GRPWT_RD__GRP7__SHIFT 0xe
651 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT_MASK 0xff0000
652 #define MC_ARB_WTM_GRPWT_RD__GRP_EXT__SHIFT 0x10
653 #define MC_ARB_WTM_GRPWT_WR__GRP0_MASK 0x3
654 #define MC_ARB_WTM_GRPWT_WR__GRP0__SHIFT 0x0
655 #define MC_ARB_WTM_GRPWT_WR__GRP1_MASK 0xc
656 #define MC_ARB_WTM_GRPWT_WR__GRP1__SHIFT 0x2
657 #define MC_ARB_WTM_GRPWT_WR__GRP2_MASK 0x30
658 #define MC_ARB_WTM_GRPWT_WR__GRP2__SHIFT 0x4
659 #define MC_ARB_WTM_GRPWT_WR__GRP3_MASK 0xc0
660 #define MC_ARB_WTM_GRPWT_WR__GRP3__SHIFT 0x6
661 #define MC_ARB_WTM_GRPWT_WR__GRP4_MASK 0x300
662 #define MC_ARB_WTM_GRPWT_WR__GRP4__SHIFT 0x8
663 #define MC_ARB_WTM_GRPWT_WR__GRP5_MASK 0xc00
664 #define MC_ARB_WTM_GRPWT_WR__GRP5__SHIFT 0xa
665 #define MC_ARB_WTM_GRPWT_WR__GRP6_MASK 0x3000
666 #define MC_ARB_WTM_GRPWT_WR__GRP6__SHIFT 0xc
667 #define MC_ARB_WTM_GRPWT_WR__GRP7_MASK 0xc000
668 #define MC_ARB_WTM_GRPWT_WR__GRP7__SHIFT 0xe
669 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT_MASK 0xff0000
670 #define MC_ARB_WTM_GRPWT_WR__GRP_EXT__SHIFT 0x10
671 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK_MASK 0x1
672 #define MC_ARB_TM_CNTL_RD__GROUPBY_RANK__SHIFT 0x0
673 #define MC_ARB_TM_CNTL_RD__BANK_SELECT_MASK 0x6
674 #define MC_ARB_TM_CNTL_RD__BANK_SELECT__SHIFT 0x1
675 #define MC_ARB_TM_CNTL_RD__MATCH_RANK_MASK 0x8
676 #define MC_ARB_TM_CNTL_RD__MATCH_RANK__SHIFT 0x3
677 #define MC_ARB_TM_CNTL_RD__MATCH_BANK_MASK 0x10
678 #define MC_ARB_TM_CNTL_RD__MATCH_BANK__SHIFT 0x4
679 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK_MASK 0x1
680 #define MC_ARB_TM_CNTL_WR__GROUPBY_RANK__SHIFT 0x0
681 #define MC_ARB_TM_CNTL_WR__BANK_SELECT_MASK 0x6
682 #define MC_ARB_TM_CNTL_WR__BANK_SELECT__SHIFT 0x1
683 #define MC_ARB_TM_CNTL_WR__MATCH_RANK_MASK 0x8
684 #define MC_ARB_TM_CNTL_WR__MATCH_RANK__SHIFT 0x3
685 #define MC_ARB_TM_CNTL_WR__MATCH_BANK_MASK 0x10
686 #define MC_ARB_TM_CNTL_WR__MATCH_BANK__SHIFT 0x4
687 #define MC_ARB_LAZY0_RD__GROUP0_MASK 0xff
688 #define MC_ARB_LAZY0_RD__GROUP0__SHIFT 0x0
689 #define MC_ARB_LAZY0_RD__GROUP1_MASK 0xff00
690 #define MC_ARB_LAZY0_RD__GROUP1__SHIFT 0x8
691 #define MC_ARB_LAZY0_RD__GROUP2_MASK 0xff0000
692 #define MC_ARB_LAZY0_RD__GROUP2__SHIFT 0x10
693 #define MC_ARB_LAZY0_RD__GROUP3_MASK 0xff000000
694 #define MC_ARB_LAZY0_RD__GROUP3__SHIFT 0x18
695 #define MC_ARB_LAZY0_WR__GROUP0_MASK 0xff
696 #define MC_ARB_LAZY0_WR__GROUP0__SHIFT 0x0
697 #define MC_ARB_LAZY0_WR__GROUP1_MASK 0xff00
698 #define MC_ARB_LAZY0_WR__GROUP1__SHIFT 0x8
699 #define MC_ARB_LAZY0_WR__GROUP2_MASK 0xff0000
700 #define MC_ARB_LAZY0_WR__GROUP2__SHIFT 0x10
701 #define MC_ARB_LAZY0_WR__GROUP3_MASK 0xff000000
702 #define MC_ARB_LAZY0_WR__GROUP3__SHIFT 0x18
703 #define MC_ARB_LAZY1_RD__GROUP4_MASK 0xff
704 #define MC_ARB_LAZY1_RD__GROUP4__SHIFT 0x0
705 #define MC_ARB_LAZY1_RD__GROUP5_MASK 0xff00
706 #define MC_ARB_LAZY1_RD__GROUP5__SHIFT 0x8
707 #define MC_ARB_LAZY1_RD__GROUP6_MASK 0xff0000
708 #define MC_ARB_LAZY1_RD__GROUP6__SHIFT 0x10
709 #define MC_ARB_LAZY1_RD__GROUP7_MASK 0xff000000
710 #define MC_ARB_LAZY1_RD__GROUP7__SHIFT 0x18
711 #define MC_ARB_LAZY1_WR__GROUP4_MASK 0xff
712 #define MC_ARB_LAZY1_WR__GROUP4__SHIFT 0x0
713 #define MC_ARB_LAZY1_WR__GROUP5_MASK 0xff00
714 #define MC_ARB_LAZY1_WR__GROUP5__SHIFT 0x8
715 #define MC_ARB_LAZY1_WR__GROUP6_MASK 0xff0000
716 #define MC_ARB_LAZY1_WR__GROUP6__SHIFT 0x10
717 #define MC_ARB_LAZY1_WR__GROUP7_MASK 0xff000000
718 #define MC_ARB_LAZY1_WR__GROUP7__SHIFT 0x18
719 #define MC_ARB_AGE_RD__RATE_GROUP0_MASK 0x3
720 #define MC_ARB_AGE_RD__RATE_GROUP0__SHIFT 0x0
721 #define MC_ARB_AGE_RD__RATE_GROUP1_MASK 0xc
722 #define MC_ARB_AGE_RD__RATE_GROUP1__SHIFT 0x2
723 #define MC_ARB_AGE_RD__RATE_GROUP2_MASK 0x30
724 #define MC_ARB_AGE_RD__RATE_GROUP2__SHIFT 0x4
725 #define MC_ARB_AGE_RD__RATE_GROUP3_MASK 0xc0
726 #define MC_ARB_AGE_RD__RATE_GROUP3__SHIFT 0x6
727 #define MC_ARB_AGE_RD__RATE_GROUP4_MASK 0x300
728 #define MC_ARB_AGE_RD__RATE_GROUP4__SHIFT 0x8
729 #define MC_ARB_AGE_RD__RATE_GROUP5_MASK 0xc00
730 #define MC_ARB_AGE_RD__RATE_GROUP5__SHIFT 0xa
731 #define MC_ARB_AGE_RD__RATE_GROUP6_MASK 0x3000
732 #define MC_ARB_AGE_RD__RATE_GROUP6__SHIFT 0xc
733 #define MC_ARB_AGE_RD__RATE_GROUP7_MASK 0xc000
734 #define MC_ARB_AGE_RD__RATE_GROUP7__SHIFT 0xe
735 #define MC_ARB_AGE_RD__ENABLE_GROUP0_MASK 0x10000
736 #define MC_ARB_AGE_RD__ENABLE_GROUP0__SHIFT 0x10
737 #define MC_ARB_AGE_RD__ENABLE_GROUP1_MASK 0x20000
738 #define MC_ARB_AGE_RD__ENABLE_GROUP1__SHIFT 0x11
739 #define MC_ARB_AGE_RD__ENABLE_GROUP2_MASK 0x40000
740 #define MC_ARB_AGE_RD__ENABLE_GROUP2__SHIFT 0x12
741 #define MC_ARB_AGE_RD__ENABLE_GROUP3_MASK 0x80000
742 #define MC_ARB_AGE_RD__ENABLE_GROUP3__SHIFT 0x13
743 #define MC_ARB_AGE_RD__ENABLE_GROUP4_MASK 0x100000
744 #define MC_ARB_AGE_RD__ENABLE_GROUP4__SHIFT 0x14
745 #define MC_ARB_AGE_RD__ENABLE_GROUP5_MASK 0x200000
746 #define MC_ARB_AGE_RD__ENABLE_GROUP5__SHIFT 0x15
747 #define MC_ARB_AGE_RD__ENABLE_GROUP6_MASK 0x400000
748 #define MC_ARB_AGE_RD__ENABLE_GROUP6__SHIFT 0x16
749 #define MC_ARB_AGE_RD__ENABLE_GROUP7_MASK 0x800000
750 #define MC_ARB_AGE_RD__ENABLE_GROUP7__SHIFT 0x17
751 #define MC_ARB_AGE_RD__DIVIDE_GROUP0_MASK 0x1000000
752 #define MC_ARB_AGE_RD__DIVIDE_GROUP0__SHIFT 0x18
753 #define MC_ARB_AGE_RD__DIVIDE_GROUP1_MASK 0x2000000
754 #define MC_ARB_AGE_RD__DIVIDE_GROUP1__SHIFT 0x19
755 #define MC_ARB_AGE_RD__DIVIDE_GROUP2_MASK 0x4000000
756 #define MC_ARB_AGE_RD__DIVIDE_GROUP2__SHIFT 0x1a
757 #define MC_ARB_AGE_RD__DIVIDE_GROUP3_MASK 0x8000000
758 #define MC_ARB_AGE_RD__DIVIDE_GROUP3__SHIFT 0x1b
759 #define MC_ARB_AGE_RD__DIVIDE_GROUP4_MASK 0x10000000
760 #define MC_ARB_AGE_RD__DIVIDE_GROUP4__SHIFT 0x1c
761 #define MC_ARB_AGE_RD__DIVIDE_GROUP5_MASK 0x20000000
762 #define MC_ARB_AGE_RD__DIVIDE_GROUP5__SHIFT 0x1d
763 #define MC_ARB_AGE_RD__DIVIDE_GROUP6_MASK 0x40000000
764 #define MC_ARB_AGE_RD__DIVIDE_GROUP6__SHIFT 0x1e
765 #define MC_ARB_AGE_RD__DIVIDE_GROUP7_MASK 0x80000000
766 #define MC_ARB_AGE_RD__DIVIDE_GROUP7__SHIFT 0x1f
767 #define MC_ARB_AGE_WR__RATE_GROUP0_MASK 0x3
768 #define MC_ARB_AGE_WR__RATE_GROUP0__SHIFT 0x0
769 #define MC_ARB_AGE_WR__RATE_GROUP1_MASK 0xc
770 #define MC_ARB_AGE_WR__RATE_GROUP1__SHIFT 0x2
771 #define MC_ARB_AGE_WR__RATE_GROUP2_MASK 0x30
772 #define MC_ARB_AGE_WR__RATE_GROUP2__SHIFT 0x4
773 #define MC_ARB_AGE_WR__RATE_GROUP3_MASK 0xc0
774 #define MC_ARB_AGE_WR__RATE_GROUP3__SHIFT 0x6
775 #define MC_ARB_AGE_WR__RATE_GROUP4_MASK 0x300
776 #define MC_ARB_AGE_WR__RATE_GROUP4__SHIFT 0x8
777 #define MC_ARB_AGE_WR__RATE_GROUP5_MASK 0xc00
778 #define MC_ARB_AGE_WR__RATE_GROUP5__SHIFT 0xa
779 #define MC_ARB_AGE_WR__RATE_GROUP6_MASK 0x3000
780 #define MC_ARB_AGE_WR__RATE_GROUP6__SHIFT 0xc
781 #define MC_ARB_AGE_WR__RATE_GROUP7_MASK 0xc000
782 #define MC_ARB_AGE_WR__RATE_GROUP7__SHIFT 0xe
783 #define MC_ARB_AGE_WR__ENABLE_GROUP0_MASK 0x10000
784 #define MC_ARB_AGE_WR__ENABLE_GROUP0__SHIFT 0x10
785 #define MC_ARB_AGE_WR__ENABLE_GROUP1_MASK 0x20000
786 #define MC_ARB_AGE_WR__ENABLE_GROUP1__SHIFT 0x11
787 #define MC_ARB_AGE_WR__ENABLE_GROUP2_MASK 0x40000
788 #define MC_ARB_AGE_WR__ENABLE_GROUP2__SHIFT 0x12
789 #define MC_ARB_AGE_WR__ENABLE_GROUP3_MASK 0x80000
790 #define MC_ARB_AGE_WR__ENABLE_GROUP3__SHIFT 0x13
791 #define MC_ARB_AGE_WR__ENABLE_GROUP4_MASK 0x100000
792 #define MC_ARB_AGE_WR__ENABLE_GROUP4__SHIFT 0x14
793 #define MC_ARB_AGE_WR__ENABLE_GROUP5_MASK 0x200000
794 #define MC_ARB_AGE_WR__ENABLE_GROUP5__SHIFT 0x15
795 #define MC_ARB_AGE_WR__ENABLE_GROUP6_MASK 0x400000
796 #define MC_ARB_AGE_WR__ENABLE_GROUP6__SHIFT 0x16
797 #define MC_ARB_AGE_WR__ENABLE_GROUP7_MASK 0x800000
798 #define MC_ARB_AGE_WR__ENABLE_GROUP7__SHIFT 0x17
799 #define MC_ARB_AGE_WR__DIVIDE_GROUP0_MASK 0x1000000
800 #define MC_ARB_AGE_WR__DIVIDE_GROUP0__SHIFT 0x18
801 #define MC_ARB_AGE_WR__DIVIDE_GROUP1_MASK 0x2000000
802 #define MC_ARB_AGE_WR__DIVIDE_GROUP1__SHIFT 0x19
803 #define MC_ARB_AGE_WR__DIVIDE_GROUP2_MASK 0x4000000
804 #define MC_ARB_AGE_WR__DIVIDE_GROUP2__SHIFT 0x1a
805 #define MC_ARB_AGE_WR__DIVIDE_GROUP3_MASK 0x8000000
806 #define MC_ARB_AGE_WR__DIVIDE_GROUP3__SHIFT 0x1b
807 #define MC_ARB_AGE_WR__DIVIDE_GROUP4_MASK 0x10000000
808 #define MC_ARB_AGE_WR__DIVIDE_GROUP4__SHIFT 0x1c
809 #define MC_ARB_AGE_WR__DIVIDE_GROUP5_MASK 0x20000000
810 #define MC_ARB_AGE_WR__DIVIDE_GROUP5__SHIFT 0x1d
811 #define MC_ARB_AGE_WR__DIVIDE_GROUP6_MASK 0x40000000
812 #define MC_ARB_AGE_WR__DIVIDE_GROUP6__SHIFT 0x1e
813 #define MC_ARB_AGE_WR__DIVIDE_GROUP7_MASK 0x80000000
814 #define MC_ARB_AGE_WR__DIVIDE_GROUP7__SHIFT 0x1f
815 #define MC_ARB_RFSH_CNTL__ENABLE_MASK 0x1
816 #define MC_ARB_RFSH_CNTL__ENABLE__SHIFT 0x0
817 #define MC_ARB_RFSH_CNTL__URG0_MASK 0x3e
818 #define MC_ARB_RFSH_CNTL__URG0__SHIFT 0x1
819 #define MC_ARB_RFSH_CNTL__URG1_MASK 0x7c0
820 #define MC_ARB_RFSH_CNTL__URG1__SHIFT 0x6
821 #define MC_ARB_RFSH_CNTL__ACCUM_MASK 0x800
822 #define MC_ARB_RFSH_CNTL__ACCUM__SHIFT 0xb
823 #define MC_ARB_RFSH_CNTL__SINGLE_BANK_MASK 0x1000
824 #define MC_ARB_RFSH_CNTL__SINGLE_BANK__SHIFT 0xc
825 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH_MASK 0x2000
826 #define MC_ARB_RFSH_CNTL__PUSH_SINGLE_BANK_REFRESH__SHIFT 0xd
827 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL_MASK 0x1c000
828 #define MC_ARB_RFSH_CNTL__PENDING_RATE_SEL__SHIFT 0xe
829 #define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE_MASK 0x20000
830 #define MC_ARB_RFSH_CNTL__REFSB_PER_PAGE__SHIFT 0x11
831 #define MC_ARB_RFSH_RATE__POWERMODE0_MASK 0xff
832 #define MC_ARB_RFSH_RATE__POWERMODE0__SHIFT 0x0
833 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE_MASK 0x3
834 #define MC_ARB_PM_CNTL__OVERRIDE_CGSTATE__SHIFT 0x0
835 #define MC_ARB_PM_CNTL__OVRR_CGRFSH_MASK 0x4
836 #define MC_ARB_PM_CNTL__OVRR_CGRFSH__SHIFT 0x2
837 #define MC_ARB_PM_CNTL__OVRR_CGSQM_MASK 0x8
838 #define MC_ARB_PM_CNTL__OVRR_CGSQM__SHIFT 0x3
839 #define MC_ARB_PM_CNTL__SRFSH_ON_D1_MASK 0x10
840 #define MC_ARB_PM_CNTL__SRFSH_ON_D1__SHIFT 0x4
841 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1_MASK 0x20
842 #define MC_ARB_PM_CNTL__BLKOUT_ON_D1__SHIFT 0x5
843 #define MC_ARB_PM_CNTL__IDLE_ON_D1_MASK 0x40
844 #define MC_ARB_PM_CNTL__IDLE_ON_D1__SHIFT 0x6
845 #define MC_ARB_PM_CNTL__OVRR_PM_MASK 0x80
846 #define MC_ARB_PM_CNTL__OVRR_PM__SHIFT 0x7
847 #define MC_ARB_PM_CNTL__OVRR_PM_STATE_MASK 0x300
848 #define MC_ARB_PM_CNTL__OVRR_PM_STATE__SHIFT 0x8
849 #define MC_ARB_PM_CNTL__OVRR_RD_MASK 0x400
850 #define MC_ARB_PM_CNTL__OVRR_RD__SHIFT 0xa
851 #define MC_ARB_PM_CNTL__OVRR_RD_STATE_MASK 0x800
852 #define MC_ARB_PM_CNTL__OVRR_RD_STATE__SHIFT 0xb
853 #define MC_ARB_PM_CNTL__OVRR_WR_MASK 0x1000
854 #define MC_ARB_PM_CNTL__OVRR_WR__SHIFT 0xc
855 #define MC_ARB_PM_CNTL__OVRR_WR_STATE_MASK 0x2000
856 #define MC_ARB_PM_CNTL__OVRR_WR_STATE__SHIFT 0xd
857 #define MC_ARB_PM_CNTL__OVRR_RFSH_MASK 0x4000
858 #define MC_ARB_PM_CNTL__OVRR_RFSH__SHIFT 0xe
859 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE_MASK 0x8000
860 #define MC_ARB_PM_CNTL__OVRR_RFSH_STATE__SHIFT 0xf
861 #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY_MASK 0x10000
862 #define MC_ARB_PM_CNTL__OVRR_RD0_BUSY__SHIFT 0x10
863 #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY_MASK 0x20000
864 #define MC_ARB_PM_CNTL__OVRR_RD1_BUSY__SHIFT 0x11
865 #define MC_ARB_PM_CNTL__IDLE_ON_D2_MASK 0x40000
866 #define MC_ARB_PM_CNTL__IDLE_ON_D2__SHIFT 0x12
867 #define MC_ARB_PM_CNTL__IDLE_ON_D3_MASK 0x80000
868 #define MC_ARB_PM_CNTL__IDLE_ON_D3__SHIFT 0x13
869 #define MC_ARB_PM_CNTL__IDLE_CNT_MASK 0xf00000
870 #define MC_ARB_PM_CNTL__IDLE_CNT__SHIFT 0x14
871 #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY_MASK 0x1000000
872 #define MC_ARB_PM_CNTL__OVRR_WR0_BUSY__SHIFT 0x18
873 #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY_MASK 0x2000000
874 #define MC_ARB_PM_CNTL__OVRR_WR1_BUSY__SHIFT 0x19
875 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0_MASK 0xf
876 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT0__SHIFT 0x0
877 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1_MASK 0xf0
878 #define MC_ARB_GDEC_RD_CNTL__PAGEBIT1__SHIFT 0x4
879 #define MC_ARB_GDEC_RD_CNTL__USE_RANK_MASK 0x100
880 #define MC_ARB_GDEC_RD_CNTL__USE_RANK__SHIFT 0x8
881 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO_MASK 0x200
882 #define MC_ARB_GDEC_RD_CNTL__USE_RSNO__SHIFT 0x9
883 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
884 #define MC_ARB_GDEC_RD_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
885 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0_MASK 0xf
886 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT0__SHIFT 0x0
887 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1_MASK 0xf0
888 #define MC_ARB_GDEC_WR_CNTL__PAGEBIT1__SHIFT 0x4
889 #define MC_ARB_GDEC_WR_CNTL__USE_RANK_MASK 0x100
890 #define MC_ARB_GDEC_WR_CNTL__USE_RANK__SHIFT 0x8
891 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO_MASK 0x200
892 #define MC_ARB_GDEC_WR_CNTL__USE_RSNO__SHIFT 0x9
893 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP_MASK 0x3c00
894 #define MC_ARB_GDEC_WR_CNTL__REM_DEFAULT_GRP__SHIFT 0xa
895 #define MC_ARB_LM_RD__STREAK_LIMIT_MASK 0xff
896 #define MC_ARB_LM_RD__STREAK_LIMIT__SHIFT 0x0
897 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER_MASK 0xff00
898 #define MC_ARB_LM_RD__STREAK_LIMIT_UBER__SHIFT 0x8
899 #define MC_ARB_LM_RD__STREAK_BREAK_MASK 0x10000
900 #define MC_ARB_LM_RD__STREAK_BREAK__SHIFT 0x10
901 #define MC_ARB_LM_RD__STREAK_UBER_MASK 0x20000
902 #define MC_ARB_LM_RD__STREAK_UBER__SHIFT 0x11
903 #define MC_ARB_LM_RD__ENABLE_TWO_LIST_MASK 0x40000
904 #define MC_ARB_LM_RD__ENABLE_TWO_LIST__SHIFT 0x12
905 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST_MASK 0x80000
906 #define MC_ARB_LM_RD__POPIDLE_RST_TWOLIST__SHIFT 0x13
907 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST_MASK 0x100000
908 #define MC_ARB_LM_RD__SKID1_RST_TWOLIST__SHIFT 0x14
909 #define MC_ARB_LM_RD__BANKGROUP_CONFIG_MASK 0xe00000
910 #define MC_ARB_LM_RD__BANKGROUP_CONFIG__SHIFT 0x15
911 #define MC_ARB_LM_WR__STREAK_LIMIT_MASK 0xff
912 #define MC_ARB_LM_WR__STREAK_LIMIT__SHIFT 0x0
913 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER_MASK 0xff00
914 #define MC_ARB_LM_WR__STREAK_LIMIT_UBER__SHIFT 0x8
915 #define MC_ARB_LM_WR__STREAK_BREAK_MASK 0x10000
916 #define MC_ARB_LM_WR__STREAK_BREAK__SHIFT 0x10
917 #define MC_ARB_LM_WR__STREAK_UBER_MASK 0x20000
918 #define MC_ARB_LM_WR__STREAK_UBER__SHIFT 0x11
919 #define MC_ARB_LM_WR__ENABLE_TWO_LIST_MASK 0x40000
920 #define MC_ARB_LM_WR__ENABLE_TWO_LIST__SHIFT 0x12
921 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST_MASK 0x80000
922 #define MC_ARB_LM_WR__POPIDLE_RST_TWOLIST__SHIFT 0x13
923 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST_MASK 0x100000
924 #define MC_ARB_LM_WR__SKID1_RST_TWOLIST__SHIFT 0x14
925 #define MC_ARB_LM_WR__BANKGROUP_CONFIG_MASK 0xe00000
926 #define MC_ARB_LM_WR__BANKGROUP_CONFIG__SHIFT 0x15
927 #define MC_ARB_LM_WR__MASKWR_LM_EOB_MASK 0x1000000
928 #define MC_ARB_LM_WR__MASKWR_LM_EOB__SHIFT 0x18
929 #define MC_ARB_LM_WR__ATOMIC_LM_EOB_MASK 0x2000000
930 #define MC_ARB_LM_WR__ATOMIC_LM_EOB__SHIFT 0x19
931 #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB_MASK 0x4000000
932 #define MC_ARB_LM_WR__ATOMIC_RTN_LM_EOB__SHIFT 0x1a
933 #define MC_ARB_REMREQ__RD_WATER_MASK 0xff
934 #define MC_ARB_REMREQ__RD_WATER__SHIFT 0x0
935 #define MC_ARB_REMREQ__WR_WATER_MASK 0xff00
936 #define MC_ARB_REMREQ__WR_WATER__SHIFT 0x8
937 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE_MASK 0xf0000
938 #define MC_ARB_REMREQ__WR_MAXBURST_SIZE__SHIFT 0x10
939 #define MC_ARB_REMREQ__WR_LAZY_TIMER_MASK 0xf00000
940 #define MC_ARB_REMREQ__WR_LAZY_TIMER__SHIFT 0x14
941 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ_MASK 0x1000000
942 #define MC_ARB_REMREQ__ENABLE_REMOTE_NACK_REQ__SHIFT 0x18
943 #define MC_ARB_REPLAY__ENABLE_RD_MASK 0x1
944 #define MC_ARB_REPLAY__ENABLE_RD__SHIFT 0x0
945 #define MC_ARB_REPLAY__ENABLE_WR_MASK 0x2
946 #define MC_ARB_REPLAY__ENABLE_WR__SHIFT 0x1
947 #define MC_ARB_REPLAY__WRACK_MODE_MASK 0x4
948 #define MC_ARB_REPLAY__WRACK_MODE__SHIFT 0x2
949 #define MC_ARB_REPLAY__WAW_ENABLE_MASK 0x8
950 #define MC_ARB_REPLAY__WAW_ENABLE__SHIFT 0x3
951 #define MC_ARB_REPLAY__RAW_ENABLE_MASK 0x10
952 #define MC_ARB_REPLAY__RAW_ENABLE__SHIFT 0x4
953 #define MC_ARB_REPLAY__IGNORE_WR_CDC_MASK 0x20
954 #define MC_ARB_REPLAY__IGNORE_WR_CDC__SHIFT 0x5
955 #define MC_ARB_REPLAY__BREAK_ON_STALL_MASK 0x40
956 #define MC_ARB_REPLAY__BREAK_ON_STALL__SHIFT 0x6
957 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC_MASK 0x80
958 #define MC_ARB_REPLAY__BOS_ENABLE_WAIT_CYC__SHIFT 0x7
959 #define MC_ARB_REPLAY__BOS_WAIT_CYC_MASK 0x7f00
960 #define MC_ARB_REPLAY__BOS_WAIT_CYC__SHIFT 0x8
961 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START_MASK 0x8000
962 #define MC_ARB_REPLAY__NO_PCH_AT_REPLAY_START__SHIFT 0xf
963 #define MC_ARB_RET_CREDITS_RD__LCL_MASK 0xff
964 #define MC_ARB_RET_CREDITS_RD__LCL__SHIFT 0x0
965 #define MC_ARB_RET_CREDITS_RD__HUB_MASK 0xff00
966 #define MC_ARB_RET_CREDITS_RD__HUB__SHIFT 0x8
967 #define MC_ARB_RET_CREDITS_RD__DISP_MASK 0xff0000
968 #define MC_ARB_RET_CREDITS_RD__DISP__SHIFT 0x10
969 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT_MASK 0xff000000
970 #define MC_ARB_RET_CREDITS_RD__RETURN_CREDIT__SHIFT 0x18
971 #define MC_ARB_RET_CREDITS_WR__LCL_MASK 0xff
972 #define MC_ARB_RET_CREDITS_WR__LCL__SHIFT 0x0
973 #define MC_ARB_RET_CREDITS_WR__HUB_MASK 0xff00
974 #define MC_ARB_RET_CREDITS_WR__HUB__SHIFT 0x8
975 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT_MASK 0xff0000
976 #define MC_ARB_RET_CREDITS_WR__RETURN_CREDIT__SHIFT 0x10
977 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID_MASK 0xf000000
978 #define MC_ARB_RET_CREDITS_WR__WRRET_SEQ_SKID__SHIFT 0x18
979 #define MC_ARB_RET_CREDITS_WR__WRRET_BP_MASK 0x10000000
980 #define MC_ARB_RET_CREDITS_WR__WRRET_BP__SHIFT 0x1c
981 #define MC_ARB_MAX_LAT_CID__CID_CH0_MASK 0xff
982 #define MC_ARB_MAX_LAT_CID__CID_CH0__SHIFT 0x0
983 #define MC_ARB_MAX_LAT_CID__CID_CH1_MASK 0xff00
984 #define MC_ARB_MAX_LAT_CID__CID_CH1__SHIFT 0x8
985 #define MC_ARB_MAX_LAT_CID__WRITE_CH0_MASK 0x10000
986 #define MC_ARB_MAX_LAT_CID__WRITE_CH0__SHIFT 0x10
987 #define MC_ARB_MAX_LAT_CID__WRITE_CH1_MASK 0x20000
988 #define MC_ARB_MAX_LAT_CID__WRITE_CH1__SHIFT 0x11
989 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0_MASK 0x40000
990 #define MC_ARB_MAX_LAT_CID__REALTIME_CH0__SHIFT 0x12
991 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1_MASK 0x80000
992 #define MC_ARB_MAX_LAT_CID__REALTIME_CH1__SHIFT 0x13
993 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY_MASK 0xffffffff
994 #define MC_ARB_MAX_LAT_RSLT0__MAX_LATENCY__SHIFT 0x0
995 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY_MASK 0xffffffff
996 #define MC_ARB_MAX_LAT_RSLT1__MAX_LATENCY__SHIFT 0x0
997 #define MC_ARB_GRUB_REALTIME_RD__CB0_MASK 0x1
998 #define MC_ARB_GRUB_REALTIME_RD__CB0__SHIFT 0x0
999 #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0_MASK 0x2
1000 #define MC_ARB_GRUB_REALTIME_RD__CBCMASK0__SHIFT 0x1
1001 #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0_MASK 0x4
1002 #define MC_ARB_GRUB_REALTIME_RD__CBFMASK0__SHIFT 0x2
1003 #define MC_ARB_GRUB_REALTIME_RD__DB0_MASK 0x8
1004 #define MC_ARB_GRUB_REALTIME_RD__DB0__SHIFT 0x3
1005 #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0_MASK 0x10
1006 #define MC_ARB_GRUB_REALTIME_RD__DBHTILE0__SHIFT 0x4
1007 #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0_MASK 0x20
1008 #define MC_ARB_GRUB_REALTIME_RD__DBSTEN0__SHIFT 0x5
1009 #define MC_ARB_GRUB_REALTIME_RD__TC0_MASK 0x40
1010 #define MC_ARB_GRUB_REALTIME_RD__TC0__SHIFT 0x6
1011 #define MC_ARB_GRUB_REALTIME_RD__IA_MASK 0x80
1012 #define MC_ARB_GRUB_REALTIME_RD__IA__SHIFT 0x7
1013 #define MC_ARB_GRUB_REALTIME_RD__ACPG_MASK 0x100
1014 #define MC_ARB_GRUB_REALTIME_RD__ACPG__SHIFT 0x8
1015 #define MC_ARB_GRUB_REALTIME_RD__ACPO_MASK 0x200
1016 #define MC_ARB_GRUB_REALTIME_RD__ACPO__SHIFT 0x9
1017 #define MC_ARB_GRUB_REALTIME_RD__DMIF_MASK 0x400
1018 #define MC_ARB_GRUB_REALTIME_RD__DMIF__SHIFT 0xa
1019 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0_MASK 0x800
1020 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT0__SHIFT 0xb
1021 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1_MASK 0x1000
1022 #define MC_ARB_GRUB_REALTIME_RD__DMIF_EXT1__SHIFT 0xc
1023 #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW_MASK 0x2000
1024 #define MC_ARB_GRUB_REALTIME_RD__DMIF_TW__SHIFT 0xd
1025 #define MC_ARB_GRUB_REALTIME_RD__MCIF_MASK 0x4000
1026 #define MC_ARB_GRUB_REALTIME_RD__MCIF__SHIFT 0xe
1027 #define MC_ARB_GRUB_REALTIME_RD__RLC_MASK 0x8000
1028 #define MC_ARB_GRUB_REALTIME_RD__RLC__SHIFT 0xf
1029 #define MC_ARB_GRUB_REALTIME_RD__VMC_MASK 0x10000
1030 #define MC_ARB_GRUB_REALTIME_RD__VMC__SHIFT 0x10
1031 #define MC_ARB_GRUB_REALTIME_RD__SDMA1_MASK 0x20000
1032 #define MC_ARB_GRUB_REALTIME_RD__SDMA1__SHIFT 0x11
1033 #define MC_ARB_GRUB_REALTIME_RD__SMU_MASK 0x40000
1034 #define MC_ARB_GRUB_REALTIME_RD__SMU__SHIFT 0x12
1035 #define MC_ARB_GRUB_REALTIME_RD__VCE0_MASK 0x80000
1036 #define MC_ARB_GRUB_REALTIME_RD__VCE0__SHIFT 0x13
1037 #define MC_ARB_GRUB_REALTIME_RD__VCE1_MASK 0x100000
1038 #define MC_ARB_GRUB_REALTIME_RD__VCE1__SHIFT 0x14
1039 #define MC_ARB_GRUB_REALTIME_RD__XDMAM_MASK 0x200000
1040 #define MC_ARB_GRUB_REALTIME_RD__XDMAM__SHIFT 0x15
1041 #define MC_ARB_GRUB_REALTIME_RD__SDMA0_MASK 0x400000
1042 #define MC_ARB_GRUB_REALTIME_RD__SDMA0__SHIFT 0x16
1043 #define MC_ARB_GRUB_REALTIME_RD__HDP_MASK 0x800000
1044 #define MC_ARB_GRUB_REALTIME_RD__HDP__SHIFT 0x17
1045 #define MC_ARB_GRUB_REALTIME_RD__UMC_MASK 0x1000000
1046 #define MC_ARB_GRUB_REALTIME_RD__UMC__SHIFT 0x18
1047 #define MC_ARB_GRUB_REALTIME_RD__UVD_MASK 0x2000000
1048 #define MC_ARB_GRUB_REALTIME_RD__UVD__SHIFT 0x19
1049 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0_MASK 0x4000000
1050 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT0__SHIFT 0x1a
1051 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1_MASK 0x8000000
1052 #define MC_ARB_GRUB_REALTIME_RD__UVD_EXT1__SHIFT 0x1b
1053 #define MC_ARB_GRUB_REALTIME_RD__SEM_MASK 0x10000000
1054 #define MC_ARB_GRUB_REALTIME_RD__SEM__SHIFT 0x1c
1055 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP_MASK 0x20000000
1056 #define MC_ARB_GRUB_REALTIME_RD__SAMMSP__SHIFT 0x1d
1057 #define MC_ARB_GRUB_REALTIME_RD__VP8_MASK 0x40000000
1058 #define MC_ARB_GRUB_REALTIME_RD__VP8__SHIFT 0x1e
1059 #define MC_ARB_GRUB_REALTIME_RD__ISP_MASK 0x80000000
1060 #define MC_ARB_GRUB_REALTIME_RD__ISP__SHIFT 0x1f
1061 #define MC_ARB_CG__CG_ARB_REQ_MASK 0xff
1062 #define MC_ARB_CG__CG_ARB_REQ__SHIFT 0x0
1063 #define MC_ARB_CG__CG_ARB_RESP_MASK 0xff00
1064 #define MC_ARB_CG__CG_ARB_RESP__SHIFT 0x8
1065 #define MC_ARB_CG__RSV_0_MASK 0xff0000
1066 #define MC_ARB_CG__RSV_0__SHIFT 0x10
1067 #define MC_ARB_CG__RSV_1_MASK 0xff000000
1068 #define MC_ARB_CG__RSV_1__SHIFT 0x18
1069 #define MC_ARB_GRUB_REALTIME_WR__CB0_MASK 0x1
1070 #define MC_ARB_GRUB_REALTIME_WR__CB0__SHIFT 0x0
1071 #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0_MASK 0x2
1072 #define MC_ARB_GRUB_REALTIME_WR__CBCMASK0__SHIFT 0x1
1073 #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0_MASK 0x4
1074 #define MC_ARB_GRUB_REALTIME_WR__CBFMASK0__SHIFT 0x2
1075 #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0_MASK 0x8
1076 #define MC_ARB_GRUB_REALTIME_WR__CBIMMED0__SHIFT 0x3
1077 #define MC_ARB_GRUB_REALTIME_WR__DB0_MASK 0x10
1078 #define MC_ARB_GRUB_REALTIME_WR__DB0__SHIFT 0x4
1079 #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0_MASK 0x20
1080 #define MC_ARB_GRUB_REALTIME_WR__DBHTILE0__SHIFT 0x5
1081 #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0_MASK 0x40
1082 #define MC_ARB_GRUB_REALTIME_WR__DBSTEN0__SHIFT 0x6
1083 #define MC_ARB_GRUB_REALTIME_WR__TC0_MASK 0x80
1084 #define MC_ARB_GRUB_REALTIME_WR__TC0__SHIFT 0x7
1085 #define MC_ARB_GRUB_REALTIME_WR__SH_MASK 0x100
1086 #define MC_ARB_GRUB_REALTIME_WR__SH__SHIFT 0x8
1087 #define MC_ARB_GRUB_REALTIME_WR__ACPG_MASK 0x200
1088 #define MC_ARB_GRUB_REALTIME_WR__ACPG__SHIFT 0x9
1089 #define MC_ARB_GRUB_REALTIME_WR__ACPO_MASK 0x400
1090 #define MC_ARB_GRUB_REALTIME_WR__ACPO__SHIFT 0xa
1091 #define MC_ARB_GRUB_REALTIME_WR__MCIF_MASK 0x800
1092 #define MC_ARB_GRUB_REALTIME_WR__MCIF__SHIFT 0xb
1093 #define MC_ARB_GRUB_REALTIME_WR__RLC_MASK 0x1000
1094 #define MC_ARB_GRUB_REALTIME_WR__RLC__SHIFT 0xc
1095 #define MC_ARB_GRUB_REALTIME_WR__SDMA1_MASK 0x2000
1096 #define MC_ARB_GRUB_REALTIME_WR__SDMA1__SHIFT 0xd
1097 #define MC_ARB_GRUB_REALTIME_WR__SMU_MASK 0x4000
1098 #define MC_ARB_GRUB_REALTIME_WR__SMU__SHIFT 0xe
1099 #define MC_ARB_GRUB_REALTIME_WR__VCE0_MASK 0x8000
1100 #define MC_ARB_GRUB_REALTIME_WR__VCE0__SHIFT 0xf
1101 #define MC_ARB_GRUB_REALTIME_WR__VCE1_MASK 0x10000
1102 #define MC_ARB_GRUB_REALTIME_WR__VCE1__SHIFT 0x10
1103 #define MC_ARB_GRUB_REALTIME_WR__SAMMSP_MASK 0x20000
1104 #define MC_ARB_GRUB_REALTIME_WR__SAMMSP__SHIFT 0x11
1105 #define MC_ARB_GRUB_REALTIME_WR__XDMA_MASK 0x40000
1106 #define MC_ARB_GRUB_REALTIME_WR__XDMA__SHIFT 0x12
1107 #define MC_ARB_GRUB_REALTIME_WR__XDMAM_MASK 0x80000
1108 #define MC_ARB_GRUB_REALTIME_WR__XDMAM__SHIFT 0x13
1109 #define MC_ARB_GRUB_REALTIME_WR__SDMA0_MASK 0x100000
1110 #define MC_ARB_GRUB_REALTIME_WR__SDMA0__SHIFT 0x14
1111 #define MC_ARB_GRUB_REALTIME_WR__HDP_MASK 0x200000
1112 #define MC_ARB_GRUB_REALTIME_WR__HDP__SHIFT 0x15
1113 #define MC_ARB_GRUB_REALTIME_WR__UMC_MASK 0x400000
1114 #define MC_ARB_GRUB_REALTIME_WR__UMC__SHIFT 0x16
1115 #define MC_ARB_GRUB_REALTIME_WR__UVD_MASK 0x800000
1116 #define MC_ARB_GRUB_REALTIME_WR__UVD__SHIFT 0x17
1117 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0_MASK 0x1000000
1118 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT0__SHIFT 0x18
1119 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1_MASK 0x2000000
1120 #define MC_ARB_GRUB_REALTIME_WR__UVD_EXT1__SHIFT 0x19
1121 #define MC_ARB_GRUB_REALTIME_WR__XDP_MASK 0x4000000
1122 #define MC_ARB_GRUB_REALTIME_WR__XDP__SHIFT 0x1a
1123 #define MC_ARB_GRUB_REALTIME_WR__SEM_MASK 0x8000000
1124 #define MC_ARB_GRUB_REALTIME_WR__SEM__SHIFT 0x1b
1125 #define MC_ARB_GRUB_REALTIME_WR__IH_MASK 0x10000000
1126 #define MC_ARB_GRUB_REALTIME_WR__IH__SHIFT 0x1c
1127 #define MC_ARB_GRUB_REALTIME_WR__VP8_MASK 0x20000000
1128 #define MC_ARB_GRUB_REALTIME_WR__VP8__SHIFT 0x1d
1129 #define MC_ARB_GRUB_REALTIME_WR__ISP_MASK 0x40000000
1130 #define MC_ARB_GRUB_REALTIME_WR__ISP__SHIFT 0x1e
1131 #define MC_ARB_GRUB_REALTIME_WR__VIN0_MASK 0x80000000
1132 #define MC_ARB_GRUB_REALTIME_WR__VIN0__SHIFT 0x1f
1133 #define MC_ARB_DRAM_TIMING_1__ACTRD_MASK 0xff
1134 #define MC_ARB_DRAM_TIMING_1__ACTRD__SHIFT 0x0
1135 #define MC_ARB_DRAM_TIMING_1__ACTWR_MASK 0xff00
1136 #define MC_ARB_DRAM_TIMING_1__ACTWR__SHIFT 0x8
1137 #define MC_ARB_DRAM_TIMING_1__RASMACTRD_MASK 0xff0000
1138 #define MC_ARB_DRAM_TIMING_1__RASMACTRD__SHIFT 0x10
1139 #define MC_ARB_DRAM_TIMING_1__RASMACTWR_MASK 0xff000000
1140 #define MC_ARB_DRAM_TIMING_1__RASMACTWR__SHIFT 0x18
1141 #define MC_ARB_BUSY_STATUS__LM_RD0_MASK 0x1
1142 #define MC_ARB_BUSY_STATUS__LM_RD0__SHIFT 0x0
1143 #define MC_ARB_BUSY_STATUS__LM_RD1_MASK 0x2
1144 #define MC_ARB_BUSY_STATUS__LM_RD1__SHIFT 0x1
1145 #define MC_ARB_BUSY_STATUS__LM_WR0_MASK 0x4
1146 #define MC_ARB_BUSY_STATUS__LM_WR0__SHIFT 0x2
1147 #define MC_ARB_BUSY_STATUS__LM_WR1_MASK 0x8
1148 #define MC_ARB_BUSY_STATUS__LM_WR1__SHIFT 0x3
1149 #define MC_ARB_BUSY_STATUS__HM_RD0_MASK 0x10
1150 #define MC_ARB_BUSY_STATUS__HM_RD0__SHIFT 0x4
1151 #define MC_ARB_BUSY_STATUS__HM_RD1_MASK 0x20
1152 #define MC_ARB_BUSY_STATUS__HM_RD1__SHIFT 0x5
1153 #define MC_ARB_BUSY_STATUS__HM_WR0_MASK 0x40
1154 #define MC_ARB_BUSY_STATUS__HM_WR0__SHIFT 0x6
1155 #define MC_ARB_BUSY_STATUS__HM_WR1_MASK 0x80
1156 #define MC_ARB_BUSY_STATUS__HM_WR1__SHIFT 0x7
1157 #define MC_ARB_BUSY_STATUS__WDE_RD0_MASK 0x100
1158 #define MC_ARB_BUSY_STATUS__WDE_RD0__SHIFT 0x8
1159 #define MC_ARB_BUSY_STATUS__WDE_RD1_MASK 0x200
1160 #define MC_ARB_BUSY_STATUS__WDE_RD1__SHIFT 0x9
1161 #define MC_ARB_BUSY_STATUS__WDE_WR0_MASK 0x400
1162 #define MC_ARB_BUSY_STATUS__WDE_WR0__SHIFT 0xa
1163 #define MC_ARB_BUSY_STATUS__WDE_WR1_MASK 0x800
1164 #define MC_ARB_BUSY_STATUS__WDE_WR1__SHIFT 0xb
1165 #define MC_ARB_BUSY_STATUS__POP0_MASK 0x1000
1166 #define MC_ARB_BUSY_STATUS__POP0__SHIFT 0xc
1167 #define MC_ARB_BUSY_STATUS__POP1_MASK 0x2000
1168 #define MC_ARB_BUSY_STATUS__POP1__SHIFT 0xd
1169 #define MC_ARB_BUSY_STATUS__TAGFIFO0_MASK 0x4000
1170 #define MC_ARB_BUSY_STATUS__TAGFIFO0__SHIFT 0xe
1171 #define MC_ARB_BUSY_STATUS__TAGFIFO1_MASK 0x8000
1172 #define MC_ARB_BUSY_STATUS__TAGFIFO1__SHIFT 0xf
1173 #define MC_ARB_BUSY_STATUS__REPLAY0_MASK 0x10000
1174 #define MC_ARB_BUSY_STATUS__REPLAY0__SHIFT 0x10
1175 #define MC_ARB_BUSY_STATUS__REPLAY1_MASK 0x20000
1176 #define MC_ARB_BUSY_STATUS__REPLAY1__SHIFT 0x11
1177 #define MC_ARB_BUSY_STATUS__RDRET0_MASK 0x40000
1178 #define MC_ARB_BUSY_STATUS__RDRET0__SHIFT 0x12
1179 #define MC_ARB_BUSY_STATUS__RDRET1_MASK 0x80000
1180 #define MC_ARB_BUSY_STATUS__RDRET1__SHIFT 0x13
1181 #define MC_ARB_BUSY_STATUS__GECC2_RD0_MASK 0x100000
1182 #define MC_ARB_BUSY_STATUS__GECC2_RD0__SHIFT 0x14
1183 #define MC_ARB_BUSY_STATUS__GECC2_RD1_MASK 0x200000
1184 #define MC_ARB_BUSY_STATUS__GECC2_RD1__SHIFT 0x15
1185 #define MC_ARB_BUSY_STATUS__GECC2_WR0_MASK 0x400000
1186 #define MC_ARB_BUSY_STATUS__GECC2_WR0__SHIFT 0x16
1187 #define MC_ARB_BUSY_STATUS__GECC2_WR1_MASK 0x800000
1188 #define MC_ARB_BUSY_STATUS__GECC2_WR1__SHIFT 0x17
1189 #define MC_ARB_BUSY_STATUS__WRRET0_MASK 0x1000000
1190 #define MC_ARB_BUSY_STATUS__WRRET0__SHIFT 0x18
1191 #define MC_ARB_BUSY_STATUS__WRRET1_MASK 0x2000000
1192 #define MC_ARB_BUSY_STATUS__WRRET1__SHIFT 0x19
1193 #define MC_ARB_BUSY_STATUS__RTT0_MASK 0x4000000
1194 #define MC_ARB_BUSY_STATUS__RTT0__SHIFT 0x1a
1195 #define MC_ARB_BUSY_STATUS__RTT1_MASK 0x8000000
1196 #define MC_ARB_BUSY_STATUS__RTT1__SHIFT 0x1b
1197 #define MC_ARB_BUSY_STATUS__REM_RD0_MASK 0x10000000
1198 #define MC_ARB_BUSY_STATUS__REM_RD0__SHIFT 0x1c
1199 #define MC_ARB_BUSY_STATUS__REM_RD1_MASK 0x20000000
1200 #define MC_ARB_BUSY_STATUS__REM_RD1__SHIFT 0x1d
1201 #define MC_ARB_BUSY_STATUS__REM_WR0_MASK 0x40000000
1202 #define MC_ARB_BUSY_STATUS__REM_WR0__SHIFT 0x1e
1203 #define MC_ARB_BUSY_STATUS__REM_WR1_MASK 0x80000000
1204 #define MC_ARB_BUSY_STATUS__REM_WR1__SHIFT 0x1f
1205 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS_MASK 0xff
1206 #define MC_ARB_DRAM_TIMING2_1__RAS2RAS__SHIFT 0x0
1207 #define MC_ARB_DRAM_TIMING2_1__RP_MASK 0xff00
1208 #define MC_ARB_DRAM_TIMING2_1__RP__SHIFT 0x8
1209 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP_MASK 0xff0000
1210 #define MC_ARB_DRAM_TIMING2_1__WRPLUSRP__SHIFT 0x10
1211 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN_MASK 0x1f000000
1212 #define MC_ARB_DRAM_TIMING2_1__BUS_TURN__SHIFT 0x18
1213 #define MC_ARB_GRUB2__REALTIME_GRP_RD_MASK 0xff
1214 #define MC_ARB_GRUB2__REALTIME_GRP_RD__SHIFT 0x0
1215 #define MC_ARB_GRUB2__REALTIME_GRP_WR_MASK 0xff00
1216 #define MC_ARB_GRUB2__REALTIME_GRP_WR__SHIFT 0x8
1217 #define MC_ARB_GRUB2__DISP_RD_STALL_EN_MASK 0x10000
1218 #define MC_ARB_GRUB2__DISP_RD_STALL_EN__SHIFT 0x10
1219 #define MC_ARB_GRUB2__ACP_RD_STALL_EN_MASK 0x20000
1220 #define MC_ARB_GRUB2__ACP_RD_STALL_EN__SHIFT 0x11
1221 #define MC_ARB_GRUB2__UVD_RD_STALL_EN_MASK 0x40000
1222 #define MC_ARB_GRUB2__UVD_RD_STALL_EN__SHIFT 0x12
1223 #define MC_ARB_GRUB2__VCE0_RD_STALL_EN_MASK 0x80000
1224 #define MC_ARB_GRUB2__VCE0_RD_STALL_EN__SHIFT 0x13
1225 #define MC_ARB_GRUB2__VCE1_RD_STALL_EN_MASK 0x100000
1226 #define MC_ARB_GRUB2__VCE1_RD_STALL_EN__SHIFT 0x14
1227 #define MC_ARB_GRUB2__REALTIME_RD_WTS_MASK 0x200000
1228 #define MC_ARB_GRUB2__REALTIME_RD_WTS__SHIFT 0x15
1229 #define MC_ARB_GRUB2__REALTIME_WR_WTS_MASK 0x400000
1230 #define MC_ARB_GRUB2__REALTIME_WR_WTS__SHIFT 0x16
1231 #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL_MASK 0x800000
1232 #define MC_ARB_GRUB2__URGENT_BY_DISP_STALL__SHIFT 0x17
1233 #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG_MASK 0x1000000
1234 #define MC_ARB_GRUB2__PROMOTE_BY_DMIF_URG__SHIFT 0x18
1235 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD_MASK 0x2000000
1236 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_RD__SHIFT 0x19
1237 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD_MASK 0x4000000
1238 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_RD__SHIFT 0x1a
1239 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR_MASK 0x8000000
1240 #define MC_ARB_GRUB2__PRIORITY_URGENT_OUTSTANDING_ONLY_WR__SHIFT 0x1b
1241 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR_MASK 0x10000000
1242 #define MC_ARB_GRUB2__PRIORITY_PROMOTE_OUTSTANDING_ONLY_WR__SHIFT 0x1c
1243 #define MC_ARB_BURST_TIME__STATE0_MASK 0x1f
1244 #define MC_ARB_BURST_TIME__STATE0__SHIFT 0x0
1245 #define MC_ARB_BURST_TIME__STATE1_MASK 0x3e0
1246 #define MC_ARB_BURST_TIME__STATE1__SHIFT 0x5
1247 #define MC_ARB_BURST_TIME__TRRDS0_MASK 0x7c00
1248 #define MC_ARB_BURST_TIME__TRRDS0__SHIFT 0xa
1249 #define MC_ARB_BURST_TIME__TRRDS1_MASK 0xf8000
1250 #define MC_ARB_BURST_TIME__TRRDS1__SHIFT 0xf
1251 #define MC_ARB_BURST_TIME__TRRDL0_MASK 0x1f00000
1252 #define MC_ARB_BURST_TIME__TRRDL0__SHIFT 0x14
1253 #define MC_ARB_BURST_TIME__TRRDL1_MASK 0x3e000000
1254 #define MC_ARB_BURST_TIME__TRRDL1__SHIFT 0x19
1255 #define MC_CITF_XTRA_ENABLE__CB1_RD_MASK 0x1
1256 #define MC_CITF_XTRA_ENABLE__CB1_RD__SHIFT 0x0
1257 #define MC_CITF_XTRA_ENABLE__CB1_WR_MASK 0x2
1258 #define MC_CITF_XTRA_ENABLE__CB1_WR__SHIFT 0x1
1259 #define MC_CITF_XTRA_ENABLE__DB1_RD_MASK 0x4
1260 #define MC_CITF_XTRA_ENABLE__DB1_RD__SHIFT 0x2
1261 #define MC_CITF_XTRA_ENABLE__DB1_WR_MASK 0x8
1262 #define MC_CITF_XTRA_ENABLE__DB1_WR__SHIFT 0x3
1263 #define MC_CITF_XTRA_ENABLE__TC2_RD_MASK 0x10
1264 #define MC_CITF_XTRA_ENABLE__TC2_RD__SHIFT 0x4
1265 #define MC_CITF_XTRA_ENABLE__ARB_DBG_MASK 0xf00
1266 #define MC_CITF_XTRA_ENABLE__ARB_DBG__SHIFT 0x8
1267 #define MC_CITF_XTRA_ENABLE__TC2_WR_MASK 0x1000
1268 #define MC_CITF_XTRA_ENABLE__TC2_WR__SHIFT 0xc
1269 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL_MASK 0x6000
1270 #define MC_CITF_XTRA_ENABLE__CB0_CONNECT_CNTL__SHIFT 0xd
1271 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL_MASK 0x18000
1272 #define MC_CITF_XTRA_ENABLE__DB0_CONNECT_CNTL__SHIFT 0xf
1273 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL_MASK 0x60000
1274 #define MC_CITF_XTRA_ENABLE__CB1_CONNECT_CNTL__SHIFT 0x11
1275 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL_MASK 0x180000
1276 #define MC_CITF_XTRA_ENABLE__DB1_CONNECT_CNTL__SHIFT 0x13
1277 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL_MASK 0x600000
1278 #define MC_CITF_XTRA_ENABLE__TC0_CONNECT_CNTL__SHIFT 0x15
1279 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL_MASK 0x1800000
1280 #define MC_CITF_XTRA_ENABLE__TC1_CONNECT_CNTL__SHIFT 0x17
1281 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE_MASK 0x2000000
1282 #define MC_CITF_XTRA_ENABLE__CB0_CID_CNTL_ENABLE__SHIFT 0x19
1283 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE_MASK 0x4000000
1284 #define MC_CITF_XTRA_ENABLE__DB0_CID_CNTL_ENABLE__SHIFT 0x1a
1285 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE_MASK 0x8000000
1286 #define MC_CITF_XTRA_ENABLE__CB1_CID_CNTL_ENABLE__SHIFT 0x1b
1287 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE_MASK 0x10000000
1288 #define MC_CITF_XTRA_ENABLE__DB1_CID_CNTL_ENABLE__SHIFT 0x1c
1289 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE_MASK 0x60000000
1290 #define MC_CITF_XTRA_ENABLE__TC2_REPAIR_ENABLE__SHIFT 0x1d
1291 #define CC_MC_MAX_CHANNEL__NOOFCHAN_MASK 0x1e
1292 #define CC_MC_MAX_CHANNEL__NOOFCHAN__SHIFT 0x1
1293 #define MC_CG_CONFIG__MCDW_WR_ENABLE_MASK 0x1
1294 #define MC_CG_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
1295 #define MC_CG_CONFIG__MCDX_WR_ENABLE_MASK 0x2
1296 #define MC_CG_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
1297 #define MC_CG_CONFIG__MCDY_WR_ENABLE_MASK 0x4
1298 #define MC_CG_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
1299 #define MC_CG_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
1300 #define MC_CG_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
1301 #define MC_CG_CONFIG__MC_RD_ENABLE_MASK 0x30
1302 #define MC_CG_CONFIG__MC_RD_ENABLE__SHIFT 0x4
1303 #define MC_CG_CONFIG__INDEX_MASK 0x3fffc0
1304 #define MC_CG_CONFIG__INDEX__SHIFT 0x6
1305 #define MC_CITF_CNTL__IGNOREPM_MASK 0x4
1306 #define MC_CITF_CNTL__IGNOREPM__SHIFT 0x2
1307 #define MC_CITF_CNTL__EXEMPTPM_MASK 0x8
1308 #define MC_CITF_CNTL__EXEMPTPM__SHIFT 0x3
1309 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE_MASK 0x30
1310 #define MC_CITF_CNTL__GFX_IDLE_OVERRIDE__SHIFT 0x4
1311 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE_MASK 0x40
1312 #define MC_CITF_CNTL__MCD_SRBM_MASK_ENABLE__SHIFT 0x6
1313 #define MC_CITF_CNTL__CNTR_CHMAP_MODE_MASK 0x180
1314 #define MC_CITF_CNTL__CNTR_CHMAP_MODE__SHIFT 0x7
1315 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE_MASK 0x200
1316 #define MC_CITF_CNTL__REMOTE_RB_CONNECT_ENABLE__SHIFT 0x9
1317 #define MC_CITF_CREDITS_VM__READ_ALL_MASK 0x3f
1318 #define MC_CITF_CREDITS_VM__READ_ALL__SHIFT 0x0
1319 #define MC_CITF_CREDITS_VM__WRITE_ALL_MASK 0xfc0
1320 #define MC_CITF_CREDITS_VM__WRITE_ALL__SHIFT 0x6
1321 #define MC_CITF_CREDITS_ARB_RD__READ_LCL_MASK 0xff
1322 #define MC_CITF_CREDITS_ARB_RD__READ_LCL__SHIFT 0x0
1323 #define MC_CITF_CREDITS_ARB_RD__READ_HUB_MASK 0xff00
1324 #define MC_CITF_CREDITS_ARB_RD__READ_HUB__SHIFT 0x8
1325 #define MC_CITF_CREDITS_ARB_RD__READ_PRI_MASK 0xff0000
1326 #define MC_CITF_CREDITS_ARB_RD__READ_PRI__SHIFT 0x10
1327 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI_MASK 0x1000000
1328 #define MC_CITF_CREDITS_ARB_RD__LCL_PRI__SHIFT 0x18
1329 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI_MASK 0x2000000
1330 #define MC_CITF_CREDITS_ARB_RD__HUB_PRI__SHIFT 0x19
1331 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL_MASK 0xff
1332 #define MC_CITF_CREDITS_ARB_WR__WRITE_LCL__SHIFT 0x0
1333 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB_MASK 0xff00
1334 #define MC_CITF_CREDITS_ARB_WR__WRITE_HUB__SHIFT 0x8
1335 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI_MASK 0xff0000
1336 #define MC_CITF_CREDITS_ARB_WR__WRITE_PRI__SHIFT 0x10
1337 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI_MASK 0x1000000
1338 #define MC_CITF_CREDITS_ARB_WR__HUB_PRI__SHIFT 0x18
1339 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI_MASK 0x2000000
1340 #define MC_CITF_CREDITS_ARB_WR__LCL_PRI__SHIFT 0x19
1341 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD_MASK 0x1
1342 #define MC_CITF_DAGB_CNTL__JUMP_AHEAD__SHIFT 0x0
1343 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST_MASK 0x1e
1344 #define MC_CITF_DAGB_CNTL__CENTER_RD_MAX_BURST__SHIFT 0x1
1345 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT_MASK 0x20
1346 #define MC_CITF_DAGB_CNTL__DISABLE_SELF_INIT__SHIFT 0x5
1347 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST_MASK 0x3c0
1348 #define MC_CITF_DAGB_CNTL__CENTER_WR_MAX_BURST__SHIFT 0x6
1349 #define MC_CITF_INT_CREDITS__REMRDRET_MASK 0x3f
1350 #define MC_CITF_INT_CREDITS__REMRDRET__SHIFT 0x0
1351 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP_MASK 0x3f000
1352 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_LP__SHIFT 0xc
1353 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP_MASK 0xfc0000
1354 #define MC_CITF_INT_CREDITS__CNTR_RD_HUB_HP__SHIFT 0x12
1355 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL_MASK 0x3f000000
1356 #define MC_CITF_INT_CREDITS__CNTR_RD_LCL__SHIFT 0x18
1357 #define MC_CITF_RET_MODE__INORDER_RD_MASK 0x1
1358 #define MC_CITF_RET_MODE__INORDER_RD__SHIFT 0x0
1359 #define MC_CITF_RET_MODE__INORDER_WR_MASK 0x2
1360 #define MC_CITF_RET_MODE__INORDER_WR__SHIFT 0x1
1361 #define MC_CITF_RET_MODE__REMPRI_RD_MASK 0x4
1362 #define MC_CITF_RET_MODE__REMPRI_RD__SHIFT 0x2
1363 #define MC_CITF_RET_MODE__REMPRI_WR_MASK 0x8
1364 #define MC_CITF_RET_MODE__REMPRI_WR__SHIFT 0x3
1365 #define MC_CITF_RET_MODE__LCLPRI_RD_MASK 0x10
1366 #define MC_CITF_RET_MODE__LCLPRI_RD__SHIFT 0x4
1367 #define MC_CITF_RET_MODE__LCLPRI_WR_MASK 0x20
1368 #define MC_CITF_RET_MODE__LCLPRI_WR__SHIFT 0x5
1369 #define MC_CITF_RET_MODE__RDRET_STALL_EN_MASK 0x40
1370 #define MC_CITF_RET_MODE__RDRET_STALL_EN__SHIFT 0x6
1371 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD_MASK 0x7f80
1372 #define MC_CITF_RET_MODE__RDRET_STALL_THRESHOLD__SHIFT 0x7
1373 #define MC_CITF_DAGB_DLY__DLY_MASK 0x1f
1374 #define MC_CITF_DAGB_DLY__DLY__SHIFT 0x0
1375 #define MC_CITF_DAGB_DLY__CLI_MASK 0x3f0000
1376 #define MC_CITF_DAGB_DLY__CLI__SHIFT 0x10
1377 #define MC_CITF_DAGB_DLY__POS_MASK 0x3f000000
1378 #define MC_CITF_DAGB_DLY__POS__SHIFT 0x18
1379 #define MC_RD_GRP_EXT__DBSTEN0_MASK 0xf
1380 #define MC_RD_GRP_EXT__DBSTEN0__SHIFT 0x0
1381 #define MC_RD_GRP_EXT__TC0_MASK 0xf0
1382 #define MC_RD_GRP_EXT__TC0__SHIFT 0x4
1383 #define MC_WR_GRP_EXT__DBSTEN0_MASK 0xf
1384 #define MC_WR_GRP_EXT__DBSTEN0__SHIFT 0x0
1385 #define MC_WR_GRP_EXT__TC0_MASK 0xf0
1386 #define MC_WR_GRP_EXT__TC0__SHIFT 0x4
1387 #define MC_CITF_REMREQ__READ_CREDITS_MASK 0x7f
1388 #define MC_CITF_REMREQ__READ_CREDITS__SHIFT 0x0
1389 #define MC_CITF_REMREQ__WRITE_CREDITS_MASK 0x3f80
1390 #define MC_CITF_REMREQ__WRITE_CREDITS__SHIFT 0x7
1391 #define MC_CITF_REMREQ__CREDITS_ENABLE_MASK 0x4000
1392 #define MC_CITF_REMREQ__CREDITS_ENABLE__SHIFT 0xe
1393 #define MC_WR_TC0__ENABLE_MASK 0x1
1394 #define MC_WR_TC0__ENABLE__SHIFT 0x0
1395 #define MC_WR_TC0__PRESCALE_MASK 0x6
1396 #define MC_WR_TC0__PRESCALE__SHIFT 0x1
1397 #define MC_WR_TC0__BLACKOUT_EXEMPT_MASK 0x8
1398 #define MC_WR_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1399 #define MC_WR_TC0__STALL_MODE_MASK 0x30
1400 #define MC_WR_TC0__STALL_MODE__SHIFT 0x4
1401 #define MC_WR_TC0__STALL_OVERRIDE_MASK 0x40
1402 #define MC_WR_TC0__STALL_OVERRIDE__SHIFT 0x6
1403 #define MC_WR_TC0__MAX_BURST_MASK 0x780
1404 #define MC_WR_TC0__MAX_BURST__SHIFT 0x7
1405 #define MC_WR_TC0__LAZY_TIMER_MASK 0x7800
1406 #define MC_WR_TC0__LAZY_TIMER__SHIFT 0xb
1407 #define MC_WR_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1408 #define MC_WR_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1409 #define MC_WR_TC1__ENABLE_MASK 0x1
1410 #define MC_WR_TC1__ENABLE__SHIFT 0x0
1411 #define MC_WR_TC1__PRESCALE_MASK 0x6
1412 #define MC_WR_TC1__PRESCALE__SHIFT 0x1
1413 #define MC_WR_TC1__BLACKOUT_EXEMPT_MASK 0x8
1414 #define MC_WR_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1415 #define MC_WR_TC1__STALL_MODE_MASK 0x30
1416 #define MC_WR_TC1__STALL_MODE__SHIFT 0x4
1417 #define MC_WR_TC1__STALL_OVERRIDE_MASK 0x40
1418 #define MC_WR_TC1__STALL_OVERRIDE__SHIFT 0x6
1419 #define MC_WR_TC1__MAX_BURST_MASK 0x780
1420 #define MC_WR_TC1__MAX_BURST__SHIFT 0x7
1421 #define MC_WR_TC1__LAZY_TIMER_MASK 0x7800
1422 #define MC_WR_TC1__LAZY_TIMER__SHIFT 0xb
1423 #define MC_WR_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1424 #define MC_WR_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1425 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB_MASK 0x3f
1426 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_HUB__SHIFT 0x0
1427 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL_MASK 0xfc0
1428 #define MC_CITF_INT_CREDITS_WR__CNTR_WR_LCL__SHIFT 0x6
1429 #define MC_CITF_CREDITS_ARB_RD2__READ_MED_MASK 0xff
1430 #define MC_CITF_CREDITS_ARB_RD2__READ_MED__SHIFT 0x0
1431 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT_MASK 0x7
1432 #define MC_CITF_WTM_RD_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1433 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT_MASK 0x38
1434 #define MC_CITF_WTM_RD_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1435 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1436 #define MC_CITF_WTM_RD_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1437 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT_MASK 0xe00
1438 #define MC_CITF_WTM_RD_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1439 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT_MASK 0x7000
1440 #define MC_CITF_WTM_RD_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1441 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT_MASK 0x38000
1442 #define MC_CITF_WTM_RD_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1443 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1444 #define MC_CITF_WTM_RD_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1445 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1446 #define MC_CITF_WTM_RD_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1447 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE_MASK 0x1000000
1448 #define MC_CITF_WTM_RD_CNTL__DISABLE_REMOTE__SHIFT 0x18
1449 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL_MASK 0x2000000
1450 #define MC_CITF_WTM_RD_CNTL__DISABLE_LOCAL__SHIFT 0x19
1451 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT_MASK 0x7
1452 #define MC_CITF_WTM_WR_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1453 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT_MASK 0x38
1454 #define MC_CITF_WTM_WR_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1455 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1456 #define MC_CITF_WTM_WR_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1457 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT_MASK 0xe00
1458 #define MC_CITF_WTM_WR_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1459 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT_MASK 0x7000
1460 #define MC_CITF_WTM_WR_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1461 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT_MASK 0x38000
1462 #define MC_CITF_WTM_WR_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1463 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1464 #define MC_CITF_WTM_WR_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1465 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1466 #define MC_CITF_WTM_WR_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1467 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE_MASK 0x1000000
1468 #define MC_CITF_WTM_WR_CNTL__DISABLE_REMOTE__SHIFT 0x18
1469 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL_MASK 0x2000000
1470 #define MC_CITF_WTM_WR_CNTL__DISABLE_LOCAL__SHIFT 0x19
1471 #define MC_RD_CB__ENABLE_MASK 0x1
1472 #define MC_RD_CB__ENABLE__SHIFT 0x0
1473 #define MC_RD_CB__PRESCALE_MASK 0x6
1474 #define MC_RD_CB__PRESCALE__SHIFT 0x1
1475 #define MC_RD_CB__BLACKOUT_EXEMPT_MASK 0x8
1476 #define MC_RD_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1477 #define MC_RD_CB__STALL_MODE_MASK 0x30
1478 #define MC_RD_CB__STALL_MODE__SHIFT 0x4
1479 #define MC_RD_CB__STALL_OVERRIDE_MASK 0x40
1480 #define MC_RD_CB__STALL_OVERRIDE__SHIFT 0x6
1481 #define MC_RD_CB__MAX_BURST_MASK 0x780
1482 #define MC_RD_CB__MAX_BURST__SHIFT 0x7
1483 #define MC_RD_CB__LAZY_TIMER_MASK 0x7800
1484 #define MC_RD_CB__LAZY_TIMER__SHIFT 0xb
1485 #define MC_RD_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1486 #define MC_RD_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1487 #define MC_RD_DB__ENABLE_MASK 0x1
1488 #define MC_RD_DB__ENABLE__SHIFT 0x0
1489 #define MC_RD_DB__PRESCALE_MASK 0x6
1490 #define MC_RD_DB__PRESCALE__SHIFT 0x1
1491 #define MC_RD_DB__BLACKOUT_EXEMPT_MASK 0x8
1492 #define MC_RD_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1493 #define MC_RD_DB__STALL_MODE_MASK 0x30
1494 #define MC_RD_DB__STALL_MODE__SHIFT 0x4
1495 #define MC_RD_DB__STALL_OVERRIDE_MASK 0x40
1496 #define MC_RD_DB__STALL_OVERRIDE__SHIFT 0x6
1497 #define MC_RD_DB__MAX_BURST_MASK 0x780
1498 #define MC_RD_DB__MAX_BURST__SHIFT 0x7
1499 #define MC_RD_DB__LAZY_TIMER_MASK 0x7800
1500 #define MC_RD_DB__LAZY_TIMER__SHIFT 0xb
1501 #define MC_RD_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1502 #define MC_RD_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1503 #define MC_RD_TC0__ENABLE_MASK 0x1
1504 #define MC_RD_TC0__ENABLE__SHIFT 0x0
1505 #define MC_RD_TC0__PRESCALE_MASK 0x6
1506 #define MC_RD_TC0__PRESCALE__SHIFT 0x1
1507 #define MC_RD_TC0__BLACKOUT_EXEMPT_MASK 0x8
1508 #define MC_RD_TC0__BLACKOUT_EXEMPT__SHIFT 0x3
1509 #define MC_RD_TC0__STALL_MODE_MASK 0x30
1510 #define MC_RD_TC0__STALL_MODE__SHIFT 0x4
1511 #define MC_RD_TC0__STALL_OVERRIDE_MASK 0x40
1512 #define MC_RD_TC0__STALL_OVERRIDE__SHIFT 0x6
1513 #define MC_RD_TC0__MAX_BURST_MASK 0x780
1514 #define MC_RD_TC0__MAX_BURST__SHIFT 0x7
1515 #define MC_RD_TC0__LAZY_TIMER_MASK 0x7800
1516 #define MC_RD_TC0__LAZY_TIMER__SHIFT 0xb
1517 #define MC_RD_TC0__STALL_OVERRIDE_WTM_MASK 0x8000
1518 #define MC_RD_TC0__STALL_OVERRIDE_WTM__SHIFT 0xf
1519 #define MC_RD_TC1__ENABLE_MASK 0x1
1520 #define MC_RD_TC1__ENABLE__SHIFT 0x0
1521 #define MC_RD_TC1__PRESCALE_MASK 0x6
1522 #define MC_RD_TC1__PRESCALE__SHIFT 0x1
1523 #define MC_RD_TC1__BLACKOUT_EXEMPT_MASK 0x8
1524 #define MC_RD_TC1__BLACKOUT_EXEMPT__SHIFT 0x3
1525 #define MC_RD_TC1__STALL_MODE_MASK 0x30
1526 #define MC_RD_TC1__STALL_MODE__SHIFT 0x4
1527 #define MC_RD_TC1__STALL_OVERRIDE_MASK 0x40
1528 #define MC_RD_TC1__STALL_OVERRIDE__SHIFT 0x6
1529 #define MC_RD_TC1__MAX_BURST_MASK 0x780
1530 #define MC_RD_TC1__MAX_BURST__SHIFT 0x7
1531 #define MC_RD_TC1__LAZY_TIMER_MASK 0x7800
1532 #define MC_RD_TC1__LAZY_TIMER__SHIFT 0xb
1533 #define MC_RD_TC1__STALL_OVERRIDE_WTM_MASK 0x8000
1534 #define MC_RD_TC1__STALL_OVERRIDE_WTM__SHIFT 0xf
1535 #define MC_RD_HUB__ENABLE_MASK 0x1
1536 #define MC_RD_HUB__ENABLE__SHIFT 0x0
1537 #define MC_RD_HUB__PRESCALE_MASK 0x6
1538 #define MC_RD_HUB__PRESCALE__SHIFT 0x1
1539 #define MC_RD_HUB__BLACKOUT_EXEMPT_MASK 0x8
1540 #define MC_RD_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1541 #define MC_RD_HUB__STALL_MODE_MASK 0x30
1542 #define MC_RD_HUB__STALL_MODE__SHIFT 0x4
1543 #define MC_RD_HUB__STALL_OVERRIDE_MASK 0x40
1544 #define MC_RD_HUB__STALL_OVERRIDE__SHIFT 0x6
1545 #define MC_RD_HUB__MAX_BURST_MASK 0x780
1546 #define MC_RD_HUB__MAX_BURST__SHIFT 0x7
1547 #define MC_RD_HUB__LAZY_TIMER_MASK 0x7800
1548 #define MC_RD_HUB__LAZY_TIMER__SHIFT 0xb
1549 #define MC_RD_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1550 #define MC_RD_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1551 #define MC_WR_CB__ENABLE_MASK 0x1
1552 #define MC_WR_CB__ENABLE__SHIFT 0x0
1553 #define MC_WR_CB__PRESCALE_MASK 0x6
1554 #define MC_WR_CB__PRESCALE__SHIFT 0x1
1555 #define MC_WR_CB__BLACKOUT_EXEMPT_MASK 0x8
1556 #define MC_WR_CB__BLACKOUT_EXEMPT__SHIFT 0x3
1557 #define MC_WR_CB__STALL_MODE_MASK 0x30
1558 #define MC_WR_CB__STALL_MODE__SHIFT 0x4
1559 #define MC_WR_CB__STALL_OVERRIDE_MASK 0x40
1560 #define MC_WR_CB__STALL_OVERRIDE__SHIFT 0x6
1561 #define MC_WR_CB__MAX_BURST_MASK 0x780
1562 #define MC_WR_CB__MAX_BURST__SHIFT 0x7
1563 #define MC_WR_CB__LAZY_TIMER_MASK 0x7800
1564 #define MC_WR_CB__LAZY_TIMER__SHIFT 0xb
1565 #define MC_WR_CB__STALL_OVERRIDE_WTM_MASK 0x8000
1566 #define MC_WR_CB__STALL_OVERRIDE_WTM__SHIFT 0xf
1567 #define MC_WR_DB__ENABLE_MASK 0x1
1568 #define MC_WR_DB__ENABLE__SHIFT 0x0
1569 #define MC_WR_DB__PRESCALE_MASK 0x6
1570 #define MC_WR_DB__PRESCALE__SHIFT 0x1
1571 #define MC_WR_DB__BLACKOUT_EXEMPT_MASK 0x8
1572 #define MC_WR_DB__BLACKOUT_EXEMPT__SHIFT 0x3
1573 #define MC_WR_DB__STALL_MODE_MASK 0x30
1574 #define MC_WR_DB__STALL_MODE__SHIFT 0x4
1575 #define MC_WR_DB__STALL_OVERRIDE_MASK 0x40
1576 #define MC_WR_DB__STALL_OVERRIDE__SHIFT 0x6
1577 #define MC_WR_DB__MAX_BURST_MASK 0x780
1578 #define MC_WR_DB__MAX_BURST__SHIFT 0x7
1579 #define MC_WR_DB__LAZY_TIMER_MASK 0x7800
1580 #define MC_WR_DB__LAZY_TIMER__SHIFT 0xb
1581 #define MC_WR_DB__STALL_OVERRIDE_WTM_MASK 0x8000
1582 #define MC_WR_DB__STALL_OVERRIDE_WTM__SHIFT 0xf
1583 #define MC_WR_HUB__ENABLE_MASK 0x1
1584 #define MC_WR_HUB__ENABLE__SHIFT 0x0
1585 #define MC_WR_HUB__PRESCALE_MASK 0x6
1586 #define MC_WR_HUB__PRESCALE__SHIFT 0x1
1587 #define MC_WR_HUB__BLACKOUT_EXEMPT_MASK 0x8
1588 #define MC_WR_HUB__BLACKOUT_EXEMPT__SHIFT 0x3
1589 #define MC_WR_HUB__STALL_MODE_MASK 0x30
1590 #define MC_WR_HUB__STALL_MODE__SHIFT 0x4
1591 #define MC_WR_HUB__STALL_OVERRIDE_MASK 0x40
1592 #define MC_WR_HUB__STALL_OVERRIDE__SHIFT 0x6
1593 #define MC_WR_HUB__MAX_BURST_MASK 0x780
1594 #define MC_WR_HUB__MAX_BURST__SHIFT 0x7
1595 #define MC_WR_HUB__LAZY_TIMER_MASK 0x7800
1596 #define MC_WR_HUB__LAZY_TIMER__SHIFT 0xb
1597 #define MC_WR_HUB__STALL_OVERRIDE_WTM_MASK 0x8000
1598 #define MC_WR_HUB__STALL_OVERRIDE_WTM__SHIFT 0xf
1599 #define MC_CITF_CREDITS_XBAR__READ_LCL_MASK 0xff
1600 #define MC_CITF_CREDITS_XBAR__READ_LCL__SHIFT 0x0
1601 #define MC_CITF_CREDITS_XBAR__WRITE_LCL_MASK 0xff00
1602 #define MC_CITF_CREDITS_XBAR__WRITE_LCL__SHIFT 0x8
1603 #define MC_RD_GRP_LCL__CB0_MASK 0xf000
1604 #define MC_RD_GRP_LCL__CB0__SHIFT 0xc
1605 #define MC_RD_GRP_LCL__CBCMASK0_MASK 0xf0000
1606 #define MC_RD_GRP_LCL__CBCMASK0__SHIFT 0x10
1607 #define MC_RD_GRP_LCL__CBFMASK0_MASK 0xf00000
1608 #define MC_RD_GRP_LCL__CBFMASK0__SHIFT 0x14
1609 #define MC_RD_GRP_LCL__DB0_MASK 0xf000000
1610 #define MC_RD_GRP_LCL__DB0__SHIFT 0x18
1611 #define MC_RD_GRP_LCL__DBHTILE0_MASK 0xf0000000
1612 #define MC_RD_GRP_LCL__DBHTILE0__SHIFT 0x1c
1613 #define MC_WR_GRP_LCL__CB0_MASK 0xf
1614 #define MC_WR_GRP_LCL__CB0__SHIFT 0x0
1615 #define MC_WR_GRP_LCL__CBCMASK0_MASK 0xf0
1616 #define MC_WR_GRP_LCL__CBCMASK0__SHIFT 0x4
1617 #define MC_WR_GRP_LCL__CBFMASK0_MASK 0xf00
1618 #define MC_WR_GRP_LCL__CBFMASK0__SHIFT 0x8
1619 #define MC_WR_GRP_LCL__DB0_MASK 0xf000
1620 #define MC_WR_GRP_LCL__DB0__SHIFT 0xc
1621 #define MC_WR_GRP_LCL__DBHTILE0_MASK 0xf0000
1622 #define MC_WR_GRP_LCL__DBHTILE0__SHIFT 0x10
1623 #define MC_WR_GRP_LCL__SX0_MASK 0xf00000
1624 #define MC_WR_GRP_LCL__SX0__SHIFT 0x14
1625 #define MC_WR_GRP_LCL__CBIMMED0_MASK 0xf0000000
1626 #define MC_WR_GRP_LCL__CBIMMED0__SHIFT 0x1c
1627 #define MC_CITF_PERF_MON_CNTL2__CID_MASK 0xff
1628 #define MC_CITF_PERF_MON_CNTL2__CID__SHIFT 0x0
1629 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY_MASK 0x2
1630 #define MC_CITF_PERF_MON_RSLT2__CB_RD_BUSY__SHIFT 0x1
1631 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY_MASK 0x4
1632 #define MC_CITF_PERF_MON_RSLT2__DB_RD_BUSY__SHIFT 0x2
1633 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY_MASK 0x8
1634 #define MC_CITF_PERF_MON_RSLT2__TC0_RD_BUSY__SHIFT 0x3
1635 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY_MASK 0x10
1636 #define MC_CITF_PERF_MON_RSLT2__VC0_RD_BUSY__SHIFT 0x4
1637 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY_MASK 0x20
1638 #define MC_CITF_PERF_MON_RSLT2__TC1_RD_BUSY__SHIFT 0x5
1639 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY_MASK 0x40
1640 #define MC_CITF_PERF_MON_RSLT2__VC1_RD_BUSY__SHIFT 0x6
1641 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY_MASK 0x80
1642 #define MC_CITF_PERF_MON_RSLT2__CB_WR_BUSY__SHIFT 0x7
1643 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY_MASK 0x100
1644 #define MC_CITF_PERF_MON_RSLT2__DB_WR_BUSY__SHIFT 0x8
1645 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY_MASK 0x200
1646 #define MC_CITF_PERF_MON_RSLT2__SX_WR_BUSY__SHIFT 0x9
1647 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY_MASK 0x400
1648 #define MC_CITF_PERF_MON_RSLT2__TC2_RD_BUSY__SHIFT 0xa
1649 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY_MASK 0x800
1650 #define MC_CITF_PERF_MON_RSLT2__TC0_WR_BUSY__SHIFT 0xb
1651 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY_MASK 0x1000
1652 #define MC_CITF_PERF_MON_RSLT2__TC1_WR_BUSY__SHIFT 0xc
1653 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY_MASK 0x2000
1654 #define MC_CITF_PERF_MON_RSLT2__TC2_WR_BUSY__SHIFT 0xd
1655 #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY_MASK 0x4000
1656 #define MC_CITF_PERF_MON_RSLT2__TC0_ATOM_BUSY__SHIFT 0xe
1657 #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY_MASK 0x8000
1658 #define MC_CITF_PERF_MON_RSLT2__TC1_ATOM_BUSY__SHIFT 0xf
1659 #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY_MASK 0x10000
1660 #define MC_CITF_PERF_MON_RSLT2__TC2_ATOM_BUSY__SHIFT 0x10
1661 #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY_MASK 0x20000
1662 #define MC_CITF_PERF_MON_RSLT2__CB_ATOM_BUSY__SHIFT 0x11
1663 #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY_MASK 0x40000
1664 #define MC_CITF_PERF_MON_RSLT2__DB_ATOM_BUSY__SHIFT 0x12
1665 #define MC_CITF_MISC_RD_CG__ONDLY_MASK 0x3f
1666 #define MC_CITF_MISC_RD_CG__ONDLY__SHIFT 0x0
1667 #define MC_CITF_MISC_RD_CG__OFFDLY_MASK 0xfc0
1668 #define MC_CITF_MISC_RD_CG__OFFDLY__SHIFT 0x6
1669 #define MC_CITF_MISC_RD_CG__RDYDLY_MASK 0x3f000
1670 #define MC_CITF_MISC_RD_CG__RDYDLY__SHIFT 0xc
1671 #define MC_CITF_MISC_RD_CG__ENABLE_MASK 0x40000
1672 #define MC_CITF_MISC_RD_CG__ENABLE__SHIFT 0x12
1673 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK 0x80000
1674 #define MC_CITF_MISC_RD_CG__MEM_LS_ENABLE__SHIFT 0x13
1675 #define MC_CITF_MISC_WR_CG__ONDLY_MASK 0x3f
1676 #define MC_CITF_MISC_WR_CG__ONDLY__SHIFT 0x0
1677 #define MC_CITF_MISC_WR_CG__OFFDLY_MASK 0xfc0
1678 #define MC_CITF_MISC_WR_CG__OFFDLY__SHIFT 0x6
1679 #define MC_CITF_MISC_WR_CG__RDYDLY_MASK 0x3f000
1680 #define MC_CITF_MISC_WR_CG__RDYDLY__SHIFT 0xc
1681 #define MC_CITF_MISC_WR_CG__ENABLE_MASK 0x40000
1682 #define MC_CITF_MISC_WR_CG__ENABLE__SHIFT 0x12
1683 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK 0x80000
1684 #define MC_CITF_MISC_WR_CG__MEM_LS_ENABLE__SHIFT 0x13
1685 #define MC_CITF_MISC_VM_CG__ONDLY_MASK 0x3f
1686 #define MC_CITF_MISC_VM_CG__ONDLY__SHIFT 0x0
1687 #define MC_CITF_MISC_VM_CG__OFFDLY_MASK 0xfc0
1688 #define MC_CITF_MISC_VM_CG__OFFDLY__SHIFT 0x6
1689 #define MC_CITF_MISC_VM_CG__RDYDLY_MASK 0x3f000
1690 #define MC_CITF_MISC_VM_CG__RDYDLY__SHIFT 0xc
1691 #define MC_CITF_MISC_VM_CG__ENABLE_MASK 0x40000
1692 #define MC_CITF_MISC_VM_CG__ENABLE__SHIFT 0x12
1693 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1694 #define MC_CITF_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1695 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE_MASK 0x4
1696 #define MC_HUB_MISC_POWER__SRBM_GATE_OVERRIDE__SHIFT 0x2
1697 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL_MASK 0x18
1698 #define MC_HUB_MISC_POWER__PM_BLACKOUT_CNTL__SHIFT 0x3
1699 #define MC_HUB_MISC_HUB_CG__ONDLY_MASK 0x3f
1700 #define MC_HUB_MISC_HUB_CG__ONDLY__SHIFT 0x0
1701 #define MC_HUB_MISC_HUB_CG__OFFDLY_MASK 0xfc0
1702 #define MC_HUB_MISC_HUB_CG__OFFDLY__SHIFT 0x6
1703 #define MC_HUB_MISC_HUB_CG__RDYDLY_MASK 0x3f000
1704 #define MC_HUB_MISC_HUB_CG__RDYDLY__SHIFT 0xc
1705 #define MC_HUB_MISC_HUB_CG__ENABLE_MASK 0x40000
1706 #define MC_HUB_MISC_HUB_CG__ENABLE__SHIFT 0x12
1707 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK 0x80000
1708 #define MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE__SHIFT 0x13
1709 #define MC_HUB_MISC_VM_CG__ONDLY_MASK 0x3f
1710 #define MC_HUB_MISC_VM_CG__ONDLY__SHIFT 0x0
1711 #define MC_HUB_MISC_VM_CG__OFFDLY_MASK 0xfc0
1712 #define MC_HUB_MISC_VM_CG__OFFDLY__SHIFT 0x6
1713 #define MC_HUB_MISC_VM_CG__RDYDLY_MASK 0x3f000
1714 #define MC_HUB_MISC_VM_CG__RDYDLY__SHIFT 0xc
1715 #define MC_HUB_MISC_VM_CG__ENABLE_MASK 0x40000
1716 #define MC_HUB_MISC_VM_CG__ENABLE__SHIFT 0x12
1717 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK 0x80000
1718 #define MC_HUB_MISC_VM_CG__MEM_LS_ENABLE__SHIFT 0x13
1719 #define MC_HUB_MISC_SIP_CG__ONDLY_MASK 0x3f
1720 #define MC_HUB_MISC_SIP_CG__ONDLY__SHIFT 0x0
1721 #define MC_HUB_MISC_SIP_CG__OFFDLY_MASK 0xfc0
1722 #define MC_HUB_MISC_SIP_CG__OFFDLY__SHIFT 0x6
1723 #define MC_HUB_MISC_SIP_CG__RDYDLY_MASK 0x3f000
1724 #define MC_HUB_MISC_SIP_CG__RDYDLY__SHIFT 0xc
1725 #define MC_HUB_MISC_SIP_CG__ENABLE_MASK 0x40000
1726 #define MC_HUB_MISC_SIP_CG__ENABLE__SHIFT 0x12
1727 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK 0x80000
1728 #define MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE__SHIFT 0x13
1729 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ_MASK 0x1
1730 #define MC_HUB_MISC_STATUS__OUTSTANDING_READ__SHIFT 0x0
1731 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE_MASK 0x2
1732 #define MC_HUB_MISC_STATUS__OUTSTANDING_WRITE__SHIFT 0x1
1733 #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC_MASK 0x4
1734 #define MC_HUB_MISC_STATUS__OUTSTANDING_ATOMIC__SHIFT 0x2
1735 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ_MASK 0x8
1736 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDREQ__SHIFT 0x3
1737 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET_MASK 0x10
1738 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_RDRET__SHIFT 0x4
1739 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ_MASK 0x20
1740 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRREQ__SHIFT 0x5
1741 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET_MASK 0x40
1742 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_WRRET__SHIFT 0x6
1743 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ_MASK 0x80
1744 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_REQ__SHIFT 0x7
1745 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET_MASK 0x100
1746 #define MC_HUB_MISC_STATUS__OUTSTANDING_HUB_ATOMIC_RET__SHIFT 0x8
1747 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ_MASK 0x200
1748 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_READ__SHIFT 0x9
1749 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE_MASK 0x400
1750 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_WRITE__SHIFT 0xa
1751 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC_MASK 0x800
1752 #define MC_HUB_MISC_STATUS__OUTSTANDING_RPB_ATOMIC__SHIFT 0xb
1753 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ_MASK 0x1000
1754 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_READ__SHIFT 0xc
1755 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE_MASK 0x2000
1756 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_WRITE__SHIFT 0xd
1757 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC_MASK 0x4000
1758 #define MC_HUB_MISC_STATUS__OUTSTANDING_MCD_ATOMIC__SHIFT 0xe
1759 #define MC_HUB_MISC_STATUS__RPB_BUSY_MASK 0x8000
1760 #define MC_HUB_MISC_STATUS__RPB_BUSY__SHIFT 0xf
1761 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING_MASK 0x10000
1762 #define MC_HUB_MISC_STATUS__WRITE_DEADLOCK_WARNING__SHIFT 0x10
1763 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING_MASK 0x20000
1764 #define MC_HUB_MISC_STATUS__READ_DEADLOCK_WARNING__SHIFT 0x11
1765 #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING_MASK 0x40000
1766 #define MC_HUB_MISC_STATUS__ATOMIC_DEADLOCK_WARNING__SHIFT 0x12
1767 #define MC_HUB_MISC_STATUS__GFX_BUSY_MASK 0x80000
1768 #define MC_HUB_MISC_STATUS__GFX_BUSY__SHIFT 0x13
1769 #define MC_HUB_MISC_OVERRIDE__IDLE_MASK 0x3
1770 #define MC_HUB_MISC_OVERRIDE__IDLE__SHIFT 0x0
1771 #define MC_HUB_MISC_FRAMING__BITS_MASK 0xffffffff
1772 #define MC_HUB_MISC_FRAMING__BITS__SHIFT 0x0
1773 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0_MASK 0x2
1774 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL0__SHIFT 0x1
1775 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1_MASK 0x4
1776 #define MC_HUB_WDP_CNTL__JUMPAHEAD_GBL1__SHIFT 0x2
1777 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL_MASK 0x8
1778 #define MC_HUB_WDP_CNTL__JUMPAHEAD_INTERNAL__SHIFT 0x3
1779 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1780 #define MC_HUB_WDP_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1781 #define MC_HUB_WDP_CNTL__DEBUG_REG_MASK 0x1fe0
1782 #define MC_HUB_WDP_CNTL__DEBUG_REG__SHIFT 0x5
1783 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x2000
1784 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0xd
1785 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x4000
1786 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0xe
1787 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL_MASK 0x8000
1788 #define MC_HUB_WDP_CNTL__DISABLE_SELF_INIT_INTERNAL__SHIFT 0xf
1789 #define MC_HUB_WDP_CNTL__FAIR_CH_SW_MASK 0x10000
1790 #define MC_HUB_WDP_CNTL__FAIR_CH_SW__SHIFT 0x10
1791 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS_MASK 0x20000
1792 #define MC_HUB_WDP_CNTL__LCLWRREQ_BYPASS__SHIFT 0x11
1793 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP_MASK 0x40000
1794 #define MC_HUB_WDP_CNTL__DISP_WAIT_EOP__SHIFT 0x12
1795 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP_MASK 0x80000
1796 #define MC_HUB_WDP_CNTL__MCD_WAIT_EOP__SHIFT 0x13
1797 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP_MASK 0x100000
1798 #define MC_HUB_WDP_CNTL__SIP_WAIT_EOP__SHIFT 0x14
1799 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN_MASK 0x200000
1800 #define MC_HUB_WDP_CNTL__UVD_VCE_WRITE_PRI_EN__SHIFT 0x15
1801 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN_MASK 0x400000
1802 #define MC_HUB_WDP_CNTL__WRITE_PRI_EN__SHIFT 0x16
1803 #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE_MASK 0x800000
1804 #define MC_HUB_WDP_CNTL__IH_PHYSADDR_ENABLE__SHIFT 0x17
1805 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS_MASK 0x1
1806 #define MC_HUB_WDP_ERR__MGPU1_TARG_SYS__SHIFT 0x0
1807 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS_MASK 0x2
1808 #define MC_HUB_WDP_ERR__MGPU2_TARG_SYS__SHIFT 0x1
1809 #define MC_HUB_WDP_BP__ENABLE_MASK 0x1
1810 #define MC_HUB_WDP_BP__ENABLE__SHIFT 0x0
1811 #define MC_HUB_WDP_BP__RDRET_MASK 0x3fffe
1812 #define MC_HUB_WDP_BP__RDRET__SHIFT 0x1
1813 #define MC_HUB_WDP_BP__WRREQ_MASK 0x3ffc0000
1814 #define MC_HUB_WDP_BP__WRREQ__SHIFT 0x12
1815 #define MC_HUB_WDP_STATUS__SIP_AVAIL_MASK 0x1
1816 #define MC_HUB_WDP_STATUS__SIP_AVAIL__SHIFT 0x0
1817 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL_MASK 0x2
1818 #define MC_HUB_WDP_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1819 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL_MASK 0x4
1820 #define MC_HUB_WDP_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1821 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL_MASK 0x8
1822 #define MC_HUB_WDP_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1823 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1824 #define MC_HUB_WDP_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1825 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL_MASK 0x20
1826 #define MC_HUB_WDP_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1827 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL_MASK 0x40
1828 #define MC_HUB_WDP_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1829 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL_MASK 0x80
1830 #define MC_HUB_WDP_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1831 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL_MASK 0x100
1832 #define MC_HUB_WDP_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1833 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL_MASK 0x200
1834 #define MC_HUB_WDP_STATUS__MCDW_WR_AVAIL__SHIFT 0x9
1835 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL_MASK 0x400
1836 #define MC_HUB_WDP_STATUS__MCDX_WR_AVAIL__SHIFT 0xa
1837 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL_MASK 0x800
1838 #define MC_HUB_WDP_STATUS__MCDY_WR_AVAIL__SHIFT 0xb
1839 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL_MASK 0x1000
1840 #define MC_HUB_WDP_STATUS__MCDZ_WR_AVAIL__SHIFT 0xc
1841 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL_MASK 0x2000
1842 #define MC_HUB_WDP_STATUS__MCDS_WR_AVAIL__SHIFT 0xd
1843 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL_MASK 0x4000
1844 #define MC_HUB_WDP_STATUS__MCDT_WR_AVAIL__SHIFT 0xe
1845 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL_MASK 0x8000
1846 #define MC_HUB_WDP_STATUS__MCDU_WR_AVAIL__SHIFT 0xf
1847 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL_MASK 0x10000
1848 #define MC_HUB_WDP_STATUS__MCDV_WR_AVAIL__SHIFT 0x10
1849 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL_MASK 0x20000
1850 #define MC_HUB_WDP_STATUS__GBL0_VM_FULL__SHIFT 0x11
1851 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL_MASK 0x40000
1852 #define MC_HUB_WDP_STATUS__GBL0_STOR_FULL__SHIFT 0x12
1853 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x80000
1854 #define MC_HUB_WDP_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0x13
1855 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL_MASK 0x100000
1856 #define MC_HUB_WDP_STATUS__GBL1_VM_FULL__SHIFT 0x14
1857 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL_MASK 0x200000
1858 #define MC_HUB_WDP_STATUS__GBL1_STOR_FULL__SHIFT 0x15
1859 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x400000
1860 #define MC_HUB_WDP_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0x16
1861 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL_MASK 0x1
1862 #define MC_HUB_RDREQ_STATUS__SIP_AVAIL__SHIFT 0x0
1863 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL_MASK 0x2
1864 #define MC_HUB_RDREQ_STATUS__MCDW_RD_AVAIL__SHIFT 0x1
1865 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL_MASK 0x4
1866 #define MC_HUB_RDREQ_STATUS__MCDX_RD_AVAIL__SHIFT 0x2
1867 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL_MASK 0x8
1868 #define MC_HUB_RDREQ_STATUS__MCDY_RD_AVAIL__SHIFT 0x3
1869 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL_MASK 0x10
1870 #define MC_HUB_RDREQ_STATUS__MCDZ_RD_AVAIL__SHIFT 0x4
1871 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL_MASK 0x20
1872 #define MC_HUB_RDREQ_STATUS__MCDS_RD_AVAIL__SHIFT 0x5
1873 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL_MASK 0x40
1874 #define MC_HUB_RDREQ_STATUS__MCDT_RD_AVAIL__SHIFT 0x6
1875 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL_MASK 0x80
1876 #define MC_HUB_RDREQ_STATUS__MCDU_RD_AVAIL__SHIFT 0x7
1877 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL_MASK 0x100
1878 #define MC_HUB_RDREQ_STATUS__MCDV_RD_AVAIL__SHIFT 0x8
1879 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL_MASK 0x200
1880 #define MC_HUB_RDREQ_STATUS__GBL0_VM_FULL__SHIFT 0x9
1881 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL_MASK 0x400
1882 #define MC_HUB_RDREQ_STATUS__GBL0_STOR_FULL__SHIFT 0xa
1883 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL_MASK 0x800
1884 #define MC_HUB_RDREQ_STATUS__GBL0_BYPASS_STOR_FULL__SHIFT 0xb
1885 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL_MASK 0x1000
1886 #define MC_HUB_RDREQ_STATUS__GBL1_VM_FULL__SHIFT 0xc
1887 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL_MASK 0x2000
1888 #define MC_HUB_RDREQ_STATUS__GBL1_STOR_FULL__SHIFT 0xd
1889 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL_MASK 0x4000
1890 #define MC_HUB_RDREQ_STATUS__GBL1_BYPASS_STOR_FULL__SHIFT 0xe
1891 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR_MASK 0x8000
1892 #define MC_HUB_RDREQ_STATUS__PWRXPRESS_ERR__SHIFT 0xf
1893 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL_MASK 0x1
1894 #define MC_HUB_WRRET_STATUS__MCDW_AVAIL__SHIFT 0x0
1895 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL_MASK 0x2
1896 #define MC_HUB_WRRET_STATUS__MCDX_AVAIL__SHIFT 0x1
1897 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL_MASK 0x4
1898 #define MC_HUB_WRRET_STATUS__MCDY_AVAIL__SHIFT 0x2
1899 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL_MASK 0x8
1900 #define MC_HUB_WRRET_STATUS__MCDZ_AVAIL__SHIFT 0x3
1901 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL_MASK 0x10
1902 #define MC_HUB_WRRET_STATUS__MCDS_AVAIL__SHIFT 0x4
1903 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL_MASK 0x20
1904 #define MC_HUB_WRRET_STATUS__MCDT_AVAIL__SHIFT 0x5
1905 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL_MASK 0x40
1906 #define MC_HUB_WRRET_STATUS__MCDU_AVAIL__SHIFT 0x6
1907 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL_MASK 0x80
1908 #define MC_HUB_WRRET_STATUS__MCDV_AVAIL__SHIFT 0x7
1909 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT_MASK 0x1
1910 #define MC_HUB_RDREQ_CNTL__REMOTE_BLACKOUT__SHIFT 0x0
1911 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0_MASK 0x4
1912 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL0__SHIFT 0x2
1913 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1_MASK 0x8
1914 #define MC_HUB_RDREQ_CNTL__JUMPAHEAD_GBL1__SHIFT 0x3
1915 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE_MASK 0x10
1916 #define MC_HUB_RDREQ_CNTL__OVERRIDE_STALL_ENABLE__SHIFT 0x4
1917 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE_MASK 0x20
1918 #define MC_HUB_RDREQ_CNTL__MCDW_STALL_MODE__SHIFT 0x5
1919 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE_MASK 0x40
1920 #define MC_HUB_RDREQ_CNTL__MCDX_STALL_MODE__SHIFT 0x6
1921 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE_MASK 0x80
1922 #define MC_HUB_RDREQ_CNTL__MCDY_STALL_MODE__SHIFT 0x7
1923 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE_MASK 0x100
1924 #define MC_HUB_RDREQ_CNTL__MCDZ_STALL_MODE__SHIFT 0x8
1925 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE_MASK 0x200
1926 #define MC_HUB_RDREQ_CNTL__MCDS_STALL_MODE__SHIFT 0x9
1927 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE_MASK 0x400
1928 #define MC_HUB_RDREQ_CNTL__MCDT_STALL_MODE__SHIFT 0xa
1929 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE_MASK 0x800
1930 #define MC_HUB_RDREQ_CNTL__MCDU_STALL_MODE__SHIFT 0xb
1931 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE_MASK 0x1000
1932 #define MC_HUB_RDREQ_CNTL__MCDV_STALL_MODE__SHIFT 0xc
1933 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK_MASK 0x2000
1934 #define MC_HUB_RDREQ_CNTL__BREAK_HDP_DEADLOCK__SHIFT 0xd
1935 #define MC_HUB_RDREQ_CNTL__DEBUG_REG_MASK 0x1fc000
1936 #define MC_HUB_RDREQ_CNTL__DEBUG_REG__SHIFT 0xe
1937 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0_MASK 0x200000
1938 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL0__SHIFT 0x15
1939 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1_MASK 0x400000
1940 #define MC_HUB_RDREQ_CNTL__DISABLE_SELF_INIT_GBL1__SHIFT 0x16
1941 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE_MASK 0x800000
1942 #define MC_HUB_RDREQ_CNTL__PWRXPRESS_MODE__SHIFT 0x17
1943 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE_MASK 0x1000000
1944 #define MC_HUB_RDREQ_CNTL__ACPG_HP_TO_MCD_OVERRIDE__SHIFT 0x18
1945 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE_MASK 0x2000000
1946 #define MC_HUB_RDREQ_CNTL__GBL0_PRI_ENABLE__SHIFT 0x19
1947 #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE_MASK 0x4000000
1948 #define MC_HUB_RDREQ_CNTL__UVD_TRANSCODE_ENABLE__SHIFT 0x1a
1949 #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD_MASK 0x78000000
1950 #define MC_HUB_RDREQ_CNTL__DMIF_URG_THRESHOLD__SHIFT 0x1b
1951 #define MC_HUB_WRRET_CNTL__JUMPAHEAD_MASK 0x1
1952 #define MC_HUB_WRRET_CNTL__JUMPAHEAD__SHIFT 0x0
1953 #define MC_HUB_WRRET_CNTL__BP_MASK 0x1ffffe
1954 #define MC_HUB_WRRET_CNTL__BP__SHIFT 0x1
1955 #define MC_HUB_WRRET_CNTL__BP_ENABLE_MASK 0x200000
1956 #define MC_HUB_WRRET_CNTL__BP_ENABLE__SHIFT 0x15
1957 #define MC_HUB_WRRET_CNTL__DEBUG_REG_MASK 0x3fc00000
1958 #define MC_HUB_WRRET_CNTL__DEBUG_REG__SHIFT 0x16
1959 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT_MASK 0x40000000
1960 #define MC_HUB_WRRET_CNTL__DISABLE_SELF_INIT__SHIFT 0x1e
1961 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW_MASK 0x80000000
1962 #define MC_HUB_WRRET_CNTL__FAIR_CH_SW__SHIFT 0x1f
1963 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1964 #define MC_HUB_RDREQ_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1965 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1966 #define MC_HUB_RDREQ_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1967 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1968 #define MC_HUB_RDREQ_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1969 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1970 #define MC_HUB_RDREQ_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1971 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1972 #define MC_HUB_RDREQ_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1973 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1974 #define MC_HUB_RDREQ_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1975 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1976 #define MC_HUB_RDREQ_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1977 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1978 #define MC_HUB_RDREQ_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1979 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT_MASK 0x7
1980 #define MC_HUB_WDP_WTM_CNTL__GROUP0_DECREMENT__SHIFT 0x0
1981 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT_MASK 0x38
1982 #define MC_HUB_WDP_WTM_CNTL__GROUP1_DECREMENT__SHIFT 0x3
1983 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT_MASK 0x1c0
1984 #define MC_HUB_WDP_WTM_CNTL__GROUP2_DECREMENT__SHIFT 0x6
1985 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT_MASK 0xe00
1986 #define MC_HUB_WDP_WTM_CNTL__GROUP3_DECREMENT__SHIFT 0x9
1987 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT_MASK 0x7000
1988 #define MC_HUB_WDP_WTM_CNTL__GROUP4_DECREMENT__SHIFT 0xc
1989 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT_MASK 0x38000
1990 #define MC_HUB_WDP_WTM_CNTL__GROUP5_DECREMENT__SHIFT 0xf
1991 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT_MASK 0x1c0000
1992 #define MC_HUB_WDP_WTM_CNTL__GROUP6_DECREMENT__SHIFT 0x12
1993 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT_MASK 0xe00000
1994 #define MC_HUB_WDP_WTM_CNTL__GROUP7_DECREMENT__SHIFT 0x15
1995 #define MC_HUB_WDP_CREDITS__VM0_MASK 0xff
1996 #define MC_HUB_WDP_CREDITS__VM0__SHIFT 0x0
1997 #define MC_HUB_WDP_CREDITS__VM1_MASK 0xff00
1998 #define MC_HUB_WDP_CREDITS__VM1__SHIFT 0x8
1999 #define MC_HUB_WDP_CREDITS__STOR0_MASK 0xff0000
2000 #define MC_HUB_WDP_CREDITS__STOR0__SHIFT 0x10
2001 #define MC_HUB_WDP_CREDITS__STOR1_MASK 0xff000000
2002 #define MC_HUB_WDP_CREDITS__STOR1__SHIFT 0x18
2003 #define MC_HUB_WDP_CREDITS2__STOR0_PRI_MASK 0xff
2004 #define MC_HUB_WDP_CREDITS2__STOR0_PRI__SHIFT 0x0
2005 #define MC_HUB_WDP_CREDITS2__STOR1_PRI_MASK 0xff00
2006 #define MC_HUB_WDP_CREDITS2__STOR1_PRI__SHIFT 0x8
2007 #define MC_HUB_WDP_CREDITS2__VM2_MASK 0xff0000
2008 #define MC_HUB_WDP_CREDITS2__VM2__SHIFT 0x10
2009 #define MC_HUB_WDP_CREDITS2__VM3_MASK 0xff000000
2010 #define MC_HUB_WDP_CREDITS2__VM3__SHIFT 0x18
2011 #define MC_HUB_WDP_GBL0__MAXBURST_MASK 0xf
2012 #define MC_HUB_WDP_GBL0__MAXBURST__SHIFT 0x0
2013 #define MC_HUB_WDP_GBL0__LAZY_TIMER_MASK 0xf0
2014 #define MC_HUB_WDP_GBL0__LAZY_TIMER__SHIFT 0x4
2015 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_MASK 0xff00
2016 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD__SHIFT 0x8
2017 #define MC_HUB_WDP_GBL0__STALL_MODE_MASK 0x10000
2018 #define MC_HUB_WDP_GBL0__STALL_MODE__SHIFT 0x10
2019 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI_MASK 0x1fe0000
2020 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x11
2021 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG_MASK 0xfe000000
2022 #define MC_HUB_WDP_GBL0__STALL_THRESHOLD_URG__SHIFT 0x19
2023 #define MC_HUB_WDP_GBL1__MAXBURST_MASK 0xf
2024 #define MC_HUB_WDP_GBL1__MAXBURST__SHIFT 0x0
2025 #define MC_HUB_WDP_GBL1__LAZY_TIMER_MASK 0xf0
2026 #define MC_HUB_WDP_GBL1__LAZY_TIMER__SHIFT 0x4
2027 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_MASK 0xff00
2028 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD__SHIFT 0x8
2029 #define MC_HUB_WDP_GBL1__STALL_MODE_MASK 0x10000
2030 #define MC_HUB_WDP_GBL1__STALL_MODE__SHIFT 0x10
2031 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI_MASK 0x1fe0000
2032 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x11
2033 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG_MASK 0xfe000000
2034 #define MC_HUB_WDP_GBL1__STALL_THRESHOLD_URG__SHIFT 0x19
2035 #define MC_HUB_WDP_CREDITS3__STOR0_URG_MASK 0xff
2036 #define MC_HUB_WDP_CREDITS3__STOR0_URG__SHIFT 0x0
2037 #define MC_HUB_WDP_CREDITS3__STOR1_URG_MASK 0xff00
2038 #define MC_HUB_WDP_CREDITS3__STOR1_URG__SHIFT 0x8
2039 #define MC_HUB_RDREQ_CREDITS__VM0_MASK 0xff
2040 #define MC_HUB_RDREQ_CREDITS__VM0__SHIFT 0x0
2041 #define MC_HUB_RDREQ_CREDITS__VM1_MASK 0xff00
2042 #define MC_HUB_RDREQ_CREDITS__VM1__SHIFT 0x8
2043 #define MC_HUB_RDREQ_CREDITS__STOR0_MASK 0xff0000
2044 #define MC_HUB_RDREQ_CREDITS__STOR0__SHIFT 0x10
2045 #define MC_HUB_RDREQ_CREDITS__STOR1_MASK 0xff000000
2046 #define MC_HUB_RDREQ_CREDITS__STOR1__SHIFT 0x18
2047 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI_MASK 0xff
2048 #define MC_HUB_RDREQ_CREDITS2__STOR0_PRI__SHIFT 0x0
2049 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI_MASK 0xff00
2050 #define MC_HUB_RDREQ_CREDITS2__STOR1_PRI__SHIFT 0x8
2051 #define MC_HUB_SHARED_DAGB_DLY__DLY_MASK 0x3f
2052 #define MC_HUB_SHARED_DAGB_DLY__DLY__SHIFT 0x0
2053 #define MC_HUB_SHARED_DAGB_DLY__CLI_MASK 0x3f0000
2054 #define MC_HUB_SHARED_DAGB_DLY__CLI__SHIFT 0x10
2055 #define MC_HUB_SHARED_DAGB_DLY__POS_MASK 0x1f000000
2056 #define MC_HUB_SHARED_DAGB_DLY__POS__SHIFT 0x18
2057 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ_MASK 0x1
2058 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_READ__SHIFT 0x0
2059 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE_MASK 0x2
2060 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_GFX_WRITE__SHIFT 0x1
2061 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ_MASK 0x4
2062 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_READ__SHIFT 0x2
2063 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE_MASK 0x8
2064 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_RLC_WRITE__SHIFT 0x3
2065 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ_MASK 0x10
2066 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_READ__SHIFT 0x4
2067 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE_MASK 0x20
2068 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA0_WRITE__SHIFT 0x5
2069 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ_MASK 0x40
2070 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_READ__SHIFT 0x6
2071 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE_MASK 0x80
2072 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SDMA1_WRITE__SHIFT 0x7
2073 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ_MASK 0x100
2074 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_READ__SHIFT 0x8
2075 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE_MASK 0x200
2076 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_DISP_WRITE__SHIFT 0x9
2077 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ_MASK 0x400
2078 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_READ__SHIFT 0xa
2079 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE_MASK 0x800
2080 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_UVD_WRITE__SHIFT 0xb
2081 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ_MASK 0x1000
2082 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_READ__SHIFT 0xc
2083 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE_MASK 0x2000
2084 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SMU_WRITE__SHIFT 0xd
2085 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ_MASK 0x4000
2086 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_READ__SHIFT 0xe
2087 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE_MASK 0x8000
2088 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_HDP_WRITE__SHIFT 0xf
2089 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ_MASK 0x10000
2090 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_READ__SHIFT 0x10
2091 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE_MASK 0x20000
2092 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_OTH_WRITE__SHIFT 0x11
2093 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ_MASK 0x40000
2094 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_READ__SHIFT 0x12
2095 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE_MASK 0x80000
2096 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VMC_WRITE__SHIFT 0x13
2097 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ_MASK 0x100000
2098 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_READ__SHIFT 0x14
2099 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE_MASK 0x200000
2100 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VCE_WRITE__SHIFT 0x15
2101 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ_MASK 0x400000
2102 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_READ__SHIFT 0x16
2103 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE_MASK 0x800000
2104 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ACP_WRITE__SHIFT 0x17
2105 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ_MASK 0x1000000
2106 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_READ__SHIFT 0x18
2107 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE_MASK 0x2000000
2108 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_SAMMSP_WRITE__SHIFT 0x19
2109 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ_MASK 0x4000000
2110 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_READ__SHIFT 0x1a
2111 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE_MASK 0x8000000
2112 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_XDMA_WRITE__SHIFT 0x1b
2113 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ_MASK 0x10000000
2114 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_READ__SHIFT 0x1c
2115 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE_MASK 0x20000000
2116 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_ISP_WRITE__SHIFT 0x1d
2117 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ_MASK 0x40000000
2118 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_READ__SHIFT 0x1e
2119 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE_MASK 0x80000000
2120 #define MC_HUB_MISC_IDLE_STATUS__OUTSTANDING_VP8_WRITE__SHIFT 0x1f
2121 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK 0x3
2122 #define MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT 0x0
2123 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT_MASK 0x7c
2124 #define MC_HUB_RDREQ_DMIF_LIMIT__LIMIT_COUNT__SHIFT 0x2
2125 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE_MASK 0x3
2126 #define MC_HUB_RDREQ_ACPG_LIMIT__ENABLE__SHIFT 0x0
2127 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT_MASK 0x7c
2128 #define MC_HUB_RDREQ_ACPG_LIMIT__LIMIT_COUNT__SHIFT 0x2
2129 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE_MASK 0x1
2130 #define MC_HUB_WDP_BYPASS_GBL0__ENABLE__SHIFT 0x0
2131 #define MC_HUB_WDP_BYPASS_GBL0__CID1_MASK 0x1fe
2132 #define MC_HUB_WDP_BYPASS_GBL0__CID1__SHIFT 0x1
2133 #define MC_HUB_WDP_BYPASS_GBL0__CID2_MASK 0x1fe00
2134 #define MC_HUB_WDP_BYPASS_GBL0__CID2__SHIFT 0x9
2135 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME_MASK 0xfe0000
2136 #define MC_HUB_WDP_BYPASS_GBL0__HDP_PRIORITY_TIME__SHIFT 0x11
2137 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME_MASK 0x7f000000
2138 #define MC_HUB_WDP_BYPASS_GBL0__OTH_PRIORITY_TIME__SHIFT 0x18
2139 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE_MASK 0x1
2140 #define MC_HUB_WDP_BYPASS_GBL1__ENABLE__SHIFT 0x0
2141 #define MC_HUB_WDP_BYPASS_GBL1__CID1_MASK 0x1fe
2142 #define MC_HUB_WDP_BYPASS_GBL1__CID1__SHIFT 0x1
2143 #define MC_HUB_WDP_BYPASS_GBL1__CID2_MASK 0x1fe00
2144 #define MC_HUB_WDP_BYPASS_GBL1__CID2__SHIFT 0x9
2145 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME_MASK 0xfe0000
2146 #define MC_HUB_WDP_BYPASS_GBL1__HDP_PRIORITY_TIME__SHIFT 0x11
2147 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME_MASK 0x7f000000
2148 #define MC_HUB_WDP_BYPASS_GBL1__OTH_PRIORITY_TIME__SHIFT 0x18
2149 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE_MASK 0x1
2150 #define MC_HUB_RDREQ_BYPASS_GBL0__ENABLE__SHIFT 0x0
2151 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1_MASK 0x1fe
2152 #define MC_HUB_RDREQ_BYPASS_GBL0__CID1__SHIFT 0x1
2153 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2_MASK 0x1fe00
2154 #define MC_HUB_RDREQ_BYPASS_GBL0__CID2__SHIFT 0x9
2155 #define MC_HUB_WDP_SH2__ENABLE_MASK 0x1
2156 #define MC_HUB_WDP_SH2__ENABLE__SHIFT 0x0
2157 #define MC_HUB_WDP_SH2__PRESCALE_MASK 0x6
2158 #define MC_HUB_WDP_SH2__PRESCALE__SHIFT 0x1
2159 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT_MASK 0x8
2160 #define MC_HUB_WDP_SH2__BLACKOUT_EXEMPT__SHIFT 0x3
2161 #define MC_HUB_WDP_SH2__STALL_MODE_MASK 0x30
2162 #define MC_HUB_WDP_SH2__STALL_MODE__SHIFT 0x4
2163 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_MASK 0x40
2164 #define MC_HUB_WDP_SH2__STALL_OVERRIDE__SHIFT 0x6
2165 #define MC_HUB_WDP_SH2__MAXBURST_MASK 0x780
2166 #define MC_HUB_WDP_SH2__MAXBURST__SHIFT 0x7
2167 #define MC_HUB_WDP_SH2__LAZY_TIMER_MASK 0x7800
2168 #define MC_HUB_WDP_SH2__LAZY_TIMER__SHIFT 0xb
2169 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM_MASK 0x8000
2170 #define MC_HUB_WDP_SH2__STALL_OVERRIDE_WTM__SHIFT 0xf
2171 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2172 #define MC_HUB_WDP_SH2__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2173 #define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2174 #define MC_HUB_WDP_SH2__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2175 #define MC_HUB_WDP_SH3__ENABLE_MASK 0x1
2176 #define MC_HUB_WDP_SH3__ENABLE__SHIFT 0x0
2177 #define MC_HUB_WDP_SH3__PRESCALE_MASK 0x6
2178 #define MC_HUB_WDP_SH3__PRESCALE__SHIFT 0x1
2179 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT_MASK 0x8
2180 #define MC_HUB_WDP_SH3__BLACKOUT_EXEMPT__SHIFT 0x3
2181 #define MC_HUB_WDP_SH3__STALL_MODE_MASK 0x30
2182 #define MC_HUB_WDP_SH3__STALL_MODE__SHIFT 0x4
2183 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_MASK 0x40
2184 #define MC_HUB_WDP_SH3__STALL_OVERRIDE__SHIFT 0x6
2185 #define MC_HUB_WDP_SH3__MAXBURST_MASK 0x780
2186 #define MC_HUB_WDP_SH3__MAXBURST__SHIFT 0x7
2187 #define MC_HUB_WDP_SH3__LAZY_TIMER_MASK 0x7800
2188 #define MC_HUB_WDP_SH3__LAZY_TIMER__SHIFT 0xb
2189 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM_MASK 0x8000
2190 #define MC_HUB_WDP_SH3__STALL_OVERRIDE_WTM__SHIFT 0xf
2191 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2192 #define MC_HUB_WDP_SH3__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2193 #define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2194 #define MC_HUB_WDP_SH3__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2195 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC_MASK 0x1
2196 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_GFX_ATOMIC__SHIFT 0x0
2197 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC_MASK 0x2
2198 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_RLC_ATOMIC__SHIFT 0x1
2199 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC_MASK 0x4
2200 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA0_ATOMIC__SHIFT 0x2
2201 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC_MASK 0x8
2202 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SDMA1_ATOMIC__SHIFT 0x3
2203 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC_MASK 0x10
2204 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_DISP_ATOMIC__SHIFT 0x4
2205 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC_MASK 0x20
2206 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_UVD_ATOMIC__SHIFT 0x5
2207 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC_MASK 0x40
2208 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SMU_ATOMIC__SHIFT 0x6
2209 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC_MASK 0x80
2210 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_HDP_ATOMIC__SHIFT 0x7
2211 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC_MASK 0x100
2212 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_OTH_ATOMIC__SHIFT 0x8
2213 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC_MASK 0x200
2214 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VMC_ATOMIC__SHIFT 0x9
2215 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC_MASK 0x400
2216 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VCE_ATOMIC__SHIFT 0xa
2217 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC_MASK 0x800
2218 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ACP_ATOMIC__SHIFT 0xb
2219 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC_MASK 0x1000
2220 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_SAMMSP_ATOMIC__SHIFT 0xc
2221 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC_MASK 0x2000
2222 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_XDMA_ATOMIC__SHIFT 0xd
2223 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC_MASK 0x4000
2224 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_ISP_ATOMIC__SHIFT 0xe
2225 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC_MASK 0x8000
2226 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VP8_ATOMIC__SHIFT 0xf
2227 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ_MASK 0x10000
2228 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_READ__SHIFT 0x10
2229 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE_MASK 0x20000
2230 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_WRITE__SHIFT 0x11
2231 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC_MASK 0x40000
2232 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_VIN0_ATOMIC__SHIFT 0x12
2233 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ_MASK 0x80000
2234 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_READ__SHIFT 0x13
2235 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE_MASK 0x100000
2236 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_WRITE__SHIFT 0x14
2237 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC_MASK 0x200000
2238 #define MC_HUB_MISC_ATOMIC_IDLE_STATUS__OUTSTANDING_TLS_ATOMIC__SHIFT 0x15
2239 #define MC_HUB_WDP_VIN0__ENABLE_MASK 0x1
2240 #define MC_HUB_WDP_VIN0__ENABLE__SHIFT 0x0
2241 #define MC_HUB_WDP_VIN0__PRESCALE_MASK 0x6
2242 #define MC_HUB_WDP_VIN0__PRESCALE__SHIFT 0x1
2243 #define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT_MASK 0x8
2244 #define MC_HUB_WDP_VIN0__BLACKOUT_EXEMPT__SHIFT 0x3
2245 #define MC_HUB_WDP_VIN0__STALL_MODE_MASK 0x30
2246 #define MC_HUB_WDP_VIN0__STALL_MODE__SHIFT 0x4
2247 #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_MASK 0x40
2248 #define MC_HUB_WDP_VIN0__STALL_OVERRIDE__SHIFT 0x6
2249 #define MC_HUB_WDP_VIN0__MAXBURST_MASK 0x780
2250 #define MC_HUB_WDP_VIN0__MAXBURST__SHIFT 0x7
2251 #define MC_HUB_WDP_VIN0__LAZY_TIMER_MASK 0x7800
2252 #define MC_HUB_WDP_VIN0__LAZY_TIMER__SHIFT 0xb
2253 #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM_MASK 0x8000
2254 #define MC_HUB_WDP_VIN0__STALL_OVERRIDE_WTM__SHIFT 0xf
2255 #define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2256 #define MC_HUB_WDP_VIN0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2257 #define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2258 #define MC_HUB_WDP_VIN0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2259 #define MC_HUB_RDREQ_MCDW__ENABLE_MASK 0x1
2260 #define MC_HUB_RDREQ_MCDW__ENABLE__SHIFT 0x0
2261 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2262 #define MC_HUB_RDREQ_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2263 #define MC_HUB_RDREQ_MCDW__BUS_MASK 0x4
2264 #define MC_HUB_RDREQ_MCDW__BUS__SHIFT 0x2
2265 #define MC_HUB_RDREQ_MCDW__MAXBURST_MASK 0x78
2266 #define MC_HUB_RDREQ_MCDW__MAXBURST__SHIFT 0x3
2267 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER_MASK 0x780
2268 #define MC_HUB_RDREQ_MCDW__LAZY_TIMER__SHIFT 0x7
2269 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS_MASK 0x3f800
2270 #define MC_HUB_RDREQ_MCDW__ASK_CREDITS__SHIFT 0xb
2271 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS_MASK 0x1fc0000
2272 #define MC_HUB_RDREQ_MCDW__DISPLAY_CREDITS__SHIFT 0x12
2273 #define MC_HUB_RDREQ_MCDW__MED_CREDITS_MASK 0xfe000000
2274 #define MC_HUB_RDREQ_MCDW__MED_CREDITS__SHIFT 0x19
2275 #define MC_HUB_RDREQ_MCDX__ENABLE_MASK 0x1
2276 #define MC_HUB_RDREQ_MCDX__ENABLE__SHIFT 0x0
2277 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2278 #define MC_HUB_RDREQ_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2279 #define MC_HUB_RDREQ_MCDX__BUS_MASK 0x4
2280 #define MC_HUB_RDREQ_MCDX__BUS__SHIFT 0x2
2281 #define MC_HUB_RDREQ_MCDX__MAXBURST_MASK 0x78
2282 #define MC_HUB_RDREQ_MCDX__MAXBURST__SHIFT 0x3
2283 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER_MASK 0x780
2284 #define MC_HUB_RDREQ_MCDX__LAZY_TIMER__SHIFT 0x7
2285 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS_MASK 0x3f800
2286 #define MC_HUB_RDREQ_MCDX__ASK_CREDITS__SHIFT 0xb
2287 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS_MASK 0x1fc0000
2288 #define MC_HUB_RDREQ_MCDX__DISPLAY_CREDITS__SHIFT 0x12
2289 #define MC_HUB_RDREQ_MCDX__MED_CREDITS_MASK 0xfe000000
2290 #define MC_HUB_RDREQ_MCDX__MED_CREDITS__SHIFT 0x19
2291 #define MC_HUB_RDREQ_MCDY__ENABLE_MASK 0x1
2292 #define MC_HUB_RDREQ_MCDY__ENABLE__SHIFT 0x0
2293 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2294 #define MC_HUB_RDREQ_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2295 #define MC_HUB_RDREQ_MCDY__BUS_MASK 0x4
2296 #define MC_HUB_RDREQ_MCDY__BUS__SHIFT 0x2
2297 #define MC_HUB_RDREQ_MCDY__MAXBURST_MASK 0x78
2298 #define MC_HUB_RDREQ_MCDY__MAXBURST__SHIFT 0x3
2299 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER_MASK 0x780
2300 #define MC_HUB_RDREQ_MCDY__LAZY_TIMER__SHIFT 0x7
2301 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS_MASK 0x3f800
2302 #define MC_HUB_RDREQ_MCDY__ASK_CREDITS__SHIFT 0xb
2303 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS_MASK 0x1fc0000
2304 #define MC_HUB_RDREQ_MCDY__DISPLAY_CREDITS__SHIFT 0x12
2305 #define MC_HUB_RDREQ_MCDY__MED_CREDITS_MASK 0xfe000000
2306 #define MC_HUB_RDREQ_MCDY__MED_CREDITS__SHIFT 0x19
2307 #define MC_HUB_RDREQ_MCDZ__ENABLE_MASK 0x1
2308 #define MC_HUB_RDREQ_MCDZ__ENABLE__SHIFT 0x0
2309 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2310 #define MC_HUB_RDREQ_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2311 #define MC_HUB_RDREQ_MCDZ__BUS_MASK 0x4
2312 #define MC_HUB_RDREQ_MCDZ__BUS__SHIFT 0x2
2313 #define MC_HUB_RDREQ_MCDZ__MAXBURST_MASK 0x78
2314 #define MC_HUB_RDREQ_MCDZ__MAXBURST__SHIFT 0x3
2315 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER_MASK 0x780
2316 #define MC_HUB_RDREQ_MCDZ__LAZY_TIMER__SHIFT 0x7
2317 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS_MASK 0x3f800
2318 #define MC_HUB_RDREQ_MCDZ__ASK_CREDITS__SHIFT 0xb
2319 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS_MASK 0x1fc0000
2320 #define MC_HUB_RDREQ_MCDZ__DISPLAY_CREDITS__SHIFT 0x12
2321 #define MC_HUB_RDREQ_MCDZ__MED_CREDITS_MASK 0xfe000000
2322 #define MC_HUB_RDREQ_MCDZ__MED_CREDITS__SHIFT 0x19
2323 #define MC_HUB_RDREQ_SIP__ASK_CREDITS_MASK 0x7f
2324 #define MC_HUB_RDREQ_SIP__ASK_CREDITS__SHIFT 0x0
2325 #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL_MASK 0x80
2326 #define MC_HUB_RDREQ_SIP__MED_CREDIT_SEL__SHIFT 0x7
2327 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS_MASK 0x7f00
2328 #define MC_HUB_RDREQ_SIP__DISPLAY_CREDITS__SHIFT 0x8
2329 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_MASK 0xff
2330 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD__SHIFT 0x0
2331 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI_MASK 0xff00
2332 #define MC_HUB_RDREQ_GBL0__STALL_THRESHOLD_PRI__SHIFT 0x8
2333 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_MASK 0xff
2334 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD__SHIFT 0x0
2335 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI_MASK 0xff00
2336 #define MC_HUB_RDREQ_GBL1__STALL_THRESHOLD_PRI__SHIFT 0x8
2337 #define MC_HUB_RDREQ_SMU__ENABLE_MASK 0x1
2338 #define MC_HUB_RDREQ_SMU__ENABLE__SHIFT 0x0
2339 #define MC_HUB_RDREQ_SMU__PRESCALE_MASK 0x6
2340 #define MC_HUB_RDREQ_SMU__PRESCALE__SHIFT 0x1
2341 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT_MASK 0x8
2342 #define MC_HUB_RDREQ_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2343 #define MC_HUB_RDREQ_SMU__STALL_MODE_MASK 0x30
2344 #define MC_HUB_RDREQ_SMU__STALL_MODE__SHIFT 0x4
2345 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_MASK 0x40
2346 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE__SHIFT 0x6
2347 #define MC_HUB_RDREQ_SMU__MAXBURST_MASK 0x780
2348 #define MC_HUB_RDREQ_SMU__MAXBURST__SHIFT 0x7
2349 #define MC_HUB_RDREQ_SMU__LAZY_TIMER_MASK 0x7800
2350 #define MC_HUB_RDREQ_SMU__LAZY_TIMER__SHIFT 0xb
2351 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2352 #define MC_HUB_RDREQ_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2353 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2354 #define MC_HUB_RDREQ_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2355 #define MC_HUB_RDREQ_SDMA0__ENABLE_MASK 0x1
2356 #define MC_HUB_RDREQ_SDMA0__ENABLE__SHIFT 0x0
2357 #define MC_HUB_RDREQ_SDMA0__PRESCALE_MASK 0x6
2358 #define MC_HUB_RDREQ_SDMA0__PRESCALE__SHIFT 0x1
2359 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2360 #define MC_HUB_RDREQ_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2361 #define MC_HUB_RDREQ_SDMA0__STALL_MODE_MASK 0x30
2362 #define MC_HUB_RDREQ_SDMA0__STALL_MODE__SHIFT 0x4
2363 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_MASK 0x40
2364 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2365 #define MC_HUB_RDREQ_SDMA0__MAXBURST_MASK 0x780
2366 #define MC_HUB_RDREQ_SDMA0__MAXBURST__SHIFT 0x7
2367 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER_MASK 0x7800
2368 #define MC_HUB_RDREQ_SDMA0__LAZY_TIMER__SHIFT 0xb
2369 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2370 #define MC_HUB_RDREQ_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2371 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2372 #define MC_HUB_RDREQ_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2373 #define MC_HUB_RDREQ_HDP__ENABLE_MASK 0x1
2374 #define MC_HUB_RDREQ_HDP__ENABLE__SHIFT 0x0
2375 #define MC_HUB_RDREQ_HDP__PRESCALE_MASK 0x6
2376 #define MC_HUB_RDREQ_HDP__PRESCALE__SHIFT 0x1
2377 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT_MASK 0x8
2378 #define MC_HUB_RDREQ_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2379 #define MC_HUB_RDREQ_HDP__STALL_MODE_MASK 0x30
2380 #define MC_HUB_RDREQ_HDP__STALL_MODE__SHIFT 0x4
2381 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_MASK 0x40
2382 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE__SHIFT 0x6
2383 #define MC_HUB_RDREQ_HDP__MAXBURST_MASK 0x780
2384 #define MC_HUB_RDREQ_HDP__MAXBURST__SHIFT 0x7
2385 #define MC_HUB_RDREQ_HDP__LAZY_TIMER_MASK 0x7800
2386 #define MC_HUB_RDREQ_HDP__LAZY_TIMER__SHIFT 0xb
2387 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2388 #define MC_HUB_RDREQ_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2389 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2390 #define MC_HUB_RDREQ_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2391 #define MC_HUB_RDREQ_SDMA1__ENABLE_MASK 0x1
2392 #define MC_HUB_RDREQ_SDMA1__ENABLE__SHIFT 0x0
2393 #define MC_HUB_RDREQ_SDMA1__PRESCALE_MASK 0x6
2394 #define MC_HUB_RDREQ_SDMA1__PRESCALE__SHIFT 0x1
2395 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2396 #define MC_HUB_RDREQ_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2397 #define MC_HUB_RDREQ_SDMA1__STALL_MODE_MASK 0x30
2398 #define MC_HUB_RDREQ_SDMA1__STALL_MODE__SHIFT 0x4
2399 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_MASK 0x40
2400 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2401 #define MC_HUB_RDREQ_SDMA1__MAXBURST_MASK 0x780
2402 #define MC_HUB_RDREQ_SDMA1__MAXBURST__SHIFT 0x7
2403 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER_MASK 0x7800
2404 #define MC_HUB_RDREQ_SDMA1__LAZY_TIMER__SHIFT 0xb
2405 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2406 #define MC_HUB_RDREQ_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2407 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2408 #define MC_HUB_RDREQ_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2409 #define MC_HUB_RDREQ_RLC__ENABLE_MASK 0x1
2410 #define MC_HUB_RDREQ_RLC__ENABLE__SHIFT 0x0
2411 #define MC_HUB_RDREQ_RLC__PRESCALE_MASK 0x6
2412 #define MC_HUB_RDREQ_RLC__PRESCALE__SHIFT 0x1
2413 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT_MASK 0x8
2414 #define MC_HUB_RDREQ_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2415 #define MC_HUB_RDREQ_RLC__STALL_MODE_MASK 0x30
2416 #define MC_HUB_RDREQ_RLC__STALL_MODE__SHIFT 0x4
2417 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_MASK 0x40
2418 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE__SHIFT 0x6
2419 #define MC_HUB_RDREQ_RLC__MAXBURST_MASK 0x780
2420 #define MC_HUB_RDREQ_RLC__MAXBURST__SHIFT 0x7
2421 #define MC_HUB_RDREQ_RLC__LAZY_TIMER_MASK 0x7800
2422 #define MC_HUB_RDREQ_RLC__LAZY_TIMER__SHIFT 0xb
2423 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2424 #define MC_HUB_RDREQ_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2425 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2426 #define MC_HUB_RDREQ_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2427 #define MC_HUB_RDREQ_SEM__ENABLE_MASK 0x1
2428 #define MC_HUB_RDREQ_SEM__ENABLE__SHIFT 0x0
2429 #define MC_HUB_RDREQ_SEM__PRESCALE_MASK 0x6
2430 #define MC_HUB_RDREQ_SEM__PRESCALE__SHIFT 0x1
2431 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT_MASK 0x8
2432 #define MC_HUB_RDREQ_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2433 #define MC_HUB_RDREQ_SEM__STALL_MODE_MASK 0x30
2434 #define MC_HUB_RDREQ_SEM__STALL_MODE__SHIFT 0x4
2435 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_MASK 0x40
2436 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE__SHIFT 0x6
2437 #define MC_HUB_RDREQ_SEM__MAXBURST_MASK 0x780
2438 #define MC_HUB_RDREQ_SEM__MAXBURST__SHIFT 0x7
2439 #define MC_HUB_RDREQ_SEM__LAZY_TIMER_MASK 0x7800
2440 #define MC_HUB_RDREQ_SEM__LAZY_TIMER__SHIFT 0xb
2441 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2442 #define MC_HUB_RDREQ_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2443 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2444 #define MC_HUB_RDREQ_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2445 #define MC_HUB_RDREQ_VCE0__ENABLE_MASK 0x1
2446 #define MC_HUB_RDREQ_VCE0__ENABLE__SHIFT 0x0
2447 #define MC_HUB_RDREQ_VCE0__PRESCALE_MASK 0x6
2448 #define MC_HUB_RDREQ_VCE0__PRESCALE__SHIFT 0x1
2449 #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT_MASK 0x8
2450 #define MC_HUB_RDREQ_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
2451 #define MC_HUB_RDREQ_VCE0__STALL_MODE_MASK 0x30
2452 #define MC_HUB_RDREQ_VCE0__STALL_MODE__SHIFT 0x4
2453 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_MASK 0x40
2454 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE__SHIFT 0x6
2455 #define MC_HUB_RDREQ_VCE0__MAXBURST_MASK 0x780
2456 #define MC_HUB_RDREQ_VCE0__MAXBURST__SHIFT 0x7
2457 #define MC_HUB_RDREQ_VCE0__LAZY_TIMER_MASK 0x7800
2458 #define MC_HUB_RDREQ_VCE0__LAZY_TIMER__SHIFT 0xb
2459 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
2460 #define MC_HUB_RDREQ_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
2461 #define MC_HUB_RDREQ_VCE0__VM_BYPASS_MASK 0x10000
2462 #define MC_HUB_RDREQ_VCE0__VM_BYPASS__SHIFT 0x10
2463 #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2464 #define MC_HUB_RDREQ_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2465 #define MC_HUB_RDREQ_UMC__ENABLE_MASK 0x1
2466 #define MC_HUB_RDREQ_UMC__ENABLE__SHIFT 0x0
2467 #define MC_HUB_RDREQ_UMC__PRESCALE_MASK 0x6
2468 #define MC_HUB_RDREQ_UMC__PRESCALE__SHIFT 0x1
2469 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT_MASK 0x8
2470 #define MC_HUB_RDREQ_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2471 #define MC_HUB_RDREQ_UMC__STALL_MODE_MASK 0x30
2472 #define MC_HUB_RDREQ_UMC__STALL_MODE__SHIFT 0x4
2473 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_MASK 0x40
2474 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE__SHIFT 0x6
2475 #define MC_HUB_RDREQ_UMC__MAXBURST_MASK 0x780
2476 #define MC_HUB_RDREQ_UMC__MAXBURST__SHIFT 0x7
2477 #define MC_HUB_RDREQ_UMC__LAZY_TIMER_MASK 0x7800
2478 #define MC_HUB_RDREQ_UMC__LAZY_TIMER__SHIFT 0xb
2479 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2480 #define MC_HUB_RDREQ_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2481 #define MC_HUB_RDREQ_UMC__VM_BYPASS_MASK 0x10000
2482 #define MC_HUB_RDREQ_UMC__VM_BYPASS__SHIFT 0x10
2483 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2484 #define MC_HUB_RDREQ_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2485 #define MC_HUB_RDREQ_UVD__ENABLE_MASK 0x1
2486 #define MC_HUB_RDREQ_UVD__ENABLE__SHIFT 0x0
2487 #define MC_HUB_RDREQ_UVD__PRESCALE_MASK 0x6
2488 #define MC_HUB_RDREQ_UVD__PRESCALE__SHIFT 0x1
2489 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT_MASK 0x8
2490 #define MC_HUB_RDREQ_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2491 #define MC_HUB_RDREQ_UVD__STALL_MODE_MASK 0x30
2492 #define MC_HUB_RDREQ_UVD__STALL_MODE__SHIFT 0x4
2493 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_MASK 0x40
2494 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE__SHIFT 0x6
2495 #define MC_HUB_RDREQ_UVD__MAXBURST_MASK 0x780
2496 #define MC_HUB_RDREQ_UVD__MAXBURST__SHIFT 0x7
2497 #define MC_HUB_RDREQ_UVD__LAZY_TIMER_MASK 0x7800
2498 #define MC_HUB_RDREQ_UVD__LAZY_TIMER__SHIFT 0xb
2499 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2500 #define MC_HUB_RDREQ_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2501 #define MC_HUB_RDREQ_UVD__VM_BYPASS_MASK 0x10000
2502 #define MC_HUB_RDREQ_UVD__VM_BYPASS__SHIFT 0x10
2503 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2504 #define MC_HUB_RDREQ_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2505 #define MC_HUB_RDREQ_TLS__ENABLE_MASK 0x1
2506 #define MC_HUB_RDREQ_TLS__ENABLE__SHIFT 0x0
2507 #define MC_HUB_RDREQ_TLS__PRESCALE_MASK 0x6
2508 #define MC_HUB_RDREQ_TLS__PRESCALE__SHIFT 0x1
2509 #define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT_MASK 0x8
2510 #define MC_HUB_RDREQ_TLS__BLACKOUT_EXEMPT__SHIFT 0x3
2511 #define MC_HUB_RDREQ_TLS__STALL_MODE_MASK 0x30
2512 #define MC_HUB_RDREQ_TLS__STALL_MODE__SHIFT 0x4
2513 #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_MASK 0x40
2514 #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE__SHIFT 0x6
2515 #define MC_HUB_RDREQ_TLS__MAXBURST_MASK 0x780
2516 #define MC_HUB_RDREQ_TLS__MAXBURST__SHIFT 0x7
2517 #define MC_HUB_RDREQ_TLS__LAZY_TIMER_MASK 0x7800
2518 #define MC_HUB_RDREQ_TLS__LAZY_TIMER__SHIFT 0xb
2519 #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM_MASK 0x8000
2520 #define MC_HUB_RDREQ_TLS__STALL_OVERRIDE_WTM__SHIFT 0xf
2521 #define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2522 #define MC_HUB_RDREQ_TLS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2523 #define MC_HUB_RDREQ_DMIF__ENABLE_MASK 0x1
2524 #define MC_HUB_RDREQ_DMIF__ENABLE__SHIFT 0x0
2525 #define MC_HUB_RDREQ_DMIF__PRESCALE_MASK 0x6
2526 #define MC_HUB_RDREQ_DMIF__PRESCALE__SHIFT 0x1
2527 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT_MASK 0x8
2528 #define MC_HUB_RDREQ_DMIF__BLACKOUT_EXEMPT__SHIFT 0x3
2529 #define MC_HUB_RDREQ_DMIF__STALL_MODE_MASK 0x30
2530 #define MC_HUB_RDREQ_DMIF__STALL_MODE__SHIFT 0x4
2531 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_MASK 0x40
2532 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE__SHIFT 0x6
2533 #define MC_HUB_RDREQ_DMIF__MAXBURST_MASK 0x780
2534 #define MC_HUB_RDREQ_DMIF__MAXBURST__SHIFT 0x7
2535 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER_MASK 0x7800
2536 #define MC_HUB_RDREQ_DMIF__LAZY_TIMER__SHIFT 0xb
2537 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM_MASK 0x8000
2538 #define MC_HUB_RDREQ_DMIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2539 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2540 #define MC_HUB_RDREQ_DMIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2541 #define MC_HUB_RDREQ_MCIF__ENABLE_MASK 0x1
2542 #define MC_HUB_RDREQ_MCIF__ENABLE__SHIFT 0x0
2543 #define MC_HUB_RDREQ_MCIF__PRESCALE_MASK 0x6
2544 #define MC_HUB_RDREQ_MCIF__PRESCALE__SHIFT 0x1
2545 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2546 #define MC_HUB_RDREQ_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2547 #define MC_HUB_RDREQ_MCIF__STALL_MODE_MASK 0x30
2548 #define MC_HUB_RDREQ_MCIF__STALL_MODE__SHIFT 0x4
2549 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_MASK 0x40
2550 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE__SHIFT 0x6
2551 #define MC_HUB_RDREQ_MCIF__MAXBURST_MASK 0x780
2552 #define MC_HUB_RDREQ_MCIF__MAXBURST__SHIFT 0x7
2553 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER_MASK 0x7800
2554 #define MC_HUB_RDREQ_MCIF__LAZY_TIMER__SHIFT 0xb
2555 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2556 #define MC_HUB_RDREQ_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2557 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2558 #define MC_HUB_RDREQ_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2559 #define MC_HUB_RDREQ_VMC__ENABLE_MASK 0x1
2560 #define MC_HUB_RDREQ_VMC__ENABLE__SHIFT 0x0
2561 #define MC_HUB_RDREQ_VMC__PRESCALE_MASK 0x6
2562 #define MC_HUB_RDREQ_VMC__PRESCALE__SHIFT 0x1
2563 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT_MASK 0x8
2564 #define MC_HUB_RDREQ_VMC__BLACKOUT_EXEMPT__SHIFT 0x3
2565 #define MC_HUB_RDREQ_VMC__STALL_MODE_MASK 0x30
2566 #define MC_HUB_RDREQ_VMC__STALL_MODE__SHIFT 0x4
2567 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_MASK 0x40
2568 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE__SHIFT 0x6
2569 #define MC_HUB_RDREQ_VMC__MAXBURST_MASK 0x780
2570 #define MC_HUB_RDREQ_VMC__MAXBURST__SHIFT 0x7
2571 #define MC_HUB_RDREQ_VMC__LAZY_TIMER_MASK 0x7800
2572 #define MC_HUB_RDREQ_VMC__LAZY_TIMER__SHIFT 0xb
2573 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM_MASK 0x8000
2574 #define MC_HUB_RDREQ_VMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2575 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2576 #define MC_HUB_RDREQ_VMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2577 #define MC_HUB_RDREQ_VCEU0__ENABLE_MASK 0x1
2578 #define MC_HUB_RDREQ_VCEU0__ENABLE__SHIFT 0x0
2579 #define MC_HUB_RDREQ_VCEU0__PRESCALE_MASK 0x6
2580 #define MC_HUB_RDREQ_VCEU0__PRESCALE__SHIFT 0x1
2581 #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
2582 #define MC_HUB_RDREQ_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
2583 #define MC_HUB_RDREQ_VCEU0__STALL_MODE_MASK 0x30
2584 #define MC_HUB_RDREQ_VCEU0__STALL_MODE__SHIFT 0x4
2585 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_MASK 0x40
2586 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE__SHIFT 0x6
2587 #define MC_HUB_RDREQ_VCEU0__MAXBURST_MASK 0x780
2588 #define MC_HUB_RDREQ_VCEU0__MAXBURST__SHIFT 0x7
2589 #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER_MASK 0x7800
2590 #define MC_HUB_RDREQ_VCEU0__LAZY_TIMER__SHIFT 0xb
2591 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
2592 #define MC_HUB_RDREQ_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
2593 #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2594 #define MC_HUB_RDREQ_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2595 #define MC_HUB_WDP_MCDW__ENABLE_MASK 0x1
2596 #define MC_HUB_WDP_MCDW__ENABLE__SHIFT 0x0
2597 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT_MASK 0x2
2598 #define MC_HUB_WDP_MCDW__BLACKOUT_EXEMPT__SHIFT 0x1
2599 #define MC_HUB_WDP_MCDW__STALL_MODE_MASK 0x4
2600 #define MC_HUB_WDP_MCDW__STALL_MODE__SHIFT 0x2
2601 #define MC_HUB_WDP_MCDW__MAXBURST_MASK 0x78
2602 #define MC_HUB_WDP_MCDW__MAXBURST__SHIFT 0x3
2603 #define MC_HUB_WDP_MCDW__ASK_CREDITS_MASK 0x1f80
2604 #define MC_HUB_WDP_MCDW__ASK_CREDITS__SHIFT 0x7
2605 #define MC_HUB_WDP_MCDW__LAZY_TIMER_MASK 0x1e000
2606 #define MC_HUB_WDP_MCDW__LAZY_TIMER__SHIFT 0xd
2607 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD_MASK 0xfe0000
2608 #define MC_HUB_WDP_MCDW__STALL_THRESHOLD__SHIFT 0x11
2609 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W_MASK 0x7f000000
2610 #define MC_HUB_WDP_MCDW__ASK_CREDITS_W__SHIFT 0x18
2611 #define MC_HUB_WDP_MCDX__ENABLE_MASK 0x1
2612 #define MC_HUB_WDP_MCDX__ENABLE__SHIFT 0x0
2613 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT_MASK 0x2
2614 #define MC_HUB_WDP_MCDX__BLACKOUT_EXEMPT__SHIFT 0x1
2615 #define MC_HUB_WDP_MCDX__STALL_MODE_MASK 0x4
2616 #define MC_HUB_WDP_MCDX__STALL_MODE__SHIFT 0x2
2617 #define MC_HUB_WDP_MCDX__MAXBURST_MASK 0x78
2618 #define MC_HUB_WDP_MCDX__MAXBURST__SHIFT 0x3
2619 #define MC_HUB_WDP_MCDX__ASK_CREDITS_MASK 0x1f80
2620 #define MC_HUB_WDP_MCDX__ASK_CREDITS__SHIFT 0x7
2621 #define MC_HUB_WDP_MCDX__LAZY_TIMER_MASK 0x1e000
2622 #define MC_HUB_WDP_MCDX__LAZY_TIMER__SHIFT 0xd
2623 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD_MASK 0xfe0000
2624 #define MC_HUB_WDP_MCDX__STALL_THRESHOLD__SHIFT 0x11
2625 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W_MASK 0x7f000000
2626 #define MC_HUB_WDP_MCDX__ASK_CREDITS_W__SHIFT 0x18
2627 #define MC_HUB_WDP_MCDY__ENABLE_MASK 0x1
2628 #define MC_HUB_WDP_MCDY__ENABLE__SHIFT 0x0
2629 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT_MASK 0x2
2630 #define MC_HUB_WDP_MCDY__BLACKOUT_EXEMPT__SHIFT 0x1
2631 #define MC_HUB_WDP_MCDY__STALL_MODE_MASK 0x4
2632 #define MC_HUB_WDP_MCDY__STALL_MODE__SHIFT 0x2
2633 #define MC_HUB_WDP_MCDY__MAXBURST_MASK 0x78
2634 #define MC_HUB_WDP_MCDY__MAXBURST__SHIFT 0x3
2635 #define MC_HUB_WDP_MCDY__ASK_CREDITS_MASK 0x1f80
2636 #define MC_HUB_WDP_MCDY__ASK_CREDITS__SHIFT 0x7
2637 #define MC_HUB_WDP_MCDY__LAZY_TIMER_MASK 0x1e000
2638 #define MC_HUB_WDP_MCDY__LAZY_TIMER__SHIFT 0xd
2639 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD_MASK 0xfe0000
2640 #define MC_HUB_WDP_MCDY__STALL_THRESHOLD__SHIFT 0x11
2641 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W_MASK 0x7f000000
2642 #define MC_HUB_WDP_MCDY__ASK_CREDITS_W__SHIFT 0x18
2643 #define MC_HUB_WDP_MCDZ__ENABLE_MASK 0x1
2644 #define MC_HUB_WDP_MCDZ__ENABLE__SHIFT 0x0
2645 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT_MASK 0x2
2646 #define MC_HUB_WDP_MCDZ__BLACKOUT_EXEMPT__SHIFT 0x1
2647 #define MC_HUB_WDP_MCDZ__STALL_MODE_MASK 0x4
2648 #define MC_HUB_WDP_MCDZ__STALL_MODE__SHIFT 0x2
2649 #define MC_HUB_WDP_MCDZ__MAXBURST_MASK 0x78
2650 #define MC_HUB_WDP_MCDZ__MAXBURST__SHIFT 0x3
2651 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_MASK 0x1f80
2652 #define MC_HUB_WDP_MCDZ__ASK_CREDITS__SHIFT 0x7
2653 #define MC_HUB_WDP_MCDZ__LAZY_TIMER_MASK 0x1e000
2654 #define MC_HUB_WDP_MCDZ__LAZY_TIMER__SHIFT 0xd
2655 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD_MASK 0xfe0000
2656 #define MC_HUB_WDP_MCDZ__STALL_THRESHOLD__SHIFT 0x11
2657 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W_MASK 0x7f000000
2658 #define MC_HUB_WDP_MCDZ__ASK_CREDITS_W__SHIFT 0x18
2659 #define MC_HUB_WDP_SIP__STALL_MODE_MASK 0x3
2660 #define MC_HUB_WDP_SIP__STALL_MODE__SHIFT 0x0
2661 #define MC_HUB_WDP_SIP__ASK_CREDITS_MASK 0x1fc
2662 #define MC_HUB_WDP_SIP__ASK_CREDITS__SHIFT 0x2
2663 #define MC_HUB_WDP_SDMA1__ENABLE_MASK 0x1
2664 #define MC_HUB_WDP_SDMA1__ENABLE__SHIFT 0x0
2665 #define MC_HUB_WDP_SDMA1__PRESCALE_MASK 0x6
2666 #define MC_HUB_WDP_SDMA1__PRESCALE__SHIFT 0x1
2667 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT_MASK 0x8
2668 #define MC_HUB_WDP_SDMA1__BLACKOUT_EXEMPT__SHIFT 0x3
2669 #define MC_HUB_WDP_SDMA1__STALL_MODE_MASK 0x30
2670 #define MC_HUB_WDP_SDMA1__STALL_MODE__SHIFT 0x4
2671 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_MASK 0x40
2672 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE__SHIFT 0x6
2673 #define MC_HUB_WDP_SDMA1__MAXBURST_MASK 0x780
2674 #define MC_HUB_WDP_SDMA1__MAXBURST__SHIFT 0x7
2675 #define MC_HUB_WDP_SDMA1__LAZY_TIMER_MASK 0x7800
2676 #define MC_HUB_WDP_SDMA1__LAZY_TIMER__SHIFT 0xb
2677 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM_MASK 0x8000
2678 #define MC_HUB_WDP_SDMA1__STALL_OVERRIDE_WTM__SHIFT 0xf
2679 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2680 #define MC_HUB_WDP_SDMA1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2681 #define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2682 #define MC_HUB_WDP_SDMA1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2683 #define MC_HUB_WDP_SH0__ENABLE_MASK 0x1
2684 #define MC_HUB_WDP_SH0__ENABLE__SHIFT 0x0
2685 #define MC_HUB_WDP_SH0__PRESCALE_MASK 0x6
2686 #define MC_HUB_WDP_SH0__PRESCALE__SHIFT 0x1
2687 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT_MASK 0x8
2688 #define MC_HUB_WDP_SH0__BLACKOUT_EXEMPT__SHIFT 0x3
2689 #define MC_HUB_WDP_SH0__STALL_MODE_MASK 0x30
2690 #define MC_HUB_WDP_SH0__STALL_MODE__SHIFT 0x4
2691 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_MASK 0x40
2692 #define MC_HUB_WDP_SH0__STALL_OVERRIDE__SHIFT 0x6
2693 #define MC_HUB_WDP_SH0__MAXBURST_MASK 0x780
2694 #define MC_HUB_WDP_SH0__MAXBURST__SHIFT 0x7
2695 #define MC_HUB_WDP_SH0__LAZY_TIMER_MASK 0x7800
2696 #define MC_HUB_WDP_SH0__LAZY_TIMER__SHIFT 0xb
2697 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM_MASK 0x8000
2698 #define MC_HUB_WDP_SH0__STALL_OVERRIDE_WTM__SHIFT 0xf
2699 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2700 #define MC_HUB_WDP_SH0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2701 #define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2702 #define MC_HUB_WDP_SH0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2703 #define MC_HUB_WDP_MCIF__ENABLE_MASK 0x1
2704 #define MC_HUB_WDP_MCIF__ENABLE__SHIFT 0x0
2705 #define MC_HUB_WDP_MCIF__PRESCALE_MASK 0x6
2706 #define MC_HUB_WDP_MCIF__PRESCALE__SHIFT 0x1
2707 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT_MASK 0x8
2708 #define MC_HUB_WDP_MCIF__BLACKOUT_EXEMPT__SHIFT 0x3
2709 #define MC_HUB_WDP_MCIF__STALL_MODE_MASK 0x30
2710 #define MC_HUB_WDP_MCIF__STALL_MODE__SHIFT 0x4
2711 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_MASK 0x40
2712 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE__SHIFT 0x6
2713 #define MC_HUB_WDP_MCIF__MAXBURST_MASK 0x780
2714 #define MC_HUB_WDP_MCIF__MAXBURST__SHIFT 0x7
2715 #define MC_HUB_WDP_MCIF__LAZY_TIMER_MASK 0x7800
2716 #define MC_HUB_WDP_MCIF__LAZY_TIMER__SHIFT 0xb
2717 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM_MASK 0x8000
2718 #define MC_HUB_WDP_MCIF__STALL_OVERRIDE_WTM__SHIFT 0xf
2719 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2720 #define MC_HUB_WDP_MCIF__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2721 #define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2722 #define MC_HUB_WDP_MCIF__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2723 #define MC_HUB_WDP_VCE0__ENABLE_MASK 0x1
2724 #define MC_HUB_WDP_VCE0__ENABLE__SHIFT 0x0
2725 #define MC_HUB_WDP_VCE0__PRESCALE_MASK 0x6
2726 #define MC_HUB_WDP_VCE0__PRESCALE__SHIFT 0x1
2727 #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT_MASK 0x8
2728 #define MC_HUB_WDP_VCE0__BLACKOUT_EXEMPT__SHIFT 0x3
2729 #define MC_HUB_WDP_VCE0__STALL_MODE_MASK 0x30
2730 #define MC_HUB_WDP_VCE0__STALL_MODE__SHIFT 0x4
2731 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_MASK 0x40
2732 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE__SHIFT 0x6
2733 #define MC_HUB_WDP_VCE0__MAXBURST_MASK 0x780
2734 #define MC_HUB_WDP_VCE0__MAXBURST__SHIFT 0x7
2735 #define MC_HUB_WDP_VCE0__LAZY_TIMER_MASK 0x7800
2736 #define MC_HUB_WDP_VCE0__LAZY_TIMER__SHIFT 0xb
2737 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM_MASK 0x8000
2738 #define MC_HUB_WDP_VCE0__STALL_OVERRIDE_WTM__SHIFT 0xf
2739 #define MC_HUB_WDP_VCE0__VM_BYPASS_MASK 0x10000
2740 #define MC_HUB_WDP_VCE0__VM_BYPASS__SHIFT 0x10
2741 #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2742 #define MC_HUB_WDP_VCE0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2743 #define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
2744 #define MC_HUB_WDP_VCE0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
2745 #define MC_HUB_WDP_XDP__ENABLE_MASK 0x1
2746 #define MC_HUB_WDP_XDP__ENABLE__SHIFT 0x0
2747 #define MC_HUB_WDP_XDP__PRESCALE_MASK 0x6
2748 #define MC_HUB_WDP_XDP__PRESCALE__SHIFT 0x1
2749 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT_MASK 0x8
2750 #define MC_HUB_WDP_XDP__BLACKOUT_EXEMPT__SHIFT 0x3
2751 #define MC_HUB_WDP_XDP__STALL_MODE_MASK 0x30
2752 #define MC_HUB_WDP_XDP__STALL_MODE__SHIFT 0x4
2753 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_MASK 0x40
2754 #define MC_HUB_WDP_XDP__STALL_OVERRIDE__SHIFT 0x6
2755 #define MC_HUB_WDP_XDP__MAXBURST_MASK 0x780
2756 #define MC_HUB_WDP_XDP__MAXBURST__SHIFT 0x7
2757 #define MC_HUB_WDP_XDP__LAZY_TIMER_MASK 0x7800
2758 #define MC_HUB_WDP_XDP__LAZY_TIMER__SHIFT 0xb
2759 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM_MASK 0x8000
2760 #define MC_HUB_WDP_XDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2761 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2762 #define MC_HUB_WDP_XDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2763 #define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2764 #define MC_HUB_WDP_XDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2765 #define MC_HUB_WDP_IH__ENABLE_MASK 0x1
2766 #define MC_HUB_WDP_IH__ENABLE__SHIFT 0x0
2767 #define MC_HUB_WDP_IH__PRESCALE_MASK 0x6
2768 #define MC_HUB_WDP_IH__PRESCALE__SHIFT 0x1
2769 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT_MASK 0x8
2770 #define MC_HUB_WDP_IH__BLACKOUT_EXEMPT__SHIFT 0x3
2771 #define MC_HUB_WDP_IH__STALL_MODE_MASK 0x30
2772 #define MC_HUB_WDP_IH__STALL_MODE__SHIFT 0x4
2773 #define MC_HUB_WDP_IH__STALL_OVERRIDE_MASK 0x40
2774 #define MC_HUB_WDP_IH__STALL_OVERRIDE__SHIFT 0x6
2775 #define MC_HUB_WDP_IH__MAXBURST_MASK 0x780
2776 #define MC_HUB_WDP_IH__MAXBURST__SHIFT 0x7
2777 #define MC_HUB_WDP_IH__LAZY_TIMER_MASK 0x7800
2778 #define MC_HUB_WDP_IH__LAZY_TIMER__SHIFT 0xb
2779 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM_MASK 0x8000
2780 #define MC_HUB_WDP_IH__STALL_OVERRIDE_WTM__SHIFT 0xf
2781 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2782 #define MC_HUB_WDP_IH__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2783 #define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2784 #define MC_HUB_WDP_IH__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2785 #define MC_HUB_WDP_RLC__ENABLE_MASK 0x1
2786 #define MC_HUB_WDP_RLC__ENABLE__SHIFT 0x0
2787 #define MC_HUB_WDP_RLC__PRESCALE_MASK 0x6
2788 #define MC_HUB_WDP_RLC__PRESCALE__SHIFT 0x1
2789 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT_MASK 0x8
2790 #define MC_HUB_WDP_RLC__BLACKOUT_EXEMPT__SHIFT 0x3
2791 #define MC_HUB_WDP_RLC__STALL_MODE_MASK 0x30
2792 #define MC_HUB_WDP_RLC__STALL_MODE__SHIFT 0x4
2793 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_MASK 0x40
2794 #define MC_HUB_WDP_RLC__STALL_OVERRIDE__SHIFT 0x6
2795 #define MC_HUB_WDP_RLC__MAXBURST_MASK 0x780
2796 #define MC_HUB_WDP_RLC__MAXBURST__SHIFT 0x7
2797 #define MC_HUB_WDP_RLC__LAZY_TIMER_MASK 0x7800
2798 #define MC_HUB_WDP_RLC__LAZY_TIMER__SHIFT 0xb
2799 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM_MASK 0x8000
2800 #define MC_HUB_WDP_RLC__STALL_OVERRIDE_WTM__SHIFT 0xf
2801 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2802 #define MC_HUB_WDP_RLC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2803 #define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2804 #define MC_HUB_WDP_RLC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2805 #define MC_HUB_WDP_SEM__ENABLE_MASK 0x1
2806 #define MC_HUB_WDP_SEM__ENABLE__SHIFT 0x0
2807 #define MC_HUB_WDP_SEM__PRESCALE_MASK 0x6
2808 #define MC_HUB_WDP_SEM__PRESCALE__SHIFT 0x1
2809 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT_MASK 0x8
2810 #define MC_HUB_WDP_SEM__BLACKOUT_EXEMPT__SHIFT 0x3
2811 #define MC_HUB_WDP_SEM__STALL_MODE_MASK 0x30
2812 #define MC_HUB_WDP_SEM__STALL_MODE__SHIFT 0x4
2813 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_MASK 0x40
2814 #define MC_HUB_WDP_SEM__STALL_OVERRIDE__SHIFT 0x6
2815 #define MC_HUB_WDP_SEM__MAXBURST_MASK 0x780
2816 #define MC_HUB_WDP_SEM__MAXBURST__SHIFT 0x7
2817 #define MC_HUB_WDP_SEM__LAZY_TIMER_MASK 0x7800
2818 #define MC_HUB_WDP_SEM__LAZY_TIMER__SHIFT 0xb
2819 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM_MASK 0x8000
2820 #define MC_HUB_WDP_SEM__STALL_OVERRIDE_WTM__SHIFT 0xf
2821 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2822 #define MC_HUB_WDP_SEM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2823 #define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2824 #define MC_HUB_WDP_SEM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2825 #define MC_HUB_WDP_SMU__ENABLE_MASK 0x1
2826 #define MC_HUB_WDP_SMU__ENABLE__SHIFT 0x0
2827 #define MC_HUB_WDP_SMU__PRESCALE_MASK 0x6
2828 #define MC_HUB_WDP_SMU__PRESCALE__SHIFT 0x1
2829 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT_MASK 0x8
2830 #define MC_HUB_WDP_SMU__BLACKOUT_EXEMPT__SHIFT 0x3
2831 #define MC_HUB_WDP_SMU__STALL_MODE_MASK 0x30
2832 #define MC_HUB_WDP_SMU__STALL_MODE__SHIFT 0x4
2833 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_MASK 0x40
2834 #define MC_HUB_WDP_SMU__STALL_OVERRIDE__SHIFT 0x6
2835 #define MC_HUB_WDP_SMU__MAXBURST_MASK 0x780
2836 #define MC_HUB_WDP_SMU__MAXBURST__SHIFT 0x7
2837 #define MC_HUB_WDP_SMU__LAZY_TIMER_MASK 0x7800
2838 #define MC_HUB_WDP_SMU__LAZY_TIMER__SHIFT 0xb
2839 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM_MASK 0x8000
2840 #define MC_HUB_WDP_SMU__STALL_OVERRIDE_WTM__SHIFT 0xf
2841 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2842 #define MC_HUB_WDP_SMU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2843 #define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2844 #define MC_HUB_WDP_SMU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2845 #define MC_HUB_WDP_SH1__ENABLE_MASK 0x1
2846 #define MC_HUB_WDP_SH1__ENABLE__SHIFT 0x0
2847 #define MC_HUB_WDP_SH1__PRESCALE_MASK 0x6
2848 #define MC_HUB_WDP_SH1__PRESCALE__SHIFT 0x1
2849 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT_MASK 0x8
2850 #define MC_HUB_WDP_SH1__BLACKOUT_EXEMPT__SHIFT 0x3
2851 #define MC_HUB_WDP_SH1__STALL_MODE_MASK 0x30
2852 #define MC_HUB_WDP_SH1__STALL_MODE__SHIFT 0x4
2853 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_MASK 0x40
2854 #define MC_HUB_WDP_SH1__STALL_OVERRIDE__SHIFT 0x6
2855 #define MC_HUB_WDP_SH1__MAXBURST_MASK 0x780
2856 #define MC_HUB_WDP_SH1__MAXBURST__SHIFT 0x7
2857 #define MC_HUB_WDP_SH1__LAZY_TIMER_MASK 0x7800
2858 #define MC_HUB_WDP_SH1__LAZY_TIMER__SHIFT 0xb
2859 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM_MASK 0x8000
2860 #define MC_HUB_WDP_SH1__STALL_OVERRIDE_WTM__SHIFT 0xf
2861 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2862 #define MC_HUB_WDP_SH1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2863 #define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2864 #define MC_HUB_WDP_SH1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2865 #define MC_HUB_WDP_UMC__ENABLE_MASK 0x1
2866 #define MC_HUB_WDP_UMC__ENABLE__SHIFT 0x0
2867 #define MC_HUB_WDP_UMC__PRESCALE_MASK 0x6
2868 #define MC_HUB_WDP_UMC__PRESCALE__SHIFT 0x1
2869 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT_MASK 0x8
2870 #define MC_HUB_WDP_UMC__BLACKOUT_EXEMPT__SHIFT 0x3
2871 #define MC_HUB_WDP_UMC__STALL_MODE_MASK 0x30
2872 #define MC_HUB_WDP_UMC__STALL_MODE__SHIFT 0x4
2873 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_MASK 0x40
2874 #define MC_HUB_WDP_UMC__STALL_OVERRIDE__SHIFT 0x6
2875 #define MC_HUB_WDP_UMC__MAXBURST_MASK 0x780
2876 #define MC_HUB_WDP_UMC__MAXBURST__SHIFT 0x7
2877 #define MC_HUB_WDP_UMC__LAZY_TIMER_MASK 0x7800
2878 #define MC_HUB_WDP_UMC__LAZY_TIMER__SHIFT 0xb
2879 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM_MASK 0x8000
2880 #define MC_HUB_WDP_UMC__STALL_OVERRIDE_WTM__SHIFT 0xf
2881 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2882 #define MC_HUB_WDP_UMC__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2883 #define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2884 #define MC_HUB_WDP_UMC__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2885 #define MC_HUB_WDP_UVD__ENABLE_MASK 0x1
2886 #define MC_HUB_WDP_UVD__ENABLE__SHIFT 0x0
2887 #define MC_HUB_WDP_UVD__PRESCALE_MASK 0x6
2888 #define MC_HUB_WDP_UVD__PRESCALE__SHIFT 0x1
2889 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT_MASK 0x8
2890 #define MC_HUB_WDP_UVD__BLACKOUT_EXEMPT__SHIFT 0x3
2891 #define MC_HUB_WDP_UVD__STALL_MODE_MASK 0x30
2892 #define MC_HUB_WDP_UVD__STALL_MODE__SHIFT 0x4
2893 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_MASK 0x40
2894 #define MC_HUB_WDP_UVD__STALL_OVERRIDE__SHIFT 0x6
2895 #define MC_HUB_WDP_UVD__MAXBURST_MASK 0x780
2896 #define MC_HUB_WDP_UVD__MAXBURST__SHIFT 0x7
2897 #define MC_HUB_WDP_UVD__LAZY_TIMER_MASK 0x7800
2898 #define MC_HUB_WDP_UVD__LAZY_TIMER__SHIFT 0xb
2899 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM_MASK 0x8000
2900 #define MC_HUB_WDP_UVD__STALL_OVERRIDE_WTM__SHIFT 0xf
2901 #define MC_HUB_WDP_UVD__VM_BYPASS_MASK 0x10000
2902 #define MC_HUB_WDP_UVD__VM_BYPASS__SHIFT 0x10
2903 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2904 #define MC_HUB_WDP_UVD__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2905 #define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
2906 #define MC_HUB_WDP_UVD__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
2907 #define MC_HUB_WDP_HDP__ENABLE_MASK 0x1
2908 #define MC_HUB_WDP_HDP__ENABLE__SHIFT 0x0
2909 #define MC_HUB_WDP_HDP__PRESCALE_MASK 0x6
2910 #define MC_HUB_WDP_HDP__PRESCALE__SHIFT 0x1
2911 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT_MASK 0x8
2912 #define MC_HUB_WDP_HDP__BLACKOUT_EXEMPT__SHIFT 0x3
2913 #define MC_HUB_WDP_HDP__STALL_MODE_MASK 0x30
2914 #define MC_HUB_WDP_HDP__STALL_MODE__SHIFT 0x4
2915 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_MASK 0x40
2916 #define MC_HUB_WDP_HDP__STALL_OVERRIDE__SHIFT 0x6
2917 #define MC_HUB_WDP_HDP__MAXBURST_MASK 0x780
2918 #define MC_HUB_WDP_HDP__MAXBURST__SHIFT 0x7
2919 #define MC_HUB_WDP_HDP__LAZY_TIMER_MASK 0x7800
2920 #define MC_HUB_WDP_HDP__LAZY_TIMER__SHIFT 0xb
2921 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM_MASK 0x8000
2922 #define MC_HUB_WDP_HDP__STALL_OVERRIDE_WTM__SHIFT 0xf
2923 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2924 #define MC_HUB_WDP_HDP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2925 #define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2926 #define MC_HUB_WDP_HDP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2927 #define MC_HUB_WDP_SDMA0__ENABLE_MASK 0x1
2928 #define MC_HUB_WDP_SDMA0__ENABLE__SHIFT 0x0
2929 #define MC_HUB_WDP_SDMA0__PRESCALE_MASK 0x6
2930 #define MC_HUB_WDP_SDMA0__PRESCALE__SHIFT 0x1
2931 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT_MASK 0x8
2932 #define MC_HUB_WDP_SDMA0__BLACKOUT_EXEMPT__SHIFT 0x3
2933 #define MC_HUB_WDP_SDMA0__STALL_MODE_MASK 0x30
2934 #define MC_HUB_WDP_SDMA0__STALL_MODE__SHIFT 0x4
2935 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_MASK 0x40
2936 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE__SHIFT 0x6
2937 #define MC_HUB_WDP_SDMA0__MAXBURST_MASK 0x780
2938 #define MC_HUB_WDP_SDMA0__MAXBURST__SHIFT 0x7
2939 #define MC_HUB_WDP_SDMA0__LAZY_TIMER_MASK 0x7800
2940 #define MC_HUB_WDP_SDMA0__LAZY_TIMER__SHIFT 0xb
2941 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM_MASK 0x8000
2942 #define MC_HUB_WDP_SDMA0__STALL_OVERRIDE_WTM__SHIFT 0xf
2943 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2944 #define MC_HUB_WDP_SDMA0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2945 #define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2946 #define MC_HUB_WDP_SDMA0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2947 #define MC_HUB_WRRET_MCDW__STALL_MODE_MASK 0x1
2948 #define MC_HUB_WRRET_MCDW__STALL_MODE__SHIFT 0x0
2949 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT_MASK 0xfe
2950 #define MC_HUB_WRRET_MCDW__CREDIT_COUNT__SHIFT 0x1
2951 #define MC_HUB_WRRET_MCDX__STALL_MODE_MASK 0x1
2952 #define MC_HUB_WRRET_MCDX__STALL_MODE__SHIFT 0x0
2953 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT_MASK 0xfe
2954 #define MC_HUB_WRRET_MCDX__CREDIT_COUNT__SHIFT 0x1
2955 #define MC_HUB_WRRET_MCDY__STALL_MODE_MASK 0x1
2956 #define MC_HUB_WRRET_MCDY__STALL_MODE__SHIFT 0x0
2957 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT_MASK 0xfe
2958 #define MC_HUB_WRRET_MCDY__CREDIT_COUNT__SHIFT 0x1
2959 #define MC_HUB_WRRET_MCDZ__STALL_MODE_MASK 0x1
2960 #define MC_HUB_WRRET_MCDZ__STALL_MODE__SHIFT 0x0
2961 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT_MASK 0xfe
2962 #define MC_HUB_WRRET_MCDZ__CREDIT_COUNT__SHIFT 0x1
2963 #define MC_HUB_WDP_VCEU0__ENABLE_MASK 0x1
2964 #define MC_HUB_WDP_VCEU0__ENABLE__SHIFT 0x0
2965 #define MC_HUB_WDP_VCEU0__PRESCALE_MASK 0x6
2966 #define MC_HUB_WDP_VCEU0__PRESCALE__SHIFT 0x1
2967 #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT_MASK 0x8
2968 #define MC_HUB_WDP_VCEU0__BLACKOUT_EXEMPT__SHIFT 0x3
2969 #define MC_HUB_WDP_VCEU0__STALL_MODE_MASK 0x30
2970 #define MC_HUB_WDP_VCEU0__STALL_MODE__SHIFT 0x4
2971 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_MASK 0x40
2972 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE__SHIFT 0x6
2973 #define MC_HUB_WDP_VCEU0__MAXBURST_MASK 0x780
2974 #define MC_HUB_WDP_VCEU0__MAXBURST__SHIFT 0x7
2975 #define MC_HUB_WDP_VCEU0__LAZY_TIMER_MASK 0x7800
2976 #define MC_HUB_WDP_VCEU0__LAZY_TIMER__SHIFT 0xb
2977 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM_MASK 0x8000
2978 #define MC_HUB_WDP_VCEU0__STALL_OVERRIDE_WTM__SHIFT 0xf
2979 #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
2980 #define MC_HUB_WDP_VCEU0__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
2981 #define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
2982 #define MC_HUB_WDP_VCEU0__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
2983 #define MC_HUB_WDP_XDMAM__ENABLE_MASK 0x1
2984 #define MC_HUB_WDP_XDMAM__ENABLE__SHIFT 0x0
2985 #define MC_HUB_WDP_XDMAM__PRESCALE_MASK 0x6
2986 #define MC_HUB_WDP_XDMAM__PRESCALE__SHIFT 0x1
2987 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
2988 #define MC_HUB_WDP_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
2989 #define MC_HUB_WDP_XDMAM__STALL_MODE_MASK 0x30
2990 #define MC_HUB_WDP_XDMAM__STALL_MODE__SHIFT 0x4
2991 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_MASK 0x40
2992 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE__SHIFT 0x6
2993 #define MC_HUB_WDP_XDMAM__MAXBURST_MASK 0x780
2994 #define MC_HUB_WDP_XDMAM__MAXBURST__SHIFT 0x7
2995 #define MC_HUB_WDP_XDMAM__LAZY_TIMER_MASK 0x7800
2996 #define MC_HUB_WDP_XDMAM__LAZY_TIMER__SHIFT 0xb
2997 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
2998 #define MC_HUB_WDP_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
2999 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3000 #define MC_HUB_WDP_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3001 #define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3002 #define MC_HUB_WDP_XDMAM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3003 #define MC_HUB_WDP_XDMA__ENABLE_MASK 0x1
3004 #define MC_HUB_WDP_XDMA__ENABLE__SHIFT 0x0
3005 #define MC_HUB_WDP_XDMA__PRESCALE_MASK 0x6
3006 #define MC_HUB_WDP_XDMA__PRESCALE__SHIFT 0x1
3007 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT_MASK 0x8
3008 #define MC_HUB_WDP_XDMA__BLACKOUT_EXEMPT__SHIFT 0x3
3009 #define MC_HUB_WDP_XDMA__STALL_MODE_MASK 0x30
3010 #define MC_HUB_WDP_XDMA__STALL_MODE__SHIFT 0x4
3011 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_MASK 0x40
3012 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE__SHIFT 0x6
3013 #define MC_HUB_WDP_XDMA__MAXBURST_MASK 0x780
3014 #define MC_HUB_WDP_XDMA__MAXBURST__SHIFT 0x7
3015 #define MC_HUB_WDP_XDMA__LAZY_TIMER_MASK 0x7800
3016 #define MC_HUB_WDP_XDMA__LAZY_TIMER__SHIFT 0xb
3017 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM_MASK 0x8000
3018 #define MC_HUB_WDP_XDMA__STALL_OVERRIDE_WTM__SHIFT 0xf
3019 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3020 #define MC_HUB_WDP_XDMA__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3021 #define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3022 #define MC_HUB_WDP_XDMA__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3023 #define MC_HUB_RDREQ_XDMAM__ENABLE_MASK 0x1
3024 #define MC_HUB_RDREQ_XDMAM__ENABLE__SHIFT 0x0
3025 #define MC_HUB_RDREQ_XDMAM__PRESCALE_MASK 0x6
3026 #define MC_HUB_RDREQ_XDMAM__PRESCALE__SHIFT 0x1
3027 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT_MASK 0x8
3028 #define MC_HUB_RDREQ_XDMAM__BLACKOUT_EXEMPT__SHIFT 0x3
3029 #define MC_HUB_RDREQ_XDMAM__STALL_MODE_MASK 0x30
3030 #define MC_HUB_RDREQ_XDMAM__STALL_MODE__SHIFT 0x4
3031 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_MASK 0x40
3032 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE__SHIFT 0x6
3033 #define MC_HUB_RDREQ_XDMAM__MAXBURST_MASK 0x780
3034 #define MC_HUB_RDREQ_XDMAM__MAXBURST__SHIFT 0x7
3035 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER_MASK 0x7800
3036 #define MC_HUB_RDREQ_XDMAM__LAZY_TIMER__SHIFT 0xb
3037 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM_MASK 0x8000
3038 #define MC_HUB_RDREQ_XDMAM__STALL_OVERRIDE_WTM__SHIFT 0xf
3039 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3040 #define MC_HUB_RDREQ_XDMAM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3041 #define MC_HUB_RDREQ_ACPG__ENABLE_MASK 0x1
3042 #define MC_HUB_RDREQ_ACPG__ENABLE__SHIFT 0x0
3043 #define MC_HUB_RDREQ_ACPG__PRESCALE_MASK 0x6
3044 #define MC_HUB_RDREQ_ACPG__PRESCALE__SHIFT 0x1
3045 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT_MASK 0x8
3046 #define MC_HUB_RDREQ_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
3047 #define MC_HUB_RDREQ_ACPG__STALL_MODE_MASK 0x30
3048 #define MC_HUB_RDREQ_ACPG__STALL_MODE__SHIFT 0x4
3049 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_MASK 0x40
3050 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE__SHIFT 0x6
3051 #define MC_HUB_RDREQ_ACPG__MAXBURST_MASK 0x780
3052 #define MC_HUB_RDREQ_ACPG__MAXBURST__SHIFT 0x7
3053 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER_MASK 0x7800
3054 #define MC_HUB_RDREQ_ACPG__LAZY_TIMER__SHIFT 0xb
3055 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
3056 #define MC_HUB_RDREQ_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
3057 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3058 #define MC_HUB_RDREQ_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3059 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE_MASK 0x20000
3060 #define MC_HUB_RDREQ_ACPG__PRIORITY_DISABLE__SHIFT 0x11
3061 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE_MASK 0x40000
3062 #define MC_HUB_RDREQ_ACPG__STALL_FILTER_ENABLE__SHIFT 0x12
3063 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD_MASK 0x1f80000
3064 #define MC_HUB_RDREQ_ACPG__STALL_THRESHOLD__SHIFT 0x13
3065 #define MC_HUB_RDREQ_ACPO__ENABLE_MASK 0x1
3066 #define MC_HUB_RDREQ_ACPO__ENABLE__SHIFT 0x0
3067 #define MC_HUB_RDREQ_ACPO__PRESCALE_MASK 0x6
3068 #define MC_HUB_RDREQ_ACPO__PRESCALE__SHIFT 0x1
3069 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT_MASK 0x8
3070 #define MC_HUB_RDREQ_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
3071 #define MC_HUB_RDREQ_ACPO__STALL_MODE_MASK 0x30
3072 #define MC_HUB_RDREQ_ACPO__STALL_MODE__SHIFT 0x4
3073 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_MASK 0x40
3074 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE__SHIFT 0x6
3075 #define MC_HUB_RDREQ_ACPO__MAXBURST_MASK 0x780
3076 #define MC_HUB_RDREQ_ACPO__MAXBURST__SHIFT 0x7
3077 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER_MASK 0x7800
3078 #define MC_HUB_RDREQ_ACPO__LAZY_TIMER__SHIFT 0xb
3079 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
3080 #define MC_HUB_RDREQ_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
3081 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3082 #define MC_HUB_RDREQ_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3083 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE_MASK 0x20000
3084 #define MC_HUB_RDREQ_ACPO__PRIORITY_DISABLE__SHIFT 0x11
3085 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE_MASK 0x40000
3086 #define MC_HUB_RDREQ_ACPO__STALL_FILTER_ENABLE__SHIFT 0x12
3087 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD_MASK 0x1f80000
3088 #define MC_HUB_RDREQ_ACPO__STALL_THRESHOLD__SHIFT 0x13
3089 #define MC_HUB_RDREQ_SAMMSP__ENABLE_MASK 0x1
3090 #define MC_HUB_RDREQ_SAMMSP__ENABLE__SHIFT 0x0
3091 #define MC_HUB_RDREQ_SAMMSP__PRESCALE_MASK 0x6
3092 #define MC_HUB_RDREQ_SAMMSP__PRESCALE__SHIFT 0x1
3093 #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
3094 #define MC_HUB_RDREQ_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
3095 #define MC_HUB_RDREQ_SAMMSP__STALL_MODE_MASK 0x30
3096 #define MC_HUB_RDREQ_SAMMSP__STALL_MODE__SHIFT 0x4
3097 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_MASK 0x40
3098 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
3099 #define MC_HUB_RDREQ_SAMMSP__MAXBURST_MASK 0x780
3100 #define MC_HUB_RDREQ_SAMMSP__MAXBURST__SHIFT 0x7
3101 #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER_MASK 0x7800
3102 #define MC_HUB_RDREQ_SAMMSP__LAZY_TIMER__SHIFT 0xb
3103 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
3104 #define MC_HUB_RDREQ_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
3105 #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3106 #define MC_HUB_RDREQ_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3107 #define MC_HUB_RDREQ_VP8__ENABLE_MASK 0x1
3108 #define MC_HUB_RDREQ_VP8__ENABLE__SHIFT 0x0
3109 #define MC_HUB_RDREQ_VP8__PRESCALE_MASK 0x6
3110 #define MC_HUB_RDREQ_VP8__PRESCALE__SHIFT 0x1
3111 #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT_MASK 0x8
3112 #define MC_HUB_RDREQ_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
3113 #define MC_HUB_RDREQ_VP8__STALL_MODE_MASK 0x30
3114 #define MC_HUB_RDREQ_VP8__STALL_MODE__SHIFT 0x4
3115 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_MASK 0x40
3116 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE__SHIFT 0x6
3117 #define MC_HUB_RDREQ_VP8__MAXBURST_MASK 0x780
3118 #define MC_HUB_RDREQ_VP8__MAXBURST__SHIFT 0x7
3119 #define MC_HUB_RDREQ_VP8__LAZY_TIMER_MASK 0x7800
3120 #define MC_HUB_RDREQ_VP8__LAZY_TIMER__SHIFT 0xb
3121 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
3122 #define MC_HUB_RDREQ_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
3123 #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3124 #define MC_HUB_RDREQ_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3125 #define MC_HUB_RDREQ_VP8U__ENABLE_MASK 0x1
3126 #define MC_HUB_RDREQ_VP8U__ENABLE__SHIFT 0x0
3127 #define MC_HUB_RDREQ_VP8U__PRESCALE_MASK 0x6
3128 #define MC_HUB_RDREQ_VP8U__PRESCALE__SHIFT 0x1
3129 #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT_MASK 0x8
3130 #define MC_HUB_RDREQ_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
3131 #define MC_HUB_RDREQ_VP8U__STALL_MODE_MASK 0x30
3132 #define MC_HUB_RDREQ_VP8U__STALL_MODE__SHIFT 0x4
3133 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_MASK 0x40
3134 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE__SHIFT 0x6
3135 #define MC_HUB_RDREQ_VP8U__MAXBURST_MASK 0x780
3136 #define MC_HUB_RDREQ_VP8U__MAXBURST__SHIFT 0x7
3137 #define MC_HUB_RDREQ_VP8U__LAZY_TIMER_MASK 0x7800
3138 #define MC_HUB_RDREQ_VP8U__LAZY_TIMER__SHIFT 0xb
3139 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
3140 #define MC_HUB_RDREQ_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
3141 #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3142 #define MC_HUB_RDREQ_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3143 #define MC_HUB_WDP_ACPG__ENABLE_MASK 0x1
3144 #define MC_HUB_WDP_ACPG__ENABLE__SHIFT 0x0
3145 #define MC_HUB_WDP_ACPG__PRESCALE_MASK 0x6
3146 #define MC_HUB_WDP_ACPG__PRESCALE__SHIFT 0x1
3147 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT_MASK 0x8
3148 #define MC_HUB_WDP_ACPG__BLACKOUT_EXEMPT__SHIFT 0x3
3149 #define MC_HUB_WDP_ACPG__STALL_MODE_MASK 0x30
3150 #define MC_HUB_WDP_ACPG__STALL_MODE__SHIFT 0x4
3151 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_MASK 0x40
3152 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE__SHIFT 0x6
3153 #define MC_HUB_WDP_ACPG__MAXBURST_MASK 0x780
3154 #define MC_HUB_WDP_ACPG__MAXBURST__SHIFT 0x7
3155 #define MC_HUB_WDP_ACPG__LAZY_TIMER_MASK 0x7800
3156 #define MC_HUB_WDP_ACPG__LAZY_TIMER__SHIFT 0xb
3157 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM_MASK 0x8000
3158 #define MC_HUB_WDP_ACPG__STALL_OVERRIDE_WTM__SHIFT 0xf
3159 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3160 #define MC_HUB_WDP_ACPG__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3161 #define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3162 #define MC_HUB_WDP_ACPG__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3163 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE_MASK 0x40000
3164 #define MC_HUB_WDP_ACPG__PRIORITY_DISABLE__SHIFT 0x12
3165 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE_MASK 0x80000
3166 #define MC_HUB_WDP_ACPG__STALL_FILTER_ENABLE__SHIFT 0x13
3167 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD_MASK 0x3f00000
3168 #define MC_HUB_WDP_ACPG__STALL_THRESHOLD__SHIFT 0x14
3169 #define MC_HUB_WDP_ACPO__ENABLE_MASK 0x1
3170 #define MC_HUB_WDP_ACPO__ENABLE__SHIFT 0x0
3171 #define MC_HUB_WDP_ACPO__PRESCALE_MASK 0x6
3172 #define MC_HUB_WDP_ACPO__PRESCALE__SHIFT 0x1
3173 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT_MASK 0x8
3174 #define MC_HUB_WDP_ACPO__BLACKOUT_EXEMPT__SHIFT 0x3
3175 #define MC_HUB_WDP_ACPO__STALL_MODE_MASK 0x30
3176 #define MC_HUB_WDP_ACPO__STALL_MODE__SHIFT 0x4
3177 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_MASK 0x40
3178 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE__SHIFT 0x6
3179 #define MC_HUB_WDP_ACPO__MAXBURST_MASK 0x780
3180 #define MC_HUB_WDP_ACPO__MAXBURST__SHIFT 0x7
3181 #define MC_HUB_WDP_ACPO__LAZY_TIMER_MASK 0x7800
3182 #define MC_HUB_WDP_ACPO__LAZY_TIMER__SHIFT 0xb
3183 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM_MASK 0x8000
3184 #define MC_HUB_WDP_ACPO__STALL_OVERRIDE_WTM__SHIFT 0xf
3185 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3186 #define MC_HUB_WDP_ACPO__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3187 #define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3188 #define MC_HUB_WDP_ACPO__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3189 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE_MASK 0x40000
3190 #define MC_HUB_WDP_ACPO__PRIORITY_DISABLE__SHIFT 0x12
3191 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE_MASK 0x80000
3192 #define MC_HUB_WDP_ACPO__STALL_FILTER_ENABLE__SHIFT 0x13
3193 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD_MASK 0x3f00000
3194 #define MC_HUB_WDP_ACPO__STALL_THRESHOLD__SHIFT 0x14
3195 #define MC_HUB_WDP_SAMMSP__ENABLE_MASK 0x1
3196 #define MC_HUB_WDP_SAMMSP__ENABLE__SHIFT 0x0
3197 #define MC_HUB_WDP_SAMMSP__PRESCALE_MASK 0x6
3198 #define MC_HUB_WDP_SAMMSP__PRESCALE__SHIFT 0x1
3199 #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT_MASK 0x8
3200 #define MC_HUB_WDP_SAMMSP__BLACKOUT_EXEMPT__SHIFT 0x3
3201 #define MC_HUB_WDP_SAMMSP__STALL_MODE_MASK 0x30
3202 #define MC_HUB_WDP_SAMMSP__STALL_MODE__SHIFT 0x4
3203 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_MASK 0x40
3204 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE__SHIFT 0x6
3205 #define MC_HUB_WDP_SAMMSP__MAXBURST_MASK 0x780
3206 #define MC_HUB_WDP_SAMMSP__MAXBURST__SHIFT 0x7
3207 #define MC_HUB_WDP_SAMMSP__LAZY_TIMER_MASK 0x7800
3208 #define MC_HUB_WDP_SAMMSP__LAZY_TIMER__SHIFT 0xb
3209 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM_MASK 0x8000
3210 #define MC_HUB_WDP_SAMMSP__STALL_OVERRIDE_WTM__SHIFT 0xf
3211 #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3212 #define MC_HUB_WDP_SAMMSP__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3213 #define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3214 #define MC_HUB_WDP_SAMMSP__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3215 #define MC_HUB_WDP_VP8__ENABLE_MASK 0x1
3216 #define MC_HUB_WDP_VP8__ENABLE__SHIFT 0x0
3217 #define MC_HUB_WDP_VP8__PRESCALE_MASK 0x6
3218 #define MC_HUB_WDP_VP8__PRESCALE__SHIFT 0x1
3219 #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT_MASK 0x8
3220 #define MC_HUB_WDP_VP8__BLACKOUT_EXEMPT__SHIFT 0x3
3221 #define MC_HUB_WDP_VP8__STALL_MODE_MASK 0x30
3222 #define MC_HUB_WDP_VP8__STALL_MODE__SHIFT 0x4
3223 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_MASK 0x40
3224 #define MC_HUB_WDP_VP8__STALL_OVERRIDE__SHIFT 0x6
3225 #define MC_HUB_WDP_VP8__MAXBURST_MASK 0x780
3226 #define MC_HUB_WDP_VP8__MAXBURST__SHIFT 0x7
3227 #define MC_HUB_WDP_VP8__LAZY_TIMER_MASK 0x7800
3228 #define MC_HUB_WDP_VP8__LAZY_TIMER__SHIFT 0xb
3229 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM_MASK 0x8000
3230 #define MC_HUB_WDP_VP8__STALL_OVERRIDE_WTM__SHIFT 0xf
3231 #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3232 #define MC_HUB_WDP_VP8__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3233 #define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3234 #define MC_HUB_WDP_VP8__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3235 #define MC_HUB_WDP_VP8U__ENABLE_MASK 0x1
3236 #define MC_HUB_WDP_VP8U__ENABLE__SHIFT 0x0
3237 #define MC_HUB_WDP_VP8U__PRESCALE_MASK 0x6
3238 #define MC_HUB_WDP_VP8U__PRESCALE__SHIFT 0x1
3239 #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT_MASK 0x8
3240 #define MC_HUB_WDP_VP8U__BLACKOUT_EXEMPT__SHIFT 0x3
3241 #define MC_HUB_WDP_VP8U__STALL_MODE_MASK 0x30
3242 #define MC_HUB_WDP_VP8U__STALL_MODE__SHIFT 0x4
3243 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_MASK 0x40
3244 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE__SHIFT 0x6
3245 #define MC_HUB_WDP_VP8U__MAXBURST_MASK 0x780
3246 #define MC_HUB_WDP_VP8U__MAXBURST__SHIFT 0x7
3247 #define MC_HUB_WDP_VP8U__LAZY_TIMER_MASK 0x7800
3248 #define MC_HUB_WDP_VP8U__LAZY_TIMER__SHIFT 0xb
3249 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM_MASK 0x8000
3250 #define MC_HUB_WDP_VP8U__STALL_OVERRIDE_WTM__SHIFT 0xf
3251 #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3252 #define MC_HUB_WDP_VP8U__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3253 #define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3254 #define MC_HUB_WDP_VP8U__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3255 #define MC_HUB_RDREQ_ISP_SPM__ENABLE_MASK 0x1
3256 #define MC_HUB_RDREQ_ISP_SPM__ENABLE__SHIFT 0x0
3257 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE_MASK 0x6
3258 #define MC_HUB_RDREQ_ISP_SPM__PRESCALE__SHIFT 0x1
3259 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3260 #define MC_HUB_RDREQ_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3261 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE_MASK 0x30
3262 #define MC_HUB_RDREQ_ISP_SPM__STALL_MODE__SHIFT 0x4
3263 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3264 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3265 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST_MASK 0x780
3266 #define MC_HUB_RDREQ_ISP_SPM__MAXBURST__SHIFT 0x7
3267 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER_MASK 0x7800
3268 #define MC_HUB_RDREQ_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3269 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3270 #define MC_HUB_RDREQ_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3271 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3272 #define MC_HUB_RDREQ_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3273 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE_MASK 0x20000
3274 #define MC_HUB_RDREQ_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x11
3275 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x40000
3276 #define MC_HUB_RDREQ_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x12
3277 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD_MASK 0x1f80000
3278 #define MC_HUB_RDREQ_ISP_SPM__STALL_THRESHOLD__SHIFT 0x13
3279 #define MC_HUB_RDREQ_ISP_MPM__ENABLE_MASK 0x1
3280 #define MC_HUB_RDREQ_ISP_MPM__ENABLE__SHIFT 0x0
3281 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE_MASK 0x6
3282 #define MC_HUB_RDREQ_ISP_MPM__PRESCALE__SHIFT 0x1
3283 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3284 #define MC_HUB_RDREQ_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3285 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE_MASK 0x30
3286 #define MC_HUB_RDREQ_ISP_MPM__STALL_MODE__SHIFT 0x4
3287 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3288 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3289 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST_MASK 0x780
3290 #define MC_HUB_RDREQ_ISP_MPM__MAXBURST__SHIFT 0x7
3291 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER_MASK 0x7800
3292 #define MC_HUB_RDREQ_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3293 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3294 #define MC_HUB_RDREQ_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3295 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3296 #define MC_HUB_RDREQ_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3297 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE_MASK 0x20000
3298 #define MC_HUB_RDREQ_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x11
3299 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x40000
3300 #define MC_HUB_RDREQ_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x12
3301 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD_MASK 0x1f80000
3302 #define MC_HUB_RDREQ_ISP_MPM__STALL_THRESHOLD__SHIFT 0x13
3303 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE_MASK 0x1
3304 #define MC_HUB_RDREQ_ISP_CCPU__ENABLE__SHIFT 0x0
3305 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE_MASK 0x6
3306 #define MC_HUB_RDREQ_ISP_CCPU__PRESCALE__SHIFT 0x1
3307 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3308 #define MC_HUB_RDREQ_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3309 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE_MASK 0x30
3310 #define MC_HUB_RDREQ_ISP_CCPU__STALL_MODE__SHIFT 0x4
3311 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3312 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3313 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST_MASK 0x780
3314 #define MC_HUB_RDREQ_ISP_CCPU__MAXBURST__SHIFT 0x7
3315 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3316 #define MC_HUB_RDREQ_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3317 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3318 #define MC_HUB_RDREQ_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3319 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3320 #define MC_HUB_RDREQ_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3321 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE_MASK 0x20000
3322 #define MC_HUB_RDREQ_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x11
3323 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x40000
3324 #define MC_HUB_RDREQ_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x12
3325 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD_MASK 0x1f80000
3326 #define MC_HUB_RDREQ_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x13
3327 #define MC_HUB_WDP_ISP_SPM__ENABLE_MASK 0x1
3328 #define MC_HUB_WDP_ISP_SPM__ENABLE__SHIFT 0x0
3329 #define MC_HUB_WDP_ISP_SPM__PRESCALE_MASK 0x6
3330 #define MC_HUB_WDP_ISP_SPM__PRESCALE__SHIFT 0x1
3331 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT_MASK 0x8
3332 #define MC_HUB_WDP_ISP_SPM__BLACKOUT_EXEMPT__SHIFT 0x3
3333 #define MC_HUB_WDP_ISP_SPM__STALL_MODE_MASK 0x30
3334 #define MC_HUB_WDP_ISP_SPM__STALL_MODE__SHIFT 0x4
3335 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_MASK 0x40
3336 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE__SHIFT 0x6
3337 #define MC_HUB_WDP_ISP_SPM__MAXBURST_MASK 0x780
3338 #define MC_HUB_WDP_ISP_SPM__MAXBURST__SHIFT 0x7
3339 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER_MASK 0x7800
3340 #define MC_HUB_WDP_ISP_SPM__LAZY_TIMER__SHIFT 0xb
3341 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM_MASK 0x8000
3342 #define MC_HUB_WDP_ISP_SPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3343 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3344 #define MC_HUB_WDP_ISP_SPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3345 #define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3346 #define MC_HUB_WDP_ISP_SPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3347 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE_MASK 0x40000
3348 #define MC_HUB_WDP_ISP_SPM__PRIORITY_DISABLE__SHIFT 0x12
3349 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE_MASK 0x80000
3350 #define MC_HUB_WDP_ISP_SPM__STALL_FILTER_ENABLE__SHIFT 0x13
3351 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD_MASK 0x3f00000
3352 #define MC_HUB_WDP_ISP_SPM__STALL_THRESHOLD__SHIFT 0x14
3353 #define MC_HUB_WDP_ISP_MPS__ENABLE_MASK 0x1
3354 #define MC_HUB_WDP_ISP_MPS__ENABLE__SHIFT 0x0
3355 #define MC_HUB_WDP_ISP_MPS__PRESCALE_MASK 0x6
3356 #define MC_HUB_WDP_ISP_MPS__PRESCALE__SHIFT 0x1
3357 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT_MASK 0x8
3358 #define MC_HUB_WDP_ISP_MPS__BLACKOUT_EXEMPT__SHIFT 0x3
3359 #define MC_HUB_WDP_ISP_MPS__STALL_MODE_MASK 0x30
3360 #define MC_HUB_WDP_ISP_MPS__STALL_MODE__SHIFT 0x4
3361 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_MASK 0x40
3362 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE__SHIFT 0x6
3363 #define MC_HUB_WDP_ISP_MPS__MAXBURST_MASK 0x780
3364 #define MC_HUB_WDP_ISP_MPS__MAXBURST__SHIFT 0x7
3365 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER_MASK 0x7800
3366 #define MC_HUB_WDP_ISP_MPS__LAZY_TIMER__SHIFT 0xb
3367 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM_MASK 0x8000
3368 #define MC_HUB_WDP_ISP_MPS__STALL_OVERRIDE_WTM__SHIFT 0xf
3369 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3370 #define MC_HUB_WDP_ISP_MPS__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3371 #define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3372 #define MC_HUB_WDP_ISP_MPS__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3373 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE_MASK 0x40000
3374 #define MC_HUB_WDP_ISP_MPS__PRIORITY_DISABLE__SHIFT 0x12
3375 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE_MASK 0x80000
3376 #define MC_HUB_WDP_ISP_MPS__STALL_FILTER_ENABLE__SHIFT 0x13
3377 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD_MASK 0x3f00000
3378 #define MC_HUB_WDP_ISP_MPS__STALL_THRESHOLD__SHIFT 0x14
3379 #define MC_HUB_WDP_ISP_MPM__ENABLE_MASK 0x1
3380 #define MC_HUB_WDP_ISP_MPM__ENABLE__SHIFT 0x0
3381 #define MC_HUB_WDP_ISP_MPM__PRESCALE_MASK 0x6
3382 #define MC_HUB_WDP_ISP_MPM__PRESCALE__SHIFT 0x1
3383 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT_MASK 0x8
3384 #define MC_HUB_WDP_ISP_MPM__BLACKOUT_EXEMPT__SHIFT 0x3
3385 #define MC_HUB_WDP_ISP_MPM__STALL_MODE_MASK 0x30
3386 #define MC_HUB_WDP_ISP_MPM__STALL_MODE__SHIFT 0x4
3387 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_MASK 0x40
3388 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE__SHIFT 0x6
3389 #define MC_HUB_WDP_ISP_MPM__MAXBURST_MASK 0x780
3390 #define MC_HUB_WDP_ISP_MPM__MAXBURST__SHIFT 0x7
3391 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER_MASK 0x7800
3392 #define MC_HUB_WDP_ISP_MPM__LAZY_TIMER__SHIFT 0xb
3393 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM_MASK 0x8000
3394 #define MC_HUB_WDP_ISP_MPM__STALL_OVERRIDE_WTM__SHIFT 0xf
3395 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3396 #define MC_HUB_WDP_ISP_MPM__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3397 #define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3398 #define MC_HUB_WDP_ISP_MPM__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3399 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE_MASK 0x40000
3400 #define MC_HUB_WDP_ISP_MPM__PRIORITY_DISABLE__SHIFT 0x12
3401 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE_MASK 0x80000
3402 #define MC_HUB_WDP_ISP_MPM__STALL_FILTER_ENABLE__SHIFT 0x13
3403 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD_MASK 0x3f00000
3404 #define MC_HUB_WDP_ISP_MPM__STALL_THRESHOLD__SHIFT 0x14
3405 #define MC_HUB_WDP_ISP_CCPU__ENABLE_MASK 0x1
3406 #define MC_HUB_WDP_ISP_CCPU__ENABLE__SHIFT 0x0
3407 #define MC_HUB_WDP_ISP_CCPU__PRESCALE_MASK 0x6
3408 #define MC_HUB_WDP_ISP_CCPU__PRESCALE__SHIFT 0x1
3409 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT_MASK 0x8
3410 #define MC_HUB_WDP_ISP_CCPU__BLACKOUT_EXEMPT__SHIFT 0x3
3411 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE_MASK 0x30
3412 #define MC_HUB_WDP_ISP_CCPU__STALL_MODE__SHIFT 0x4
3413 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_MASK 0x40
3414 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE__SHIFT 0x6
3415 #define MC_HUB_WDP_ISP_CCPU__MAXBURST_MASK 0x780
3416 #define MC_HUB_WDP_ISP_CCPU__MAXBURST__SHIFT 0x7
3417 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER_MASK 0x7800
3418 #define MC_HUB_WDP_ISP_CCPU__LAZY_TIMER__SHIFT 0xb
3419 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM_MASK 0x8000
3420 #define MC_HUB_WDP_ISP_CCPU__STALL_OVERRIDE_WTM__SHIFT 0xf
3421 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3422 #define MC_HUB_WDP_ISP_CCPU__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3423 #define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3424 #define MC_HUB_WDP_ISP_CCPU__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3425 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE_MASK 0x40000
3426 #define MC_HUB_WDP_ISP_CCPU__PRIORITY_DISABLE__SHIFT 0x12
3427 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE_MASK 0x80000
3428 #define MC_HUB_WDP_ISP_CCPU__STALL_FILTER_ENABLE__SHIFT 0x13
3429 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD_MASK 0x3f00000
3430 #define MC_HUB_WDP_ISP_CCPU__STALL_THRESHOLD__SHIFT 0x14
3431 #define MC_HUB_RDREQ_MCDS__ENABLE_MASK 0x1
3432 #define MC_HUB_RDREQ_MCDS__ENABLE__SHIFT 0x0
3433 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3434 #define MC_HUB_RDREQ_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3435 #define MC_HUB_RDREQ_MCDS__BUS_MASK 0x4
3436 #define MC_HUB_RDREQ_MCDS__BUS__SHIFT 0x2
3437 #define MC_HUB_RDREQ_MCDS__MAXBURST_MASK 0x78
3438 #define MC_HUB_RDREQ_MCDS__MAXBURST__SHIFT 0x3
3439 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER_MASK 0x780
3440 #define MC_HUB_RDREQ_MCDS__LAZY_TIMER__SHIFT 0x7
3441 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS_MASK 0x3f800
3442 #define MC_HUB_RDREQ_MCDS__ASK_CREDITS__SHIFT 0xb
3443 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS_MASK 0x1fc0000
3444 #define MC_HUB_RDREQ_MCDS__DISPLAY_CREDITS__SHIFT 0x12
3445 #define MC_HUB_RDREQ_MCDS__MED_CREDITS_MASK 0xfe000000
3446 #define MC_HUB_RDREQ_MCDS__MED_CREDITS__SHIFT 0x19
3447 #define MC_HUB_RDREQ_MCDT__ENABLE_MASK 0x1
3448 #define MC_HUB_RDREQ_MCDT__ENABLE__SHIFT 0x0
3449 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3450 #define MC_HUB_RDREQ_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3451 #define MC_HUB_RDREQ_MCDT__BUS_MASK 0x4
3452 #define MC_HUB_RDREQ_MCDT__BUS__SHIFT 0x2
3453 #define MC_HUB_RDREQ_MCDT__MAXBURST_MASK 0x78
3454 #define MC_HUB_RDREQ_MCDT__MAXBURST__SHIFT 0x3
3455 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER_MASK 0x780
3456 #define MC_HUB_RDREQ_MCDT__LAZY_TIMER__SHIFT 0x7
3457 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS_MASK 0x3f800
3458 #define MC_HUB_RDREQ_MCDT__ASK_CREDITS__SHIFT 0xb
3459 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS_MASK 0x1fc0000
3460 #define MC_HUB_RDREQ_MCDT__DISPLAY_CREDITS__SHIFT 0x12
3461 #define MC_HUB_RDREQ_MCDT__MED_CREDITS_MASK 0xfe000000
3462 #define MC_HUB_RDREQ_MCDT__MED_CREDITS__SHIFT 0x19
3463 #define MC_HUB_RDREQ_MCDU__ENABLE_MASK 0x1
3464 #define MC_HUB_RDREQ_MCDU__ENABLE__SHIFT 0x0
3465 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3466 #define MC_HUB_RDREQ_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3467 #define MC_HUB_RDREQ_MCDU__BUS_MASK 0x4
3468 #define MC_HUB_RDREQ_MCDU__BUS__SHIFT 0x2
3469 #define MC_HUB_RDREQ_MCDU__MAXBURST_MASK 0x78
3470 #define MC_HUB_RDREQ_MCDU__MAXBURST__SHIFT 0x3
3471 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER_MASK 0x780
3472 #define MC_HUB_RDREQ_MCDU__LAZY_TIMER__SHIFT 0x7
3473 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS_MASK 0x3f800
3474 #define MC_HUB_RDREQ_MCDU__ASK_CREDITS__SHIFT 0xb
3475 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS_MASK 0x1fc0000
3476 #define MC_HUB_RDREQ_MCDU__DISPLAY_CREDITS__SHIFT 0x12
3477 #define MC_HUB_RDREQ_MCDU__MED_CREDITS_MASK 0xfe000000
3478 #define MC_HUB_RDREQ_MCDU__MED_CREDITS__SHIFT 0x19
3479 #define MC_HUB_RDREQ_MCDV__ENABLE_MASK 0x1
3480 #define MC_HUB_RDREQ_MCDV__ENABLE__SHIFT 0x0
3481 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3482 #define MC_HUB_RDREQ_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3483 #define MC_HUB_RDREQ_MCDV__BUS_MASK 0x4
3484 #define MC_HUB_RDREQ_MCDV__BUS__SHIFT 0x2
3485 #define MC_HUB_RDREQ_MCDV__MAXBURST_MASK 0x78
3486 #define MC_HUB_RDREQ_MCDV__MAXBURST__SHIFT 0x3
3487 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER_MASK 0x780
3488 #define MC_HUB_RDREQ_MCDV__LAZY_TIMER__SHIFT 0x7
3489 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS_MASK 0x3f800
3490 #define MC_HUB_RDREQ_MCDV__ASK_CREDITS__SHIFT 0xb
3491 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS_MASK 0x1fc0000
3492 #define MC_HUB_RDREQ_MCDV__DISPLAY_CREDITS__SHIFT 0x12
3493 #define MC_HUB_RDREQ_MCDV__MED_CREDITS_MASK 0xfe000000
3494 #define MC_HUB_RDREQ_MCDV__MED_CREDITS__SHIFT 0x19
3495 #define MC_HUB_WDP_MCDS__ENABLE_MASK 0x1
3496 #define MC_HUB_WDP_MCDS__ENABLE__SHIFT 0x0
3497 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT_MASK 0x2
3498 #define MC_HUB_WDP_MCDS__BLACKOUT_EXEMPT__SHIFT 0x1
3499 #define MC_HUB_WDP_MCDS__STALL_MODE_MASK 0x4
3500 #define MC_HUB_WDP_MCDS__STALL_MODE__SHIFT 0x2
3501 #define MC_HUB_WDP_MCDS__MAXBURST_MASK 0x78
3502 #define MC_HUB_WDP_MCDS__MAXBURST__SHIFT 0x3
3503 #define MC_HUB_WDP_MCDS__ASK_CREDITS_MASK 0x1f80
3504 #define MC_HUB_WDP_MCDS__ASK_CREDITS__SHIFT 0x7
3505 #define MC_HUB_WDP_MCDS__LAZY_TIMER_MASK 0x1e000
3506 #define MC_HUB_WDP_MCDS__LAZY_TIMER__SHIFT 0xd
3507 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD_MASK 0xfe0000
3508 #define MC_HUB_WDP_MCDS__STALL_THRESHOLD__SHIFT 0x11
3509 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W_MASK 0x7f000000
3510 #define MC_HUB_WDP_MCDS__ASK_CREDITS_W__SHIFT 0x18
3511 #define MC_HUB_WDP_MCDT__ENABLE_MASK 0x1
3512 #define MC_HUB_WDP_MCDT__ENABLE__SHIFT 0x0
3513 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT_MASK 0x2
3514 #define MC_HUB_WDP_MCDT__BLACKOUT_EXEMPT__SHIFT 0x1
3515 #define MC_HUB_WDP_MCDT__STALL_MODE_MASK 0x4
3516 #define MC_HUB_WDP_MCDT__STALL_MODE__SHIFT 0x2
3517 #define MC_HUB_WDP_MCDT__MAXBURST_MASK 0x78
3518 #define MC_HUB_WDP_MCDT__MAXBURST__SHIFT 0x3
3519 #define MC_HUB_WDP_MCDT__ASK_CREDITS_MASK 0x1f80
3520 #define MC_HUB_WDP_MCDT__ASK_CREDITS__SHIFT 0x7
3521 #define MC_HUB_WDP_MCDT__LAZY_TIMER_MASK 0x1e000
3522 #define MC_HUB_WDP_MCDT__LAZY_TIMER__SHIFT 0xd
3523 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD_MASK 0xfe0000
3524 #define MC_HUB_WDP_MCDT__STALL_THRESHOLD__SHIFT 0x11
3525 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W_MASK 0x7f000000
3526 #define MC_HUB_WDP_MCDT__ASK_CREDITS_W__SHIFT 0x18
3527 #define MC_HUB_WDP_MCDU__ENABLE_MASK 0x1
3528 #define MC_HUB_WDP_MCDU__ENABLE__SHIFT 0x0
3529 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT_MASK 0x2
3530 #define MC_HUB_WDP_MCDU__BLACKOUT_EXEMPT__SHIFT 0x1
3531 #define MC_HUB_WDP_MCDU__STALL_MODE_MASK 0x4
3532 #define MC_HUB_WDP_MCDU__STALL_MODE__SHIFT 0x2
3533 #define MC_HUB_WDP_MCDU__MAXBURST_MASK 0x78
3534 #define MC_HUB_WDP_MCDU__MAXBURST__SHIFT 0x3
3535 #define MC_HUB_WDP_MCDU__ASK_CREDITS_MASK 0x1f80
3536 #define MC_HUB_WDP_MCDU__ASK_CREDITS__SHIFT 0x7
3537 #define MC_HUB_WDP_MCDU__LAZY_TIMER_MASK 0x1e000
3538 #define MC_HUB_WDP_MCDU__LAZY_TIMER__SHIFT 0xd
3539 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD_MASK 0xfe0000
3540 #define MC_HUB_WDP_MCDU__STALL_THRESHOLD__SHIFT 0x11
3541 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W_MASK 0x7f000000
3542 #define MC_HUB_WDP_MCDU__ASK_CREDITS_W__SHIFT 0x18
3543 #define MC_HUB_WDP_MCDV__ENABLE_MASK 0x1
3544 #define MC_HUB_WDP_MCDV__ENABLE__SHIFT 0x0
3545 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT_MASK 0x2
3546 #define MC_HUB_WDP_MCDV__BLACKOUT_EXEMPT__SHIFT 0x1
3547 #define MC_HUB_WDP_MCDV__STALL_MODE_MASK 0x4
3548 #define MC_HUB_WDP_MCDV__STALL_MODE__SHIFT 0x2
3549 #define MC_HUB_WDP_MCDV__MAXBURST_MASK 0x78
3550 #define MC_HUB_WDP_MCDV__MAXBURST__SHIFT 0x3
3551 #define MC_HUB_WDP_MCDV__ASK_CREDITS_MASK 0x1f80
3552 #define MC_HUB_WDP_MCDV__ASK_CREDITS__SHIFT 0x7
3553 #define MC_HUB_WDP_MCDV__LAZY_TIMER_MASK 0x1e000
3554 #define MC_HUB_WDP_MCDV__LAZY_TIMER__SHIFT 0xd
3555 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD_MASK 0xfe0000
3556 #define MC_HUB_WDP_MCDV__STALL_THRESHOLD__SHIFT 0x11
3557 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W_MASK 0x7f000000
3558 #define MC_HUB_WDP_MCDV__ASK_CREDITS_W__SHIFT 0x18
3559 #define MC_HUB_WRRET_MCDS__STALL_MODE_MASK 0x1
3560 #define MC_HUB_WRRET_MCDS__STALL_MODE__SHIFT 0x0
3561 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT_MASK 0xfe
3562 #define MC_HUB_WRRET_MCDS__CREDIT_COUNT__SHIFT 0x1
3563 #define MC_HUB_WRRET_MCDT__STALL_MODE_MASK 0x1
3564 #define MC_HUB_WRRET_MCDT__STALL_MODE__SHIFT 0x0
3565 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT_MASK 0xfe
3566 #define MC_HUB_WRRET_MCDT__CREDIT_COUNT__SHIFT 0x1
3567 #define MC_HUB_WRRET_MCDU__STALL_MODE_MASK 0x1
3568 #define MC_HUB_WRRET_MCDU__STALL_MODE__SHIFT 0x0
3569 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT_MASK 0xfe
3570 #define MC_HUB_WRRET_MCDU__CREDIT_COUNT__SHIFT 0x1
3571 #define MC_HUB_WRRET_MCDV__STALL_MODE_MASK 0x1
3572 #define MC_HUB_WRRET_MCDV__STALL_MODE__SHIFT 0x0
3573 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT_MASK 0xfe
3574 #define MC_HUB_WRRET_MCDV__CREDIT_COUNT__SHIFT 0x1
3575 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_MASK 0x7f
3576 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI__SHIFT 0x0
3577 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3578 #define MC_HUB_WDP_CREDITS_MCDW__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3579 #define MC_HUB_WDP_CREDITS_MCDW__WR_URG_MASK 0x1fc000
3580 #define MC_HUB_WDP_CREDITS_MCDW__WR_URG__SHIFT 0xe
3581 #define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3582 #define MC_HUB_WDP_CREDITS_MCDW__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3583 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_MASK 0x7f
3584 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI__SHIFT 0x0
3585 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3586 #define MC_HUB_WDP_CREDITS_MCDX__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3587 #define MC_HUB_WDP_CREDITS_MCDX__WR_URG_MASK 0x1fc000
3588 #define MC_HUB_WDP_CREDITS_MCDX__WR_URG__SHIFT 0xe
3589 #define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3590 #define MC_HUB_WDP_CREDITS_MCDX__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3591 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_MASK 0x7f
3592 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI__SHIFT 0x0
3593 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3594 #define MC_HUB_WDP_CREDITS_MCDY__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3595 #define MC_HUB_WDP_CREDITS_MCDY__WR_URG_MASK 0x1fc000
3596 #define MC_HUB_WDP_CREDITS_MCDY__WR_URG__SHIFT 0xe
3597 #define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3598 #define MC_HUB_WDP_CREDITS_MCDY__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3599 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_MASK 0x7f
3600 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI__SHIFT 0x0
3601 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3602 #define MC_HUB_WDP_CREDITS_MCDZ__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3603 #define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_MASK 0x1fc000
3604 #define MC_HUB_WDP_CREDITS_MCDZ__WR_URG__SHIFT 0xe
3605 #define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3606 #define MC_HUB_WDP_CREDITS_MCDZ__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3607 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_MASK 0x7f
3608 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI__SHIFT 0x0
3609 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3610 #define MC_HUB_WDP_CREDITS_MCDS__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3611 #define MC_HUB_WDP_CREDITS_MCDS__WR_URG_MASK 0x1fc000
3612 #define MC_HUB_WDP_CREDITS_MCDS__WR_URG__SHIFT 0xe
3613 #define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3614 #define MC_HUB_WDP_CREDITS_MCDS__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3615 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_MASK 0x7f
3616 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI__SHIFT 0x0
3617 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3618 #define MC_HUB_WDP_CREDITS_MCDT__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3619 #define MC_HUB_WDP_CREDITS_MCDT__WR_URG_MASK 0x1fc000
3620 #define MC_HUB_WDP_CREDITS_MCDT__WR_URG__SHIFT 0xe
3621 #define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3622 #define MC_HUB_WDP_CREDITS_MCDT__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3623 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_MASK 0x7f
3624 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI__SHIFT 0x0
3625 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3626 #define MC_HUB_WDP_CREDITS_MCDU__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3627 #define MC_HUB_WDP_CREDITS_MCDU__WR_URG_MASK 0x1fc000
3628 #define MC_HUB_WDP_CREDITS_MCDU__WR_URG__SHIFT 0xe
3629 #define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3630 #define MC_HUB_WDP_CREDITS_MCDU__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3631 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_MASK 0x7f
3632 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI__SHIFT 0x0
3633 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD_MASK 0x3f80
3634 #define MC_HUB_WDP_CREDITS_MCDV__WR_PRI_STALL_THRESHOLD__SHIFT 0x7
3635 #define MC_HUB_WDP_CREDITS_MCDV__WR_URG_MASK 0x1fc000
3636 #define MC_HUB_WDP_CREDITS_MCDV__WR_URG__SHIFT 0xe
3637 #define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD_MASK 0xfe00000
3638 #define MC_HUB_WDP_CREDITS_MCDV__WR_URG_STALL_THRESHOLD__SHIFT 0x15
3639 #define MC_HUB_WDP_BP2__RDRET_MASK 0xffff
3640 #define MC_HUB_WDP_BP2__RDRET__SHIFT 0x0
3641 #define MC_HUB_RDREQ_VCE1__ENABLE_MASK 0x1
3642 #define MC_HUB_RDREQ_VCE1__ENABLE__SHIFT 0x0
3643 #define MC_HUB_RDREQ_VCE1__PRESCALE_MASK 0x6
3644 #define MC_HUB_RDREQ_VCE1__PRESCALE__SHIFT 0x1
3645 #define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT_MASK 0x8
3646 #define MC_HUB_RDREQ_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
3647 #define MC_HUB_RDREQ_VCE1__STALL_MODE_MASK 0x30
3648 #define MC_HUB_RDREQ_VCE1__STALL_MODE__SHIFT 0x4
3649 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_MASK 0x40
3650 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE__SHIFT 0x6
3651 #define MC_HUB_RDREQ_VCE1__MAXBURST_MASK 0x780
3652 #define MC_HUB_RDREQ_VCE1__MAXBURST__SHIFT 0x7
3653 #define MC_HUB_RDREQ_VCE1__LAZY_TIMER_MASK 0x7800
3654 #define MC_HUB_RDREQ_VCE1__LAZY_TIMER__SHIFT 0xb
3655 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
3656 #define MC_HUB_RDREQ_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
3657 #define MC_HUB_RDREQ_VCE1__VM_BYPASS_MASK 0x10000
3658 #define MC_HUB_RDREQ_VCE1__VM_BYPASS__SHIFT 0x10
3659 #define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3660 #define MC_HUB_RDREQ_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3661 #define MC_HUB_RDREQ_VCEU1__ENABLE_MASK 0x1
3662 #define MC_HUB_RDREQ_VCEU1__ENABLE__SHIFT 0x0
3663 #define MC_HUB_RDREQ_VCEU1__PRESCALE_MASK 0x6
3664 #define MC_HUB_RDREQ_VCEU1__PRESCALE__SHIFT 0x1
3665 #define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
3666 #define MC_HUB_RDREQ_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
3667 #define MC_HUB_RDREQ_VCEU1__STALL_MODE_MASK 0x30
3668 #define MC_HUB_RDREQ_VCEU1__STALL_MODE__SHIFT 0x4
3669 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_MASK 0x40
3670 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE__SHIFT 0x6
3671 #define MC_HUB_RDREQ_VCEU1__MAXBURST_MASK 0x780
3672 #define MC_HUB_RDREQ_VCEU1__MAXBURST__SHIFT 0x7
3673 #define MC_HUB_RDREQ_VCEU1__LAZY_TIMER_MASK 0x7800
3674 #define MC_HUB_RDREQ_VCEU1__LAZY_TIMER__SHIFT 0xb
3675 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
3676 #define MC_HUB_RDREQ_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
3677 #define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3678 #define MC_HUB_RDREQ_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3679 #define MC_HUB_WDP_VCE1__ENABLE_MASK 0x1
3680 #define MC_HUB_WDP_VCE1__ENABLE__SHIFT 0x0
3681 #define MC_HUB_WDP_VCE1__PRESCALE_MASK 0x6
3682 #define MC_HUB_WDP_VCE1__PRESCALE__SHIFT 0x1
3683 #define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT_MASK 0x8
3684 #define MC_HUB_WDP_VCE1__BLACKOUT_EXEMPT__SHIFT 0x3
3685 #define MC_HUB_WDP_VCE1__STALL_MODE_MASK 0x30
3686 #define MC_HUB_WDP_VCE1__STALL_MODE__SHIFT 0x4
3687 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_MASK 0x40
3688 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE__SHIFT 0x6
3689 #define MC_HUB_WDP_VCE1__MAXBURST_MASK 0x780
3690 #define MC_HUB_WDP_VCE1__MAXBURST__SHIFT 0x7
3691 #define MC_HUB_WDP_VCE1__LAZY_TIMER_MASK 0x7800
3692 #define MC_HUB_WDP_VCE1__LAZY_TIMER__SHIFT 0xb
3693 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM_MASK 0x8000
3694 #define MC_HUB_WDP_VCE1__STALL_OVERRIDE_WTM__SHIFT 0xf
3695 #define MC_HUB_WDP_VCE1__VM_BYPASS_MASK 0x10000
3696 #define MC_HUB_WDP_VCE1__VM_BYPASS__SHIFT 0x10
3697 #define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3698 #define MC_HUB_WDP_VCE1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3699 #define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x40000
3700 #define MC_HUB_WDP_VCE1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x12
3701 #define MC_HUB_WDP_VCEU1__ENABLE_MASK 0x1
3702 #define MC_HUB_WDP_VCEU1__ENABLE__SHIFT 0x0
3703 #define MC_HUB_WDP_VCEU1__PRESCALE_MASK 0x6
3704 #define MC_HUB_WDP_VCEU1__PRESCALE__SHIFT 0x1
3705 #define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT_MASK 0x8
3706 #define MC_HUB_WDP_VCEU1__BLACKOUT_EXEMPT__SHIFT 0x3
3707 #define MC_HUB_WDP_VCEU1__STALL_MODE_MASK 0x30
3708 #define MC_HUB_WDP_VCEU1__STALL_MODE__SHIFT 0x4
3709 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_MASK 0x40
3710 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE__SHIFT 0x6
3711 #define MC_HUB_WDP_VCEU1__MAXBURST_MASK 0x780
3712 #define MC_HUB_WDP_VCEU1__MAXBURST__SHIFT 0x7
3713 #define MC_HUB_WDP_VCEU1__LAZY_TIMER_MASK 0x7800
3714 #define MC_HUB_WDP_VCEU1__LAZY_TIMER__SHIFT 0xb
3715 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM_MASK 0x8000
3716 #define MC_HUB_WDP_VCEU1__STALL_OVERRIDE_WTM__SHIFT 0xf
3717 #define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE_MASK 0x10000
3718 #define MC_HUB_WDP_VCEU1__BYPASS_AVAIL_OVERRIDE__SHIFT 0x10
3719 #define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE_MASK 0x20000
3720 #define MC_HUB_WDP_VCEU1__URG_BYPASS_AVAIL_OVERRIDE__SHIFT 0x11
3721 #define MC_RPB_CONF__XPB_PCIE_ORDER_MASK 0x8000
3722 #define MC_RPB_CONF__XPB_PCIE_ORDER__SHIFT 0xf
3723 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER_MASK 0x10000
3724 #define MC_RPB_CONF__RPB_RD_PCIE_ORDER__SHIFT 0x10
3725 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER_MASK 0x20000
3726 #define MC_RPB_CONF__RPB_WR_PCIE_ORDER__SHIFT 0x11
3727 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS_MASK 0xff
3728 #define MC_RPB_IF_CONF__RPB_BIF_CREDITS__SHIFT 0x0
3729 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK_MASK 0xff00
3730 #define MC_RPB_IF_CONF__OUTSTANDING_WRRET_ASK__SHIFT 0x8
3731 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_MASK 0xff
3732 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD__SHIFT 0x0
3733 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B_MASK 0xfff00
3734 #define MC_RPB_DBG1__RPB_BIF_OUTSTANDING_RD_32B__SHIFT 0x8
3735 #define MC_RPB_DBG1__DEBUG_BITS_MASK 0xfff00000
3736 #define MC_RPB_DBG1__DEBUG_BITS__SHIFT 0x14
3737 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER_MASK 0xff
3738 #define MC_RPB_EFF_CNTL__WR_LAZY_TIMER__SHIFT 0x0
3739 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER_MASK 0xff00
3740 #define MC_RPB_EFF_CNTL__RD_LAZY_TIMER__SHIFT 0x8
3741 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM_MASK 0xff
3742 #define MC_RPB_ARB_CNTL__WR_SWITCH_NUM__SHIFT 0x0
3743 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM_MASK 0xff00
3744 #define MC_RPB_ARB_CNTL__RD_SWITCH_NUM__SHIFT 0x8
3745 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM_MASK 0xff0000
3746 #define MC_RPB_ARB_CNTL__ATC_SWITCH_NUM__SHIFT 0x10
3747 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM_MASK 0xff
3748 #define MC_RPB_BIF_CNTL__ARB_SWITCH_NUM__SHIFT 0x0
3749 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM_MASK 0xff00
3750 #define MC_RPB_BIF_CNTL__XPB_SWITCH_NUM__SHIFT 0x8
3751 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3752 #define MC_RPB_WR_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3753 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3754 #define MC_RPB_WR_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3755 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3756 #define MC_RPB_WR_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3757 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3758 #define MC_RPB_WR_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3759 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE_MASK 0x1
3760 #define MC_RPB_WR_COMBINE_CNTL__WC_ENABLE__SHIFT 0x0
3761 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE_MASK 0x6
3762 #define MC_RPB_WR_COMBINE_CNTL__WC_MAX_PACKET_SIZE__SHIFT 0x1
3763 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER_MASK 0x78
3764 #define MC_RPB_WR_COMBINE_CNTL__WC_FLUSH_TIMER__SHIFT 0x3
3765 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN_MASK 0x80
3766 #define MC_RPB_WR_COMBINE_CNTL__WC_ALIGN__SHIFT 0x7
3767 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM_MASK 0xff
3768 #define MC_RPB_RD_SWITCH_CNTL__QUEUE0_SWITCH_NUM__SHIFT 0x0
3769 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM_MASK 0xff00
3770 #define MC_RPB_RD_SWITCH_CNTL__QUEUE1_SWITCH_NUM__SHIFT 0x8
3771 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM_MASK 0xff0000
3772 #define MC_RPB_RD_SWITCH_CNTL__QUEUE2_SWITCH_NUM__SHIFT 0x10
3773 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM_MASK 0xff000000
3774 #define MC_RPB_RD_SWITCH_CNTL__QUEUE3_SWITCH_NUM__SHIFT 0x18
3775 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID_MASK 0xff
3776 #define MC_RPB_CID_QUEUE_WR__CLIENT_ID__SHIFT 0x0
3777 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE_MASK 0x100
3778 #define MC_RPB_CID_QUEUE_WR__UPDATE_MODE__SHIFT 0x8
3779 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE_MASK 0x600
3780 #define MC_RPB_CID_QUEUE_WR__WRITE_QUEUE__SHIFT 0x9
3781 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE_MASK 0x1800
3782 #define MC_RPB_CID_QUEUE_WR__READ_QUEUE__SHIFT 0xb
3783 #define MC_RPB_CID_QUEUE_WR__UPDATE_MASK 0x2000
3784 #define MC_RPB_CID_QUEUE_WR__UPDATE__SHIFT 0xd
3785 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID_MASK 0xff
3786 #define MC_RPB_CID_QUEUE_RD__CLIENT_ID__SHIFT 0x0
3787 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE_MASK 0x300
3788 #define MC_RPB_CID_QUEUE_RD__WRITE_QUEUE__SHIFT 0x8
3789 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE_MASK 0xc00
3790 #define MC_RPB_CID_QUEUE_RD__READ_QUEUE__SHIFT 0xa
3791 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT_MASK 0x3
3792 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
3793 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER_MASK 0x4
3794 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_SELECTED_PERF_COUNTER__SHIFT 0x2
3795 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS_MASK 0x8
3796 #define MC_RPB_PERF_COUNTER_CNTL__CLEAR_ALL_PERF_COUNTERS__SHIFT 0x3
3797 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION_MASK 0x10
3798 #define MC_RPB_PERF_COUNTER_CNTL__STOP_ON_COUNTER_SATURATION__SHIFT 0x4
3799 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS_MASK 0x1e0
3800 #define MC_RPB_PERF_COUNTER_CNTL__ENABLE_PERF_COUNTERS__SHIFT 0x5
3801 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0_MASK 0x3e00
3802 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_0__SHIFT 0x9
3803 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1_MASK 0x7c000
3804 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_1__SHIFT 0xe
3805 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2_MASK 0xf80000
3806 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_2__SHIFT 0x13
3807 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3_MASK 0x1f000000
3808 #define MC_RPB_PERF_COUNTER_CNTL__PERF_COUNTER_ASSIGN_3__SHIFT 0x18
3809 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE_MASK 0xffffffff
3810 #define MC_RPB_PERF_COUNTER_STATUS__PERFORMANCE_COUNTER_VALUE__SHIFT 0x0
3811 #define MC_RPB_CID_QUEUE_EX__START_MASK 0x1
3812 #define MC_RPB_CID_QUEUE_EX__START__SHIFT 0x0
3813 #define MC_RPB_CID_QUEUE_EX__OFFSET_MASK 0x3e
3814 #define MC_RPB_CID_QUEUE_EX__OFFSET__SHIFT 0x1
3815 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES_MASK 0xffff
3816 #define MC_RPB_CID_QUEUE_EX_DATA__WRITE_ENTRIES__SHIFT 0x0
3817 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES_MASK 0xffff0000
3818 #define MC_RPB_CID_QUEUE_EX_DATA__READ_ENTRIES__SHIFT 0x10
3819 #define MC_RPB_TCI_CNTL__TCI_ENABLE_MASK 0x1
3820 #define MC_RPB_TCI_CNTL__TCI_ENABLE__SHIFT 0x0
3821 #define MC_RPB_TCI_CNTL__TCI_POLICY_MASK 0x6
3822 #define MC_RPB_TCI_CNTL__TCI_POLICY__SHIFT 0x1
3823 #define MC_RPB_TCI_CNTL__TCI_VOL_MASK 0x8
3824 #define MC_RPB_TCI_CNTL__TCI_VOL__SHIFT 0x3
3825 #define MC_RPB_TCI_CNTL__TCI_VMID_MASK 0xf0
3826 #define MC_RPB_TCI_CNTL__TCI_VMID__SHIFT 0x4
3827 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS_MASK 0xff00
3828 #define MC_RPB_TCI_CNTL__TCI_REQ_CREDITS__SHIFT 0x8
3829 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES_MASK 0xff0000
3830 #define MC_RPB_TCI_CNTL__TCI_MAX_WRITES__SHIFT 0x10
3831 #define MC_RPB_TCI_CNTL__TCI_MAX_READS_MASK 0xff000000
3832 #define MC_RPB_TCI_CNTL__TCI_MAX_READS__SHIFT 0x18
3833 #define MC_RPB_TCI_CNTL2__TCI_POLICY_MASK 0x1
3834 #define MC_RPB_TCI_CNTL2__TCI_POLICY__SHIFT 0x0
3835 #define MC_RPB_TCI_CNTL2__TCI_MTYPE_MASK 0x6
3836 #define MC_RPB_TCI_CNTL2__TCI_MTYPE__SHIFT 0x1
3837 #define MC_RPB_TCI_CNTL2__TCI_SNOOP_MASK 0x8
3838 #define MC_RPB_TCI_CNTL2__TCI_SNOOP__SHIFT 0x3
3839 #define MC_RPB_TCI_CNTL2__TCI_PHYSICAL_MASK 0x10
3840 #define MC_RPB_TCI_CNTL2__TCI_PHYSICAL__SHIFT 0x4
3841 #define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN_MASK 0x20
3842 #define MC_RPB_TCI_CNTL2__TCI_PERF_CNTR_EN__SHIFT 0x5
3843 #define MC_RPB_TCI_CNTL2__TCI_EXE_MASK 0x40
3844 #define MC_RPB_TCI_CNTL2__TCI_EXE__SHIFT 0x6
3845 #define MC_SHARED_CHMAP__CHAN0_MASK 0xf
3846 #define MC_SHARED_CHMAP__CHAN0__SHIFT 0x0
3847 #define MC_SHARED_CHMAP__CHAN1_MASK 0xf0
3848 #define MC_SHARED_CHMAP__CHAN1__SHIFT 0x4
3849 #define MC_SHARED_CHMAP__CHAN2_MASK 0xf00
3850 #define MC_SHARED_CHMAP__CHAN2__SHIFT 0x8
3851 #define MC_SHARED_CHMAP__NOOFCHAN_MASK 0xf000
3852 #define MC_SHARED_CHMAP__NOOFCHAN__SHIFT 0xc
3853 #define MC_SHARED_CHMAP__CHAN3_MASK 0xf0000
3854 #define MC_SHARED_CHMAP__CHAN3__SHIFT 0x10
3855 #define MC_SHARED_CHMAP__CHAN4_MASK 0xf00000
3856 #define MC_SHARED_CHMAP__CHAN4__SHIFT 0x14
3857 #define MC_SHARED_CHREMAP__CHAN0_MASK 0xf
3858 #define MC_SHARED_CHREMAP__CHAN0__SHIFT 0x0
3859 #define MC_SHARED_CHREMAP__CHAN1_MASK 0xf0
3860 #define MC_SHARED_CHREMAP__CHAN1__SHIFT 0x4
3861 #define MC_SHARED_CHREMAP__CHAN2_MASK 0xf00
3862 #define MC_SHARED_CHREMAP__CHAN2__SHIFT 0x8
3863 #define MC_SHARED_CHREMAP__CHAN3_MASK 0xf000
3864 #define MC_SHARED_CHREMAP__CHAN3__SHIFT 0xc
3865 #define MC_SHARED_CHREMAP__CHAN4_MASK 0xf0000
3866 #define MC_SHARED_CHREMAP__CHAN4__SHIFT 0x10
3867 #define MC_SHARED_CHREMAP__CHAN5_MASK 0xf00000
3868 #define MC_SHARED_CHREMAP__CHAN5__SHIFT 0x14
3869 #define MC_SHARED_CHREMAP__CHAN6_MASK 0xf000000
3870 #define MC_SHARED_CHREMAP__CHAN6__SHIFT 0x18
3871 #define MC_SHARED_CHREMAP__CHAN7_MASK 0xf0000000
3872 #define MC_SHARED_CHREMAP__CHAN7__SHIFT 0x1c
3873 #define MC_RD_GRP_GFX__CP_MASK 0xf
3874 #define MC_RD_GRP_GFX__CP__SHIFT 0x0
3875 #define MC_RD_GRP_GFX__SH_MASK 0xf0
3876 #define MC_RD_GRP_GFX__SH__SHIFT 0x4
3877 #define MC_RD_GRP_GFX__TLS_MASK 0xf00
3878 #define MC_RD_GRP_GFX__TLS__SHIFT 0x8
3879 #define MC_RD_GRP_GFX__ACPG_MASK 0xf000
3880 #define MC_RD_GRP_GFX__ACPG__SHIFT 0xc
3881 #define MC_RD_GRP_GFX__ACPO_MASK 0xf0000
3882 #define MC_RD_GRP_GFX__ACPO__SHIFT 0x10
3883 #define MC_RD_GRP_GFX__XDMAM_MASK 0xf00000
3884 #define MC_RD_GRP_GFX__XDMAM__SHIFT 0x14
3885 #define MC_RD_GRP_GFX__ISP_MASK 0xf000000
3886 #define MC_RD_GRP_GFX__ISP__SHIFT 0x18
3887 #define MC_RD_GRP_GFX__VP8_MASK 0xf0000000
3888 #define MC_RD_GRP_GFX__VP8__SHIFT 0x1c
3889 #define MC_WR_GRP_GFX__VIN0_MASK 0xf
3890 #define MC_WR_GRP_GFX__VIN0__SHIFT 0x0
3891 #define MC_WR_GRP_GFX__SH_MASK 0xf0
3892 #define MC_WR_GRP_GFX__SH__SHIFT 0x4
3893 #define MC_WR_GRP_GFX__ACPG_MASK 0xf00
3894 #define MC_WR_GRP_GFX__ACPG__SHIFT 0x8
3895 #define MC_WR_GRP_GFX__ACPO_MASK 0xf000
3896 #define MC_WR_GRP_GFX__ACPO__SHIFT 0xc
3897 #define MC_WR_GRP_GFX__ISP_MASK 0xf0000
3898 #define MC_WR_GRP_GFX__ISP__SHIFT 0x10
3899 #define MC_WR_GRP_GFX__VP8_MASK 0xf00000
3900 #define MC_WR_GRP_GFX__VP8__SHIFT 0x14
3901 #define MC_WR_GRP_GFX__XDMA_MASK 0xf000000
3902 #define MC_WR_GRP_GFX__XDMA__SHIFT 0x18
3903 #define MC_WR_GRP_GFX__XDMAM_MASK 0xf0000000
3904 #define MC_WR_GRP_GFX__XDMAM__SHIFT 0x1c
3905 #define MC_RD_GRP_SYS__RLC_MASK 0xf
3906 #define MC_RD_GRP_SYS__RLC__SHIFT 0x0
3907 #define MC_RD_GRP_SYS__VMC_MASK 0xf0
3908 #define MC_RD_GRP_SYS__VMC__SHIFT 0x4
3909 #define MC_RD_GRP_SYS__SDMA1_MASK 0xf00
3910 #define MC_RD_GRP_SYS__SDMA1__SHIFT 0x8
3911 #define MC_RD_GRP_SYS__DMIF_MASK 0xf000
3912 #define MC_RD_GRP_SYS__DMIF__SHIFT 0xc
3913 #define MC_RD_GRP_SYS__MCIF_MASK 0xf0000
3914 #define MC_RD_GRP_SYS__MCIF__SHIFT 0x10
3915 #define MC_RD_GRP_SYS__SMU_MASK 0xf00000
3916 #define MC_RD_GRP_SYS__SMU__SHIFT 0x14
3917 #define MC_RD_GRP_SYS__VCE0_MASK 0xf000000
3918 #define MC_RD_GRP_SYS__VCE0__SHIFT 0x18
3919 #define MC_RD_GRP_SYS__VCE1_MASK 0xf0000000
3920 #define MC_RD_GRP_SYS__VCE1__SHIFT 0x1c
3921 #define MC_WR_GRP_SYS__IH_MASK 0xf
3922 #define MC_WR_GRP_SYS__IH__SHIFT 0x0
3923 #define MC_WR_GRP_SYS__MCIF_MASK 0xf0
3924 #define MC_WR_GRP_SYS__MCIF__SHIFT 0x4
3925 #define MC_WR_GRP_SYS__RLC_MASK 0xf00
3926 #define MC_WR_GRP_SYS__RLC__SHIFT 0x8
3927 #define MC_WR_GRP_SYS__SAMMSP_MASK 0xf000
3928 #define MC_WR_GRP_SYS__SAMMSP__SHIFT 0xc
3929 #define MC_WR_GRP_SYS__SMU_MASK 0xf0000
3930 #define MC_WR_GRP_SYS__SMU__SHIFT 0x10
3931 #define MC_WR_GRP_SYS__SDMA1_MASK 0xf00000
3932 #define MC_WR_GRP_SYS__SDMA1__SHIFT 0x14
3933 #define MC_WR_GRP_SYS__VCE0_MASK 0xf000000
3934 #define MC_WR_GRP_SYS__VCE0__SHIFT 0x18
3935 #define MC_WR_GRP_SYS__VCE1_MASK 0xf0000000
3936 #define MC_WR_GRP_SYS__VCE1__SHIFT 0x1c
3937 #define MC_RD_GRP_OTH__UVD_EXT0_MASK 0xf
3938 #define MC_RD_GRP_OTH__UVD_EXT0__SHIFT 0x0
3939 #define MC_RD_GRP_OTH__SDMA0_MASK 0xf0
3940 #define MC_RD_GRP_OTH__SDMA0__SHIFT 0x4
3941 #define MC_RD_GRP_OTH__HDP_MASK 0xf00
3942 #define MC_RD_GRP_OTH__HDP__SHIFT 0x8
3943 #define MC_RD_GRP_OTH__SEM_MASK 0xf000
3944 #define MC_RD_GRP_OTH__SEM__SHIFT 0xc
3945 #define MC_RD_GRP_OTH__UMC_MASK 0xf0000
3946 #define MC_RD_GRP_OTH__UMC__SHIFT 0x10
3947 #define MC_RD_GRP_OTH__UVD_MASK 0xf00000
3948 #define MC_RD_GRP_OTH__UVD__SHIFT 0x14
3949 #define MC_RD_GRP_OTH__UVD_EXT1_MASK 0xf000000
3950 #define MC_RD_GRP_OTH__UVD_EXT1__SHIFT 0x18
3951 #define MC_RD_GRP_OTH__SAMMSP_MASK 0xf0000000
3952 #define MC_RD_GRP_OTH__SAMMSP__SHIFT 0x1c
3953 #define MC_WR_GRP_OTH__UVD_EXT0_MASK 0xf
3954 #define MC_WR_GRP_OTH__UVD_EXT0__SHIFT 0x0
3955 #define MC_WR_GRP_OTH__SDMA0_MASK 0xf0
3956 #define MC_WR_GRP_OTH__SDMA0__SHIFT 0x4
3957 #define MC_WR_GRP_OTH__HDP_MASK 0xf00
3958 #define MC_WR_GRP_OTH__HDP__SHIFT 0x8
3959 #define MC_WR_GRP_OTH__SEM_MASK 0xf000
3960 #define MC_WR_GRP_OTH__SEM__SHIFT 0xc
3961 #define MC_WR_GRP_OTH__UMC_MASK 0xf0000
3962 #define MC_WR_GRP_OTH__UMC__SHIFT 0x10
3963 #define MC_WR_GRP_OTH__UVD_MASK 0xf00000
3964 #define MC_WR_GRP_OTH__UVD__SHIFT 0x14
3965 #define MC_WR_GRP_OTH__XDP_MASK 0xf000000
3966 #define MC_WR_GRP_OTH__XDP__SHIFT 0x18
3967 #define MC_WR_GRP_OTH__UVD_EXT1_MASK 0xf0000000
3968 #define MC_WR_GRP_OTH__UVD_EXT1__SHIFT 0x1c
3969 #define MC_VM_FB_LOCATION__FB_BASE_MASK 0xffff
3970 #define MC_VM_FB_LOCATION__FB_BASE__SHIFT 0x0
3971 #define MC_VM_FB_LOCATION__FB_TOP_MASK 0xffff0000
3972 #define MC_VM_FB_LOCATION__FB_TOP__SHIFT 0x10
3973 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x3ffff
3974 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0
3975 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x3ffff
3976 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0
3977 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x3ffff
3978 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0
3979 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3980 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3981 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
3982 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
3983 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
3984 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
3985 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE_MASK 0x3
3986 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_0_MODE__SHIFT 0x0
3987 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE_MASK 0xc
3988 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_1_MODE__SHIFT 0x2
3989 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE_MASK 0x30
3990 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_2_MODE__SHIFT 0x4
3991 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE_MASK 0xc0
3992 #define MC_VM_DC_WRITE_CNTL__DC_WRITE_HIT_REGION_3_MODE__SHIFT 0x6
3993 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL_MASK 0x100
3994 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_LOCAL__SHIFT 0x8
3995 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM_MASK 0x200
3996 #define MC_VM_DC_WRITE_CNTL__DC_MEMORY_WRITE_SYSTEM__SHIFT 0x9
3997 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
3998 #define MC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
3999 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4000 #define MC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4001 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4002 #define MC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4003 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4004 #define MC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4005 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4006 #define MC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4007 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4008 #define MC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4009 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4010 #define MC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4011 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS_MASK 0xfffffff
4012 #define MC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR__PHYSICAL_ADDRESS__SHIFT 0x0
4013 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x1
4014 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0
4015 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK 0x2
4016 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING__SHIFT 0x1
4017 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x18
4018 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3
4019 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x20
4020 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5
4021 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x40
4022 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6
4023 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x780
4024 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7
4025 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x3ffff
4026 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0
4027 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x3
4028 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0
4029 #define MC_SHARED_CHREMAP2__CHAN8_MASK 0xf
4030 #define MC_SHARED_CHREMAP2__CHAN8__SHIFT 0x0
4031 #define MC_SHARED_CHREMAP2__CHAN9_MASK 0xf0
4032 #define MC_SHARED_CHREMAP2__CHAN9__SHIFT 0x4
4033 #define MC_SHARED_CHREMAP2__CHAN10_MASK 0xf00
4034 #define MC_SHARED_CHREMAP2__CHAN10__SHIFT 0x8
4035 #define MC_SHARED_CHREMAP2__CHAN11_MASK 0xf000
4036 #define MC_SHARED_CHREMAP2__CHAN11__SHIFT 0xc
4037 #define MC_SHARED_CHREMAP2__CHAN12_MASK 0xf0000
4038 #define MC_SHARED_CHREMAP2__CHAN12__SHIFT 0x10
4039 #define MC_SHARED_CHREMAP2__CHAN13_MASK 0xf00000
4040 #define MC_SHARED_CHREMAP2__CHAN13__SHIFT 0x14
4041 #define MC_SHARED_CHREMAP2__CHAN14_MASK 0xf000000
4042 #define MC_SHARED_CHREMAP2__CHAN14__SHIFT 0x18
4043 #define MC_SHARED_CHREMAP2__CHAN15_MASK 0xf0000000
4044 #define MC_SHARED_CHREMAP2__CHAN15__SHIFT 0x1c
4045 #define MC_SHARED_VF_ENABLE__VF_ENABLE_MASK 0x1
4046 #define MC_SHARED_VF_ENABLE__VF_ENABLE__SHIFT 0x0
4047 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0xffff
4048 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0
4049 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000
4050 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f
4051 #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0xf
4052 #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0
4053 #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000
4054 #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f
4055 #define MC_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
4056 #define MC_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
4057 #define MC_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
4058 #define MC_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
4059 #define MC_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
4060 #define MC_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
4061 #define MC_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
4062 #define MC_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
4063 #define MC_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
4064 #define MC_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
4065 #define MC_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
4066 #define MC_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
4067 #define MC_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
4068 #define MC_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
4069 #define MC_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
4070 #define MC_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
4071 #define MC_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
4072 #define MC_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
4073 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
4074 #define MC_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
4075 #define MC_CONFIG_MCD__ARB0_WR_ENABLE_MASK 0x1000
4076 #define MC_CONFIG_MCD__ARB0_WR_ENABLE__SHIFT 0xc
4077 #define MC_CONFIG_MCD__ARB1_WR_ENABLE_MASK 0x2000
4078 #define MC_CONFIG_MCD__ARB1_WR_ENABLE__SHIFT 0xd
4079 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE_MASK 0x80000000
4080 #define MC_CONFIG_MCD__MCD_INDEX_MODE_ENABLE__SHIFT 0x1f
4081 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE_MASK 0x1
4082 #define MC_CG_CONFIG_MCD__MCD0_WR_ENABLE__SHIFT 0x0
4083 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE_MASK 0x2
4084 #define MC_CG_CONFIG_MCD__MCD1_WR_ENABLE__SHIFT 0x1
4085 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE_MASK 0x4
4086 #define MC_CG_CONFIG_MCD__MCD2_WR_ENABLE__SHIFT 0x2
4087 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE_MASK 0x8
4088 #define MC_CG_CONFIG_MCD__MCD3_WR_ENABLE__SHIFT 0x3
4089 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE_MASK 0x10
4090 #define MC_CG_CONFIG_MCD__MCD4_WR_ENABLE__SHIFT 0x4
4091 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE_MASK 0x20
4092 #define MC_CG_CONFIG_MCD__MCD5_WR_ENABLE__SHIFT 0x5
4093 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE_MASK 0x40
4094 #define MC_CG_CONFIG_MCD__MCD6_WR_ENABLE__SHIFT 0x6
4095 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE_MASK 0x80
4096 #define MC_CG_CONFIG_MCD__MCD7_WR_ENABLE__SHIFT 0x7
4097 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_MASK 0x700
4098 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE__SHIFT 0x8
4099 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB_MASK 0x800
4100 #define MC_CG_CONFIG_MCD__MC_RD_ENABLE_SUB__SHIFT 0xb
4101 #define MC_CG_CONFIG_MCD__INDEX_MASK 0x1fffe000
4102 #define MC_CG_CONFIG_MCD__INDEX__SHIFT 0xd
4103 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x3f
4104 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0
4105 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0xfc0
4106 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6
4107 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE_MASK 0x7
4108 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MODE__SHIFT 0x0
4109 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE_MASK 0x8
4110 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_SEQ_FREE__SHIFT 0x3
4111 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM_MASK 0xff0
4112 #define MC_SHARED_BLACKOUT_CNTL__BLACKOUT_MCD_NUM__SHIFT 0x4
4113 #define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH_MASK 0x1000
4114 #define MC_SHARED_BLACKOUT_CNTL__FREE_TIE_HIGH__SHIFT 0xc
4115 #define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN_MASK 0x2000
4116 #define MC_SHARED_BLACKOUT_CNTL__SRBM_DUMMY_READ_RETURN__SHIFT 0xd
4117 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4118 #define MC_VM_MB_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4119 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4120 #define MC_VM_MB_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4121 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4122 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4123 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4124 #define MC_VM_MB_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4125 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4126 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4127 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4128 #define MC_VM_MB_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4129 #define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4130 #define MC_VM_MB_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4131 #define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4132 #define MC_VM_MB_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4133 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4134 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4135 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4136 #define MC_VM_MB_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4137 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4138 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4139 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4140 #define MC_VM_MB_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4141 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4142 #define MC_VM_MB_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4143 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4144 #define MC_VM_MB_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4145 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4146 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4147 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4148 #define MC_VM_MB_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4149 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4150 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4151 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4152 #define MC_VM_MB_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4153 #define MC_VM_MB_L1_TLB0_STATUS__BUSY_MASK 0x1
4154 #define MC_VM_MB_L1_TLB0_STATUS__BUSY__SHIFT 0x0
4155 #define MC_VM_MB_L1_TLB1_STATUS__BUSY_MASK 0x1
4156 #define MC_VM_MB_L1_TLB1_STATUS__BUSY__SHIFT 0x0
4157 #define MC_VM_MB_L1_TLB2_STATUS__BUSY_MASK 0x1
4158 #define MC_VM_MB_L1_TLB2_STATUS__BUSY__SHIFT 0x0
4159 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
4160 #define MC_VM_MB_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
4161 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4162 #define MC_VM_MB_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4163 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4164 #define MC_VM_MB_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4165 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4166 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4167 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4168 #define MC_VM_MB_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4169 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4170 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4171 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4172 #define MC_VM_MB_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4173 #define MC_VM_MB_L1_TLB3_STATUS__BUSY_MASK 0x1
4174 #define MC_VM_MB_L1_TLB3_STATUS__BUSY__SHIFT 0x0
4175 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4176 #define MC_VM_MD_L1_TLB0_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4177 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4178 #define MC_VM_MD_L1_TLB0_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4179 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4180 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4181 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4182 #define MC_VM_MD_L1_TLB0_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4183 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4184 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4185 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4186 #define MC_VM_MD_L1_TLB0_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4187 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4188 #define MC_VM_MD_L1_TLB1_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4189 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4190 #define MC_VM_MD_L1_TLB1_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4191 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4192 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4193 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4194 #define MC_VM_MD_L1_TLB1_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4195 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4196 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4197 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4198 #define MC_VM_MD_L1_TLB1_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4199 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4200 #define MC_VM_MD_L1_TLB2_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4201 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4202 #define MC_VM_MD_L1_TLB2_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4203 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4204 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4205 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4206 #define MC_VM_MD_L1_TLB2_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4207 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4208 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4209 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4210 #define MC_VM_MD_L1_TLB2_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4211 #define MC_VM_MD_L1_TLB0_STATUS__BUSY_MASK 0x1
4212 #define MC_VM_MD_L1_TLB0_STATUS__BUSY__SHIFT 0x0
4213 #define MC_VM_MD_L1_TLB1_STATUS__BUSY_MASK 0x1
4214 #define MC_VM_MD_L1_TLB1_STATUS__BUSY__SHIFT 0x0
4215 #define MC_VM_MD_L1_TLB2_STATUS__BUSY_MASK 0x1
4216 #define MC_VM_MD_L1_TLB2_STATUS__BUSY__SHIFT 0x0
4217 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS_MASK 0x3f
4218 #define MC_VM_MD_L2ARBITER_L2_CREDITS__L2_IF_CREDITS__SHIFT 0x0
4219 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB_MASK 0x1
4220 #define MC_VM_MD_L1_TLB3_DEBUG__INVALIDATE_L1_TLB__SHIFT 0x0
4221 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN_MASK 0x100
4222 #define MC_VM_MD_L1_TLB3_DEBUG__SEND_FREE_AT_RTN__SHIFT 0x8
4223 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE_MASK 0xe00
4224 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_TLB_SIZE__SHIFT 0x9
4225 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE_MASK 0x7000
4226 #define MC_VM_MD_L1_TLB3_DEBUG__EFFECTIVE_L1_QUEUE_SIZE__SHIFT 0xc
4227 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG_MASK 0x78000
4228 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_DEBUG__SHIFT 0xf
4229 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS_MASK 0x80000
4230 #define MC_VM_MD_L1_TLB3_DEBUG__L1_TLB_FORCE_MISS__SHIFT 0x13
4231 #define MC_VM_MD_L1_TLB3_STATUS__BUSY_MASK 0x1
4232 #define MC_VM_MD_L1_TLB3_STATUS__BUSY__SHIFT 0x0
4233 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
4234 #define MC_XPB_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
4235 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
4236 #define MC_XPB_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
4237 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
4238 #define MC_XPB_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
4239 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
4240 #define MC_XPB_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
4241 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR_MASK 0x1ffffff
4242 #define MC_XPB_RTR_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
4243 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR_MASK 0x1ffffff
4244 #define MC_XPB_RTR_SRC_APRTR5__BASE_ADDR__SHIFT 0x0
4245 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR_MASK 0x1ffffff
4246 #define MC_XPB_RTR_SRC_APRTR6__BASE_ADDR__SHIFT 0x0
4247 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR_MASK 0x1ffffff
4248 #define MC_XPB_RTR_SRC_APRTR7__BASE_ADDR__SHIFT 0x0
4249 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR_MASK 0x1ffffff
4250 #define MC_XPB_RTR_SRC_APRTR8__BASE_ADDR__SHIFT 0x0
4251 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR_MASK 0x1ffffff
4252 #define MC_XPB_RTR_SRC_APRTR9__BASE_ADDR__SHIFT 0x0
4253 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR_MASK 0x1ffffff
4254 #define MC_XPB_XDMA_RTR_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
4255 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR_MASK 0x1ffffff
4256 #define MC_XPB_XDMA_RTR_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
4257 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR_MASK 0x1ffffff
4258 #define MC_XPB_XDMA_RTR_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
4259 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR_MASK 0x1ffffff
4260 #define MC_XPB_XDMA_RTR_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
4261 #define MC_XPB_RTR_DEST_MAP0__NMR_MASK 0x1
4262 #define MC_XPB_RTR_DEST_MAP0__NMR__SHIFT 0x0
4263 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
4264 #define MC_XPB_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
4265 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
4266 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
4267 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
4268 #define MC_XPB_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
4269 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
4270 #define MC_XPB_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
4271 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
4272 #define MC_XPB_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
4273 #define MC_XPB_RTR_DEST_MAP1__NMR_MASK 0x1
4274 #define MC_XPB_RTR_DEST_MAP1__NMR__SHIFT 0x0
4275 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
4276 #define MC_XPB_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
4277 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
4278 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
4279 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
4280 #define MC_XPB_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
4281 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
4282 #define MC_XPB_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
4283 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
4284 #define MC_XPB_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
4285 #define MC_XPB_RTR_DEST_MAP2__NMR_MASK 0x1
4286 #define MC_XPB_RTR_DEST_MAP2__NMR__SHIFT 0x0
4287 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
4288 #define MC_XPB_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
4289 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
4290 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
4291 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
4292 #define MC_XPB_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
4293 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
4294 #define MC_XPB_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
4295 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
4296 #define MC_XPB_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
4297 #define MC_XPB_RTR_DEST_MAP3__NMR_MASK 0x1
4298 #define MC_XPB_RTR_DEST_MAP3__NMR__SHIFT 0x0
4299 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
4300 #define MC_XPB_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
4301 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
4302 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
4303 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
4304 #define MC_XPB_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
4305 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
4306 #define MC_XPB_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
4307 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
4308 #define MC_XPB_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
4309 #define MC_XPB_RTR_DEST_MAP4__NMR_MASK 0x1
4310 #define MC_XPB_RTR_DEST_MAP4__NMR__SHIFT 0x0
4311 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET_MASK 0xffffe
4312 #define MC_XPB_RTR_DEST_MAP4__DEST_OFFSET__SHIFT 0x1
4313 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_MASK 0xf00000
4314 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL__SHIFT 0x14
4315 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB_MASK 0x1000000
4316 #define MC_XPB_RTR_DEST_MAP4__DEST_SEL_RPB__SHIFT 0x18
4317 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK_MASK 0x2000000
4318 #define MC_XPB_RTR_DEST_MAP4__SIDE_OK__SHIFT 0x19
4319 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE_MASK 0x7c000000
4320 #define MC_XPB_RTR_DEST_MAP4__APRTR_SIZE__SHIFT 0x1a
4321 #define MC_XPB_RTR_DEST_MAP5__NMR_MASK 0x1
4322 #define MC_XPB_RTR_DEST_MAP5__NMR__SHIFT 0x0
4323 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET_MASK 0xffffe
4324 #define MC_XPB_RTR_DEST_MAP5__DEST_OFFSET__SHIFT 0x1
4325 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_MASK 0xf00000
4326 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL__SHIFT 0x14
4327 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB_MASK 0x1000000
4328 #define MC_XPB_RTR_DEST_MAP5__DEST_SEL_RPB__SHIFT 0x18
4329 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK_MASK 0x2000000
4330 #define MC_XPB_RTR_DEST_MAP5__SIDE_OK__SHIFT 0x19
4331 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE_MASK 0x7c000000
4332 #define MC_XPB_RTR_DEST_MAP5__APRTR_SIZE__SHIFT 0x1a
4333 #define MC_XPB_RTR_DEST_MAP6__NMR_MASK 0x1
4334 #define MC_XPB_RTR_DEST_MAP6__NMR__SHIFT 0x0
4335 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET_MASK 0xffffe
4336 #define MC_XPB_RTR_DEST_MAP6__DEST_OFFSET__SHIFT 0x1
4337 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_MASK 0xf00000
4338 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL__SHIFT 0x14
4339 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB_MASK 0x1000000
4340 #define MC_XPB_RTR_DEST_MAP6__DEST_SEL_RPB__SHIFT 0x18
4341 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK_MASK 0x2000000
4342 #define MC_XPB_RTR_DEST_MAP6__SIDE_OK__SHIFT 0x19
4343 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE_MASK 0x7c000000
4344 #define MC_XPB_RTR_DEST_MAP6__APRTR_SIZE__SHIFT 0x1a
4345 #define MC_XPB_RTR_DEST_MAP7__NMR_MASK 0x1
4346 #define MC_XPB_RTR_DEST_MAP7__NMR__SHIFT 0x0
4347 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET_MASK 0xffffe
4348 #define MC_XPB_RTR_DEST_MAP7__DEST_OFFSET__SHIFT 0x1
4349 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_MASK 0xf00000
4350 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL__SHIFT 0x14
4351 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB_MASK 0x1000000
4352 #define MC_XPB_RTR_DEST_MAP7__DEST_SEL_RPB__SHIFT 0x18
4353 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK_MASK 0x2000000
4354 #define MC_XPB_RTR_DEST_MAP7__SIDE_OK__SHIFT 0x19
4355 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE_MASK 0x7c000000
4356 #define MC_XPB_RTR_DEST_MAP7__APRTR_SIZE__SHIFT 0x1a
4357 #define MC_XPB_RTR_DEST_MAP8__NMR_MASK 0x1
4358 #define MC_XPB_RTR_DEST_MAP8__NMR__SHIFT 0x0
4359 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET_MASK 0xffffe
4360 #define MC_XPB_RTR_DEST_MAP8__DEST_OFFSET__SHIFT 0x1
4361 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_MASK 0xf00000
4362 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL__SHIFT 0x14
4363 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB_MASK 0x1000000
4364 #define MC_XPB_RTR_DEST_MAP8__DEST_SEL_RPB__SHIFT 0x18
4365 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK_MASK 0x2000000
4366 #define MC_XPB_RTR_DEST_MAP8__SIDE_OK__SHIFT 0x19
4367 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE_MASK 0x7c000000
4368 #define MC_XPB_RTR_DEST_MAP8__APRTR_SIZE__SHIFT 0x1a
4369 #define MC_XPB_RTR_DEST_MAP9__NMR_MASK 0x1
4370 #define MC_XPB_RTR_DEST_MAP9__NMR__SHIFT 0x0
4371 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET_MASK 0xffffe
4372 #define MC_XPB_RTR_DEST_MAP9__DEST_OFFSET__SHIFT 0x1
4373 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_MASK 0xf00000
4374 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL__SHIFT 0x14
4375 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB_MASK 0x1000000
4376 #define MC_XPB_RTR_DEST_MAP9__DEST_SEL_RPB__SHIFT 0x18
4377 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK_MASK 0x2000000
4378 #define MC_XPB_RTR_DEST_MAP9__SIDE_OK__SHIFT 0x19
4379 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE_MASK 0x7c000000
4380 #define MC_XPB_RTR_DEST_MAP9__APRTR_SIZE__SHIFT 0x1a
4381 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR_MASK 0x1
4382 #define MC_XPB_XDMA_RTR_DEST_MAP0__NMR__SHIFT 0x0
4383 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET_MASK 0xffffe
4384 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_OFFSET__SHIFT 0x1
4385 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_MASK 0xf00000
4386 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL__SHIFT 0x14
4387 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB_MASK 0x1000000
4388 #define MC_XPB_XDMA_RTR_DEST_MAP0__DEST_SEL_RPB__SHIFT 0x18
4389 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK_MASK 0x2000000
4390 #define MC_XPB_XDMA_RTR_DEST_MAP0__SIDE_OK__SHIFT 0x19
4391 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE_MASK 0x7c000000
4392 #define MC_XPB_XDMA_RTR_DEST_MAP0__APRTR_SIZE__SHIFT 0x1a
4393 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR_MASK 0x1
4394 #define MC_XPB_XDMA_RTR_DEST_MAP1__NMR__SHIFT 0x0
4395 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET_MASK 0xffffe
4396 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_OFFSET__SHIFT 0x1
4397 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_MASK 0xf00000
4398 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL__SHIFT 0x14
4399 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB_MASK 0x1000000
4400 #define MC_XPB_XDMA_RTR_DEST_MAP1__DEST_SEL_RPB__SHIFT 0x18
4401 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK_MASK 0x2000000
4402 #define MC_XPB_XDMA_RTR_DEST_MAP1__SIDE_OK__SHIFT 0x19
4403 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE_MASK 0x7c000000
4404 #define MC_XPB_XDMA_RTR_DEST_MAP1__APRTR_SIZE__SHIFT 0x1a
4405 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR_MASK 0x1
4406 #define MC_XPB_XDMA_RTR_DEST_MAP2__NMR__SHIFT 0x0
4407 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET_MASK 0xffffe
4408 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_OFFSET__SHIFT 0x1
4409 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_MASK 0xf00000
4410 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL__SHIFT 0x14
4411 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB_MASK 0x1000000
4412 #define MC_XPB_XDMA_RTR_DEST_MAP2__DEST_SEL_RPB__SHIFT 0x18
4413 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK_MASK 0x2000000
4414 #define MC_XPB_XDMA_RTR_DEST_MAP2__SIDE_OK__SHIFT 0x19
4415 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE_MASK 0x7c000000
4416 #define MC_XPB_XDMA_RTR_DEST_MAP2__APRTR_SIZE__SHIFT 0x1a
4417 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR_MASK 0x1
4418 #define MC_XPB_XDMA_RTR_DEST_MAP3__NMR__SHIFT 0x0
4419 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET_MASK 0xffffe
4420 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_OFFSET__SHIFT 0x1
4421 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_MASK 0xf00000
4422 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL__SHIFT 0x14
4423 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB_MASK 0x1000000
4424 #define MC_XPB_XDMA_RTR_DEST_MAP3__DEST_SEL_RPB__SHIFT 0x18
4425 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK_MASK 0x2000000
4426 #define MC_XPB_XDMA_RTR_DEST_MAP3__SIDE_OK__SHIFT 0x19
4427 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE_MASK 0x7c000000
4428 #define MC_XPB_XDMA_RTR_DEST_MAP3__APRTR_SIZE__SHIFT 0x1a
4429 #define MC_XPB_CLG_CFG0__WCB_NUM_MASK 0xf
4430 #define MC_XPB_CLG_CFG0__WCB_NUM__SHIFT 0x0
4431 #define MC_XPB_CLG_CFG0__LB_TYPE_MASK 0x70
4432 #define MC_XPB_CLG_CFG0__LB_TYPE__SHIFT 0x4
4433 #define MC_XPB_CLG_CFG0__P2P_BAR_MASK 0x380
4434 #define MC_XPB_CLG_CFG0__P2P_BAR__SHIFT 0x7
4435 #define MC_XPB_CLG_CFG0__HOST_FLUSH_MASK 0x3c00
4436 #define MC_XPB_CLG_CFG0__HOST_FLUSH__SHIFT 0xa
4437 #define MC_XPB_CLG_CFG0__SIDE_FLUSH_MASK 0x3c000
4438 #define MC_XPB_CLG_CFG0__SIDE_FLUSH__SHIFT 0xe
4439 #define MC_XPB_CLG_CFG1__WCB_NUM_MASK 0xf
4440 #define MC_XPB_CLG_CFG1__WCB_NUM__SHIFT 0x0
4441 #define MC_XPB_CLG_CFG1__LB_TYPE_MASK 0x70
4442 #define MC_XPB_CLG_CFG1__LB_TYPE__SHIFT 0x4
4443 #define MC_XPB_CLG_CFG1__P2P_BAR_MASK 0x380
4444 #define MC_XPB_CLG_CFG1__P2P_BAR__SHIFT 0x7
4445 #define MC_XPB_CLG_CFG1__HOST_FLUSH_MASK 0x3c00
4446 #define MC_XPB_CLG_CFG1__HOST_FLUSH__SHIFT 0xa
4447 #define MC_XPB_CLG_CFG1__SIDE_FLUSH_MASK 0x3c000
4448 #define MC_XPB_CLG_CFG1__SIDE_FLUSH__SHIFT 0xe
4449 #define MC_XPB_CLG_CFG2__WCB_NUM_MASK 0xf
4450 #define MC_XPB_CLG_CFG2__WCB_NUM__SHIFT 0x0
4451 #define MC_XPB_CLG_CFG2__LB_TYPE_MASK 0x70
4452 #define MC_XPB_CLG_CFG2__LB_TYPE__SHIFT 0x4
4453 #define MC_XPB_CLG_CFG2__P2P_BAR_MASK 0x380
4454 #define MC_XPB_CLG_CFG2__P2P_BAR__SHIFT 0x7
4455 #define MC_XPB_CLG_CFG2__HOST_FLUSH_MASK 0x3c00
4456 #define MC_XPB_CLG_CFG2__HOST_FLUSH__SHIFT 0xa
4457 #define MC_XPB_CLG_CFG2__SIDE_FLUSH_MASK 0x3c000
4458 #define MC_XPB_CLG_CFG2__SIDE_FLUSH__SHIFT 0xe
4459 #define MC_XPB_CLG_CFG3__WCB_NUM_MASK 0xf
4460 #define MC_XPB_CLG_CFG3__WCB_NUM__SHIFT 0x0
4461 #define MC_XPB_CLG_CFG3__LB_TYPE_MASK 0x70
4462 #define MC_XPB_CLG_CFG3__LB_TYPE__SHIFT 0x4
4463 #define MC_XPB_CLG_CFG3__P2P_BAR_MASK 0x380
4464 #define MC_XPB_CLG_CFG3__P2P_BAR__SHIFT 0x7
4465 #define MC_XPB_CLG_CFG3__HOST_FLUSH_MASK 0x3c00
4466 #define MC_XPB_CLG_CFG3__HOST_FLUSH__SHIFT 0xa
4467 #define MC_XPB_CLG_CFG3__SIDE_FLUSH_MASK 0x3c000
4468 #define MC_XPB_CLG_CFG3__SIDE_FLUSH__SHIFT 0xe
4469 #define MC_XPB_CLG_CFG4__WCB_NUM_MASK 0xf
4470 #define MC_XPB_CLG_CFG4__WCB_NUM__SHIFT 0x0
4471 #define MC_XPB_CLG_CFG4__LB_TYPE_MASK 0x70
4472 #define MC_XPB_CLG_CFG4__LB_TYPE__SHIFT 0x4
4473 #define MC_XPB_CLG_CFG4__P2P_BAR_MASK 0x380
4474 #define MC_XPB_CLG_CFG4__P2P_BAR__SHIFT 0x7
4475 #define MC_XPB_CLG_CFG4__HOST_FLUSH_MASK 0x3c00
4476 #define MC_XPB_CLG_CFG4__HOST_FLUSH__SHIFT 0xa
4477 #define MC_XPB_CLG_CFG4__SIDE_FLUSH_MASK 0x3c000
4478 #define MC_XPB_CLG_CFG4__SIDE_FLUSH__SHIFT 0xe
4479 #define MC_XPB_CLG_CFG5__WCB_NUM_MASK 0xf
4480 #define MC_XPB_CLG_CFG5__WCB_NUM__SHIFT 0x0
4481 #define MC_XPB_CLG_CFG5__LB_TYPE_MASK 0x70
4482 #define MC_XPB_CLG_CFG5__LB_TYPE__SHIFT 0x4
4483 #define MC_XPB_CLG_CFG5__P2P_BAR_MASK 0x380
4484 #define MC_XPB_CLG_CFG5__P2P_BAR__SHIFT 0x7
4485 #define MC_XPB_CLG_CFG5__HOST_FLUSH_MASK 0x3c00
4486 #define MC_XPB_CLG_CFG5__HOST_FLUSH__SHIFT 0xa
4487 #define MC_XPB_CLG_CFG5__SIDE_FLUSH_MASK 0x3c000
4488 #define MC_XPB_CLG_CFG5__SIDE_FLUSH__SHIFT 0xe
4489 #define MC_XPB_CLG_CFG6__WCB_NUM_MASK 0xf
4490 #define MC_XPB_CLG_CFG6__WCB_NUM__SHIFT 0x0
4491 #define MC_XPB_CLG_CFG6__LB_TYPE_MASK 0x70
4492 #define MC_XPB_CLG_CFG6__LB_TYPE__SHIFT 0x4
4493 #define MC_XPB_CLG_CFG6__P2P_BAR_MASK 0x380
4494 #define MC_XPB_CLG_CFG6__P2P_BAR__SHIFT 0x7
4495 #define MC_XPB_CLG_CFG6__HOST_FLUSH_MASK 0x3c00
4496 #define MC_XPB_CLG_CFG6__HOST_FLUSH__SHIFT 0xa
4497 #define MC_XPB_CLG_CFG6__SIDE_FLUSH_MASK 0x3c000
4498 #define MC_XPB_CLG_CFG6__SIDE_FLUSH__SHIFT 0xe
4499 #define MC_XPB_CLG_CFG7__WCB_NUM_MASK 0xf
4500 #define MC_XPB_CLG_CFG7__WCB_NUM__SHIFT 0x0
4501 #define MC_XPB_CLG_CFG7__LB_TYPE_MASK 0x70
4502 #define MC_XPB_CLG_CFG7__LB_TYPE__SHIFT 0x4
4503 #define MC_XPB_CLG_CFG7__P2P_BAR_MASK 0x380
4504 #define MC_XPB_CLG_CFG7__P2P_BAR__SHIFT 0x7
4505 #define MC_XPB_CLG_CFG7__HOST_FLUSH_MASK 0x3c00
4506 #define MC_XPB_CLG_CFG7__HOST_FLUSH__SHIFT 0xa
4507 #define MC_XPB_CLG_CFG7__SIDE_FLUSH_MASK 0x3c000
4508 #define MC_XPB_CLG_CFG7__SIDE_FLUSH__SHIFT 0xe
4509 #define MC_XPB_CLG_CFG8__WCB_NUM_MASK 0xf
4510 #define MC_XPB_CLG_CFG8__WCB_NUM__SHIFT 0x0
4511 #define MC_XPB_CLG_CFG8__LB_TYPE_MASK 0x70
4512 #define MC_XPB_CLG_CFG8__LB_TYPE__SHIFT 0x4
4513 #define MC_XPB_CLG_CFG8__P2P_BAR_MASK 0x380
4514 #define MC_XPB_CLG_CFG8__P2P_BAR__SHIFT 0x7
4515 #define MC_XPB_CLG_CFG8__HOST_FLUSH_MASK 0x3c00
4516 #define MC_XPB_CLG_CFG8__HOST_FLUSH__SHIFT 0xa
4517 #define MC_XPB_CLG_CFG8__SIDE_FLUSH_MASK 0x3c000
4518 #define MC_XPB_CLG_CFG8__SIDE_FLUSH__SHIFT 0xe
4519 #define MC_XPB_CLG_CFG9__WCB_NUM_MASK 0xf
4520 #define MC_XPB_CLG_CFG9__WCB_NUM__SHIFT 0x0
4521 #define MC_XPB_CLG_CFG9__LB_TYPE_MASK 0x70
4522 #define MC_XPB_CLG_CFG9__LB_TYPE__SHIFT 0x4
4523 #define MC_XPB_CLG_CFG9__P2P_BAR_MASK 0x380
4524 #define MC_XPB_CLG_CFG9__P2P_BAR__SHIFT 0x7
4525 #define MC_XPB_CLG_CFG9__HOST_FLUSH_MASK 0x3c00
4526 #define MC_XPB_CLG_CFG9__HOST_FLUSH__SHIFT 0xa
4527 #define MC_XPB_CLG_CFG9__SIDE_FLUSH_MASK 0x3c000
4528 #define MC_XPB_CLG_CFG9__SIDE_FLUSH__SHIFT 0xe
4529 #define MC_XPB_CLG_CFG10__WCB_NUM_MASK 0xf
4530 #define MC_XPB_CLG_CFG10__WCB_NUM__SHIFT 0x0
4531 #define MC_XPB_CLG_CFG10__LB_TYPE_MASK 0x70
4532 #define MC_XPB_CLG_CFG10__LB_TYPE__SHIFT 0x4
4533 #define MC_XPB_CLG_CFG10__P2P_BAR_MASK 0x380
4534 #define MC_XPB_CLG_CFG10__P2P_BAR__SHIFT 0x7
4535 #define MC_XPB_CLG_CFG10__HOST_FLUSH_MASK 0x3c00
4536 #define MC_XPB_CLG_CFG10__HOST_FLUSH__SHIFT 0xa
4537 #define MC_XPB_CLG_CFG10__SIDE_FLUSH_MASK 0x3c000
4538 #define MC_XPB_CLG_CFG10__SIDE_FLUSH__SHIFT 0xe
4539 #define MC_XPB_CLG_CFG11__WCB_NUM_MASK 0xf
4540 #define MC_XPB_CLG_CFG11__WCB_NUM__SHIFT 0x0
4541 #define MC_XPB_CLG_CFG11__LB_TYPE_MASK 0x70
4542 #define MC_XPB_CLG_CFG11__LB_TYPE__SHIFT 0x4
4543 #define MC_XPB_CLG_CFG11__P2P_BAR_MASK 0x380
4544 #define MC_XPB_CLG_CFG11__P2P_BAR__SHIFT 0x7
4545 #define MC_XPB_CLG_CFG11__HOST_FLUSH_MASK 0x3c00
4546 #define MC_XPB_CLG_CFG11__HOST_FLUSH__SHIFT 0xa
4547 #define MC_XPB_CLG_CFG11__SIDE_FLUSH_MASK 0x3c000
4548 #define MC_XPB_CLG_CFG11__SIDE_FLUSH__SHIFT 0xe
4549 #define MC_XPB_CLG_CFG12__WCB_NUM_MASK 0xf
4550 #define MC_XPB_CLG_CFG12__WCB_NUM__SHIFT 0x0
4551 #define MC_XPB_CLG_CFG12__LB_TYPE_MASK 0x70
4552 #define MC_XPB_CLG_CFG12__LB_TYPE__SHIFT 0x4
4553 #define MC_XPB_CLG_CFG12__P2P_BAR_MASK 0x380
4554 #define MC_XPB_CLG_CFG12__P2P_BAR__SHIFT 0x7
4555 #define MC_XPB_CLG_CFG12__HOST_FLUSH_MASK 0x3c00
4556 #define MC_XPB_CLG_CFG12__HOST_FLUSH__SHIFT 0xa
4557 #define MC_XPB_CLG_CFG12__SIDE_FLUSH_MASK 0x3c000
4558 #define MC_XPB_CLG_CFG12__SIDE_FLUSH__SHIFT 0xe
4559 #define MC_XPB_CLG_CFG13__WCB_NUM_MASK 0xf
4560 #define MC_XPB_CLG_CFG13__WCB_NUM__SHIFT 0x0
4561 #define MC_XPB_CLG_CFG13__LB_TYPE_MASK 0x70
4562 #define MC_XPB_CLG_CFG13__LB_TYPE__SHIFT 0x4
4563 #define MC_XPB_CLG_CFG13__P2P_BAR_MASK 0x380
4564 #define MC_XPB_CLG_CFG13__P2P_BAR__SHIFT 0x7
4565 #define MC_XPB_CLG_CFG13__HOST_FLUSH_MASK 0x3c00
4566 #define MC_XPB_CLG_CFG13__HOST_FLUSH__SHIFT 0xa
4567 #define MC_XPB_CLG_CFG13__SIDE_FLUSH_MASK 0x3c000
4568 #define MC_XPB_CLG_CFG13__SIDE_FLUSH__SHIFT 0xe
4569 #define MC_XPB_CLG_CFG14__WCB_NUM_MASK 0xf
4570 #define MC_XPB_CLG_CFG14__WCB_NUM__SHIFT 0x0
4571 #define MC_XPB_CLG_CFG14__LB_TYPE_MASK 0x70
4572 #define MC_XPB_CLG_CFG14__LB_TYPE__SHIFT 0x4
4573 #define MC_XPB_CLG_CFG14__P2P_BAR_MASK 0x380
4574 #define MC_XPB_CLG_CFG14__P2P_BAR__SHIFT 0x7
4575 #define MC_XPB_CLG_CFG14__HOST_FLUSH_MASK 0x3c00
4576 #define MC_XPB_CLG_CFG14__HOST_FLUSH__SHIFT 0xa
4577 #define MC_XPB_CLG_CFG14__SIDE_FLUSH_MASK 0x3c000
4578 #define MC_XPB_CLG_CFG14__SIDE_FLUSH__SHIFT 0xe
4579 #define MC_XPB_CLG_CFG15__WCB_NUM_MASK 0xf
4580 #define MC_XPB_CLG_CFG15__WCB_NUM__SHIFT 0x0
4581 #define MC_XPB_CLG_CFG15__LB_TYPE_MASK 0x70
4582 #define MC_XPB_CLG_CFG15__LB_TYPE__SHIFT 0x4
4583 #define MC_XPB_CLG_CFG15__P2P_BAR_MASK 0x380
4584 #define MC_XPB_CLG_CFG15__P2P_BAR__SHIFT 0x7
4585 #define MC_XPB_CLG_CFG15__HOST_FLUSH_MASK 0x3c00
4586 #define MC_XPB_CLG_CFG15__HOST_FLUSH__SHIFT 0xa
4587 #define MC_XPB_CLG_CFG15__SIDE_FLUSH_MASK 0x3c000
4588 #define MC_XPB_CLG_CFG15__SIDE_FLUSH__SHIFT 0xe
4589 #define MC_XPB_CLG_CFG16__WCB_NUM_MASK 0xf
4590 #define MC_XPB_CLG_CFG16__WCB_NUM__SHIFT 0x0
4591 #define MC_XPB_CLG_CFG16__LB_TYPE_MASK 0x70
4592 #define MC_XPB_CLG_CFG16__LB_TYPE__SHIFT 0x4
4593 #define MC_XPB_CLG_CFG16__P2P_BAR_MASK 0x380
4594 #define MC_XPB_CLG_CFG16__P2P_BAR__SHIFT 0x7
4595 #define MC_XPB_CLG_CFG16__HOST_FLUSH_MASK 0x3c00
4596 #define MC_XPB_CLG_CFG16__HOST_FLUSH__SHIFT 0xa
4597 #define MC_XPB_CLG_CFG16__SIDE_FLUSH_MASK 0x3c000
4598 #define MC_XPB_CLG_CFG16__SIDE_FLUSH__SHIFT 0xe
4599 #define MC_XPB_CLG_CFG17__WCB_NUM_MASK 0xf
4600 #define MC_XPB_CLG_CFG17__WCB_NUM__SHIFT 0x0
4601 #define MC_XPB_CLG_CFG17__LB_TYPE_MASK 0x70
4602 #define MC_XPB_CLG_CFG17__LB_TYPE__SHIFT 0x4
4603 #define MC_XPB_CLG_CFG17__P2P_BAR_MASK 0x380
4604 #define MC_XPB_CLG_CFG17__P2P_BAR__SHIFT 0x7
4605 #define MC_XPB_CLG_CFG17__HOST_FLUSH_MASK 0x3c00
4606 #define MC_XPB_CLG_CFG17__HOST_FLUSH__SHIFT 0xa
4607 #define MC_XPB_CLG_CFG17__SIDE_FLUSH_MASK 0x3c000
4608 #define MC_XPB_CLG_CFG17__SIDE_FLUSH__SHIFT 0xe
4609 #define MC_XPB_CLG_CFG18__WCB_NUM_MASK 0xf
4610 #define MC_XPB_CLG_CFG18__WCB_NUM__SHIFT 0x0
4611 #define MC_XPB_CLG_CFG18__LB_TYPE_MASK 0x70
4612 #define MC_XPB_CLG_CFG18__LB_TYPE__SHIFT 0x4
4613 #define MC_XPB_CLG_CFG18__P2P_BAR_MASK 0x380
4614 #define MC_XPB_CLG_CFG18__P2P_BAR__SHIFT 0x7
4615 #define MC_XPB_CLG_CFG18__HOST_FLUSH_MASK 0x3c00
4616 #define MC_XPB_CLG_CFG18__HOST_FLUSH__SHIFT 0xa
4617 #define MC_XPB_CLG_CFG18__SIDE_FLUSH_MASK 0x3c000
4618 #define MC_XPB_CLG_CFG18__SIDE_FLUSH__SHIFT 0xe
4619 #define MC_XPB_CLG_CFG19__WCB_NUM_MASK 0xf
4620 #define MC_XPB_CLG_CFG19__WCB_NUM__SHIFT 0x0
4621 #define MC_XPB_CLG_CFG19__LB_TYPE_MASK 0x70
4622 #define MC_XPB_CLG_CFG19__LB_TYPE__SHIFT 0x4
4623 #define MC_XPB_CLG_CFG19__P2P_BAR_MASK 0x380
4624 #define MC_XPB_CLG_CFG19__P2P_BAR__SHIFT 0x7
4625 #define MC_XPB_CLG_CFG19__HOST_FLUSH_MASK 0x3c00
4626 #define MC_XPB_CLG_CFG19__HOST_FLUSH__SHIFT 0xa
4627 #define MC_XPB_CLG_CFG19__SIDE_FLUSH_MASK 0x3c000
4628 #define MC_XPB_CLG_CFG19__SIDE_FLUSH__SHIFT 0xe
4629 #define MC_XPB_CLG_EXTRA__CMP0_MASK 0xff
4630 #define MC_XPB_CLG_EXTRA__CMP0__SHIFT 0x0
4631 #define MC_XPB_CLG_EXTRA__MSK0_MASK 0xff00
4632 #define MC_XPB_CLG_EXTRA__MSK0__SHIFT 0x8
4633 #define MC_XPB_CLG_EXTRA__VLD0_MASK 0x10000
4634 #define MC_XPB_CLG_EXTRA__VLD0__SHIFT 0x10
4635 #define MC_XPB_CLG_EXTRA__CMP1_MASK 0x1fe0000
4636 #define MC_XPB_CLG_EXTRA__CMP1__SHIFT 0x11
4637 #define MC_XPB_CLG_EXTRA__VLD1_MASK 0x2000000
4638 #define MC_XPB_CLG_EXTRA__VLD1__SHIFT 0x19
4639 #define MC_XPB_LB_ADDR__CMP0_MASK 0x3ff
4640 #define MC_XPB_LB_ADDR__CMP0__SHIFT 0x0
4641 #define MC_XPB_LB_ADDR__MASK0_MASK 0xffc00
4642 #define MC_XPB_LB_ADDR__MASK0__SHIFT 0xa
4643 #define MC_XPB_LB_ADDR__CMP1_MASK 0x3f00000
4644 #define MC_XPB_LB_ADDR__CMP1__SHIFT 0x14
4645 #define MC_XPB_LB_ADDR__MASK1_MASK 0xfc000000
4646 #define MC_XPB_LB_ADDR__MASK1__SHIFT 0x1a
4647 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF_MASK 0x3f
4648 #define MC_XPB_UNC_THRESH_HST__CHANGE_PREF__SHIFT 0x0
4649 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF_MASK 0xfc0
4650 #define MC_XPB_UNC_THRESH_HST__STRONG_PREF__SHIFT 0x6
4651 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL_MASK 0x3f000
4652 #define MC_XPB_UNC_THRESH_HST__USE_UNFULL__SHIFT 0xc
4653 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF_MASK 0x3f
4654 #define MC_XPB_UNC_THRESH_SID__CHANGE_PREF__SHIFT 0x0
4655 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF_MASK 0xfc0
4656 #define MC_XPB_UNC_THRESH_SID__STRONG_PREF__SHIFT 0x6
4657 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL_MASK 0x3f000
4658 #define MC_XPB_UNC_THRESH_SID__USE_UNFULL__SHIFT 0xc
4659 #define MC_XPB_WCB_STS__PBUF_VLD_MASK 0xffff
4660 #define MC_XPB_WCB_STS__PBUF_VLD__SHIFT 0x0
4661 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT_MASK 0x7f0000
4662 #define MC_XPB_WCB_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x10
4663 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT_MASK 0x3f800000
4664 #define MC_XPB_WCB_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x17
4665 #define MC_XPB_WCB_CFG__TIMEOUT_MASK 0xffff
4666 #define MC_XPB_WCB_CFG__TIMEOUT__SHIFT 0x0
4667 #define MC_XPB_WCB_CFG__HST_MAX_MASK 0x30000
4668 #define MC_XPB_WCB_CFG__HST_MAX__SHIFT 0x10
4669 #define MC_XPB_WCB_CFG__SID_MAX_MASK 0xc0000
4670 #define MC_XPB_WCB_CFG__SID_MAX__SHIFT 0x12
4671 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE_MASK 0xf
4672 #define MC_XPB_P2P_BAR_CFG__ADDR_SIZE__SHIFT 0x0
4673 #define MC_XPB_P2P_BAR_CFG__SEND_BAR_MASK 0x30
4674 #define MC_XPB_P2P_BAR_CFG__SEND_BAR__SHIFT 0x4
4675 #define MC_XPB_P2P_BAR_CFG__SNOOP_MASK 0x40
4676 #define MC_XPB_P2P_BAR_CFG__SNOOP__SHIFT 0x6
4677 #define MC_XPB_P2P_BAR_CFG__SEND_DIS_MASK 0x80
4678 #define MC_XPB_P2P_BAR_CFG__SEND_DIS__SHIFT 0x7
4679 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS_MASK 0x100
4680 #define MC_XPB_P2P_BAR_CFG__COMPRESS_DIS__SHIFT 0x8
4681 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS_MASK 0x200
4682 #define MC_XPB_P2P_BAR_CFG__UPDATE_DIS__SHIFT 0x9
4683 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR_MASK 0x400
4684 #define MC_XPB_P2P_BAR_CFG__REGBAR_FROM_SYSBAR__SHIFT 0xa
4685 #define MC_XPB_P2P_BAR_CFG__RD_EN_MASK 0x800
4686 #define MC_XPB_P2P_BAR_CFG__RD_EN__SHIFT 0xb
4687 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED_MASK 0x1000
4688 #define MC_XPB_P2P_BAR_CFG__ATC_TRANSLATED__SHIFT 0xc
4689 #define MC_XPB_P2P_BAR0__HOST_FLUSH_MASK 0xf
4690 #define MC_XPB_P2P_BAR0__HOST_FLUSH__SHIFT 0x0
4691 #define MC_XPB_P2P_BAR0__REG_SYS_BAR_MASK 0xf0
4692 #define MC_XPB_P2P_BAR0__REG_SYS_BAR__SHIFT 0x4
4693 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR_MASK 0xf00
4694 #define MC_XPB_P2P_BAR0__MEM_SYS_BAR__SHIFT 0x8
4695 #define MC_XPB_P2P_BAR0__VALID_MASK 0x1000
4696 #define MC_XPB_P2P_BAR0__VALID__SHIFT 0xc
4697 #define MC_XPB_P2P_BAR0__SEND_DIS_MASK 0x2000
4698 #define MC_XPB_P2P_BAR0__SEND_DIS__SHIFT 0xd
4699 #define MC_XPB_P2P_BAR0__COMPRESS_DIS_MASK 0x4000
4700 #define MC_XPB_P2P_BAR0__COMPRESS_DIS__SHIFT 0xe
4701 #define MC_XPB_P2P_BAR0__RESERVED_MASK 0x8000
4702 #define MC_XPB_P2P_BAR0__RESERVED__SHIFT 0xf
4703 #define MC_XPB_P2P_BAR0__ADDRESS_MASK 0xffff0000
4704 #define MC_XPB_P2P_BAR0__ADDRESS__SHIFT 0x10
4705 #define MC_XPB_P2P_BAR1__HOST_FLUSH_MASK 0xf
4706 #define MC_XPB_P2P_BAR1__HOST_FLUSH__SHIFT 0x0
4707 #define MC_XPB_P2P_BAR1__REG_SYS_BAR_MASK 0xf0
4708 #define MC_XPB_P2P_BAR1__REG_SYS_BAR__SHIFT 0x4
4709 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR_MASK 0xf00
4710 #define MC_XPB_P2P_BAR1__MEM_SYS_BAR__SHIFT 0x8
4711 #define MC_XPB_P2P_BAR1__VALID_MASK 0x1000
4712 #define MC_XPB_P2P_BAR1__VALID__SHIFT 0xc
4713 #define MC_XPB_P2P_BAR1__SEND_DIS_MASK 0x2000
4714 #define MC_XPB_P2P_BAR1__SEND_DIS__SHIFT 0xd
4715 #define MC_XPB_P2P_BAR1__COMPRESS_DIS_MASK 0x4000
4716 #define MC_XPB_P2P_BAR1__COMPRESS_DIS__SHIFT 0xe
4717 #define MC_XPB_P2P_BAR1__RESERVED_MASK 0x8000
4718 #define MC_XPB_P2P_BAR1__RESERVED__SHIFT 0xf
4719 #define MC_XPB_P2P_BAR1__ADDRESS_MASK 0xffff0000
4720 #define MC_XPB_P2P_BAR1__ADDRESS__SHIFT 0x10
4721 #define MC_XPB_P2P_BAR2__HOST_FLUSH_MASK 0xf
4722 #define MC_XPB_P2P_BAR2__HOST_FLUSH__SHIFT 0x0
4723 #define MC_XPB_P2P_BAR2__REG_SYS_BAR_MASK 0xf0
4724 #define MC_XPB_P2P_BAR2__REG_SYS_BAR__SHIFT 0x4
4725 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR_MASK 0xf00
4726 #define MC_XPB_P2P_BAR2__MEM_SYS_BAR__SHIFT 0x8
4727 #define MC_XPB_P2P_BAR2__VALID_MASK 0x1000
4728 #define MC_XPB_P2P_BAR2__VALID__SHIFT 0xc
4729 #define MC_XPB_P2P_BAR2__SEND_DIS_MASK 0x2000
4730 #define MC_XPB_P2P_BAR2__SEND_DIS__SHIFT 0xd
4731 #define MC_XPB_P2P_BAR2__COMPRESS_DIS_MASK 0x4000
4732 #define MC_XPB_P2P_BAR2__COMPRESS_DIS__SHIFT 0xe
4733 #define MC_XPB_P2P_BAR2__RESERVED_MASK 0x8000
4734 #define MC_XPB_P2P_BAR2__RESERVED__SHIFT 0xf
4735 #define MC_XPB_P2P_BAR2__ADDRESS_MASK 0xffff0000
4736 #define MC_XPB_P2P_BAR2__ADDRESS__SHIFT 0x10
4737 #define MC_XPB_P2P_BAR3__HOST_FLUSH_MASK 0xf
4738 #define MC_XPB_P2P_BAR3__HOST_FLUSH__SHIFT 0x0
4739 #define MC_XPB_P2P_BAR3__REG_SYS_BAR_MASK 0xf0
4740 #define MC_XPB_P2P_BAR3__REG_SYS_BAR__SHIFT 0x4
4741 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR_MASK 0xf00
4742 #define MC_XPB_P2P_BAR3__MEM_SYS_BAR__SHIFT 0x8
4743 #define MC_XPB_P2P_BAR3__VALID_MASK 0x1000
4744 #define MC_XPB_P2P_BAR3__VALID__SHIFT 0xc
4745 #define MC_XPB_P2P_BAR3__SEND_DIS_MASK 0x2000
4746 #define MC_XPB_P2P_BAR3__SEND_DIS__SHIFT 0xd
4747 #define MC_XPB_P2P_BAR3__COMPRESS_DIS_MASK 0x4000
4748 #define MC_XPB_P2P_BAR3__COMPRESS_DIS__SHIFT 0xe
4749 #define MC_XPB_P2P_BAR3__RESERVED_MASK 0x8000
4750 #define MC_XPB_P2P_BAR3__RESERVED__SHIFT 0xf
4751 #define MC_XPB_P2P_BAR3__ADDRESS_MASK 0xffff0000
4752 #define MC_XPB_P2P_BAR3__ADDRESS__SHIFT 0x10
4753 #define MC_XPB_P2P_BAR4__HOST_FLUSH_MASK 0xf
4754 #define MC_XPB_P2P_BAR4__HOST_FLUSH__SHIFT 0x0
4755 #define MC_XPB_P2P_BAR4__REG_SYS_BAR_MASK 0xf0
4756 #define MC_XPB_P2P_BAR4__REG_SYS_BAR__SHIFT 0x4
4757 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR_MASK 0xf00
4758 #define MC_XPB_P2P_BAR4__MEM_SYS_BAR__SHIFT 0x8
4759 #define MC_XPB_P2P_BAR4__VALID_MASK 0x1000
4760 #define MC_XPB_P2P_BAR4__VALID__SHIFT 0xc
4761 #define MC_XPB_P2P_BAR4__SEND_DIS_MASK 0x2000
4762 #define MC_XPB_P2P_BAR4__SEND_DIS__SHIFT 0xd
4763 #define MC_XPB_P2P_BAR4__COMPRESS_DIS_MASK 0x4000
4764 #define MC_XPB_P2P_BAR4__COMPRESS_DIS__SHIFT 0xe
4765 #define MC_XPB_P2P_BAR4__RESERVED_MASK 0x8000
4766 #define MC_XPB_P2P_BAR4__RESERVED__SHIFT 0xf
4767 #define MC_XPB_P2P_BAR4__ADDRESS_MASK 0xffff0000
4768 #define MC_XPB_P2P_BAR4__ADDRESS__SHIFT 0x10
4769 #define MC_XPB_P2P_BAR5__HOST_FLUSH_MASK 0xf
4770 #define MC_XPB_P2P_BAR5__HOST_FLUSH__SHIFT 0x0
4771 #define MC_XPB_P2P_BAR5__REG_SYS_BAR_MASK 0xf0
4772 #define MC_XPB_P2P_BAR5__REG_SYS_BAR__SHIFT 0x4
4773 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR_MASK 0xf00
4774 #define MC_XPB_P2P_BAR5__MEM_SYS_BAR__SHIFT 0x8
4775 #define MC_XPB_P2P_BAR5__VALID_MASK 0x1000
4776 #define MC_XPB_P2P_BAR5__VALID__SHIFT 0xc
4777 #define MC_XPB_P2P_BAR5__SEND_DIS_MASK 0x2000
4778 #define MC_XPB_P2P_BAR5__SEND_DIS__SHIFT 0xd
4779 #define MC_XPB_P2P_BAR5__COMPRESS_DIS_MASK 0x4000
4780 #define MC_XPB_P2P_BAR5__COMPRESS_DIS__SHIFT 0xe
4781 #define MC_XPB_P2P_BAR5__RESERVED_MASK 0x8000
4782 #define MC_XPB_P2P_BAR5__RESERVED__SHIFT 0xf
4783 #define MC_XPB_P2P_BAR5__ADDRESS_MASK 0xffff0000
4784 #define MC_XPB_P2P_BAR5__ADDRESS__SHIFT 0x10
4785 #define MC_XPB_P2P_BAR6__HOST_FLUSH_MASK 0xf
4786 #define MC_XPB_P2P_BAR6__HOST_FLUSH__SHIFT 0x0
4787 #define MC_XPB_P2P_BAR6__REG_SYS_BAR_MASK 0xf0
4788 #define MC_XPB_P2P_BAR6__REG_SYS_BAR__SHIFT 0x4
4789 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR_MASK 0xf00
4790 #define MC_XPB_P2P_BAR6__MEM_SYS_BAR__SHIFT 0x8
4791 #define MC_XPB_P2P_BAR6__VALID_MASK 0x1000
4792 #define MC_XPB_P2P_BAR6__VALID__SHIFT 0xc
4793 #define MC_XPB_P2P_BAR6__SEND_DIS_MASK 0x2000
4794 #define MC_XPB_P2P_BAR6__SEND_DIS__SHIFT 0xd
4795 #define MC_XPB_P2P_BAR6__COMPRESS_DIS_MASK 0x4000
4796 #define MC_XPB_P2P_BAR6__COMPRESS_DIS__SHIFT 0xe
4797 #define MC_XPB_P2P_BAR6__RESERVED_MASK 0x8000
4798 #define MC_XPB_P2P_BAR6__RESERVED__SHIFT 0xf
4799 #define MC_XPB_P2P_BAR6__ADDRESS_MASK 0xffff0000
4800 #define MC_XPB_P2P_BAR6__ADDRESS__SHIFT 0x10
4801 #define MC_XPB_P2P_BAR7__HOST_FLUSH_MASK 0xf
4802 #define MC_XPB_P2P_BAR7__HOST_FLUSH__SHIFT 0x0
4803 #define MC_XPB_P2P_BAR7__REG_SYS_BAR_MASK 0xf0
4804 #define MC_XPB_P2P_BAR7__REG_SYS_BAR__SHIFT 0x4
4805 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR_MASK 0xf00
4806 #define MC_XPB_P2P_BAR7__MEM_SYS_BAR__SHIFT 0x8
4807 #define MC_XPB_P2P_BAR7__VALID_MASK 0x1000
4808 #define MC_XPB_P2P_BAR7__VALID__SHIFT 0xc
4809 #define MC_XPB_P2P_BAR7__SEND_DIS_MASK 0x2000
4810 #define MC_XPB_P2P_BAR7__SEND_DIS__SHIFT 0xd
4811 #define MC_XPB_P2P_BAR7__COMPRESS_DIS_MASK 0x4000
4812 #define MC_XPB_P2P_BAR7__COMPRESS_DIS__SHIFT 0xe
4813 #define MC_XPB_P2P_BAR7__RESERVED_MASK 0x8000
4814 #define MC_XPB_P2P_BAR7__RESERVED__SHIFT 0xf
4815 #define MC_XPB_P2P_BAR7__ADDRESS_MASK 0xffff0000
4816 #define MC_XPB_P2P_BAR7__ADDRESS__SHIFT 0x10
4817 #define MC_XPB_P2P_BAR_SETUP__SEL_MASK 0xff
4818 #define MC_XPB_P2P_BAR_SETUP__SEL__SHIFT 0x0
4819 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR_MASK 0xf00
4820 #define MC_XPB_P2P_BAR_SETUP__REG_SYS_BAR__SHIFT 0x8
4821 #define MC_XPB_P2P_BAR_SETUP__VALID_MASK 0x1000
4822 #define MC_XPB_P2P_BAR_SETUP__VALID__SHIFT 0xc
4823 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS_MASK 0x2000
4824 #define MC_XPB_P2P_BAR_SETUP__SEND_DIS__SHIFT 0xd
4825 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS_MASK 0x4000
4826 #define MC_XPB_P2P_BAR_SETUP__COMPRESS_DIS__SHIFT 0xe
4827 #define MC_XPB_P2P_BAR_SETUP__RESERVED_MASK 0x8000
4828 #define MC_XPB_P2P_BAR_SETUP__RESERVED__SHIFT 0xf
4829 #define MC_XPB_P2P_BAR_SETUP__ADDRESS_MASK 0xffff0000
4830 #define MC_XPB_P2P_BAR_SETUP__ADDRESS__SHIFT 0x10
4831 #define MC_XPB_P2P_BAR_DEBUG__SEL_MASK 0xff
4832 #define MC_XPB_P2P_BAR_DEBUG__SEL__SHIFT 0x0
4833 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH_MASK 0xf00
4834 #define MC_XPB_P2P_BAR_DEBUG__HOST_FLUSH__SHIFT 0x8
4835 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR_MASK 0xf000
4836 #define MC_XPB_P2P_BAR_DEBUG__MEM_SYS_BAR__SHIFT 0xc
4837 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN_MASK 0xff
4838 #define MC_XPB_P2P_BAR_DELTA_ABOVE__EN__SHIFT 0x0
4839 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA_MASK 0xfffff00
4840 #define MC_XPB_P2P_BAR_DELTA_ABOVE__DELTA__SHIFT 0x8
4841 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN_MASK 0xff
4842 #define MC_XPB_P2P_BAR_DELTA_BELOW__EN__SHIFT 0x0
4843 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA_MASK 0xfffff00
4844 #define MC_XPB_P2P_BAR_DELTA_BELOW__DELTA__SHIFT 0x8
4845 #define MC_XPB_PEER_SYS_BAR0__VALID_MASK 0x1
4846 #define MC_XPB_PEER_SYS_BAR0__VALID__SHIFT 0x0
4847 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4848 #define MC_XPB_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4849 #define MC_XPB_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4850 #define MC_XPB_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4851 #define MC_XPB_PEER_SYS_BAR1__VALID_MASK 0x1
4852 #define MC_XPB_PEER_SYS_BAR1__VALID__SHIFT 0x0
4853 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4854 #define MC_XPB_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4855 #define MC_XPB_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4856 #define MC_XPB_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4857 #define MC_XPB_PEER_SYS_BAR2__VALID_MASK 0x1
4858 #define MC_XPB_PEER_SYS_BAR2__VALID__SHIFT 0x0
4859 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4860 #define MC_XPB_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4861 #define MC_XPB_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4862 #define MC_XPB_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4863 #define MC_XPB_PEER_SYS_BAR3__VALID_MASK 0x1
4864 #define MC_XPB_PEER_SYS_BAR3__VALID__SHIFT 0x0
4865 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4866 #define MC_XPB_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4867 #define MC_XPB_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4868 #define MC_XPB_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4869 #define MC_XPB_PEER_SYS_BAR4__VALID_MASK 0x1
4870 #define MC_XPB_PEER_SYS_BAR4__VALID__SHIFT 0x0
4871 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK_MASK 0x2
4872 #define MC_XPB_PEER_SYS_BAR4__SIDE_OK__SHIFT 0x1
4873 #define MC_XPB_PEER_SYS_BAR4__ADDR_MASK 0x7fffffc
4874 #define MC_XPB_PEER_SYS_BAR4__ADDR__SHIFT 0x2
4875 #define MC_XPB_PEER_SYS_BAR5__VALID_MASK 0x1
4876 #define MC_XPB_PEER_SYS_BAR5__VALID__SHIFT 0x0
4877 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK_MASK 0x2
4878 #define MC_XPB_PEER_SYS_BAR5__SIDE_OK__SHIFT 0x1
4879 #define MC_XPB_PEER_SYS_BAR5__ADDR_MASK 0x7fffffc
4880 #define MC_XPB_PEER_SYS_BAR5__ADDR__SHIFT 0x2
4881 #define MC_XPB_PEER_SYS_BAR6__VALID_MASK 0x1
4882 #define MC_XPB_PEER_SYS_BAR6__VALID__SHIFT 0x0
4883 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK_MASK 0x2
4884 #define MC_XPB_PEER_SYS_BAR6__SIDE_OK__SHIFT 0x1
4885 #define MC_XPB_PEER_SYS_BAR6__ADDR_MASK 0x7fffffc
4886 #define MC_XPB_PEER_SYS_BAR6__ADDR__SHIFT 0x2
4887 #define MC_XPB_PEER_SYS_BAR7__VALID_MASK 0x1
4888 #define MC_XPB_PEER_SYS_BAR7__VALID__SHIFT 0x0
4889 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK_MASK 0x2
4890 #define MC_XPB_PEER_SYS_BAR7__SIDE_OK__SHIFT 0x1
4891 #define MC_XPB_PEER_SYS_BAR7__ADDR_MASK 0x7fffffc
4892 #define MC_XPB_PEER_SYS_BAR7__ADDR__SHIFT 0x2
4893 #define MC_XPB_PEER_SYS_BAR8__VALID_MASK 0x1
4894 #define MC_XPB_PEER_SYS_BAR8__VALID__SHIFT 0x0
4895 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK_MASK 0x2
4896 #define MC_XPB_PEER_SYS_BAR8__SIDE_OK__SHIFT 0x1
4897 #define MC_XPB_PEER_SYS_BAR8__ADDR_MASK 0x7fffffc
4898 #define MC_XPB_PEER_SYS_BAR8__ADDR__SHIFT 0x2
4899 #define MC_XPB_PEER_SYS_BAR9__VALID_MASK 0x1
4900 #define MC_XPB_PEER_SYS_BAR9__VALID__SHIFT 0x0
4901 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK_MASK 0x2
4902 #define MC_XPB_PEER_SYS_BAR9__SIDE_OK__SHIFT 0x1
4903 #define MC_XPB_PEER_SYS_BAR9__ADDR_MASK 0x7fffffc
4904 #define MC_XPB_PEER_SYS_BAR9__ADDR__SHIFT 0x2
4905 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID_MASK 0x1
4906 #define MC_XPB_XDMA_PEER_SYS_BAR0__VALID__SHIFT 0x0
4907 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK_MASK 0x2
4908 #define MC_XPB_XDMA_PEER_SYS_BAR0__SIDE_OK__SHIFT 0x1
4909 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR_MASK 0x7fffffc
4910 #define MC_XPB_XDMA_PEER_SYS_BAR0__ADDR__SHIFT 0x2
4911 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID_MASK 0x1
4912 #define MC_XPB_XDMA_PEER_SYS_BAR1__VALID__SHIFT 0x0
4913 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK_MASK 0x2
4914 #define MC_XPB_XDMA_PEER_SYS_BAR1__SIDE_OK__SHIFT 0x1
4915 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR_MASK 0x7fffffc
4916 #define MC_XPB_XDMA_PEER_SYS_BAR1__ADDR__SHIFT 0x2
4917 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID_MASK 0x1
4918 #define MC_XPB_XDMA_PEER_SYS_BAR2__VALID__SHIFT 0x0
4919 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK_MASK 0x2
4920 #define MC_XPB_XDMA_PEER_SYS_BAR2__SIDE_OK__SHIFT 0x1
4921 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR_MASK 0x7fffffc
4922 #define MC_XPB_XDMA_PEER_SYS_BAR2__ADDR__SHIFT 0x2
4923 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID_MASK 0x1
4924 #define MC_XPB_XDMA_PEER_SYS_BAR3__VALID__SHIFT 0x0
4925 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK_MASK 0x2
4926 #define MC_XPB_XDMA_PEER_SYS_BAR3__SIDE_OK__SHIFT 0x1
4927 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR_MASK 0x7fffffc
4928 #define MC_XPB_XDMA_PEER_SYS_BAR3__ADDR__SHIFT 0x2
4929 #define MC_XPB_CLK_GAT__ONDLY_MASK 0x3f
4930 #define MC_XPB_CLK_GAT__ONDLY__SHIFT 0x0
4931 #define MC_XPB_CLK_GAT__OFFDLY_MASK 0xfc0
4932 #define MC_XPB_CLK_GAT__OFFDLY__SHIFT 0x6
4933 #define MC_XPB_CLK_GAT__RDYDLY_MASK 0x3f000
4934 #define MC_XPB_CLK_GAT__RDYDLY__SHIFT 0xc
4935 #define MC_XPB_CLK_GAT__ENABLE_MASK 0x40000
4936 #define MC_XPB_CLK_GAT__ENABLE__SHIFT 0x12
4937 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK 0x80000
4938 #define MC_XPB_CLK_GAT__MEM_LS_ENABLE__SHIFT 0x13
4939 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD_MASK 0xff
4940 #define MC_XPB_INTF_CFG__RPB_WRREQ_CRD__SHIFT 0x0
4941 #define MC_XPB_INTF_CFG__MC_WRRET_ASK_MASK 0xff00
4942 #define MC_XPB_INTF_CFG__MC_WRRET_ASK__SHIFT 0x8
4943 #define MC_XPB_INTF_CFG__XSP_REQ_CRD_MASK 0x7f0000
4944 #define MC_XPB_INTF_CFG__XSP_REQ_CRD__SHIFT 0x10
4945 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL_MASK 0x800000
4946 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_SEL__SHIFT 0x17
4947 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL_MASK 0x1000000
4948 #define MC_XPB_INTF_CFG__BIF_REG_SNOOP_VAL__SHIFT 0x18
4949 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL_MASK 0x2000000
4950 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_SEL__SHIFT 0x19
4951 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL_MASK 0x4000000
4952 #define MC_XPB_INTF_CFG__BIF_MEM_SNOOP_VAL__SHIFT 0x1a
4953 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL_MASK 0x18000000
4954 #define MC_XPB_INTF_CFG__XSP_SNOOP_SEL__SHIFT 0x1b
4955 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL_MASK 0x20000000
4956 #define MC_XPB_INTF_CFG__XSP_SNOOP_VAL__SHIFT 0x1d
4957 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL_MASK 0x40000000
4958 #define MC_XPB_INTF_CFG__XSP_ORDERING_SEL__SHIFT 0x1e
4959 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL_MASK 0x80000000
4960 #define MC_XPB_INTF_CFG__XSP_ORDERING_VAL__SHIFT 0x1f
4961 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD_MASK 0xff
4962 #define MC_XPB_INTF_STS__RPB_WRREQ_CRD__SHIFT 0x0
4963 #define MC_XPB_INTF_STS__XSP_REQ_CRD_MASK 0x7f00
4964 #define MC_XPB_INTF_STS__XSP_REQ_CRD__SHIFT 0x8
4965 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL_MASK 0x8000
4966 #define MC_XPB_INTF_STS__HOP_DATA_BUF_FULL__SHIFT 0xf
4967 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL_MASK 0x10000
4968 #define MC_XPB_INTF_STS__HOP_ATTR_BUF_FULL__SHIFT 0x10
4969 #define MC_XPB_INTF_STS__CNS_BUF_FULL_MASK 0x20000
4970 #define MC_XPB_INTF_STS__CNS_BUF_FULL__SHIFT 0x11
4971 #define MC_XPB_INTF_STS__CNS_BUF_BUSY_MASK 0x40000
4972 #define MC_XPB_INTF_STS__CNS_BUF_BUSY__SHIFT 0x12
4973 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD_MASK 0x7f80000
4974 #define MC_XPB_INTF_STS__RPB_RDREQ_CRD__SHIFT 0x13
4975 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF_MASK 0x1
4976 #define MC_XPB_PIPE_STS__WCB_ANY_PBUF__SHIFT 0x0
4977 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT_MASK 0xfe
4978 #define MC_XPB_PIPE_STS__WCB_HST_DATA_BUF_CNT__SHIFT 0x1
4979 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT_MASK 0x7f00
4980 #define MC_XPB_PIPE_STS__WCB_SID_DATA_BUF_CNT__SHIFT 0x8
4981 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL_MASK 0x8000
4982 #define MC_XPB_PIPE_STS__WCB_HST_RD_PTR_BUF_FULL__SHIFT 0xf
4983 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL_MASK 0x10000
4984 #define MC_XPB_PIPE_STS__WCB_SID_RD_PTR_BUF_FULL__SHIFT 0x10
4985 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL_MASK 0x20000
4986 #define MC_XPB_PIPE_STS__WCB_HST_REQ_FIFO_FULL__SHIFT 0x11
4987 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL_MASK 0x40000
4988 #define MC_XPB_PIPE_STS__WCB_SID_REQ_FIFO_FULL__SHIFT 0x12
4989 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL_MASK 0x80000
4990 #define MC_XPB_PIPE_STS__WCB_HST_REQ_OBUF_FULL__SHIFT 0x13
4991 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL_MASK 0x100000
4992 #define MC_XPB_PIPE_STS__WCB_SID_REQ_OBUF_FULL__SHIFT 0x14
4993 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL_MASK 0x200000
4994 #define MC_XPB_PIPE_STS__WCB_HST_DATA_OBUF_FULL__SHIFT 0x15
4995 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL_MASK 0x400000
4996 #define MC_XPB_PIPE_STS__WCB_SID_DATA_OBUF_FULL__SHIFT 0x16
4997 #define MC_XPB_PIPE_STS__RET_BUF_FULL_MASK 0x800000
4998 #define MC_XPB_PIPE_STS__RET_BUF_FULL__SHIFT 0x17
4999 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS_MASK 0xff000000
5000 #define MC_XPB_PIPE_STS__XPB_CLK_BUSY_BITS__SHIFT 0x18
5001 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB_MASK 0x1
5002 #define MC_XPB_SUB_CTRL__WRREQ_BYPASS_XPB__SHIFT 0x0
5003 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ_MASK 0x2
5004 #define MC_XPB_SUB_CTRL__STALL_CNS_RTR_REQ__SHIFT 0x1
5005 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ_MASK 0x4
5006 #define MC_XPB_SUB_CTRL__STALL_RTR_RPB_WRREQ__SHIFT 0x2
5007 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ_MASK 0x8
5008 #define MC_XPB_SUB_CTRL__STALL_RTR_MAP_REQ__SHIFT 0x3
5009 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ_MASK 0x10
5010 #define MC_XPB_SUB_CTRL__STALL_MAP_WCB_REQ__SHIFT 0x4
5011 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ_MASK 0x20
5012 #define MC_XPB_SUB_CTRL__STALL_WCB_SID_REQ__SHIFT 0x5
5013 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND_MASK 0x40
5014 #define MC_XPB_SUB_CTRL__STALL_MC_XSP_REQ_SEND__SHIFT 0x6
5015 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ_MASK 0x80
5016 #define MC_XPB_SUB_CTRL__STALL_WCB_HST_REQ__SHIFT 0x7
5017 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ_MASK 0x100
5018 #define MC_XPB_SUB_CTRL__STALL_HST_HOP_REQ__SHIFT 0x8
5019 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR_MASK 0x200
5020 #define MC_XPB_SUB_CTRL__STALL_XPB_RPB_REQ_ATTR__SHIFT 0x9
5021 #define MC_XPB_SUB_CTRL__RESET_CNS_MASK 0x400
5022 #define MC_XPB_SUB_CTRL__RESET_CNS__SHIFT 0xa
5023 #define MC_XPB_SUB_CTRL__RESET_RTR_MASK 0x800
5024 #define MC_XPB_SUB_CTRL__RESET_RTR__SHIFT 0xb
5025 #define MC_XPB_SUB_CTRL__RESET_RET_MASK 0x1000
5026 #define MC_XPB_SUB_CTRL__RESET_RET__SHIFT 0xc
5027 #define MC_XPB_SUB_CTRL__RESET_MAP_MASK 0x2000
5028 #define MC_XPB_SUB_CTRL__RESET_MAP__SHIFT 0xd
5029 #define MC_XPB_SUB_CTRL__RESET_WCB_MASK 0x4000
5030 #define MC_XPB_SUB_CTRL__RESET_WCB__SHIFT 0xe
5031 #define MC_XPB_SUB_CTRL__RESET_HST_MASK 0x8000
5032 #define MC_XPB_SUB_CTRL__RESET_HST__SHIFT 0xf
5033 #define MC_XPB_SUB_CTRL__RESET_HOP_MASK 0x10000
5034 #define MC_XPB_SUB_CTRL__RESET_HOP__SHIFT 0x10
5035 #define MC_XPB_SUB_CTRL__RESET_SID_MASK 0x20000
5036 #define MC_XPB_SUB_CTRL__RESET_SID__SHIFT 0x11
5037 #define MC_XPB_SUB_CTRL__RESET_SRB_MASK 0x40000
5038 #define MC_XPB_SUB_CTRL__RESET_SRB__SHIFT 0x12
5039 #define MC_XPB_SUB_CTRL__RESET_CGR_MASK 0x80000
5040 #define MC_XPB_SUB_CTRL__RESET_CGR__SHIFT 0x13
5041 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM_MASK 0xffff
5042 #define MC_XPB_MAP_INVERT_FLUSH_NUM_LSB__ALTER_FLUSH_NUM__SHIFT 0x0
5043 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH_MASK 0x3f
5044 #define MC_XPB_PERF_KNOBS__CNS_FIFO_DEPTH__SHIFT 0x0
5045 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH_MASK 0xfc0
5046 #define MC_XPB_PERF_KNOBS__WCB_HST_FIFO_DEPTH__SHIFT 0x6
5047 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH_MASK 0x3f000
5048 #define MC_XPB_PERF_KNOBS__WCB_SID_FIFO_DEPTH__SHIFT 0xc
5049 #define MC_XPB_STICKY__BITS_MASK 0xffffffff
5050 #define MC_XPB_STICKY__BITS__SHIFT 0x0
5051 #define MC_XPB_STICKY_W1C__BITS_MASK 0xffffffff
5052 #define MC_XPB_STICKY_W1C__BITS__SHIFT 0x0
5053 #define MC_XPB_MISC_CFG__FIELDNAME0_MASK 0xff
5054 #define MC_XPB_MISC_CFG__FIELDNAME0__SHIFT 0x0
5055 #define MC_XPB_MISC_CFG__FIELDNAME1_MASK 0xff00
5056 #define MC_XPB_MISC_CFG__FIELDNAME1__SHIFT 0x8
5057 #define MC_XPB_MISC_CFG__FIELDNAME2_MASK 0xff0000
5058 #define MC_XPB_MISC_CFG__FIELDNAME2__SHIFT 0x10
5059 #define MC_XPB_MISC_CFG__FIELDNAME3_MASK 0x7f000000
5060 #define MC_XPB_MISC_CFG__FIELDNAME3__SHIFT 0x18
5061 #define MC_XPB_MISC_CFG__TRIGGERNAME_MASK 0x80000000
5062 #define MC_XPB_MISC_CFG__TRIGGERNAME__SHIFT 0x1f
5063 #define MC_XPB_CLG_CFG20__WCB_NUM_MASK 0xf
5064 #define MC_XPB_CLG_CFG20__WCB_NUM__SHIFT 0x0
5065 #define MC_XPB_CLG_CFG20__LB_TYPE_MASK 0x70
5066 #define MC_XPB_CLG_CFG20__LB_TYPE__SHIFT 0x4
5067 #define MC_XPB_CLG_CFG20__P2P_BAR_MASK 0x380
5068 #define MC_XPB_CLG_CFG20__P2P_BAR__SHIFT 0x7
5069 #define MC_XPB_CLG_CFG20__HOST_FLUSH_MASK 0x3c00
5070 #define MC_XPB_CLG_CFG20__HOST_FLUSH__SHIFT 0xa
5071 #define MC_XPB_CLG_CFG20__SIDE_FLUSH_MASK 0x3c000
5072 #define MC_XPB_CLG_CFG20__SIDE_FLUSH__SHIFT 0xe
5073 #define MC_XPB_CLG_CFG21__WCB_NUM_MASK 0xf
5074 #define MC_XPB_CLG_CFG21__WCB_NUM__SHIFT 0x0
5075 #define MC_XPB_CLG_CFG21__LB_TYPE_MASK 0x70
5076 #define MC_XPB_CLG_CFG21__LB_TYPE__SHIFT 0x4
5077 #define MC_XPB_CLG_CFG21__P2P_BAR_MASK 0x380
5078 #define MC_XPB_CLG_CFG21__P2P_BAR__SHIFT 0x7
5079 #define MC_XPB_CLG_CFG21__HOST_FLUSH_MASK 0x3c00
5080 #define MC_XPB_CLG_CFG21__HOST_FLUSH__SHIFT 0xa
5081 #define MC_XPB_CLG_CFG21__SIDE_FLUSH_MASK 0x3c000
5082 #define MC_XPB_CLG_CFG21__SIDE_FLUSH__SHIFT 0xe
5083 #define MC_XPB_CLG_CFG22__WCB_NUM_MASK 0xf
5084 #define MC_XPB_CLG_CFG22__WCB_NUM__SHIFT 0x0
5085 #define MC_XPB_CLG_CFG22__LB_TYPE_MASK 0x70
5086 #define MC_XPB_CLG_CFG22__LB_TYPE__SHIFT 0x4
5087 #define MC_XPB_CLG_CFG22__P2P_BAR_MASK 0x380
5088 #define MC_XPB_CLG_CFG22__P2P_BAR__SHIFT 0x7
5089 #define MC_XPB_CLG_CFG22__HOST_FLUSH_MASK 0x3c00
5090 #define MC_XPB_CLG_CFG22__HOST_FLUSH__SHIFT 0xa
5091 #define MC_XPB_CLG_CFG22__SIDE_FLUSH_MASK 0x3c000
5092 #define MC_XPB_CLG_CFG22__SIDE_FLUSH__SHIFT 0xe
5093 #define MC_XPB_CLG_CFG23__WCB_NUM_MASK 0xf
5094 #define MC_XPB_CLG_CFG23__WCB_NUM__SHIFT 0x0
5095 #define MC_XPB_CLG_CFG23__LB_TYPE_MASK 0x70
5096 #define MC_XPB_CLG_CFG23__LB_TYPE__SHIFT 0x4
5097 #define MC_XPB_CLG_CFG23__P2P_BAR_MASK 0x380
5098 #define MC_XPB_CLG_CFG23__P2P_BAR__SHIFT 0x7
5099 #define MC_XPB_CLG_CFG23__HOST_FLUSH_MASK 0x3c00
5100 #define MC_XPB_CLG_CFG23__HOST_FLUSH__SHIFT 0xa
5101 #define MC_XPB_CLG_CFG23__SIDE_FLUSH_MASK 0x3c000
5102 #define MC_XPB_CLG_CFG23__SIDE_FLUSH__SHIFT 0xe
5103 #define MC_XPB_CLG_CFG24__WCB_NUM_MASK 0xf
5104 #define MC_XPB_CLG_CFG24__WCB_NUM__SHIFT 0x0
5105 #define MC_XPB_CLG_CFG24__LB_TYPE_MASK 0x70
5106 #define MC_XPB_CLG_CFG24__LB_TYPE__SHIFT 0x4
5107 #define MC_XPB_CLG_CFG24__P2P_BAR_MASK 0x380
5108 #define MC_XPB_CLG_CFG24__P2P_BAR__SHIFT 0x7
5109 #define MC_XPB_CLG_CFG24__HOST_FLUSH_MASK 0x3c00
5110 #define MC_XPB_CLG_CFG24__HOST_FLUSH__SHIFT 0xa
5111 #define MC_XPB_CLG_CFG24__SIDE_FLUSH_MASK 0x3c000
5112 #define MC_XPB_CLG_CFG24__SIDE_FLUSH__SHIFT 0xe
5113 #define MC_XPB_CLG_CFG25__WCB_NUM_MASK 0xf
5114 #define MC_XPB_CLG_CFG25__WCB_NUM__SHIFT 0x0
5115 #define MC_XPB_CLG_CFG25__LB_TYPE_MASK 0x70
5116 #define MC_XPB_CLG_CFG25__LB_TYPE__SHIFT 0x4
5117 #define MC_XPB_CLG_CFG25__P2P_BAR_MASK 0x380
5118 #define MC_XPB_CLG_CFG25__P2P_BAR__SHIFT 0x7
5119 #define MC_XPB_CLG_CFG25__HOST_FLUSH_MASK 0x3c00
5120 #define MC_XPB_CLG_CFG25__HOST_FLUSH__SHIFT 0xa
5121 #define MC_XPB_CLG_CFG25__SIDE_FLUSH_MASK 0x3c000
5122 #define MC_XPB_CLG_CFG25__SIDE_FLUSH__SHIFT 0xe
5123 #define MC_XPB_CLG_CFG26__WCB_NUM_MASK 0xf
5124 #define MC_XPB_CLG_CFG26__WCB_NUM__SHIFT 0x0
5125 #define MC_XPB_CLG_CFG26__LB_TYPE_MASK 0x70
5126 #define MC_XPB_CLG_CFG26__LB_TYPE__SHIFT 0x4
5127 #define MC_XPB_CLG_CFG26__P2P_BAR_MASK 0x380
5128 #define MC_XPB_CLG_CFG26__P2P_BAR__SHIFT 0x7
5129 #define MC_XPB_CLG_CFG26__HOST_FLUSH_MASK 0x3c00
5130 #define MC_XPB_CLG_CFG26__HOST_FLUSH__SHIFT 0xa
5131 #define MC_XPB_CLG_CFG26__SIDE_FLUSH_MASK 0x3c000
5132 #define MC_XPB_CLG_CFG26__SIDE_FLUSH__SHIFT 0xe
5133 #define MC_XPB_CLG_CFG27__WCB_NUM_MASK 0xf
5134 #define MC_XPB_CLG_CFG27__WCB_NUM__SHIFT 0x0
5135 #define MC_XPB_CLG_CFG27__LB_TYPE_MASK 0x70
5136 #define MC_XPB_CLG_CFG27__LB_TYPE__SHIFT 0x4
5137 #define MC_XPB_CLG_CFG27__P2P_BAR_MASK 0x380
5138 #define MC_XPB_CLG_CFG27__P2P_BAR__SHIFT 0x7
5139 #define MC_XPB_CLG_CFG27__HOST_FLUSH_MASK 0x3c00
5140 #define MC_XPB_CLG_CFG27__HOST_FLUSH__SHIFT 0xa
5141 #define MC_XPB_CLG_CFG27__SIDE_FLUSH_MASK 0x3c000
5142 #define MC_XPB_CLG_CFG27__SIDE_FLUSH__SHIFT 0xe
5143 #define MC_XPB_CLG_CFG28__WCB_NUM_MASK 0xf
5144 #define MC_XPB_CLG_CFG28__WCB_NUM__SHIFT 0x0
5145 #define MC_XPB_CLG_CFG28__LB_TYPE_MASK 0x70
5146 #define MC_XPB_CLG_CFG28__LB_TYPE__SHIFT 0x4
5147 #define MC_XPB_CLG_CFG28__P2P_BAR_MASK 0x380
5148 #define MC_XPB_CLG_CFG28__P2P_BAR__SHIFT 0x7
5149 #define MC_XPB_CLG_CFG28__HOST_FLUSH_MASK 0x3c00
5150 #define MC_XPB_CLG_CFG28__HOST_FLUSH__SHIFT 0xa
5151 #define MC_XPB_CLG_CFG28__SIDE_FLUSH_MASK 0x3c000
5152 #define MC_XPB_CLG_CFG28__SIDE_FLUSH__SHIFT 0xe
5153 #define MC_XPB_CLG_CFG29__WCB_NUM_MASK 0xf
5154 #define MC_XPB_CLG_CFG29__WCB_NUM__SHIFT 0x0
5155 #define MC_XPB_CLG_CFG29__LB_TYPE_MASK 0x70
5156 #define MC_XPB_CLG_CFG29__LB_TYPE__SHIFT 0x4
5157 #define MC_XPB_CLG_CFG29__P2P_BAR_MASK 0x380
5158 #define MC_XPB_CLG_CFG29__P2P_BAR__SHIFT 0x7
5159 #define MC_XPB_CLG_CFG29__HOST_FLUSH_MASK 0x3c00
5160 #define MC_XPB_CLG_CFG29__HOST_FLUSH__SHIFT 0xa
5161 #define MC_XPB_CLG_CFG29__SIDE_FLUSH_MASK 0x3c000
5162 #define MC_XPB_CLG_CFG29__SIDE_FLUSH__SHIFT 0xe
5163 #define MC_XPB_CLG_CFG30__WCB_NUM_MASK 0xf
5164 #define MC_XPB_CLG_CFG30__WCB_NUM__SHIFT 0x0
5165 #define MC_XPB_CLG_CFG30__LB_TYPE_MASK 0x70
5166 #define MC_XPB_CLG_CFG30__LB_TYPE__SHIFT 0x4
5167 #define MC_XPB_CLG_CFG30__P2P_BAR_MASK 0x380
5168 #define MC_XPB_CLG_CFG30__P2P_BAR__SHIFT 0x7
5169 #define MC_XPB_CLG_CFG30__HOST_FLUSH_MASK 0x3c00
5170 #define MC_XPB_CLG_CFG30__HOST_FLUSH__SHIFT 0xa
5171 #define MC_XPB_CLG_CFG30__SIDE_FLUSH_MASK 0x3c000
5172 #define MC_XPB_CLG_CFG30__SIDE_FLUSH__SHIFT 0xe
5173 #define MC_XPB_CLG_CFG31__WCB_NUM_MASK 0xf
5174 #define MC_XPB_CLG_CFG31__WCB_NUM__SHIFT 0x0
5175 #define MC_XPB_CLG_CFG31__LB_TYPE_MASK 0x70
5176 #define MC_XPB_CLG_CFG31__LB_TYPE__SHIFT 0x4
5177 #define MC_XPB_CLG_CFG31__P2P_BAR_MASK 0x380
5178 #define MC_XPB_CLG_CFG31__P2P_BAR__SHIFT 0x7
5179 #define MC_XPB_CLG_CFG31__HOST_FLUSH_MASK 0x3c00
5180 #define MC_XPB_CLG_CFG31__HOST_FLUSH__SHIFT 0xa
5181 #define MC_XPB_CLG_CFG31__SIDE_FLUSH_MASK 0x3c000
5182 #define MC_XPB_CLG_CFG31__SIDE_FLUSH__SHIFT 0xe
5183 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD_MASK 0xff
5184 #define MC_XPB_INTF_CFG2__RPB_RDREQ_CRD__SHIFT 0x0
5185 #define MC_XPB_CLG_EXTRA_RD__CMP0_MASK 0xff
5186 #define MC_XPB_CLG_EXTRA_RD__CMP0__SHIFT 0x0
5187 #define MC_XPB_CLG_EXTRA_RD__MSK0_MASK 0xff00
5188 #define MC_XPB_CLG_EXTRA_RD__MSK0__SHIFT 0x8
5189 #define MC_XPB_CLG_EXTRA_RD__VLD0_MASK 0x10000
5190 #define MC_XPB_CLG_EXTRA_RD__VLD0__SHIFT 0x10
5191 #define MC_XPB_CLG_EXTRA_RD__CMP1_MASK 0x1fe0000
5192 #define MC_XPB_CLG_EXTRA_RD__CMP1__SHIFT 0x11
5193 #define MC_XPB_CLG_EXTRA_RD__VLD1_MASK 0x2000000
5194 #define MC_XPB_CLG_EXTRA_RD__VLD1__SHIFT 0x19
5195 #define MC_XPB_CLG_CFG32__WCB_NUM_MASK 0xf
5196 #define MC_XPB_CLG_CFG32__WCB_NUM__SHIFT 0x0
5197 #define MC_XPB_CLG_CFG32__LB_TYPE_MASK 0x70
5198 #define MC_XPB_CLG_CFG32__LB_TYPE__SHIFT 0x4
5199 #define MC_XPB_CLG_CFG32__P2P_BAR_MASK 0x380
5200 #define MC_XPB_CLG_CFG32__P2P_BAR__SHIFT 0x7
5201 #define MC_XPB_CLG_CFG32__HOST_FLUSH_MASK 0x3c00
5202 #define MC_XPB_CLG_CFG32__HOST_FLUSH__SHIFT 0xa
5203 #define MC_XPB_CLG_CFG32__SIDE_FLUSH_MASK 0x3c000
5204 #define MC_XPB_CLG_CFG32__SIDE_FLUSH__SHIFT 0xe
5205 #define MC_XPB_CLG_CFG33__WCB_NUM_MASK 0xf
5206 #define MC_XPB_CLG_CFG33__WCB_NUM__SHIFT 0x0
5207 #define MC_XPB_CLG_CFG33__LB_TYPE_MASK 0x70
5208 #define MC_XPB_CLG_CFG33__LB_TYPE__SHIFT 0x4
5209 #define MC_XPB_CLG_CFG33__P2P_BAR_MASK 0x380
5210 #define MC_XPB_CLG_CFG33__P2P_BAR__SHIFT 0x7
5211 #define MC_XPB_CLG_CFG33__HOST_FLUSH_MASK 0x3c00
5212 #define MC_XPB_CLG_CFG33__HOST_FLUSH__SHIFT 0xa
5213 #define MC_XPB_CLG_CFG33__SIDE_FLUSH_MASK 0x3c000
5214 #define MC_XPB_CLG_CFG33__SIDE_FLUSH__SHIFT 0xe
5215 #define MC_XPB_CLG_CFG34__WCB_NUM_MASK 0xf
5216 #define MC_XPB_CLG_CFG34__WCB_NUM__SHIFT 0x0
5217 #define MC_XPB_CLG_CFG34__LB_TYPE_MASK 0x70
5218 #define MC_XPB_CLG_CFG34__LB_TYPE__SHIFT 0x4
5219 #define MC_XPB_CLG_CFG34__P2P_BAR_MASK 0x380
5220 #define MC_XPB_CLG_CFG34__P2P_BAR__SHIFT 0x7
5221 #define MC_XPB_CLG_CFG34__HOST_FLUSH_MASK 0x3c00
5222 #define MC_XPB_CLG_CFG34__HOST_FLUSH__SHIFT 0xa
5223 #define MC_XPB_CLG_CFG34__SIDE_FLUSH_MASK 0x3c000
5224 #define MC_XPB_CLG_CFG34__SIDE_FLUSH__SHIFT 0xe
5225 #define MC_XPB_CLG_CFG35__WCB_NUM_MASK 0xf
5226 #define MC_XPB_CLG_CFG35__WCB_NUM__SHIFT 0x0
5227 #define MC_XPB_CLG_CFG35__LB_TYPE_MASK 0x70
5228 #define MC_XPB_CLG_CFG35__LB_TYPE__SHIFT 0x4
5229 #define MC_XPB_CLG_CFG35__P2P_BAR_MASK 0x380
5230 #define MC_XPB_CLG_CFG35__P2P_BAR__SHIFT 0x7
5231 #define MC_XPB_CLG_CFG35__HOST_FLUSH_MASK 0x3c00
5232 #define MC_XPB_CLG_CFG35__HOST_FLUSH__SHIFT 0xa
5233 #define MC_XPB_CLG_CFG35__SIDE_FLUSH_MASK 0x3c000
5234 #define MC_XPB_CLG_CFG35__SIDE_FLUSH__SHIFT 0xe
5235 #define MC_XPB_CLG_CFG36__WCB_NUM_MASK 0xf
5236 #define MC_XPB_CLG_CFG36__WCB_NUM__SHIFT 0x0
5237 #define MC_XPB_CLG_CFG36__LB_TYPE_MASK 0x70
5238 #define MC_XPB_CLG_CFG36__LB_TYPE__SHIFT 0x4
5239 #define MC_XPB_CLG_CFG36__P2P_BAR_MASK 0x380
5240 #define MC_XPB_CLG_CFG36__P2P_BAR__SHIFT 0x7
5241 #define MC_XPB_CLG_CFG36__HOST_FLUSH_MASK 0x3c00
5242 #define MC_XPB_CLG_CFG36__HOST_FLUSH__SHIFT 0xa
5243 #define MC_XPB_CLG_CFG36__SIDE_FLUSH_MASK 0x3c000
5244 #define MC_XPB_CLG_CFG36__SIDE_FLUSH__SHIFT 0xe
5245 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3_MASK 0x1
5246 #define MC_XBAR_ADDR_DEC__NO_DIV_BY_3__SHIFT 0x0
5247 #define MC_XBAR_ADDR_DEC__GECC_MASK 0x2
5248 #define MC_XBAR_ADDR_DEC__GECC__SHIFT 0x1
5249 #define MC_XBAR_ADDR_DEC__RB_SPLIT_MASK 0x4
5250 #define MC_XBAR_ADDR_DEC__RB_SPLIT__SHIFT 0x2
5251 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI_MASK 0x8
5252 #define MC_XBAR_ADDR_DEC__RB_SPLIT_COLHI__SHIFT 0x3
5253 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ_MASK 0x1
5254 #define MC_XBAR_REMOTE__WRREQ_EN_GOQ__SHIFT 0x0
5255 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ_MASK 0x2
5256 #define MC_XBAR_REMOTE__RDREQ_EN_GOQ__SHIFT 0x1
5257 #define MC_XBAR_WRREQ_CREDIT__OUT0_MASK 0xff
5258 #define MC_XBAR_WRREQ_CREDIT__OUT0__SHIFT 0x0
5259 #define MC_XBAR_WRREQ_CREDIT__OUT1_MASK 0xff00
5260 #define MC_XBAR_WRREQ_CREDIT__OUT1__SHIFT 0x8
5261 #define MC_XBAR_WRREQ_CREDIT__OUT2_MASK 0xff0000
5262 #define MC_XBAR_WRREQ_CREDIT__OUT2__SHIFT 0x10
5263 #define MC_XBAR_WRREQ_CREDIT__OUT3_MASK 0xff000000
5264 #define MC_XBAR_WRREQ_CREDIT__OUT3__SHIFT 0x18
5265 #define MC_XBAR_RDREQ_CREDIT__OUT0_MASK 0xff
5266 #define MC_XBAR_RDREQ_CREDIT__OUT0__SHIFT 0x0
5267 #define MC_XBAR_RDREQ_CREDIT__OUT1_MASK 0xff00
5268 #define MC_XBAR_RDREQ_CREDIT__OUT1__SHIFT 0x8
5269 #define MC_XBAR_RDREQ_CREDIT__OUT2_MASK 0xff0000
5270 #define MC_XBAR_RDREQ_CREDIT__OUT2__SHIFT 0x10
5271 #define MC_XBAR_RDREQ_CREDIT__OUT3_MASK 0xff000000
5272 #define MC_XBAR_RDREQ_CREDIT__OUT3__SHIFT 0x18
5273 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0_MASK 0xff
5274 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT0__SHIFT 0x0
5275 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1_MASK 0xff00
5276 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT1__SHIFT 0x8
5277 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2_MASK 0xff0000
5278 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT2__SHIFT 0x10
5279 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3_MASK 0xff000000
5280 #define MC_XBAR_RDREQ_PRI_CREDIT__OUT3__SHIFT 0x18
5281 #define MC_XBAR_WRRET_CREDIT1__OUT0_MASK 0xff
5282 #define MC_XBAR_WRRET_CREDIT1__OUT0__SHIFT 0x0
5283 #define MC_XBAR_WRRET_CREDIT1__OUT1_MASK 0xff00
5284 #define MC_XBAR_WRRET_CREDIT1__OUT1__SHIFT 0x8
5285 #define MC_XBAR_WRRET_CREDIT1__OUT2_MASK 0xff0000
5286 #define MC_XBAR_WRRET_CREDIT1__OUT2__SHIFT 0x10
5287 #define MC_XBAR_WRRET_CREDIT1__OUT3_MASK 0xff000000
5288 #define MC_XBAR_WRRET_CREDIT1__OUT3__SHIFT 0x18
5289 #define MC_XBAR_WRRET_CREDIT2__OUT4_MASK 0xff
5290 #define MC_XBAR_WRRET_CREDIT2__OUT4__SHIFT 0x0
5291 #define MC_XBAR_WRRET_CREDIT2__OUT5_MASK 0xff00
5292 #define MC_XBAR_WRRET_CREDIT2__OUT5__SHIFT 0x8
5293 #define MC_XBAR_RDRET_CREDIT1__OUT0_MASK 0xff
5294 #define MC_XBAR_RDRET_CREDIT1__OUT0__SHIFT 0x0
5295 #define MC_XBAR_RDRET_CREDIT1__OUT1_MASK 0xff00
5296 #define MC_XBAR_RDRET_CREDIT1__OUT1__SHIFT 0x8
5297 #define MC_XBAR_RDRET_CREDIT1__OUT2_MASK 0xff0000
5298 #define MC_XBAR_RDRET_CREDIT1__OUT2__SHIFT 0x10
5299 #define MC_XBAR_RDRET_CREDIT1__OUT3_MASK 0xff000000
5300 #define MC_XBAR_RDRET_CREDIT1__OUT3__SHIFT 0x18
5301 #define MC_XBAR_RDRET_CREDIT2__OUT4_MASK 0xff
5302 #define MC_XBAR_RDRET_CREDIT2__OUT4__SHIFT 0x0
5303 #define MC_XBAR_RDRET_CREDIT2__OUT5_MASK 0xff00
5304 #define MC_XBAR_RDRET_CREDIT2__OUT5__SHIFT 0x8
5305 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID_MASK 0xff0000
5306 #define MC_XBAR_RDRET_CREDIT2__HUB_LP_RDRET_SKID__SHIFT 0x10
5307 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0_MASK 0xff
5308 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT0__SHIFT 0x0
5309 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1_MASK 0xff00
5310 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT1__SHIFT 0x8
5311 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2_MASK 0xff0000
5312 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT2__SHIFT 0x10
5313 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3_MASK 0xff000000
5314 #define MC_XBAR_RDRET_PRI_CREDIT1__OUT3__SHIFT 0x18
5315 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4_MASK 0xff
5316 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT4__SHIFT 0x0
5317 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5_MASK 0xff00
5318 #define MC_XBAR_RDRET_PRI_CREDIT2__OUT5__SHIFT 0x8
5319 #define MC_XBAR_CHTRIREMAP__CH0_MASK 0x3
5320 #define MC_XBAR_CHTRIREMAP__CH0__SHIFT 0x0
5321 #define MC_XBAR_CHTRIREMAP__CH1_MASK 0xc
5322 #define MC_XBAR_CHTRIREMAP__CH1__SHIFT 0x2
5323 #define MC_XBAR_CHTRIREMAP__CH2_MASK 0x30
5324 #define MC_XBAR_CHTRIREMAP__CH2__SHIFT 0x4
5325 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT_MASK 0x1
5326 #define MC_XBAR_TWOCHAN__DISABLE_ONEPORT__SHIFT 0x0
5327 #define MC_XBAR_TWOCHAN__CH0_MASK 0x6
5328 #define MC_XBAR_TWOCHAN__CH0__SHIFT 0x1
5329 #define MC_XBAR_TWOCHAN__CH1_MASK 0x18
5330 #define MC_XBAR_TWOCHAN__CH1__SHIFT 0x3
5331 #define MC_XBAR_ARB__HUBRD_HIGHEST_MASK 0x1
5332 #define MC_XBAR_ARB__HUBRD_HIGHEST__SHIFT 0x0
5333 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST_MASK 0x2
5334 #define MC_XBAR_ARB__DISABLE_HUB_STALL_HIGHEST__SHIFT 0x1
5335 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE_MASK 0x4
5336 #define MC_XBAR_ARB__BREAK_BURST_CID_CHANGE__SHIFT 0x2
5337 #define MC_XBAR_ARB__ACP_RDRET_URG_MASK 0x8
5338 #define MC_XBAR_ARB__ACP_RDRET_URG__SHIFT 0x3
5339 #define MC_XBAR_ARB__HDP_RDRET_URG_MASK 0x10
5340 #define MC_XBAR_ARB__HDP_RDRET_URG__SHIFT 0x4
5341 #define MC_XBAR_ARB__BREAK_BURST_BY_URG_MASK 0x20
5342 #define MC_XBAR_ARB__BREAK_BURST_BY_URG__SHIFT 0x5
5343 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0_MASK 0xf
5344 #define MC_XBAR_ARB_MAX_BURST__RD_PORT0__SHIFT 0x0
5345 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1_MASK 0xf0
5346 #define MC_XBAR_ARB_MAX_BURST__RD_PORT1__SHIFT 0x4
5347 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2_MASK 0xf00
5348 #define MC_XBAR_ARB_MAX_BURST__RD_PORT2__SHIFT 0x8
5349 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3_MASK 0xf000
5350 #define MC_XBAR_ARB_MAX_BURST__RD_PORT3__SHIFT 0xc
5351 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0_MASK 0xf0000
5352 #define MC_XBAR_ARB_MAX_BURST__WR_PORT0__SHIFT 0x10
5353 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1_MASK 0xf00000
5354 #define MC_XBAR_ARB_MAX_BURST__WR_PORT1__SHIFT 0x14
5355 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2_MASK 0xf000000
5356 #define MC_XBAR_ARB_MAX_BURST__WR_PORT2__SHIFT 0x18
5357 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3_MASK 0xf0000000
5358 #define MC_XBAR_ARB_MAX_BURST__WR_PORT3__SHIFT 0x1c
5359 #define MC_XBAR_FIFO_MON_CNTL0__START_THRESH_MASK 0xfff
5360 #define MC_XBAR_FIFO_MON_CNTL0__START_THRESH__SHIFT 0x0
5361 #define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH_MASK 0xfff000
5362 #define MC_XBAR_FIFO_MON_CNTL0__STOP_THRESH__SHIFT 0xc
5363 #define MC_XBAR_FIFO_MON_CNTL0__START_MODE_MASK 0x3000000
5364 #define MC_XBAR_FIFO_MON_CNTL0__START_MODE__SHIFT 0x18
5365 #define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE_MASK 0xc000000
5366 #define MC_XBAR_FIFO_MON_CNTL0__STOP_MODE__SHIFT 0x1a
5367 #define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
5368 #define MC_XBAR_FIFO_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
5369 #define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID_MASK 0xff
5370 #define MC_XBAR_FIFO_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
5371 #define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID_MASK 0xff00
5372 #define MC_XBAR_FIFO_MON_CNTL1__START_TRIG_ID__SHIFT 0x8
5373 #define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID_MASK 0xff0000
5374 #define MC_XBAR_FIFO_MON_CNTL1__STOP_TRIG_ID__SHIFT 0x10
5375 #define MC_XBAR_FIFO_MON_CNTL2__MON0_ID_MASK 0xff
5376 #define MC_XBAR_FIFO_MON_CNTL2__MON0_ID__SHIFT 0x0
5377 #define MC_XBAR_FIFO_MON_CNTL2__MON1_ID_MASK 0xff00
5378 #define MC_XBAR_FIFO_MON_CNTL2__MON1_ID__SHIFT 0x8
5379 #define MC_XBAR_FIFO_MON_CNTL2__MON2_ID_MASK 0xff0000
5380 #define MC_XBAR_FIFO_MON_CNTL2__MON2_ID__SHIFT 0x10
5381 #define MC_XBAR_FIFO_MON_CNTL2__MON3_ID_MASK 0xff000000
5382 #define MC_XBAR_FIFO_MON_CNTL2__MON3_ID__SHIFT 0x18
5383 #define MC_XBAR_FIFO_MON_RSLT0__COUNT_MASK 0xffffffff
5384 #define MC_XBAR_FIFO_MON_RSLT0__COUNT__SHIFT 0x0
5385 #define MC_XBAR_FIFO_MON_RSLT1__COUNT_MASK 0xffffffff
5386 #define MC_XBAR_FIFO_MON_RSLT1__COUNT__SHIFT 0x0
5387 #define MC_XBAR_FIFO_MON_RSLT2__COUNT_MASK 0xffffffff
5388 #define MC_XBAR_FIFO_MON_RSLT2__COUNT__SHIFT 0x0
5389 #define MC_XBAR_FIFO_MON_RSLT3__COUNT_MASK 0xffffffff
5390 #define MC_XBAR_FIFO_MON_RSLT3__COUNT__SHIFT 0x0
5391 #define MC_XBAR_FIFO_MON_MAX_THSH__MON0_MASK 0xff
5392 #define MC_XBAR_FIFO_MON_MAX_THSH__MON0__SHIFT 0x0
5393 #define MC_XBAR_FIFO_MON_MAX_THSH__MON1_MASK 0xff00
5394 #define MC_XBAR_FIFO_MON_MAX_THSH__MON1__SHIFT 0x8
5395 #define MC_XBAR_FIFO_MON_MAX_THSH__MON2_MASK 0xff0000
5396 #define MC_XBAR_FIFO_MON_MAX_THSH__MON2__SHIFT 0x10
5397 #define MC_XBAR_FIFO_MON_MAX_THSH__MON3_MASK 0xff000000
5398 #define MC_XBAR_FIFO_MON_MAX_THSH__MON3__SHIFT 0x18
5399 #define MC_XBAR_SPARE0__BIT_MASK 0xffffffff
5400 #define MC_XBAR_SPARE0__BIT__SHIFT 0x0
5401 #define MC_XBAR_SPARE1__BIT_MASK 0xffffffff
5402 #define MC_XBAR_SPARE1__BIT__SHIFT 0x0
5403 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5404 #define MC_CITF_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5405 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5406 #define MC_HUB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5407 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5408 #define MC_RPB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5409 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5410 #define MC_MCBVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5411 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5412 #define MC_MCDVM_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5413 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5414 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5415 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5416 #define MC_ARB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5417 #define ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5418 #define ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5419 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5420 #define MC_CITF_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5421 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5422 #define MC_CITF_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5423 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5424 #define MC_HUB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5425 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5426 #define MC_HUB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5427 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5428 #define MC_MCBVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5429 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5430 #define MC_MCBVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5431 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5432 #define MC_MCDVM_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5433 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5434 #define MC_MCDVM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5435 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5436 #define MC_RPB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5437 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5438 #define MC_RPB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5439 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5440 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5441 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5442 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5443 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5444 #define MC_ARB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5445 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5446 #define MC_ARB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5447 #define ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5448 #define ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5449 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5450 #define ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5451 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5452 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5453 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5454 #define MC_CITF_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5455 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5456 #define MC_CITF_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5457 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5458 #define MC_CITF_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5459 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5460 #define MC_CITF_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5461 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5462 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5463 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5464 #define MC_CITF_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5465 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5466 #define MC_CITF_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5467 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5468 #define MC_CITF_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5469 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5470 #define MC_CITF_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5471 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5472 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5473 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5474 #define MC_CITF_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5475 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5476 #define MC_CITF_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5477 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5478 #define MC_CITF_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5479 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5480 #define MC_CITF_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5481 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5482 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5483 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5484 #define MC_CITF_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5485 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5486 #define MC_CITF_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5487 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5488 #define MC_CITF_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5489 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5490 #define MC_CITF_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5491 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5492 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5493 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5494 #define MC_HUB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5495 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5496 #define MC_HUB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5497 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5498 #define MC_HUB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5499 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5500 #define MC_HUB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5501 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5502 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5503 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5504 #define MC_HUB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5505 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5506 #define MC_HUB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5507 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5508 #define MC_HUB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5509 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5510 #define MC_HUB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5511 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5512 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5513 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5514 #define MC_HUB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5515 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5516 #define MC_HUB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5517 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5518 #define MC_HUB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5519 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5520 #define MC_HUB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5521 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5522 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5523 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5524 #define MC_HUB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5525 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5526 #define MC_HUB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5527 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5528 #define MC_HUB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5529 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5530 #define MC_HUB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5531 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5532 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5533 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5534 #define MC_RPB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5535 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5536 #define MC_RPB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5537 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5538 #define MC_RPB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5539 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5540 #define MC_RPB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5541 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5542 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5543 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5544 #define MC_RPB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5545 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5546 #define MC_RPB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5547 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5548 #define MC_RPB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5549 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5550 #define MC_RPB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5551 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5552 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5553 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5554 #define MC_RPB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5555 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5556 #define MC_RPB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5557 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5558 #define MC_RPB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5559 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5560 #define MC_RPB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5561 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5562 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5563 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5564 #define MC_RPB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5565 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5566 #define MC_RPB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5567 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5568 #define MC_RPB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5569 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5570 #define MC_RPB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5571 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5572 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5573 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5574 #define MC_ARB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5575 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5576 #define MC_ARB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5577 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5578 #define MC_ARB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5579 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5580 #define MC_ARB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5581 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5582 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5583 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5584 #define MC_ARB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5585 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5586 #define MC_ARB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5587 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5588 #define MC_ARB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5589 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5590 #define MC_ARB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5591 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5592 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5593 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5594 #define MC_ARB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5595 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5596 #define MC_ARB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5597 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5598 #define MC_ARB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5599 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5600 #define MC_ARB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5601 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5602 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5603 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5604 #define MC_ARB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5605 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5606 #define MC_ARB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5607 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5608 #define MC_ARB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5609 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5610 #define MC_ARB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5611 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5612 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5613 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5614 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5615 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5616 #define MC_MCBVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5617 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5618 #define MC_MCBVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5619 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5620 #define MC_MCBVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5621 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5622 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5623 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5624 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5625 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5626 #define MC_MCBVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5627 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5628 #define MC_MCBVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5629 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5630 #define MC_MCBVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5631 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5632 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5633 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5634 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5635 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5636 #define MC_MCBVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5637 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5638 #define MC_MCBVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5639 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5640 #define MC_MCBVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5641 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5642 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5643 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5644 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5645 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5646 #define MC_MCBVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5647 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5648 #define MC_MCBVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5649 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5650 #define MC_MCBVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5651 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5652 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5653 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5654 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5655 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5656 #define MC_MCDVM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5657 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5658 #define MC_MCDVM_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5659 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5660 #define MC_MCDVM_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5661 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5662 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5663 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5664 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5665 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5666 #define MC_MCDVM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5667 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5668 #define MC_MCDVM_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5669 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5670 #define MC_MCDVM_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5671 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5672 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5673 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5674 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5675 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5676 #define MC_MCDVM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5677 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5678 #define MC_MCDVM_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5679 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5680 #define MC_MCDVM_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5681 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5682 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5683 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5684 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5685 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5686 #define MC_MCDVM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5687 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5688 #define MC_MCDVM_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5689 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5690 #define MC_MCDVM_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5691 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5692 #define ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5693 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5694 #define ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5695 #define ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5696 #define ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5697 #define ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5698 #define ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5699 #define ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5700 #define ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5701 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5702 #define ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5703 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5704 #define ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5705 #define ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5706 #define ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5707 #define ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5708 #define ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5709 #define ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5710 #define ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5711 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_MASK 0xff
5712 #define ATC_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0
5713 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0xff00
5714 #define ATC_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8
5715 #define ATC_PERFCOUNTER2_CFG__PERF_MODE_MASK 0xf000000
5716 #define ATC_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18
5717 #define ATC_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000
5718 #define ATC_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c
5719 #define ATC_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000
5720 #define ATC_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d
5721 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_MASK 0xff
5722 #define ATC_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0
5723 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0xff00
5724 #define ATC_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8
5725 #define ATC_PERFCOUNTER3_CFG__PERF_MODE_MASK 0xf000000
5726 #define ATC_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18
5727 #define ATC_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000
5728 #define ATC_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c
5729 #define ATC_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000
5730 #define ATC_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d
5731 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5732 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5733 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5734 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5735 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5736 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5737 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5738 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5739 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5740 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5741 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5742 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5743 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5744 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5745 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5746 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5747 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5748 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5749 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5750 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5751 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5752 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5753 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5754 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5755 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5756 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5757 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5758 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5759 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5760 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5761 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5762 #define MC_CITF_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5763 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5764 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5765 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5766 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5767 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5768 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5769 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5770 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5771 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5772 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5773 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5774 #define MC_HUB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5775 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5776 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5777 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5778 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5779 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5780 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5781 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5782 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5783 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5784 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5785 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5786 #define MC_RPB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5787 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5788 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5789 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5790 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5791 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5792 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5793 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5794 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5795 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5796 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5797 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5798 #define MC_MCBVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5799 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5800 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5801 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5802 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5803 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5804 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5805 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5806 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5807 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5808 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5809 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5810 #define MC_MCDVM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5811 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5812 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5813 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5814 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5815 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5816 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5817 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5818 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5819 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5820 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5821 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5822 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5823 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5824 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5825 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5826 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5827 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5828 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5829 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5830 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5831 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5832 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5833 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5834 #define MC_ARB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5835 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5836 #define ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5837 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5838 #define ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5839 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5840 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5841 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5842 #define ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5843 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5844 #define ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5845 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5846 #define ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5847 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO_MASK 0xffffffff
5848 #define CHUB_ATC_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0
5849 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI_MASK 0xffff
5850 #define CHUB_ATC_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0
5851 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xffff0000
5852 #define CHUB_ATC_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10
5853 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_MASK 0xff
5854 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0
5855 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0xff00
5856 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8
5857 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE_MASK 0xf000000
5858 #define CHUB_ATC_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18
5859 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000
5860 #define CHUB_ATC_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c
5861 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000
5862 #define CHUB_ATC_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d
5863 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_MASK 0xff
5864 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0
5865 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0xff00
5866 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8
5867 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE_MASK 0xf000000
5868 #define CHUB_ATC_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18
5869 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000
5870 #define CHUB_ATC_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c
5871 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000
5872 #define CHUB_ATC_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d
5873 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0xf
5874 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0
5875 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0xff00
5876 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8
5877 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0xff0000
5878 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10
5879 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x1000000
5880 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18
5881 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x2000000
5882 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19
5883 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x4000000
5884 #define CHUB_ATC_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a
5885 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5886 #define ATC_VM_APERTURE0_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5887 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5888 #define ATC_VM_APERTURE1_LOW_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5889 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5890 #define ATC_VM_APERTURE0_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5891 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER_MASK 0xfffffff
5892 #define ATC_VM_APERTURE1_HIGH_ADDR__VIRTUAL_PAGE_NUMBER__SHIFT 0x0
5893 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE_MASK 0x3
5894 #define ATC_VM_APERTURE0_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
5895 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE_MASK 0x3
5896 #define ATC_VM_APERTURE1_CNTL__ATS_ACCESS_MODE__SHIFT 0x0
5897 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
5898 #define ATC_VM_APERTURE0_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
5899 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE_MASK 0xffff
5900 #define ATC_VM_APERTURE1_CNTL2__VMIDS_USING_RANGE__SHIFT 0x0
5901 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x1
5902 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x0
5903 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x2
5904 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x1
5905 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x4
5906 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x2
5907 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x3f00
5908 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x8
5909 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0xf0000
5910 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x10
5911 #define ATC_ATS_DEBUG__INVALIDATE_ALL_MASK 0x1
5912 #define ATC_ATS_DEBUG__INVALIDATE_ALL__SHIFT 0x0
5913 #define ATC_ATS_DEBUG__IDENT_RETURN_MASK 0x2
5914 #define ATC_ATS_DEBUG__IDENT_RETURN__SHIFT 0x1
5915 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS_MASK 0x4
5916 #define ATC_ATS_DEBUG__ADDRESS_TRANSLATION_REQUEST_WRITE_PERMS__SHIFT 0x2
5917 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING_MASK 0x20
5918 #define ATC_ATS_DEBUG__PAGE_REQUESTS_USE_RELAXED_ORDERING__SHIFT 0x5
5919 #define ATC_ATS_DEBUG__PRIV_BIT_MASK 0x40
5920 #define ATC_ATS_DEBUG__PRIV_BIT__SHIFT 0x6
5921 #define ATC_ATS_DEBUG__EXE_BIT_MASK 0x80
5922 #define ATC_ATS_DEBUG__EXE_BIT__SHIFT 0x7
5923 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS_MASK 0x100
5924 #define ATC_ATS_DEBUG__PAGE_REQUEST_PERMS__SHIFT 0x8
5925 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE_MASK 0x200
5926 #define ATC_ATS_DEBUG__UNTRANSLATED_ONLY_REQUESTS_CARRY_SIZE__SHIFT 0x9
5927 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR_MASK 0x3c00
5928 #define ATC_ATS_DEBUG__NUM_REQUESTS_AT_ERR__SHIFT 0xa
5929 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE_MASK 0x4000
5930 #define ATC_ATS_DEBUG__DISALLOW_ERR_TO_DONE__SHIFT 0xe
5931 #define ATC_ATS_DEBUG__IGNORE_FED_MASK 0x8000
5932 #define ATC_ATS_DEBUG__IGNORE_FED__SHIFT 0xf
5933 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED_MASK 0x10000
5934 #define ATC_ATS_DEBUG__INVALIDATION_REQUESTS_DISALLOWED_WHEN_ATC_IS_DISABLED__SHIFT 0x10
5935 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT_MASK 0x20000
5936 #define ATC_ATS_DEBUG__DEBUG_BUS_SELECT__SHIFT 0x11
5937 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x40000
5938 #define ATC_ATS_DEBUG__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x12
5939 #define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING_MASK 0x80000
5940 #define ATC_ATS_DEBUG__DISABLE_VMID0_PASID_MAPPING__SHIFT 0x13
5941 #define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH_MASK 0x100000
5942 #define ATC_ATS_DEBUG__DISABLE_INVALIDATION_ON_WORLD_SWITCH__SHIFT 0x14
5943 #define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT_MASK 0x200000
5944 #define ATC_ATS_DEBUG__ENABLE_INVALIDATION_ON_VIRTUALIZATION_ENTRY_AND_EXIT__SHIFT 0x15
5945 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH_MASK 0x1f
5946 #define ATC_ATS_FAULT_DEBUG__CREDITS_ATS_IH__SHIFT 0x0
5947 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES_MASK 0x100
5948 #define ATC_ATS_FAULT_DEBUG__ALLOW_SUBSEQUENT_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x8
5949 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR_MASK 0x10000
5950 #define ATC_ATS_FAULT_DEBUG__CLEAR_FAULT_STATUS_ADDR__SHIFT 0x10
5951 #define ATC_ATS_STATUS__BUSY_MASK 0x1
5952 #define ATC_ATS_STATUS__BUSY__SHIFT 0x0
5953 #define ATC_ATS_STATUS__CRASHED_MASK 0x2
5954 #define ATC_ATS_STATUS__CRASHED__SHIFT 0x1
5955 #define ATC_ATS_STATUS__DEADLOCK_DETECTION_MASK 0x4
5956 #define ATC_ATS_STATUS__DEADLOCK_DETECTION__SHIFT 0x2
5957 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG_MASK 0x1ff
5958 #define ATC_ATS_FAULT_CNTL__FAULT_REGISTER_LOG__SHIFT 0x0
5959 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE_MASK 0x7fc00
5960 #define ATC_ATS_FAULT_CNTL__FAULT_INTERRUPT_TABLE__SHIFT 0xa
5961 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE_MASK 0x1ff00000
5962 #define ATC_ATS_FAULT_CNTL__FAULT_CRASH_TABLE__SHIFT 0x14
5963 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE_MASK 0x1ff
5964 #define ATC_ATS_FAULT_STATUS_INFO__FAULT_TYPE__SHIFT 0x0
5965 #define ATC_ATS_FAULT_STATUS_INFO__VMID_MASK 0x7c00
5966 #define ATC_ATS_FAULT_STATUS_INFO__VMID__SHIFT 0xa
5967 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO_MASK 0x8000
5968 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO__SHIFT 0xf
5969 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2_MASK 0x10000
5970 #define ATC_ATS_FAULT_STATUS_INFO__EXTRA_INFO2__SHIFT 0x10
5971 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION_MASK 0x20000
5972 #define ATC_ATS_FAULT_STATUS_INFO__INVALIDATION__SHIFT 0x11
5973 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST_MASK 0x40000
5974 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_REQUEST__SHIFT 0x12
5975 #define ATC_ATS_FAULT_STATUS_INFO__STATUS_MASK 0xf80000
5976 #define ATC_ATS_FAULT_STATUS_INFO__STATUS__SHIFT 0x13
5977 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH_MASK 0xf000000
5978 #define ATC_ATS_FAULT_STATUS_INFO__PAGE_ADDR_HIGH__SHIFT 0x18
5979 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR_MASK 0xffffffff
5980 #define ATC_ATS_FAULT_STATUS_ADDR__PAGE_ADDR__SHIFT 0x0
5981 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE_MASK 0xfffffff
5982 #define ATC_ATS_DEFAULT_PAGE_LOW__DEFAULT_PAGE__SHIFT 0x0
5983 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE_MASK 0x1
5984 #define ATC_ATS_DEFAULT_PAGE_CNTL__SEND_DEFAULT_PAGE__SHIFT 0x0
5985 #define ATC_ATS_FAULT_STATUS_INFO2__VF_MASK 0x1
5986 #define ATC_ATS_FAULT_STATUS_INFO2__VF__SHIFT 0x0
5987 #define ATC_ATS_FAULT_STATUS_INFO2__VFID_MASK 0x3e
5988 #define ATC_ATS_FAULT_STATUS_INFO2__VFID__SHIFT 0x1
5989 #define ATC_ATS_FAULT_STATUS_INFO2__L1_ID_MASK 0x1fe00
5990 #define ATC_ATS_FAULT_STATUS_INFO2__L1_ID__SHIFT 0x9
5991 #define ATC_MISC_CG__OFFDLY_MASK 0xfc0
5992 #define ATC_MISC_CG__OFFDLY__SHIFT 0x6
5993 #define ATC_MISC_CG__ENABLE_MASK 0x40000
5994 #define ATC_MISC_CG__ENABLE__SHIFT 0x12
5995 #define ATC_MISC_CG__MEM_LS_ENABLE_MASK 0x80000
5996 #define ATC_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13
5997 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x3
5998 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0
5999 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x30
6000 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x4
6001 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x100
6002 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x8
6003 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x200
6004 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x9
6005 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x3f
6006 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0
6007 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0xc0
6008 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6009 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x100
6010 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8
6011 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0xe00
6012 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9
6013 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x7000
6014 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc
6015 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f8000
6016 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf
6017 #define ATC_L2_DEBUG__CREDITS_L2_ATS_MASK 0x3f
6018 #define ATC_L2_DEBUG__CREDITS_L2_ATS__SHIFT 0x0
6019 #define ATC_L2_DEBUG__L2_MEM_SELECT_MASK 0x80
6020 #define ATC_L2_DEBUG__L2_MEM_SELECT__SHIFT 0x7
6021 #define ATC_L2_DEBUG__CACHE_INDEX_MASK 0xfff00
6022 #define ATC_L2_DEBUG__CACHE_INDEX__SHIFT 0x8
6023 #define ATC_L2_DEBUG__CACHE_SELECT_MASK 0x1000000
6024 #define ATC_L2_DEBUG__CACHE_SELECT__SHIFT 0x18
6025 #define ATC_L2_DEBUG__CACHE_BANK_SELECT_MASK 0x2000000
6026 #define ATC_L2_DEBUG__CACHE_BANK_SELECT__SHIFT 0x19
6027 #define ATC_L2_DEBUG__CACHE_WAY_SELECT_MASK 0x8000000
6028 #define ATC_L2_DEBUG__CACHE_WAY_SELECT__SHIFT 0x1b
6029 #define ATC_L2_DEBUG__CACHE_READ_MASK 0x20000000
6030 #define ATC_L2_DEBUG__CACHE_READ__SHIFT 0x1d
6031 #define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR_MASK 0x40000000
6032 #define ATC_L2_DEBUG__CACHE_INJECT_SOFT_PARITY_ERROR__SHIFT 0x1e
6033 #define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR_MASK 0x80000000
6034 #define ATC_L2_DEBUG__CACHE_INJECT_HARD_PARITY_ERROR__SHIFT 0x1f
6035 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE_MASK 0x1f
6036 #define ATC_L2_DEBUG2__EFFECTIVE_CACHE_SIZE__SHIFT 0x0
6037 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0xe0
6038 #define ATC_L2_DEBUG2__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x5
6039 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS_MASK 0x100
6040 #define ATC_L2_DEBUG2__FORCE_CACHE_MISS__SHIFT 0x8
6041 #define ATC_L2_DEBUG2__INVALIDATE_ALL_MASK 0x200
6042 #define ATC_L2_DEBUG2__INVALIDATE_ALL__SHIFT 0x9
6043 #define ATC_L2_DEBUG2__DISABLE_2M_CACHE_MASK 0x400
6044 #define ATC_L2_DEBUG2__DISABLE_2M_CACHE__SHIFT 0xa
6045 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS_MASK 0x800
6046 #define ATC_L2_DEBUG2__DISABLE_CACHING_SPECULATIVE_RETURNS__SHIFT 0xb
6047 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS_MASK 0x4000
6048 #define ATC_L2_DEBUG2__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0xe
6049 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT_MASK 0x18000
6050 #define ATC_L2_DEBUG2__DEBUG_BUS_SELECT__SHIFT 0xf
6051 #define ATC_L2_DEBUG2__DEBUG_ECO_MASK 0x60000
6052 #define ATC_L2_DEBUG2__DEBUG_ECO__SHIFT 0x11
6053 #define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE_MASK 0x780000
6054 #define ATC_L2_DEBUG2__EFFECTIVE_2M_CACHE_SIZE__SHIFT 0x13
6055 #define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD_MASK 0x7f800000
6056 #define ATC_L2_DEBUG2__CACHE_PARITY_ERROR_INTERRUPT_THRESHOLD__SHIFT 0x17
6057 #define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO_MASK 0x80000000
6058 #define ATC_L2_DEBUG2__CLEAR_PARITY_ERROR_INFO__SHIFT 0x1f
6059 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x1
6060 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0
6061 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x2
6062 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1
6063 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x1fffffc
6064 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2
6065 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x1e000000
6066 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x19
6067 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xffffffff
6068 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0
6069 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW_MASK 0xfffffff
6070 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_LOW__SHIFT 0x0
6071 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR_MASK 0x3
6072 #define ATC_L1_CNTL__DONT_NEED_ATS_BEHAVIOR__SHIFT 0x0
6073 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR_MASK 0x4
6074 #define ATC_L1_CNTL__NEED_ATS_BEHAVIOR__SHIFT 0x2
6075 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT_MASK 0x10
6076 #define ATC_L1_CNTL__NEED_ATS_SNOOP_DEFAULT__SHIFT 0x4
6077 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS_MASK 0xffffffff
6078 #define ATC_L1_ADDRESS_OFFSET__LOGICAL_ADDRESS__SHIFT 0x0
6079 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
6080 #define ATC_L1RD_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
6081 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
6082 #define ATC_L1RD_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
6083 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
6084 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
6085 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
6086 #define ATC_L1RD_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
6087 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
6088 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
6089 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
6090 #define ATC_L1RD_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
6091 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
6092 #define ATC_L1RD_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
6093 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
6094 #define ATC_L1RD_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
6095 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
6096 #define ATC_L1RD_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
6097 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS_MASK 0x1
6098 #define ATC_L1WR_DEBUG_TLB__DISABLE_FRAGMENTS__SHIFT 0x0
6099 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE_MASK 0x2
6100 #define ATC_L1WR_DEBUG_TLB__DISABLE_INVALIDATE_BY_ADDRESS_RANGE__SHIFT 0x1
6101 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE_MASK 0xf0
6102 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_CAM_SIZE__SHIFT 0x4
6103 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE_MASK 0x700
6104 #define ATC_L1WR_DEBUG_TLB__EFFECTIVE_WORK_QUEUE_SIZE__SHIFT 0x8
6105 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2_MASK 0x3f000
6106 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_L2__SHIFT 0xc
6107 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB_MASK 0xff00000
6108 #define ATC_L1WR_DEBUG_TLB__CREDITS_L1_RPB__SHIFT 0x14
6109 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO_MASK 0x30000000
6110 #define ATC_L1WR_DEBUG_TLB__DEBUG_ECO__SHIFT 0x1c
6111 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL_MASK 0x40000000
6112 #define ATC_L1WR_DEBUG_TLB__INVALIDATE_ALL__SHIFT 0x1e
6113 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS_MASK 0x80000000
6114 #define ATC_L1WR_DEBUG_TLB__DISABLE_CACHING_FAULT_RETURNS__SHIFT 0x1f
6115 #define ATC_L1RD_STATUS__BUSY_MASK 0x1
6116 #define ATC_L1RD_STATUS__BUSY__SHIFT 0x0
6117 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION_MASK 0x2
6118 #define ATC_L1RD_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
6119 #define ATC_L1RD_STATUS__BAD_NEED_ATS_MASK 0x100
6120 #define ATC_L1RD_STATUS__BAD_NEED_ATS__SHIFT 0x8
6121 #define ATC_L1RD_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
6122 #define ATC_L1RD_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
6123 #define ATC_L1RD_STATUS__CAM_INDEX_MASK 0x3e0000
6124 #define ATC_L1RD_STATUS__CAM_INDEX__SHIFT 0x11
6125 #define ATC_L1WR_STATUS__BUSY_MASK 0x1
6126 #define ATC_L1WR_STATUS__BUSY__SHIFT 0x0
6127 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION_MASK 0x2
6128 #define ATC_L1WR_STATUS__DEADLOCK_DETECTION__SHIFT 0x1
6129 #define ATC_L1WR_STATUS__BAD_NEED_ATS_MASK 0x100
6130 #define ATC_L1WR_STATUS__BAD_NEED_ATS__SHIFT 0x8
6131 #define ATC_L1WR_STATUS__CAM_PARITY_ERRORS_MASK 0x1f000
6132 #define ATC_L1WR_STATUS__CAM_PARITY_ERRORS__SHIFT 0xc
6133 #define ATC_L1WR_STATUS__CAM_INDEX_MASK 0x3e0000
6134 #define ATC_L1WR_STATUS__CAM_INDEX__SHIFT 0x11
6135 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
6136 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
6137 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
6138 #define ATC_L1RD_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
6139 #define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
6140 #define ATC_L1RD_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
6141 #define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
6142 #define ATC_L1RD_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
6143 #define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
6144 #define ATC_L1RD_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
6145 #define ATC_L1RD_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
6146 #define ATC_L1RD_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
6147 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD_MASK 0xfff
6148 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_PERIOD__SHIFT 0x0
6149 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE_MASK 0xc000
6150 #define ATC_L1WR_DEBUG2_TLB__XNACK_RETRY_MODE__SHIFT 0xe
6151 #define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR_MASK 0x10000
6152 #define ATC_L1WR_DEBUG2_TLB__INJECT_SOFT_PARITY_ERROR__SHIFT 0x10
6153 #define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR_MASK 0x20000
6154 #define ATC_L1WR_DEBUG2_TLB__INJECT_HARD_PARITY_ERROR__SHIFT 0x11
6155 #define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR_MASK 0x40000
6156 #define ATC_L1WR_DEBUG2_TLB__CLEAR_CAM_PARITY_ERROR__SHIFT 0x12
6157 #define ATC_L1WR_DEBUG2_TLB__CAM_INDEX_MASK 0xf80000
6158 #define ATC_L1WR_DEBUG2_TLB__CAM_INDEX__SHIFT 0x13
6159 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED_MASK 0x1
6160 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID0_REMAPPING_FINISHED__SHIFT 0x0
6161 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED_MASK 0x2
6162 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID1_REMAPPING_FINISHED__SHIFT 0x1
6163 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED_MASK 0x4
6164 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID2_REMAPPING_FINISHED__SHIFT 0x2
6165 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED_MASK 0x8
6166 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID3_REMAPPING_FINISHED__SHIFT 0x3
6167 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED_MASK 0x10
6168 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID4_REMAPPING_FINISHED__SHIFT 0x4
6169 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED_MASK 0x20
6170 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID5_REMAPPING_FINISHED__SHIFT 0x5
6171 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED_MASK 0x40
6172 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID6_REMAPPING_FINISHED__SHIFT 0x6
6173 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED_MASK 0x80
6174 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID7_REMAPPING_FINISHED__SHIFT 0x7
6175 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED_MASK 0x100
6176 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID8_REMAPPING_FINISHED__SHIFT 0x8
6177 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED_MASK 0x200
6178 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID9_REMAPPING_FINISHED__SHIFT 0x9
6179 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED_MASK 0x400
6180 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID10_REMAPPING_FINISHED__SHIFT 0xa
6181 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED_MASK 0x800
6182 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID11_REMAPPING_FINISHED__SHIFT 0xb
6183 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED_MASK 0x1000
6184 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID12_REMAPPING_FINISHED__SHIFT 0xc
6185 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED_MASK 0x2000
6186 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID13_REMAPPING_FINISHED__SHIFT 0xd
6187 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED_MASK 0x4000
6188 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID14_REMAPPING_FINISHED__SHIFT 0xe
6189 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED_MASK 0x8000
6190 #define ATC_VMID_PASID_MAPPING_UPDATE_STATUS__VMID15_REMAPPING_FINISHED__SHIFT 0xf
6191 #define ATC_VMID0_PASID_MAPPING__PASID_MASK 0xffff
6192 #define ATC_VMID0_PASID_MAPPING__PASID__SHIFT 0x0
6193 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6194 #define ATC_VMID0_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6195 #define ATC_VMID0_PASID_MAPPING__VALID_MASK 0x80000000
6196 #define ATC_VMID0_PASID_MAPPING__VALID__SHIFT 0x1f
6197 #define ATC_VMID1_PASID_MAPPING__PASID_MASK 0xffff
6198 #define ATC_VMID1_PASID_MAPPING__PASID__SHIFT 0x0
6199 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6200 #define ATC_VMID1_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6201 #define ATC_VMID1_PASID_MAPPING__VALID_MASK 0x80000000
6202 #define ATC_VMID1_PASID_MAPPING__VALID__SHIFT 0x1f
6203 #define ATC_VMID2_PASID_MAPPING__PASID_MASK 0xffff
6204 #define ATC_VMID2_PASID_MAPPING__PASID__SHIFT 0x0
6205 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6206 #define ATC_VMID2_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6207 #define ATC_VMID2_PASID_MAPPING__VALID_MASK 0x80000000
6208 #define ATC_VMID2_PASID_MAPPING__VALID__SHIFT 0x1f
6209 #define ATC_VMID3_PASID_MAPPING__PASID_MASK 0xffff
6210 #define ATC_VMID3_PASID_MAPPING__PASID__SHIFT 0x0
6211 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6212 #define ATC_VMID3_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6213 #define ATC_VMID3_PASID_MAPPING__VALID_MASK 0x80000000
6214 #define ATC_VMID3_PASID_MAPPING__VALID__SHIFT 0x1f
6215 #define ATC_VMID4_PASID_MAPPING__PASID_MASK 0xffff
6216 #define ATC_VMID4_PASID_MAPPING__PASID__SHIFT 0x0
6217 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6218 #define ATC_VMID4_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6219 #define ATC_VMID4_PASID_MAPPING__VALID_MASK 0x80000000
6220 #define ATC_VMID4_PASID_MAPPING__VALID__SHIFT 0x1f
6221 #define ATC_VMID5_PASID_MAPPING__PASID_MASK 0xffff
6222 #define ATC_VMID5_PASID_MAPPING__PASID__SHIFT 0x0
6223 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6224 #define ATC_VMID5_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6225 #define ATC_VMID5_PASID_MAPPING__VALID_MASK 0x80000000
6226 #define ATC_VMID5_PASID_MAPPING__VALID__SHIFT 0x1f
6227 #define ATC_VMID6_PASID_MAPPING__PASID_MASK 0xffff
6228 #define ATC_VMID6_PASID_MAPPING__PASID__SHIFT 0x0
6229 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6230 #define ATC_VMID6_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6231 #define ATC_VMID6_PASID_MAPPING__VALID_MASK 0x80000000
6232 #define ATC_VMID6_PASID_MAPPING__VALID__SHIFT 0x1f
6233 #define ATC_VMID7_PASID_MAPPING__PASID_MASK 0xffff
6234 #define ATC_VMID7_PASID_MAPPING__PASID__SHIFT 0x0
6235 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6236 #define ATC_VMID7_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6237 #define ATC_VMID7_PASID_MAPPING__VALID_MASK 0x80000000
6238 #define ATC_VMID7_PASID_MAPPING__VALID__SHIFT 0x1f
6239 #define ATC_VMID8_PASID_MAPPING__PASID_MASK 0xffff
6240 #define ATC_VMID8_PASID_MAPPING__PASID__SHIFT 0x0
6241 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6242 #define ATC_VMID8_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6243 #define ATC_VMID8_PASID_MAPPING__VALID_MASK 0x80000000
6244 #define ATC_VMID8_PASID_MAPPING__VALID__SHIFT 0x1f
6245 #define ATC_VMID9_PASID_MAPPING__PASID_MASK 0xffff
6246 #define ATC_VMID9_PASID_MAPPING__PASID__SHIFT 0x0
6247 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6248 #define ATC_VMID9_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6249 #define ATC_VMID9_PASID_MAPPING__VALID_MASK 0x80000000
6250 #define ATC_VMID9_PASID_MAPPING__VALID__SHIFT 0x1f
6251 #define ATC_VMID10_PASID_MAPPING__PASID_MASK 0xffff
6252 #define ATC_VMID10_PASID_MAPPING__PASID__SHIFT 0x0
6253 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6254 #define ATC_VMID10_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6255 #define ATC_VMID10_PASID_MAPPING__VALID_MASK 0x80000000
6256 #define ATC_VMID10_PASID_MAPPING__VALID__SHIFT 0x1f
6257 #define ATC_VMID11_PASID_MAPPING__PASID_MASK 0xffff
6258 #define ATC_VMID11_PASID_MAPPING__PASID__SHIFT 0x0
6259 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6260 #define ATC_VMID11_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6261 #define ATC_VMID11_PASID_MAPPING__VALID_MASK 0x80000000
6262 #define ATC_VMID11_PASID_MAPPING__VALID__SHIFT 0x1f
6263 #define ATC_VMID12_PASID_MAPPING__PASID_MASK 0xffff
6264 #define ATC_VMID12_PASID_MAPPING__PASID__SHIFT 0x0
6265 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6266 #define ATC_VMID12_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6267 #define ATC_VMID12_PASID_MAPPING__VALID_MASK 0x80000000
6268 #define ATC_VMID12_PASID_MAPPING__VALID__SHIFT 0x1f
6269 #define ATC_VMID13_PASID_MAPPING__PASID_MASK 0xffff
6270 #define ATC_VMID13_PASID_MAPPING__PASID__SHIFT 0x0
6271 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6272 #define ATC_VMID13_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6273 #define ATC_VMID13_PASID_MAPPING__VALID_MASK 0x80000000
6274 #define ATC_VMID13_PASID_MAPPING__VALID__SHIFT 0x1f
6275 #define ATC_VMID14_PASID_MAPPING__PASID_MASK 0xffff
6276 #define ATC_VMID14_PASID_MAPPING__PASID__SHIFT 0x0
6277 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6278 #define ATC_VMID14_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6279 #define ATC_VMID14_PASID_MAPPING__VALID_MASK 0x80000000
6280 #define ATC_VMID14_PASID_MAPPING__VALID__SHIFT 0x1f
6281 #define ATC_VMID15_PASID_MAPPING__PASID_MASK 0xffff
6282 #define ATC_VMID15_PASID_MAPPING__PASID__SHIFT 0x0
6283 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION_MASK 0x40000000
6284 #define ATC_VMID15_PASID_MAPPING__NO_INVALIDATION__SHIFT 0x1e
6285 #define ATC_VMID15_PASID_MAPPING__VALID_MASK 0x80000000
6286 #define ATC_VMID15_PASID_MAPPING__VALID__SHIFT 0x1f
6287 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING_MASK 0x1
6288 #define ATC_ATS_VMID_STATUS__VMID0_OUTSTANDING__SHIFT 0x0
6289 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING_MASK 0x2
6290 #define ATC_ATS_VMID_STATUS__VMID1_OUTSTANDING__SHIFT 0x1
6291 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING_MASK 0x4
6292 #define ATC_ATS_VMID_STATUS__VMID2_OUTSTANDING__SHIFT 0x2
6293 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING_MASK 0x8
6294 #define ATC_ATS_VMID_STATUS__VMID3_OUTSTANDING__SHIFT 0x3
6295 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING_MASK 0x10
6296 #define ATC_ATS_VMID_STATUS__VMID4_OUTSTANDING__SHIFT 0x4
6297 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING_MASK 0x20
6298 #define ATC_ATS_VMID_STATUS__VMID5_OUTSTANDING__SHIFT 0x5
6299 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING_MASK 0x40
6300 #define ATC_ATS_VMID_STATUS__VMID6_OUTSTANDING__SHIFT 0x6
6301 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING_MASK 0x80
6302 #define ATC_ATS_VMID_STATUS__VMID7_OUTSTANDING__SHIFT 0x7
6303 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING_MASK 0x100
6304 #define ATC_ATS_VMID_STATUS__VMID8_OUTSTANDING__SHIFT 0x8
6305 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING_MASK 0x200
6306 #define ATC_ATS_VMID_STATUS__VMID9_OUTSTANDING__SHIFT 0x9
6307 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING_MASK 0x400
6308 #define ATC_ATS_VMID_STATUS__VMID10_OUTSTANDING__SHIFT 0xa
6309 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING_MASK 0x800
6310 #define ATC_ATS_VMID_STATUS__VMID11_OUTSTANDING__SHIFT 0xb
6311 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING_MASK 0x1000
6312 #define ATC_ATS_VMID_STATUS__VMID12_OUTSTANDING__SHIFT 0xc
6313 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING_MASK 0x2000
6314 #define ATC_ATS_VMID_STATUS__VMID13_OUTSTANDING__SHIFT 0xd
6315 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING_MASK 0x4000
6316 #define ATC_ATS_VMID_STATUS__VMID14_OUTSTANDING__SHIFT 0xe
6317 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING_MASK 0x8000
6318 #define ATC_ATS_VMID_STATUS__VMID15_OUTSTANDING__SHIFT 0xf
6319 #define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN_MASK 0x1
6320 #define ATC_ATS_SMU_STATUS__VDDGFX_POWERED_DOWN__SHIFT 0x0
6321 #define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING_MASK 0x7f
6322 #define ATC_L2_CNTL3__ENABLE_HW_L2_CACHE_ADDRESS_MODES_SWITCHING__SHIFT 0x0
6323 #define ATC_L2_CNTL3__ENABLE_FREE_COUNTER_MASK 0x80
6324 #define ATC_L2_CNTL3__ENABLE_FREE_COUNTER__SHIFT 0x7
6325 #define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD_MASK 0x1f00
6326 #define ATC_L2_CNTL3__L2_CACHE_EVICTION_THRESHOLD__SHIFT 0x8
6327 #define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION_MASK 0x2000
6328 #define ATC_L2_CNTL3__DISABLE_CLEAR_CACHE_EVICTION_COUNTER_ON_INVALIDATION__SHIFT 0xd
6329 #define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST_MASK 0x1c000
6330 #define ATC_L2_CNTL3__L2_DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0xe
6331 #define ATC_L2_STATUS__BUSY_MASK 0x1
6332 #define ATC_L2_STATUS__BUSY__SHIFT 0x0
6333 #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3ffffffe
6334 #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1
6335 #define ATC_L2_STATUS2__CACHE_ADDRESS_MODE_MASK 0x7
6336 #define ATC_L2_STATUS2__CACHE_ADDRESS_MODE__SHIFT 0x0
6337 #define ATC_L2_STATUS2__PARITY_ERROR_INFO_MASK 0x7f8
6338 #define ATC_L2_STATUS2__PARITY_ERROR_INFO__SHIFT 0x3
6339 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x3ff
6340 #define GMCON_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0
6341 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xffffffff
6342 #define GMCON_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0
6343 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x1
6344 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0
6345 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x2
6346 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1
6347 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0xffc
6348 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x2
6349 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR_MASK 0x3ff000
6350 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_DSP_END_PTR__SHIFT 0xc
6351 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0xffc00000
6352 #define GMCON_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0x16
6353 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE_MASK 0x400
6354 #define GMCON_MISC__RENG_EXECUTE_NOW_MODE__SHIFT 0xa
6355 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x800
6356 #define GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0xb
6357 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD_MASK 0xf000
6358 #define GMCON_MISC__RENG_SRBM_CREDITS_MCD__SHIFT 0xc
6359 #define GMCON_MISC__STCTRL_STUTTER_EN_MASK 0x10000
6360 #define GMCON_MISC__STCTRL_STUTTER_EN__SHIFT 0x10
6361 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD_MASK 0x60000
6362 #define GMCON_MISC__STCTRL_GMC_IDLE_THRESHOLD__SHIFT 0x11
6363 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD_MASK 0x180000
6364 #define GMCON_MISC__STCTRL_SRBM_IDLE_THRESHOLD__SHIFT 0x13
6365 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR_MASK 0x200000
6366 #define GMCON_MISC__STCTRL_IGNORE_PRE_SR__SHIFT 0x15
6367 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP_MASK 0x400000
6368 #define GMCON_MISC__STCTRL_IGNORE_ALLOW_STOP__SHIFT 0x16
6369 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT_MASK 0x800000
6370 #define GMCON_MISC__STCTRL_IGNORE_SR_COMMIT__SHIFT 0x17
6371 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x1000000
6372 #define GMCON_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x18
6373 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR_MASK 0x2000000
6374 #define GMCON_MISC__STCTRL_DISABLE_ALLOW_SR__SHIFT 0x19
6375 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE_MASK 0x4000000
6376 #define GMCON_MISC__STCTRL_DISABLE_GMC_OFFLINE__SHIFT 0x1a
6377 #define GMCON_MISC__CRITICAL_REGS_LOCK_MASK 0x8000000
6378 #define GMCON_MISC__CRITICAL_REGS_LOCK__SHIFT 0x1b
6379 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x70000000
6380 #define GMCON_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1c
6381 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR_MASK 0x80000000
6382 #define GMCON_MISC__STCTRL_FORCE_ALLOW_SR__SHIFT 0x1f
6383 #define GMCON_MISC2__GMCON_MISC2_RESERVED0_MASK 0x3f
6384 #define GMCON_MISC2__GMCON_MISC2_RESERVED0__SHIFT 0x0
6385 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD_MASK 0x7c0
6386 #define GMCON_MISC2__STCTRL_NONDISP_IDLE_THRESHOLD__SHIFT 0x6
6387 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD_MASK 0x1f800
6388 #define GMCON_MISC2__RENG_SR_HOLD_THRESHOLD__SHIFT 0xb
6389 #define GMCON_MISC2__GMCON_MISC2_RESERVED1_MASK 0x1ffe0000
6390 #define GMCON_MISC2__GMCON_MISC2_RESERVED1__SHIFT 0x11
6391 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY_MASK 0x20000000
6392 #define GMCON_MISC2__STCTRL_IGNORE_ARB_BUSY__SHIFT 0x1d
6393 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE_MASK 0x40000000
6394 #define GMCON_MISC2__STCTRL_EXTEND_GMC_OFFLINE__SHIFT 0x1e
6395 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE_MASK 0x80000000
6396 #define GMCON_MISC2__STCTRL_TIMER_PULSE_OVERRIDE__SHIFT 0x1f
6397 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0_MASK 0xffff
6398 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE0__SHIFT 0x0
6399 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0_MASK 0xffff0000
6400 #define GMCON_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT0__SHIFT 0x10
6401 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1_MASK 0xffff
6402 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE1__SHIFT 0x0
6403 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1_MASK 0xffff0000
6404 #define GMCON_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT1__SHIFT 0x10
6405 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2_MASK 0xffff
6406 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE2__SHIFT 0x0
6407 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2_MASK 0xffff0000
6408 #define GMCON_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT2__SHIFT 0x10
6409 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK 0xffff
6410 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0
6411 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xffff0000
6412 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10
6413 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0xffff
6414 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0
6415 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xffff0000
6416 #define GMCON_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10
6417 #define GMCON_PERF_MON_CNTL0__START_THRESH_MASK 0xfff
6418 #define GMCON_PERF_MON_CNTL0__START_THRESH__SHIFT 0x0
6419 #define GMCON_PERF_MON_CNTL0__STOP_THRESH_MASK 0xfff000
6420 #define GMCON_PERF_MON_CNTL0__STOP_THRESH__SHIFT 0xc
6421 #define GMCON_PERF_MON_CNTL0__START_MODE_MASK 0x3000000
6422 #define GMCON_PERF_MON_CNTL0__START_MODE__SHIFT 0x18
6423 #define GMCON_PERF_MON_CNTL0__STOP_MODE_MASK 0xc000000
6424 #define GMCON_PERF_MON_CNTL0__STOP_MODE__SHIFT 0x1a
6425 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP_MASK 0x10000000
6426 #define GMCON_PERF_MON_CNTL0__ALLOW_WRAP__SHIFT 0x1c
6427 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT_MASK 0x20000000
6428 #define GMCON_PERF_MON_CNTL0__THRESH_CNTR_ID_EXT__SHIFT 0x1d
6429 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT_MASK 0x40000000
6430 #define GMCON_PERF_MON_CNTL0__START_TRIG_ID_EXT__SHIFT 0x1e
6431 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT_MASK 0x80000000
6432 #define GMCON_PERF_MON_CNTL0__STOP_TRIG_ID_EXT__SHIFT 0x1f
6433 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID_MASK 0x3f
6434 #define GMCON_PERF_MON_CNTL1__THRESH_CNTR_ID__SHIFT 0x0
6435 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID_MASK 0xfc0
6436 #define GMCON_PERF_MON_CNTL1__START_TRIG_ID__SHIFT 0x6
6437 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID_MASK 0x3f000
6438 #define GMCON_PERF_MON_CNTL1__STOP_TRIG_ID__SHIFT 0xc
6439 #define GMCON_PERF_MON_CNTL1__MON0_ID_MASK 0x1fc0000
6440 #define GMCON_PERF_MON_CNTL1__MON0_ID__SHIFT 0x12
6441 #define GMCON_PERF_MON_CNTL1__MON1_ID_MASK 0xfe000000
6442 #define GMCON_PERF_MON_CNTL1__MON1_ID__SHIFT 0x19
6443 #define GMCON_PERF_MON_RSLT0__COUNT_MASK 0xffffffff
6444 #define GMCON_PERF_MON_RSLT0__COUNT__SHIFT 0x0
6445 #define GMCON_PERF_MON_RSLT1__COUNT_MASK 0xffffffff
6446 #define GMCON_PERF_MON_RSLT1__COUNT__SHIFT 0x0
6447 #define GMCON_PGFSM_CONFIG__FSM_ADDR_MASK 0xff
6448 #define GMCON_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0
6449 #define GMCON_PGFSM_CONFIG__POWER_DOWN_MASK 0x100
6450 #define GMCON_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8
6451 #define GMCON_PGFSM_CONFIG__POWER_UP_MASK 0x200
6452 #define GMCON_PGFSM_CONFIG__POWER_UP__SHIFT 0x9
6453 #define GMCON_PGFSM_CONFIG__P1_SELECT_MASK 0x400
6454 #define GMCON_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
6455 #define GMCON_PGFSM_CONFIG__P2_SELECT_MASK 0x800
6456 #define GMCON_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb
6457 #define GMCON_PGFSM_CONFIG__WRITE_MASK 0x1000
6458 #define GMCON_PGFSM_CONFIG__WRITE__SHIFT 0xc
6459 #define GMCON_PGFSM_CONFIG__READ_MASK 0x2000
6460 #define GMCON_PGFSM_CONFIG__READ__SHIFT 0xd
6461 #define GMCON_PGFSM_CONFIG__RSRVD_MASK 0x7ffc000
6462 #define GMCON_PGFSM_CONFIG__RSRVD__SHIFT 0xe
6463 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x8000000
6464 #define GMCON_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b
6465 #define GMCON_PGFSM_CONFIG__REG_ADDR_MASK 0xf0000000
6466 #define GMCON_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c
6467 #define GMCON_PGFSM_WRITE__WRITE_VALUE_MASK 0xffffffff
6468 #define GMCON_PGFSM_WRITE__WRITE_VALUE__SHIFT 0x0
6469 #define GMCON_PGFSM_READ__READ_VALUE_MASK 0xffffff
6470 #define GMCON_PGFSM_READ__READ_VALUE__SHIFT 0x0
6471 #define GMCON_PGFSM_READ__PGFSM_SELECT_MASK 0xf000000
6472 #define GMCON_PGFSM_READ__PGFSM_SELECT__SHIFT 0x18
6473 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY_MASK 0x10000000
6474 #define GMCON_PGFSM_READ__SERDES_MASTER_BUSY__SHIFT 0x1c
6475 #define GMCON_MISC3__RENG_DISABLE_MCC_MASK 0xff
6476 #define GMCON_MISC3__RENG_DISABLE_MCC__SHIFT 0x0
6477 #define GMCON_MISC3__RENG_DISABLE_MCD_MASK 0xff00
6478 #define GMCON_MISC3__RENG_DISABLE_MCD__SHIFT 0x8
6479 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0xfff0000
6480 #define GMCON_MISC3__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10
6481 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER_MASK 0x10000000
6482 #define GMCON_MISC3__STCTRL_IGNORE_ALLOW_STUTTER__SHIFT 0x1c
6483 #define GMCON_MISC3__RENG_MEM_LS_ENABLE_MASK 0x20000000
6484 #define GMCON_MISC3__RENG_MEM_LS_ENABLE__SHIFT 0x1d
6485 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS_MASK 0x40000000
6486 #define GMCON_MISC3__STCTRL_EXCLUDE_NONMEM_CLIENTS__SHIFT 0x1e
6487 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD_MASK 0x1
6488 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_RD__SHIFT 0x0
6489 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR_MASK 0x2
6490 #define GMCON_MASK__STCTRL_BUSY_MASK_ACP_WR__SHIFT 0x1
6491 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD_MASK 0x4
6492 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_RD__SHIFT 0x2
6493 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR_MASK 0x8
6494 #define GMCON_MASK__STCTRL_BUSY_MASK_VCE_WR__SHIFT 0x3
6495 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK_MASK 0xff0
6496 #define GMCON_MASK__STCTRL_SR_HANDSHAKE_MASK__SHIFT 0x4
6497 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET_MASK 0xffffffff
6498 #define GMCON_LPT_TARGET__STCTRL_LPT_TARGET__SHIFT 0x0
6499 #define GMCON_DEBUG__GFX_STALL_MASK 0x1
6500 #define GMCON_DEBUG__GFX_STALL__SHIFT 0x0
6501 #define GMCON_DEBUG__GFX_CLEAR_MASK 0x2
6502 #define GMCON_DEBUG__GFX_CLEAR__SHIFT 0x1
6503 #define GMCON_DEBUG__GMCON_DEBUG_RESERVED0_MASK 0x4
6504 #define GMCON_DEBUG__GMCON_DEBUG_RESERVED0__SHIFT 0x2
6505 #define GMCON_DEBUG__SR_COMMIT_STATE_MASK 0x8
6506 #define GMCON_DEBUG__SR_COMMIT_STATE__SHIFT 0x3
6507 #define GMCON_DEBUG__STCTRL_ST_MASK 0xf0
6508 #define GMCON_DEBUG__STCTRL_ST__SHIFT 0x4
6509 #define GMCON_DEBUG__MISC_FLAGS_MASK 0xffffff00
6510 #define GMCON_DEBUG__MISC_FLAGS__SHIFT 0x8
6511 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x1
6512 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0
6513 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x2
6514 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1
6515 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0xc
6516 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2
6517 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x30
6518 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4
6519 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x100
6520 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8
6521 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x200
6522 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9
6523 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x400
6524 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa
6525 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x800
6526 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb
6527 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x7000
6528 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc
6529 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x38000
6530 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf
6531 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x40000
6532 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12
6533 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x180000
6534 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13
6535 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x3e00000
6536 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15
6537 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0xc000000
6538 #define VM_L2_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a
6539 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000
6540 #define VM_L2_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c
6541 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x1
6542 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0
6543 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x2
6544 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1
6545 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x200000
6546 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15
6547 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x400000
6548 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16
6549 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x3800000
6550 #define VM_L2_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17
6551 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0xc000000
6552 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a
6553 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000
6554 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c
6555 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x3f
6556 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0
6557 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0xc0
6558 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6
6559 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x1f00
6560 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8
6561 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0xf8000
6562 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf
6563 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x100000
6564 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14
6565 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0xe00000
6566 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15
6567 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0xf000000
6568 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18
6569 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000
6570 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c
6571 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000
6572 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d
6573 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000
6574 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e
6575 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000
6576 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f
6577 #define VM_L2_STATUS__L2_BUSY_MASK 0x1
6578 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0
6579 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x1fffe
6580 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1
6581 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x1
6582 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6583 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
6584 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6585 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
6586 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
6587 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
6588 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
6589 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
6590 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
6591 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
6592 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
6593 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
6594 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6595 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
6596 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6597 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
6598 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
6599 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
6600 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
6601 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
6602 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
6603 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
6604 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
6605 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
6606 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6607 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
6608 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6609 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
6610 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
6611 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
6612 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
6613 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
6614 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
6615 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
6616 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
6617 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
6618 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6619 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
6620 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6621 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
6622 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
6623 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
6624 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
6625 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x1
6626 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0
6627 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x6
6628 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1
6629 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8
6630 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3
6631 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10
6632 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4
6633 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40
6634 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6
6635 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80
6636 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7
6637 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200
6638 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9
6639 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400
6640 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa
6641 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800
6642 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb
6643 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x1000
6644 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc
6645 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x2000
6646 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd
6647 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x4000
6648 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe
6649 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x8000
6650 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf
6651 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x10000
6652 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10
6653 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x20000
6654 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11
6655 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x40000
6656 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12
6657 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x80000
6658 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13
6659 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x100000
6660 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14
6661 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x200000
6662 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15
6663 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x400000
6664 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16
6665 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x800000
6666 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17
6667 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0xf000000
6668 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18
6669 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x1
6670 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0
6671 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x2
6672 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1
6673 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK_MASK 0xc
6674 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MASK__SHIFT 0x2
6675 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR_MASK 0xfffffff
6676 #define VM_DUMMY_PAGE_FAULT_ADDR__DUMMY_PAGE_ADDR__SHIFT 0x0
6677 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
6678 #define VM_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6679 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
6680 #define VM_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
6681 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
6682 #define VM_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
6683 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
6684 #define VM_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
6685 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
6686 #define VM_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
6687 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x1
6688 #define VM_CONTEXT1_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0
6689 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x2
6690 #define VM_CONTEXT1_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1
6691 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x4
6692 #define VM_CONTEXT1_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2
6693 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x8
6694 #define VM_CONTEXT1_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3
6695 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x10
6696 #define VM_CONTEXT1_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4
6697 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6698 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6699 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6700 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6701 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6702 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6703 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6704 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6705 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6706 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6707 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6708 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6709 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6710 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6711 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6712 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6713 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0_MASK 0x1
6714 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_0__SHIFT 0x0
6715 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1_MASK 0x2
6716 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_1__SHIFT 0x1
6717 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2_MASK 0x4
6718 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_2__SHIFT 0x2
6719 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3_MASK 0x8
6720 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_3__SHIFT 0x3
6721 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4_MASK 0x10
6722 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_4__SHIFT 0x4
6723 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5_MASK 0x20
6724 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_5__SHIFT 0x5
6725 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6_MASK 0x40
6726 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_6__SHIFT 0x6
6727 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7_MASK 0x80
6728 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_7__SHIFT 0x7
6729 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8_MASK 0x100
6730 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_8__SHIFT 0x8
6731 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9_MASK 0x200
6732 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_9__SHIFT 0x9
6733 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10_MASK 0x400
6734 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_10__SHIFT 0xa
6735 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11_MASK 0x800
6736 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_11__SHIFT 0xb
6737 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12_MASK 0x1000
6738 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_12__SHIFT 0xc
6739 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13_MASK 0x2000
6740 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_13__SHIFT 0xd
6741 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14_MASK 0x4000
6742 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_14__SHIFT 0xe
6743 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15_MASK 0x8000
6744 #define VM_INVALIDATE_REQUEST__INVALIDATE_DOMAIN_15__SHIFT 0xf
6745 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0_MASK 0x1
6746 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_0__SHIFT 0x0
6747 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1_MASK 0x2
6748 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_1__SHIFT 0x1
6749 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2_MASK 0x4
6750 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_2__SHIFT 0x2
6751 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3_MASK 0x8
6752 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_3__SHIFT 0x3
6753 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4_MASK 0x10
6754 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_4__SHIFT 0x4
6755 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5_MASK 0x20
6756 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_5__SHIFT 0x5
6757 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6_MASK 0x40
6758 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_6__SHIFT 0x6
6759 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7_MASK 0x80
6760 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_7__SHIFT 0x7
6761 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8_MASK 0x100
6762 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_8__SHIFT 0x8
6763 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9_MASK 0x200
6764 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_9__SHIFT 0x9
6765 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10_MASK 0x400
6766 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_10__SHIFT 0xa
6767 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11_MASK 0x800
6768 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_11__SHIFT 0xb
6769 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12_MASK 0x1000
6770 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_12__SHIFT 0xc
6771 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13_MASK 0x2000
6772 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_13__SHIFT 0xd
6773 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14_MASK 0x4000
6774 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_14__SHIFT 0xe
6775 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15_MASK 0x8000
6776 #define VM_INVALIDATE_RESPONSE__DOMAIN_INVALIDATED_15__SHIFT 0xf
6777 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6778 #define VM_PRT_APERTURE0_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6779 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6780 #define VM_PRT_APERTURE1_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6781 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6782 #define VM_PRT_APERTURE2_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6783 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6784 #define VM_PRT_APERTURE3_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6785 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6786 #define VM_PRT_APERTURE0_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6787 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6788 #define VM_PRT_APERTURE1_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6789 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6790 #define VM_PRT_APERTURE2_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6791 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6792 #define VM_PRT_APERTURE3_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6793 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x1
6794 #define VM_PRT_CNTL__CB_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x0
6795 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS_MASK 0x2
6796 #define VM_PRT_CNTL__TC_DISABLE_READ_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x1
6797 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES_MASK 0x4
6798 #define VM_PRT_CNTL__L2_CACHE_STORE_INVALID_ENTRIES__SHIFT 0x2
6799 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES_MASK 0x8
6800 #define VM_PRT_CNTL__L1_TLB_STORE_INVALID_ENTRIES__SHIFT 0x3
6801 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x10
6802 #define VM_PRT_CNTL__CB_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x4
6803 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS_MASK 0x20
6804 #define VM_PRT_CNTL__TC_DISABLE_WRITE_FAULT_ON_UNMAPPED_ACCESS__SHIFT 0x5
6805 #define VM_PRT_CNTL__MASK_PDE0_FAULT_MASK 0x40
6806 #define VM_PRT_CNTL__MASK_PDE0_FAULT__SHIFT 0x6
6807 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x1
6808 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0
6809 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x2
6810 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1
6811 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x4
6812 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2
6813 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x8
6814 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3
6815 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x10
6816 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4
6817 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x20
6818 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5
6819 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x40
6820 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6
6821 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x80
6822 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7
6823 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x100
6824 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8
6825 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x200
6826 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9
6827 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x400
6828 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa
6829 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x800
6830 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb
6831 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x1000
6832 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc
6833 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x2000
6834 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd
6835 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x4000
6836 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe
6837 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x8000
6838 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf
6839 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
6840 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
6841 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
6842 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
6843 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
6844 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
6845 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
6846 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
6847 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
6848 #define VM_CONTEXT0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
6849 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
6850 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
6851 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
6852 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
6853 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
6854 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
6855 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
6856 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
6857 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
6858 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
6859 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
6860 #define VM_CONTEXT0_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
6861 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME_MASK 0xffffffff
6862 #define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT__NAME__SHIFT 0x0
6863 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
6864 #define VM_CONTEXT0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
6865 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
6866 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
6867 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
6868 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
6869 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR_MASK 0xfffffff
6870 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR__PHYSICAL_PAGE_ADDR__SHIFT 0x0
6871 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK 0x1ff
6872 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT__SHIFT 0x0
6873 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK_MASK 0x3fe00
6874 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_MASK__SHIFT 0x9
6875 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB_MASK 0x40000
6876 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MSB__SHIFT 0x12
6877 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB_MASK 0x80000
6878 #define VM_FAULT_CLIENT_ID__MEMORY_CLIENT_ID_MASK_MSB__SHIFT 0x13
6879 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6880 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6881 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6882 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6883 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6884 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6885 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6886 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6887 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6888 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6889 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6890 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6891 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6892 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6893 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER_MASK 0xfffffff
6894 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR__PHYSICAL_PAGE_NUMBER__SHIFT 0x0
6895 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6896 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6897 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6898 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6899 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6900 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6901 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6902 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6903 #define VM_DEBUG__FLAGS_MASK 0xffffffff
6904 #define VM_DEBUG__FLAGS__SHIFT 0x0
6905 #define VM_L2_CG__OFFDLY_MASK 0xfc0
6906 #define VM_L2_CG__OFFDLY__SHIFT 0x6
6907 #define VM_L2_CG__ENABLE_MASK 0x40000
6908 #define VM_L2_CG__ENABLE__SHIFT 0x12
6909 #define VM_L2_CG__MEM_LS_ENABLE_MASK 0x80000
6910 #define VM_L2_CG__MEM_LS_ENABLE__SHIFT 0x13
6911 #define VM_L2_CG__OVERRIDE_MASK 0x100000
6912 #define VM_L2_CG__OVERRIDE__SHIFT 0x14
6913 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK_MASK 0xfffffff
6914 #define VM_L2_BANK_SELECT_MASKA__BANK_SELECT_MASK__SHIFT 0x0
6915 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK_MASK 0xff
6916 #define VM_L2_BANK_SELECT_MASKB__BANK_SELECT_MASK__SHIFT 0x0
6917 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6918 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6919 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER_MASK 0xfffffff
6920 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR__LOGICAL_PAGE_NUMBER__SHIFT 0x0
6921 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET_MASK 0xfffffff
6922 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET__PHYSICAL_PAGE_OFFSET__SHIFT 0x0
6923 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x3f
6924 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0
6925 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x40
6926 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6
6927 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x80
6928 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7
6929 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x100
6930 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8
6931 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x200
6932 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9
6933 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x400
6934 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa
6935 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x800
6936 #define VM_L2_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb
6937 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x1000
6938 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc
6939 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x2000
6940 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd
6941 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x4000
6942 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe
6943 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x8000
6944 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf
6945 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x10000
6946 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10
6947 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x20000
6948 #define VM_L2_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11
6949 #define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x40000
6950 #define VM_L2_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12
6951 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x1ff
6952 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6953 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
6954 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6955 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x100000
6956 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14
6957 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
6958 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6959 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
6960 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6961 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x1ff
6962 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0
6963 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x7fc00
6964 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa
6965 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x100000
6966 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14
6967 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x1000000
6968 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18
6969 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x2000000
6970 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19
6971 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0xffff
6972 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0
6973 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xffff0000
6974 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10
6975 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0xffff
6976 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0
6977 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xffff0000
6978 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10
6979 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0xffff
6980 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0
6981 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xffff0000
6982 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10
6983 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0xffff
6984 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0
6985 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xffff0000
6986 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10
6987 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0xffff
6988 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0
6989 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xffff0000
6990 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10
6991 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0xffff
6992 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0
6993 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xffff0000
6994 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10
6995 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0xffff
6996 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0
6997 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xffff0000
6998 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10
6999 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0xffff
7000 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0
7001 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xffff0000
7002 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10
7003 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0xffff
7004 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0
7005 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xffff0000
7006 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10
7007 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0xffff
7008 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0
7009 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xffff0000
7010 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10
7011 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0xffff
7012 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0
7013 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xffff0000
7014 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10
7015 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0xffff
7016 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0
7017 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xffff0000
7018 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10
7019 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0xffff
7020 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0
7021 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xffff0000
7022 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10
7023 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0xffff
7024 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0
7025 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xffff0000
7026 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10
7027 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0xffff
7028 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0
7029 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xffff0000
7030 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10
7031 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0xffff
7032 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0
7033 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xffff0000
7034 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10
7035 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xffffffff
7036 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0
7037 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xffffffff
7038 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0
7039 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x800000
7040 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17
7041 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x8
7042 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3
7043 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xff800000
7044 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17
7045 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x1
7046 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0
7047 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xff800000
7048 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17
7049 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0xff
7050 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0
7051 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT_MASK 0x3fffffff
7052 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_LIMIT__SHIFT 0x0
7053 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE_MASK 0x80000000
7054 #define MC_VM_NB_TOP_OF_DRAM3__TOM3_ENABLE__SHIFT 0x1f
7055 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xfffff000
7056 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc
7057 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xfffff000
7058 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc
7059 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xfffff000
7060 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc
7061 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xfffff000
7062 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc
7063 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0xfffff
7064 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0
7065 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0xfffff
7066 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0
7067 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0xfffff
7068 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0
7069 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0xfffff
7070 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0
7071 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x1
7072 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0
7073 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x2
7074 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1
7075 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xfffff000
7076 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc
7077 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x1
7078 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0
7079 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x2
7080 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1
7081 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xfffff000
7082 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc
7083 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x1
7084 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0
7085 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x2
7086 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1
7087 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xfffff000
7088 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc
7089 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x1
7090 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0
7091 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x2
7092 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1
7093 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xfffff000
7094 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc
7095 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0xfffff
7096 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0
7097 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0xfffff
7098 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0
7099 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0xfffff
7100 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0
7101 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0xfffff
7102 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0
7103 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xfffff000
7104 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc
7105 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xfffff000
7106 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc
7107 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xfffff000
7108 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc
7109 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xfffff000
7110 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc
7111 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0xfffff
7112 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0
7113 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0xfffff
7114 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0
7115 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0xfffff
7116 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0
7117 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0xfffff
7118 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0
7119 #define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS_MASK 0x1
7120 #define MC_VM_MARC_CNTL__ENABLE_ALL_CLIENTS__SHIFT 0x0
7121 #define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK 0x1ff
7122 #define MC_VM_MB_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT 0x0
7123 #define MC_VM_MB_L1_TLS0_CNTL0__EN_MASK 0x1000
7124 #define MC_VM_MB_L1_TLS0_CNTL0__EN__SHIFT 0xc
7125 #define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE_MASK 0x2000
7126 #define MC_VM_MB_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT 0xd
7127 #define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK 0x1ff
7128 #define MC_VM_MB_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT 0x0
7129 #define MC_VM_MB_L1_TLS0_CNTL1__EN_MASK 0x1000
7130 #define MC_VM_MB_L1_TLS0_CNTL1__EN__SHIFT 0xc
7131 #define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE_MASK 0x2000
7132 #define MC_VM_MB_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT 0xd
7133 #define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK 0x1ff
7134 #define MC_VM_MB_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT 0x0
7135 #define MC_VM_MB_L1_TLS0_CNTL2__EN_MASK 0x1000
7136 #define MC_VM_MB_L1_TLS0_CNTL2__EN__SHIFT 0xc
7137 #define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE_MASK 0x2000
7138 #define MC_VM_MB_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT 0xd
7139 #define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK 0x1ff
7140 #define MC_VM_MB_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT 0x0
7141 #define MC_VM_MB_L1_TLS0_CNTL3__EN_MASK 0x1000
7142 #define MC_VM_MB_L1_TLS0_CNTL3__EN__SHIFT 0xc
7143 #define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE_MASK 0x2000
7144 #define MC_VM_MB_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT 0xd
7145 #define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK 0x1ff
7146 #define MC_VM_MB_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT 0x0
7147 #define MC_VM_MB_L1_TLS0_CNTL4__EN_MASK 0x1000
7148 #define MC_VM_MB_L1_TLS0_CNTL4__EN__SHIFT 0xc
7149 #define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE_MASK 0x2000
7150 #define MC_VM_MB_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT 0xd
7151 #define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK 0x1ff
7152 #define MC_VM_MB_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT 0x0
7153 #define MC_VM_MB_L1_TLS0_CNTL5__EN_MASK 0x1000
7154 #define MC_VM_MB_L1_TLS0_CNTL5__EN__SHIFT 0xc
7155 #define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE_MASK 0x2000
7156 #define MC_VM_MB_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT 0xd
7157 #define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK 0x1ff
7158 #define MC_VM_MB_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT 0x0
7159 #define MC_VM_MB_L1_TLS0_CNTL6__EN_MASK 0x1000
7160 #define MC_VM_MB_L1_TLS0_CNTL6__EN__SHIFT 0xc
7161 #define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE_MASK 0x2000
7162 #define MC_VM_MB_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT 0xd
7163 #define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK 0x1ff
7164 #define MC_VM_MB_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT 0x0
7165 #define MC_VM_MB_L1_TLS0_CNTL7__EN_MASK 0x1000
7166 #define MC_VM_MB_L1_TLS0_CNTL7__EN__SHIFT 0xc
7167 #define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE_MASK 0x2000
7168 #define MC_VM_MB_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT 0xd
7169 #define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK 0x1ff
7170 #define MC_VM_MB_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT 0x0
7171 #define MC_VM_MB_L1_TLS0_CNTL8__EN_MASK 0x1000
7172 #define MC_VM_MB_L1_TLS0_CNTL8__EN__SHIFT 0xc
7173 #define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE_MASK 0x2000
7174 #define MC_VM_MB_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT 0xd
7175 #define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR_MASK 0xfffffff
7176 #define MC_VM_MB_L1_TLS0_START_ADDR0__START_ADDR__SHIFT 0x0
7177 #define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR_MASK 0xfffffff
7178 #define MC_VM_MB_L1_TLS0_START_ADDR1__START_ADDR__SHIFT 0x0
7179 #define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR_MASK 0xfffffff
7180 #define MC_VM_MB_L1_TLS0_START_ADDR2__START_ADDR__SHIFT 0x0
7181 #define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR_MASK 0xfffffff
7182 #define MC_VM_MB_L1_TLS0_START_ADDR3__START_ADDR__SHIFT 0x0
7183 #define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR_MASK 0xfffffff
7184 #define MC_VM_MB_L1_TLS0_START_ADDR4__START_ADDR__SHIFT 0x0
7185 #define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR_MASK 0xfffffff
7186 #define MC_VM_MB_L1_TLS0_START_ADDR5__START_ADDR__SHIFT 0x0
7187 #define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR_MASK 0xfffffff
7188 #define MC_VM_MB_L1_TLS0_START_ADDR6__START_ADDR__SHIFT 0x0
7189 #define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR_MASK 0xfffffff
7190 #define MC_VM_MB_L1_TLS0_START_ADDR7__START_ADDR__SHIFT 0x0
7191 #define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR_MASK 0xfffffff
7192 #define MC_VM_MB_L1_TLS0_START_ADDR8__START_ADDR__SHIFT 0x0
7193 #define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR_MASK 0xfffffff
7194 #define MC_VM_MB_L1_TLS0_END_ADDR0__END_ADDR__SHIFT 0x0
7195 #define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR_MASK 0xfffffff
7196 #define MC_VM_MB_L1_TLS0_END_ADDR1__END_ADDR__SHIFT 0x0
7197 #define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR_MASK 0xfffffff
7198 #define MC_VM_MB_L1_TLS0_END_ADDR2__END_ADDR__SHIFT 0x0
7199 #define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR_MASK 0xfffffff
7200 #define MC_VM_MB_L1_TLS0_END_ADDR3__END_ADDR__SHIFT 0x0
7201 #define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR_MASK 0xfffffff
7202 #define MC_VM_MB_L1_TLS0_END_ADDR4__END_ADDR__SHIFT 0x0
7203 #define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR_MASK 0xfffffff
7204 #define MC_VM_MB_L1_TLS0_END_ADDR5__END_ADDR__SHIFT 0x0
7205 #define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR_MASK 0xfffffff
7206 #define MC_VM_MB_L1_TLS0_END_ADDR6__END_ADDR__SHIFT 0x0
7207 #define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR_MASK 0xfffffff
7208 #define MC_VM_MB_L1_TLS0_END_ADDR7__END_ADDR__SHIFT 0x0
7209 #define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR_MASK 0xfffffff
7210 #define MC_VM_MB_L1_TLS0_END_ADDR8__END_ADDR__SHIFT 0x0
7211 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK 0xff
7212 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT 0x0
7213 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK 0x1ff000
7214 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT 0xc
7215 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK 0x1000000
7216 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT 0x18
7217 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK 0x1e000000
7218 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x19
7219 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x20000000
7220 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x1d
7221 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR_MASK 0xfffffff
7222 #define MC_VM_MB_L1_TLS0_PROTECTION_FAULT_ADDR__LOGICAL_PAGE_ADDR__SHIFT 0x0
7223 #define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS_MASK 0x3
7224 #define MC_SEQ_CNTL__MEM_ADDR_MAP_COLS__SHIFT 0x0
7225 #define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK_MASK 0xc
7226 #define MC_SEQ_CNTL__MEM_ADDR_MAP_BANK__SHIFT 0x2
7227 #define MC_SEQ_CNTL__SAFE_MODE_MASK 0x30
7228 #define MC_SEQ_CNTL__SAFE_MODE__SHIFT 0x4
7229 #define MC_SEQ_CNTL__DAT_INV_MASK 0x40
7230 #define MC_SEQ_CNTL__DAT_INV__SHIFT 0x6
7231 #define MC_SEQ_CNTL__MSK_DF1_MASK 0x80
7232 #define MC_SEQ_CNTL__MSK_DF1__SHIFT 0x7
7233 #define MC_SEQ_CNTL__CHANNEL_DISABLE_MASK 0x300
7234 #define MC_SEQ_CNTL__CHANNEL_DISABLE__SHIFT 0x8
7235 #define MC_SEQ_CNTL__MSKOFF_DAT_TL_MASK 0x4000
7236 #define MC_SEQ_CNTL__MSKOFF_DAT_TL__SHIFT 0xe
7237 #define MC_SEQ_CNTL__MSKOFF_DAT_TH_MASK 0x8000
7238 #define MC_SEQ_CNTL__MSKOFF_DAT_TH__SHIFT 0xf
7239 #define MC_SEQ_CNTL__RET_HOLD_EOP_MASK 0x10000
7240 #define MC_SEQ_CNTL__RET_HOLD_EOP__SHIFT 0x10
7241 #define MC_SEQ_CNTL__BANKGROUP_SIZE_MASK 0x20000
7242 #define MC_SEQ_CNTL__BANKGROUP_SIZE__SHIFT 0x11
7243 #define MC_SEQ_CNTL__BANKGROUP_ENB_MASK 0x40000
7244 #define MC_SEQ_CNTL__BANKGROUP_ENB__SHIFT 0x12
7245 #define MC_SEQ_CNTL__RTR_OVERRIDE_MASK 0x80000
7246 #define MC_SEQ_CNTL__RTR_OVERRIDE__SHIFT 0x13
7247 #define MC_SEQ_CNTL__ARB_REQCMD_WMK_MASK 0xf00000
7248 #define MC_SEQ_CNTL__ARB_REQCMD_WMK__SHIFT 0x14
7249 #define MC_SEQ_CNTL__ARB_REQDAT_WMK_MASK 0xf000000
7250 #define MC_SEQ_CNTL__ARB_REQDAT_WMK__SHIFT 0x18
7251 #define MC_SEQ_CNTL__ARB_RTDAT_WMK_MASK 0xf0000000
7252 #define MC_SEQ_CNTL__ARB_RTDAT_WMK__SHIFT 0x1c
7253 #define MC_SEQ_CNTL_2__DRST_PDRV_MASK 0xf
7254 #define MC_SEQ_CNTL_2__DRST_PDRV__SHIFT 0x0
7255 #define MC_SEQ_CNTL_2__DRST_PU_MASK 0x10
7256 #define MC_SEQ_CNTL_2__DRST_PU__SHIFT 0x4
7257 #define MC_SEQ_CNTL_2__DRST_PD_MASK 0x20
7258 #define MC_SEQ_CNTL_2__DRST_PD__SHIFT 0x5
7259 #define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB_MASK 0x300
7260 #define MC_SEQ_CNTL_2__ARB_RTDAT_WMK_MSB__SHIFT 0x8
7261 #define MC_SEQ_CNTL_2__DRST_NSTR_MASK 0xfc00
7262 #define MC_SEQ_CNTL_2__DRST_NSTR__SHIFT 0xa
7263 #define MC_SEQ_CNTL_2__DRST_PSTR_MASK 0x3f0000
7264 #define MC_SEQ_CNTL_2__DRST_PSTR__SHIFT 0x10
7265 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0_MASK 0x400000
7266 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D0__SHIFT 0x16
7267 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1_MASK 0x800000
7268 #define MC_SEQ_CNTL_2__PLL_TX_PWRON_D1__SHIFT 0x17
7269 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0_MASK 0xf000000
7270 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D0__SHIFT 0x18
7271 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1_MASK 0xf0000000
7272 #define MC_SEQ_CNTL_2__PLL_RX_PWRON_D1__SHIFT 0x1c
7273 #define MC_SEQ_DRAM__ADR_2CK_MASK 0x1
7274 #define MC_SEQ_DRAM__ADR_2CK__SHIFT 0x0
7275 #define MC_SEQ_DRAM__ADR_MUX_MASK 0x2
7276 #define MC_SEQ_DRAM__ADR_MUX__SHIFT 0x1
7277 #define MC_SEQ_DRAM__ADR_DF1_MASK 0x4
7278 #define MC_SEQ_DRAM__ADR_DF1__SHIFT 0x2
7279 #define MC_SEQ_DRAM__AP8_MASK 0x8
7280 #define MC_SEQ_DRAM__AP8__SHIFT 0x3
7281 #define MC_SEQ_DRAM__DAT_DF1_MASK 0x10
7282 #define MC_SEQ_DRAM__DAT_DF1__SHIFT 0x4
7283 #define MC_SEQ_DRAM__DQS_DF1_MASK 0x20
7284 #define MC_SEQ_DRAM__DQS_DF1__SHIFT 0x5
7285 #define MC_SEQ_DRAM__DQM_DF1_MASK 0x40
7286 #define MC_SEQ_DRAM__DQM_DF1__SHIFT 0x6
7287 #define MC_SEQ_DRAM__DQM_ACT_MASK 0x80
7288 #define MC_SEQ_DRAM__DQM_ACT__SHIFT 0x7
7289 #define MC_SEQ_DRAM__STB_CNT_MASK 0xf00
7290 #define MC_SEQ_DRAM__STB_CNT__SHIFT 0x8
7291 #define MC_SEQ_DRAM__CKE_DYN_MASK 0x1000
7292 #define MC_SEQ_DRAM__CKE_DYN__SHIFT 0xc
7293 #define MC_SEQ_DRAM__CKE_ACT_MASK 0x2000
7294 #define MC_SEQ_DRAM__CKE_ACT__SHIFT 0xd
7295 #define MC_SEQ_DRAM__BO4_MASK 0x4000
7296 #define MC_SEQ_DRAM__BO4__SHIFT 0xe
7297 #define MC_SEQ_DRAM__DLL_CLR_MASK 0x8000
7298 #define MC_SEQ_DRAM__DLL_CLR__SHIFT 0xf
7299 #define MC_SEQ_DRAM__DLL_CNT_MASK 0xff0000
7300 #define MC_SEQ_DRAM__DLL_CNT__SHIFT 0x10
7301 #define MC_SEQ_DRAM__DAT_INV_MASK 0x1000000
7302 #define MC_SEQ_DRAM__DAT_INV__SHIFT 0x18
7303 #define MC_SEQ_DRAM__INV_ACM_MASK 0x2000000
7304 #define MC_SEQ_DRAM__INV_ACM__SHIFT 0x19
7305 #define MC_SEQ_DRAM__ODT_ENB_MASK 0x4000000
7306 #define MC_SEQ_DRAM__ODT_ENB__SHIFT 0x1a
7307 #define MC_SEQ_DRAM__ODT_ACT_MASK 0x8000000
7308 #define MC_SEQ_DRAM__ODT_ACT__SHIFT 0x1b
7309 #define MC_SEQ_DRAM__RST_CTL_MASK 0x10000000
7310 #define MC_SEQ_DRAM__RST_CTL__SHIFT 0x1c
7311 #define MC_SEQ_DRAM__TRI_MIO_DYN_MASK 0x20000000
7312 #define MC_SEQ_DRAM__TRI_MIO_DYN__SHIFT 0x1d
7313 #define MC_SEQ_DRAM__TRI_CKE_MASK 0x40000000
7314 #define MC_SEQ_DRAM__TRI_CKE__SHIFT 0x1e
7315 #define MC_SEQ_DRAM__RDSTRB_RSYC_DIS_MASK 0x80000000
7316 #define MC_SEQ_DRAM__RDSTRB_RSYC_DIS__SHIFT 0x1f
7317 #define MC_SEQ_DRAM_2__ADR_DDR_MASK 0x1
7318 #define MC_SEQ_DRAM_2__ADR_DDR__SHIFT 0x0
7319 #define MC_SEQ_DRAM_2__ADR_DBI_MASK 0x2
7320 #define MC_SEQ_DRAM_2__ADR_DBI__SHIFT 0x1
7321 #define MC_SEQ_DRAM_2__ADR_DBI_ACM_MASK 0x4
7322 #define MC_SEQ_DRAM_2__ADR_DBI_ACM__SHIFT 0x2
7323 #define MC_SEQ_DRAM_2__CMD_QDR_MASK 0x8
7324 #define MC_SEQ_DRAM_2__CMD_QDR__SHIFT 0x3
7325 #define MC_SEQ_DRAM_2__DAT_QDR_MASK 0x10
7326 #define MC_SEQ_DRAM_2__DAT_QDR__SHIFT 0x4
7327 #define MC_SEQ_DRAM_2__WDAT_EDC_MASK 0x20
7328 #define MC_SEQ_DRAM_2__WDAT_EDC__SHIFT 0x5
7329 #define MC_SEQ_DRAM_2__RDAT_EDC_MASK 0x40
7330 #define MC_SEQ_DRAM_2__RDAT_EDC__SHIFT 0x6
7331 #define MC_SEQ_DRAM_2__DQM_EST_MASK 0x80
7332 #define MC_SEQ_DRAM_2__DQM_EST__SHIFT 0x7
7333 #define MC_SEQ_DRAM_2__RD_DQS_MASK 0x100
7334 #define MC_SEQ_DRAM_2__RD_DQS__SHIFT 0x8
7335 #define MC_SEQ_DRAM_2__WR_DQS_MASK 0x200
7336 #define MC_SEQ_DRAM_2__WR_DQS__SHIFT 0x9
7337 #define MC_SEQ_DRAM_2__PLL_EST_MASK 0x400
7338 #define MC_SEQ_DRAM_2__PLL_EST__SHIFT 0xa
7339 #define MC_SEQ_DRAM_2__PLL_CLR_MASK 0x800
7340 #define MC_SEQ_DRAM_2__PLL_CLR__SHIFT 0xb
7341 #define MC_SEQ_DRAM_2__DLL_EST_MASK 0x1000
7342 #define MC_SEQ_DRAM_2__DLL_EST__SHIFT 0xc
7343 #define MC_SEQ_DRAM_2__BNK_MRS_MASK 0x2000
7344 #define MC_SEQ_DRAM_2__BNK_MRS__SHIFT 0xd
7345 #define MC_SEQ_DRAM_2__DBI_OVR_MASK 0x4000
7346 #define MC_SEQ_DRAM_2__DBI_OVR__SHIFT 0xe
7347 #define MC_SEQ_DRAM_2__TRI_CLK_MASK 0x8000
7348 #define MC_SEQ_DRAM_2__TRI_CLK__SHIFT 0xf
7349 #define MC_SEQ_DRAM_2__PLL_CNT_MASK 0xff0000
7350 #define MC_SEQ_DRAM_2__PLL_CNT__SHIFT 0x10
7351 #define MC_SEQ_DRAM_2__PCH_BNK_MASK 0x1000000
7352 #define MC_SEQ_DRAM_2__PCH_BNK__SHIFT 0x18
7353 #define MC_SEQ_DRAM_2__ADBI_DF1_MASK 0x2000000
7354 #define MC_SEQ_DRAM_2__ADBI_DF1__SHIFT 0x19
7355 #define MC_SEQ_DRAM_2__ADBI_ACT_MASK 0x4000000
7356 #define MC_SEQ_DRAM_2__ADBI_ACT__SHIFT 0x1a
7357 #define MC_SEQ_DRAM_2__DBI_DF1_MASK 0x8000000
7358 #define MC_SEQ_DRAM_2__DBI_DF1__SHIFT 0x1b
7359 #define MC_SEQ_DRAM_2__DBI_ACT_MASK 0x10000000
7360 #define MC_SEQ_DRAM_2__DBI_ACT__SHIFT 0x1c
7361 #define MC_SEQ_DRAM_2__DBI_EDC_DF1_MASK 0x20000000
7362 #define MC_SEQ_DRAM_2__DBI_EDC_DF1__SHIFT 0x1d
7363 #define MC_SEQ_DRAM_2__TESTCHIP_EN_MASK 0x40000000
7364 #define MC_SEQ_DRAM_2__TESTCHIP_EN__SHIFT 0x1e
7365 #define MC_SEQ_DRAM_2__CS_BY16_MASK 0x80000000
7366 #define MC_SEQ_DRAM_2__CS_BY16__SHIFT 0x1f
7367 #define MC_SEQ_RAS_TIMING__TRCDW_MASK 0x1f
7368 #define MC_SEQ_RAS_TIMING__TRCDW__SHIFT 0x0
7369 #define MC_SEQ_RAS_TIMING__TRCDWA_MASK 0x3e0
7370 #define MC_SEQ_RAS_TIMING__TRCDWA__SHIFT 0x5
7371 #define MC_SEQ_RAS_TIMING__TRCDR_MASK 0x7c00
7372 #define MC_SEQ_RAS_TIMING__TRCDR__SHIFT 0xa
7373 #define MC_SEQ_RAS_TIMING__TRCDRA_MASK 0xf8000
7374 #define MC_SEQ_RAS_TIMING__TRCDRA__SHIFT 0xf
7375 #define MC_SEQ_RAS_TIMING__TRRD_MASK 0xf00000
7376 #define MC_SEQ_RAS_TIMING__TRRD__SHIFT 0x14
7377 #define MC_SEQ_RAS_TIMING__TRC_MASK 0x7f000000
7378 #define MC_SEQ_RAS_TIMING__TRC__SHIFT 0x18
7379 #define MC_SEQ_CAS_TIMING__TNOPW_MASK 0x3
7380 #define MC_SEQ_CAS_TIMING__TNOPW__SHIFT 0x0
7381 #define MC_SEQ_CAS_TIMING__TNOPR_MASK 0xc
7382 #define MC_SEQ_CAS_TIMING__TNOPR__SHIFT 0x2
7383 #define MC_SEQ_CAS_TIMING__TR2W_MASK 0x1f0
7384 #define MC_SEQ_CAS_TIMING__TR2W__SHIFT 0x4
7385 #define MC_SEQ_CAS_TIMING__TCCDL_MASK 0xe00
7386 #define MC_SEQ_CAS_TIMING__TCCDL__SHIFT 0x9
7387 #define MC_SEQ_CAS_TIMING__TR2R_MASK 0xf000
7388 #define MC_SEQ_CAS_TIMING__TR2R__SHIFT 0xc
7389 #define MC_SEQ_CAS_TIMING__TW2R_MASK 0x1f0000
7390 #define MC_SEQ_CAS_TIMING__TW2R__SHIFT 0x10
7391 #define MC_SEQ_CAS_TIMING__TCL_MASK 0x1f000000
7392 #define MC_SEQ_CAS_TIMING__TCL__SHIFT 0x18
7393 #define MC_SEQ_MISC_TIMING__TRP_WRA_MASK 0x3f
7394 #define MC_SEQ_MISC_TIMING__TRP_WRA__SHIFT 0x0
7395 #define MC_SEQ_MISC_TIMING__TRP_RDA_MASK 0x3f00
7396 #define MC_SEQ_MISC_TIMING__TRP_RDA__SHIFT 0x8
7397 #define MC_SEQ_MISC_TIMING__TRP_MASK 0xf8000
7398 #define MC_SEQ_MISC_TIMING__TRP__SHIFT 0xf
7399 #define MC_SEQ_MISC_TIMING__TRFC_MASK 0x1ff00000
7400 #define MC_SEQ_MISC_TIMING__TRFC__SHIFT 0x14
7401 #define MC_SEQ_MISC_TIMING2__PA2RDATA_MASK 0x7
7402 #define MC_SEQ_MISC_TIMING2__PA2RDATA__SHIFT 0x0
7403 #define MC_SEQ_MISC_TIMING2__PA2WDATA_MASK 0x70
7404 #define MC_SEQ_MISC_TIMING2__PA2WDATA__SHIFT 0x4
7405 #define MC_SEQ_MISC_TIMING2__FAW_MASK 0x1f00
7406 #define MC_SEQ_MISC_TIMING2__FAW__SHIFT 0x8
7407 #define MC_SEQ_MISC_TIMING2__TREDC_MASK 0xe000
7408 #define MC_SEQ_MISC_TIMING2__TREDC__SHIFT 0xd
7409 #define MC_SEQ_MISC_TIMING2__TWEDC_MASK 0x1f0000
7410 #define MC_SEQ_MISC_TIMING2__TWEDC__SHIFT 0x10
7411 #define MC_SEQ_MISC_TIMING2__T32AW_MASK 0x1e00000
7412 #define MC_SEQ_MISC_TIMING2__T32AW__SHIFT 0x15
7413 #define MC_SEQ_MISC_TIMING2__TWDATATR_MASK 0xf0000000
7414 #define MC_SEQ_MISC_TIMING2__TWDATATR__SHIFT 0x1c
7415 #define MC_SEQ_PMG_TIMING__TCKSRE_MASK 0x7
7416 #define MC_SEQ_PMG_TIMING__TCKSRE__SHIFT 0x0
7417 #define MC_SEQ_PMG_TIMING__TCKSRX_MASK 0x70
7418 #define MC_SEQ_PMG_TIMING__TCKSRX__SHIFT 0x4
7419 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MASK 0xf00
7420 #define MC_SEQ_PMG_TIMING__TCKE_PULSE__SHIFT 0x8
7421 #define MC_SEQ_PMG_TIMING__TCKE_MASK 0x3f000
7422 #define MC_SEQ_PMG_TIMING__TCKE__SHIFT 0xc
7423 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_MASK 0x1c0000
7424 #define MC_SEQ_PMG_TIMING__SEQ_IDLE__SHIFT 0x12
7425 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB_MASK 0x800000
7426 #define MC_SEQ_PMG_TIMING__TCKE_PULSE_MSB__SHIFT 0x17
7427 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS_MASK 0xff000000
7428 #define MC_SEQ_PMG_TIMING__SEQ_IDLE_SS__SHIFT 0x18
7429 #define MC_SEQ_RD_CTL_D0__RCV_DLY_MASK 0x7
7430 #define MC_SEQ_RD_CTL_D0__RCV_DLY__SHIFT 0x0
7431 #define MC_SEQ_RD_CTL_D0__RCV_EXT_MASK 0xf8
7432 #define MC_SEQ_RD_CTL_D0__RCV_EXT__SHIFT 0x3
7433 #define MC_SEQ_RD_CTL_D0__RST_SEL_MASK 0x300
7434 #define MC_SEQ_RD_CTL_D0__RST_SEL__SHIFT 0x8
7435 #define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY_MASK 0xc00
7436 #define MC_SEQ_RD_CTL_D0__RXDPWRON_DLY__SHIFT 0xa
7437 #define MC_SEQ_RD_CTL_D0__RST_HLD_MASK 0xf000
7438 #define MC_SEQ_RD_CTL_D0__RST_HLD__SHIFT 0xc
7439 #define MC_SEQ_RD_CTL_D0__STR_PRE_MASK 0x10000
7440 #define MC_SEQ_RD_CTL_D0__STR_PRE__SHIFT 0x10
7441 #define MC_SEQ_RD_CTL_D0__STR_PST_MASK 0x20000
7442 #define MC_SEQ_RD_CTL_D0__STR_PST__SHIFT 0x11
7443 #define MC_SEQ_RD_CTL_D0__RBS_DLY_MASK 0x1f00000
7444 #define MC_SEQ_RD_CTL_D0__RBS_DLY__SHIFT 0x14
7445 #define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY_MASK 0x3e000000
7446 #define MC_SEQ_RD_CTL_D0__RBS_WEDC_DLY__SHIFT 0x19
7447 #define MC_SEQ_RD_CTL_D1__RCV_DLY_MASK 0x7
7448 #define MC_SEQ_RD_CTL_D1__RCV_DLY__SHIFT 0x0
7449 #define MC_SEQ_RD_CTL_D1__RCV_EXT_MASK 0xf8
7450 #define MC_SEQ_RD_CTL_D1__RCV_EXT__SHIFT 0x3
7451 #define MC_SEQ_RD_CTL_D1__RST_SEL_MASK 0x300
7452 #define MC_SEQ_RD_CTL_D1__RST_SEL__SHIFT 0x8
7453 #define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY_MASK 0xc00
7454 #define MC_SEQ_RD_CTL_D1__RXDPWRON_DLY__SHIFT 0xa
7455 #define MC_SEQ_RD_CTL_D1__RST_HLD_MASK 0xf000
7456 #define MC_SEQ_RD_CTL_D1__RST_HLD__SHIFT 0xc
7457 #define MC_SEQ_RD_CTL_D1__STR_PRE_MASK 0x10000
7458 #define MC_SEQ_RD_CTL_D1__STR_PRE__SHIFT 0x10
7459 #define MC_SEQ_RD_CTL_D1__STR_PST_MASK 0x20000
7460 #define MC_SEQ_RD_CTL_D1__STR_PST__SHIFT 0x11
7461 #define MC_SEQ_RD_CTL_D1__RBS_DLY_MASK 0x1f00000
7462 #define MC_SEQ_RD_CTL_D1__RBS_DLY__SHIFT 0x14
7463 #define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY_MASK 0x3e000000
7464 #define MC_SEQ_RD_CTL_D1__RBS_WEDC_DLY__SHIFT 0x19
7465 #define MC_SEQ_WR_CTL_D0__DAT_DLY_MASK 0xf
7466 #define MC_SEQ_WR_CTL_D0__DAT_DLY__SHIFT 0x0
7467 #define MC_SEQ_WR_CTL_D0__DQS_DLY_MASK 0xf0
7468 #define MC_SEQ_WR_CTL_D0__DQS_DLY__SHIFT 0x4
7469 #define MC_SEQ_WR_CTL_D0__DQS_XTR_MASK 0x100
7470 #define MC_SEQ_WR_CTL_D0__DQS_XTR__SHIFT 0x8
7471 #define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY_MASK 0x200
7472 #define MC_SEQ_WR_CTL_D0__DAT_2Y_DLY__SHIFT 0x9
7473 #define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY_MASK 0x400
7474 #define MC_SEQ_WR_CTL_D0__ADR_2Y_DLY__SHIFT 0xa
7475 #define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY_MASK 0x800
7476 #define MC_SEQ_WR_CTL_D0__CMD_2Y_DLY__SHIFT 0xb
7477 #define MC_SEQ_WR_CTL_D0__OEN_DLY_MASK 0xf000
7478 #define MC_SEQ_WR_CTL_D0__OEN_DLY__SHIFT 0xc
7479 #define MC_SEQ_WR_CTL_D0__OEN_EXT_MASK 0xf0000
7480 #define MC_SEQ_WR_CTL_D0__OEN_EXT__SHIFT 0x10
7481 #define MC_SEQ_WR_CTL_D0__OEN_SEL_MASK 0x300000
7482 #define MC_SEQ_WR_CTL_D0__OEN_SEL__SHIFT 0x14
7483 #define MC_SEQ_WR_CTL_D0__ODT_DLY_MASK 0xf000000
7484 #define MC_SEQ_WR_CTL_D0__ODT_DLY__SHIFT 0x18
7485 #define MC_SEQ_WR_CTL_D0__ODT_EXT_MASK 0x10000000
7486 #define MC_SEQ_WR_CTL_D0__ODT_EXT__SHIFT 0x1c
7487 #define MC_SEQ_WR_CTL_D0__ADR_DLY_MASK 0x20000000
7488 #define MC_SEQ_WR_CTL_D0__ADR_DLY__SHIFT 0x1d
7489 #define MC_SEQ_WR_CTL_D0__CMD_DLY_MASK 0x40000000
7490 #define MC_SEQ_WR_CTL_D0__CMD_DLY__SHIFT 0x1e
7491 #define MC_SEQ_WR_CTL_D1__DAT_DLY_MASK 0xf
7492 #define MC_SEQ_WR_CTL_D1__DAT_DLY__SHIFT 0x0
7493 #define MC_SEQ_WR_CTL_D1__DQS_DLY_MASK 0xf0
7494 #define MC_SEQ_WR_CTL_D1__DQS_DLY__SHIFT 0x4
7495 #define MC_SEQ_WR_CTL_D1__DQS_XTR_MASK 0x100
7496 #define MC_SEQ_WR_CTL_D1__DQS_XTR__SHIFT 0x8
7497 #define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY_MASK 0x200
7498 #define MC_SEQ_WR_CTL_D1__DAT_2Y_DLY__SHIFT 0x9
7499 #define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY_MASK 0x400
7500 #define MC_SEQ_WR_CTL_D1__ADR_2Y_DLY__SHIFT 0xa
7501 #define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY_MASK 0x800
7502 #define MC_SEQ_WR_CTL_D1__CMD_2Y_DLY__SHIFT 0xb
7503 #define MC_SEQ_WR_CTL_D1__OEN_DLY_MASK 0xf000
7504 #define MC_SEQ_WR_CTL_D1__OEN_DLY__SHIFT 0xc
7505 #define MC_SEQ_WR_CTL_D1__OEN_EXT_MASK 0xf0000
7506 #define MC_SEQ_WR_CTL_D1__OEN_EXT__SHIFT 0x10
7507 #define MC_SEQ_WR_CTL_D1__OEN_SEL_MASK 0x300000
7508 #define MC_SEQ_WR_CTL_D1__OEN_SEL__SHIFT 0x14
7509 #define MC_SEQ_WR_CTL_D1__ODT_DLY_MASK 0xf000000
7510 #define MC_SEQ_WR_CTL_D1__ODT_DLY__SHIFT 0x18
7511 #define MC_SEQ_WR_CTL_D1__ODT_EXT_MASK 0x10000000
7512 #define MC_SEQ_WR_CTL_D1__ODT_EXT__SHIFT 0x1c
7513 #define MC_SEQ_WR_CTL_D1__ADR_DLY_MASK 0x20000000
7514 #define MC_SEQ_WR_CTL_D1__ADR_DLY__SHIFT 0x1d
7515 #define MC_SEQ_WR_CTL_D1__CMD_DLY_MASK 0x40000000
7516 #define MC_SEQ_WR_CTL_D1__CMD_DLY__SHIFT 0x1e
7517 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0_MASK 0x1
7518 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D0__SHIFT 0x0
7519 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0_MASK 0x2
7520 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D0__SHIFT 0x1
7521 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0_MASK 0x4
7522 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D0__SHIFT 0x2
7523 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1_MASK 0x8
7524 #define MC_SEQ_WR_CTL_2__DAT_DLY_H_D1__SHIFT 0x3
7525 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1_MASK 0x10
7526 #define MC_SEQ_WR_CTL_2__DQS_DLY_H_D1__SHIFT 0x4
7527 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1_MASK 0x20
7528 #define MC_SEQ_WR_CTL_2__OEN_DLY_H_D1__SHIFT 0x5
7529 #define MC_SEQ_WR_CTL_2__WCDR_EN_MASK 0x40
7530 #define MC_SEQ_WR_CTL_2__WCDR_EN__SHIFT 0x6
7531 #define MC_SEQ_CMD__ADR_MASK 0xffff
7532 #define MC_SEQ_CMD__ADR__SHIFT 0x0
7533 #define MC_SEQ_CMD__MOP_MASK 0xf0000
7534 #define MC_SEQ_CMD__MOP__SHIFT 0x10
7535 #define MC_SEQ_CMD__END_MASK 0x100000
7536 #define MC_SEQ_CMD__END__SHIFT 0x14
7537 #define MC_SEQ_CMD__CSB_MASK 0x600000
7538 #define MC_SEQ_CMD__CSB__SHIFT 0x15
7539 #define MC_SEQ_CMD__CHAN0_MASK 0x1000000
7540 #define MC_SEQ_CMD__CHAN0__SHIFT 0x18
7541 #define MC_SEQ_CMD__CHAN1_MASK 0x2000000
7542 #define MC_SEQ_CMD__CHAN1__SHIFT 0x19
7543 #define MC_SEQ_CMD__ADR_MSB1_MASK 0x10000000
7544 #define MC_SEQ_CMD__ADR_MSB1__SHIFT 0x1c
7545 #define MC_SEQ_CMD__ADR_MSB0_MASK 0x20000000
7546 #define MC_SEQ_CMD__ADR_MSB0__SHIFT 0x1d
7547 #define MC_PMG_CMD_EMRS__ADR_MASK 0xffff
7548 #define MC_PMG_CMD_EMRS__ADR__SHIFT 0x0
7549 #define MC_PMG_CMD_EMRS__MOP_MASK 0x70000
7550 #define MC_PMG_CMD_EMRS__MOP__SHIFT 0x10
7551 #define MC_PMG_CMD_EMRS__BNK_MSB_MASK 0x80000
7552 #define MC_PMG_CMD_EMRS__BNK_MSB__SHIFT 0x13
7553 #define MC_PMG_CMD_EMRS__END_MASK 0x100000
7554 #define MC_PMG_CMD_EMRS__END__SHIFT 0x14
7555 #define MC_PMG_CMD_EMRS__CSB_MASK 0x600000
7556 #define MC_PMG_CMD_EMRS__CSB__SHIFT 0x15
7557 #define MC_PMG_CMD_EMRS__ADR_MSB1_MASK 0x10000000
7558 #define MC_PMG_CMD_EMRS__ADR_MSB1__SHIFT 0x1c
7559 #define MC_PMG_CMD_EMRS__ADR_MSB0_MASK 0x20000000
7560 #define MC_PMG_CMD_EMRS__ADR_MSB0__SHIFT 0x1d
7561 #define MC_PMG_CMD_MRS__ADR_MASK 0xffff
7562 #define MC_PMG_CMD_MRS__ADR__SHIFT 0x0
7563 #define MC_PMG_CMD_MRS__MOP_MASK 0x70000
7564 #define MC_PMG_CMD_MRS__MOP__SHIFT 0x10
7565 #define MC_PMG_CMD_MRS__BNK_MSB_MASK 0x80000
7566 #define MC_PMG_CMD_MRS__BNK_MSB__SHIFT 0x13
7567 #define MC_PMG_CMD_MRS__END_MASK 0x100000
7568 #define MC_PMG_CMD_MRS__END__SHIFT 0x14
7569 #define MC_PMG_CMD_MRS__CSB_MASK 0x600000
7570 #define MC_PMG_CMD_MRS__CSB__SHIFT 0x15
7571 #define MC_PMG_CMD_MRS__ADR_MSB1_MASK 0x10000000
7572 #define MC_PMG_CMD_MRS__ADR_MSB1__SHIFT 0x1c
7573 #define MC_PMG_CMD_MRS__ADR_MSB0_MASK 0x20000000
7574 #define MC_PMG_CMD_MRS__ADR_MSB0__SHIFT 0x1d
7575 #define MC_PMG_CMD_MRS1__ADR_MASK 0xffff
7576 #define MC_PMG_CMD_MRS1__ADR__SHIFT 0x0
7577 #define MC_PMG_CMD_MRS1__MOP_MASK 0x70000
7578 #define MC_PMG_CMD_MRS1__MOP__SHIFT 0x10
7579 #define MC_PMG_CMD_MRS1__BNK_MSB_MASK 0x80000
7580 #define MC_PMG_CMD_MRS1__BNK_MSB__SHIFT 0x13
7581 #define MC_PMG_CMD_MRS1__END_MASK 0x100000
7582 #define MC_PMG_CMD_MRS1__END__SHIFT 0x14
7583 #define MC_PMG_CMD_MRS1__CSB_MASK 0x600000
7584 #define MC_PMG_CMD_MRS1__CSB__SHIFT 0x15
7585 #define MC_PMG_CMD_MRS1__ADR_MSB1_MASK 0x10000000
7586 #define MC_PMG_CMD_MRS1__ADR_MSB1__SHIFT 0x1c
7587 #define MC_PMG_CMD_MRS1__ADR_MSB0_MASK 0x20000000
7588 #define MC_PMG_CMD_MRS1__ADR_MSB0__SHIFT 0x1d
7589 #define MC_PMG_CMD_MRS2__ADR_MASK 0xffff
7590 #define MC_PMG_CMD_MRS2__ADR__SHIFT 0x0
7591 #define MC_PMG_CMD_MRS2__MOP_MASK 0x70000
7592 #define MC_PMG_CMD_MRS2__MOP__SHIFT 0x10
7593 #define MC_PMG_CMD_MRS2__BNK_MSB_MASK 0x80000
7594 #define MC_PMG_CMD_MRS2__BNK_MSB__SHIFT 0x13
7595 #define MC_PMG_CMD_MRS2__END_MASK 0x100000
7596 #define MC_PMG_CMD_MRS2__END__SHIFT 0x14
7597 #define MC_PMG_CMD_MRS2__CSB_MASK 0x600000
7598 #define MC_PMG_CMD_MRS2__CSB__SHIFT 0x15
7599 #define MC_PMG_CMD_MRS2__ADR_MSB1_MASK 0x10000000
7600 #define MC_PMG_CMD_MRS2__ADR_MSB1__SHIFT 0x1c
7601 #define MC_PMG_CMD_MRS2__ADR_MSB0_MASK 0x20000000
7602 #define MC_PMG_CMD_MRS2__ADR_MSB0__SHIFT 0x1d
7603 #define MC_PMG_CFG__SYC_CLK_MASK 0x1
7604 #define MC_PMG_CFG__SYC_CLK__SHIFT 0x0
7605 #define MC_PMG_CFG__RST_MRS_MASK 0x2
7606 #define MC_PMG_CFG__RST_MRS__SHIFT 0x1
7607 #define MC_PMG_CFG__RST_EMRS_MASK 0x4
7608 #define MC_PMG_CFG__RST_EMRS__SHIFT 0x2
7609 #define MC_PMG_CFG__TRI_MIO_MASK 0x8
7610 #define MC_PMG_CFG__TRI_MIO__SHIFT 0x3
7611 #define MC_PMG_CFG__XSR_TMR_MASK 0xf0
7612 #define MC_PMG_CFG__XSR_TMR__SHIFT 0x4
7613 #define MC_PMG_CFG__RST_MRS1_MASK 0x100
7614 #define MC_PMG_CFG__RST_MRS1__SHIFT 0x8
7615 #define MC_PMG_CFG__RST_MRS2_MASK 0x200
7616 #define MC_PMG_CFG__RST_MRS2__SHIFT 0x9
7617 #define MC_PMG_CFG__DPM_WAKE_MASK 0x400
7618 #define MC_PMG_CFG__DPM_WAKE__SHIFT 0xa
7619 #define MC_PMG_CFG__RFS_SRX_MASK 0x1000
7620 #define MC_PMG_CFG__RFS_SRX__SHIFT 0xc
7621 #define MC_PMG_CFG__PREA_SRX_MASK 0x2000
7622 #define MC_PMG_CFG__PREA_SRX__SHIFT 0xd
7623 #define MC_PMG_CFG__MRS_WAIT_CNT_MASK 0xf0000
7624 #define MC_PMG_CFG__MRS_WAIT_CNT__SHIFT 0x10
7625 #define MC_PMG_CFG__WRITE_DURING_DLOCK_MASK 0x100000
7626 #define MC_PMG_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
7627 #define MC_PMG_CFG__YCLK_ON_MASK 0x200000
7628 #define MC_PMG_CFG__YCLK_ON__SHIFT 0x15
7629 #define MC_PMG_CFG__EARLY_ACK_ACPI_MASK 0x400000
7630 #define MC_PMG_CFG__EARLY_ACK_ACPI__SHIFT 0x16
7631 #define MC_PMG_CFG__RXPDNB_MASK 0x2000000
7632 #define MC_PMG_CFG__RXPDNB__SHIFT 0x19
7633 #define MC_PMG_CFG__ZQCL_SEND_MASK 0xc000000
7634 #define MC_PMG_CFG__ZQCL_SEND__SHIFT 0x1a
7635 #define MC_PMG_AUTO_CMD__ADR_MASK 0x1ffff
7636 #define MC_PMG_AUTO_CMD__ADR__SHIFT 0x0
7637 #define MC_PMG_AUTO_CMD__ADR_MSB1_MASK 0x10000000
7638 #define MC_PMG_AUTO_CMD__ADR_MSB1__SHIFT 0x1c
7639 #define MC_PMG_AUTO_CMD__ADR_MSB0_MASK 0x20000000
7640 #define MC_PMG_AUTO_CMD__ADR_MSB0__SHIFT 0x1d
7641 #define MC_PMG_AUTO_CFG__SYC_CLK_MASK 0x1
7642 #define MC_PMG_AUTO_CFG__SYC_CLK__SHIFT 0x0
7643 #define MC_PMG_AUTO_CFG__RST_MRS_MASK 0x2
7644 #define MC_PMG_AUTO_CFG__RST_MRS__SHIFT 0x1
7645 #define MC_PMG_AUTO_CFG__TRI_MIO_MASK 0x4
7646 #define MC_PMG_AUTO_CFG__TRI_MIO__SHIFT 0x2
7647 #define MC_PMG_AUTO_CFG__XSR_TMR_MASK 0xf0
7648 #define MC_PMG_AUTO_CFG__XSR_TMR__SHIFT 0x4
7649 #define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF_MASK 0x100
7650 #define MC_PMG_AUTO_CFG__SS_ALWAYS_SLF__SHIFT 0x8
7651 #define MC_PMG_AUTO_CFG__SS_S_SLF_MASK 0x200
7652 #define MC_PMG_AUTO_CFG__SS_S_SLF__SHIFT 0x9
7653 #define MC_PMG_AUTO_CFG__SCDS_MODE_MASK 0x400
7654 #define MC_PMG_AUTO_CFG__SCDS_MODE__SHIFT 0xa
7655 #define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP_MASK 0x800
7656 #define MC_PMG_AUTO_CFG__EXIT_ALLOW_STOP__SHIFT 0xb
7657 #define MC_PMG_AUTO_CFG__RFS_SRX_MASK 0x1000
7658 #define MC_PMG_AUTO_CFG__RFS_SRX__SHIFT 0xc
7659 #define MC_PMG_AUTO_CFG__PREA_SRX_MASK 0x2000
7660 #define MC_PMG_AUTO_CFG__PREA_SRX__SHIFT 0xd
7661 #define MC_PMG_AUTO_CFG__STUTTER_EN_MASK 0x4000
7662 #define MC_PMG_AUTO_CFG__STUTTER_EN__SHIFT 0xe
7663 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0_MASK 0x8000
7664 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_0__SHIFT 0xf
7665 #define MC_PMG_AUTO_CFG__MRS_WAIT_CNT_MASK 0xf0000
7666 #define MC_PMG_AUTO_CFG__MRS_WAIT_CNT__SHIFT 0x10
7667 #define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK_MASK 0x100000
7668 #define MC_PMG_AUTO_CFG__WRITE_DURING_DLOCK__SHIFT 0x14
7669 #define MC_PMG_AUTO_CFG__YCLK_ON_MASK 0x200000
7670 #define MC_PMG_AUTO_CFG__YCLK_ON__SHIFT 0x15
7671 #define MC_PMG_AUTO_CFG__RXPDNB_MASK 0x400000
7672 #define MC_PMG_AUTO_CFG__RXPDNB__SHIFT 0x16
7673 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1_MASK 0x800000
7674 #define MC_PMG_AUTO_CFG__SELFREFR_COMMIT_1__SHIFT 0x17
7675 #define MC_PMG_AUTO_CFG__DLL_CNT_MASK 0xff000000
7676 #define MC_PMG_AUTO_CFG__DLL_CNT__SHIFT 0x18
7677 #define MC_IMP_CNTL__MEM_IO_UPDATE_RATE_MASK 0x1f
7678 #define MC_IMP_CNTL__MEM_IO_UPDATE_RATE__SHIFT 0x0
7679 #define MC_IMP_CNTL__CAL_VREF_SEL_MASK 0x20
7680 #define MC_IMP_CNTL__CAL_VREF_SEL__SHIFT 0x5
7681 #define MC_IMP_CNTL__CAL_VREFMODE_MASK 0x40
7682 #define MC_IMP_CNTL__CAL_VREFMODE__SHIFT 0x6
7683 #define MC_IMP_CNTL__TIMEOUT_ERR_MASK 0x100
7684 #define MC_IMP_CNTL__TIMEOUT_ERR__SHIFT 0x8
7685 #define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR_MASK 0x200
7686 #define MC_IMP_CNTL__CLEAR_TIMEOUT_ERR__SHIFT 0x9
7687 #define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT_MASK 0xe000
7688 #define MC_IMP_CNTL__MEM_IO_SAMPLE_CNT__SHIFT 0xd
7689 #define MC_IMP_CNTL__CAL_VREF_MASK 0x7f0000
7690 #define MC_IMP_CNTL__CAL_VREF__SHIFT 0x10
7691 #define MC_IMP_CNTL__CAL_WHEN_IDLE_MASK 0x20000000
7692 #define MC_IMP_CNTL__CAL_WHEN_IDLE__SHIFT 0x1d
7693 #define MC_IMP_CNTL__CAL_WHEN_REFRESH_MASK 0x40000000
7694 #define MC_IMP_CNTL__CAL_WHEN_REFRESH__SHIFT 0x1e
7695 #define MC_IMP_CNTL__CAL_PWRON_MASK 0x80000000
7696 #define MC_IMP_CNTL__CAL_PWRON__SHIFT 0x1f
7697 #define MC_IMP_DEBUG__TSTARTUP_CNTR_MASK 0xff
7698 #define MC_IMP_DEBUG__TSTARTUP_CNTR__SHIFT 0x0
7699 #define MC_IMP_DEBUG__TIMEOUT_CNTR_MASK 0xff00
7700 #define MC_IMP_DEBUG__TIMEOUT_CNTR__SHIFT 0x8
7701 #define MC_IMP_DEBUG__PMVCAL_RESERVED_MASK 0xfff0000
7702 #define MC_IMP_DEBUG__PMVCAL_RESERVED__SHIFT 0x10
7703 #define MC_IMP_DEBUG__DEBUG_CAL_EN_MASK 0x10000000
7704 #define MC_IMP_DEBUG__DEBUG_CAL_EN__SHIFT 0x1c
7705 #define MC_IMP_DEBUG__DEBUG_CAL_START_MASK 0x20000000
7706 #define MC_IMP_DEBUG__DEBUG_CAL_START__SHIFT 0x1d
7707 #define MC_IMP_DEBUG__DEBUG_CAL_INTR_MASK 0x40000000
7708 #define MC_IMP_DEBUG__DEBUG_CAL_INTR__SHIFT 0x1e
7709 #define MC_IMP_DEBUG__DEBUG_CAL_DONE_MASK 0x80000000
7710 #define MC_IMP_DEBUG__DEBUG_CAL_DONE__SHIFT 0x1f
7711 #define MC_IMP_STATUS__PSTR_CAL_MASK 0xff
7712 #define MC_IMP_STATUS__PSTR_CAL__SHIFT 0x0
7713 #define MC_IMP_STATUS__PSTR_ACCUM_VAL_MASK 0xff00
7714 #define MC_IMP_STATUS__PSTR_ACCUM_VAL__SHIFT 0x8
7715 #define MC_IMP_STATUS__NSTR_CAL_MASK 0xff0000
7716 #define MC_IMP_STATUS__NSTR_CAL__SHIFT 0x10
7717 #define MC_IMP_STATUS__NSTR_ACCUM_VAL_MASK 0xff000000
7718 #define MC_IMP_STATUS__NSTR_ACCUM_VAL__SHIFT 0x18
7719 #define MC_IMP_DQ_STATUS__CH0_DQ_PSTR_MASK 0xff
7720 #define MC_IMP_DQ_STATUS__CH0_DQ_PSTR__SHIFT 0x0
7721 #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR_MASK 0xff00
7722 #define MC_IMP_DQ_STATUS__CH0_DQ_NSTR__SHIFT 0x8
7723 #define MC_IMP_DQ_STATUS__CH1_DQ_PSTR_MASK 0xff0000
7724 #define MC_IMP_DQ_STATUS__CH1_DQ_PSTR__SHIFT 0x10
7725 #define MC_IMP_DQ_STATUS__CH1_DQ_NSTR_MASK 0xff000000
7726 #define MC_IMP_DQ_STATUS__CH1_DQ_NSTR__SHIFT 0x18
7727 #define MC_SEQ_WCDR_CTRL__WCDR_PRE_MASK 0xff
7728 #define MC_SEQ_WCDR_CTRL__WCDR_PRE__SHIFT 0x0
7729 #define MC_SEQ_WCDR_CTRL__WCDR_TIM_MASK 0xf00
7730 #define MC_SEQ_WCDR_CTRL__WCDR_TIM__SHIFT 0x8
7731 #define MC_SEQ_WCDR_CTRL__WR_EN_MASK 0x1000
7732 #define MC_SEQ_WCDR_CTRL__WR_EN__SHIFT 0xc
7733 #define MC_SEQ_WCDR_CTRL__RD_EN_MASK 0x2000
7734 #define MC_SEQ_WCDR_CTRL__RD_EN__SHIFT 0xd
7735 #define MC_SEQ_WCDR_CTRL__AREF_EN_MASK 0x4000
7736 #define MC_SEQ_WCDR_CTRL__AREF_EN__SHIFT 0xe
7737 #define MC_SEQ_WCDR_CTRL__TRAIN_EN_MASK 0x8000
7738 #define MC_SEQ_WCDR_CTRL__TRAIN_EN__SHIFT 0xf
7739 #define MC_SEQ_WCDR_CTRL__TWCDRL_MASK 0xf0000
7740 #define MC_SEQ_WCDR_CTRL__TWCDRL__SHIFT 0x10
7741 #define MC_SEQ_WCDR_CTRL__PRBS_EN_MASK 0x100000
7742 #define MC_SEQ_WCDR_CTRL__PRBS_EN__SHIFT 0x14
7743 #define MC_SEQ_WCDR_CTRL__PRBS_RST_MASK 0x200000
7744 #define MC_SEQ_WCDR_CTRL__PRBS_RST__SHIFT 0x15
7745 #define MC_SEQ_WCDR_CTRL__PREAMBLE_MASK 0xf000000
7746 #define MC_SEQ_WCDR_CTRL__PREAMBLE__SHIFT 0x18
7747 #define MC_SEQ_WCDR_CTRL__PRE_MASK_MASK 0xf0000000
7748 #define MC_SEQ_WCDR_CTRL__PRE_MASK__SHIFT 0x1c
7749 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN_MASK 0x1
7750 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_ADDR_TRAIN__SHIFT 0x0
7751 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN_MASK 0x2
7752 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WCK_TRAIN__SHIFT 0x1
7753 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN_MASK 0x4
7754 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_READ_TRAIN__SHIFT 0x2
7755 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN_MASK 0x8
7756 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BOOT_UP_WRITE_TRAIN__SHIFT 0x3
7757 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN_MASK 0x10
7758 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_ADDR_TRAIN__SHIFT 0x4
7759 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN_MASK 0x20
7760 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WCK_TRAIN__SHIFT 0x5
7761 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN_MASK 0x40
7762 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_READ_TRAIN__SHIFT 0x6
7763 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN_MASK 0x80
7764 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SELF_REFRESH_WRITE_TRAIN__SHIFT 0x7
7765 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN_MASK 0x100
7766 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_ADDR_TRAIN__SHIFT 0x8
7767 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN_MASK 0x200
7768 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WCK_TRAIN__SHIFT 0x9
7769 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN_MASK 0x400
7770 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_READ_TRAIN__SHIFT 0xa
7771 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN_MASK 0x800
7772 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WRITE_TRAIN__SHIFT 0xb
7773 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN_MASK 0x1000
7774 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_ADDR_TRAIN__SHIFT 0xc
7775 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN_MASK 0x2000
7776 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WCK_TRAIN__SHIFT 0xd
7777 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN_MASK 0x4000
7778 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_READ_TRAIN__SHIFT 0xe
7779 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN_MASK 0x8000
7780 #define MC_SEQ_TRAIN_WAKEUP_CNTL__WRITE_ECC_WRITE_TRAIN__SHIFT 0xf
7781 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN_MASK 0x10000
7782 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_ADDR_TRAIN__SHIFT 0x10
7783 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN_MASK 0x20000
7784 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WCK_TRAIN__SHIFT 0x11
7785 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN_MASK 0x40000
7786 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_READ_TRAIN__SHIFT 0x12
7787 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN_MASK 0x80000
7788 #define MC_SEQ_TRAIN_WAKEUP_CNTL__READ_ECC_WRITE_TRAIN__SHIFT 0x13
7789 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY_MASK 0x100000
7790 #define MC_SEQ_TRAIN_WAKEUP_CNTL__AUTO_REFRESH_WAKEUP_EARLY__SHIFT 0x14
7791 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0_MASK 0x200000
7792 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D0__SHIFT 0x15
7793 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1_MASK 0x400000
7794 #define MC_SEQ_TRAIN_WAKEUP_CNTL__STOP_WCK_D1__SHIFT 0x16
7795 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0_MASK 0x1000000
7796 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D0__SHIFT 0x18
7797 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0_MASK 0x2000000
7798 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D0__SHIFT 0x19
7799 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1_MASK 0x4000000
7800 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_RD_D1__SHIFT 0x1a
7801 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1_MASK 0x8000000
7802 #define MC_SEQ_TRAIN_WAKEUP_CNTL__BLOCK_ARB_WR_D1__SHIFT 0x1b
7803 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP_MASK 0x10000000
7804 #define MC_SEQ_TRAIN_WAKEUP_CNTL__SW_WAKEUP__SHIFT 0x1c
7805 #define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP_MASK 0x20000000
7806 #define MC_SEQ_TRAIN_WAKEUP_CNTL__DISP_ASTOP_WAKEUP__SHIFT 0x1d
7807 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK 0x40000000
7808 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0__SHIFT 0x1e
7809 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK 0x80000000
7810 #define MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1__SHIFT 0x1f
7811 #define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD_MASK 0xffff
7812 #define MC_SEQ_TRAIN_EDC_THRESHOLD__WRITE_EDC_THRESHOLD__SHIFT 0x0
7813 #define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD_MASK 0xffff0000
7814 #define MC_SEQ_TRAIN_EDC_THRESHOLD__READ_EDC_THRESHOLD__SHIFT 0x10
7815 #define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD_MASK 0xffffffff
7816 #define MC_SEQ_TRAIN_EDC_THRESHOLD2__THRESHOLD_PERIOD__SHIFT 0x0
7817 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS_MASK 0x1
7818 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_STATUS__SHIFT 0x0
7819 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS_MASK 0x2
7820 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_STATUS__SHIFT 0x1
7821 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS_MASK 0x4
7822 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CLEAR_RETRAIN_STATUS__SHIFT 0x2
7823 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI_MASK 0x8
7824 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_VBI__SHIFT 0x3
7825 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR_MASK 0x30
7826 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__RETRAIN_MONITOR__SHIFT 0x4
7827 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS_MASK 0x100
7828 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH0_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x8
7829 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS_MASK 0x200
7830 #define MC_SEQ_TRAIN_EDC_THRESHOLD3__CH1_LINK_RETRAIN_IN_PROGRESS__SHIFT 0x9
7831 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP_MASK 0x1
7832 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_ARF_WAKEUP__SHIFT 0x0
7833 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP_MASK 0x2
7834 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_ARF_WAKEUP__SHIFT 0x1
7835 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP_MASK 0x4
7836 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_REDC_WAKEUP__SHIFT 0x2
7837 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP_MASK 0x8
7838 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_REDC_WAKEUP__SHIFT 0x3
7839 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP_MASK 0x10
7840 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_WEDC_WAKEUP__SHIFT 0x4
7841 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP_MASK 0x20
7842 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_WEDC_WAKEUP__SHIFT 0x5
7843 #define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
7844 #define MC_SEQ_TRAIN_WAKEUP_EDGE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
7845 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
7846 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
7847 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
7848 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
7849 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
7850 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
7851 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
7852 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
7853 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
7854 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
7855 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
7856 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
7857 #define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP_MASK 0x2000
7858 #define MC_SEQ_TRAIN_WAKEUP_EDGE__RESERVE0_WAKEUP__SHIFT 0xd
7859 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP_MASK 0x4000
7860 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TSM_DONE_WAKEUP__SHIFT 0xe
7861 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP_MASK 0x8000
7862 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TIMER_DONE_WAKEUP__SHIFT 0xf
7863 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP_MASK 0x20000
7864 #define MC_SEQ_TRAIN_WAKEUP_EDGE__TCG_DONE_WAKEUP__SHIFT 0x11
7865 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP_MASK 0x40000
7866 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7867 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP_MASK 0x80000
7868 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7869 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP_MASK 0x100000
7870 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_WAKEUP__SHIFT 0x14
7871 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7872 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7873 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7874 #define MC_SEQ_TRAIN_WAKEUP_EDGE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7875 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP_MASK 0x800000
7876 #define MC_SEQ_TRAIN_WAKEUP_EDGE__DPM_LPT_WAKEUP__SHIFT 0x17
7877 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP_MASK 0x1000000
7878 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D0_IDLEH_WAKEUP__SHIFT 0x18
7879 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP_MASK 0x2000000
7880 #define MC_SEQ_TRAIN_WAKEUP_EDGE__D1_IDLEH_WAKEUP__SHIFT 0x19
7881 #define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP_MASK 0x4000000
7882 #define MC_SEQ_TRAIN_WAKEUP_EDGE__PHY_PG_WAKEUP__SHIFT 0x1a
7883 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP_MASK 0x8000000
7884 #define MC_SEQ_TRAIN_WAKEUP_EDGE__SREG_WAKEUP__SHIFT 0x1b
7885 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP_MASK 0x1
7886 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_ARF_WAKEUP__SHIFT 0x0
7887 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP_MASK 0x2
7888 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_ARF_WAKEUP__SHIFT 0x1
7889 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP_MASK 0x4
7890 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_REDC_WAKEUP__SHIFT 0x2
7891 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP_MASK 0x8
7892 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_REDC_WAKEUP__SHIFT 0x3
7893 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP_MASK 0x10
7894 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_WEDC_WAKEUP__SHIFT 0x4
7895 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP_MASK 0x20
7896 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_WEDC_WAKEUP__SHIFT 0x5
7897 #define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
7898 #define MC_SEQ_TRAIN_WAKEUP_MASK__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
7899 #define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP_MASK 0x80
7900 #define MC_SEQ_TRAIN_WAKEUP_MASK__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
7901 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
7902 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
7903 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
7904 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
7905 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
7906 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
7907 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
7908 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
7909 #define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
7910 #define MC_SEQ_TRAIN_WAKEUP_MASK__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
7911 #define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP_MASK 0x2000
7912 #define MC_SEQ_TRAIN_WAKEUP_MASK__RESERVE0_WAKEUP__SHIFT 0xd
7913 #define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP_MASK 0x4000
7914 #define MC_SEQ_TRAIN_WAKEUP_MASK__TSM_DONE_WAKEUP__SHIFT 0xe
7915 #define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP_MASK 0x8000
7916 #define MC_SEQ_TRAIN_WAKEUP_MASK__TIMER_DONE_WAKEUP__SHIFT 0xf
7917 #define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP_MASK 0x20000
7918 #define MC_SEQ_TRAIN_WAKEUP_MASK__TCG_DONE_WAKEUP__SHIFT 0x11
7919 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP_MASK 0x40000
7920 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7921 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP_MASK 0x80000
7922 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7923 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP_MASK 0x100000
7924 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_WAKEUP__SHIFT 0x14
7925 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7926 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7927 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7928 #define MC_SEQ_TRAIN_WAKEUP_MASK__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7929 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP_MASK 0x800000
7930 #define MC_SEQ_TRAIN_WAKEUP_MASK__DPM_LPT_WAKEUP__SHIFT 0x17
7931 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP_MASK 0x1000000
7932 #define MC_SEQ_TRAIN_WAKEUP_MASK__D0_IDLEH_WAKEUP__SHIFT 0x18
7933 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP_MASK 0x2000000
7934 #define MC_SEQ_TRAIN_WAKEUP_MASK__D1_IDLEH_WAKEUP__SHIFT 0x19
7935 #define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP_MASK 0x4000000
7936 #define MC_SEQ_TRAIN_WAKEUP_MASK__PHY_PG_WAKEUP__SHIFT 0x1a
7937 #define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP_MASK 0x8000000
7938 #define MC_SEQ_TRAIN_WAKEUP_MASK__SREG_WAKEUP__SHIFT 0x1b
7939 #define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP_MASK 0x1
7940 #define MC_SEQ_TRAIN_CAPTURE__D0_ARF_WAKEUP__SHIFT 0x0
7941 #define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP_MASK 0x2
7942 #define MC_SEQ_TRAIN_CAPTURE__D1_ARF_WAKEUP__SHIFT 0x1
7943 #define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP_MASK 0x4
7944 #define MC_SEQ_TRAIN_CAPTURE__D0_REDC_WAKEUP__SHIFT 0x2
7945 #define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP_MASK 0x8
7946 #define MC_SEQ_TRAIN_CAPTURE__D1_REDC_WAKEUP__SHIFT 0x3
7947 #define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP_MASK 0x10
7948 #define MC_SEQ_TRAIN_CAPTURE__D0_WEDC_WAKEUP__SHIFT 0x4
7949 #define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP_MASK 0x20
7950 #define MC_SEQ_TRAIN_CAPTURE__D1_WEDC_WAKEUP__SHIFT 0x5
7951 #define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
7952 #define MC_SEQ_TRAIN_CAPTURE__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
7953 #define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP_MASK 0x80
7954 #define MC_SEQ_TRAIN_CAPTURE__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
7955 #define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
7956 #define MC_SEQ_TRAIN_CAPTURE__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
7957 #define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
7958 #define MC_SEQ_TRAIN_CAPTURE__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
7959 #define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
7960 #define MC_SEQ_TRAIN_CAPTURE__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
7961 #define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
7962 #define MC_SEQ_TRAIN_CAPTURE__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
7963 #define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
7964 #define MC_SEQ_TRAIN_CAPTURE__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
7965 #define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP_MASK 0x2000
7966 #define MC_SEQ_TRAIN_CAPTURE__RESERVE0_WAKEUP__SHIFT 0xd
7967 #define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP_MASK 0x4000
7968 #define MC_SEQ_TRAIN_CAPTURE__TSM_DONE_WAKEUP__SHIFT 0xe
7969 #define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP_MASK 0x8000
7970 #define MC_SEQ_TRAIN_CAPTURE__TIMER_DONE_WAKEUP__SHIFT 0xf
7971 #define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP_MASK 0x20000
7972 #define MC_SEQ_TRAIN_CAPTURE__TCG_DONE_WAKEUP__SHIFT 0x11
7973 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP_MASK 0x40000
7974 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP0_WAKEUP__SHIFT 0x12
7975 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP_MASK 0x80000
7976 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOP1_WAKEUP__SHIFT 0x13
7977 #define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP_MASK 0x100000
7978 #define MC_SEQ_TRAIN_CAPTURE__DPM_WAKEUP__SHIFT 0x14
7979 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP_MASK 0x200000
7980 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
7981 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP_MASK 0x400000
7982 #define MC_SEQ_TRAIN_CAPTURE__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
7983 #define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP_MASK 0x800000
7984 #define MC_SEQ_TRAIN_CAPTURE__DPM_LPT_WAKEUP__SHIFT 0x17
7985 #define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP_MASK 0x1000000
7986 #define MC_SEQ_TRAIN_CAPTURE__D0_IDLEH_WAKEUP__SHIFT 0x18
7987 #define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP_MASK 0x2000000
7988 #define MC_SEQ_TRAIN_CAPTURE__D1_IDLEH_WAKEUP__SHIFT 0x19
7989 #define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP_MASK 0x4000000
7990 #define MC_SEQ_TRAIN_CAPTURE__PHY_PG_WAKEUP__SHIFT 0x1a
7991 #define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP_MASK 0x8000000
7992 #define MC_SEQ_TRAIN_CAPTURE__SREG_WAKEUP__SHIFT 0x1b
7993 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP_MASK 0x1
7994 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_ARF_WAKEUP__SHIFT 0x0
7995 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP_MASK 0x2
7996 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_ARF_WAKEUP__SHIFT 0x1
7997 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP_MASK 0x4
7998 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_REDC_WAKEUP__SHIFT 0x2
7999 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP_MASK 0x8
8000 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_REDC_WAKEUP__SHIFT 0x3
8001 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP_MASK 0x10
8002 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_WEDC_WAKEUP__SHIFT 0x4
8003 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP_MASK 0x20
8004 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_WEDC_WAKEUP__SHIFT 0x5
8005 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP_MASK 0x40
8006 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__MCLK_FREQ_CHANGE_WAKEUP__SHIFT 0x6
8007 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP_MASK 0x80
8008 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SCLK_SRBM_READY_WAKEUP__SHIFT 0x7
8009 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP_MASK 0x100
8010 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_CMD_FIFO_READY_WAKEUP__SHIFT 0x8
8011 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP_MASK 0x200
8012 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_CMD_FIFO_READY_WAKEUP__SHIFT 0x9
8013 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP_MASK 0x400
8014 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_DATA_FIFO_READY_WAKEUP__SHIFT 0xa
8015 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP_MASK 0x800
8016 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_DATA_FIFO_READY_WAKEUP__SHIFT 0xb
8017 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP_MASK 0x1000
8018 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SOFTWARE_WAKEUP_WAKEUP__SHIFT 0xc
8019 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP_MASK 0x2000
8020 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__RESERVE0_WAKEUP__SHIFT 0xd
8021 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP_MASK 0x4000
8022 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TSM_DONE_WAKEUP__SHIFT 0xe
8023 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP_MASK 0x8000
8024 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TIMER_DONE_WAKEUP__SHIFT 0xf
8025 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL_MASK 0x10000
8026 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__CLEARALL__SHIFT 0x10
8027 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP_MASK 0x20000
8028 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__TCG_DONE_WAKEUP__SHIFT 0x11
8029 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP_MASK 0x40000
8030 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP0_WAKEUP__SHIFT 0x12
8031 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP_MASK 0x80000
8032 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOP1_WAKEUP__SHIFT 0x13
8033 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP_MASK 0x100000
8034 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_WAKEUP__SHIFT 0x14
8035 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP_MASK 0x200000
8036 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB0_WAKEUP__SHIFT 0x15
8037 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP_MASK 0x400000
8038 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__ALLOWSTOPB1_WAKEUP__SHIFT 0x16
8039 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP_MASK 0x800000
8040 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__DPM_LPT_WAKEUP__SHIFT 0x17
8041 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP_MASK 0x1000000
8042 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D0_IDLEH_WAKEUP__SHIFT 0x18
8043 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP_MASK 0x2000000
8044 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__D1_IDLEH_WAKEUP__SHIFT 0x19
8045 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP_MASK 0x4000000
8046 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__PHY_PG_WAKEUP__SHIFT 0x1a
8047 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP_MASK 0x8000000
8048 #define MC_SEQ_TRAIN_WAKEUP_CLEAR__SREG_WAKEUP__SHIFT 0x1b
8049 #define MC_SEQ_TRAIN_TIMING__TWT2RT_MASK 0x1f
8050 #define MC_SEQ_TRAIN_TIMING__TWT2RT__SHIFT 0x0
8051 #define MC_SEQ_TRAIN_TIMING__TARF2T_MASK 0x3e0
8052 #define MC_SEQ_TRAIN_TIMING__TARF2T__SHIFT 0x5
8053 #define MC_SEQ_TRAIN_TIMING__TT2ROW_MASK 0x7c00
8054 #define MC_SEQ_TRAIN_TIMING__TT2ROW__SHIFT 0xa
8055 #define MC_SEQ_TRAIN_TIMING__TLD2LD_MASK 0xf8000
8056 #define MC_SEQ_TRAIN_TIMING__TLD2LD__SHIFT 0xf
8057 #define MC_TRAIN_EDCCDR_R_D0__EDC0_MASK 0xff
8058 #define MC_TRAIN_EDCCDR_R_D0__EDC0__SHIFT 0x0
8059 #define MC_TRAIN_EDCCDR_R_D0__EDC1_MASK 0xff00
8060 #define MC_TRAIN_EDCCDR_R_D0__EDC1__SHIFT 0x8
8061 #define MC_TRAIN_EDCCDR_R_D0__EDC2_MASK 0xff0000
8062 #define MC_TRAIN_EDCCDR_R_D0__EDC2__SHIFT 0x10
8063 #define MC_TRAIN_EDCCDR_R_D0__EDC3_MASK 0xff000000
8064 #define MC_TRAIN_EDCCDR_R_D0__EDC3__SHIFT 0x18
8065 #define MC_TRAIN_EDCCDR_R_D1__EDC0_MASK 0xff
8066 #define MC_TRAIN_EDCCDR_R_D1__EDC0__SHIFT 0x0
8067 #define MC_TRAIN_EDCCDR_R_D1__EDC1_MASK 0xff00
8068 #define MC_TRAIN_EDCCDR_R_D1__EDC1__SHIFT 0x8
8069 #define MC_TRAIN_EDCCDR_R_D1__EDC2_MASK 0xff0000
8070 #define MC_TRAIN_EDCCDR_R_D1__EDC2__SHIFT 0x10
8071 #define MC_TRAIN_EDCCDR_R_D1__EDC3_MASK 0xff000000
8072 #define MC_TRAIN_EDCCDR_R_D1__EDC3__SHIFT 0x18
8073 #define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS_MASK 0xffffffff
8074 #define MC_TRAIN_PRBSERR_0_D0__DQ_STATUS__SHIFT 0x0
8075 #define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS_MASK 0xf
8076 #define MC_TRAIN_PRBSERR_1_D0__DBI_STATUS__SHIFT 0x0
8077 #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS_MASK 0xf0
8078 #define MC_TRAIN_PRBSERR_1_D0__EDC_STATUS__SHIFT 0x4
8079 #define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS_MASK 0xf00
8080 #define MC_TRAIN_PRBSERR_1_D0__WCK_STATUS__SHIFT 0x8
8081 #define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS_MASK 0xf000
8082 #define MC_TRAIN_PRBSERR_1_D0__WCDR_STATUS__SHIFT 0xc
8083 #define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR_MASK 0x10000000
8084 #define MC_TRAIN_PRBSERR_1_D0__PMA_PRBSCLR__SHIFT 0x1c
8085 #define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR_MASK 0x20000000
8086 #define MC_TRAIN_PRBSERR_1_D0__PMD0_PRBSCLR__SHIFT 0x1d
8087 #define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR_MASK 0x40000000
8088 #define MC_TRAIN_PRBSERR_1_D0__PMD1_PRBSCLR__SHIFT 0x1e
8089 #define MC_TRAIN_PRBSERR_2_D0__CK_STATUS_MASK 0x1
8090 #define MC_TRAIN_PRBSERR_2_D0__CK_STATUS__SHIFT 0x0
8091 #define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS_MASK 0x2
8092 #define MC_TRAIN_PRBSERR_2_D0__CKB_STATUS__SHIFT 0x1
8093 #define MC_TRAIN_PRBSERR_2_D0__CS_STATUS_MASK 0x30
8094 #define MC_TRAIN_PRBSERR_2_D0__CS_STATUS__SHIFT 0x4
8095 #define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS_MASK 0x100
8096 #define MC_TRAIN_PRBSERR_2_D0__CKE_STATUS__SHIFT 0x8
8097 #define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS_MASK 0x200
8098 #define MC_TRAIN_PRBSERR_2_D0__RAS_STATUS__SHIFT 0x9
8099 #define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS_MASK 0x400
8100 #define MC_TRAIN_PRBSERR_2_D0__CAS_STATUS__SHIFT 0xa
8101 #define MC_TRAIN_PRBSERR_2_D0__WE_STATUS_MASK 0x800
8102 #define MC_TRAIN_PRBSERR_2_D0__WE_STATUS__SHIFT 0xb
8103 #define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS_MASK 0x3ff0000
8104 #define MC_TRAIN_PRBSERR_2_D0__ADDR_STATUS__SHIFT 0x10
8105 #define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS_MASK 0x10000000
8106 #define MC_TRAIN_PRBSERR_2_D0__ABI_STATUS__SHIFT 0x1c
8107 #define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT_MASK 0xffff
8108 #define MC_TRAIN_EDC_STATUS_D0__WEDC_CNT__SHIFT 0x0
8109 #define MC_TRAIN_EDC_STATUS_D0__REDC_CNT_MASK 0xffff0000
8110 #define MC_TRAIN_EDC_STATUS_D0__REDC_CNT__SHIFT 0x10
8111 #define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS_MASK 0xffffffff
8112 #define MC_TRAIN_PRBSERR_0_D1__DQ_STATUS__SHIFT 0x0
8113 #define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS_MASK 0xf
8114 #define MC_TRAIN_PRBSERR_1_D1__DBI_STATUS__SHIFT 0x0
8115 #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS_MASK 0xf0
8116 #define MC_TRAIN_PRBSERR_1_D1__EDC_STATUS__SHIFT 0x4
8117 #define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS_MASK 0xf00
8118 #define MC_TRAIN_PRBSERR_1_D1__WCK_STATUS__SHIFT 0x8
8119 #define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS_MASK 0xf000
8120 #define MC_TRAIN_PRBSERR_1_D1__WCDR_STATUS__SHIFT 0xc
8121 #define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR_MASK 0x10000000
8122 #define MC_TRAIN_PRBSERR_1_D1__PMA_PRBSCLR__SHIFT 0x1c
8123 #define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR_MASK 0x20000000
8124 #define MC_TRAIN_PRBSERR_1_D1__PMD0_PRBSCLR__SHIFT 0x1d
8125 #define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR_MASK 0x40000000
8126 #define MC_TRAIN_PRBSERR_1_D1__PMD1_PRBSCLR__SHIFT 0x1e
8127 #define MC_TRAIN_PRBSERR_2_D1__CK_STATUS_MASK 0x1
8128 #define MC_TRAIN_PRBSERR_2_D1__CK_STATUS__SHIFT 0x0
8129 #define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS_MASK 0x2
8130 #define MC_TRAIN_PRBSERR_2_D1__CKB_STATUS__SHIFT 0x1
8131 #define MC_TRAIN_PRBSERR_2_D1__CS_STATUS_MASK 0x30
8132 #define MC_TRAIN_PRBSERR_2_D1__CS_STATUS__SHIFT 0x4
8133 #define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS_MASK 0x100
8134 #define MC_TRAIN_PRBSERR_2_D1__CKE_STATUS__SHIFT 0x8
8135 #define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS_MASK 0x200
8136 #define MC_TRAIN_PRBSERR_2_D1__RAS_STATUS__SHIFT 0x9
8137 #define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS_MASK 0x400
8138 #define MC_TRAIN_PRBSERR_2_D1__CAS_STATUS__SHIFT 0xa
8139 #define MC_TRAIN_PRBSERR_2_D1__WE_STATUS_MASK 0x800
8140 #define MC_TRAIN_PRBSERR_2_D1__WE_STATUS__SHIFT 0xb
8141 #define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS_MASK 0x3ff0000
8142 #define MC_TRAIN_PRBSERR_2_D1__ADDR_STATUS__SHIFT 0x10
8143 #define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS_MASK 0x10000000
8144 #define MC_TRAIN_PRBSERR_2_D1__ABI_STATUS__SHIFT 0x1c
8145 #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT_MASK 0xffff
8146 #define MC_TRAIN_EDC_STATUS_D1__WEDC_CNT__SHIFT 0x0
8147 #define MC_TRAIN_EDC_STATUS_D1__REDC_CNT_MASK 0xffff0000
8148 #define MC_TRAIN_EDC_STATUS_D1__REDC_CNT__SHIFT 0x10
8149 #define MC_IO_TXCNTL_DPHY0_D0__BIASSEL_MASK 0x3
8150 #define MC_IO_TXCNTL_DPHY0_D0__BIASSEL__SHIFT 0x0
8151 #define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY_MASK 0xc
8152 #define MC_IO_TXCNTL_DPHY0_D0__DRVDUTY__SHIFT 0x2
8153 #define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN_MASK 0x10
8154 #define MC_IO_TXCNTL_DPHY0_D0__LOWCMEN__SHIFT 0x4
8155 #define MC_IO_TXCNTL_DPHY0_D0__QDR_MASK 0x20
8156 #define MC_IO_TXCNTL_DPHY0_D0__QDR__SHIFT 0x5
8157 #define MC_IO_TXCNTL_DPHY0_D0__EMPH_MASK 0x40
8158 #define MC_IO_TXCNTL_DPHY0_D0__EMPH__SHIFT 0x6
8159 #define MC_IO_TXCNTL_DPHY0_D0__TXPD_MASK 0x80
8160 #define MC_IO_TXCNTL_DPHY0_D0__TXPD__SHIFT 0x7
8161 #define MC_IO_TXCNTL_DPHY0_D0__PTERM_MASK 0xf00
8162 #define MC_IO_TXCNTL_DPHY0_D0__PTERM__SHIFT 0x8
8163 #define MC_IO_TXCNTL_DPHY0_D0__NTERM_MASK 0xf000
8164 #define MC_IO_TXCNTL_DPHY0_D0__NTERM__SHIFT 0xc
8165 #define MC_IO_TXCNTL_DPHY0_D0__PDRV_MASK 0xf0000
8166 #define MC_IO_TXCNTL_DPHY0_D0__PDRV__SHIFT 0x10
8167 #define MC_IO_TXCNTL_DPHY0_D0__NDRV_MASK 0xf00000
8168 #define MC_IO_TXCNTL_DPHY0_D0__NDRV__SHIFT 0x14
8169 #define MC_IO_TXCNTL_DPHY0_D0__TSTEN_MASK 0x1000000
8170 #define MC_IO_TXCNTL_DPHY0_D0__TSTEN__SHIFT 0x18
8171 #define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
8172 #define MC_IO_TXCNTL_DPHY0_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
8173 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_MASK 0x4000000
8174 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS__SHIFT 0x1a
8175 #define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK_MASK 0x8000000
8176 #define MC_IO_TXCNTL_DPHY0_D0__PLL_LOOPBCK__SHIFT 0x1b
8177 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA_MASK 0xf0000000
8178 #define MC_IO_TXCNTL_DPHY0_D0__TXBYPASS_DATA__SHIFT 0x1c
8179 #define MC_IO_TXCNTL_DPHY1_D0__BIASSEL_MASK 0x3
8180 #define MC_IO_TXCNTL_DPHY1_D0__BIASSEL__SHIFT 0x0
8181 #define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY_MASK 0xc
8182 #define MC_IO_TXCNTL_DPHY1_D0__DRVDUTY__SHIFT 0x2
8183 #define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN_MASK 0x10
8184 #define MC_IO_TXCNTL_DPHY1_D0__LOWCMEN__SHIFT 0x4
8185 #define MC_IO_TXCNTL_DPHY1_D0__QDR_MASK 0x20
8186 #define MC_IO_TXCNTL_DPHY1_D0__QDR__SHIFT 0x5
8187 #define MC_IO_TXCNTL_DPHY1_D0__EMPH_MASK 0x40
8188 #define MC_IO_TXCNTL_DPHY1_D0__EMPH__SHIFT 0x6
8189 #define MC_IO_TXCNTL_DPHY1_D0__TXPD_MASK 0x80
8190 #define MC_IO_TXCNTL_DPHY1_D0__TXPD__SHIFT 0x7
8191 #define MC_IO_TXCNTL_DPHY1_D0__PTERM_MASK 0xf00
8192 #define MC_IO_TXCNTL_DPHY1_D0__PTERM__SHIFT 0x8
8193 #define MC_IO_TXCNTL_DPHY1_D0__NTERM_MASK 0xf000
8194 #define MC_IO_TXCNTL_DPHY1_D0__NTERM__SHIFT 0xc
8195 #define MC_IO_TXCNTL_DPHY1_D0__PDRV_MASK 0xf0000
8196 #define MC_IO_TXCNTL_DPHY1_D0__PDRV__SHIFT 0x10
8197 #define MC_IO_TXCNTL_DPHY1_D0__NDRV_MASK 0xf00000
8198 #define MC_IO_TXCNTL_DPHY1_D0__NDRV__SHIFT 0x14
8199 #define MC_IO_TXCNTL_DPHY1_D0__TSTEN_MASK 0x1000000
8200 #define MC_IO_TXCNTL_DPHY1_D0__TSTEN__SHIFT 0x18
8201 #define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN_MASK 0x2000000
8202 #define MC_IO_TXCNTL_DPHY1_D0__EDCTX_CLKGATE_EN__SHIFT 0x19
8203 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_MASK 0x4000000
8204 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS__SHIFT 0x1a
8205 #define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK_MASK 0x8000000
8206 #define MC_IO_TXCNTL_DPHY1_D0__PLL_LOOPBCK__SHIFT 0x1b
8207 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA_MASK 0xf0000000
8208 #define MC_IO_TXCNTL_DPHY1_D0__TXBYPASS_DATA__SHIFT 0x1c
8209 #define MC_IO_TXCNTL_APHY_D0__BIASSEL_MASK 0x3
8210 #define MC_IO_TXCNTL_APHY_D0__BIASSEL__SHIFT 0x0
8211 #define MC_IO_TXCNTL_APHY_D0__DRVDUTY_MASK 0xc
8212 #define MC_IO_TXCNTL_APHY_D0__DRVDUTY__SHIFT 0x2
8213 #define MC_IO_TXCNTL_APHY_D0__LOWCMEN_MASK 0x10
8214 #define MC_IO_TXCNTL_APHY_D0__LOWCMEN__SHIFT 0x4
8215 #define MC_IO_TXCNTL_APHY_D0__QDR_MASK 0x20
8216 #define MC_IO_TXCNTL_APHY_D0__QDR__SHIFT 0x5
8217 #define MC_IO_TXCNTL_APHY_D0__EMPH_MASK 0x40
8218 #define MC_IO_TXCNTL_APHY_D0__EMPH__SHIFT 0x6
8219 #define MC_IO_TXCNTL_APHY_D0__TXPD_MASK 0x80
8220 #define MC_IO_TXCNTL_APHY_D0__TXPD__SHIFT 0x7
8221 #define MC_IO_TXCNTL_APHY_D0__PTERM_MASK 0xf00
8222 #define MC_IO_TXCNTL_APHY_D0__PTERM__SHIFT 0x8
8223 #define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL_MASK 0x1000
8224 #define MC_IO_TXCNTL_APHY_D0__TXBPASS_SEL__SHIFT 0xc
8225 #define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK_MASK 0xe000
8226 #define MC_IO_TXCNTL_APHY_D0__PMA_LOOPBACK__SHIFT 0xd
8227 #define MC_IO_TXCNTL_APHY_D0__PDRV_MASK 0xf0000
8228 #define MC_IO_TXCNTL_APHY_D0__PDRV__SHIFT 0x10
8229 #define MC_IO_TXCNTL_APHY_D0__NDRV_MASK 0x700000
8230 #define MC_IO_TXCNTL_APHY_D0__NDRV__SHIFT 0x14
8231 #define MC_IO_TXCNTL_APHY_D0__YCLKON_MASK 0x800000
8232 #define MC_IO_TXCNTL_APHY_D0__YCLKON__SHIFT 0x17
8233 #define MC_IO_TXCNTL_APHY_D0__TSTEN_MASK 0x1000000
8234 #define MC_IO_TXCNTL_APHY_D0__TSTEN__SHIFT 0x18
8235 #define MC_IO_TXCNTL_APHY_D0__TXRESET_MASK 0x2000000
8236 #define MC_IO_TXCNTL_APHY_D0__TXRESET__SHIFT 0x19
8237 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_MASK 0x4000000
8238 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS__SHIFT 0x1a
8239 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA_MASK 0x38000000
8240 #define MC_IO_TXCNTL_APHY_D0__TXBYPASS_DATA__SHIFT 0x1b
8241 #define MC_IO_TXCNTL_APHY_D0__CKE_BIT_MASK 0x40000000
8242 #define MC_IO_TXCNTL_APHY_D0__CKE_BIT__SHIFT 0x1e
8243 #define MC_IO_TXCNTL_APHY_D0__CKE_SEL_MASK 0x80000000
8244 #define MC_IO_TXCNTL_APHY_D0__CKE_SEL__SHIFT 0x1f
8245 #define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL_MASK 0x3
8246 #define MC_IO_RXCNTL_DPHY0_D0__RXBIASSEL__SHIFT 0x0
8247 #define MC_IO_RXCNTL_DPHY0_D0__RCVSEL_MASK 0x4
8248 #define MC_IO_RXCNTL_DPHY0_D0__RCVSEL__SHIFT 0x2
8249 #define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB_MASK 0x8
8250 #define MC_IO_RXCNTL_DPHY0_D0__VREFPDNB__SHIFT 0x3
8251 #define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY_MASK 0x30
8252 #define MC_IO_RXCNTL_DPHY0_D0__RXDPWRON_DLY__SHIFT 0x4
8253 #define MC_IO_RXCNTL_DPHY0_D0__RXPDNB_MASK 0x40
8254 #define MC_IO_RXCNTL_DPHY0_D0__RXPDNB__SHIFT 0x6
8255 #define MC_IO_RXCNTL_DPHY0_D0__RXLP_MASK 0x80
8256 #define MC_IO_RXCNTL_DPHY0_D0__RXLP__SHIFT 0x7
8257 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_MASK 0xf00
8258 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL__SHIFT 0x8
8259 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR_MASK 0xf000
8260 #define MC_IO_RXCNTL_DPHY0_D0__VREFCAL_STR__SHIFT 0xc
8261 #define MC_IO_RXCNTL_DPHY0_D0__VREFSEL_MASK 0x10000
8262 #define MC_IO_RXCNTL_DPHY0_D0__VREFSEL__SHIFT 0x10
8263 #define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL_MASK 0xc0000
8264 #define MC_IO_RXCNTL_DPHY0_D0__RX_PEAKSEL__SHIFT 0x12
8265 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0_MASK 0x700000
8266 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B0__SHIFT 0x14
8267 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1_MASK 0x7000000
8268 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_B1__SHIFT 0x18
8269 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M_MASK 0x10000000
8270 #define MC_IO_RXCNTL_DPHY0_D0__DLL_ADJ_M__SHIFT 0x1c
8271 #define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON_MASK 0x20000000
8272 #define MC_IO_RXCNTL_DPHY0_D0__REFCLK_PWRON__SHIFT 0x1d
8273 #define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL_MASK 0xc0000000
8274 #define MC_IO_RXCNTL_DPHY0_D0__DLL_BW_CTRL__SHIFT 0x1e
8275 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB_MASK 0xf
8276 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL1_MSB__SHIFT 0x0
8277 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB_MASK 0xf0
8278 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL2_MSB__SHIFT 0x4
8279 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3_MASK 0xff00
8280 #define MC_IO_RXCNTL1_DPHY0_D0__VREFCAL3__SHIFT 0x8
8281 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2_MASK 0x10000
8282 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL2__SHIFT 0x10
8283 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3_MASK 0x20000
8284 #define MC_IO_RXCNTL1_DPHY0_D0__VREFSEL3__SHIFT 0x11
8285 #define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1_MASK 0x40000
8286 #define MC_IO_RXCNTL1_DPHY0_D0__VREFPDNB_1__SHIFT 0x12
8287 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR_MASK 0x80000
8288 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
8289 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN_MASK 0x100000
8290 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_VCTRLADC_EN__SHIFT 0x14
8291 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY_MASK 0x200000
8292 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_MSTR_STBY__SHIFT 0x15
8293 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN_MASK 0x400000
8294 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_EN__SHIFT 0x16
8295 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT_MASK 0x800000
8296 #define MC_IO_RXCNTL1_DPHY0_D0__RXLEQ_NXT__SHIFT 0x17
8297 #define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK_MASK 0xe000000
8298 #define MC_IO_RXCNTL1_DPHY0_D0__PMD_LOOPBACK__SHIFT 0x19
8299 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV_MASK 0xf0000000
8300 #define MC_IO_RXCNTL1_DPHY0_D0__DLL_RSV__SHIFT 0x1c
8301 #define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL_MASK 0x3
8302 #define MC_IO_RXCNTL_DPHY1_D0__RXBIASSEL__SHIFT 0x0
8303 #define MC_IO_RXCNTL_DPHY1_D0__RCVSEL_MASK 0x4
8304 #define MC_IO_RXCNTL_DPHY1_D0__RCVSEL__SHIFT 0x2
8305 #define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB_MASK 0x8
8306 #define MC_IO_RXCNTL_DPHY1_D0__VREFPDNB__SHIFT 0x3
8307 #define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY_MASK 0x30
8308 #define MC_IO_RXCNTL_DPHY1_D0__RXDPWRON_DLY__SHIFT 0x4
8309 #define MC_IO_RXCNTL_DPHY1_D0__RXPDNB_MASK 0x40
8310 #define MC_IO_RXCNTL_DPHY1_D0__RXPDNB__SHIFT 0x6
8311 #define MC_IO_RXCNTL_DPHY1_D0__RXLP_MASK 0x80
8312 #define MC_IO_RXCNTL_DPHY1_D0__RXLP__SHIFT 0x7
8313 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_MASK 0xf00
8314 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL__SHIFT 0x8
8315 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR_MASK 0xf000
8316 #define MC_IO_RXCNTL_DPHY1_D0__VREFCAL_STR__SHIFT 0xc
8317 #define MC_IO_RXCNTL_DPHY1_D0__VREFSEL_MASK 0x10000
8318 #define MC_IO_RXCNTL_DPHY1_D0__VREFSEL__SHIFT 0x10
8319 #define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL_MASK 0xc0000
8320 #define MC_IO_RXCNTL_DPHY1_D0__RX_PEAKSEL__SHIFT 0x12
8321 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0_MASK 0x700000
8322 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B0__SHIFT 0x14
8323 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1_MASK 0x7000000
8324 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_B1__SHIFT 0x18
8325 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M_MASK 0x10000000
8326 #define MC_IO_RXCNTL_DPHY1_D0__DLL_ADJ_M__SHIFT 0x1c
8327 #define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON_MASK 0x20000000
8328 #define MC_IO_RXCNTL_DPHY1_D0__REFCLK_PWRON__SHIFT 0x1d
8329 #define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL_MASK 0xc0000000
8330 #define MC_IO_RXCNTL_DPHY1_D0__DLL_BW_CTRL__SHIFT 0x1e
8331 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB_MASK 0xf
8332 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL1_MSB__SHIFT 0x0
8333 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB_MASK 0xf0
8334 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL2_MSB__SHIFT 0x4
8335 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3_MASK 0xff00
8336 #define MC_IO_RXCNTL1_DPHY1_D0__VREFCAL3__SHIFT 0x8
8337 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2_MASK 0x10000
8338 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL2__SHIFT 0x10
8339 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3_MASK 0x20000
8340 #define MC_IO_RXCNTL1_DPHY1_D0__VREFSEL3__SHIFT 0x11
8341 #define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1_MASK 0x40000
8342 #define MC_IO_RXCNTL1_DPHY1_D0__VREFPDNB_1__SHIFT 0x12
8343 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR_MASK 0x80000
8344 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_PWRGOOD_OVR__SHIFT 0x13
8345 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN_MASK 0x100000
8346 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_VCTRLADC_EN__SHIFT 0x14
8347 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY_MASK 0x200000
8348 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_MSTR_STBY__SHIFT 0x15
8349 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN_MASK 0x400000
8350 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_EN__SHIFT 0x16
8351 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT_MASK 0x800000
8352 #define MC_IO_RXCNTL1_DPHY1_D0__RXLEQ_NXT__SHIFT 0x17
8353 #define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK_MASK 0xe000000
8354 #define MC_IO_RXCNTL1_DPHY1_D0__PMD_LOOPBACK__SHIFT 0x19
8355 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV_MASK 0xf0000000
8356 #define MC_IO_RXCNTL1_DPHY1_D0__DLL_RSV__SHIFT 0x1c
8357 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D_MASK 0x3f
8358 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_D__SHIFT 0x0
8359 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D_MASK 0xfc0
8360 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_D__SHIFT 0x6
8361 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S_MASK 0x3f000
8362 #define MC_IO_DPHY_STR_CNTL_D0__PSTR_OFF_S__SHIFT 0xc
8363 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S_MASK 0xfc0000
8364 #define MC_IO_DPHY_STR_CNTL_D0__NSTR_OFF_S__SHIFT 0x12
8365 #define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL_MASK 0x1000000
8366 #define MC_IO_DPHY_STR_CNTL_D0__USE_D_CAL__SHIFT 0x18
8367 #define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL_MASK 0x2000000
8368 #define MC_IO_DPHY_STR_CNTL_D0__USE_S_CAL__SHIFT 0x19
8369 #define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
8370 #define MC_IO_DPHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
8371 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR_MASK 0x10000000
8372 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_D_STR__SHIFT 0x1c
8373 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR_MASK 0x20000000
8374 #define MC_IO_DPHY_STR_CNTL_D0__LOAD_S_STR__SHIFT 0x1d
8375 #define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR_MASK 0x40000000
8376 #define MC_IO_DPHY_STR_CNTL_D0__AUTO_LD_STR__SHIFT 0x1e
8377 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A_MASK 0x3f
8378 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_A__SHIFT 0x0
8379 #define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A_MASK 0xfc0
8380 #define MC_IO_APHY_STR_CNTL_D0__NSTR_OFF_A__SHIFT 0x6
8381 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD_MASK 0x3f000
8382 #define MC_IO_APHY_STR_CNTL_D0__PSTR_OFF_D_RD__SHIFT 0xc
8383 #define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL_MASK 0x1000000
8384 #define MC_IO_APHY_STR_CNTL_D0__USE_A_CAL__SHIFT 0x18
8385 #define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL_MASK 0x2000000
8386 #define MC_IO_APHY_STR_CNTL_D0__USE_D_RD_CAL__SHIFT 0x19
8387 #define MC_IO_APHY_STR_CNTL_D0__CAL_SEL_MASK 0xc000000
8388 #define MC_IO_APHY_STR_CNTL_D0__CAL_SEL__SHIFT 0x1a
8389 #define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR_MASK 0x10000000
8390 #define MC_IO_APHY_STR_CNTL_D0__LOAD_A_STR__SHIFT 0x1c
8391 #define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR_MASK 0x20000000
8392 #define MC_IO_APHY_STR_CNTL_D0__LOAD_D_RD_STR__SHIFT 0x1d
8393 #define MC_IO_TXCNTL_DPHY0_D1__BIASSEL_MASK 0x3
8394 #define MC_IO_TXCNTL_DPHY0_D1__BIASSEL__SHIFT 0x0
8395 #define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY_MASK 0xc
8396 #define MC_IO_TXCNTL_DPHY0_D1__DRVDUTY__SHIFT 0x2
8397 #define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN_MASK 0x10
8398 #define MC_IO_TXCNTL_DPHY0_D1__LOWCMEN__SHIFT 0x4
8399 #define MC_IO_TXCNTL_DPHY0_D1__QDR_MASK 0x20
8400 #define MC_IO_TXCNTL_DPHY0_D1__QDR__SHIFT 0x5
8401 #define MC_IO_TXCNTL_DPHY0_D1__EMPH_MASK 0x40
8402 #define MC_IO_TXCNTL_DPHY0_D1__EMPH__SHIFT 0x6
8403 #define MC_IO_TXCNTL_DPHY0_D1__TXPD_MASK 0x80
8404 #define MC_IO_TXCNTL_DPHY0_D1__TXPD__SHIFT 0x7
8405 #define MC_IO_TXCNTL_DPHY0_D1__PTERM_MASK 0xf00
8406 #define MC_IO_TXCNTL_DPHY0_D1__PTERM__SHIFT 0x8
8407 #define MC_IO_TXCNTL_DPHY0_D1__NTERM_MASK 0xf000
8408 #define MC_IO_TXCNTL_DPHY0_D1__NTERM__SHIFT 0xc
8409 #define MC_IO_TXCNTL_DPHY0_D1__PDRV_MASK 0xf0000
8410 #define MC_IO_TXCNTL_DPHY0_D1__PDRV__SHIFT 0x10
8411 #define MC_IO_TXCNTL_DPHY0_D1__NDRV_MASK 0xf00000
8412 #define MC_IO_TXCNTL_DPHY0_D1__NDRV__SHIFT 0x14
8413 #define MC_IO_TXCNTL_DPHY0_D1__TSTEN_MASK 0x1000000
8414 #define MC_IO_TXCNTL_DPHY0_D1__TSTEN__SHIFT 0x18
8415 #define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
8416 #define MC_IO_TXCNTL_DPHY0_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
8417 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_MASK 0x4000000
8418 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS__SHIFT 0x1a
8419 #define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK_MASK 0x8000000
8420 #define MC_IO_TXCNTL_DPHY0_D1__PLL_LOOPBCK__SHIFT 0x1b
8421 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA_MASK 0xf0000000
8422 #define MC_IO_TXCNTL_DPHY0_D1__TXBYPASS_DATA__SHIFT 0x1c
8423 #define MC_IO_TXCNTL_DPHY1_D1__BIASSEL_MASK 0x3
8424 #define MC_IO_TXCNTL_DPHY1_D1__BIASSEL__SHIFT 0x0
8425 #define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY_MASK 0xc
8426 #define MC_IO_TXCNTL_DPHY1_D1__DRVDUTY__SHIFT 0x2
8427 #define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN_MASK 0x10
8428 #define MC_IO_TXCNTL_DPHY1_D1__LOWCMEN__SHIFT 0x4
8429 #define MC_IO_TXCNTL_DPHY1_D1__QDR_MASK 0x20
8430 #define MC_IO_TXCNTL_DPHY1_D1__QDR__SHIFT 0x5
8431 #define MC_IO_TXCNTL_DPHY1_D1__EMPH_MASK 0x40
8432 #define MC_IO_TXCNTL_DPHY1_D1__EMPH__SHIFT 0x6
8433 #define MC_IO_TXCNTL_DPHY1_D1__TXPD_MASK 0x80
8434 #define MC_IO_TXCNTL_DPHY1_D1__TXPD__SHIFT 0x7
8435 #define MC_IO_TXCNTL_DPHY1_D1__PTERM_MASK 0xf00
8436 #define MC_IO_TXCNTL_DPHY1_D1__PTERM__SHIFT 0x8
8437 #define MC_IO_TXCNTL_DPHY1_D1__NTERM_MASK 0xf000
8438 #define MC_IO_TXCNTL_DPHY1_D1__NTERM__SHIFT 0xc
8439 #define MC_IO_TXCNTL_DPHY1_D1__PDRV_MASK 0xf0000
8440 #define MC_IO_TXCNTL_DPHY1_D1__PDRV__SHIFT 0x10
8441 #define MC_IO_TXCNTL_DPHY1_D1__NDRV_MASK 0xf00000
8442 #define MC_IO_TXCNTL_DPHY1_D1__NDRV__SHIFT 0x14
8443 #define MC_IO_TXCNTL_DPHY1_D1__TSTEN_MASK 0x1000000
8444 #define MC_IO_TXCNTL_DPHY1_D1__TSTEN__SHIFT 0x18
8445 #define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN_MASK 0x2000000
8446 #define MC_IO_TXCNTL_DPHY1_D1__EDCTX_CLKGATE_EN__SHIFT 0x19
8447 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_MASK 0x4000000
8448 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS__SHIFT 0x1a
8449 #define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK_MASK 0x8000000
8450 #define MC_IO_TXCNTL_DPHY1_D1__PLL_LOOPBCK__SHIFT 0x1b
8451 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA_MASK 0xf0000000
8452 #define MC_IO_TXCNTL_DPHY1_D1__TXBYPASS_DATA__SHIFT 0x1c
8453 #define MC_IO_TXCNTL_APHY_D1__BIASSEL_MASK 0x3
8454 #define MC_IO_TXCNTL_APHY_D1__BIASSEL__SHIFT 0x0
8455 #define MC_IO_TXCNTL_APHY_D1__DRVDUTY_MASK 0xc
8456 #define MC_IO_TXCNTL_APHY_D1__DRVDUTY__SHIFT 0x2
8457 #define MC_IO_TXCNTL_APHY_D1__LOWCMEN_MASK 0x10
8458 #define MC_IO_TXCNTL_APHY_D1__LOWCMEN__SHIFT 0x4
8459 #define MC_IO_TXCNTL_APHY_D1__QDR_MASK 0x20
8460 #define MC_IO_TXCNTL_APHY_D1__QDR__SHIFT 0x5
8461 #define MC_IO_TXCNTL_APHY_D1__EMPH_MASK 0x40
8462 #define MC_IO_TXCNTL_APHY_D1__EMPH__SHIFT 0x6
8463 #define MC_IO_TXCNTL_APHY_D1__TXPD_MASK 0x80
8464 #define MC_IO_TXCNTL_APHY_D1__TXPD__SHIFT 0x7
8465 #define MC_IO_TXCNTL_APHY_D1__PTERM_MASK 0xf00
8466 #define MC_IO_TXCNTL_APHY_D1__PTERM__SHIFT 0x8
8467 #define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL_MASK 0x1000
8468 #define MC_IO_TXCNTL_APHY_D1__TXBPASS_SEL__SHIFT 0xc
8469 #define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK_MASK 0xe000
8470 #define MC_IO_TXCNTL_APHY_D1__PMA_LOOPBACK__SHIFT 0xd
8471 #define MC_IO_TXCNTL_APHY_D1__PDRV_MASK 0xf0000
8472 #define MC_IO_TXCNTL_APHY_D1__PDRV__SHIFT 0x10
8473 #define MC_IO_TXCNTL_APHY_D1__NDRV_MASK 0x700000
8474 #define MC_IO_TXCNTL_APHY_D1__NDRV__SHIFT 0x14
8475 #define MC_IO_TXCNTL_APHY_D1__YCLKON_MASK 0x800000
8476 #define MC_IO_TXCNTL_APHY_D1__YCLKON__SHIFT 0x17
8477 #define MC_IO_TXCNTL_APHY_D1__TSTEN_MASK 0x1000000
8478 #define MC_IO_TXCNTL_APHY_D1__TSTEN__SHIFT 0x18
8479 #define MC_IO_TXCNTL_APHY_D1__TXRESET_MASK 0x2000000
8480 #define MC_IO_TXCNTL_APHY_D1__TXRESET__SHIFT 0x19
8481 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_MASK 0x4000000
8482 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS__SHIFT 0x1a
8483 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA_MASK 0x38000000
8484 #define MC_IO_TXCNTL_APHY_D1__TXBYPASS_DATA__SHIFT 0x1b
8485 #define MC_IO_TXCNTL_APHY_D1__CKE_BIT_MASK 0x40000000
8486 #define MC_IO_TXCNTL_APHY_D1__CKE_BIT__SHIFT 0x1e
8487 #define MC_IO_TXCNTL_APHY_D1__CKE_SEL_MASK 0x80000000
8488 #define MC_IO_TXCNTL_APHY_D1__CKE_SEL__SHIFT 0x1f
8489 #define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL_MASK 0x3
8490 #define MC_IO_RXCNTL_DPHY0_D1__RXBIASSEL__SHIFT 0x0
8491 #define MC_IO_RXCNTL_DPHY0_D1__RCVSEL_MASK 0x4
8492 #define MC_IO_RXCNTL_DPHY0_D1__RCVSEL__SHIFT 0x2
8493 #define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB_MASK 0x8
8494 #define MC_IO_RXCNTL_DPHY0_D1__VREFPDNB__SHIFT 0x3
8495 #define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY_MASK 0x30
8496 #define MC_IO_RXCNTL_DPHY0_D1__RXDPWRON_DLY__SHIFT 0x4
8497 #define MC_IO_RXCNTL_DPHY0_D1__RXPDNB_MASK 0x40
8498 #define MC_IO_RXCNTL_DPHY0_D1__RXPDNB__SHIFT 0x6
8499 #define MC_IO_RXCNTL_DPHY0_D1__RXLP_MASK 0x80
8500 #define MC_IO_RXCNTL_DPHY0_D1__RXLP__SHIFT 0x7
8501 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_MASK 0xf00
8502 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL__SHIFT 0x8
8503 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR_MASK 0xf000
8504 #define MC_IO_RXCNTL_DPHY0_D1__VREFCAL_STR__SHIFT 0xc
8505 #define MC_IO_RXCNTL_DPHY0_D1__VREFSEL_MASK 0x10000
8506 #define MC_IO_RXCNTL_DPHY0_D1__VREFSEL__SHIFT 0x10
8507 #define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL_MASK 0xc0000
8508 #define MC_IO_RXCNTL_DPHY0_D1__RX_PEAKSEL__SHIFT 0x12
8509 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0_MASK 0x700000
8510 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B0__SHIFT 0x14
8511 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1_MASK 0x7000000
8512 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_B1__SHIFT 0x18
8513 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M_MASK 0x10000000
8514 #define MC_IO_RXCNTL_DPHY0_D1__DLL_ADJ_M__SHIFT 0x1c
8515 #define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON_MASK 0x20000000
8516 #define MC_IO_RXCNTL_DPHY0_D1__REFCLK_PWRON__SHIFT 0x1d
8517 #define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL_MASK 0xc0000000
8518 #define MC_IO_RXCNTL_DPHY0_D1__DLL_BW_CTRL__SHIFT 0x1e
8519 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB_MASK 0xf
8520 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL1_MSB__SHIFT 0x0
8521 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB_MASK 0xf0
8522 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL2_MSB__SHIFT 0x4
8523 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3_MASK 0xff00
8524 #define MC_IO_RXCNTL1_DPHY0_D1__VREFCAL3__SHIFT 0x8
8525 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2_MASK 0x10000
8526 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL2__SHIFT 0x10
8527 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3_MASK 0x20000
8528 #define MC_IO_RXCNTL1_DPHY0_D1__VREFSEL3__SHIFT 0x11
8529 #define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1_MASK 0x40000
8530 #define MC_IO_RXCNTL1_DPHY0_D1__VREFPDNB_1__SHIFT 0x12
8531 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR_MASK 0x80000
8532 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
8533 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN_MASK 0x100000
8534 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_VCTRLADC_EN__SHIFT 0x14
8535 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY_MASK 0x200000
8536 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_MSTR_STBY__SHIFT 0x15
8537 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN_MASK 0x400000
8538 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_EN__SHIFT 0x16
8539 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT_MASK 0x800000
8540 #define MC_IO_RXCNTL1_DPHY0_D1__RXLEQ_NXT__SHIFT 0x17
8541 #define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK_MASK 0xe000000
8542 #define MC_IO_RXCNTL1_DPHY0_D1__PMD_LOOPBACK__SHIFT 0x19
8543 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV_MASK 0xf0000000
8544 #define MC_IO_RXCNTL1_DPHY0_D1__DLL_RSV__SHIFT 0x1c
8545 #define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL_MASK 0x3
8546 #define MC_IO_RXCNTL_DPHY1_D1__RXBIASSEL__SHIFT 0x0
8547 #define MC_IO_RXCNTL_DPHY1_D1__RCVSEL_MASK 0x4
8548 #define MC_IO_RXCNTL_DPHY1_D1__RCVSEL__SHIFT 0x2
8549 #define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB_MASK 0x8
8550 #define MC_IO_RXCNTL_DPHY1_D1__VREFPDNB__SHIFT 0x3
8551 #define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY_MASK 0x30
8552 #define MC_IO_RXCNTL_DPHY1_D1__RXDPWRON_DLY__SHIFT 0x4
8553 #define MC_IO_RXCNTL_DPHY1_D1__RXPDNB_MASK 0x40
8554 #define MC_IO_RXCNTL_DPHY1_D1__RXPDNB__SHIFT 0x6
8555 #define MC_IO_RXCNTL_DPHY1_D1__RXLP_MASK 0x80
8556 #define MC_IO_RXCNTL_DPHY1_D1__RXLP__SHIFT 0x7
8557 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_MASK 0xf00
8558 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL__SHIFT 0x8
8559 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR_MASK 0xf000
8560 #define MC_IO_RXCNTL_DPHY1_D1__VREFCAL_STR__SHIFT 0xc
8561 #define MC_IO_RXCNTL_DPHY1_D1__VREFSEL_MASK 0x10000
8562 #define MC_IO_RXCNTL_DPHY1_D1__VREFSEL__SHIFT 0x10
8563 #define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL_MASK 0xc0000
8564 #define MC_IO_RXCNTL_DPHY1_D1__RX_PEAKSEL__SHIFT 0x12
8565 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0_MASK 0x700000
8566 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B0__SHIFT 0x14
8567 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1_MASK 0x7000000
8568 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_B1__SHIFT 0x18
8569 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M_MASK 0x10000000
8570 #define MC_IO_RXCNTL_DPHY1_D1__DLL_ADJ_M__SHIFT 0x1c
8571 #define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON_MASK 0x20000000
8572 #define MC_IO_RXCNTL_DPHY1_D1__REFCLK_PWRON__SHIFT 0x1d
8573 #define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL_MASK 0xc0000000
8574 #define MC_IO_RXCNTL_DPHY1_D1__DLL_BW_CTRL__SHIFT 0x1e
8575 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB_MASK 0xf
8576 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL1_MSB__SHIFT 0x0
8577 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB_MASK 0xf0
8578 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL2_MSB__SHIFT 0x4
8579 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3_MASK 0xff00
8580 #define MC_IO_RXCNTL1_DPHY1_D1__VREFCAL3__SHIFT 0x8
8581 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2_MASK 0x10000
8582 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL2__SHIFT 0x10
8583 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3_MASK 0x20000
8584 #define MC_IO_RXCNTL1_DPHY1_D1__VREFSEL3__SHIFT 0x11
8585 #define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1_MASK 0x40000
8586 #define MC_IO_RXCNTL1_DPHY1_D1__VREFPDNB_1__SHIFT 0x12
8587 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR_MASK 0x80000
8588 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_PWRGOOD_OVR__SHIFT 0x13
8589 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN_MASK 0x100000
8590 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_VCTRLADC_EN__SHIFT 0x14
8591 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY_MASK 0x200000
8592 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_MSTR_STBY__SHIFT 0x15
8593 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN_MASK 0x400000
8594 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_EN__SHIFT 0x16
8595 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT_MASK 0x800000
8596 #define MC_IO_RXCNTL1_DPHY1_D1__RXLEQ_NXT__SHIFT 0x17
8597 #define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK_MASK 0xe000000
8598 #define MC_IO_RXCNTL1_DPHY1_D1__PMD_LOOPBACK__SHIFT 0x19
8599 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV_MASK 0xf0000000
8600 #define MC_IO_RXCNTL1_DPHY1_D1__DLL_RSV__SHIFT 0x1c
8601 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D_MASK 0x3f
8602 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_D__SHIFT 0x0
8603 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D_MASK 0xfc0
8604 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_D__SHIFT 0x6
8605 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S_MASK 0x3f000
8606 #define MC_IO_DPHY_STR_CNTL_D1__PSTR_OFF_S__SHIFT 0xc
8607 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S_MASK 0xfc0000
8608 #define MC_IO_DPHY_STR_CNTL_D1__NSTR_OFF_S__SHIFT 0x12
8609 #define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL_MASK 0x1000000
8610 #define MC_IO_DPHY_STR_CNTL_D1__USE_D_CAL__SHIFT 0x18
8611 #define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL_MASK 0x2000000
8612 #define MC_IO_DPHY_STR_CNTL_D1__USE_S_CAL__SHIFT 0x19
8613 #define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
8614 #define MC_IO_DPHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
8615 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR_MASK 0x10000000
8616 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_D_STR__SHIFT 0x1c
8617 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR_MASK 0x20000000
8618 #define MC_IO_DPHY_STR_CNTL_D1__LOAD_S_STR__SHIFT 0x1d
8619 #define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR_MASK 0x40000000
8620 #define MC_IO_DPHY_STR_CNTL_D1__AUTO_LD_STR__SHIFT 0x1e
8621 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A_MASK 0x3f
8622 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_A__SHIFT 0x0
8623 #define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A_MASK 0xfc0
8624 #define MC_IO_APHY_STR_CNTL_D1__NSTR_OFF_A__SHIFT 0x6
8625 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD_MASK 0x3f000
8626 #define MC_IO_APHY_STR_CNTL_D1__PSTR_OFF_D_RD__SHIFT 0xc
8627 #define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL_MASK 0x1000000
8628 #define MC_IO_APHY_STR_CNTL_D1__USE_A_CAL__SHIFT 0x18
8629 #define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL_MASK 0x2000000
8630 #define MC_IO_APHY_STR_CNTL_D1__USE_D_RD_CAL__SHIFT 0x19
8631 #define MC_IO_APHY_STR_CNTL_D1__CAL_SEL_MASK 0xc000000
8632 #define MC_IO_APHY_STR_CNTL_D1__CAL_SEL__SHIFT 0x1a
8633 #define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR_MASK 0x10000000
8634 #define MC_IO_APHY_STR_CNTL_D1__LOAD_A_STR__SHIFT 0x1c
8635 #define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR_MASK 0x20000000
8636 #define MC_IO_APHY_STR_CNTL_D1__LOAD_D_RD_STR__SHIFT 0x1d
8637 #define MC_IO_CDRCNTL_D0__RXPHASE_B01_MASK 0xf
8638 #define MC_IO_CDRCNTL_D0__RXPHASE_B01__SHIFT 0x0
8639 #define MC_IO_CDRCNTL_D0__RXPHASE_B23_MASK 0xf0
8640 #define MC_IO_CDRCNTL_D0__RXPHASE_B23__SHIFT 0x4
8641 #define MC_IO_CDRCNTL_D0__RXCDREN_B01_MASK 0x100
8642 #define MC_IO_CDRCNTL_D0__RXCDREN_B01__SHIFT 0x8
8643 #define MC_IO_CDRCNTL_D0__RXCDREN_B23_MASK 0x200
8644 #define MC_IO_CDRCNTL_D0__RXCDREN_B23__SHIFT 0x9
8645 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01_MASK 0x400
8646 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B01__SHIFT 0xa
8647 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23_MASK 0x800
8648 #define MC_IO_CDRCNTL_D0__RXCDRBYPASS_B23__SHIFT 0xb
8649 #define MC_IO_CDRCNTL_D0__RXPHASE1_B01_MASK 0xf000
8650 #define MC_IO_CDRCNTL_D0__RXPHASE1_B01__SHIFT 0xc
8651 #define MC_IO_CDRCNTL_D0__RXPHASE1_B23_MASK 0xf0000
8652 #define MC_IO_CDRCNTL_D0__RXPHASE1_B23__SHIFT 0x10
8653 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B0_MASK 0x100000
8654 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B0__SHIFT 0x14
8655 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B1_MASK 0x200000
8656 #define MC_IO_CDRCNTL_D0__DQTXCDREN_B1__SHIFT 0x15
8657 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B0_MASK 0x400000
8658 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B0__SHIFT 0x16
8659 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B1_MASK 0x800000
8660 #define MC_IO_CDRCNTL_D0__DQRXCDREN_B1__SHIFT 0x17
8661 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0_MASK 0x1000000
8662 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B0__SHIFT 0x18
8663 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1_MASK 0x2000000
8664 #define MC_IO_CDRCNTL_D0__WCDRRXCDREN_B1__SHIFT 0x19
8665 #define MC_IO_CDRCNTL_D0__WCDREDC_B0_MASK 0x4000000
8666 #define MC_IO_CDRCNTL_D0__WCDREDC_B0__SHIFT 0x1a
8667 #define MC_IO_CDRCNTL_D0__WCDREDC_B1_MASK 0x8000000
8668 #define MC_IO_CDRCNTL_D0__WCDREDC_B1__SHIFT 0x1b
8669 #define MC_IO_CDRCNTL_D0__DQRXSEL_B0_MASK 0x10000000
8670 #define MC_IO_CDRCNTL_D0__DQRXSEL_B0__SHIFT 0x1c
8671 #define MC_IO_CDRCNTL_D0__DQRXSEL_B1_MASK 0x20000000
8672 #define MC_IO_CDRCNTL_D0__DQRXSEL_B1__SHIFT 0x1d
8673 #define MC_IO_CDRCNTL_D0__DQTXSEL_B0_MASK 0x40000000
8674 #define MC_IO_CDRCNTL_D0__DQTXSEL_B0__SHIFT 0x1e
8675 #define MC_IO_CDRCNTL_D0__DQTXSEL_B1_MASK 0x80000000
8676 #define MC_IO_CDRCNTL_D0__DQTXSEL_B1__SHIFT 0x1f
8677 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0_MASK 0xff
8678 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B0__SHIFT 0x0
8679 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1_MASK 0xff00
8680 #define MC_IO_CDRCNTL1_D0__DQ_RXPHASE_B1__SHIFT 0x8
8681 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0_MASK 0xff0000
8682 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B0__SHIFT 0x10
8683 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1_MASK 0xff000000
8684 #define MC_IO_CDRCNTL1_D0__WCDR_TXPHASE_B1__SHIFT 0x18
8685 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0_MASK 0x1
8686 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL0__SHIFT 0x0
8687 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1_MASK 0x2
8688 #define MC_IO_CDRCNTL2_D0__CDR_FB_SEL1__SHIFT 0x1
8689 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0_MASK 0x4
8690 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR0__SHIFT 0x2
8691 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1_MASK 0x8
8692 #define MC_IO_CDRCNTL2_D0__EDC_RXEN_OVR1__SHIFT 0x3
8693 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0_MASK 0x10
8694 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS0__SHIFT 0x4
8695 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1_MASK 0x20
8696 #define MC_IO_CDRCNTL2_D0__TXCDRBYPASS1__SHIFT 0x5
8697 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0_MASK 0x40
8698 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR0__SHIFT 0x6
8699 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1_MASK 0x80
8700 #define MC_IO_CDRCNTL2_D0__WCK_RXEN_OVR1__SHIFT 0x7
8701 #define MC_IO_CDRCNTL2_D0__WCDRTXPWRON_MASK 0xf00
8702 #define MC_IO_CDRCNTL2_D0__WCDRTXPWRON__SHIFT 0x8
8703 #define MC_IO_CDRCNTL2_D0__WCDRTXSEL_MASK 0xf000
8704 #define MC_IO_CDRCNTL2_D0__WCDRTXSEL__SHIFT 0xc
8705 #define MC_IO_CDRCNTL2_D0__WCDRTRACK01_MASK 0xf0000
8706 #define MC_IO_CDRCNTL2_D0__WCDRTRACK01__SHIFT 0x10
8707 #define MC_IO_CDRCNTL_D1__RXPHASE_B01_MASK 0xf
8708 #define MC_IO_CDRCNTL_D1__RXPHASE_B01__SHIFT 0x0
8709 #define MC_IO_CDRCNTL_D1__RXPHASE_B23_MASK 0xf0
8710 #define MC_IO_CDRCNTL_D1__RXPHASE_B23__SHIFT 0x4
8711 #define MC_IO_CDRCNTL_D1__RXCDREN_B01_MASK 0x100
8712 #define MC_IO_CDRCNTL_D1__RXCDREN_B01__SHIFT 0x8
8713 #define MC_IO_CDRCNTL_D1__RXCDREN_B23_MASK 0x200
8714 #define MC_IO_CDRCNTL_D1__RXCDREN_B23__SHIFT 0x9
8715 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01_MASK 0x400
8716 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B01__SHIFT 0xa
8717 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23_MASK 0x800
8718 #define MC_IO_CDRCNTL_D1__RXCDRBYPASS_B23__SHIFT 0xb
8719 #define MC_IO_CDRCNTL_D1__RXPHASE1_B01_MASK 0xf000
8720 #define MC_IO_CDRCNTL_D1__RXPHASE1_B01__SHIFT 0xc
8721 #define MC_IO_CDRCNTL_D1__RXPHASE1_B23_MASK 0xf0000
8722 #define MC_IO_CDRCNTL_D1__RXPHASE1_B23__SHIFT 0x10
8723 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B0_MASK 0x100000
8724 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B0__SHIFT 0x14
8725 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B1_MASK 0x200000
8726 #define MC_IO_CDRCNTL_D1__DQTXCDREN_B1__SHIFT 0x15
8727 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B0_MASK 0x400000
8728 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B0__SHIFT 0x16
8729 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B1_MASK 0x800000
8730 #define MC_IO_CDRCNTL_D1__DQRXCDREN_B1__SHIFT 0x17
8731 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0_MASK 0x1000000
8732 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B0__SHIFT 0x18
8733 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1_MASK 0x2000000
8734 #define MC_IO_CDRCNTL_D1__WCDRRXCDREN_B1__SHIFT 0x19
8735 #define MC_IO_CDRCNTL_D1__WCDREDC_B0_MASK 0x4000000
8736 #define MC_IO_CDRCNTL_D1__WCDREDC_B0__SHIFT 0x1a
8737 #define MC_IO_CDRCNTL_D1__WCDREDC_B1_MASK 0x8000000
8738 #define MC_IO_CDRCNTL_D1__WCDREDC_B1__SHIFT 0x1b
8739 #define MC_IO_CDRCNTL_D1__DQRXSEL_B0_MASK 0x10000000
8740 #define MC_IO_CDRCNTL_D1__DQRXSEL_B0__SHIFT 0x1c
8741 #define MC_IO_CDRCNTL_D1__DQRXSEL_B1_MASK 0x20000000
8742 #define MC_IO_CDRCNTL_D1__DQRXSEL_B1__SHIFT 0x1d
8743 #define MC_IO_CDRCNTL_D1__DQTXSEL_B0_MASK 0x40000000
8744 #define MC_IO_CDRCNTL_D1__DQTXSEL_B0__SHIFT 0x1e
8745 #define MC_IO_CDRCNTL_D1__DQTXSEL_B1_MASK 0x80000000
8746 #define MC_IO_CDRCNTL_D1__DQTXSEL_B1__SHIFT 0x1f
8747 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0_MASK 0xff
8748 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B0__SHIFT 0x0
8749 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1_MASK 0xff00
8750 #define MC_IO_CDRCNTL1_D1__DQ_RXPHASE_B1__SHIFT 0x8
8751 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0_MASK 0xff0000
8752 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B0__SHIFT 0x10
8753 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1_MASK 0xff000000
8754 #define MC_IO_CDRCNTL1_D1__WCDR_TXPHASE_B1__SHIFT 0x18
8755 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0_MASK 0x1
8756 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL0__SHIFT 0x0
8757 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1_MASK 0x2
8758 #define MC_IO_CDRCNTL2_D1__CDR_FB_SEL1__SHIFT 0x1
8759 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0_MASK 0x4
8760 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR0__SHIFT 0x2
8761 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1_MASK 0x8
8762 #define MC_IO_CDRCNTL2_D1__EDC_RXEN_OVR1__SHIFT 0x3
8763 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0_MASK 0x10
8764 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS0__SHIFT 0x4
8765 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1_MASK 0x20
8766 #define MC_IO_CDRCNTL2_D1__TXCDRBYPASS1__SHIFT 0x5
8767 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0_MASK 0x40
8768 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR0__SHIFT 0x6
8769 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1_MASK 0x80
8770 #define MC_IO_CDRCNTL2_D1__WCK_RXEN_OVR1__SHIFT 0x7
8771 #define MC_IO_CDRCNTL2_D1__WCDRTXPWRON_MASK 0xf00
8772 #define MC_IO_CDRCNTL2_D1__WCDRTXPWRON__SHIFT 0x8
8773 #define MC_IO_CDRCNTL2_D1__WCDRTXSEL_MASK 0xf000
8774 #define MC_IO_CDRCNTL2_D1__WCDRTXSEL__SHIFT 0xc
8775 #define MC_IO_CDRCNTL2_D1__WCDRTRACK01_MASK 0xf0000
8776 #define MC_IO_CDRCNTL2_D1__WCDRTRACK01__SHIFT 0x10
8777 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D0_MASK 0x3
8778 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D0__SHIFT 0x0
8779 #define MC_SEQ_FIFO_CTL__W_SYC_SEL_MASK 0xc
8780 #define MC_SEQ_FIFO_CTL__W_SYC_SEL__SHIFT 0x2
8781 #define MC_SEQ_FIFO_CTL__R_LD_INIT_MASK 0x30
8782 #define MC_SEQ_FIFO_CTL__R_LD_INIT__SHIFT 0x4
8783 #define MC_SEQ_FIFO_CTL__R_SYC_SEL_MASK 0xc0
8784 #define MC_SEQ_FIFO_CTL__R_SYC_SEL__SHIFT 0x6
8785 #define MC_SEQ_FIFO_CTL__CG_DIS_D0_MASK 0x100
8786 #define MC_SEQ_FIFO_CTL__CG_DIS_D0__SHIFT 0x8
8787 #define MC_SEQ_FIFO_CTL__CG_DIS_D1_MASK 0x200
8788 #define MC_SEQ_FIFO_CTL__CG_DIS_D1__SHIFT 0x9
8789 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D1_MASK 0xc00
8790 #define MC_SEQ_FIFO_CTL__W_LD_INIT_D1__SHIFT 0xa
8791 #define MC_SEQ_FIFO_CTL__SYC_DLY_MASK 0x7000
8792 #define MC_SEQ_FIFO_CTL__SYC_DLY__SHIFT 0xc
8793 #define MC_SEQ_FIFO_CTL__W_ASYC_EXT_MASK 0x30000
8794 #define MC_SEQ_FIFO_CTL__W_ASYC_EXT__SHIFT 0x10
8795 #define MC_SEQ_FIFO_CTL__W_DSYC_EXT_MASK 0xc0000
8796 #define MC_SEQ_FIFO_CTL__W_DSYC_EXT__SHIFT 0x12
8797 #define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT_MASK 0xf00000
8798 #define MC_SEQ_FIFO_CTL__R_DQS_LD_INIT__SHIFT 0x14
8799 #define MC_SEQ_FIFO_CTL__R_DQS_STEP_MASK 0xf000000
8800 #define MC_SEQ_FIFO_CTL__R_DQS_STEP__SHIFT 0x18
8801 #define MC_SEQ_FIFO_CTL__R_DQS_FRC_MASK 0x10000000
8802 #define MC_SEQ_FIFO_CTL__R_DQS_FRC__SHIFT 0x1c
8803 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0_MASK 0xf
8804 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
8805 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
8806 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
8807 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
8808 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
8809 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
8810 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
8811 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
8812 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
8813 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
8814 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
8815 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
8816 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
8817 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
8818 #define MC_SEQ_TXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
8819 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0_MASK 0xf
8820 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
8821 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
8822 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
8823 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
8824 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
8825 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
8826 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
8827 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
8828 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
8829 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
8830 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
8831 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
8832 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
8833 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
8834 #define MC_SEQ_TXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
8835 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0_MASK 0xf
8836 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
8837 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
8838 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
8839 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
8840 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
8841 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
8842 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
8843 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
8844 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
8845 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
8846 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
8847 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
8848 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
8849 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
8850 #define MC_SEQ_TXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
8851 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0_MASK 0xf
8852 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
8853 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
8854 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
8855 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
8856 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
8857 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
8858 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
8859 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
8860 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
8861 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
8862 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
8863 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
8864 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
8865 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
8866 #define MC_SEQ_TXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
8867 #define MC_SEQ_TXFRAMING_DBI_D0__DBI0_MASK 0xf
8868 #define MC_SEQ_TXFRAMING_DBI_D0__DBI0__SHIFT 0x0
8869 #define MC_SEQ_TXFRAMING_DBI_D0__DBI1_MASK 0xf0
8870 #define MC_SEQ_TXFRAMING_DBI_D0__DBI1__SHIFT 0x4
8871 #define MC_SEQ_TXFRAMING_DBI_D0__DBI2_MASK 0xf00
8872 #define MC_SEQ_TXFRAMING_DBI_D0__DBI2__SHIFT 0x8
8873 #define MC_SEQ_TXFRAMING_DBI_D0__DBI3_MASK 0xf000
8874 #define MC_SEQ_TXFRAMING_DBI_D0__DBI3__SHIFT 0xc
8875 #define MC_SEQ_TXFRAMING_EDC_D0__EDC0_MASK 0xf
8876 #define MC_SEQ_TXFRAMING_EDC_D0__EDC0__SHIFT 0x0
8877 #define MC_SEQ_TXFRAMING_EDC_D0__EDC1_MASK 0xf0
8878 #define MC_SEQ_TXFRAMING_EDC_D0__EDC1__SHIFT 0x4
8879 #define MC_SEQ_TXFRAMING_EDC_D0__EDC2_MASK 0xf00
8880 #define MC_SEQ_TXFRAMING_EDC_D0__EDC2__SHIFT 0x8
8881 #define MC_SEQ_TXFRAMING_EDC_D0__EDC3_MASK 0xf000
8882 #define MC_SEQ_TXFRAMING_EDC_D0__EDC3__SHIFT 0xc
8883 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
8884 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
8885 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
8886 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
8887 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
8888 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
8889 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
8890 #define MC_SEQ_TXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
8891 #define MC_SEQ_TXFRAMING_FCK_D0__FCK0_MASK 0xf
8892 #define MC_SEQ_TXFRAMING_FCK_D0__FCK0__SHIFT 0x0
8893 #define MC_SEQ_TXFRAMING_FCK_D0__FCK1_MASK 0xf0
8894 #define MC_SEQ_TXFRAMING_FCK_D0__FCK1__SHIFT 0x4
8895 #define MC_SEQ_TXFRAMING_FCK_D0__FCK2_MASK 0xf00
8896 #define MC_SEQ_TXFRAMING_FCK_D0__FCK2__SHIFT 0x8
8897 #define MC_SEQ_TXFRAMING_FCK_D0__FCK3_MASK 0xf000
8898 #define MC_SEQ_TXFRAMING_FCK_D0__FCK3__SHIFT 0xc
8899 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0_MASK 0xf
8900 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
8901 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
8902 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
8903 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
8904 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
8905 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
8906 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
8907 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
8908 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
8909 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
8910 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
8911 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
8912 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
8913 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
8914 #define MC_SEQ_TXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
8915 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0_MASK 0xf
8916 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
8917 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
8918 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
8919 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
8920 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
8921 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
8922 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
8923 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
8924 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
8925 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
8926 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
8927 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
8928 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
8929 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
8930 #define MC_SEQ_TXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
8931 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0_MASK 0xf
8932 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
8933 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
8934 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
8935 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
8936 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
8937 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
8938 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
8939 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
8940 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
8941 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
8942 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
8943 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
8944 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
8945 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
8946 #define MC_SEQ_TXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
8947 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0_MASK 0xf
8948 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
8949 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
8950 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
8951 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
8952 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
8953 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
8954 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
8955 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
8956 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
8957 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
8958 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
8959 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
8960 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
8961 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
8962 #define MC_SEQ_TXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
8963 #define MC_SEQ_TXFRAMING_DBI_D1__DBI0_MASK 0xf
8964 #define MC_SEQ_TXFRAMING_DBI_D1__DBI0__SHIFT 0x0
8965 #define MC_SEQ_TXFRAMING_DBI_D1__DBI1_MASK 0xf0
8966 #define MC_SEQ_TXFRAMING_DBI_D1__DBI1__SHIFT 0x4
8967 #define MC_SEQ_TXFRAMING_DBI_D1__DBI2_MASK 0xf00
8968 #define MC_SEQ_TXFRAMING_DBI_D1__DBI2__SHIFT 0x8
8969 #define MC_SEQ_TXFRAMING_DBI_D1__DBI3_MASK 0xf000
8970 #define MC_SEQ_TXFRAMING_DBI_D1__DBI3__SHIFT 0xc
8971 #define MC_SEQ_TXFRAMING_EDC_D1__EDC0_MASK 0xf
8972 #define MC_SEQ_TXFRAMING_EDC_D1__EDC0__SHIFT 0x0
8973 #define MC_SEQ_TXFRAMING_EDC_D1__EDC1_MASK 0xf0
8974 #define MC_SEQ_TXFRAMING_EDC_D1__EDC1__SHIFT 0x4
8975 #define MC_SEQ_TXFRAMING_EDC_D1__EDC2_MASK 0xf00
8976 #define MC_SEQ_TXFRAMING_EDC_D1__EDC2__SHIFT 0x8
8977 #define MC_SEQ_TXFRAMING_EDC_D1__EDC3_MASK 0xf000
8978 #define MC_SEQ_TXFRAMING_EDC_D1__EDC3__SHIFT 0xc
8979 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
8980 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
8981 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
8982 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
8983 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
8984 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
8985 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
8986 #define MC_SEQ_TXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
8987 #define MC_SEQ_TXFRAMING_FCK_D1__FCK0_MASK 0xf
8988 #define MC_SEQ_TXFRAMING_FCK_D1__FCK0__SHIFT 0x0
8989 #define MC_SEQ_TXFRAMING_FCK_D1__FCK1_MASK 0xf0
8990 #define MC_SEQ_TXFRAMING_FCK_D1__FCK1__SHIFT 0x4
8991 #define MC_SEQ_TXFRAMING_FCK_D1__FCK2_MASK 0xf00
8992 #define MC_SEQ_TXFRAMING_FCK_D1__FCK2__SHIFT 0x8
8993 #define MC_SEQ_TXFRAMING_FCK_D1__FCK3_MASK 0xf000
8994 #define MC_SEQ_TXFRAMING_FCK_D1__FCK3__SHIFT 0xc
8995 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0_MASK 0xf
8996 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ0__SHIFT 0x0
8997 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1_MASK 0xf0
8998 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ1__SHIFT 0x4
8999 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2_MASK 0xf00
9000 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ2__SHIFT 0x8
9001 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3_MASK 0xf000
9002 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ3__SHIFT 0xc
9003 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4_MASK 0xf0000
9004 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ4__SHIFT 0x10
9005 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5_MASK 0xf00000
9006 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ5__SHIFT 0x14
9007 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6_MASK 0xf000000
9008 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ6__SHIFT 0x18
9009 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7_MASK 0xf0000000
9010 #define MC_SEQ_RXFRAMING_BYTE0_D0__DQ7__SHIFT 0x1c
9011 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0_MASK 0xf
9012 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ0__SHIFT 0x0
9013 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1_MASK 0xf0
9014 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ1__SHIFT 0x4
9015 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2_MASK 0xf00
9016 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ2__SHIFT 0x8
9017 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3_MASK 0xf000
9018 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ3__SHIFT 0xc
9019 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4_MASK 0xf0000
9020 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ4__SHIFT 0x10
9021 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5_MASK 0xf00000
9022 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ5__SHIFT 0x14
9023 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6_MASK 0xf000000
9024 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ6__SHIFT 0x18
9025 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7_MASK 0xf0000000
9026 #define MC_SEQ_RXFRAMING_BYTE1_D0__DQ7__SHIFT 0x1c
9027 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0_MASK 0xf
9028 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ0__SHIFT 0x0
9029 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1_MASK 0xf0
9030 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ1__SHIFT 0x4
9031 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2_MASK 0xf00
9032 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ2__SHIFT 0x8
9033 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3_MASK 0xf000
9034 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ3__SHIFT 0xc
9035 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4_MASK 0xf0000
9036 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ4__SHIFT 0x10
9037 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5_MASK 0xf00000
9038 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ5__SHIFT 0x14
9039 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6_MASK 0xf000000
9040 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ6__SHIFT 0x18
9041 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7_MASK 0xf0000000
9042 #define MC_SEQ_RXFRAMING_BYTE2_D0__DQ7__SHIFT 0x1c
9043 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0_MASK 0xf
9044 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ0__SHIFT 0x0
9045 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1_MASK 0xf0
9046 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ1__SHIFT 0x4
9047 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2_MASK 0xf00
9048 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ2__SHIFT 0x8
9049 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3_MASK 0xf000
9050 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ3__SHIFT 0xc
9051 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4_MASK 0xf0000
9052 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ4__SHIFT 0x10
9053 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5_MASK 0xf00000
9054 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ5__SHIFT 0x14
9055 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6_MASK 0xf000000
9056 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ6__SHIFT 0x18
9057 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7_MASK 0xf0000000
9058 #define MC_SEQ_RXFRAMING_BYTE3_D0__DQ7__SHIFT 0x1c
9059 #define MC_SEQ_RXFRAMING_DBI_D0__DBI0_MASK 0xf
9060 #define MC_SEQ_RXFRAMING_DBI_D0__DBI0__SHIFT 0x0
9061 #define MC_SEQ_RXFRAMING_DBI_D0__DBI1_MASK 0xf0
9062 #define MC_SEQ_RXFRAMING_DBI_D0__DBI1__SHIFT 0x4
9063 #define MC_SEQ_RXFRAMING_DBI_D0__DBI2_MASK 0xf00
9064 #define MC_SEQ_RXFRAMING_DBI_D0__DBI2__SHIFT 0x8
9065 #define MC_SEQ_RXFRAMING_DBI_D0__DBI3_MASK 0xf000
9066 #define MC_SEQ_RXFRAMING_DBI_D0__DBI3__SHIFT 0xc
9067 #define MC_SEQ_RXFRAMING_EDC_D0__EDC0_MASK 0xf
9068 #define MC_SEQ_RXFRAMING_EDC_D0__EDC0__SHIFT 0x0
9069 #define MC_SEQ_RXFRAMING_EDC_D0__EDC1_MASK 0xf0
9070 #define MC_SEQ_RXFRAMING_EDC_D0__EDC1__SHIFT 0x4
9071 #define MC_SEQ_RXFRAMING_EDC_D0__EDC2_MASK 0xf00
9072 #define MC_SEQ_RXFRAMING_EDC_D0__EDC2__SHIFT 0x8
9073 #define MC_SEQ_RXFRAMING_EDC_D0__EDC3_MASK 0xf000
9074 #define MC_SEQ_RXFRAMING_EDC_D0__EDC3__SHIFT 0xc
9075 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR0_MASK 0xf0000
9076 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR0__SHIFT 0x10
9077 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR1_MASK 0xf00000
9078 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR1__SHIFT 0x14
9079 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR2_MASK 0xf000000
9080 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR2__SHIFT 0x18
9081 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR3_MASK 0xf0000000
9082 #define MC_SEQ_RXFRAMING_EDC_D0__WCDR3__SHIFT 0x1c
9083 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0_MASK 0xf
9084 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ0__SHIFT 0x0
9085 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1_MASK 0xf0
9086 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ1__SHIFT 0x4
9087 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2_MASK 0xf00
9088 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ2__SHIFT 0x8
9089 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3_MASK 0xf000
9090 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ3__SHIFT 0xc
9091 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4_MASK 0xf0000
9092 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ4__SHIFT 0x10
9093 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5_MASK 0xf00000
9094 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ5__SHIFT 0x14
9095 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6_MASK 0xf000000
9096 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ6__SHIFT 0x18
9097 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7_MASK 0xf0000000
9098 #define MC_SEQ_RXFRAMING_BYTE0_D1__DQ7__SHIFT 0x1c
9099 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0_MASK 0xf
9100 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ0__SHIFT 0x0
9101 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1_MASK 0xf0
9102 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ1__SHIFT 0x4
9103 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2_MASK 0xf00
9104 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ2__SHIFT 0x8
9105 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3_MASK 0xf000
9106 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ3__SHIFT 0xc
9107 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4_MASK 0xf0000
9108 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ4__SHIFT 0x10
9109 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5_MASK 0xf00000
9110 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ5__SHIFT 0x14
9111 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6_MASK 0xf000000
9112 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ6__SHIFT 0x18
9113 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7_MASK 0xf0000000
9114 #define MC_SEQ_RXFRAMING_BYTE1_D1__DQ7__SHIFT 0x1c
9115 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0_MASK 0xf
9116 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ0__SHIFT 0x0
9117 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1_MASK 0xf0
9118 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ1__SHIFT 0x4
9119 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2_MASK 0xf00
9120 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ2__SHIFT 0x8
9121 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3_MASK 0xf000
9122 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ3__SHIFT 0xc
9123 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4_MASK 0xf0000
9124 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ4__SHIFT 0x10
9125 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5_MASK 0xf00000
9126 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ5__SHIFT 0x14
9127 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6_MASK 0xf000000
9128 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ6__SHIFT 0x18
9129 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7_MASK 0xf0000000
9130 #define MC_SEQ_RXFRAMING_BYTE2_D1__DQ7__SHIFT 0x1c
9131 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0_MASK 0xf
9132 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ0__SHIFT 0x0
9133 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1_MASK 0xf0
9134 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ1__SHIFT 0x4
9135 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2_MASK 0xf00
9136 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ2__SHIFT 0x8
9137 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3_MASK 0xf000
9138 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ3__SHIFT 0xc
9139 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4_MASK 0xf0000
9140 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ4__SHIFT 0x10
9141 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5_MASK 0xf00000
9142 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ5__SHIFT 0x14
9143 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6_MASK 0xf000000
9144 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ6__SHIFT 0x18
9145 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7_MASK 0xf0000000
9146 #define MC_SEQ_RXFRAMING_BYTE3_D1__DQ7__SHIFT 0x1c
9147 #define MC_SEQ_RXFRAMING_DBI_D1__DBI0_MASK 0xf
9148 #define MC_SEQ_RXFRAMING_DBI_D1__DBI0__SHIFT 0x0
9149 #define MC_SEQ_RXFRAMING_DBI_D1__DBI1_MASK 0xf0
9150 #define MC_SEQ_RXFRAMING_DBI_D1__DBI1__SHIFT 0x4
9151 #define MC_SEQ_RXFRAMING_DBI_D1__DBI2_MASK 0xf00
9152 #define MC_SEQ_RXFRAMING_DBI_D1__DBI2__SHIFT 0x8
9153 #define MC_SEQ_RXFRAMING_DBI_D1__DBI3_MASK 0xf000
9154 #define MC_SEQ_RXFRAMING_DBI_D1__DBI3__SHIFT 0xc
9155 #define MC_SEQ_RXFRAMING_EDC_D1__EDC0_MASK 0xf
9156 #define MC_SEQ_RXFRAMING_EDC_D1__EDC0__SHIFT 0x0
9157 #define MC_SEQ_RXFRAMING_EDC_D1__EDC1_MASK 0xf0
9158 #define MC_SEQ_RXFRAMING_EDC_D1__EDC1__SHIFT 0x4
9159 #define MC_SEQ_RXFRAMING_EDC_D1__EDC2_MASK 0xf00
9160 #define MC_SEQ_RXFRAMING_EDC_D1__EDC2__SHIFT 0x8
9161 #define MC_SEQ_RXFRAMING_EDC_D1__EDC3_MASK 0xf000
9162 #define MC_SEQ_RXFRAMING_EDC_D1__EDC3__SHIFT 0xc
9163 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR0_MASK 0xf0000
9164 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR0__SHIFT 0x10
9165 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR1_MASK 0xf00000
9166 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR1__SHIFT 0x14
9167 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR2_MASK 0xf000000
9168 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR2__SHIFT 0x18
9169 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR3_MASK 0xf0000000
9170 #define MC_SEQ_RXFRAMING_EDC_D1__WCDR3__SHIFT 0x1c
9171 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN_MASK 0xff
9172 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MIN__SHIFT 0x0
9173 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX_MASK 0xff00
9174 #define MC_IO_PAD_CNTL__MEM_IO_IMP_MAX__SHIFT 0x8
9175 #define MC_IO_PAD_CNTL__TXPHASE_GRAY_MASK 0x10000
9176 #define MC_IO_PAD_CNTL__TXPHASE_GRAY__SHIFT 0x10
9177 #define MC_IO_PAD_CNTL__RXPHASE_GRAY_MASK 0x20000
9178 #define MC_IO_PAD_CNTL__RXPHASE_GRAY__SHIFT 0x11
9179 #define MC_IO_PAD_CNTL__OVL_YCLKON_D0_MASK 0x40000
9180 #define MC_IO_PAD_CNTL__OVL_YCLKON_D0__SHIFT 0x12
9181 #define MC_IO_PAD_CNTL__OVL_YCLKON_D1_MASK 0x80000
9182 #define MC_IO_PAD_CNTL__OVL_YCLKON_D1__SHIFT 0x13
9183 #define MC_IO_PAD_CNTL__ATBSEL_MASK 0xf00000
9184 #define MC_IO_PAD_CNTL__ATBSEL__SHIFT 0x14
9185 #define MC_IO_PAD_CNTL__ATBEN_MASK 0x3f000000
9186 #define MC_IO_PAD_CNTL__ATBEN__SHIFT 0x18
9187 #define MC_IO_PAD_CNTL__ATBSEL_D1_MASK 0x40000000
9188 #define MC_IO_PAD_CNTL__ATBSEL_D1__SHIFT 0x1e
9189 #define MC_IO_PAD_CNTL__ATBSEL_D0_MASK 0x80000000
9190 #define MC_IO_PAD_CNTL__ATBSEL_D0__SHIFT 0x1f
9191 #define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC_MASK 0x4
9192 #define MC_IO_PAD_CNTL_D0__DELAY_CLK_SYNC__SHIFT 0x2
9193 #define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC_MASK 0x8
9194 #define MC_IO_PAD_CNTL_D0__DELAY_CMD_SYNC__SHIFT 0x3
9195 #define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC_MASK 0x10
9196 #define MC_IO_PAD_CNTL_D0__DELAY_ADR_SYNC__SHIFT 0x4
9197 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK_MASK 0x80
9198 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CLK__SHIFT 0x7
9199 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD_MASK 0x100
9200 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_CMD__SHIFT 0x8
9201 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR_MASK 0x200
9202 #define MC_IO_PAD_CNTL_D0__MEM_FALL_OUT_ADR__SHIFT 0x9
9203 #define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR_MASK 0x400
9204 #define MC_IO_PAD_CNTL_D0__FORCE_EN_RD_STR__SHIFT 0xa
9205 #define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY_MASK 0x800
9206 #define MC_IO_PAD_CNTL_D0__EN_RD_STR_DLY__SHIFT 0xb
9207 #define MC_IO_PAD_CNTL_D0__DISABLE_CMD_MASK 0x1000
9208 #define MC_IO_PAD_CNTL_D0__DISABLE_CMD__SHIFT 0xc
9209 #define MC_IO_PAD_CNTL_D0__DISABLE_ADR_MASK 0x2000
9210 #define MC_IO_PAD_CNTL_D0__DISABLE_ADR__SHIFT 0xd
9211 #define MC_IO_PAD_CNTL_D0__VREFI_EN_MASK 0x4000
9212 #define MC_IO_PAD_CNTL_D0__VREFI_EN__SHIFT 0xe
9213 #define MC_IO_PAD_CNTL_D0__VREFI_SEL_MASK 0xf8000
9214 #define MC_IO_PAD_CNTL_D0__VREFI_SEL__SHIFT 0xf
9215 #define MC_IO_PAD_CNTL_D0__CK_AUTO_EN_MASK 0x100000
9216 #define MC_IO_PAD_CNTL_D0__CK_AUTO_EN__SHIFT 0x14
9217 #define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL_MASK 0x200000
9218 #define MC_IO_PAD_CNTL_D0__CK_DELAY_SEL__SHIFT 0x15
9219 #define MC_IO_PAD_CNTL_D0__CK_DELAY_N_MASK 0xc00000
9220 #define MC_IO_PAD_CNTL_D0__CK_DELAY_N__SHIFT 0x16
9221 #define MC_IO_PAD_CNTL_D0__CK_DELAY_P_MASK 0x3000000
9222 #define MC_IO_PAD_CNTL_D0__CK_DELAY_P__SHIFT 0x18
9223 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE_MASK 0x8000000
9224 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CKE__SHIFT 0x1b
9225 #define MC_IO_PAD_CNTL_D0__UNI_STR_MASK 0x10000000
9226 #define MC_IO_PAD_CNTL_D0__UNI_STR__SHIFT 0x1c
9227 #define MC_IO_PAD_CNTL_D0__DIFF_STR_MASK 0x20000000
9228 #define MC_IO_PAD_CNTL_D0__DIFF_STR__SHIFT 0x1d
9229 #define MC_IO_PAD_CNTL_D0__GDDR_PWRON_MASK 0x40000000
9230 #define MC_IO_PAD_CNTL_D0__GDDR_PWRON__SHIFT 0x1e
9231 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK_MASK 0x80000000
9232 #define MC_IO_PAD_CNTL_D0__TXPWROFF_CLK__SHIFT 0x1f
9233 #define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC_MASK 0x1
9234 #define MC_IO_PAD_CNTL_D1__DELAY_DATA_SYNC__SHIFT 0x0
9235 #define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC_MASK 0x2
9236 #define MC_IO_PAD_CNTL_D1__DELAY_STR_SYNC__SHIFT 0x1
9237 #define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC_MASK 0x4
9238 #define MC_IO_PAD_CNTL_D1__DELAY_CLK_SYNC__SHIFT 0x2
9239 #define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC_MASK 0x8
9240 #define MC_IO_PAD_CNTL_D1__DELAY_CMD_SYNC__SHIFT 0x3
9241 #define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC_MASK 0x10
9242 #define MC_IO_PAD_CNTL_D1__DELAY_ADR_SYNC__SHIFT 0x4
9243 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA_MASK 0x20
9244 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_DATA__SHIFT 0x5
9245 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR_MASK 0x40
9246 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_STR__SHIFT 0x6
9247 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK_MASK 0x80
9248 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CLK__SHIFT 0x7
9249 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD_MASK 0x100
9250 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_CMD__SHIFT 0x8
9251 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR_MASK 0x200
9252 #define MC_IO_PAD_CNTL_D1__MEM_FALL_OUT_ADR__SHIFT 0x9
9253 #define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR_MASK 0x400
9254 #define MC_IO_PAD_CNTL_D1__FORCE_EN_RD_STR__SHIFT 0xa
9255 #define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY_MASK 0x800
9256 #define MC_IO_PAD_CNTL_D1__EN_RD_STR_DLY__SHIFT 0xb
9257 #define MC_IO_PAD_CNTL_D1__DISABLE_CMD_MASK 0x1000
9258 #define MC_IO_PAD_CNTL_D1__DISABLE_CMD__SHIFT 0xc
9259 #define MC_IO_PAD_CNTL_D1__DISABLE_ADR_MASK 0x2000
9260 #define MC_IO_PAD_CNTL_D1__DISABLE_ADR__SHIFT 0xd
9261 #define MC_IO_PAD_CNTL_D1__VREFI_EN_MASK 0x4000
9262 #define MC_IO_PAD_CNTL_D1__VREFI_EN__SHIFT 0xe
9263 #define MC_IO_PAD_CNTL_D1__VREFI_SEL_MASK 0xf8000
9264 #define MC_IO_PAD_CNTL_D1__VREFI_SEL__SHIFT 0xf
9265 #define MC_IO_PAD_CNTL_D1__CK_AUTO_EN_MASK 0x100000
9266 #define MC_IO_PAD_CNTL_D1__CK_AUTO_EN__SHIFT 0x14
9267 #define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL_MASK 0x200000
9268 #define MC_IO_PAD_CNTL_D1__CK_DELAY_SEL__SHIFT 0x15
9269 #define MC_IO_PAD_CNTL_D1__CK_DELAY_N_MASK 0xc00000
9270 #define MC_IO_PAD_CNTL_D1__CK_DELAY_N__SHIFT 0x16
9271 #define MC_IO_PAD_CNTL_D1__CK_DELAY_P_MASK 0x3000000
9272 #define MC_IO_PAD_CNTL_D1__CK_DELAY_P__SHIFT 0x18
9273 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE_MASK 0x8000000
9274 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CKE__SHIFT 0x1b
9275 #define MC_IO_PAD_CNTL_D1__UNI_STR_MASK 0x10000000
9276 #define MC_IO_PAD_CNTL_D1__UNI_STR__SHIFT 0x1c
9277 #define MC_IO_PAD_CNTL_D1__DIFF_STR_MASK 0x20000000
9278 #define MC_IO_PAD_CNTL_D1__DIFF_STR__SHIFT 0x1d
9279 #define MC_IO_PAD_CNTL_D1__GDDR_PWRON_MASK 0x40000000
9280 #define MC_IO_PAD_CNTL_D1__GDDR_PWRON__SHIFT 0x1e
9281 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK_MASK 0x80000000
9282 #define MC_IO_PAD_CNTL_D1__TXPWROFF_CLK__SHIFT 0x1f
9283 #define MC_NPL_STATUS__D0_PDELAY_MASK 0x3
9284 #define MC_NPL_STATUS__D0_PDELAY__SHIFT 0x0
9285 #define MC_NPL_STATUS__D0_NDELAY_MASK 0xc
9286 #define MC_NPL_STATUS__D0_NDELAY__SHIFT 0x2
9287 #define MC_NPL_STATUS__D0_PEARLY_MASK 0x10
9288 #define MC_NPL_STATUS__D0_PEARLY__SHIFT 0x4
9289 #define MC_NPL_STATUS__D0_NEARLY_MASK 0x20
9290 #define MC_NPL_STATUS__D0_NEARLY__SHIFT 0x5
9291 #define MC_NPL_STATUS__D1_PDELAY_MASK 0xc0
9292 #define MC_NPL_STATUS__D1_PDELAY__SHIFT 0x6
9293 #define MC_NPL_STATUS__D1_NDELAY_MASK 0x300
9294 #define MC_NPL_STATUS__D1_NDELAY__SHIFT 0x8
9295 #define MC_NPL_STATUS__D1_PEARLY_MASK 0x400
9296 #define MC_NPL_STATUS__D1_PEARLY__SHIFT 0xa
9297 #define MC_NPL_STATUS__D1_NEARLY_MASK 0x800
9298 #define MC_NPL_STATUS__D1_NEARLY__SHIFT 0xb
9299 #define MC_BIST_CMD_CNTL__RESET_MASK 0x1
9300 #define MC_BIST_CMD_CNTL__RESET__SHIFT 0x0
9301 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_MASK 0x2
9302 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE__SHIFT 0x1
9303 #define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP_MASK 0x4
9304 #define MC_BIST_CMD_CNTL__CMD_ISSUE_LOOP__SHIFT 0x2
9305 #define MC_BIST_CMD_CNTL__LOOP_END_CONDITION_MASK 0x8
9306 #define MC_BIST_CMD_CNTL__LOOP_END_CONDITION__SHIFT 0x3
9307 #define MC_BIST_CMD_CNTL__LOOP_CNT_MAX_MASK 0xfff0
9308 #define MC_BIST_CMD_CNTL__LOOP_CNT_MAX__SHIFT 0x4
9309 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U_MASK 0x10000
9310 #define MC_BIST_CMD_CNTL__CMD_ISSUE_MODE_U__SHIFT 0x10
9311 #define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN_MASK 0x20000
9312 #define MC_BIST_CMD_CNTL__CMD_ISSUE_RUN__SHIFT 0x11
9313 #define MC_BIST_CMD_CNTL__LOOP_CNT_RD_MASK 0xffc0000
9314 #define MC_BIST_CMD_CNTL__LOOP_CNT_RD__SHIFT 0x12
9315 #define MC_BIST_CMD_CNTL__ENABLE_D0_MASK 0x10000000
9316 #define MC_BIST_CMD_CNTL__ENABLE_D0__SHIFT 0x1c
9317 #define MC_BIST_CMD_CNTL__ENABLE_D1_MASK 0x20000000
9318 #define MC_BIST_CMD_CNTL__ENABLE_D1__SHIFT 0x1d
9319 #define MC_BIST_CMD_CNTL__STATUS_CH_MASK 0x40000000
9320 #define MC_BIST_CMD_CNTL__STATUS_CH__SHIFT 0x1e
9321 #define MC_BIST_CMD_CNTL__DONE_MASK 0x80000000
9322 #define MC_BIST_CMD_CNTL__DONE__SHIFT 0x1f
9323 #define MC_BIST_CNTL__RESET_MASK 0x1
9324 #define MC_BIST_CNTL__RESET__SHIFT 0x0
9325 #define MC_BIST_CNTL__RUN_MASK 0x2
9326 #define MC_BIST_CNTL__RUN__SHIFT 0x1
9327 #define MC_BIST_CNTL__PTR_RST_D0_MASK 0x4
9328 #define MC_BIST_CNTL__PTR_RST_D0__SHIFT 0x2
9329 #define MC_BIST_CNTL__PTR_RST_D1_MASK 0x8
9330 #define MC_BIST_CNTL__PTR_RST_D1__SHIFT 0x3
9331 #define MC_BIST_CNTL__MOP_MODE_MASK 0x10
9332 #define MC_BIST_CNTL__MOP_MODE__SHIFT 0x4
9333 #define MC_BIST_CNTL__ADR_MODE_MASK 0x20
9334 #define MC_BIST_CNTL__ADR_MODE__SHIFT 0x5
9335 #define MC_BIST_CNTL__DAT_MODE_MASK 0x40
9336 #define MC_BIST_CNTL__DAT_MODE__SHIFT 0x6
9337 #define MC_BIST_CNTL__LOOP_MASK 0xc00
9338 #define MC_BIST_CNTL__LOOP__SHIFT 0xa
9339 #define MC_BIST_CNTL__ENABLE_D0_MASK 0x1000
9340 #define MC_BIST_CNTL__ENABLE_D0__SHIFT 0xc
9341 #define MC_BIST_CNTL__ENABLE_D1_MASK 0x2000
9342 #define MC_BIST_CNTL__ENABLE_D1__SHIFT 0xd
9343 #define MC_BIST_CNTL__LOAD_RTDATA_CH_MASK 0x4000
9344 #define MC_BIST_CNTL__LOAD_RTDATA_CH__SHIFT 0xe
9345 #define MC_BIST_CNTL__LOOP_CNT_MASK 0xfff0000
9346 #define MC_BIST_CNTL__LOOP_CNT__SHIFT 0x10
9347 #define MC_BIST_CNTL__DONE_MASK 0x40000000
9348 #define MC_BIST_CNTL__DONE__SHIFT 0x1e
9349 #define MC_BIST_CNTL__LOAD_RTDATA_MASK 0x80000000
9350 #define MC_BIST_CNTL__LOAD_RTDATA__SHIFT 0x1f
9351 #define MC_BIST_AUTO_CNTL__MOP_MASK 0x3
9352 #define MC_BIST_AUTO_CNTL__MOP__SHIFT 0x0
9353 #define MC_BIST_AUTO_CNTL__ADR_GEN_MASK 0xf0
9354 #define MC_BIST_AUTO_CNTL__ADR_GEN__SHIFT 0x4
9355 #define MC_BIST_AUTO_CNTL__LFSR_KEY_MASK 0xffff00
9356 #define MC_BIST_AUTO_CNTL__LFSR_KEY__SHIFT 0x8
9357 #define MC_BIST_AUTO_CNTL__LFSR_RESET_MASK 0x1000000
9358 #define MC_BIST_AUTO_CNTL__LFSR_RESET__SHIFT 0x18
9359 #define MC_BIST_AUTO_CNTL__ADR_RESET_MASK 0x2000000
9360 #define MC_BIST_AUTO_CNTL__ADR_RESET__SHIFT 0x19
9361 #define MC_BIST_DIR_CNTL__MOP_MASK 0x7
9362 #define MC_BIST_DIR_CNTL__MOP__SHIFT 0x0
9363 #define MC_BIST_DIR_CNTL__EOB_MASK 0x8
9364 #define MC_BIST_DIR_CNTL__EOB__SHIFT 0x3
9365 #define MC_BIST_DIR_CNTL__MOP_LOAD_MASK 0x10
9366 #define MC_BIST_DIR_CNTL__MOP_LOAD__SHIFT 0x4
9367 #define MC_BIST_DIR_CNTL__DATA_LOAD_MASK 0x20
9368 #define MC_BIST_DIR_CNTL__DATA_LOAD__SHIFT 0x5
9369 #define MC_BIST_DIR_CNTL__CMD_RTR_D0_MASK 0x40
9370 #define MC_BIST_DIR_CNTL__CMD_RTR_D0__SHIFT 0x6
9371 #define MC_BIST_DIR_CNTL__DAT_RTR_D0_MASK 0x80
9372 #define MC_BIST_DIR_CNTL__DAT_RTR_D0__SHIFT 0x7
9373 #define MC_BIST_DIR_CNTL__CMD_RTR_D1_MASK 0x100
9374 #define MC_BIST_DIR_CNTL__CMD_RTR_D1__SHIFT 0x8
9375 #define MC_BIST_DIR_CNTL__DAT_RTR_D1_MASK 0x200
9376 #define MC_BIST_DIR_CNTL__DAT_RTR_D1__SHIFT 0x9
9377 #define MC_BIST_DIR_CNTL__MOP3_MASK 0x400
9378 #define MC_BIST_DIR_CNTL__MOP3__SHIFT 0xa
9379 #define MC_BIST_SADDR__COL_MASK 0x3ff
9380 #define MC_BIST_SADDR__COL__SHIFT 0x0
9381 #define MC_BIST_SADDR__ROW_MASK 0xfffc00
9382 #define MC_BIST_SADDR__ROW__SHIFT 0xa
9383 #define MC_BIST_SADDR__BANK_MASK 0xf000000
9384 #define MC_BIST_SADDR__BANK__SHIFT 0x18
9385 #define MC_BIST_SADDR__RANK_MASK 0x10000000
9386 #define MC_BIST_SADDR__RANK__SHIFT 0x1c
9387 #define MC_BIST_SADDR__COLH_MASK 0x20000000
9388 #define MC_BIST_SADDR__COLH__SHIFT 0x1d
9389 #define MC_BIST_SADDR__ROWH_MASK 0xc0000000
9390 #define MC_BIST_SADDR__ROWH__SHIFT 0x1e
9391 #define MC_BIST_EADDR__COL_MASK 0x3ff
9392 #define MC_BIST_EADDR__COL__SHIFT 0x0
9393 #define MC_BIST_EADDR__ROW_MASK 0xfffc00
9394 #define MC_BIST_EADDR__ROW__SHIFT 0xa
9395 #define MC_BIST_EADDR__BANK_MASK 0xf000000
9396 #define MC_BIST_EADDR__BANK__SHIFT 0x18
9397 #define MC_BIST_EADDR__RANK_MASK 0x10000000
9398 #define MC_BIST_EADDR__RANK__SHIFT 0x1c
9399 #define MC_BIST_EADDR__COLH_MASK 0x20000000
9400 #define MC_BIST_EADDR__COLH__SHIFT 0x1d
9401 #define MC_BIST_EADDR__ROWH_MASK 0xc0000000
9402 #define MC_BIST_EADDR__ROWH__SHIFT 0x1e
9403 #define MC_BIST_CMP_CNTL__CMP_MASK_BYTE_MASK 0xf
9404 #define MC_BIST_CMP_CNTL__CMP_MASK_BYTE__SHIFT 0x0
9405 #define MC_BIST_CMP_CNTL__CMP_MASK_BIT_MASK 0xff0
9406 #define MC_BIST_CMP_CNTL__CMP_MASK_BIT__SHIFT 0x4
9407 #define MC_BIST_CMP_CNTL__LOAD_RTEDC_MASK 0x1000
9408 #define MC_BIST_CMP_CNTL__LOAD_RTEDC__SHIFT 0xc
9409 #define MC_BIST_CMP_CNTL__DATA_STORE_SEL_MASK 0x2000
9410 #define MC_BIST_CMP_CNTL__DATA_STORE_SEL__SHIFT 0xd
9411 #define MC_BIST_CMP_CNTL__EDC_STORE_SEL_MASK 0x4000
9412 #define MC_BIST_CMP_CNTL__EDC_STORE_SEL__SHIFT 0xe
9413 #define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO_MASK 0x8000
9414 #define MC_BIST_CMP_CNTL__ENABLE_CMD_FIFO__SHIFT 0xf
9415 #define MC_BIST_CMP_CNTL__CMP_MASK 0x30000
9416 #define MC_BIST_CMP_CNTL__CMP__SHIFT 0x10
9417 #define MC_BIST_CMP_CNTL__DAT_MODE_MASK 0x40000
9418 #define MC_BIST_CMP_CNTL__DAT_MODE__SHIFT 0x12
9419 #define MC_BIST_CMP_CNTL__EDC_STORE_MODE_MASK 0x80000
9420 #define MC_BIST_CMP_CNTL__EDC_STORE_MODE__SHIFT 0x13
9421 #define MC_BIST_CMP_CNTL__DATA_STORE_MODE_MASK 0x300000
9422 #define MC_BIST_CMP_CNTL__DATA_STORE_MODE__SHIFT 0x14
9423 #define MC_BIST_CMP_CNTL__MISMATCH_CNT_MASK 0xffc00000
9424 #define MC_BIST_CMP_CNTL__MISMATCH_CNT__SHIFT 0x16
9425 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_MASK 0x1f
9426 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT__SHIFT 0x0
9427 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST_MASK 0x100
9428 #define MC_BIST_CMP_CNTL_2__DATA_STORE_CNT_RST__SHIFT 0x8
9429 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_MASK 0x1f000
9430 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT__SHIFT 0xc
9431 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST_MASK 0x100000
9432 #define MC_BIST_CMP_CNTL_2__EDC_STORE_CNT_RST__SHIFT 0x14
9433 #define MC_BIST_DATA_WORD0__DATA_MASK 0xffffffff
9434 #define MC_BIST_DATA_WORD0__DATA__SHIFT 0x0
9435 #define MC_BIST_DATA_WORD1__DATA_MASK 0xffffffff
9436 #define MC_BIST_DATA_WORD1__DATA__SHIFT 0x0
9437 #define MC_BIST_DATA_WORD2__DATA_MASK 0xffffffff
9438 #define MC_BIST_DATA_WORD2__DATA__SHIFT 0x0
9439 #define MC_BIST_DATA_WORD3__DATA_MASK 0xffffffff
9440 #define MC_BIST_DATA_WORD3__DATA__SHIFT 0x0
9441 #define MC_BIST_DATA_WORD4__DATA_MASK 0xffffffff
9442 #define MC_BIST_DATA_WORD4__DATA__SHIFT 0x0
9443 #define MC_BIST_DATA_WORD5__DATA_MASK 0xffffffff
9444 #define MC_BIST_DATA_WORD5__DATA__SHIFT 0x0
9445 #define MC_BIST_DATA_WORD6__DATA_MASK 0xffffffff
9446 #define MC_BIST_DATA_WORD6__DATA__SHIFT 0x0
9447 #define MC_BIST_DATA_WORD7__DATA_MASK 0xffffffff
9448 #define MC_BIST_DATA_WORD7__DATA__SHIFT 0x0
9449 #define MC_BIST_DATA_MASK__MASK_MASK 0xffffffff
9450 #define MC_BIST_DATA_MASK__MASK__SHIFT 0x0
9451 #define MC_BIST_MISMATCH_ADDR__COL_MASK 0x3ff
9452 #define MC_BIST_MISMATCH_ADDR__COL__SHIFT 0x0
9453 #define MC_BIST_MISMATCH_ADDR__ROW_MASK 0xfffc00
9454 #define MC_BIST_MISMATCH_ADDR__ROW__SHIFT 0xa
9455 #define MC_BIST_MISMATCH_ADDR__BANK_MASK 0xf000000
9456 #define MC_BIST_MISMATCH_ADDR__BANK__SHIFT 0x18
9457 #define MC_BIST_MISMATCH_ADDR__RANK_MASK 0x10000000
9458 #define MC_BIST_MISMATCH_ADDR__RANK__SHIFT 0x1c
9459 #define MC_BIST_MISMATCH_ADDR__COLH_MASK 0x20000000
9460 #define MC_BIST_MISMATCH_ADDR__COLH__SHIFT 0x1d
9461 #define MC_BIST_MISMATCH_ADDR__ROWH_MASK 0xc0000000
9462 #define MC_BIST_MISMATCH_ADDR__ROWH__SHIFT 0x1e
9463 #define MC_BIST_RDATA_WORD0__RDATA_MASK 0xffffffff
9464 #define MC_BIST_RDATA_WORD0__RDATA__SHIFT 0x0
9465 #define MC_BIST_RDATA_WORD1__RDATA_MASK 0xffffffff
9466 #define MC_BIST_RDATA_WORD1__RDATA__SHIFT 0x0
9467 #define MC_BIST_RDATA_WORD2__RDATA_MASK 0xffffffff
9468 #define MC_BIST_RDATA_WORD2__RDATA__SHIFT 0x0
9469 #define MC_BIST_RDATA_WORD3__RDATA_MASK 0xffffffff
9470 #define MC_BIST_RDATA_WORD3__RDATA__SHIFT 0x0
9471 #define MC_BIST_RDATA_WORD4__RDATA_MASK 0xffffffff
9472 #define MC_BIST_RDATA_WORD4__RDATA__SHIFT 0x0
9473 #define MC_BIST_RDATA_WORD5__RDATA_MASK 0xffffffff
9474 #define MC_BIST_RDATA_WORD5__RDATA__SHIFT 0x0
9475 #define MC_BIST_RDATA_WORD6__RDATA_MASK 0xffffffff
9476 #define MC_BIST_RDATA_WORD6__RDATA__SHIFT 0x0
9477 #define MC_BIST_RDATA_WORD7__RDATA_MASK 0xffffffff
9478 #define MC_BIST_RDATA_WORD7__RDATA__SHIFT 0x0
9479 #define MC_BIST_RDATA_MASK__MASK_MASK 0xffffffff
9480 #define MC_BIST_RDATA_MASK__MASK__SHIFT 0x0
9481 #define MC_BIST_RDATA_EDC__EDC_MASK 0xffffffff
9482 #define MC_BIST_RDATA_EDC__EDC__SHIFT 0x0
9483 #define MC_SEQ_PERF_CNTL__MONITOR_PERIOD_MASK 0x3fffffff
9484 #define MC_SEQ_PERF_CNTL__MONITOR_PERIOD__SHIFT 0x0
9485 #define MC_SEQ_PERF_CNTL__CNTL_MASK 0xc0000000
9486 #define MC_SEQ_PERF_CNTL__CNTL__SHIFT 0x1e
9487 #define MC_SEQ_PERF_CNTL_1__PAUSE_MASK 0x1
9488 #define MC_SEQ_PERF_CNTL_1__PAUSE__SHIFT 0x0
9489 #define MC_SEQ_PERF_CNTL_1__SEL_A_MSB_MASK 0x100
9490 #define MC_SEQ_PERF_CNTL_1__SEL_A_MSB__SHIFT 0x8
9491 #define MC_SEQ_PERF_CNTL_1__SEL_B_MSB_MASK 0x200
9492 #define MC_SEQ_PERF_CNTL_1__SEL_B_MSB__SHIFT 0x9
9493 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB_MASK 0x400
9494 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_C_MSB__SHIFT 0xa
9495 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB_MASK 0x800
9496 #define MC_SEQ_PERF_CNTL_1__SEL_CH0_D_MSB__SHIFT 0xb
9497 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB_MASK 0x1000
9498 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_A_MSB__SHIFT 0xc
9499 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB_MASK 0x2000
9500 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_B_MSB__SHIFT 0xd
9501 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB_MASK 0x4000
9502 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_C_MSB__SHIFT 0xe
9503 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB_MASK 0x8000
9504 #define MC_SEQ_PERF_CNTL_1__SEL_CH1_D_MSB__SHIFT 0xf
9505 #define MC_SEQ_PERF_SEQ_CTL__SEL_A_MASK 0xf
9506 #define MC_SEQ_PERF_SEQ_CTL__SEL_A__SHIFT 0x0
9507 #define MC_SEQ_PERF_SEQ_CTL__SEL_B_MASK 0xf0
9508 #define MC_SEQ_PERF_SEQ_CTL__SEL_B__SHIFT 0x4
9509 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C_MASK 0xf00
9510 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_C__SHIFT 0x8
9511 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D_MASK 0xf000
9512 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH0_D__SHIFT 0xc
9513 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A_MASK 0xf0000
9514 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_A__SHIFT 0x10
9515 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B_MASK 0xf00000
9516 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_B__SHIFT 0x14
9517 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C_MASK 0xf000000
9518 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_C__SHIFT 0x18
9519 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D_MASK 0xf0000000
9520 #define MC_SEQ_PERF_SEQ_CTL__SEL_CH1_D__SHIFT 0x1c
9521 #define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE_MASK 0xffffffff
9522 #define MC_SEQ_PERF_SEQ_CNT_A_I0__VALUE__SHIFT 0x0
9523 #define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE_MASK 0xffffffff
9524 #define MC_SEQ_PERF_SEQ_CNT_A_I1__VALUE__SHIFT 0x0
9525 #define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE_MASK 0xffffffff
9526 #define MC_SEQ_PERF_SEQ_CNT_B_I0__VALUE__SHIFT 0x0
9527 #define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE_MASK 0xffffffff
9528 #define MC_SEQ_PERF_SEQ_CNT_B_I1__VALUE__SHIFT 0x0
9529 #define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE_MASK 0xffffffff
9530 #define MC_SEQ_PERF_SEQ_CNT_C_I0__VALUE__SHIFT 0x0
9531 #define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE_MASK 0xffffffff
9532 #define MC_SEQ_PERF_SEQ_CNT_C_I1__VALUE__SHIFT 0x0
9533 #define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE_MASK 0xffffffff
9534 #define MC_SEQ_PERF_SEQ_CNT_D_I0__VALUE__SHIFT 0x0
9535 #define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE_MASK 0xffffffff
9536 #define MC_SEQ_PERF_SEQ_CNT_D_I1__VALUE__SHIFT 0x0
9537 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D0_MASK 0x1
9538 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D0__SHIFT 0x0
9539 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D1_MASK 0x2
9540 #define MC_SEQ_STATUS_M__PWRUP_COMPL_D1__SHIFT 0x1
9541 #define MC_SEQ_STATUS_M__CMD_RDY_D0_MASK 0x4
9542 #define MC_SEQ_STATUS_M__CMD_RDY_D0__SHIFT 0x2
9543 #define MC_SEQ_STATUS_M__CMD_RDY_D1_MASK 0x8
9544 #define MC_SEQ_STATUS_M__CMD_RDY_D1__SHIFT 0x3
9545 #define MC_SEQ_STATUS_M__SLF_D0_MASK 0x10
9546 #define MC_SEQ_STATUS_M__SLF_D0__SHIFT 0x4
9547 #define MC_SEQ_STATUS_M__SLF_D1_MASK 0x20
9548 #define MC_SEQ_STATUS_M__SLF_D1__SHIFT 0x5
9549 #define MC_SEQ_STATUS_M__SS_SLF_D0_MASK 0x40
9550 #define MC_SEQ_STATUS_M__SS_SLF_D0__SHIFT 0x6
9551 #define MC_SEQ_STATUS_M__SS_SLF_D1_MASK 0x80
9552 #define MC_SEQ_STATUS_M__SS_SLF_D1__SHIFT 0x7
9553 #define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY_MASK 0x100
9554 #define MC_SEQ_STATUS_M__SEQ0_ARB_CMD_FIFO_EMPTY__SHIFT 0x8
9555 #define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY_MASK 0x200
9556 #define MC_SEQ_STATUS_M__SEQ1_ARB_CMD_FIFO_EMPTY__SHIFT 0x9
9557 #define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL_MASK 0x1000
9558 #define MC_SEQ_STATUS_M__SEQ0_RS_DATA_FIFO_FULL__SHIFT 0xc
9559 #define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL_MASK 0x2000
9560 #define MC_SEQ_STATUS_M__SEQ1_RS_DATA_FIFO_FULL__SHIFT 0xd
9561 #define MC_SEQ_STATUS_M__SEQ0_BUSY_MASK 0x4000
9562 #define MC_SEQ_STATUS_M__SEQ0_BUSY__SHIFT 0xe
9563 #define MC_SEQ_STATUS_M__SEQ1_BUSY_MASK 0x8000
9564 #define MC_SEQ_STATUS_M__SEQ1_BUSY__SHIFT 0xf
9565 #define MC_SEQ_STATUS_M__PMG_PWRSTATE_MASK 0x10000
9566 #define MC_SEQ_STATUS_M__PMG_PWRSTATE__SHIFT 0x10
9567 #define MC_SEQ_STATUS_M__PMG_FSMSTATE_MASK 0x1f00000
9568 #define MC_SEQ_STATUS_M__PMG_FSMSTATE__SHIFT 0x14
9569 #define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS_MASK 0x2000000
9570 #define MC_SEQ_STATUS_M__SEQ0_BUSY_HYS__SHIFT 0x19
9571 #define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS_MASK 0x4000000
9572 #define MC_SEQ_STATUS_M__SEQ1_BUSY_HYS__SHIFT 0x1a
9573 #define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP_MASK 0x8000000
9574 #define MC_SEQ_STATUS_M__SEQ0_ALLOWSTOP__SHIFT 0x1b
9575 #define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP_MASK 0x10000000
9576 #define MC_SEQ_STATUS_M__SEQ1_ALLOWSTOP__SHIFT 0x1c
9577 #define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL_MASK 0x1
9578 #define MC_SEQ_STATUS_S__SEQ0_ARB_DATA_FIFO_FULL__SHIFT 0x0
9579 #define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL_MASK 0x2
9580 #define MC_SEQ_STATUS_S__SEQ1_ARB_DATA_FIFO_FULL__SHIFT 0x1
9581 #define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL_MASK 0x10
9582 #define MC_SEQ_STATUS_S__SEQ0_ARB_CMD_FIFO_FULL__SHIFT 0x4
9583 #define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL_MASK 0x20
9584 #define MC_SEQ_STATUS_S__SEQ1_ARB_CMD_FIFO_FULL__SHIFT 0x5
9585 #define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY_MASK 0x100
9586 #define MC_SEQ_STATUS_S__SEQ0_RS_DATA_FIFO_EMPTY__SHIFT 0x8
9587 #define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY_MASK 0x200
9588 #define MC_SEQ_STATUS_S__SEQ1_RS_DATA_FIFO_EMPTY__SHIFT 0x9
9589 #define MC_CG_DATAPORT__DATA_FIELD_MASK 0xffffffff
9590 #define MC_CG_DATAPORT__DATA_FIELD__SHIFT 0x0
9591 #define MC_SEQ_VENDOR_ID_I0__VALUE_MASK 0xffffffff
9592 #define MC_SEQ_VENDOR_ID_I0__VALUE__SHIFT 0x0
9593 #define MC_SEQ_VENDOR_ID_I1__VALUE_MASK 0xffffffff
9594 #define MC_SEQ_VENDOR_ID_I1__VALUE__SHIFT 0x0
9595 #define MC_SEQ_MISC0__VALUE_MASK 0xffffffff
9596 #define MC_SEQ_MISC0__VALUE__SHIFT 0x0
9597 #define MC_SEQ_MISC1__VALUE_MASK 0xffffffff
9598 #define MC_SEQ_MISC1__VALUE__SHIFT 0x0
9599 #define MC_SEQ_RESERVE_0_S__SCLK_FIELD_MASK 0xffffffff
9600 #define MC_SEQ_RESERVE_0_S__SCLK_FIELD__SHIFT 0x0
9601 #define MC_SEQ_RESERVE_1_S__SCLK_FIELD_MASK 0xffffffff
9602 #define MC_SEQ_RESERVE_1_S__SCLK_FIELD__SHIFT 0x0
9603 #define MC_SEQ_RESERVE_M__MCLK_FIELD_MASK 0xffffffff
9604 #define MC_SEQ_RESERVE_M__MCLK_FIELD__SHIFT 0x0
9605 #define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV_MASK 0xfff
9606 #define MC_SEQ_IO_RESERVE_D0__DPHY0_RSV__SHIFT 0x0
9607 #define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV_MASK 0xfff000
9608 #define MC_SEQ_IO_RESERVE_D0__DPHY1_RSV__SHIFT 0xc
9609 #define MC_SEQ_IO_RESERVE_D0__APHY_RSV_MASK 0xff000000
9610 #define MC_SEQ_IO_RESERVE_D0__APHY_RSV__SHIFT 0x18
9611 #define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV_MASK 0xfff
9612 #define MC_SEQ_IO_RESERVE_D1__DPHY0_RSV__SHIFT 0x0
9613 #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV_MASK 0xfff000
9614 #define MC_SEQ_IO_RESERVE_D1__DPHY1_RSV__SHIFT 0xc
9615 #define MC_SEQ_IO_RESERVE_D1__APHY_RSV_MASK 0xff000000
9616 #define MC_SEQ_IO_RESERVE_D1__APHY_RSV__SHIFT 0x18
9617 #define MC_SEQ_SUP_CNTL__RUN_MASK 0x1
9618 #define MC_SEQ_SUP_CNTL__RUN__SHIFT 0x0
9619 #define MC_SEQ_SUP_CNTL__SINGLE_STEP_MASK 0x2
9620 #define MC_SEQ_SUP_CNTL__SINGLE_STEP__SHIFT 0x1
9621 #define MC_SEQ_SUP_CNTL__SW_WAKE_MASK 0x4
9622 #define MC_SEQ_SUP_CNTL__SW_WAKE__SHIFT 0x2
9623 #define MC_SEQ_SUP_CNTL__RESET_PC_MASK 0x8
9624 #define MC_SEQ_SUP_CNTL__RESET_PC__SHIFT 0x3
9625 #define MC_SEQ_SUP_CNTL__PGM_WRITE_MASK 0x10
9626 #define MC_SEQ_SUP_CNTL__PGM_WRITE__SHIFT 0x4
9627 #define MC_SEQ_SUP_CNTL__PGM_READ_MASK 0x20
9628 #define MC_SEQ_SUP_CNTL__PGM_READ__SHIFT 0x5
9629 #define MC_SEQ_SUP_CNTL__FAST_WRITE_MASK 0x40
9630 #define MC_SEQ_SUP_CNTL__FAST_WRITE__SHIFT 0x6
9631 #define MC_SEQ_SUP_CNTL__BKPT_CLEAR_MASK 0x80
9632 #define MC_SEQ_SUP_CNTL__BKPT_CLEAR__SHIFT 0x7
9633 #define MC_SEQ_SUP_CNTL__PGM_CHKSUM_MASK 0xff800000
9634 #define MC_SEQ_SUP_CNTL__PGM_CHKSUM__SHIFT 0x17
9635 #define MC_SEQ_SUP_PGM__CNTL_MASK 0xffffffff
9636 #define MC_SEQ_SUP_PGM__CNTL__SHIFT 0x0
9637 #define MC_SEQ_SUP_GP0_STAT__STATUS_MASK 0xffffffff
9638 #define MC_SEQ_SUP_GP0_STAT__STATUS__SHIFT 0x0
9639 #define MC_SEQ_SUP_GP1_STAT__STATUS_MASK 0xffffffff
9640 #define MC_SEQ_SUP_GP1_STAT__STATUS__SHIFT 0x0
9641 #define MC_SEQ_SUP_GP2_STAT__STATUS_MASK 0xffffffff
9642 #define MC_SEQ_SUP_GP2_STAT__STATUS__SHIFT 0x0
9643 #define MC_SEQ_SUP_GP3_STAT__STATUS_MASK 0xffffffff
9644 #define MC_SEQ_SUP_GP3_STAT__STATUS__SHIFT 0x0
9645 #define MC_SEQ_SUP_IR_STAT__STATUS_MASK 0xffffffff
9646 #define MC_SEQ_SUP_IR_STAT__STATUS__SHIFT 0x0
9647 #define MC_SEQ_SUP_DEC_STAT__STATUS_MASK 0xffffffff
9648 #define MC_SEQ_SUP_DEC_STAT__STATUS__SHIFT 0x0
9649 #define MC_SEQ_SUP_PGM_STAT__STATUS_MASK 0xffffffff
9650 #define MC_SEQ_SUP_PGM_STAT__STATUS__SHIFT 0x0
9651 #define MC_SEQ_SUP_R_PGM__PGM_MASK 0xffffffff
9652 #define MC_SEQ_SUP_R_PGM__PGM__SHIFT 0x0
9653 #define MC_SEQ_MISC3__VALUE_MASK 0xffffffff
9654 #define MC_SEQ_MISC3__VALUE__SHIFT 0x0
9655 #define MC_SEQ_MISC4__VALUE_MASK 0xffffffff
9656 #define MC_SEQ_MISC4__VALUE__SHIFT 0x0
9657 #define MC_SEQ_MISC5__VALUE_MASK 0xffffffff
9658 #define MC_SEQ_MISC5__VALUE__SHIFT 0x0
9659 #define MC_SEQ_MISC6__VALUE_MASK 0xffffffff
9660 #define MC_SEQ_MISC6__VALUE__SHIFT 0x0
9661 #define MC_SEQ_MISC7__VALUE_MASK 0xffffffff
9662 #define MC_SEQ_MISC7__VALUE__SHIFT 0x0
9663 #define MC_SEQ_MISC8__VALUE_MASK 0xffffffff
9664 #define MC_SEQ_MISC8__VALUE__SHIFT 0x0
9665 #define MC_SEQ_MISC9__VALUE_MASK 0xffffffff
9666 #define MC_SEQ_MISC9__VALUE__SHIFT 0x0
9667 #define MC_SEQ_CG__CG_SEQ_REQ_MASK 0xff
9668 #define MC_SEQ_CG__CG_SEQ_REQ__SHIFT 0x0
9669 #define MC_SEQ_CG__CG_SEQ_RESP_MASK 0xff00
9670 #define MC_SEQ_CG__CG_SEQ_RESP__SHIFT 0x8
9671 #define MC_SEQ_CG__SEQ_CG_REQ_MASK 0xff0000
9672 #define MC_SEQ_CG__SEQ_CG_REQ__SHIFT 0x10
9673 #define MC_SEQ_CG__SEQ_CG_RESP_MASK 0xff000000
9674 #define MC_SEQ_CG__SEQ_CG_RESP__SHIFT 0x18
9675 #define MC_SEQ_BYTE_REMAP_D0__BYTE0_MASK 0x3
9676 #define MC_SEQ_BYTE_REMAP_D0__BYTE0__SHIFT 0x0
9677 #define MC_SEQ_BYTE_REMAP_D0__BYTE1_MASK 0xc
9678 #define MC_SEQ_BYTE_REMAP_D0__BYTE1__SHIFT 0x2
9679 #define MC_SEQ_BYTE_REMAP_D0__BYTE2_MASK 0x30
9680 #define MC_SEQ_BYTE_REMAP_D0__BYTE2__SHIFT 0x4
9681 #define MC_SEQ_BYTE_REMAP_D0__BYTE3_MASK 0xc0
9682 #define MC_SEQ_BYTE_REMAP_D0__BYTE3__SHIFT 0x6
9683 #define MC_SEQ_BYTE_REMAP_D1__BYTE0_MASK 0x3
9684 #define MC_SEQ_BYTE_REMAP_D1__BYTE0__SHIFT 0x0
9685 #define MC_SEQ_BYTE_REMAP_D1__BYTE1_MASK 0xc
9686 #define MC_SEQ_BYTE_REMAP_D1__BYTE1__SHIFT 0x2
9687 #define MC_SEQ_BYTE_REMAP_D1__BYTE2_MASK 0x30
9688 #define MC_SEQ_BYTE_REMAP_D1__BYTE2__SHIFT 0x4
9689 #define MC_SEQ_BYTE_REMAP_D1__BYTE3_MASK 0xc0
9690 #define MC_SEQ_BYTE_REMAP_D1__BYTE3__SHIFT 0x6
9691 #define MC_SEQ_BIT_REMAP_B0_D0__BIT0_MASK 0x7
9692 #define MC_SEQ_BIT_REMAP_B0_D0__BIT0__SHIFT 0x0
9693 #define MC_SEQ_BIT_REMAP_B0_D0__BIT1_MASK 0x38
9694 #define MC_SEQ_BIT_REMAP_B0_D0__BIT1__SHIFT 0x3
9695 #define MC_SEQ_BIT_REMAP_B0_D0__BIT2_MASK 0x1c0
9696 #define MC_SEQ_BIT_REMAP_B0_D0__BIT2__SHIFT 0x6
9697 #define MC_SEQ_BIT_REMAP_B0_D0__BIT3_MASK 0xe00
9698 #define MC_SEQ_BIT_REMAP_B0_D0__BIT3__SHIFT 0x9
9699 #define MC_SEQ_BIT_REMAP_B0_D0__BIT4_MASK 0x7000
9700 #define MC_SEQ_BIT_REMAP_B0_D0__BIT4__SHIFT 0xc
9701 #define MC_SEQ_BIT_REMAP_B0_D0__BIT5_MASK 0x38000
9702 #define MC_SEQ_BIT_REMAP_B0_D0__BIT5__SHIFT 0xf
9703 #define MC_SEQ_BIT_REMAP_B0_D0__BIT6_MASK 0x1c0000
9704 #define MC_SEQ_BIT_REMAP_B0_D0__BIT6__SHIFT 0x12
9705 #define MC_SEQ_BIT_REMAP_B0_D0__BIT7_MASK 0xe00000
9706 #define MC_SEQ_BIT_REMAP_B0_D0__BIT7__SHIFT 0x15
9707 #define MC_SEQ_BIT_REMAP_B1_D0__BIT0_MASK 0x7
9708 #define MC_SEQ_BIT_REMAP_B1_D0__BIT0__SHIFT 0x0
9709 #define MC_SEQ_BIT_REMAP_B1_D0__BIT1_MASK 0x38
9710 #define MC_SEQ_BIT_REMAP_B1_D0__BIT1__SHIFT 0x3
9711 #define MC_SEQ_BIT_REMAP_B1_D0__BIT2_MASK 0x1c0
9712 #define MC_SEQ_BIT_REMAP_B1_D0__BIT2__SHIFT 0x6
9713 #define MC_SEQ_BIT_REMAP_B1_D0__BIT3_MASK 0xe00
9714 #define MC_SEQ_BIT_REMAP_B1_D0__BIT3__SHIFT 0x9
9715 #define MC_SEQ_BIT_REMAP_B1_D0__BIT4_MASK 0x7000
9716 #define MC_SEQ_BIT_REMAP_B1_D0__BIT4__SHIFT 0xc
9717 #define MC_SEQ_BIT_REMAP_B1_D0__BIT5_MASK 0x38000
9718 #define MC_SEQ_BIT_REMAP_B1_D0__BIT5__SHIFT 0xf
9719 #define MC_SEQ_BIT_REMAP_B1_D0__BIT6_MASK 0x1c0000
9720 #define MC_SEQ_BIT_REMAP_B1_D0__BIT6__SHIFT 0x12
9721 #define MC_SEQ_BIT_REMAP_B1_D0__BIT7_MASK 0xe00000
9722 #define MC_SEQ_BIT_REMAP_B1_D0__BIT7__SHIFT 0x15
9723 #define MC_SEQ_BIT_REMAP_B2_D0__BIT0_MASK 0x7
9724 #define MC_SEQ_BIT_REMAP_B2_D0__BIT0__SHIFT 0x0
9725 #define MC_SEQ_BIT_REMAP_B2_D0__BIT1_MASK 0x38
9726 #define MC_SEQ_BIT_REMAP_B2_D0__BIT1__SHIFT 0x3
9727 #define MC_SEQ_BIT_REMAP_B2_D0__BIT2_MASK 0x1c0
9728 #define MC_SEQ_BIT_REMAP_B2_D0__BIT2__SHIFT 0x6
9729 #define MC_SEQ_BIT_REMAP_B2_D0__BIT3_MASK 0xe00
9730 #define MC_SEQ_BIT_REMAP_B2_D0__BIT3__SHIFT 0x9
9731 #define MC_SEQ_BIT_REMAP_B2_D0__BIT4_MASK 0x7000
9732 #define MC_SEQ_BIT_REMAP_B2_D0__BIT4__SHIFT 0xc
9733 #define MC_SEQ_BIT_REMAP_B2_D0__BIT5_MASK 0x38000
9734 #define MC_SEQ_BIT_REMAP_B2_D0__BIT5__SHIFT 0xf
9735 #define MC_SEQ_BIT_REMAP_B2_D0__BIT6_MASK 0x1c0000
9736 #define MC_SEQ_BIT_REMAP_B2_D0__BIT6__SHIFT 0x12
9737 #define MC_SEQ_BIT_REMAP_B2_D0__BIT7_MASK 0xe00000
9738 #define MC_SEQ_BIT_REMAP_B2_D0__BIT7__SHIFT 0x15
9739 #define MC_SEQ_BIT_REMAP_B3_D0__BIT0_MASK 0x7
9740 #define MC_SEQ_BIT_REMAP_B3_D0__BIT0__SHIFT 0x0
9741 #define MC_SEQ_BIT_REMAP_B3_D0__BIT1_MASK 0x38
9742 #define MC_SEQ_BIT_REMAP_B3_D0__BIT1__SHIFT 0x3
9743 #define MC_SEQ_BIT_REMAP_B3_D0__BIT2_MASK 0x1c0
9744 #define MC_SEQ_BIT_REMAP_B3_D0__BIT2__SHIFT 0x6
9745 #define MC_SEQ_BIT_REMAP_B3_D0__BIT3_MASK 0xe00
9746 #define MC_SEQ_BIT_REMAP_B3_D0__BIT3__SHIFT 0x9
9747 #define MC_SEQ_BIT_REMAP_B3_D0__BIT4_MASK 0x7000
9748 #define MC_SEQ_BIT_REMAP_B3_D0__BIT4__SHIFT 0xc
9749 #define MC_SEQ_BIT_REMAP_B3_D0__BIT5_MASK 0x38000
9750 #define MC_SEQ_BIT_REMAP_B3_D0__BIT5__SHIFT 0xf
9751 #define MC_SEQ_BIT_REMAP_B3_D0__BIT6_MASK 0x1c0000
9752 #define MC_SEQ_BIT_REMAP_B3_D0__BIT6__SHIFT 0x12
9753 #define MC_SEQ_BIT_REMAP_B3_D0__BIT7_MASK 0xe00000
9754 #define MC_SEQ_BIT_REMAP_B3_D0__BIT7__SHIFT 0x15
9755 #define MC_SEQ_BIT_REMAP_B0_D1__BIT0_MASK 0x7
9756 #define MC_SEQ_BIT_REMAP_B0_D1__BIT0__SHIFT 0x0
9757 #define MC_SEQ_BIT_REMAP_B0_D1__BIT1_MASK 0x38
9758 #define MC_SEQ_BIT_REMAP_B0_D1__BIT1__SHIFT 0x3
9759 #define MC_SEQ_BIT_REMAP_B0_D1__BIT2_MASK 0x1c0
9760 #define MC_SEQ_BIT_REMAP_B0_D1__BIT2__SHIFT 0x6
9761 #define MC_SEQ_BIT_REMAP_B0_D1__BIT3_MASK 0xe00
9762 #define MC_SEQ_BIT_REMAP_B0_D1__BIT3__SHIFT 0x9
9763 #define MC_SEQ_BIT_REMAP_B0_D1__BIT4_MASK 0x7000
9764 #define MC_SEQ_BIT_REMAP_B0_D1__BIT4__SHIFT 0xc
9765 #define MC_SEQ_BIT_REMAP_B0_D1__BIT5_MASK 0x38000
9766 #define MC_SEQ_BIT_REMAP_B0_D1__BIT5__SHIFT 0xf
9767 #define MC_SEQ_BIT_REMAP_B0_D1__BIT6_MASK 0x1c0000
9768 #define MC_SEQ_BIT_REMAP_B0_D1__BIT6__SHIFT 0x12
9769 #define MC_SEQ_BIT_REMAP_B0_D1__BIT7_MASK 0xe00000
9770 #define MC_SEQ_BIT_REMAP_B0_D1__BIT7__SHIFT 0x15
9771 #define MC_SEQ_BIT_REMAP_B1_D1__BIT0_MASK 0x7
9772 #define MC_SEQ_BIT_REMAP_B1_D1__BIT0__SHIFT 0x0
9773 #define MC_SEQ_BIT_REMAP_B1_D1__BIT1_MASK 0x38
9774 #define MC_SEQ_BIT_REMAP_B1_D1__BIT1__SHIFT 0x3
9775 #define MC_SEQ_BIT_REMAP_B1_D1__BIT2_MASK 0x1c0
9776 #define MC_SEQ_BIT_REMAP_B1_D1__BIT2__SHIFT 0x6
9777 #define MC_SEQ_BIT_REMAP_B1_D1__BIT3_MASK 0xe00
9778 #define MC_SEQ_BIT_REMAP_B1_D1__BIT3__SHIFT 0x9
9779 #define MC_SEQ_BIT_REMAP_B1_D1__BIT4_MASK 0x7000
9780 #define MC_SEQ_BIT_REMAP_B1_D1__BIT4__SHIFT 0xc
9781 #define MC_SEQ_BIT_REMAP_B1_D1__BIT5_MASK 0x38000
9782 #define MC_SEQ_BIT_REMAP_B1_D1__BIT5__SHIFT 0xf
9783 #define MC_SEQ_BIT_REMAP_B1_D1__BIT6_MASK 0x1c0000
9784 #define MC_SEQ_BIT_REMAP_B1_D1__BIT6__SHIFT 0x12
9785 #define MC_SEQ_BIT_REMAP_B1_D1__BIT7_MASK 0xe00000
9786 #define MC_SEQ_BIT_REMAP_B1_D1__BIT7__SHIFT 0x15
9787 #define MC_SEQ_BIT_REMAP_B2_D1__BIT0_MASK 0x7
9788 #define MC_SEQ_BIT_REMAP_B2_D1__BIT0__SHIFT 0x0
9789 #define MC_SEQ_BIT_REMAP_B2_D1__BIT1_MASK 0x38
9790 #define MC_SEQ_BIT_REMAP_B2_D1__BIT1__SHIFT 0x3
9791 #define MC_SEQ_BIT_REMAP_B2_D1__BIT2_MASK 0x1c0
9792 #define MC_SEQ_BIT_REMAP_B2_D1__BIT2__SHIFT 0x6
9793 #define MC_SEQ_BIT_REMAP_B2_D1__BIT3_MASK 0xe00
9794 #define MC_SEQ_BIT_REMAP_B2_D1__BIT3__SHIFT 0x9
9795 #define MC_SEQ_BIT_REMAP_B2_D1__BIT4_MASK 0x7000
9796 #define MC_SEQ_BIT_REMAP_B2_D1__BIT4__SHIFT 0xc
9797 #define MC_SEQ_BIT_REMAP_B2_D1__BIT5_MASK 0x38000
9798 #define MC_SEQ_BIT_REMAP_B2_D1__BIT5__SHIFT 0xf
9799 #define MC_SEQ_BIT_REMAP_B2_D1__BIT6_MASK 0x1c0000
9800 #define MC_SEQ_BIT_REMAP_B2_D1__BIT6__SHIFT 0x12
9801 #define MC_SEQ_BIT_REMAP_B2_D1__BIT7_MASK 0xe00000
9802 #define MC_SEQ_BIT_REMAP_B2_D1__BIT7__SHIFT 0x15
9803 #define MC_SEQ_BIT_REMAP_B3_D1__BIT0_MASK 0x7
9804 #define MC_SEQ_BIT_REMAP_B3_D1__BIT0__SHIFT 0x0
9805 #define MC_SEQ_BIT_REMAP_B3_D1__BIT1_MASK 0x38
9806 #define MC_SEQ_BIT_REMAP_B3_D1__BIT1__SHIFT 0x3
9807 #define MC_SEQ_BIT_REMAP_B3_D1__BIT2_MASK 0x1c0
9808 #define MC_SEQ_BIT_REMAP_B3_D1__BIT2__SHIFT 0x6
9809 #define MC_SEQ_BIT_REMAP_B3_D1__BIT3_MASK 0xe00
9810 #define MC_SEQ_BIT_REMAP_B3_D1__BIT3__SHIFT 0x9
9811 #define MC_SEQ_BIT_REMAP_B3_D1__BIT4_MASK 0x7000
9812 #define MC_SEQ_BIT_REMAP_B3_D1__BIT4__SHIFT 0xc
9813 #define MC_SEQ_BIT_REMAP_B3_D1__BIT5_MASK 0x38000
9814 #define MC_SEQ_BIT_REMAP_B3_D1__BIT5__SHIFT 0xf
9815 #define MC_SEQ_BIT_REMAP_B3_D1__BIT6_MASK 0x1c0000
9816 #define MC_SEQ_BIT_REMAP_B3_D1__BIT6__SHIFT 0x12
9817 #define MC_SEQ_BIT_REMAP_B3_D1__BIT7_MASK 0xe00000
9818 #define MC_SEQ_BIT_REMAP_B3_D1__BIT7__SHIFT 0x15
9819 #define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
9820 #define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0
9821 #define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
9822 #define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5
9823 #define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
9824 #define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa
9825 #define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
9826 #define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf
9827 #define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
9828 #define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14
9829 #define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
9830 #define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18
9831 #define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
9832 #define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0
9833 #define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
9834 #define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2
9835 #define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
9836 #define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4
9837 #define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
9838 #define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9
9839 #define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000
9840 #define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
9841 #define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000
9842 #define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
9843 #define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000
9844 #define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
9845 #define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f
9846 #define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0
9847 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
9848 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8
9849 #define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
9850 #define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf
9851 #define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
9852 #define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14
9853 #define MC_SEQ_MISC_TIMING2_LP__PA2RDATA_MASK 0x7
9854 #define MC_SEQ_MISC_TIMING2_LP__PA2RDATA__SHIFT 0x0
9855 #define MC_SEQ_MISC_TIMING2_LP__PA2WDATA_MASK 0x70
9856 #define MC_SEQ_MISC_TIMING2_LP__PA2WDATA__SHIFT 0x4
9857 #define MC_SEQ_MISC_TIMING2_LP__FAW_MASK 0x1f00
9858 #define MC_SEQ_MISC_TIMING2_LP__FAW__SHIFT 0x8
9859 #define MC_SEQ_MISC_TIMING2_LP__TREDC_MASK 0xe000
9860 #define MC_SEQ_MISC_TIMING2_LP__TREDC__SHIFT 0xd
9861 #define MC_SEQ_MISC_TIMING2_LP__TWEDC_MASK 0x1f0000
9862 #define MC_SEQ_MISC_TIMING2_LP__TWEDC__SHIFT 0x10
9863 #define MC_SEQ_MISC_TIMING2_LP__TADR_MASK 0xe00000
9864 #define MC_SEQ_MISC_TIMING2_LP__TADR__SHIFT 0x15
9865 #define MC_SEQ_MISC_TIMING2_LP__TFCKTR_MASK 0xf000000
9866 #define MC_SEQ_MISC_TIMING2_LP__TFCKTR__SHIFT 0x18
9867 #define MC_SEQ_MISC_TIMING2_LP__TWDATATR_MASK 0xf0000000
9868 #define MC_SEQ_MISC_TIMING2_LP__TWDATATR__SHIFT 0x1c
9869 #define MC_SEQ_RD_CTL_D0_LP__RCV_DLY_MASK 0x7
9870 #define MC_SEQ_RD_CTL_D0_LP__RCV_DLY__SHIFT 0x0
9871 #define MC_SEQ_RD_CTL_D0_LP__RCV_EXT_MASK 0xf8
9872 #define MC_SEQ_RD_CTL_D0_LP__RCV_EXT__SHIFT 0x3
9873 #define MC_SEQ_RD_CTL_D0_LP__RST_SEL_MASK 0x300
9874 #define MC_SEQ_RD_CTL_D0_LP__RST_SEL__SHIFT 0x8
9875 #define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY_MASK 0xc00
9876 #define MC_SEQ_RD_CTL_D0_LP__RXDPWRON_DLY__SHIFT 0xa
9877 #define MC_SEQ_RD_CTL_D0_LP__RST_HLD_MASK 0xf000
9878 #define MC_SEQ_RD_CTL_D0_LP__RST_HLD__SHIFT 0xc
9879 #define MC_SEQ_RD_CTL_D0_LP__STR_PRE_MASK 0x10000
9880 #define MC_SEQ_RD_CTL_D0_LP__STR_PRE__SHIFT 0x10
9881 #define MC_SEQ_RD_CTL_D0_LP__STR_PST_MASK 0x20000
9882 #define MC_SEQ_RD_CTL_D0_LP__STR_PST__SHIFT 0x11
9883 #define MC_SEQ_RD_CTL_D0_LP__RBS_DLY_MASK 0x1f00000
9884 #define MC_SEQ_RD_CTL_D0_LP__RBS_DLY__SHIFT 0x14
9885 #define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY_MASK 0x3e000000
9886 #define MC_SEQ_RD_CTL_D0_LP__RBS_WEDC_DLY__SHIFT 0x19
9887 #define MC_SEQ_RD_CTL_D1_LP__RCV_DLY_MASK 0x7
9888 #define MC_SEQ_RD_CTL_D1_LP__RCV_DLY__SHIFT 0x0
9889 #define MC_SEQ_RD_CTL_D1_LP__RCV_EXT_MASK 0xf8
9890 #define MC_SEQ_RD_CTL_D1_LP__RCV_EXT__SHIFT 0x3
9891 #define MC_SEQ_RD_CTL_D1_LP__RST_SEL_MASK 0x300
9892 #define MC_SEQ_RD_CTL_D1_LP__RST_SEL__SHIFT 0x8
9893 #define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY_MASK 0xc00
9894 #define MC_SEQ_RD_CTL_D1_LP__RXDPWRON_DLY__SHIFT 0xa
9895 #define MC_SEQ_RD_CTL_D1_LP__RST_HLD_MASK 0xf000
9896 #define MC_SEQ_RD_CTL_D1_LP__RST_HLD__SHIFT 0xc
9897 #define MC_SEQ_RD_CTL_D1_LP__STR_PRE_MASK 0x10000
9898 #define MC_SEQ_RD_CTL_D1_LP__STR_PRE__SHIFT 0x10
9899 #define MC_SEQ_RD_CTL_D1_LP__STR_PST_MASK 0x20000
9900 #define MC_SEQ_RD_CTL_D1_LP__STR_PST__SHIFT 0x11
9901 #define MC_SEQ_RD_CTL_D1_LP__RBS_DLY_MASK 0x1f00000
9902 #define MC_SEQ_RD_CTL_D1_LP__RBS_DLY__SHIFT 0x14
9903 #define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY_MASK 0x3e000000
9904 #define MC_SEQ_RD_CTL_D1_LP__RBS_WEDC_DLY__SHIFT 0x19
9905 #define MC_SEQ_WR_CTL_D0_LP__DAT_DLY_MASK 0xf
9906 #define MC_SEQ_WR_CTL_D0_LP__DAT_DLY__SHIFT 0x0
9907 #define MC_SEQ_WR_CTL_D0_LP__DQS_DLY_MASK 0xf0
9908 #define MC_SEQ_WR_CTL_D0_LP__DQS_DLY__SHIFT 0x4
9909 #define MC_SEQ_WR_CTL_D0_LP__DQS_XTR_MASK 0x100
9910 #define MC_SEQ_WR_CTL_D0_LP__DQS_XTR__SHIFT 0x8
9911 #define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY_MASK 0x200
9912 #define MC_SEQ_WR_CTL_D0_LP__DAT_2Y_DLY__SHIFT 0x9
9913 #define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY_MASK 0x400
9914 #define MC_SEQ_WR_CTL_D0_LP__ADR_2Y_DLY__SHIFT 0xa
9915 #define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY_MASK 0x800
9916 #define MC_SEQ_WR_CTL_D0_LP__CMD_2Y_DLY__SHIFT 0xb
9917 #define MC_SEQ_WR_CTL_D0_LP__OEN_DLY_MASK 0xf000
9918 #define MC_SEQ_WR_CTL_D0_LP__OEN_DLY__SHIFT 0xc
9919 #define MC_SEQ_WR_CTL_D0_LP__OEN_EXT_MASK 0xf0000
9920 #define MC_SEQ_WR_CTL_D0_LP__OEN_EXT__SHIFT 0x10
9921 #define MC_SEQ_WR_CTL_D0_LP__OEN_SEL_MASK 0x300000
9922 #define MC_SEQ_WR_CTL_D0_LP__OEN_SEL__SHIFT 0x14
9923 #define MC_SEQ_WR_CTL_D0_LP__ODT_DLY_MASK 0xf000000
9924 #define MC_SEQ_WR_CTL_D0_LP__ODT_DLY__SHIFT 0x18
9925 #define MC_SEQ_WR_CTL_D0_LP__ODT_EXT_MASK 0x10000000
9926 #define MC_SEQ_WR_CTL_D0_LP__ODT_EXT__SHIFT 0x1c
9927 #define MC_SEQ_WR_CTL_D0_LP__ADR_DLY_MASK 0x20000000
9928 #define MC_SEQ_WR_CTL_D0_LP__ADR_DLY__SHIFT 0x1d
9929 #define MC_SEQ_WR_CTL_D0_LP__CMD_DLY_MASK 0x40000000
9930 #define MC_SEQ_WR_CTL_D0_LP__CMD_DLY__SHIFT 0x1e
9931 #define MC_SEQ_WR_CTL_D1_LP__DAT_DLY_MASK 0xf
9932 #define MC_SEQ_WR_CTL_D1_LP__DAT_DLY__SHIFT 0x0
9933 #define MC_SEQ_WR_CTL_D1_LP__DQS_DLY_MASK 0xf0
9934 #define MC_SEQ_WR_CTL_D1_LP__DQS_DLY__SHIFT 0x4
9935 #define MC_SEQ_WR_CTL_D1_LP__DQS_XTR_MASK 0x100
9936 #define MC_SEQ_WR_CTL_D1_LP__DQS_XTR__SHIFT 0x8
9937 #define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY_MASK 0x200
9938 #define MC_SEQ_WR_CTL_D1_LP__DAT_2Y_DLY__SHIFT 0x9
9939 #define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY_MASK 0x400
9940 #define MC_SEQ_WR_CTL_D1_LP__ADR_2Y_DLY__SHIFT 0xa
9941 #define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY_MASK 0x800
9942 #define MC_SEQ_WR_CTL_D1_LP__CMD_2Y_DLY__SHIFT 0xb
9943 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY_MASK 0xf000
9944 #define MC_SEQ_WR_CTL_D1_LP__OEN_DLY__SHIFT 0xc
9945 #define MC_SEQ_WR_CTL_D1_LP__OEN_EXT_MASK 0xf0000
9946 #define MC_SEQ_WR_CTL_D1_LP__OEN_EXT__SHIFT 0x10
9947 #define MC_SEQ_WR_CTL_D1_LP__OEN_SEL_MASK 0x300000
9948 #define MC_SEQ_WR_CTL_D1_LP__OEN_SEL__SHIFT 0x14
9949 #define MC_SEQ_WR_CTL_D1_LP__ODT_DLY_MASK 0xf000000
9950 #define MC_SEQ_WR_CTL_D1_LP__ODT_DLY__SHIFT 0x18
9951 #define MC_SEQ_WR_CTL_D1_LP__ODT_EXT_MASK 0x10000000
9952 #define MC_SEQ_WR_CTL_D1_LP__ODT_EXT__SHIFT 0x1c
9953 #define MC_SEQ_WR_CTL_D1_LP__ADR_DLY_MASK 0x20000000
9954 #define MC_SEQ_WR_CTL_D1_LP__ADR_DLY__SHIFT 0x1d
9955 #define MC_SEQ_WR_CTL_D1_LP__CMD_DLY_MASK 0x40000000
9956 #define MC_SEQ_WR_CTL_D1_LP__CMD_DLY__SHIFT 0x1e
9957 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0_MASK 0x1
9958 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D0__SHIFT 0x0
9959 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0_MASK 0x2
9960 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D0__SHIFT 0x1
9961 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0_MASK 0x4
9962 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D0__SHIFT 0x2
9963 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1_MASK 0x8
9964 #define MC_SEQ_WR_CTL_2_LP__DAT_DLY_H_D1__SHIFT 0x3
9965 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1_MASK 0x10
9966 #define MC_SEQ_WR_CTL_2_LP__DQS_DLY_H_D1__SHIFT 0x4
9967 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1_MASK 0x20
9968 #define MC_SEQ_WR_CTL_2_LP__OEN_DLY_H_D1__SHIFT 0x5
9969 #define MC_SEQ_WR_CTL_2_LP__WCDR_EN_MASK 0x40
9970 #define MC_SEQ_WR_CTL_2_LP__WCDR_EN__SHIFT 0x6
9971 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MASK 0xffff
9972 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR__SHIFT 0x0
9973 #define MC_SEQ_PMG_CMD_EMRS_LP__MOP_MASK 0x70000
9974 #define MC_SEQ_PMG_CMD_EMRS_LP__MOP__SHIFT 0x10
9975 #define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB_MASK 0x80000
9976 #define MC_SEQ_PMG_CMD_EMRS_LP__BNK_MSB__SHIFT 0x13
9977 #define MC_SEQ_PMG_CMD_EMRS_LP__END_MASK 0x100000
9978 #define MC_SEQ_PMG_CMD_EMRS_LP__END__SHIFT 0x14
9979 #define MC_SEQ_PMG_CMD_EMRS_LP__CSB_MASK 0x600000
9980 #define MC_SEQ_PMG_CMD_EMRS_LP__CSB__SHIFT 0x15
9981 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1_MASK 0x10000000
9982 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB1__SHIFT 0x1c
9983 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0_MASK 0x20000000
9984 #define MC_SEQ_PMG_CMD_EMRS_LP__ADR_MSB0__SHIFT 0x1d
9985 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MASK 0xffff
9986 #define MC_SEQ_PMG_CMD_MRS_LP__ADR__SHIFT 0x0
9987 #define MC_SEQ_PMG_CMD_MRS_LP__MOP_MASK 0x70000
9988 #define MC_SEQ_PMG_CMD_MRS_LP__MOP__SHIFT 0x10
9989 #define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB_MASK 0x80000
9990 #define MC_SEQ_PMG_CMD_MRS_LP__BNK_MSB__SHIFT 0x13
9991 #define MC_SEQ_PMG_CMD_MRS_LP__END_MASK 0x100000
9992 #define MC_SEQ_PMG_CMD_MRS_LP__END__SHIFT 0x14
9993 #define MC_SEQ_PMG_CMD_MRS_LP__CSB_MASK 0x600000
9994 #define MC_SEQ_PMG_CMD_MRS_LP__CSB__SHIFT 0x15
9995 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1_MASK 0x10000000
9996 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB1__SHIFT 0x1c
9997 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0_MASK 0x20000000
9998 #define MC_SEQ_PMG_CMD_MRS_LP__ADR_MSB0__SHIFT 0x1d
9999 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MASK 0xffff
10000 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR__SHIFT 0x0
10001 #define MC_SEQ_PMG_CMD_MRS1_LP__MOP_MASK 0x70000
10002 #define MC_SEQ_PMG_CMD_MRS1_LP__MOP__SHIFT 0x10
10003 #define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB_MASK 0x80000
10004 #define MC_SEQ_PMG_CMD_MRS1_LP__BNK_MSB__SHIFT 0x13
10005 #define MC_SEQ_PMG_CMD_MRS1_LP__END_MASK 0x100000
10006 #define MC_SEQ_PMG_CMD_MRS1_LP__END__SHIFT 0x14
10007 #define MC_SEQ_PMG_CMD_MRS1_LP__CSB_MASK 0x600000
10008 #define MC_SEQ_PMG_CMD_MRS1_LP__CSB__SHIFT 0x15
10009 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1_MASK 0x10000000
10010 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB1__SHIFT 0x1c
10011 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0_MASK 0x20000000
10012 #define MC_SEQ_PMG_CMD_MRS1_LP__ADR_MSB0__SHIFT 0x1d
10013 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MASK 0xffff
10014 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR__SHIFT 0x0
10015 #define MC_SEQ_PMG_CMD_MRS2_LP__MOP_MASK 0x70000
10016 #define MC_SEQ_PMG_CMD_MRS2_LP__MOP__SHIFT 0x10
10017 #define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB_MASK 0x80000
10018 #define MC_SEQ_PMG_CMD_MRS2_LP__BNK_MSB__SHIFT 0x13
10019 #define MC_SEQ_PMG_CMD_MRS2_LP__END_MASK 0x100000
10020 #define MC_SEQ_PMG_CMD_MRS2_LP__END__SHIFT 0x14
10021 #define MC_SEQ_PMG_CMD_MRS2_LP__CSB_MASK 0x600000
10022 #define MC_SEQ_PMG_CMD_MRS2_LP__CSB__SHIFT 0x15
10023 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1_MASK 0x10000000
10024 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB1__SHIFT 0x1c
10025 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0_MASK 0x20000000
10026 #define MC_SEQ_PMG_CMD_MRS2_LP__ADR_MSB0__SHIFT 0x1d
10027 #define MC_SEQ_PMG_TIMING_LP__TCKSRE_MASK 0x7
10028 #define MC_SEQ_PMG_TIMING_LP__TCKSRE__SHIFT 0x0
10029 #define MC_SEQ_PMG_TIMING_LP__TCKSRX_MASK 0x70
10030 #define MC_SEQ_PMG_TIMING_LP__TCKSRX__SHIFT 0x4
10031 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MASK 0xf00
10032 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE__SHIFT 0x8
10033 #define MC_SEQ_PMG_TIMING_LP__TCKE_MASK 0x3f000
10034 #define MC_SEQ_PMG_TIMING_LP__TCKE__SHIFT 0xc
10035 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_MASK 0x1c0000
10036 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE__SHIFT 0x12
10037 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB_MASK 0x800000
10038 #define MC_SEQ_PMG_TIMING_LP__TCKE_PULSE_MSB__SHIFT 0x17
10039 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS_MASK 0xff000000
10040 #define MC_SEQ_PMG_TIMING_LP__SEQ_IDLE_SS__SHIFT 0x18
10041 #define MC_SEQ_IO_RWORD0__RDATA_MASK 0xffffffff
10042 #define MC_SEQ_IO_RWORD0__RDATA__SHIFT 0x0
10043 #define MC_SEQ_IO_RWORD1__RDATA_MASK 0xffffffff
10044 #define MC_SEQ_IO_RWORD1__RDATA__SHIFT 0x0
10045 #define MC_SEQ_IO_RWORD2__RDATA_MASK 0xffffffff
10046 #define MC_SEQ_IO_RWORD2__RDATA__SHIFT 0x0
10047 #define MC_SEQ_IO_RWORD3__RDATA_MASK 0xffffffff
10048 #define MC_SEQ_IO_RWORD3__RDATA__SHIFT 0x0
10049 #define MC_SEQ_IO_RWORD4__RDATA_MASK 0xffffffff
10050 #define MC_SEQ_IO_RWORD4__RDATA__SHIFT 0x0
10051 #define MC_SEQ_IO_RWORD5__RDATA_MASK 0xffffffff
10052 #define MC_SEQ_IO_RWORD5__RDATA__SHIFT 0x0
10053 #define MC_SEQ_IO_RWORD6__RDATA_MASK 0xffffffff
10054 #define MC_SEQ_IO_RWORD6__RDATA__SHIFT 0x0
10055 #define MC_SEQ_IO_RWORD7__RDATA_MASK 0xffffffff
10056 #define MC_SEQ_IO_RWORD7__RDATA__SHIFT 0x0
10057 #define MC_SEQ_IO_RDBI__MASK_MASK 0xffffffff
10058 #define MC_SEQ_IO_RDBI__MASK__SHIFT 0x0
10059 #define MC_SEQ_IO_REDC__EDC_MASK 0xffffffff
10060 #define MC_SEQ_IO_REDC__EDC__SHIFT 0x0
10061 #define MC_SEQ_TCG_CNTL__RESET_MASK 0x1
10062 #define MC_SEQ_TCG_CNTL__RESET__SHIFT 0x0
10063 #define MC_SEQ_TCG_CNTL__ENABLE_D0_MASK 0x2
10064 #define MC_SEQ_TCG_CNTL__ENABLE_D0__SHIFT 0x1
10065 #define MC_SEQ_TCG_CNTL__ENABLE_D1_MASK 0x4
10066 #define MC_SEQ_TCG_CNTL__ENABLE_D1__SHIFT 0x2
10067 #define MC_SEQ_TCG_CNTL__START_MASK 0x8
10068 #define MC_SEQ_TCG_CNTL__START__SHIFT 0x3
10069 #define MC_SEQ_TCG_CNTL__NFIFO_MASK 0x70
10070 #define MC_SEQ_TCG_CNTL__NFIFO__SHIFT 0x4
10071 #define MC_SEQ_TCG_CNTL__INFINITE_CMD_MASK 0x80
10072 #define MC_SEQ_TCG_CNTL__INFINITE_CMD__SHIFT 0x7
10073 #define MC_SEQ_TCG_CNTL__MOP_MASK 0xf00
10074 #define MC_SEQ_TCG_CNTL__MOP__SHIFT 0x8
10075 #define MC_SEQ_TCG_CNTL__DATA_CNT_MASK 0xf000
10076 #define MC_SEQ_TCG_CNTL__DATA_CNT__SHIFT 0xc
10077 #define MC_SEQ_TCG_CNTL__LOAD_FIFO_MASK 0x10000
10078 #define MC_SEQ_TCG_CNTL__LOAD_FIFO__SHIFT 0x10
10079 #define MC_SEQ_TCG_CNTL__SHORT_LDFF_MASK 0x20000
10080 #define MC_SEQ_TCG_CNTL__SHORT_LDFF__SHIFT 0x11
10081 #define MC_SEQ_TCG_CNTL__FRAME_TRAIN_MASK 0x40000
10082 #define MC_SEQ_TCG_CNTL__FRAME_TRAIN__SHIFT 0x12
10083 #define MC_SEQ_TCG_CNTL__BURST_NUM_MASK 0x380000
10084 #define MC_SEQ_TCG_CNTL__BURST_NUM__SHIFT 0x13
10085 #define MC_SEQ_TCG_CNTL__ISSUE_AREF_MASK 0x400000
10086 #define MC_SEQ_TCG_CNTL__ISSUE_AREF__SHIFT 0x16
10087 #define MC_SEQ_TCG_CNTL__TXDBI_CNTL_MASK 0x800000
10088 #define MC_SEQ_TCG_CNTL__TXDBI_CNTL__SHIFT 0x17
10089 #define MC_SEQ_TCG_CNTL__VPTR_MASK_MASK 0x1000000
10090 #define MC_SEQ_TCG_CNTL__VPTR_MASK__SHIFT 0x18
10091 #define MC_SEQ_TCG_CNTL__AREF_LAST_MASK 0x2000000
10092 #define MC_SEQ_TCG_CNTL__AREF_LAST__SHIFT 0x19
10093 #define MC_SEQ_TCG_CNTL__AREF_BOTH_MASK 0x4000000
10094 #define MC_SEQ_TCG_CNTL__AREF_BOTH__SHIFT 0x1a
10095 #define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR_MASK 0x10000000
10096 #define MC_SEQ_TCG_CNTL__LD_RTDATA_OVR__SHIFT 0x1c
10097 #define MC_SEQ_TCG_CNTL__LD_RTDATA_CH_MASK 0x20000000
10098 #define MC_SEQ_TCG_CNTL__LD_RTDATA_CH__SHIFT 0x1d
10099 #define MC_SEQ_TCG_CNTL__DONE_MASK 0x80000000
10100 #define MC_SEQ_TCG_CNTL__DONE__SHIFT 0x1f
10101 #define MC_SEQ_TSM_CTRL__START_MASK 0x1
10102 #define MC_SEQ_TSM_CTRL__START__SHIFT 0x0
10103 #define MC_SEQ_TSM_CTRL__CAPTURE_START_MASK 0x2
10104 #define MC_SEQ_TSM_CTRL__CAPTURE_START__SHIFT 0x1
10105 #define MC_SEQ_TSM_CTRL__DONE_MASK 0x4
10106 #define MC_SEQ_TSM_CTRL__DONE__SHIFT 0x2
10107 #define MC_SEQ_TSM_CTRL__ERR_MASK 0x8
10108 #define MC_SEQ_TSM_CTRL__ERR__SHIFT 0x3
10109 #define MC_SEQ_TSM_CTRL__STEP_MASK 0x10
10110 #define MC_SEQ_TSM_CTRL__STEP__SHIFT 0x4
10111 #define MC_SEQ_TSM_CTRL__DIRECTION_MASK 0x20
10112 #define MC_SEQ_TSM_CTRL__DIRECTION__SHIFT 0x5
10113 #define MC_SEQ_TSM_CTRL__INVERT_MASK 0x40
10114 #define MC_SEQ_TSM_CTRL__INVERT__SHIFT 0x6
10115 #define MC_SEQ_TSM_CTRL__MASK_BITS_MASK 0x80
10116 #define MC_SEQ_TSM_CTRL__MASK_BITS__SHIFT 0x7
10117 #define MC_SEQ_TSM_CTRL__UPDATE_LOOP_MASK 0x300
10118 #define MC_SEQ_TSM_CTRL__UPDATE_LOOP__SHIFT 0x8
10119 #define MC_SEQ_TSM_CTRL__ROT_INV_MASK 0x400
10120 #define MC_SEQ_TSM_CTRL__ROT_INV__SHIFT 0xa
10121 #define MC_SEQ_TSM_CTRL__DUAL_CH_EN_MASK 0x800
10122 #define MC_SEQ_TSM_CTRL__DUAL_CH_EN__SHIFT 0xb
10123 #define MC_SEQ_TSM_CTRL__DONE0_MASK 0x1000
10124 #define MC_SEQ_TSM_CTRL__DONE0__SHIFT 0xc
10125 #define MC_SEQ_TSM_CTRL__DONE1_MASK 0x2000
10126 #define MC_SEQ_TSM_CTRL__DONE1__SHIFT 0xd
10127 #define MC_SEQ_TSM_CTRL__POINTER_MASK 0xffff0000
10128 #define MC_SEQ_TSM_CTRL__POINTER__SHIFT 0x10
10129 #define MC_SEQ_TSM_GCNT__TRUE_ACT_MASK 0xf
10130 #define MC_SEQ_TSM_GCNT__TRUE_ACT__SHIFT 0x0
10131 #define MC_SEQ_TSM_GCNT__FALSE_ACT_MASK 0xf0
10132 #define MC_SEQ_TSM_GCNT__FALSE_ACT__SHIFT 0x4
10133 #define MC_SEQ_TSM_GCNT__TESTS_MASK 0xff00
10134 #define MC_SEQ_TSM_GCNT__TESTS__SHIFT 0x8
10135 #define MC_SEQ_TSM_GCNT__COMP_VALUE_MASK 0xffff0000
10136 #define MC_SEQ_TSM_GCNT__COMP_VALUE__SHIFT 0x10
10137 #define MC_SEQ_TSM_OCNT__TRUE_ACT_MASK 0xf
10138 #define MC_SEQ_TSM_OCNT__TRUE_ACT__SHIFT 0x0
10139 #define MC_SEQ_TSM_OCNT__FALSE_ACT_MASK 0xf0
10140 #define MC_SEQ_TSM_OCNT__FALSE_ACT__SHIFT 0x4
10141 #define MC_SEQ_TSM_OCNT__TESTS_MASK 0xff00
10142 #define MC_SEQ_TSM_OCNT__TESTS__SHIFT 0x8
10143 #define MC_SEQ_TSM_OCNT__CMP_VALUE_MASK 0xffff0000
10144 #define MC_SEQ_TSM_OCNT__CMP_VALUE__SHIFT 0x10
10145 #define MC_SEQ_TSM_NCNT__TRUE_ACT_MASK 0xf
10146 #define MC_SEQ_TSM_NCNT__TRUE_ACT__SHIFT 0x0
10147 #define MC_SEQ_TSM_NCNT__FALSE_ACT_MASK 0xf0
10148 #define MC_SEQ_TSM_NCNT__FALSE_ACT__SHIFT 0x4
10149 #define MC_SEQ_TSM_NCNT__TESTS_MASK 0xff00
10150 #define MC_SEQ_TSM_NCNT__TESTS__SHIFT 0x8
10151 #define MC_SEQ_TSM_NCNT__RANGE_LOW_MASK 0xf0000
10152 #define MC_SEQ_TSM_NCNT__RANGE_LOW__SHIFT 0x10
10153 #define MC_SEQ_TSM_NCNT__RANGE_HIGH_MASK 0xf00000
10154 #define MC_SEQ_TSM_NCNT__RANGE_HIGH__SHIFT 0x14
10155 #define MC_SEQ_TSM_NCNT__NIBBLE_SKIP_MASK 0xf000000
10156 #define MC_SEQ_TSM_NCNT__NIBBLE_SKIP__SHIFT 0x18
10157 #define MC_SEQ_TSM_BCNT__TRUE_ACT_MASK 0xf
10158 #define MC_SEQ_TSM_BCNT__TRUE_ACT__SHIFT 0x0
10159 #define MC_SEQ_TSM_BCNT__FALSE_ACT_MASK 0xf0
10160 #define MC_SEQ_TSM_BCNT__FALSE_ACT__SHIFT 0x4
10161 #define MC_SEQ_TSM_BCNT__BCNT_TESTS_MASK 0xff00
10162 #define MC_SEQ_TSM_BCNT__BCNT_TESTS__SHIFT 0x8
10163 #define MC_SEQ_TSM_BCNT__COMP_VALUE_MASK 0xff0000
10164 #define MC_SEQ_TSM_BCNT__COMP_VALUE__SHIFT 0x10
10165 #define MC_SEQ_TSM_BCNT__DONE_TESTS_MASK 0xff000000
10166 #define MC_SEQ_TSM_BCNT__DONE_TESTS__SHIFT 0x18
10167 #define MC_SEQ_TSM_FLAG__TRUE_ACT_MASK 0xf
10168 #define MC_SEQ_TSM_FLAG__TRUE_ACT__SHIFT 0x0
10169 #define MC_SEQ_TSM_FLAG__FALSE_ACT_MASK 0xf0
10170 #define MC_SEQ_TSM_FLAG__FALSE_ACT__SHIFT 0x4
10171 #define MC_SEQ_TSM_FLAG__FLAG_TESTS_MASK 0xff00
10172 #define MC_SEQ_TSM_FLAG__FLAG_TESTS__SHIFT 0x8
10173 #define MC_SEQ_TSM_FLAG__NBBL_MASK_MASK 0xf0000
10174 #define MC_SEQ_TSM_FLAG__NBBL_MASK__SHIFT 0x10
10175 #define MC_SEQ_TSM_FLAG__ERROR_TESTS_MASK 0xff000000
10176 #define MC_SEQ_TSM_FLAG__ERROR_TESTS__SHIFT 0x18
10177 #define MC_SEQ_TSM_UPDATE__TRUE_ACT_MASK 0xf
10178 #define MC_SEQ_TSM_UPDATE__TRUE_ACT__SHIFT 0x0
10179 #define MC_SEQ_TSM_UPDATE__FALSE_ACT_MASK 0xf0
10180 #define MC_SEQ_TSM_UPDATE__FALSE_ACT__SHIFT 0x4
10181 #define MC_SEQ_TSM_UPDATE__UPDT_TESTS_MASK 0xff00
10182 #define MC_SEQ_TSM_UPDATE__UPDT_TESTS__SHIFT 0x8
10183 #define MC_SEQ_TSM_UPDATE__AREF_COUNT_MASK 0xff0000
10184 #define MC_SEQ_TSM_UPDATE__AREF_COUNT__SHIFT 0x10
10185 #define MC_SEQ_TSM_UPDATE__CAPTR_TESTS_MASK 0xff000000
10186 #define MC_SEQ_TSM_UPDATE__CAPTR_TESTS__SHIFT 0x18
10187 #define MC_SEQ_TSM_EDC__EDC_MASK 0xffffffff
10188 #define MC_SEQ_TSM_EDC__EDC__SHIFT 0x0
10189 #define MC_SEQ_TSM_DBI__DBI_MASK 0xffffffff
10190 #define MC_SEQ_TSM_DBI__DBI__SHIFT 0x0
10191 #define MC_SEQ_TSM_WCDR__WCDR_MASK 0xffffffff
10192 #define MC_SEQ_TSM_WCDR__WCDR__SHIFT 0x0
10193 #define MC_SEQ_TSM_MISC__WCDR_PTR_MASK 0xffff
10194 #define MC_SEQ_TSM_MISC__WCDR_PTR__SHIFT 0x0
10195 #define MC_SEQ_TSM_MISC__WCDR_MASK_MASK 0xf0000
10196 #define MC_SEQ_TSM_MISC__WCDR_MASK__SHIFT 0x10
10197 #define MC_SEQ_TSM_MISC__CH1_OFFSET_MASK 0x3f00000
10198 #define MC_SEQ_TSM_MISC__CH1_OFFSET__SHIFT 0x14
10199 #define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET_MASK 0xfc000000
10200 #define MC_SEQ_TSM_MISC__CH1_WCDR_OFFSET__SHIFT 0x1a
10201 #define MC_SEQ_TIMER_WR__COUNTER_MASK 0xffffffff
10202 #define MC_SEQ_TIMER_WR__COUNTER__SHIFT 0x0
10203 #define MC_SEQ_TIMER_RD__COUNTER_MASK 0xffffffff
10204 #define MC_SEQ_TIMER_RD__COUNTER__SHIFT 0x0
10205 #define MC_SEQ_DRAM_ERROR_INSERTION__TX_MASK 0xffff
10206 #define MC_SEQ_DRAM_ERROR_INSERTION__TX__SHIFT 0x0
10207 #define MC_SEQ_DRAM_ERROR_INSERTION__RX_MASK 0xffff0000
10208 #define MC_SEQ_DRAM_ERROR_INSERTION__RX__SHIFT 0x10
10209 #define MC_PHY_TIMING_D0__RXC0_DLY_MASK 0xf
10210 #define MC_PHY_TIMING_D0__RXC0_DLY__SHIFT 0x0
10211 #define MC_PHY_TIMING_D0__RXC0_EXT_MASK 0xf0
10212 #define MC_PHY_TIMING_D0__RXC0_EXT__SHIFT 0x4
10213 #define MC_PHY_TIMING_D0__RXC1_DLY_MASK 0xf00
10214 #define MC_PHY_TIMING_D0__RXC1_DLY__SHIFT 0x8
10215 #define MC_PHY_TIMING_D0__RXC1_EXT_MASK 0xf000
10216 #define MC_PHY_TIMING_D0__RXC1_EXT__SHIFT 0xc
10217 #define MC_PHY_TIMING_D0__TXC0_DLY_MASK 0x70000
10218 #define MC_PHY_TIMING_D0__TXC0_DLY__SHIFT 0x10
10219 #define MC_PHY_TIMING_D0__TXC0_EXT_MASK 0xf00000
10220 #define MC_PHY_TIMING_D0__TXC0_EXT__SHIFT 0x14
10221 #define MC_PHY_TIMING_D0__TXC1_DLY_MASK 0x7000000
10222 #define MC_PHY_TIMING_D0__TXC1_DLY__SHIFT 0x18
10223 #define MC_PHY_TIMING_D0__TXC1_EXT_MASK 0xf0000000
10224 #define MC_PHY_TIMING_D0__TXC1_EXT__SHIFT 0x1c
10225 #define MC_PHY_TIMING_D1__RXC0_DLY_MASK 0xf
10226 #define MC_PHY_TIMING_D1__RXC0_DLY__SHIFT 0x0
10227 #define MC_PHY_TIMING_D1__RXC0_EXT_MASK 0xf0
10228 #define MC_PHY_TIMING_D1__RXC0_EXT__SHIFT 0x4
10229 #define MC_PHY_TIMING_D1__RXC1_DLY_MASK 0xf00
10230 #define MC_PHY_TIMING_D1__RXC1_DLY__SHIFT 0x8
10231 #define MC_PHY_TIMING_D1__RXC1_EXT_MASK 0xf000
10232 #define MC_PHY_TIMING_D1__RXC1_EXT__SHIFT 0xc
10233 #define MC_PHY_TIMING_D1__TXC0_DLY_MASK 0x70000
10234 #define MC_PHY_TIMING_D1__TXC0_DLY__SHIFT 0x10
10235 #define MC_PHY_TIMING_D1__TXC0_EXT_MASK 0xf00000
10236 #define MC_PHY_TIMING_D1__TXC0_EXT__SHIFT 0x14
10237 #define MC_PHY_TIMING_D1__TXC1_DLY_MASK 0x7000000
10238 #define MC_PHY_TIMING_D1__TXC1_DLY__SHIFT 0x18
10239 #define MC_PHY_TIMING_D1__TXC1_EXT_MASK 0xf0000000
10240 #define MC_PHY_TIMING_D1__TXC1_EXT__SHIFT 0x1c
10241 #define MC_PHY_TIMING_2__IND_LD_CNT_MASK 0x7f
10242 #define MC_PHY_TIMING_2__IND_LD_CNT__SHIFT 0x0
10243 #define MC_PHY_TIMING_2__RXC0_INV_MASK 0x100
10244 #define MC_PHY_TIMING_2__RXC0_INV__SHIFT 0x8
10245 #define MC_PHY_TIMING_2__RXC1_INV_MASK 0x200
10246 #define MC_PHY_TIMING_2__RXC1_INV__SHIFT 0x9
10247 #define MC_PHY_TIMING_2__TXC0_INV_MASK 0x400
10248 #define MC_PHY_TIMING_2__TXC0_INV__SHIFT 0xa
10249 #define MC_PHY_TIMING_2__TXC1_INV_MASK 0x800
10250 #define MC_PHY_TIMING_2__TXC1_INV__SHIFT 0xb
10251 #define MC_PHY_TIMING_2__RXC0_FRC_MASK 0x1000
10252 #define MC_PHY_TIMING_2__RXC0_FRC__SHIFT 0xc
10253 #define MC_PHY_TIMING_2__RXC1_FRC_MASK 0x2000
10254 #define MC_PHY_TIMING_2__RXC1_FRC__SHIFT 0xd
10255 #define MC_PHY_TIMING_2__TXC0_FRC_MASK 0x4000
10256 #define MC_PHY_TIMING_2__TXC0_FRC__SHIFT 0xe
10257 #define MC_PHY_TIMING_2__TXC1_FRC_MASK 0x8000
10258 #define MC_PHY_TIMING_2__TXC1_FRC__SHIFT 0xf
10259 #define MC_PHY_TIMING_2__TX_CDREN_D0_MASK 0x10000
10260 #define MC_PHY_TIMING_2__TX_CDREN_D0__SHIFT 0x10
10261 #define MC_PHY_TIMING_2__TX_CDREN_D1_MASK 0x20000
10262 #define MC_PHY_TIMING_2__TX_CDREN_D1__SHIFT 0x11
10263 #define MC_PHY_TIMING_2__ADR_CLKEN_D0_MASK 0x40000
10264 #define MC_PHY_TIMING_2__ADR_CLKEN_D0__SHIFT 0x12
10265 #define MC_PHY_TIMING_2__ADR_CLKEN_D1_MASK 0x80000
10266 #define MC_PHY_TIMING_2__ADR_CLKEN_D1__SHIFT 0x13
10267 #define MC_PHY_TIMING_2__WR_DLY_MASK 0xf00000
10268 #define MC_PHY_TIMING_2__WR_DLY__SHIFT 0x14
10269 #define MC_PHY_TIMING_2__RXDPWRONC0_FRC_MASK 0x1000000
10270 #define MC_PHY_TIMING_2__RXDPWRONC0_FRC__SHIFT 0x18
10271 #define MC_PHY_TIMING_2__RXDPWRONC1_FRC_MASK 0x2000000
10272 #define MC_PHY_TIMING_2__RXDPWRONC1_FRC__SHIFT 0x19
10273 #define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE_MASK 0x1
10274 #define MC_SEQ_MPLL_OVERRIDE__AD_PLL_RESET_OVERRIDE__SHIFT 0x0
10275 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE_MASK 0x2
10276 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_0_PLL_RESET_OVERRIDE__SHIFT 0x1
10277 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE_MASK 0x4
10278 #define MC_SEQ_MPLL_OVERRIDE__DQ_0_1_PLL_RESET_OVERRIDE__SHIFT 0x2
10279 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE_MASK 0x8
10280 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_0_PLL_RESET_OVERRIDE__SHIFT 0x3
10281 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE_MASK 0x10
10282 #define MC_SEQ_MPLL_OVERRIDE__DQ_1_1_PLL_RESET_OVERRIDE__SHIFT 0x4
10283 #define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE_MASK 0x20
10284 #define MC_SEQ_MPLL_OVERRIDE__ATGM_CLK_SEL_OVERRIDE__SHIFT 0x5
10285 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE_MASK 0x40
10286 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_EN_OVERRIDE__SHIFT 0x6
10287 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE_MASK 0x80
10288 #define MC_SEQ_MPLL_OVERRIDE__TEST_BYPASS_CLK_SEL_OVERRIDE__SHIFT 0x7
10289 #define MCLK_PWRMGT_CNTL__DLL_SPEED_MASK 0x1f
10290 #define MCLK_PWRMGT_CNTL__DLL_SPEED__SHIFT 0x0
10291 #define MCLK_PWRMGT_CNTL__DLL_READY_MASK 0x40
10292 #define MCLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x6
10293 #define MCLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x80
10294 #define MCLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x7
10295 #define MCLK_PWRMGT_CNTL__MRDCK0_PDNB_MASK 0x100
10296 #define MCLK_PWRMGT_CNTL__MRDCK0_PDNB__SHIFT 0x8
10297 #define MCLK_PWRMGT_CNTL__MRDCK1_PDNB_MASK 0x200
10298 #define MCLK_PWRMGT_CNTL__MRDCK1_PDNB__SHIFT 0x9
10299 #define MCLK_PWRMGT_CNTL__MRDCK0_RESET_MASK 0x10000
10300 #define MCLK_PWRMGT_CNTL__MRDCK0_RESET__SHIFT 0x10
10301 #define MCLK_PWRMGT_CNTL__MRDCK1_RESET_MASK 0x20000
10302 #define MCLK_PWRMGT_CNTL__MRDCK1_RESET__SHIFT 0x11
10303 #define MCLK_PWRMGT_CNTL__DLL_READY_READ_MASK 0x1000000
10304 #define MCLK_PWRMGT_CNTL__DLL_READY_READ__SHIFT 0x18
10305 #define DLL_CNTL__DLL_RESET_TIME_MASK 0x3ff
10306 #define DLL_CNTL__DLL_RESET_TIME__SHIFT 0x0
10307 #define DLL_CNTL__DLL_LOCK_TIME_MASK 0x3ff000
10308 #define DLL_CNTL__DLL_LOCK_TIME__SHIFT 0xc
10309 #define DLL_CNTL__MRDCK0_BYPASS_MASK 0x1000000
10310 #define DLL_CNTL__MRDCK0_BYPASS__SHIFT 0x18
10311 #define DLL_CNTL__MRDCK1_BYPASS_MASK 0x2000000
10312 #define DLL_CNTL__MRDCK1_BYPASS__SHIFT 0x19
10313 #define DLL_CNTL__PWR2_MODE_MASK 0x4000000
10314 #define DLL_CNTL__PWR2_MODE__SHIFT 0x1a
10315 #define MPLL_SEQ_UCODE_1__INSTR0_MASK 0xf
10316 #define MPLL_SEQ_UCODE_1__INSTR0__SHIFT 0x0
10317 #define MPLL_SEQ_UCODE_1__INSTR1_MASK 0xf0
10318 #define MPLL_SEQ_UCODE_1__INSTR1__SHIFT 0x4
10319 #define MPLL_SEQ_UCODE_1__INSTR2_MASK 0xf00
10320 #define MPLL_SEQ_UCODE_1__INSTR2__SHIFT 0x8
10321 #define MPLL_SEQ_UCODE_1__INSTR3_MASK 0xf000
10322 #define MPLL_SEQ_UCODE_1__INSTR3__SHIFT 0xc
10323 #define MPLL_SEQ_UCODE_1__INSTR4_MASK 0xf0000
10324 #define MPLL_SEQ_UCODE_1__INSTR4__SHIFT 0x10
10325 #define MPLL_SEQ_UCODE_1__INSTR5_MASK 0xf00000
10326 #define MPLL_SEQ_UCODE_1__INSTR5__SHIFT 0x14
10327 #define MPLL_SEQ_UCODE_1__INSTR6_MASK 0xf000000
10328 #define MPLL_SEQ_UCODE_1__INSTR6__SHIFT 0x18
10329 #define MPLL_SEQ_UCODE_1__INSTR7_MASK 0xf0000000
10330 #define MPLL_SEQ_UCODE_1__INSTR7__SHIFT 0x1c
10331 #define MPLL_SEQ_UCODE_2__INSTR8_MASK 0xf
10332 #define MPLL_SEQ_UCODE_2__INSTR8__SHIFT 0x0
10333 #define MPLL_SEQ_UCODE_2__INSTR9_MASK 0xf0
10334 #define MPLL_SEQ_UCODE_2__INSTR9__SHIFT 0x4
10335 #define MPLL_SEQ_UCODE_2__INSTR10_MASK 0xf00
10336 #define MPLL_SEQ_UCODE_2__INSTR10__SHIFT 0x8
10337 #define MPLL_SEQ_UCODE_2__INSTR11_MASK 0xf000
10338 #define MPLL_SEQ_UCODE_2__INSTR11__SHIFT 0xc
10339 #define MPLL_SEQ_UCODE_2__INSTR12_MASK 0xf0000
10340 #define MPLL_SEQ_UCODE_2__INSTR12__SHIFT 0x10
10341 #define MPLL_SEQ_UCODE_2__INSTR13_MASK 0xf00000
10342 #define MPLL_SEQ_UCODE_2__INSTR13__SHIFT 0x14
10343 #define MPLL_SEQ_UCODE_2__INSTR14_MASK 0xf000000
10344 #define MPLL_SEQ_UCODE_2__INSTR14__SHIFT 0x18
10345 #define MPLL_SEQ_UCODE_2__INSTR15_MASK 0xf0000000
10346 #define MPLL_SEQ_UCODE_2__INSTR15__SHIFT 0x1c
10347 #define MPLL_CNTL_MODE__INSTR_DELAY_MASK 0xff
10348 #define MPLL_CNTL_MODE__INSTR_DELAY__SHIFT 0x0
10349 #define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL_MASK 0x100
10350 #define MPLL_CNTL_MODE__MPLL_SW_DIR_CONTROL__SHIFT 0x8
10351 #define MPLL_CNTL_MODE__GDDR_PWRON_OVR_MASK 0x200
10352 #define MPLL_CNTL_MODE__GDDR_PWRON_OVR__SHIFT 0x9
10353 #define MPLL_CNTL_MODE__MPLL_MCLK_SEL_MASK 0x800
10354 #define MPLL_CNTL_MODE__MPLL_MCLK_SEL__SHIFT 0xb
10355 #define MPLL_CNTL_MODE__SPARE_1_MASK 0x1000
10356 #define MPLL_CNTL_MODE__SPARE_1__SHIFT 0xc
10357 #define MPLL_CNTL_MODE__QDR_MASK 0x2000
10358 #define MPLL_CNTL_MODE__QDR__SHIFT 0xd
10359 #define MPLL_CNTL_MODE__MPLL_CTLREQ_MASK 0x4000
10360 #define MPLL_CNTL_MODE__MPLL_CTLREQ__SHIFT 0xe
10361 #define MPLL_CNTL_MODE__MPLL_CHG_STATUS_MASK 0x10000
10362 #define MPLL_CNTL_MODE__MPLL_CHG_STATUS__SHIFT 0x10
10363 #define MPLL_CNTL_MODE__FORCE_TESTMODE_MASK 0x20000
10364 #define MPLL_CNTL_MODE__FORCE_TESTMODE__SHIFT 0x11
10365 #define MPLL_CNTL_MODE__FAST_LOCK_EN_MASK 0x100000
10366 #define MPLL_CNTL_MODE__FAST_LOCK_EN__SHIFT 0x14
10367 #define MPLL_CNTL_MODE__FAST_LOCK_CNTRL_MASK 0x600000
10368 #define MPLL_CNTL_MODE__FAST_LOCK_CNTRL__SHIFT 0x15
10369 #define MPLL_CNTL_MODE__SPARE_2_MASK 0x800000
10370 #define MPLL_CNTL_MODE__SPARE_2__SHIFT 0x17
10371 #define MPLL_CNTL_MODE__SS_SSEN_MASK 0x3000000
10372 #define MPLL_CNTL_MODE__SS_SSEN__SHIFT 0x18
10373 #define MPLL_CNTL_MODE__SS_DSMODE_EN_MASK 0x4000000
10374 #define MPLL_CNTL_MODE__SS_DSMODE_EN__SHIFT 0x1a
10375 #define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL_MASK 0x8000000
10376 #define MPLL_CNTL_MODE__VTOI_BIAS_CNTRL__SHIFT 0x1b
10377 #define MPLL_CNTL_MODE__SPARE_3_MASK 0x70000000
10378 #define MPLL_CNTL_MODE__SPARE_3__SHIFT 0x1c
10379 #define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET_MASK 0x80000000
10380 #define MPLL_CNTL_MODE__GLOBAL_MPLL_RESET__SHIFT 0x1f
10381 #define MPLL_FUNC_CNTL__SPARE_0_MASK 0x20
10382 #define MPLL_FUNC_CNTL__SPARE_0__SHIFT 0x5
10383 #define MPLL_FUNC_CNTL__BG_100ADJ_MASK 0xf00
10384 #define MPLL_FUNC_CNTL__BG_100ADJ__SHIFT 0x8
10385 #define MPLL_FUNC_CNTL__BG_135ADJ_MASK 0xf0000
10386 #define MPLL_FUNC_CNTL__BG_135ADJ__SHIFT 0x10
10387 #define MPLL_FUNC_CNTL__BWCTRL_MASK 0xff00000
10388 #define MPLL_FUNC_CNTL__BWCTRL__SHIFT 0x14
10389 #define MPLL_FUNC_CNTL__REG_BIAS_MASK 0xc0000000
10390 #define MPLL_FUNC_CNTL__REG_BIAS__SHIFT 0x1e
10391 #define MPLL_FUNC_CNTL_1__VCO_MODE_MASK 0x3
10392 #define MPLL_FUNC_CNTL_1__VCO_MODE__SHIFT 0x0
10393 #define MPLL_FUNC_CNTL_1__SPARE_0_MASK 0xc
10394 #define MPLL_FUNC_CNTL_1__SPARE_0__SHIFT 0x2
10395 #define MPLL_FUNC_CNTL_1__CLKFRAC_MASK 0xfff0
10396 #define MPLL_FUNC_CNTL_1__CLKFRAC__SHIFT 0x4
10397 #define MPLL_FUNC_CNTL_1__CLKF_MASK 0xfff0000
10398 #define MPLL_FUNC_CNTL_1__CLKF__SHIFT 0x10
10399 #define MPLL_FUNC_CNTL_1__SPARE_1_MASK 0xf0000000
10400 #define MPLL_FUNC_CNTL_1__SPARE_1__SHIFT 0x1c
10401 #define MPLL_FUNC_CNTL_2__VCTRLADC_EN_MASK 0x1
10402 #define MPLL_FUNC_CNTL_2__VCTRLADC_EN__SHIFT 0x0
10403 #define MPLL_FUNC_CNTL_2__TEST_VCTL_EN_MASK 0x2
10404 #define MPLL_FUNC_CNTL_2__TEST_VCTL_EN__SHIFT 0x1
10405 #define MPLL_FUNC_CNTL_2__RESET_EN_MASK 0x4
10406 #define MPLL_FUNC_CNTL_2__RESET_EN__SHIFT 0x2
10407 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN_MASK 0x8
10408 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_EN__SHIFT 0x3
10409 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC_MASK 0x10
10410 #define MPLL_FUNC_CNTL_2__TEST_BYPCLK_SRC__SHIFT 0x4
10411 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS_MASK 0x20
10412 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_FRAC_BYPASS__SHIFT 0x5
10413 #define MPLL_FUNC_CNTL_2__TEST_BYPMCLK_MASK 0x40
10414 #define MPLL_FUNC_CNTL_2__TEST_BYPMCLK__SHIFT 0x6
10415 #define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR_MASK 0x80
10416 #define MPLL_FUNC_CNTL_2__MPLL_UNLOCK_CLEAR__SHIFT 0x7
10417 #define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL_MASK 0x100
10418 #define MPLL_FUNC_CNTL_2__TEST_VCTL_CNTRL__SHIFT 0x8
10419 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS_MASK 0x200
10420 #define MPLL_FUNC_CNTL_2__TEST_FBDIV_SSC_BYPASS__SHIFT 0x9
10421 #define MPLL_FUNC_CNTL_2__RESET_TIMER_MASK 0xc00
10422 #define MPLL_FUNC_CNTL_2__RESET_TIMER__SHIFT 0xa
10423 #define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL_MASK 0x3000
10424 #define MPLL_FUNC_CNTL_2__PFD_RESET_CNTRL__SHIFT 0xc
10425 #define MPLL_FUNC_CNTL_2__RISEFBVCO_EN_MASK 0x4000
10426 #define MPLL_FUNC_CNTL_2__RISEFBVCO_EN__SHIFT 0xe
10427 #define MPLL_FUNC_CNTL_2__PWRGOOD_OVR_MASK 0x8000
10428 #define MPLL_FUNC_CNTL_2__PWRGOOD_OVR__SHIFT 0xf
10429 #define MPLL_FUNC_CNTL_2__ISO_DIS_P_MASK 0x10000
10430 #define MPLL_FUNC_CNTL_2__ISO_DIS_P__SHIFT 0x10
10431 #define MPLL_FUNC_CNTL_2__BACKUP_2_MASK 0xe0000
10432 #define MPLL_FUNC_CNTL_2__BACKUP_2__SHIFT 0x11
10433 #define MPLL_FUNC_CNTL_2__LF_CNTRL_MASK 0x7f00000
10434 #define MPLL_FUNC_CNTL_2__LF_CNTRL__SHIFT 0x14
10435 #define MPLL_FUNC_CNTL_2__BACKUP_MASK 0xf8000000
10436 #define MPLL_FUNC_CNTL_2__BACKUP__SHIFT 0x1b
10437 #define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
10438 #define MPLL_AD_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
10439 #define MPLL_AD_FUNC_CNTL__SPARE_MASK 0xfffffff8
10440 #define MPLL_AD_FUNC_CNTL__SPARE__SHIFT 0x3
10441 #define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV_MASK 0x7
10442 #define MPLL_DQ_FUNC_CNTL__YCLK_POST_DIV__SHIFT 0x0
10443 #define MPLL_DQ_FUNC_CNTL__SPARE_0_MASK 0x8
10444 #define MPLL_DQ_FUNC_CNTL__SPARE_0__SHIFT 0x3
10445 #define MPLL_DQ_FUNC_CNTL__YCLK_SEL_MASK 0x10
10446 #define MPLL_DQ_FUNC_CNTL__YCLK_SEL__SHIFT 0x4
10447 #define MPLL_DQ_FUNC_CNTL__SPARE_MASK 0xffffffe0
10448 #define MPLL_DQ_FUNC_CNTL__SPARE__SHIFT 0x5
10449 #define MPLL_TIME__MPLL_LOCK_TIME_MASK 0xffff
10450 #define MPLL_TIME__MPLL_LOCK_TIME__SHIFT 0x0
10451 #define MPLL_TIME__MPLL_RESET_TIME_MASK 0xffff0000
10452 #define MPLL_TIME__MPLL_RESET_TIME__SHIFT 0x10
10453 #define MPLL_SS1__CLKV_MASK 0x3ffffff
10454 #define MPLL_SS1__CLKV__SHIFT 0x0
10455 #define MPLL_SS1__SPARE_MASK 0xfc000000
10456 #define MPLL_SS1__SPARE__SHIFT 0x1a
10457 #define MPLL_SS2__CLKS_MASK 0xfff
10458 #define MPLL_SS2__CLKS__SHIFT 0x0
10459 #define MPLL_SS2__SPARE_MASK 0xfffff000
10460 #define MPLL_SS2__SPARE__SHIFT 0xc
10461 #define MPLL_CONTROL__GDDR_PWRON_MASK 0x1
10462 #define MPLL_CONTROL__GDDR_PWRON__SHIFT 0x0
10463 #define MPLL_CONTROL__REFCLK_PWRON_MASK 0x2
10464 #define MPLL_CONTROL__REFCLK_PWRON__SHIFT 0x1
10465 #define MPLL_CONTROL__PLL_BUF_PWRON_TX_MASK 0x4
10466 #define MPLL_CONTROL__PLL_BUF_PWRON_TX__SHIFT 0x2
10467 #define MPLL_CONTROL__AD_BG_PWRON_MASK 0x1000
10468 #define MPLL_CONTROL__AD_BG_PWRON__SHIFT 0xc
10469 #define MPLL_CONTROL__AD_PLL_PWRON_MASK 0x2000
10470 #define MPLL_CONTROL__AD_PLL_PWRON__SHIFT 0xd
10471 #define MPLL_CONTROL__AD_PLL_RESET_MASK 0x4000
10472 #define MPLL_CONTROL__AD_PLL_RESET__SHIFT 0xe
10473 #define MPLL_CONTROL__SPARE_AD_0_MASK 0x8000
10474 #define MPLL_CONTROL__SPARE_AD_0__SHIFT 0xf
10475 #define MPLL_CONTROL__DQ_0_0_BG_PWRON_MASK 0x10000
10476 #define MPLL_CONTROL__DQ_0_0_BG_PWRON__SHIFT 0x10
10477 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON_MASK 0x20000
10478 #define MPLL_CONTROL__DQ_0_0_PLL_PWRON__SHIFT 0x11
10479 #define MPLL_CONTROL__DQ_0_0_PLL_RESET_MASK 0x40000
10480 #define MPLL_CONTROL__DQ_0_0_PLL_RESET__SHIFT 0x12
10481 #define MPLL_CONTROL__SPARE_DQ_0_0_MASK 0x80000
10482 #define MPLL_CONTROL__SPARE_DQ_0_0__SHIFT 0x13
10483 #define MPLL_CONTROL__DQ_0_1_BG_PWRON_MASK 0x100000
10484 #define MPLL_CONTROL__DQ_0_1_BG_PWRON__SHIFT 0x14
10485 #define MPLL_CONTROL__DQ_0_1_PLL_PWRON_MASK 0x200000
10486 #define MPLL_CONTROL__DQ_0_1_PLL_PWRON__SHIFT 0x15
10487 #define MPLL_CONTROL__DQ_0_1_PLL_RESET_MASK 0x400000
10488 #define MPLL_CONTROL__DQ_0_1_PLL_RESET__SHIFT 0x16
10489 #define MPLL_CONTROL__SPARE_DQ_0_1_MASK 0x800000
10490 #define MPLL_CONTROL__SPARE_DQ_0_1__SHIFT 0x17
10491 #define MPLL_CONTROL__DQ_1_0_BG_PWRON_MASK 0x1000000
10492 #define MPLL_CONTROL__DQ_1_0_BG_PWRON__SHIFT 0x18
10493 #define MPLL_CONTROL__DQ_1_0_PLL_PWRON_MASK 0x2000000
10494 #define MPLL_CONTROL__DQ_1_0_PLL_PWRON__SHIFT 0x19
10495 #define MPLL_CONTROL__DQ_1_0_PLL_RESET_MASK 0x4000000
10496 #define MPLL_CONTROL__DQ_1_0_PLL_RESET__SHIFT 0x1a
10497 #define MPLL_CONTROL__SPARE_DQ_1_0_MASK 0x8000000
10498 #define MPLL_CONTROL__SPARE_DQ_1_0__SHIFT 0x1b
10499 #define MPLL_CONTROL__DQ_1_1_BG_PWRON_MASK 0x10000000
10500 #define MPLL_CONTROL__DQ_1_1_BG_PWRON__SHIFT 0x1c
10501 #define MPLL_CONTROL__DQ_1_1_PLL_PWRON_MASK 0x20000000
10502 #define MPLL_CONTROL__DQ_1_1_PLL_PWRON__SHIFT 0x1d
10503 #define MPLL_CONTROL__DQ_1_1_PLL_RESET_MASK 0x40000000
10504 #define MPLL_CONTROL__DQ_1_1_PLL_RESET__SHIFT 0x1e
10505 #define MPLL_CONTROL__SPARE_DQ_1_1_MASK 0x80000000
10506 #define MPLL_CONTROL__SPARE_DQ_1_1__SHIFT 0x1f
10507 #define MPLL_AD_STATUS__VCTRLADC_MASK 0x7
10508 #define MPLL_AD_STATUS__VCTRLADC__SHIFT 0x0
10509 #define MPLL_AD_STATUS__TEST_FBDIV_FRAC_MASK 0x70
10510 #define MPLL_AD_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
10511 #define MPLL_AD_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
10512 #define MPLL_AD_STATUS__TEST_FBDIV_INT__SHIFT 0x7
10513 #define MPLL_AD_STATUS__OINT_RESET_MASK 0x20000
10514 #define MPLL_AD_STATUS__OINT_RESET__SHIFT 0x11
10515 #define MPLL_AD_STATUS__FREQ_LOCK_MASK 0x40000
10516 #define MPLL_AD_STATUS__FREQ_LOCK__SHIFT 0x12
10517 #define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
10518 #define MPLL_AD_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
10519 #define MPLL_DQ_0_0_STATUS__VCTRLADC_MASK 0x7
10520 #define MPLL_DQ_0_0_STATUS__VCTRLADC__SHIFT 0x0
10521 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
10522 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
10523 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
10524 #define MPLL_DQ_0_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
10525 #define MPLL_DQ_0_0_STATUS__OINT_RESET_MASK 0x20000
10526 #define MPLL_DQ_0_0_STATUS__OINT_RESET__SHIFT 0x11
10527 #define MPLL_DQ_0_0_STATUS__FREQ_LOCK_MASK 0x40000
10528 #define MPLL_DQ_0_0_STATUS__FREQ_LOCK__SHIFT 0x12
10529 #define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
10530 #define MPLL_DQ_0_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
10531 #define MPLL_DQ_0_1_STATUS__VCTRLADC_MASK 0x7
10532 #define MPLL_DQ_0_1_STATUS__VCTRLADC__SHIFT 0x0
10533 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
10534 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
10535 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
10536 #define MPLL_DQ_0_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
10537 #define MPLL_DQ_0_1_STATUS__OINT_RESET_MASK 0x20000
10538 #define MPLL_DQ_0_1_STATUS__OINT_RESET__SHIFT 0x11
10539 #define MPLL_DQ_0_1_STATUS__FREQ_LOCK_MASK 0x40000
10540 #define MPLL_DQ_0_1_STATUS__FREQ_LOCK__SHIFT 0x12
10541 #define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
10542 #define MPLL_DQ_0_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
10543 #define MPLL_DQ_1_0_STATUS__VCTRLADC_MASK 0x7
10544 #define MPLL_DQ_1_0_STATUS__VCTRLADC__SHIFT 0x0
10545 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC_MASK 0x70
10546 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
10547 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
10548 #define MPLL_DQ_1_0_STATUS__TEST_FBDIV_INT__SHIFT 0x7
10549 #define MPLL_DQ_1_0_STATUS__OINT_RESET_MASK 0x20000
10550 #define MPLL_DQ_1_0_STATUS__OINT_RESET__SHIFT 0x11
10551 #define MPLL_DQ_1_0_STATUS__FREQ_LOCK_MASK 0x40000
10552 #define MPLL_DQ_1_0_STATUS__FREQ_LOCK__SHIFT 0x12
10553 #define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
10554 #define MPLL_DQ_1_0_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
10555 #define MPLL_DQ_1_1_STATUS__VCTRLADC_MASK 0x7
10556 #define MPLL_DQ_1_1_STATUS__VCTRLADC__SHIFT 0x0
10557 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC_MASK 0x70
10558 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_FRAC__SHIFT 0x4
10559 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT_MASK 0x1ff80
10560 #define MPLL_DQ_1_1_STATUS__TEST_FBDIV_INT__SHIFT 0x7
10561 #define MPLL_DQ_1_1_STATUS__OINT_RESET_MASK 0x20000
10562 #define MPLL_DQ_1_1_STATUS__OINT_RESET__SHIFT 0x11
10563 #define MPLL_DQ_1_1_STATUS__FREQ_LOCK_MASK 0x40000
10564 #define MPLL_DQ_1_1_STATUS__FREQ_LOCK__SHIFT 0x12
10565 #define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY_MASK 0x80000
10566 #define MPLL_DQ_1_1_STATUS__FREQ_UNLOCK_STICKY__SHIFT 0x13
10567 #define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN_MASK 0x1
10568 #define MC_SEQ_PMG_PG_HWCNTL__PWRGATE_EN__SHIFT 0x0
10569 #define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN_MASK 0x2
10570 #define MC_SEQ_PMG_PG_HWCNTL__STAGGER_EN__SHIFT 0x1
10571 #define MC_SEQ_PMG_PG_HWCNTL__TPGCG_MASK 0x3c
10572 #define MC_SEQ_PMG_PG_HWCNTL__TPGCG__SHIFT 0x2
10573 #define MC_SEQ_PMG_PG_HWCNTL__D_DLY_MASK 0xc0
10574 #define MC_SEQ_PMG_PG_HWCNTL__D_DLY__SHIFT 0x6
10575 #define MC_SEQ_PMG_PG_HWCNTL__AC_DLY_MASK 0x300
10576 #define MC_SEQ_PMG_PG_HWCNTL__AC_DLY__SHIFT 0x8
10577 #define MC_SEQ_PMG_PG_HWCNTL__G_DLY_MASK 0x3c00
10578 #define MC_SEQ_PMG_PG_HWCNTL__G_DLY__SHIFT 0xa
10579 #define MC_SEQ_PMG_PG_HWCNTL__TXAO_MASK 0x10000
10580 #define MC_SEQ_PMG_PG_HWCNTL__TXAO__SHIFT 0x10
10581 #define MC_SEQ_PMG_PG_HWCNTL__RXAO_MASK 0x20000
10582 #define MC_SEQ_PMG_PG_HWCNTL__RXAO__SHIFT 0x11
10583 #define MC_SEQ_PMG_PG_HWCNTL__ACAO_MASK 0x40000
10584 #define MC_SEQ_PMG_PG_HWCNTL__ACAO__SHIFT 0x12
10585 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB_MASK 0x1
10586 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_TX_ENB__SHIFT 0x0
10587 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB_MASK 0x2
10588 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_TX_ENB__SHIFT 0x1
10589 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB_MASK 0x4
10590 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_TX_ENB__SHIFT 0x2
10591 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB_MASK 0x8
10592 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_TX_ENB__SHIFT 0x3
10593 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB_MASK 0x10
10594 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DQ_RX_ENB__SHIFT 0x4
10595 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB_MASK 0x20
10596 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_DBI_RX_ENB__SHIFT 0x5
10597 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB_MASK 0x40
10598 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_EDC_RX_ENB__SHIFT 0x6
10599 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB_MASK 0x80
10600 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD0_WCLKX_RX_ENB__SHIFT 0x7
10601 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB_MASK 0x100
10602 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_TX_ENB__SHIFT 0x8
10603 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB_MASK 0x200
10604 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_TX_ENB__SHIFT 0x9
10605 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB_MASK 0x400
10606 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_TX_ENB__SHIFT 0xa
10607 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB_MASK 0x800
10608 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_TX_ENB__SHIFT 0xb
10609 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB_MASK 0x1000
10610 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DQ_RX_ENB__SHIFT 0xc
10611 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB_MASK 0x2000
10612 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_DBI_RX_ENB__SHIFT 0xd
10613 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB_MASK 0x4000
10614 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_EDC_RX_ENB__SHIFT 0xe
10615 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB_MASK 0x8000
10616 #define MC_SEQ_PMG_PG_SWCNTL_0__PMD1_WCLKX_RX_ENB__SHIFT 0xf
10617 #define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB_MASK 0x10000
10618 #define MC_SEQ_PMG_PG_SWCNTL_0__PMA0_AC_ENB__SHIFT 0x10
10619 #define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT_MASK 0x80000000
10620 #define MC_SEQ_PMG_PG_SWCNTL_0__GMCON_SR_COMMIT__SHIFT 0x1f
10621 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB_MASK 0x1
10622 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_TX_ENB__SHIFT 0x0
10623 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB_MASK 0x2
10624 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_TX_ENB__SHIFT 0x1
10625 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB_MASK 0x4
10626 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_TX_ENB__SHIFT 0x2
10627 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB_MASK 0x8
10628 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_TX_ENB__SHIFT 0x3
10629 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB_MASK 0x10
10630 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DQ_RX_ENB__SHIFT 0x4
10631 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB_MASK 0x20
10632 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_DBI_RX_ENB__SHIFT 0x5
10633 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB_MASK 0x40
10634 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_EDC_RX_ENB__SHIFT 0x6
10635 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB_MASK 0x80
10636 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD2_WCLKX_RX_ENB__SHIFT 0x7
10637 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB_MASK 0x100
10638 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_TX_ENB__SHIFT 0x8
10639 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB_MASK 0x200
10640 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_TX_ENB__SHIFT 0x9
10641 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB_MASK 0x400
10642 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_TX_ENB__SHIFT 0xa
10643 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB_MASK 0x800
10644 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_TX_ENB__SHIFT 0xb
10645 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB_MASK 0x1000
10646 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DQ_RX_ENB__SHIFT 0xc
10647 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB_MASK 0x2000
10648 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_DBI_RX_ENB__SHIFT 0xd
10649 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB_MASK 0x4000
10650 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_EDC_RX_ENB__SHIFT 0xe
10651 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB_MASK 0x8000
10652 #define MC_SEQ_PMG_PG_SWCNTL_1__PMD3_WCLKX_RX_ENB__SHIFT 0xf
10653 #define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB_MASK 0x10000
10654 #define MC_SEQ_PMG_PG_SWCNTL_1__PMA1_AC_ENB__SHIFT 0x10
10655 #define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT_MASK 0x80000000
10656 #define MC_SEQ_PMG_PG_SWCNTL_1__GMCON_SR_COMMIT__SHIFT 0x1f
10657 #define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX_MASK 0x1f
10658 #define MC_SEQ_TSM_DEBUG_INDEX__TSM_DEBUG_INDEX__SHIFT 0x0
10659 #define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA_MASK 0xffffffff
10660 #define MC_SEQ_TSM_DEBUG_DATA__TSM_DEBUG_DATA__SHIFT 0x0
10661 #define MC_TSM_DEBUG_GCNT__DATA_MASK 0xffffffff
10662 #define MC_TSM_DEBUG_GCNT__DATA__SHIFT 0x0
10663 #define MC_TSM_DEBUG_FLAG__DATA_MASK 0xffffffff
10664 #define MC_TSM_DEBUG_FLAG__DATA__SHIFT 0x0
10665 #define MC_TSM_DEBUG_MISC__FLAG_MASK 0xff
10666 #define MC_TSM_DEBUG_MISC__FLAG__SHIFT 0x0
10667 #define MC_TSM_DEBUG_MISC__NCNT_RD_MASK 0xf00
10668 #define MC_TSM_DEBUG_MISC__NCNT_RD__SHIFT 0x8
10669 #define MC_TSM_DEBUG_MISC__NCNT_WR_MASK 0xf000
10670 #define MC_TSM_DEBUG_MISC__NCNT_WR__SHIFT 0xc
10671 #define MC_TSM_DEBUG_BCNT0__BYTE0_MASK 0xff
10672 #define MC_TSM_DEBUG_BCNT0__BYTE0__SHIFT 0x0
10673 #define MC_TSM_DEBUG_BCNT0__BYTE1_MASK 0xff00
10674 #define MC_TSM_DEBUG_BCNT0__BYTE1__SHIFT 0x8
10675 #define MC_TSM_DEBUG_BCNT0__BYTE2_MASK 0xff0000
10676 #define MC_TSM_DEBUG_BCNT0__BYTE2__SHIFT 0x10
10677 #define MC_TSM_DEBUG_BCNT0__BYTE3_MASK 0xff000000
10678 #define MC_TSM_DEBUG_BCNT0__BYTE3__SHIFT 0x18
10679 #define MC_TSM_DEBUG_BCNT1__BYTE0_MASK 0xff
10680 #define MC_TSM_DEBUG_BCNT1__BYTE0__SHIFT 0x0
10681 #define MC_TSM_DEBUG_BCNT1__BYTE1_MASK 0xff00
10682 #define MC_TSM_DEBUG_BCNT1__BYTE1__SHIFT 0x8
10683 #define MC_TSM_DEBUG_BCNT1__BYTE2_MASK 0xff0000
10684 #define MC_TSM_DEBUG_BCNT1__BYTE2__SHIFT 0x10
10685 #define MC_TSM_DEBUG_BCNT1__BYTE3_MASK 0xff000000
10686 #define MC_TSM_DEBUG_BCNT1__BYTE3__SHIFT 0x18
10687 #define MC_TSM_DEBUG_BCNT2__BYTE0_MASK 0xff
10688 #define MC_TSM_DEBUG_BCNT2__BYTE0__SHIFT 0x0
10689 #define MC_TSM_DEBUG_BCNT2__BYTE1_MASK 0xff00
10690 #define MC_TSM_DEBUG_BCNT2__BYTE1__SHIFT 0x8
10691 #define MC_TSM_DEBUG_BCNT2__BYTE2_MASK 0xff0000
10692 #define MC_TSM_DEBUG_BCNT2__BYTE2__SHIFT 0x10
10693 #define MC_TSM_DEBUG_BCNT2__BYTE3_MASK 0xff000000
10694 #define MC_TSM_DEBUG_BCNT2__BYTE3__SHIFT 0x18
10695 #define MC_TSM_DEBUG_BCNT3__BYTE0_MASK 0xff
10696 #define MC_TSM_DEBUG_BCNT3__BYTE0__SHIFT 0x0
10697 #define MC_TSM_DEBUG_BCNT3__BYTE1_MASK 0xff00
10698 #define MC_TSM_DEBUG_BCNT3__BYTE1__SHIFT 0x8
10699 #define MC_TSM_DEBUG_BCNT3__BYTE2_MASK 0xff0000
10700 #define MC_TSM_DEBUG_BCNT3__BYTE2__SHIFT 0x10
10701 #define MC_TSM_DEBUG_BCNT3__BYTE3_MASK 0xff000000
10702 #define MC_TSM_DEBUG_BCNT3__BYTE3__SHIFT 0x18
10703 #define MC_TSM_DEBUG_BCNT4__BYTE0_MASK 0xff
10704 #define MC_TSM_DEBUG_BCNT4__BYTE0__SHIFT 0x0
10705 #define MC_TSM_DEBUG_BCNT4__BYTE1_MASK 0xff00
10706 #define MC_TSM_DEBUG_BCNT4__BYTE1__SHIFT 0x8
10707 #define MC_TSM_DEBUG_BCNT4__BYTE2_MASK 0xff0000
10708 #define MC_TSM_DEBUG_BCNT4__BYTE2__SHIFT 0x10
10709 #define MC_TSM_DEBUG_BCNT4__BYTE3_MASK 0xff000000
10710 #define MC_TSM_DEBUG_BCNT4__BYTE3__SHIFT 0x18
10711 #define MC_TSM_DEBUG_BCNT5__BYTE0_MASK 0xff
10712 #define MC_TSM_DEBUG_BCNT5__BYTE0__SHIFT 0x0
10713 #define MC_TSM_DEBUG_BCNT5__BYTE1_MASK 0xff00
10714 #define MC_TSM_DEBUG_BCNT5__BYTE1__SHIFT 0x8
10715 #define MC_TSM_DEBUG_BCNT5__BYTE2_MASK 0xff0000
10716 #define MC_TSM_DEBUG_BCNT5__BYTE2__SHIFT 0x10
10717 #define MC_TSM_DEBUG_BCNT5__BYTE3_MASK 0xff000000
10718 #define MC_TSM_DEBUG_BCNT5__BYTE3__SHIFT 0x18
10719 #define MC_TSM_DEBUG_BCNT6__BYTE0_MASK 0xff
10720 #define MC_TSM_DEBUG_BCNT6__BYTE0__SHIFT 0x0
10721 #define MC_TSM_DEBUG_BCNT6__BYTE1_MASK 0xff00
10722 #define MC_TSM_DEBUG_BCNT6__BYTE1__SHIFT 0x8
10723 #define MC_TSM_DEBUG_BCNT6__BYTE2_MASK 0xff0000
10724 #define MC_TSM_DEBUG_BCNT6__BYTE2__SHIFT 0x10
10725 #define MC_TSM_DEBUG_BCNT6__BYTE3_MASK 0xff000000
10726 #define MC_TSM_DEBUG_BCNT6__BYTE3__SHIFT 0x18
10727 #define MC_TSM_DEBUG_BCNT7__BYTE0_MASK 0xff
10728 #define MC_TSM_DEBUG_BCNT7__BYTE0__SHIFT 0x0
10729 #define MC_TSM_DEBUG_BCNT7__BYTE1_MASK 0xff00
10730 #define MC_TSM_DEBUG_BCNT7__BYTE1__SHIFT 0x8
10731 #define MC_TSM_DEBUG_BCNT7__BYTE2_MASK 0xff0000
10732 #define MC_TSM_DEBUG_BCNT7__BYTE2__SHIFT 0x10
10733 #define MC_TSM_DEBUG_BCNT7__BYTE3_MASK 0xff000000
10734 #define MC_TSM_DEBUG_BCNT7__BYTE3__SHIFT 0x18
10735 #define MC_TSM_DEBUG_BCNT8__BYTE0_MASK 0xff
10736 #define MC_TSM_DEBUG_BCNT8__BYTE0__SHIFT 0x0
10737 #define MC_TSM_DEBUG_BCNT8__BYTE1_MASK 0xff00
10738 #define MC_TSM_DEBUG_BCNT8__BYTE1__SHIFT 0x8
10739 #define MC_TSM_DEBUG_BCNT8__BYTE2_MASK 0xff0000
10740 #define MC_TSM_DEBUG_BCNT8__BYTE2__SHIFT 0x10
10741 #define MC_TSM_DEBUG_BCNT8__BYTE3_MASK 0xff000000
10742 #define MC_TSM_DEBUG_BCNT8__BYTE3__SHIFT 0x18
10743 #define MC_TSM_DEBUG_BCNT9__BYTE0_MASK 0xff
10744 #define MC_TSM_DEBUG_BCNT9__BYTE0__SHIFT 0x0
10745 #define MC_TSM_DEBUG_BCNT9__BYTE1_MASK 0xff00
10746 #define MC_TSM_DEBUG_BCNT9__BYTE1__SHIFT 0x8
10747 #define MC_TSM_DEBUG_BCNT9__BYTE2_MASK 0xff0000
10748 #define MC_TSM_DEBUG_BCNT9__BYTE2__SHIFT 0x10
10749 #define MC_TSM_DEBUG_BCNT9__BYTE3_MASK 0xff000000
10750 #define MC_TSM_DEBUG_BCNT9__BYTE3__SHIFT 0x18
10751 #define MC_TSM_DEBUG_BCNT10__BYTE0_MASK 0xff
10752 #define MC_TSM_DEBUG_BCNT10__BYTE0__SHIFT 0x0
10753 #define MC_TSM_DEBUG_BCNT10__BYTE1_MASK 0xff00
10754 #define MC_TSM_DEBUG_BCNT10__BYTE1__SHIFT 0x8
10755 #define MC_TSM_DEBUG_BCNT10__BYTE2_MASK 0xff0000
10756 #define MC_TSM_DEBUG_BCNT10__BYTE2__SHIFT 0x10
10757 #define MC_TSM_DEBUG_BCNT10__BYTE3_MASK 0xff000000
10758 #define MC_TSM_DEBUG_BCNT10__BYTE3__SHIFT 0x18
10759 #define MC_TSM_DEBUG_ST01__DATA_MASK 0xffffffff
10760 #define MC_TSM_DEBUG_ST01__DATA__SHIFT 0x0
10761 #define MC_TSM_DEBUG_ST23__DATA_MASK 0xffffffff
10762 #define MC_TSM_DEBUG_ST23__DATA__SHIFT 0x0
10763 #define MC_TSM_DEBUG_ST45__DATA_MASK 0xffffffff
10764 #define MC_TSM_DEBUG_ST45__DATA__SHIFT 0x0
10765 #define MC_TSM_DEBUG_BKPT__DATA_MASK 0xffffffff
10766 #define MC_TSM_DEBUG_BKPT__DATA__SHIFT 0x0
10767 #define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX_MASK 0x1ff
10768 #define MC_SEQ_IO_DEBUG_INDEX__IO_DEBUG_INDEX__SHIFT 0x0
10769 #define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA_MASK 0xffffffff
10770 #define MC_SEQ_IO_DEBUG_DATA__IO_DEBUG_DATA__SHIFT 0x0
10771 #define MC_IO_DEBUG_UP_0__VALUE0_MASK 0xff
10772 #define MC_IO_DEBUG_UP_0__VALUE0__SHIFT 0x0
10773 #define MC_IO_DEBUG_UP_0__VALUE1_MASK 0xff00
10774 #define MC_IO_DEBUG_UP_0__VALUE1__SHIFT 0x8
10775 #define MC_IO_DEBUG_UP_0__VALUE2_MASK 0xff0000
10776 #define MC_IO_DEBUG_UP_0__VALUE2__SHIFT 0x10
10777 #define MC_IO_DEBUG_UP_0__VALUE3_MASK 0xff000000
10778 #define MC_IO_DEBUG_UP_0__VALUE3__SHIFT 0x18
10779 #define MC_IO_DEBUG_UP_1__VALUE0_MASK 0xff
10780 #define MC_IO_DEBUG_UP_1__VALUE0__SHIFT 0x0
10781 #define MC_IO_DEBUG_UP_1__VALUE1_MASK 0xff00
10782 #define MC_IO_DEBUG_UP_1__VALUE1__SHIFT 0x8
10783 #define MC_IO_DEBUG_UP_1__VALUE2_MASK 0xff0000
10784 #define MC_IO_DEBUG_UP_1__VALUE2__SHIFT 0x10
10785 #define MC_IO_DEBUG_UP_1__VALUE3_MASK 0xff000000
10786 #define MC_IO_DEBUG_UP_1__VALUE3__SHIFT 0x18
10787 #define MC_IO_DEBUG_UP_2__VALUE0_MASK 0xff
10788 #define MC_IO_DEBUG_UP_2__VALUE0__SHIFT 0x0
10789 #define MC_IO_DEBUG_UP_2__VALUE1_MASK 0xff00
10790 #define MC_IO_DEBUG_UP_2__VALUE1__SHIFT 0x8
10791 #define MC_IO_DEBUG_UP_2__VALUE2_MASK 0xff0000
10792 #define MC_IO_DEBUG_UP_2__VALUE2__SHIFT 0x10
10793 #define MC_IO_DEBUG_UP_2__VALUE3_MASK 0xff000000
10794 #define MC_IO_DEBUG_UP_2__VALUE3__SHIFT 0x18
10795 #define MC_IO_DEBUG_UP_3__VALUE0_MASK 0xff
10796 #define MC_IO_DEBUG_UP_3__VALUE0__SHIFT 0x0
10797 #define MC_IO_DEBUG_UP_3__VALUE1_MASK 0xff00
10798 #define MC_IO_DEBUG_UP_3__VALUE1__SHIFT 0x8
10799 #define MC_IO_DEBUG_UP_3__VALUE2_MASK 0xff0000
10800 #define MC_IO_DEBUG_UP_3__VALUE2__SHIFT 0x10
10801 #define MC_IO_DEBUG_UP_3__VALUE3_MASK 0xff000000
10802 #define MC_IO_DEBUG_UP_3__VALUE3__SHIFT 0x18
10803 #define MC_IO_DEBUG_UP_4__VALUE0_MASK 0xff
10804 #define MC_IO_DEBUG_UP_4__VALUE0__SHIFT 0x0
10805 #define MC_IO_DEBUG_UP_4__VALUE1_MASK 0xff00
10806 #define MC_IO_DEBUG_UP_4__VALUE1__SHIFT 0x8
10807 #define MC_IO_DEBUG_UP_4__VALUE2_MASK 0xff0000
10808 #define MC_IO_DEBUG_UP_4__VALUE2__SHIFT 0x10
10809 #define MC_IO_DEBUG_UP_4__VALUE3_MASK 0xff000000
10810 #define MC_IO_DEBUG_UP_4__VALUE3__SHIFT 0x18
10811 #define MC_IO_DEBUG_UP_5__VALUE0_MASK 0xff
10812 #define MC_IO_DEBUG_UP_5__VALUE0__SHIFT 0x0
10813 #define MC_IO_DEBUG_UP_5__VALUE1_MASK 0xff00
10814 #define MC_IO_DEBUG_UP_5__VALUE1__SHIFT 0x8
10815 #define MC_IO_DEBUG_UP_5__VALUE2_MASK 0xff0000
10816 #define MC_IO_DEBUG_UP_5__VALUE2__SHIFT 0x10
10817 #define MC_IO_DEBUG_UP_5__VALUE3_MASK 0xff000000
10818 #define MC_IO_DEBUG_UP_5__VALUE3__SHIFT 0x18
10819 #define MC_IO_DEBUG_UP_6__VALUE0_MASK 0xff
10820 #define MC_IO_DEBUG_UP_6__VALUE0__SHIFT 0x0
10821 #define MC_IO_DEBUG_UP_6__VALUE1_MASK 0xff00
10822 #define MC_IO_DEBUG_UP_6__VALUE1__SHIFT 0x8
10823 #define MC_IO_DEBUG_UP_6__VALUE2_MASK 0xff0000
10824 #define MC_IO_DEBUG_UP_6__VALUE2__SHIFT 0x10
10825 #define MC_IO_DEBUG_UP_6__VALUE3_MASK 0xff000000
10826 #define MC_IO_DEBUG_UP_6__VALUE3__SHIFT 0x18
10827 #define MC_IO_DEBUG_UP_7__VALUE0_MASK 0xff
10828 #define MC_IO_DEBUG_UP_7__VALUE0__SHIFT 0x0
10829 #define MC_IO_DEBUG_UP_7__VALUE1_MASK 0xff00
10830 #define MC_IO_DEBUG_UP_7__VALUE1__SHIFT 0x8
10831 #define MC_IO_DEBUG_UP_7__VALUE2_MASK 0xff0000
10832 #define MC_IO_DEBUG_UP_7__VALUE2__SHIFT 0x10
10833 #define MC_IO_DEBUG_UP_7__VALUE3_MASK 0xff000000
10834 #define MC_IO_DEBUG_UP_7__VALUE3__SHIFT 0x18
10835 #define MC_IO_DEBUG_UP_8__VALUE0_MASK 0xff
10836 #define MC_IO_DEBUG_UP_8__VALUE0__SHIFT 0x0
10837 #define MC_IO_DEBUG_UP_8__VALUE1_MASK 0xff00
10838 #define MC_IO_DEBUG_UP_8__VALUE1__SHIFT 0x8
10839 #define MC_IO_DEBUG_UP_8__VALUE2_MASK 0xff0000
10840 #define MC_IO_DEBUG_UP_8__VALUE2__SHIFT 0x10
10841 #define MC_IO_DEBUG_UP_8__VALUE3_MASK 0xff000000
10842 #define MC_IO_DEBUG_UP_8__VALUE3__SHIFT 0x18
10843 #define MC_IO_DEBUG_UP_9__VALUE0_MASK 0xff
10844 #define MC_IO_DEBUG_UP_9__VALUE0__SHIFT 0x0
10845 #define MC_IO_DEBUG_UP_9__VALUE1_MASK 0xff00
10846 #define MC_IO_DEBUG_UP_9__VALUE1__SHIFT 0x8
10847 #define MC_IO_DEBUG_UP_9__VALUE2_MASK 0xff0000
10848 #define MC_IO_DEBUG_UP_9__VALUE2__SHIFT 0x10
10849 #define MC_IO_DEBUG_UP_9__VALUE3_MASK 0xff000000
10850 #define MC_IO_DEBUG_UP_9__VALUE3__SHIFT 0x18
10851 #define MC_IO_DEBUG_UP_10__VALUE0_MASK 0xff
10852 #define MC_IO_DEBUG_UP_10__VALUE0__SHIFT 0x0
10853 #define MC_IO_DEBUG_UP_10__VALUE1_MASK 0xff00
10854 #define MC_IO_DEBUG_UP_10__VALUE1__SHIFT 0x8
10855 #define MC_IO_DEBUG_UP_10__VALUE2_MASK 0xff0000
10856 #define MC_IO_DEBUG_UP_10__VALUE2__SHIFT 0x10
10857 #define MC_IO_DEBUG_UP_10__VALUE3_MASK 0xff000000
10858 #define MC_IO_DEBUG_UP_10__VALUE3__SHIFT 0x18
10859 #define MC_IO_DEBUG_UP_11__VALUE0_MASK 0xff
10860 #define MC_IO_DEBUG_UP_11__VALUE0__SHIFT 0x0
10861 #define MC_IO_DEBUG_UP_11__VALUE1_MASK 0xff00
10862 #define MC_IO_DEBUG_UP_11__VALUE1__SHIFT 0x8
10863 #define MC_IO_DEBUG_UP_11__VALUE2_MASK 0xff0000
10864 #define MC_IO_DEBUG_UP_11__VALUE2__SHIFT 0x10
10865 #define MC_IO_DEBUG_UP_11__VALUE3_MASK 0xff000000
10866 #define MC_IO_DEBUG_UP_11__VALUE3__SHIFT 0x18
10867 #define MC_IO_DEBUG_UP_12__VALUE0_MASK 0xff
10868 #define MC_IO_DEBUG_UP_12__VALUE0__SHIFT 0x0
10869 #define MC_IO_DEBUG_UP_12__VALUE1_MASK 0xff00
10870 #define MC_IO_DEBUG_UP_12__VALUE1__SHIFT 0x8
10871 #define MC_IO_DEBUG_UP_12__VALUE2_MASK 0xff0000
10872 #define MC_IO_DEBUG_UP_12__VALUE2__SHIFT 0x10
10873 #define MC_IO_DEBUG_UP_12__VALUE3_MASK 0xff000000
10874 #define MC_IO_DEBUG_UP_12__VALUE3__SHIFT 0x18
10875 #define MC_IO_DEBUG_UP_13__VALUE0_MASK 0xff
10876 #define MC_IO_DEBUG_UP_13__VALUE0__SHIFT 0x0
10877 #define MC_IO_DEBUG_UP_13__VALUE1_MASK 0xff00
10878 #define MC_IO_DEBUG_UP_13__VALUE1__SHIFT 0x8
10879 #define MC_IO_DEBUG_UP_13__VALUE2_MASK 0xff0000
10880 #define MC_IO_DEBUG_UP_13__VALUE2__SHIFT 0x10
10881 #define MC_IO_DEBUG_UP_13__VALUE3_MASK 0xff000000
10882 #define MC_IO_DEBUG_UP_13__VALUE3__SHIFT 0x18
10883 #define MC_IO_DEBUG_UP_14__VALUE0_MASK 0xff
10884 #define MC_IO_DEBUG_UP_14__VALUE0__SHIFT 0x0
10885 #define MC_IO_DEBUG_UP_14__VALUE1_MASK 0xff00
10886 #define MC_IO_DEBUG_UP_14__VALUE1__SHIFT 0x8
10887 #define MC_IO_DEBUG_UP_14__VALUE2_MASK 0xff0000
10888 #define MC_IO_DEBUG_UP_14__VALUE2__SHIFT 0x10
10889 #define MC_IO_DEBUG_UP_14__VALUE3_MASK 0xff000000
10890 #define MC_IO_DEBUG_UP_14__VALUE3__SHIFT 0x18
10891 #define MC_IO_DEBUG_UP_15__VALUE0_MASK 0xff
10892 #define MC_IO_DEBUG_UP_15__VALUE0__SHIFT 0x0
10893 #define MC_IO_DEBUG_UP_15__VALUE1_MASK 0xff00
10894 #define MC_IO_DEBUG_UP_15__VALUE1__SHIFT 0x8
10895 #define MC_IO_DEBUG_UP_15__VALUE2_MASK 0xff0000
10896 #define MC_IO_DEBUG_UP_15__VALUE2__SHIFT 0x10
10897 #define MC_IO_DEBUG_UP_15__VALUE3_MASK 0xff000000
10898 #define MC_IO_DEBUG_UP_15__VALUE3__SHIFT 0x18
10899 #define MC_IO_DEBUG_UP_16__VALUE0_MASK 0xff
10900 #define MC_IO_DEBUG_UP_16__VALUE0__SHIFT 0x0
10901 #define MC_IO_DEBUG_UP_16__VALUE1_MASK 0xff00
10902 #define MC_IO_DEBUG_UP_16__VALUE1__SHIFT 0x8
10903 #define MC_IO_DEBUG_UP_16__VALUE2_MASK 0xff0000
10904 #define MC_IO_DEBUG_UP_16__VALUE2__SHIFT 0x10
10905 #define MC_IO_DEBUG_UP_16__VALUE3_MASK 0xff000000
10906 #define MC_IO_DEBUG_UP_16__VALUE3__SHIFT 0x18
10907 #define MC_IO_DEBUG_UP_17__VALUE0_MASK 0xff
10908 #define MC_IO_DEBUG_UP_17__VALUE0__SHIFT 0x0
10909 #define MC_IO_DEBUG_UP_17__VALUE1_MASK 0xff00
10910 #define MC_IO_DEBUG_UP_17__VALUE1__SHIFT 0x8
10911 #define MC_IO_DEBUG_UP_17__VALUE2_MASK 0xff0000
10912 #define MC_IO_DEBUG_UP_17__VALUE2__SHIFT 0x10
10913 #define MC_IO_DEBUG_UP_17__VALUE3_MASK 0xff000000
10914 #define MC_IO_DEBUG_UP_17__VALUE3__SHIFT 0x18
10915 #define MC_IO_DEBUG_UP_18__VALUE0_MASK 0xff
10916 #define MC_IO_DEBUG_UP_18__VALUE0__SHIFT 0x0
10917 #define MC_IO_DEBUG_UP_18__VALUE1_MASK 0xff00
10918 #define MC_IO_DEBUG_UP_18__VALUE1__SHIFT 0x8
10919 #define MC_IO_DEBUG_UP_18__VALUE2_MASK 0xff0000
10920 #define MC_IO_DEBUG_UP_18__VALUE2__SHIFT 0x10
10921 #define MC_IO_DEBUG_UP_18__VALUE3_MASK 0xff000000
10922 #define MC_IO_DEBUG_UP_18__VALUE3__SHIFT 0x18
10923 #define MC_IO_DEBUG_UP_19__VALUE0_MASK 0xff
10924 #define MC_IO_DEBUG_UP_19__VALUE0__SHIFT 0x0
10925 #define MC_IO_DEBUG_UP_19__VALUE1_MASK 0xff00
10926 #define MC_IO_DEBUG_UP_19__VALUE1__SHIFT 0x8
10927 #define MC_IO_DEBUG_UP_19__VALUE2_MASK 0xff0000
10928 #define MC_IO_DEBUG_UP_19__VALUE2__SHIFT 0x10
10929 #define MC_IO_DEBUG_UP_19__VALUE3_MASK 0xff000000
10930 #define MC_IO_DEBUG_UP_19__VALUE3__SHIFT 0x18
10931 #define MC_IO_DEBUG_UP_20__VALUE0_MASK 0xff
10932 #define MC_IO_DEBUG_UP_20__VALUE0__SHIFT 0x0
10933 #define MC_IO_DEBUG_UP_20__VALUE1_MASK 0xff00
10934 #define MC_IO_DEBUG_UP_20__VALUE1__SHIFT 0x8
10935 #define MC_IO_DEBUG_UP_20__VALUE2_MASK 0xff0000
10936 #define MC_IO_DEBUG_UP_20__VALUE2__SHIFT 0x10
10937 #define MC_IO_DEBUG_UP_20__VALUE3_MASK 0xff000000
10938 #define MC_IO_DEBUG_UP_20__VALUE3__SHIFT 0x18
10939 #define MC_IO_DEBUG_UP_21__VALUE0_MASK 0xff
10940 #define MC_IO_DEBUG_UP_21__VALUE0__SHIFT 0x0
10941 #define MC_IO_DEBUG_UP_21__VALUE1_MASK 0xff00
10942 #define MC_IO_DEBUG_UP_21__VALUE1__SHIFT 0x8
10943 #define MC_IO_DEBUG_UP_21__VALUE2_MASK 0xff0000
10944 #define MC_IO_DEBUG_UP_21__VALUE2__SHIFT 0x10
10945 #define MC_IO_DEBUG_UP_21__VALUE3_MASK 0xff000000
10946 #define MC_IO_DEBUG_UP_21__VALUE3__SHIFT 0x18
10947 #define MC_IO_DEBUG_UP_22__VALUE0_MASK 0xff
10948 #define MC_IO_DEBUG_UP_22__VALUE0__SHIFT 0x0
10949 #define MC_IO_DEBUG_UP_22__VALUE1_MASK 0xff00
10950 #define MC_IO_DEBUG_UP_22__VALUE1__SHIFT 0x8
10951 #define MC_IO_DEBUG_UP_22__VALUE2_MASK 0xff0000
10952 #define MC_IO_DEBUG_UP_22__VALUE2__SHIFT 0x10
10953 #define MC_IO_DEBUG_UP_22__VALUE3_MASK 0xff000000
10954 #define MC_IO_DEBUG_UP_22__VALUE3__SHIFT 0x18
10955 #define MC_IO_DEBUG_UP_23__VALUE0_MASK 0xff
10956 #define MC_IO_DEBUG_UP_23__VALUE0__SHIFT 0x0
10957 #define MC_IO_DEBUG_UP_23__VALUE1_MASK 0xff00
10958 #define MC_IO_DEBUG_UP_23__VALUE1__SHIFT 0x8
10959 #define MC_IO_DEBUG_UP_23__VALUE2_MASK 0xff0000
10960 #define MC_IO_DEBUG_UP_23__VALUE2__SHIFT 0x10
10961 #define MC_IO_DEBUG_UP_23__VALUE3_MASK 0xff000000
10962 #define MC_IO_DEBUG_UP_23__VALUE3__SHIFT 0x18
10963 #define MC_IO_DEBUG_UP_24__VALUE0_MASK 0xff
10964 #define MC_IO_DEBUG_UP_24__VALUE0__SHIFT 0x0
10965 #define MC_IO_DEBUG_UP_24__VALUE1_MASK 0xff00
10966 #define MC_IO_DEBUG_UP_24__VALUE1__SHIFT 0x8
10967 #define MC_IO_DEBUG_UP_24__VALUE2_MASK 0xff0000
10968 #define MC_IO_DEBUG_UP_24__VALUE2__SHIFT 0x10
10969 #define MC_IO_DEBUG_UP_24__VALUE3_MASK 0xff000000
10970 #define MC_IO_DEBUG_UP_24__VALUE3__SHIFT 0x18
10971 #define MC_IO_DEBUG_UP_25__VALUE0_MASK 0xff
10972 #define MC_IO_DEBUG_UP_25__VALUE0__SHIFT 0x0
10973 #define MC_IO_DEBUG_UP_25__VALUE1_MASK 0xff00
10974 #define MC_IO_DEBUG_UP_25__VALUE1__SHIFT 0x8
10975 #define MC_IO_DEBUG_UP_25__VALUE2_MASK 0xff0000
10976 #define MC_IO_DEBUG_UP_25__VALUE2__SHIFT 0x10
10977 #define MC_IO_DEBUG_UP_25__VALUE3_MASK 0xff000000
10978 #define MC_IO_DEBUG_UP_25__VALUE3__SHIFT 0x18
10979 #define MC_IO_DEBUG_UP_26__VALUE0_MASK 0xff
10980 #define MC_IO_DEBUG_UP_26__VALUE0__SHIFT 0x0
10981 #define MC_IO_DEBUG_UP_26__VALUE1_MASK 0xff00
10982 #define MC_IO_DEBUG_UP_26__VALUE1__SHIFT 0x8
10983 #define MC_IO_DEBUG_UP_26__VALUE2_MASK 0xff0000
10984 #define MC_IO_DEBUG_UP_26__VALUE2__SHIFT 0x10
10985 #define MC_IO_DEBUG_UP_26__VALUE3_MASK 0xff000000
10986 #define MC_IO_DEBUG_UP_26__VALUE3__SHIFT 0x18
10987 #define MC_IO_DEBUG_UP_27__VALUE0_MASK 0xff
10988 #define MC_IO_DEBUG_UP_27__VALUE0__SHIFT 0x0
10989 #define MC_IO_DEBUG_UP_27__VALUE1_MASK 0xff00
10990 #define MC_IO_DEBUG_UP_27__VALUE1__SHIFT 0x8
10991 #define MC_IO_DEBUG_UP_27__VALUE2_MASK 0xff0000
10992 #define MC_IO_DEBUG_UP_27__VALUE2__SHIFT 0x10
10993 #define MC_IO_DEBUG_UP_27__VALUE3_MASK 0xff000000
10994 #define MC_IO_DEBUG_UP_27__VALUE3__SHIFT 0x18
10995 #define MC_IO_DEBUG_UP_28__VALUE0_MASK 0xff
10996 #define MC_IO_DEBUG_UP_28__VALUE0__SHIFT 0x0
10997 #define MC_IO_DEBUG_UP_28__VALUE1_MASK 0xff00
10998 #define MC_IO_DEBUG_UP_28__VALUE1__SHIFT 0x8
10999 #define MC_IO_DEBUG_UP_28__VALUE2_MASK 0xff0000
11000 #define MC_IO_DEBUG_UP_28__VALUE2__SHIFT 0x10
11001 #define MC_IO_DEBUG_UP_28__VALUE3_MASK 0xff000000
11002 #define MC_IO_DEBUG_UP_28__VALUE3__SHIFT 0x18
11003 #define MC_IO_DEBUG_UP_29__VALUE0_MASK 0xff
11004 #define MC_IO_DEBUG_UP_29__VALUE0__SHIFT 0x0
11005 #define MC_IO_DEBUG_UP_29__VALUE1_MASK 0xff00
11006 #define MC_IO_DEBUG_UP_29__VALUE1__SHIFT 0x8
11007 #define MC_IO_DEBUG_UP_29__VALUE2_MASK 0xff0000
11008 #define MC_IO_DEBUG_UP_29__VALUE2__SHIFT 0x10
11009 #define MC_IO_DEBUG_UP_29__VALUE3_MASK 0xff000000
11010 #define MC_IO_DEBUG_UP_29__VALUE3__SHIFT 0x18
11011 #define MC_IO_DEBUG_UP_30__VALUE0_MASK 0xff
11012 #define MC_IO_DEBUG_UP_30__VALUE0__SHIFT 0x0
11013 #define MC_IO_DEBUG_UP_30__VALUE1_MASK 0xff00
11014 #define MC_IO_DEBUG_UP_30__VALUE1__SHIFT 0x8
11015 #define MC_IO_DEBUG_UP_30__VALUE2_MASK 0xff0000
11016 #define MC_IO_DEBUG_UP_30__VALUE2__SHIFT 0x10
11017 #define MC_IO_DEBUG_UP_30__VALUE3_MASK 0xff000000
11018 #define MC_IO_DEBUG_UP_30__VALUE3__SHIFT 0x18
11019 #define MC_IO_DEBUG_UP_31__VALUE0_MASK 0xff
11020 #define MC_IO_DEBUG_UP_31__VALUE0__SHIFT 0x0
11021 #define MC_IO_DEBUG_UP_31__VALUE1_MASK 0xff00
11022 #define MC_IO_DEBUG_UP_31__VALUE1__SHIFT 0x8
11023 #define MC_IO_DEBUG_UP_31__VALUE2_MASK 0xff0000
11024 #define MC_IO_DEBUG_UP_31__VALUE2__SHIFT 0x10
11025 #define MC_IO_DEBUG_UP_31__VALUE3_MASK 0xff000000
11026 #define MC_IO_DEBUG_UP_31__VALUE3__SHIFT 0x18
11027 #define MC_IO_DEBUG_UP_32__VALUE0_MASK 0xff
11028 #define MC_IO_DEBUG_UP_32__VALUE0__SHIFT 0x0
11029 #define MC_IO_DEBUG_UP_32__VALUE1_MASK 0xff00
11030 #define MC_IO_DEBUG_UP_32__VALUE1__SHIFT 0x8
11031 #define MC_IO_DEBUG_UP_32__VALUE2_MASK 0xff0000
11032 #define MC_IO_DEBUG_UP_32__VALUE2__SHIFT 0x10
11033 #define MC_IO_DEBUG_UP_32__VALUE3_MASK 0xff000000
11034 #define MC_IO_DEBUG_UP_32__VALUE3__SHIFT 0x18
11035 #define MC_IO_DEBUG_UP_33__VALUE0_MASK 0xff
11036 #define MC_IO_DEBUG_UP_33__VALUE0__SHIFT 0x0
11037 #define MC_IO_DEBUG_UP_33__VALUE1_MASK 0xff00
11038 #define MC_IO_DEBUG_UP_33__VALUE1__SHIFT 0x8
11039 #define MC_IO_DEBUG_UP_33__VALUE2_MASK 0xff0000
11040 #define MC_IO_DEBUG_UP_33__VALUE2__SHIFT 0x10
11041 #define MC_IO_DEBUG_UP_33__VALUE3_MASK 0xff000000
11042 #define MC_IO_DEBUG_UP_33__VALUE3__SHIFT 0x18
11043 #define MC_IO_DEBUG_UP_34__VALUE0_MASK 0xff
11044 #define MC_IO_DEBUG_UP_34__VALUE0__SHIFT 0x0
11045 #define MC_IO_DEBUG_UP_34__VALUE1_MASK 0xff00
11046 #define MC_IO_DEBUG_UP_34__VALUE1__SHIFT 0x8
11047 #define MC_IO_DEBUG_UP_34__VALUE2_MASK 0xff0000
11048 #define MC_IO_DEBUG_UP_34__VALUE2__SHIFT 0x10
11049 #define MC_IO_DEBUG_UP_34__VALUE3_MASK 0xff000000
11050 #define MC_IO_DEBUG_UP_34__VALUE3__SHIFT 0x18
11051 #define MC_IO_DEBUG_UP_35__VALUE0_MASK 0xff
11052 #define MC_IO_DEBUG_UP_35__VALUE0__SHIFT 0x0
11053 #define MC_IO_DEBUG_UP_35__VALUE1_MASK 0xff00
11054 #define MC_IO_DEBUG_UP_35__VALUE1__SHIFT 0x8
11055 #define MC_IO_DEBUG_UP_35__VALUE2_MASK 0xff0000
11056 #define MC_IO_DEBUG_UP_35__VALUE2__SHIFT 0x10
11057 #define MC_IO_DEBUG_UP_35__VALUE3_MASK 0xff000000
11058 #define MC_IO_DEBUG_UP_35__VALUE3__SHIFT 0x18
11059 #define MC_IO_DEBUG_UP_36__VALUE0_MASK 0xff
11060 #define MC_IO_DEBUG_UP_36__VALUE0__SHIFT 0x0
11061 #define MC_IO_DEBUG_UP_36__VALUE1_MASK 0xff00
11062 #define MC_IO_DEBUG_UP_36__VALUE1__SHIFT 0x8
11063 #define MC_IO_DEBUG_UP_36__VALUE2_MASK 0xff0000
11064 #define MC_IO_DEBUG_UP_36__VALUE2__SHIFT 0x10
11065 #define MC_IO_DEBUG_UP_36__VALUE3_MASK 0xff000000
11066 #define MC_IO_DEBUG_UP_36__VALUE3__SHIFT 0x18
11067 #define MC_IO_DEBUG_UP_37__VALUE0_MASK 0xff
11068 #define MC_IO_DEBUG_UP_37__VALUE0__SHIFT 0x0
11069 #define MC_IO_DEBUG_UP_37__VALUE1_MASK 0xff00
11070 #define MC_IO_DEBUG_UP_37__VALUE1__SHIFT 0x8
11071 #define MC_IO_DEBUG_UP_37__VALUE2_MASK 0xff0000
11072 #define MC_IO_DEBUG_UP_37__VALUE2__SHIFT 0x10
11073 #define MC_IO_DEBUG_UP_37__VALUE3_MASK 0xff000000
11074 #define MC_IO_DEBUG_UP_37__VALUE3__SHIFT 0x18
11075 #define MC_IO_DEBUG_UP_38__VALUE0_MASK 0xff
11076 #define MC_IO_DEBUG_UP_38__VALUE0__SHIFT 0x0
11077 #define MC_IO_DEBUG_UP_38__VALUE1_MASK 0xff00
11078 #define MC_IO_DEBUG_UP_38__VALUE1__SHIFT 0x8
11079 #define MC_IO_DEBUG_UP_38__VALUE2_MASK 0xff0000
11080 #define MC_IO_DEBUG_UP_38__VALUE2__SHIFT 0x10
11081 #define MC_IO_DEBUG_UP_38__VALUE3_MASK 0xff000000
11082 #define MC_IO_DEBUG_UP_38__VALUE3__SHIFT 0x18
11083 #define MC_IO_DEBUG_UP_39__VALUE0_MASK 0xff
11084 #define MC_IO_DEBUG_UP_39__VALUE0__SHIFT 0x0
11085 #define MC_IO_DEBUG_UP_39__VALUE1_MASK 0xff00
11086 #define MC_IO_DEBUG_UP_39__VALUE1__SHIFT 0x8
11087 #define MC_IO_DEBUG_UP_39__VALUE2_MASK 0xff0000
11088 #define MC_IO_DEBUG_UP_39__VALUE2__SHIFT 0x10
11089 #define MC_IO_DEBUG_UP_39__VALUE3_MASK 0xff000000
11090 #define MC_IO_DEBUG_UP_39__VALUE3__SHIFT 0x18
11091 #define MC_IO_DEBUG_UP_40__VALUE0_MASK 0xff
11092 #define MC_IO_DEBUG_UP_40__VALUE0__SHIFT 0x0
11093 #define MC_IO_DEBUG_UP_40__VALUE1_MASK 0xff00
11094 #define MC_IO_DEBUG_UP_40__VALUE1__SHIFT 0x8
11095 #define MC_IO_DEBUG_UP_40__VALUE2_MASK 0xff0000
11096 #define MC_IO_DEBUG_UP_40__VALUE2__SHIFT 0x10
11097 #define MC_IO_DEBUG_UP_40__VALUE3_MASK 0xff000000
11098 #define MC_IO_DEBUG_UP_40__VALUE3__SHIFT 0x18
11099 #define MC_IO_DEBUG_UP_41__VALUE0_MASK 0xff
11100 #define MC_IO_DEBUG_UP_41__VALUE0__SHIFT 0x0
11101 #define MC_IO_DEBUG_UP_41__VALUE1_MASK 0xff00
11102 #define MC_IO_DEBUG_UP_41__VALUE1__SHIFT 0x8
11103 #define MC_IO_DEBUG_UP_41__VALUE2_MASK 0xff0000
11104 #define MC_IO_DEBUG_UP_41__VALUE2__SHIFT 0x10
11105 #define MC_IO_DEBUG_UP_41__VALUE3_MASK 0xff000000
11106 #define MC_IO_DEBUG_UP_41__VALUE3__SHIFT 0x18
11107 #define MC_IO_DEBUG_UP_42__VALUE0_MASK 0xff
11108 #define MC_IO_DEBUG_UP_42__VALUE0__SHIFT 0x0
11109 #define MC_IO_DEBUG_UP_42__VALUE1_MASK 0xff00
11110 #define MC_IO_DEBUG_UP_42__VALUE1__SHIFT 0x8
11111 #define MC_IO_DEBUG_UP_42__VALUE2_MASK 0xff0000
11112 #define MC_IO_DEBUG_UP_42__VALUE2__SHIFT 0x10
11113 #define MC_IO_DEBUG_UP_42__VALUE3_MASK 0xff000000
11114 #define MC_IO_DEBUG_UP_42__VALUE3__SHIFT 0x18
11115 #define MC_IO_DEBUG_UP_43__VALUE0_MASK 0xff
11116 #define MC_IO_DEBUG_UP_43__VALUE0__SHIFT 0x0
11117 #define MC_IO_DEBUG_UP_43__VALUE1_MASK 0xff00
11118 #define MC_IO_DEBUG_UP_43__VALUE1__SHIFT 0x8
11119 #define MC_IO_DEBUG_UP_43__VALUE2_MASK 0xff0000
11120 #define MC_IO_DEBUG_UP_43__VALUE2__SHIFT 0x10
11121 #define MC_IO_DEBUG_UP_43__VALUE3_MASK 0xff000000
11122 #define MC_IO_DEBUG_UP_43__VALUE3__SHIFT 0x18
11123 #define MC_IO_DEBUG_UP_44__VALUE0_MASK 0xff
11124 #define MC_IO_DEBUG_UP_44__VALUE0__SHIFT 0x0
11125 #define MC_IO_DEBUG_UP_44__VALUE1_MASK 0xff00
11126 #define MC_IO_DEBUG_UP_44__VALUE1__SHIFT 0x8
11127 #define MC_IO_DEBUG_UP_44__VALUE2_MASK 0xff0000
11128 #define MC_IO_DEBUG_UP_44__VALUE2__SHIFT 0x10
11129 #define MC_IO_DEBUG_UP_44__VALUE3_MASK 0xff000000
11130 #define MC_IO_DEBUG_UP_44__VALUE3__SHIFT 0x18
11131 #define MC_IO_DEBUG_UP_45__VALUE0_MASK 0xff
11132 #define MC_IO_DEBUG_UP_45__VALUE0__SHIFT 0x0
11133 #define MC_IO_DEBUG_UP_45__VALUE1_MASK 0xff00
11134 #define MC_IO_DEBUG_UP_45__VALUE1__SHIFT 0x8
11135 #define MC_IO_DEBUG_UP_45__VALUE2_MASK 0xff0000
11136 #define MC_IO_DEBUG_UP_45__VALUE2__SHIFT 0x10
11137 #define MC_IO_DEBUG_UP_45__VALUE3_MASK 0xff000000
11138 #define MC_IO_DEBUG_UP_45__VALUE3__SHIFT 0x18
11139 #define MC_IO_DEBUG_UP_46__VALUE0_MASK 0xff
11140 #define MC_IO_DEBUG_UP_46__VALUE0__SHIFT 0x0
11141 #define MC_IO_DEBUG_UP_46__VALUE1_MASK 0xff00
11142 #define MC_IO_DEBUG_UP_46__VALUE1__SHIFT 0x8
11143 #define MC_IO_DEBUG_UP_46__VALUE2_MASK 0xff0000
11144 #define MC_IO_DEBUG_UP_46__VALUE2__SHIFT 0x10
11145 #define MC_IO_DEBUG_UP_46__VALUE3_MASK 0xff000000
11146 #define MC_IO_DEBUG_UP_46__VALUE3__SHIFT 0x18
11147 #define MC_IO_DEBUG_UP_47__VALUE0_MASK 0xff
11148 #define MC_IO_DEBUG_UP_47__VALUE0__SHIFT 0x0
11149 #define MC_IO_DEBUG_UP_47__VALUE1_MASK 0xff00
11150 #define MC_IO_DEBUG_UP_47__VALUE1__SHIFT 0x8
11151 #define MC_IO_DEBUG_UP_47__VALUE2_MASK 0xff0000
11152 #define MC_IO_DEBUG_UP_47__VALUE2__SHIFT 0x10
11153 #define MC_IO_DEBUG_UP_47__VALUE3_MASK 0xff000000
11154 #define MC_IO_DEBUG_UP_47__VALUE3__SHIFT 0x18
11155 #define MC_IO_DEBUG_UP_48__VALUE0_MASK 0xff
11156 #define MC_IO_DEBUG_UP_48__VALUE0__SHIFT 0x0
11157 #define MC_IO_DEBUG_UP_48__VALUE1_MASK 0xff00
11158 #define MC_IO_DEBUG_UP_48__VALUE1__SHIFT 0x8
11159 #define MC_IO_DEBUG_UP_48__VALUE2_MASK 0xff0000
11160 #define MC_IO_DEBUG_UP_48__VALUE2__SHIFT 0x10
11161 #define MC_IO_DEBUG_UP_48__VALUE3_MASK 0xff000000
11162 #define MC_IO_DEBUG_UP_48__VALUE3__SHIFT 0x18
11163 #define MC_IO_DEBUG_UP_49__VALUE0_MASK 0xff
11164 #define MC_IO_DEBUG_UP_49__VALUE0__SHIFT 0x0
11165 #define MC_IO_DEBUG_UP_49__VALUE1_MASK 0xff00
11166 #define MC_IO_DEBUG_UP_49__VALUE1__SHIFT 0x8
11167 #define MC_IO_DEBUG_UP_49__VALUE2_MASK 0xff0000
11168 #define MC_IO_DEBUG_UP_49__VALUE2__SHIFT 0x10
11169 #define MC_IO_DEBUG_UP_49__VALUE3_MASK 0xff000000
11170 #define MC_IO_DEBUG_UP_49__VALUE3__SHIFT 0x18
11171 #define MC_IO_DEBUG_UP_50__VALUE0_MASK 0xff
11172 #define MC_IO_DEBUG_UP_50__VALUE0__SHIFT 0x0
11173 #define MC_IO_DEBUG_UP_50__VALUE1_MASK 0xff00
11174 #define MC_IO_DEBUG_UP_50__VALUE1__SHIFT 0x8
11175 #define MC_IO_DEBUG_UP_50__VALUE2_MASK 0xff0000
11176 #define MC_IO_DEBUG_UP_50__VALUE2__SHIFT 0x10
11177 #define MC_IO_DEBUG_UP_50__VALUE3_MASK 0xff000000
11178 #define MC_IO_DEBUG_UP_50__VALUE3__SHIFT 0x18
11179 #define MC_IO_DEBUG_UP_51__VALUE0_MASK 0xff
11180 #define MC_IO_DEBUG_UP_51__VALUE0__SHIFT 0x0
11181 #define MC_IO_DEBUG_UP_51__VALUE1_MASK 0xff00
11182 #define MC_IO_DEBUG_UP_51__VALUE1__SHIFT 0x8
11183 #define MC_IO_DEBUG_UP_51__VALUE2_MASK 0xff0000
11184 #define MC_IO_DEBUG_UP_51__VALUE2__SHIFT 0x10
11185 #define MC_IO_DEBUG_UP_51__VALUE3_MASK 0xff000000
11186 #define MC_IO_DEBUG_UP_51__VALUE3__SHIFT 0x18
11187 #define MC_IO_DEBUG_UP_52__VALUE0_MASK 0xff
11188 #define MC_IO_DEBUG_UP_52__VALUE0__SHIFT 0x0
11189 #define MC_IO_DEBUG_UP_52__VALUE1_MASK 0xff00
11190 #define MC_IO_DEBUG_UP_52__VALUE1__SHIFT 0x8
11191 #define MC_IO_DEBUG_UP_52__VALUE2_MASK 0xff0000
11192 #define MC_IO_DEBUG_UP_52__VALUE2__SHIFT 0x10
11193 #define MC_IO_DEBUG_UP_52__VALUE3_MASK 0xff000000
11194 #define MC_IO_DEBUG_UP_52__VALUE3__SHIFT 0x18
11195 #define MC_IO_DEBUG_UP_53__VALUE0_MASK 0xff
11196 #define MC_IO_DEBUG_UP_53__VALUE0__SHIFT 0x0
11197 #define MC_IO_DEBUG_UP_53__VALUE1_MASK 0xff00
11198 #define MC_IO_DEBUG_UP_53__VALUE1__SHIFT 0x8
11199 #define MC_IO_DEBUG_UP_53__VALUE2_MASK 0xff0000
11200 #define MC_IO_DEBUG_UP_53__VALUE2__SHIFT 0x10
11201 #define MC_IO_DEBUG_UP_53__VALUE3_MASK 0xff000000
11202 #define MC_IO_DEBUG_UP_53__VALUE3__SHIFT 0x18
11203 #define MC_IO_DEBUG_UP_54__VALUE0_MASK 0xff
11204 #define MC_IO_DEBUG_UP_54__VALUE0__SHIFT 0x0
11205 #define MC_IO_DEBUG_UP_54__VALUE1_MASK 0xff00
11206 #define MC_IO_DEBUG_UP_54__VALUE1__SHIFT 0x8
11207 #define MC_IO_DEBUG_UP_54__VALUE2_MASK 0xff0000
11208 #define MC_IO_DEBUG_UP_54__VALUE2__SHIFT 0x10
11209 #define MC_IO_DEBUG_UP_54__VALUE3_MASK 0xff000000
11210 #define MC_IO_DEBUG_UP_54__VALUE3__SHIFT 0x18
11211 #define MC_IO_DEBUG_UP_55__VALUE0_MASK 0xff
11212 #define MC_IO_DEBUG_UP_55__VALUE0__SHIFT 0x0
11213 #define MC_IO_DEBUG_UP_55__VALUE1_MASK 0xff00
11214 #define MC_IO_DEBUG_UP_55__VALUE1__SHIFT 0x8
11215 #define MC_IO_DEBUG_UP_55__VALUE2_MASK 0xff0000
11216 #define MC_IO_DEBUG_UP_55__VALUE2__SHIFT 0x10
11217 #define MC_IO_DEBUG_UP_55__VALUE3_MASK 0xff000000
11218 #define MC_IO_DEBUG_UP_55__VALUE3__SHIFT 0x18
11219 #define MC_IO_DEBUG_UP_56__VALUE0_MASK 0xff
11220 #define MC_IO_DEBUG_UP_56__VALUE0__SHIFT 0x0
11221 #define MC_IO_DEBUG_UP_56__VALUE1_MASK 0xff00
11222 #define MC_IO_DEBUG_UP_56__VALUE1__SHIFT 0x8
11223 #define MC_IO_DEBUG_UP_56__VALUE2_MASK 0xff0000
11224 #define MC_IO_DEBUG_UP_56__VALUE2__SHIFT 0x10
11225 #define MC_IO_DEBUG_UP_56__VALUE3_MASK 0xff000000
11226 #define MC_IO_DEBUG_UP_56__VALUE3__SHIFT 0x18
11227 #define MC_IO_DEBUG_UP_57__VALUE0_MASK 0xff
11228 #define MC_IO_DEBUG_UP_57__VALUE0__SHIFT 0x0
11229 #define MC_IO_DEBUG_UP_57__VALUE1_MASK 0xff00
11230 #define MC_IO_DEBUG_UP_57__VALUE1__SHIFT 0x8
11231 #define MC_IO_DEBUG_UP_57__VALUE2_MASK 0xff0000
11232 #define MC_IO_DEBUG_UP_57__VALUE2__SHIFT 0x10
11233 #define MC_IO_DEBUG_UP_57__VALUE3_MASK 0xff000000
11234 #define MC_IO_DEBUG_UP_57__VALUE3__SHIFT 0x18
11235 #define MC_IO_DEBUG_UP_58__VALUE0_MASK 0xff
11236 #define MC_IO_DEBUG_UP_58__VALUE0__SHIFT 0x0
11237 #define MC_IO_DEBUG_UP_58__VALUE1_MASK 0xff00
11238 #define MC_IO_DEBUG_UP_58__VALUE1__SHIFT 0x8
11239 #define MC_IO_DEBUG_UP_58__VALUE2_MASK 0xff0000
11240 #define MC_IO_DEBUG_UP_58__VALUE2__SHIFT 0x10
11241 #define MC_IO_DEBUG_UP_58__VALUE3_MASK 0xff000000
11242 #define MC_IO_DEBUG_UP_58__VALUE3__SHIFT 0x18
11243 #define MC_IO_DEBUG_UP_59__VALUE0_MASK 0xff
11244 #define MC_IO_DEBUG_UP_59__VALUE0__SHIFT 0x0
11245 #define MC_IO_DEBUG_UP_59__VALUE1_MASK 0xff00
11246 #define MC_IO_DEBUG_UP_59__VALUE1__SHIFT 0x8
11247 #define MC_IO_DEBUG_UP_59__VALUE2_MASK 0xff0000
11248 #define MC_IO_DEBUG_UP_59__VALUE2__SHIFT 0x10
11249 #define MC_IO_DEBUG_UP_59__VALUE3_MASK 0xff000000
11250 #define MC_IO_DEBUG_UP_59__VALUE3__SHIFT 0x18
11251 #define MC_IO_DEBUG_UP_60__VALUE0_MASK 0xff
11252 #define MC_IO_DEBUG_UP_60__VALUE0__SHIFT 0x0
11253 #define MC_IO_DEBUG_UP_60__VALUE1_MASK 0xff00
11254 #define MC_IO_DEBUG_UP_60__VALUE1__SHIFT 0x8
11255 #define MC_IO_DEBUG_UP_60__VALUE2_MASK 0xff0000
11256 #define MC_IO_DEBUG_UP_60__VALUE2__SHIFT 0x10
11257 #define MC_IO_DEBUG_UP_60__VALUE3_MASK 0xff000000
11258 #define MC_IO_DEBUG_UP_60__VALUE3__SHIFT 0x18
11259 #define MC_IO_DEBUG_UP_61__VALUE0_MASK 0xff
11260 #define MC_IO_DEBUG_UP_61__VALUE0__SHIFT 0x0
11261 #define MC_IO_DEBUG_UP_61__VALUE1_MASK 0xff00
11262 #define MC_IO_DEBUG_UP_61__VALUE1__SHIFT 0x8
11263 #define MC_IO_DEBUG_UP_61__VALUE2_MASK 0xff0000
11264 #define MC_IO_DEBUG_UP_61__VALUE2__SHIFT 0x10
11265 #define MC_IO_DEBUG_UP_61__VALUE3_MASK 0xff000000
11266 #define MC_IO_DEBUG_UP_61__VALUE3__SHIFT 0x18
11267 #define MC_IO_DEBUG_UP_62__VALUE0_MASK 0xff
11268 #define MC_IO_DEBUG_UP_62__VALUE0__SHIFT 0x0
11269 #define MC_IO_DEBUG_UP_62__VALUE1_MASK 0xff00
11270 #define MC_IO_DEBUG_UP_62__VALUE1__SHIFT 0x8
11271 #define MC_IO_DEBUG_UP_62__VALUE2_MASK 0xff0000
11272 #define MC_IO_DEBUG_UP_62__VALUE2__SHIFT 0x10
11273 #define MC_IO_DEBUG_UP_62__VALUE3_MASK 0xff000000
11274 #define MC_IO_DEBUG_UP_62__VALUE3__SHIFT 0x18
11275 #define MC_IO_DEBUG_UP_63__VALUE0_MASK 0xff
11276 #define MC_IO_DEBUG_UP_63__VALUE0__SHIFT 0x0
11277 #define MC_IO_DEBUG_UP_63__VALUE1_MASK 0xff00
11278 #define MC_IO_DEBUG_UP_63__VALUE1__SHIFT 0x8
11279 #define MC_IO_DEBUG_UP_63__VALUE2_MASK 0xff0000
11280 #define MC_IO_DEBUG_UP_63__VALUE2__SHIFT 0x10
11281 #define MC_IO_DEBUG_UP_63__VALUE3_MASK 0xff000000
11282 #define MC_IO_DEBUG_UP_63__VALUE3__SHIFT 0x18
11283 #define MC_IO_DEBUG_UP_64__VALUE0_MASK 0xff
11284 #define MC_IO_DEBUG_UP_64__VALUE0__SHIFT 0x0
11285 #define MC_IO_DEBUG_UP_64__VALUE1_MASK 0xff00
11286 #define MC_IO_DEBUG_UP_64__VALUE1__SHIFT 0x8
11287 #define MC_IO_DEBUG_UP_64__VALUE2_MASK 0xff0000
11288 #define MC_IO_DEBUG_UP_64__VALUE2__SHIFT 0x10
11289 #define MC_IO_DEBUG_UP_64__VALUE3_MASK 0xff000000
11290 #define MC_IO_DEBUG_UP_64__VALUE3__SHIFT 0x18
11291 #define MC_IO_DEBUG_UP_65__VALUE0_MASK 0xff
11292 #define MC_IO_DEBUG_UP_65__VALUE0__SHIFT 0x0
11293 #define MC_IO_DEBUG_UP_65__VALUE1_MASK 0xff00
11294 #define MC_IO_DEBUG_UP_65__VALUE1__SHIFT 0x8
11295 #define MC_IO_DEBUG_UP_65__VALUE2_MASK 0xff0000
11296 #define MC_IO_DEBUG_UP_65__VALUE2__SHIFT 0x10
11297 #define MC_IO_DEBUG_UP_65__VALUE3_MASK 0xff000000
11298 #define MC_IO_DEBUG_UP_65__VALUE3__SHIFT 0x18
11299 #define MC_IO_DEBUG_UP_66__VALUE0_MASK 0xff
11300 #define MC_IO_DEBUG_UP_66__VALUE0__SHIFT 0x0
11301 #define MC_IO_DEBUG_UP_66__VALUE1_MASK 0xff00
11302 #define MC_IO_DEBUG_UP_66__VALUE1__SHIFT 0x8
11303 #define MC_IO_DEBUG_UP_66__VALUE2_MASK 0xff0000
11304 #define MC_IO_DEBUG_UP_66__VALUE2__SHIFT 0x10
11305 #define MC_IO_DEBUG_UP_66__VALUE3_MASK 0xff000000
11306 #define MC_IO_DEBUG_UP_66__VALUE3__SHIFT 0x18
11307 #define MC_IO_DEBUG_UP_67__VALUE0_MASK 0xff
11308 #define MC_IO_DEBUG_UP_67__VALUE0__SHIFT 0x0
11309 #define MC_IO_DEBUG_UP_67__VALUE1_MASK 0xff00
11310 #define MC_IO_DEBUG_UP_67__VALUE1__SHIFT 0x8
11311 #define MC_IO_DEBUG_UP_67__VALUE2_MASK 0xff0000
11312 #define MC_IO_DEBUG_UP_67__VALUE2__SHIFT 0x10
11313 #define MC_IO_DEBUG_UP_67__VALUE3_MASK 0xff000000
11314 #define MC_IO_DEBUG_UP_67__VALUE3__SHIFT 0x18
11315 #define MC_IO_DEBUG_UP_68__VALUE0_MASK 0xff
11316 #define MC_IO_DEBUG_UP_68__VALUE0__SHIFT 0x0
11317 #define MC_IO_DEBUG_UP_68__VALUE1_MASK 0xff00
11318 #define MC_IO_DEBUG_UP_68__VALUE1__SHIFT 0x8
11319 #define MC_IO_DEBUG_UP_68__VALUE2_MASK 0xff0000
11320 #define MC_IO_DEBUG_UP_68__VALUE2__SHIFT 0x10
11321 #define MC_IO_DEBUG_UP_68__VALUE3_MASK 0xff000000
11322 #define MC_IO_DEBUG_UP_68__VALUE3__SHIFT 0x18
11323 #define MC_IO_DEBUG_UP_69__VALUE0_MASK 0xff
11324 #define MC_IO_DEBUG_UP_69__VALUE0__SHIFT 0x0
11325 #define MC_IO_DEBUG_UP_69__VALUE1_MASK 0xff00
11326 #define MC_IO_DEBUG_UP_69__VALUE1__SHIFT 0x8
11327 #define MC_IO_DEBUG_UP_69__VALUE2_MASK 0xff0000
11328 #define MC_IO_DEBUG_UP_69__VALUE2__SHIFT 0x10
11329 #define MC_IO_DEBUG_UP_69__VALUE3_MASK 0xff000000
11330 #define MC_IO_DEBUG_UP_69__VALUE3__SHIFT 0x18
11331 #define MC_IO_DEBUG_UP_70__VALUE0_MASK 0xff
11332 #define MC_IO_DEBUG_UP_70__VALUE0__SHIFT 0x0
11333 #define MC_IO_DEBUG_UP_70__VALUE1_MASK 0xff00
11334 #define MC_IO_DEBUG_UP_70__VALUE1__SHIFT 0x8
11335 #define MC_IO_DEBUG_UP_70__VALUE2_MASK 0xff0000
11336 #define MC_IO_DEBUG_UP_70__VALUE2__SHIFT 0x10
11337 #define MC_IO_DEBUG_UP_70__VALUE3_MASK 0xff000000
11338 #define MC_IO_DEBUG_UP_70__VALUE3__SHIFT 0x18
11339 #define MC_IO_DEBUG_UP_71__VALUE0_MASK 0xff
11340 #define MC_IO_DEBUG_UP_71__VALUE0__SHIFT 0x0
11341 #define MC_IO_DEBUG_UP_71__VALUE1_MASK 0xff00
11342 #define MC_IO_DEBUG_UP_71__VALUE1__SHIFT 0x8
11343 #define MC_IO_DEBUG_UP_71__VALUE2_MASK 0xff0000
11344 #define MC_IO_DEBUG_UP_71__VALUE2__SHIFT 0x10
11345 #define MC_IO_DEBUG_UP_71__VALUE3_MASK 0xff000000
11346 #define MC_IO_DEBUG_UP_71__VALUE3__SHIFT 0x18
11347 #define MC_IO_DEBUG_UP_72__VALUE0_MASK 0xff
11348 #define MC_IO_DEBUG_UP_72__VALUE0__SHIFT 0x0
11349 #define MC_IO_DEBUG_UP_72__VALUE1_MASK 0xff00
11350 #define MC_IO_DEBUG_UP_72__VALUE1__SHIFT 0x8
11351 #define MC_IO_DEBUG_UP_72__VALUE2_MASK 0xff0000
11352 #define MC_IO_DEBUG_UP_72__VALUE2__SHIFT 0x10
11353 #define MC_IO_DEBUG_UP_72__VALUE3_MASK 0xff000000
11354 #define MC_IO_DEBUG_UP_72__VALUE3__SHIFT 0x18
11355 #define MC_IO_DEBUG_UP_73__VALUE0_MASK 0xff
11356 #define MC_IO_DEBUG_UP_73__VALUE0__SHIFT 0x0
11357 #define MC_IO_DEBUG_UP_73__VALUE1_MASK 0xff00
11358 #define MC_IO_DEBUG_UP_73__VALUE1__SHIFT 0x8
11359 #define MC_IO_DEBUG_UP_73__VALUE2_MASK 0xff0000
11360 #define MC_IO_DEBUG_UP_73__VALUE2__SHIFT 0x10
11361 #define MC_IO_DEBUG_UP_73__VALUE3_MASK 0xff000000
11362 #define MC_IO_DEBUG_UP_73__VALUE3__SHIFT 0x18
11363 #define MC_IO_DEBUG_UP_74__VALUE0_MASK 0xff
11364 #define MC_IO_DEBUG_UP_74__VALUE0__SHIFT 0x0
11365 #define MC_IO_DEBUG_UP_74__VALUE1_MASK 0xff00
11366 #define MC_IO_DEBUG_UP_74__VALUE1__SHIFT 0x8
11367 #define MC_IO_DEBUG_UP_74__VALUE2_MASK 0xff0000
11368 #define MC_IO_DEBUG_UP_74__VALUE2__SHIFT 0x10
11369 #define MC_IO_DEBUG_UP_74__VALUE3_MASK 0xff000000
11370 #define MC_IO_DEBUG_UP_74__VALUE3__SHIFT 0x18
11371 #define MC_IO_DEBUG_UP_75__VALUE0_MASK 0xff
11372 #define MC_IO_DEBUG_UP_75__VALUE0__SHIFT 0x0
11373 #define MC_IO_DEBUG_UP_75__VALUE1_MASK 0xff00
11374 #define MC_IO_DEBUG_UP_75__VALUE1__SHIFT 0x8
11375 #define MC_IO_DEBUG_UP_75__VALUE2_MASK 0xff0000
11376 #define MC_IO_DEBUG_UP_75__VALUE2__SHIFT 0x10
11377 #define MC_IO_DEBUG_UP_75__VALUE3_MASK 0xff000000
11378 #define MC_IO_DEBUG_UP_75__VALUE3__SHIFT 0x18
11379 #define MC_IO_DEBUG_UP_76__VALUE0_MASK 0xff
11380 #define MC_IO_DEBUG_UP_76__VALUE0__SHIFT 0x0
11381 #define MC_IO_DEBUG_UP_76__VALUE1_MASK 0xff00
11382 #define MC_IO_DEBUG_UP_76__VALUE1__SHIFT 0x8
11383 #define MC_IO_DEBUG_UP_76__VALUE2_MASK 0xff0000
11384 #define MC_IO_DEBUG_UP_76__VALUE2__SHIFT 0x10
11385 #define MC_IO_DEBUG_UP_76__VALUE3_MASK 0xff000000
11386 #define MC_IO_DEBUG_UP_76__VALUE3__SHIFT 0x18
11387 #define MC_IO_DEBUG_UP_77__VALUE0_MASK 0xff
11388 #define MC_IO_DEBUG_UP_77__VALUE0__SHIFT 0x0
11389 #define MC_IO_DEBUG_UP_77__VALUE1_MASK 0xff00
11390 #define MC_IO_DEBUG_UP_77__VALUE1__SHIFT 0x8
11391 #define MC_IO_DEBUG_UP_77__VALUE2_MASK 0xff0000
11392 #define MC_IO_DEBUG_UP_77__VALUE2__SHIFT 0x10
11393 #define MC_IO_DEBUG_UP_77__VALUE3_MASK 0xff000000
11394 #define MC_IO_DEBUG_UP_77__VALUE3__SHIFT 0x18
11395 #define MC_IO_DEBUG_UP_78__VALUE0_MASK 0xff
11396 #define MC_IO_DEBUG_UP_78__VALUE0__SHIFT 0x0
11397 #define MC_IO_DEBUG_UP_78__VALUE1_MASK 0xff00
11398 #define MC_IO_DEBUG_UP_78__VALUE1__SHIFT 0x8
11399 #define MC_IO_DEBUG_UP_78__VALUE2_MASK 0xff0000
11400 #define MC_IO_DEBUG_UP_78__VALUE2__SHIFT 0x10
11401 #define MC_IO_DEBUG_UP_78__VALUE3_MASK 0xff000000
11402 #define MC_IO_DEBUG_UP_78__VALUE3__SHIFT 0x18
11403 #define MC_IO_DEBUG_UP_79__VALUE0_MASK 0xff
11404 #define MC_IO_DEBUG_UP_79__VALUE0__SHIFT 0x0
11405 #define MC_IO_DEBUG_UP_79__VALUE1_MASK 0xff00
11406 #define MC_IO_DEBUG_UP_79__VALUE1__SHIFT 0x8
11407 #define MC_IO_DEBUG_UP_79__VALUE2_MASK 0xff0000
11408 #define MC_IO_DEBUG_UP_79__VALUE2__SHIFT 0x10
11409 #define MC_IO_DEBUG_UP_79__VALUE3_MASK 0xff000000
11410 #define MC_IO_DEBUG_UP_79__VALUE3__SHIFT 0x18
11411 #define MC_IO_DEBUG_UP_80__VALUE0_MASK 0xff
11412 #define MC_IO_DEBUG_UP_80__VALUE0__SHIFT 0x0
11413 #define MC_IO_DEBUG_UP_80__VALUE1_MASK 0xff00
11414 #define MC_IO_DEBUG_UP_80__VALUE1__SHIFT 0x8
11415 #define MC_IO_DEBUG_UP_80__VALUE2_MASK 0xff0000
11416 #define MC_IO_DEBUG_UP_80__VALUE2__SHIFT 0x10
11417 #define MC_IO_DEBUG_UP_80__VALUE3_MASK 0xff000000
11418 #define MC_IO_DEBUG_UP_80__VALUE3__SHIFT 0x18
11419 #define MC_IO_DEBUG_UP_81__VALUE0_MASK 0xff
11420 #define MC_IO_DEBUG_UP_81__VALUE0__SHIFT 0x0
11421 #define MC_IO_DEBUG_UP_81__VALUE1_MASK 0xff00
11422 #define MC_IO_DEBUG_UP_81__VALUE1__SHIFT 0x8
11423 #define MC_IO_DEBUG_UP_81__VALUE2_MASK 0xff0000
11424 #define MC_IO_DEBUG_UP_81__VALUE2__SHIFT 0x10
11425 #define MC_IO_DEBUG_UP_81__VALUE3_MASK 0xff000000
11426 #define MC_IO_DEBUG_UP_81__VALUE3__SHIFT 0x18
11427 #define MC_IO_DEBUG_UP_82__VALUE0_MASK 0xff
11428 #define MC_IO_DEBUG_UP_82__VALUE0__SHIFT 0x0
11429 #define MC_IO_DEBUG_UP_82__VALUE1_MASK 0xff00
11430 #define MC_IO_DEBUG_UP_82__VALUE1__SHIFT 0x8
11431 #define MC_IO_DEBUG_UP_82__VALUE2_MASK 0xff0000
11432 #define MC_IO_DEBUG_UP_82__VALUE2__SHIFT 0x10
11433 #define MC_IO_DEBUG_UP_82__VALUE3_MASK 0xff000000
11434 #define MC_IO_DEBUG_UP_82__VALUE3__SHIFT 0x18
11435 #define MC_IO_DEBUG_UP_83__VALUE0_MASK 0xff
11436 #define MC_IO_DEBUG_UP_83__VALUE0__SHIFT 0x0
11437 #define MC_IO_DEBUG_UP_83__VALUE1_MASK 0xff00
11438 #define MC_IO_DEBUG_UP_83__VALUE1__SHIFT 0x8
11439 #define MC_IO_DEBUG_UP_83__VALUE2_MASK 0xff0000
11440 #define MC_IO_DEBUG_UP_83__VALUE2__SHIFT 0x10
11441 #define MC_IO_DEBUG_UP_83__VALUE3_MASK 0xff000000
11442 #define MC_IO_DEBUG_UP_83__VALUE3__SHIFT 0x18
11443 #define MC_IO_DEBUG_UP_84__VALUE0_MASK 0xff
11444 #define MC_IO_DEBUG_UP_84__VALUE0__SHIFT 0x0
11445 #define MC_IO_DEBUG_UP_84__VALUE1_MASK 0xff00
11446 #define MC_IO_DEBUG_UP_84__VALUE1__SHIFT 0x8
11447 #define MC_IO_DEBUG_UP_84__VALUE2_MASK 0xff0000
11448 #define MC_IO_DEBUG_UP_84__VALUE2__SHIFT 0x10
11449 #define MC_IO_DEBUG_UP_84__VALUE3_MASK 0xff000000
11450 #define MC_IO_DEBUG_UP_84__VALUE3__SHIFT 0x18
11451 #define MC_IO_DEBUG_UP_85__VALUE0_MASK 0xff
11452 #define MC_IO_DEBUG_UP_85__VALUE0__SHIFT 0x0
11453 #define MC_IO_DEBUG_UP_85__VALUE1_MASK 0xff00
11454 #define MC_IO_DEBUG_UP_85__VALUE1__SHIFT 0x8
11455 #define MC_IO_DEBUG_UP_85__VALUE2_MASK 0xff0000
11456 #define MC_IO_DEBUG_UP_85__VALUE2__SHIFT 0x10
11457 #define MC_IO_DEBUG_UP_85__VALUE3_MASK 0xff000000
11458 #define MC_IO_DEBUG_UP_85__VALUE3__SHIFT 0x18
11459 #define MC_IO_DEBUG_UP_86__VALUE0_MASK 0xff
11460 #define MC_IO_DEBUG_UP_86__VALUE0__SHIFT 0x0
11461 #define MC_IO_DEBUG_UP_86__VALUE1_MASK 0xff00
11462 #define MC_IO_DEBUG_UP_86__VALUE1__SHIFT 0x8
11463 #define MC_IO_DEBUG_UP_86__VALUE2_MASK 0xff0000
11464 #define MC_IO_DEBUG_UP_86__VALUE2__SHIFT 0x10
11465 #define MC_IO_DEBUG_UP_86__VALUE3_MASK 0xff000000
11466 #define MC_IO_DEBUG_UP_86__VALUE3__SHIFT 0x18
11467 #define MC_IO_DEBUG_UP_87__VALUE0_MASK 0xff
11468 #define MC_IO_DEBUG_UP_87__VALUE0__SHIFT 0x0
11469 #define MC_IO_DEBUG_UP_87__VALUE1_MASK 0xff00
11470 #define MC_IO_DEBUG_UP_87__VALUE1__SHIFT 0x8
11471 #define MC_IO_DEBUG_UP_87__VALUE2_MASK 0xff0000
11472 #define MC_IO_DEBUG_UP_87__VALUE2__SHIFT 0x10
11473 #define MC_IO_DEBUG_UP_87__VALUE3_MASK 0xff000000
11474 #define MC_IO_DEBUG_UP_87__VALUE3__SHIFT 0x18
11475 #define MC_IO_DEBUG_UP_88__VALUE0_MASK 0xff
11476 #define MC_IO_DEBUG_UP_88__VALUE0__SHIFT 0x0
11477 #define MC_IO_DEBUG_UP_88__VALUE1_MASK 0xff00
11478 #define MC_IO_DEBUG_UP_88__VALUE1__SHIFT 0x8
11479 #define MC_IO_DEBUG_UP_88__VALUE2_MASK 0xff0000
11480 #define MC_IO_DEBUG_UP_88__VALUE2__SHIFT 0x10
11481 #define MC_IO_DEBUG_UP_88__VALUE3_MASK 0xff000000
11482 #define MC_IO_DEBUG_UP_88__VALUE3__SHIFT 0x18
11483 #define MC_IO_DEBUG_UP_89__VALUE0_MASK 0xff
11484 #define MC_IO_DEBUG_UP_89__VALUE0__SHIFT 0x0
11485 #define MC_IO_DEBUG_UP_89__VALUE1_MASK 0xff00
11486 #define MC_IO_DEBUG_UP_89__VALUE1__SHIFT 0x8
11487 #define MC_IO_DEBUG_UP_89__VALUE2_MASK 0xff0000
11488 #define MC_IO_DEBUG_UP_89__VALUE2__SHIFT 0x10
11489 #define MC_IO_DEBUG_UP_89__VALUE3_MASK 0xff000000
11490 #define MC_IO_DEBUG_UP_89__VALUE3__SHIFT 0x18
11491 #define MC_IO_DEBUG_UP_90__VALUE0_MASK 0xff
11492 #define MC_IO_DEBUG_UP_90__VALUE0__SHIFT 0x0
11493 #define MC_IO_DEBUG_UP_90__VALUE1_MASK 0xff00
11494 #define MC_IO_DEBUG_UP_90__VALUE1__SHIFT 0x8
11495 #define MC_IO_DEBUG_UP_90__VALUE2_MASK 0xff0000
11496 #define MC_IO_DEBUG_UP_90__VALUE2__SHIFT 0x10
11497 #define MC_IO_DEBUG_UP_90__VALUE3_MASK 0xff000000
11498 #define MC_IO_DEBUG_UP_90__VALUE3__SHIFT 0x18
11499 #define MC_IO_DEBUG_UP_91__VALUE0_MASK 0xff
11500 #define MC_IO_DEBUG_UP_91__VALUE0__SHIFT 0x0
11501 #define MC_IO_DEBUG_UP_91__VALUE1_MASK 0xff00
11502 #define MC_IO_DEBUG_UP_91__VALUE1__SHIFT 0x8
11503 #define MC_IO_DEBUG_UP_91__VALUE2_MASK 0xff0000
11504 #define MC_IO_DEBUG_UP_91__VALUE2__SHIFT 0x10
11505 #define MC_IO_DEBUG_UP_91__VALUE3_MASK 0xff000000
11506 #define MC_IO_DEBUG_UP_91__VALUE3__SHIFT 0x18
11507 #define MC_IO_DEBUG_UP_92__VALUE0_MASK 0xff
11508 #define MC_IO_DEBUG_UP_92__VALUE0__SHIFT 0x0
11509 #define MC_IO_DEBUG_UP_92__VALUE1_MASK 0xff00
11510 #define MC_IO_DEBUG_UP_92__VALUE1__SHIFT 0x8
11511 #define MC_IO_DEBUG_UP_92__VALUE2_MASK 0xff0000
11512 #define MC_IO_DEBUG_UP_92__VALUE2__SHIFT 0x10
11513 #define MC_IO_DEBUG_UP_92__VALUE3_MASK 0xff000000
11514 #define MC_IO_DEBUG_UP_92__VALUE3__SHIFT 0x18
11515 #define MC_IO_DEBUG_UP_93__VALUE0_MASK 0xff
11516 #define MC_IO_DEBUG_UP_93__VALUE0__SHIFT 0x0
11517 #define MC_IO_DEBUG_UP_93__VALUE1_MASK 0xff00
11518 #define MC_IO_DEBUG_UP_93__VALUE1__SHIFT 0x8
11519 #define MC_IO_DEBUG_UP_93__VALUE2_MASK 0xff0000
11520 #define MC_IO_DEBUG_UP_93__VALUE2__SHIFT 0x10
11521 #define MC_IO_DEBUG_UP_93__VALUE3_MASK 0xff000000
11522 #define MC_IO_DEBUG_UP_93__VALUE3__SHIFT 0x18
11523 #define MC_IO_DEBUG_UP_94__VALUE0_MASK 0xff
11524 #define MC_IO_DEBUG_UP_94__VALUE0__SHIFT 0x0
11525 #define MC_IO_DEBUG_UP_94__VALUE1_MASK 0xff00
11526 #define MC_IO_DEBUG_UP_94__VALUE1__SHIFT 0x8
11527 #define MC_IO_DEBUG_UP_94__VALUE2_MASK 0xff0000
11528 #define MC_IO_DEBUG_UP_94__VALUE2__SHIFT 0x10
11529 #define MC_IO_DEBUG_UP_94__VALUE3_MASK 0xff000000
11530 #define MC_IO_DEBUG_UP_94__VALUE3__SHIFT 0x18
11531 #define MC_IO_DEBUG_UP_95__VALUE0_MASK 0xff
11532 #define MC_IO_DEBUG_UP_95__VALUE0__SHIFT 0x0
11533 #define MC_IO_DEBUG_UP_95__VALUE1_MASK 0xff00
11534 #define MC_IO_DEBUG_UP_95__VALUE1__SHIFT 0x8
11535 #define MC_IO_DEBUG_UP_95__VALUE2_MASK 0xff0000
11536 #define MC_IO_DEBUG_UP_95__VALUE2__SHIFT 0x10
11537 #define MC_IO_DEBUG_UP_95__VALUE3_MASK 0xff000000
11538 #define MC_IO_DEBUG_UP_95__VALUE3__SHIFT 0x18
11539 #define MC_IO_DEBUG_UP_96__VALUE0_MASK 0xff
11540 #define MC_IO_DEBUG_UP_96__VALUE0__SHIFT 0x0
11541 #define MC_IO_DEBUG_UP_96__VALUE1_MASK 0xff00
11542 #define MC_IO_DEBUG_UP_96__VALUE1__SHIFT 0x8
11543 #define MC_IO_DEBUG_UP_96__VALUE2_MASK 0xff0000
11544 #define MC_IO_DEBUG_UP_96__VALUE2__SHIFT 0x10
11545 #define MC_IO_DEBUG_UP_96__VALUE3_MASK 0xff000000
11546 #define MC_IO_DEBUG_UP_96__VALUE3__SHIFT 0x18
11547 #define MC_IO_DEBUG_UP_97__VALUE0_MASK 0xff
11548 #define MC_IO_DEBUG_UP_97__VALUE0__SHIFT 0x0
11549 #define MC_IO_DEBUG_UP_97__VALUE1_MASK 0xff00
11550 #define MC_IO_DEBUG_UP_97__VALUE1__SHIFT 0x8
11551 #define MC_IO_DEBUG_UP_97__VALUE2_MASK 0xff0000
11552 #define MC_IO_DEBUG_UP_97__VALUE2__SHIFT 0x10
11553 #define MC_IO_DEBUG_UP_97__VALUE3_MASK 0xff000000
11554 #define MC_IO_DEBUG_UP_97__VALUE3__SHIFT 0x18
11555 #define MC_IO_DEBUG_UP_98__VALUE0_MASK 0xff
11556 #define MC_IO_DEBUG_UP_98__VALUE0__SHIFT 0x0
11557 #define MC_IO_DEBUG_UP_98__VALUE1_MASK 0xff00
11558 #define MC_IO_DEBUG_UP_98__VALUE1__SHIFT 0x8
11559 #define MC_IO_DEBUG_UP_98__VALUE2_MASK 0xff0000
11560 #define MC_IO_DEBUG_UP_98__VALUE2__SHIFT 0x10
11561 #define MC_IO_DEBUG_UP_98__VALUE3_MASK 0xff000000
11562 #define MC_IO_DEBUG_UP_98__VALUE3__SHIFT 0x18
11563 #define MC_IO_DEBUG_UP_99__VALUE0_MASK 0xff
11564 #define MC_IO_DEBUG_UP_99__VALUE0__SHIFT 0x0
11565 #define MC_IO_DEBUG_UP_99__VALUE1_MASK 0xff00
11566 #define MC_IO_DEBUG_UP_99__VALUE1__SHIFT 0x8
11567 #define MC_IO_DEBUG_UP_99__VALUE2_MASK 0xff0000
11568 #define MC_IO_DEBUG_UP_99__VALUE2__SHIFT 0x10
11569 #define MC_IO_DEBUG_UP_99__VALUE3_MASK 0xff000000
11570 #define MC_IO_DEBUG_UP_99__VALUE3__SHIFT 0x18
11571 #define MC_IO_DEBUG_UP_100__VALUE0_MASK 0xff
11572 #define MC_IO_DEBUG_UP_100__VALUE0__SHIFT 0x0
11573 #define MC_IO_DEBUG_UP_100__VALUE1_MASK 0xff00
11574 #define MC_IO_DEBUG_UP_100__VALUE1__SHIFT 0x8
11575 #define MC_IO_DEBUG_UP_100__VALUE2_MASK 0xff0000
11576 #define MC_IO_DEBUG_UP_100__VALUE2__SHIFT 0x10
11577 #define MC_IO_DEBUG_UP_100__VALUE3_MASK 0xff000000
11578 #define MC_IO_DEBUG_UP_100__VALUE3__SHIFT 0x18
11579 #define MC_IO_DEBUG_UP_101__VALUE0_MASK 0xff
11580 #define MC_IO_DEBUG_UP_101__VALUE0__SHIFT 0x0
11581 #define MC_IO_DEBUG_UP_101__VALUE1_MASK 0xff00
11582 #define MC_IO_DEBUG_UP_101__VALUE1__SHIFT 0x8
11583 #define MC_IO_DEBUG_UP_101__VALUE2_MASK 0xff0000
11584 #define MC_IO_DEBUG_UP_101__VALUE2__SHIFT 0x10
11585 #define MC_IO_DEBUG_UP_101__VALUE3_MASK 0xff000000
11586 #define MC_IO_DEBUG_UP_101__VALUE3__SHIFT 0x18
11587 #define MC_IO_DEBUG_UP_102__VALUE0_MASK 0xff
11588 #define MC_IO_DEBUG_UP_102__VALUE0__SHIFT 0x0
11589 #define MC_IO_DEBUG_UP_102__VALUE1_MASK 0xff00
11590 #define MC_IO_DEBUG_UP_102__VALUE1__SHIFT 0x8
11591 #define MC_IO_DEBUG_UP_102__VALUE2_MASK 0xff0000
11592 #define MC_IO_DEBUG_UP_102__VALUE2__SHIFT 0x10
11593 #define MC_IO_DEBUG_UP_102__VALUE3_MASK 0xff000000
11594 #define MC_IO_DEBUG_UP_102__VALUE3__SHIFT 0x18
11595 #define MC_IO_DEBUG_UP_103__VALUE0_MASK 0xff
11596 #define MC_IO_DEBUG_UP_103__VALUE0__SHIFT 0x0
11597 #define MC_IO_DEBUG_UP_103__VALUE1_MASK 0xff00
11598 #define MC_IO_DEBUG_UP_103__VALUE1__SHIFT 0x8
11599 #define MC_IO_DEBUG_UP_103__VALUE2_MASK 0xff0000
11600 #define MC_IO_DEBUG_UP_103__VALUE2__SHIFT 0x10
11601 #define MC_IO_DEBUG_UP_103__VALUE3_MASK 0xff000000
11602 #define MC_IO_DEBUG_UP_103__VALUE3__SHIFT 0x18
11603 #define MC_IO_DEBUG_UP_104__VALUE0_MASK 0xff
11604 #define MC_IO_DEBUG_UP_104__VALUE0__SHIFT 0x0
11605 #define MC_IO_DEBUG_UP_104__VALUE1_MASK 0xff00
11606 #define MC_IO_DEBUG_UP_104__VALUE1__SHIFT 0x8
11607 #define MC_IO_DEBUG_UP_104__VALUE2_MASK 0xff0000
11608 #define MC_IO_DEBUG_UP_104__VALUE2__SHIFT 0x10
11609 #define MC_IO_DEBUG_UP_104__VALUE3_MASK 0xff000000
11610 #define MC_IO_DEBUG_UP_104__VALUE3__SHIFT 0x18
11611 #define MC_IO_DEBUG_UP_105__VALUE0_MASK 0xff
11612 #define MC_IO_DEBUG_UP_105__VALUE0__SHIFT 0x0
11613 #define MC_IO_DEBUG_UP_105__VALUE1_MASK 0xff00
11614 #define MC_IO_DEBUG_UP_105__VALUE1__SHIFT 0x8
11615 #define MC_IO_DEBUG_UP_105__VALUE2_MASK 0xff0000
11616 #define MC_IO_DEBUG_UP_105__VALUE2__SHIFT 0x10
11617 #define MC_IO_DEBUG_UP_105__VALUE3_MASK 0xff000000
11618 #define MC_IO_DEBUG_UP_105__VALUE3__SHIFT 0x18
11619 #define MC_IO_DEBUG_UP_106__VALUE0_MASK 0xff
11620 #define MC_IO_DEBUG_UP_106__VALUE0__SHIFT 0x0
11621 #define MC_IO_DEBUG_UP_106__VALUE1_MASK 0xff00
11622 #define MC_IO_DEBUG_UP_106__VALUE1__SHIFT 0x8
11623 #define MC_IO_DEBUG_UP_106__VALUE2_MASK 0xff0000
11624 #define MC_IO_DEBUG_UP_106__VALUE2__SHIFT 0x10
11625 #define MC_IO_DEBUG_UP_106__VALUE3_MASK 0xff000000
11626 #define MC_IO_DEBUG_UP_106__VALUE3__SHIFT 0x18
11627 #define MC_IO_DEBUG_UP_107__VALUE0_MASK 0xff
11628 #define MC_IO_DEBUG_UP_107__VALUE0__SHIFT 0x0
11629 #define MC_IO_DEBUG_UP_107__VALUE1_MASK 0xff00
11630 #define MC_IO_DEBUG_UP_107__VALUE1__SHIFT 0x8
11631 #define MC_IO_DEBUG_UP_107__VALUE2_MASK 0xff0000
11632 #define MC_IO_DEBUG_UP_107__VALUE2__SHIFT 0x10
11633 #define MC_IO_DEBUG_UP_107__VALUE3_MASK 0xff000000
11634 #define MC_IO_DEBUG_UP_107__VALUE3__SHIFT 0x18
11635 #define MC_IO_DEBUG_UP_108__VALUE0_MASK 0xff
11636 #define MC_IO_DEBUG_UP_108__VALUE0__SHIFT 0x0
11637 #define MC_IO_DEBUG_UP_108__VALUE1_MASK 0xff00
11638 #define MC_IO_DEBUG_UP_108__VALUE1__SHIFT 0x8
11639 #define MC_IO_DEBUG_UP_108__VALUE2_MASK 0xff0000
11640 #define MC_IO_DEBUG_UP_108__VALUE2__SHIFT 0x10
11641 #define MC_IO_DEBUG_UP_108__VALUE3_MASK 0xff000000
11642 #define MC_IO_DEBUG_UP_108__VALUE3__SHIFT 0x18
11643 #define MC_IO_DEBUG_UP_109__VALUE0_MASK 0xff
11644 #define MC_IO_DEBUG_UP_109__VALUE0__SHIFT 0x0
11645 #define MC_IO_DEBUG_UP_109__VALUE1_MASK 0xff00
11646 #define MC_IO_DEBUG_UP_109__VALUE1__SHIFT 0x8
11647 #define MC_IO_DEBUG_UP_109__VALUE2_MASK 0xff0000
11648 #define MC_IO_DEBUG_UP_109__VALUE2__SHIFT 0x10
11649 #define MC_IO_DEBUG_UP_109__VALUE3_MASK 0xff000000
11650 #define MC_IO_DEBUG_UP_109__VALUE3__SHIFT 0x18
11651 #define MC_IO_DEBUG_UP_110__VALUE0_MASK 0xff
11652 #define MC_IO_DEBUG_UP_110__VALUE0__SHIFT 0x0
11653 #define MC_IO_DEBUG_UP_110__VALUE1_MASK 0xff00
11654 #define MC_IO_DEBUG_UP_110__VALUE1__SHIFT 0x8
11655 #define MC_IO_DEBUG_UP_110__VALUE2_MASK 0xff0000
11656 #define MC_IO_DEBUG_UP_110__VALUE2__SHIFT 0x10
11657 #define MC_IO_DEBUG_UP_110__VALUE3_MASK 0xff000000
11658 #define MC_IO_DEBUG_UP_110__VALUE3__SHIFT 0x18
11659 #define MC_IO_DEBUG_UP_111__VALUE0_MASK 0xff
11660 #define MC_IO_DEBUG_UP_111__VALUE0__SHIFT 0x0
11661 #define MC_IO_DEBUG_UP_111__VALUE1_MASK 0xff00
11662 #define MC_IO_DEBUG_UP_111__VALUE1__SHIFT 0x8
11663 #define MC_IO_DEBUG_UP_111__VALUE2_MASK 0xff0000
11664 #define MC_IO_DEBUG_UP_111__VALUE2__SHIFT 0x10
11665 #define MC_IO_DEBUG_UP_111__VALUE3_MASK 0xff000000
11666 #define MC_IO_DEBUG_UP_111__VALUE3__SHIFT 0x18
11667 #define MC_IO_DEBUG_UP_112__VALUE0_MASK 0xff
11668 #define MC_IO_DEBUG_UP_112__VALUE0__SHIFT 0x0
11669 #define MC_IO_DEBUG_UP_112__VALUE1_MASK 0xff00
11670 #define MC_IO_DEBUG_UP_112__VALUE1__SHIFT 0x8
11671 #define MC_IO_DEBUG_UP_112__VALUE2_MASK 0xff0000
11672 #define MC_IO_DEBUG_UP_112__VALUE2__SHIFT 0x10
11673 #define MC_IO_DEBUG_UP_112__VALUE3_MASK 0xff000000
11674 #define MC_IO_DEBUG_UP_112__VALUE3__SHIFT 0x18
11675 #define MC_IO_DEBUG_UP_113__VALUE0_MASK 0xff
11676 #define MC_IO_DEBUG_UP_113__VALUE0__SHIFT 0x0
11677 #define MC_IO_DEBUG_UP_113__VALUE1_MASK 0xff00
11678 #define MC_IO_DEBUG_UP_113__VALUE1__SHIFT 0x8
11679 #define MC_IO_DEBUG_UP_113__VALUE2_MASK 0xff0000
11680 #define MC_IO_DEBUG_UP_113__VALUE2__SHIFT 0x10
11681 #define MC_IO_DEBUG_UP_113__VALUE3_MASK 0xff000000
11682 #define MC_IO_DEBUG_UP_113__VALUE3__SHIFT 0x18
11683 #define MC_IO_DEBUG_UP_114__VALUE0_MASK 0xff
11684 #define MC_IO_DEBUG_UP_114__VALUE0__SHIFT 0x0
11685 #define MC_IO_DEBUG_UP_114__VALUE1_MASK 0xff00
11686 #define MC_IO_DEBUG_UP_114__VALUE1__SHIFT 0x8
11687 #define MC_IO_DEBUG_UP_114__VALUE2_MASK 0xff0000
11688 #define MC_IO_DEBUG_UP_114__VALUE2__SHIFT 0x10
11689 #define MC_IO_DEBUG_UP_114__VALUE3_MASK 0xff000000
11690 #define MC_IO_DEBUG_UP_114__VALUE3__SHIFT 0x18
11691 #define MC_IO_DEBUG_UP_115__VALUE0_MASK 0xff
11692 #define MC_IO_DEBUG_UP_115__VALUE0__SHIFT 0x0
11693 #define MC_IO_DEBUG_UP_115__VALUE1_MASK 0xff00
11694 #define MC_IO_DEBUG_UP_115__VALUE1__SHIFT 0x8
11695 #define MC_IO_DEBUG_UP_115__VALUE2_MASK 0xff0000
11696 #define MC_IO_DEBUG_UP_115__VALUE2__SHIFT 0x10
11697 #define MC_IO_DEBUG_UP_115__VALUE3_MASK 0xff000000
11698 #define MC_IO_DEBUG_UP_115__VALUE3__SHIFT 0x18
11699 #define MC_IO_DEBUG_UP_116__VALUE0_MASK 0xff
11700 #define MC_IO_DEBUG_UP_116__VALUE0__SHIFT 0x0
11701 #define MC_IO_DEBUG_UP_116__VALUE1_MASK 0xff00
11702 #define MC_IO_DEBUG_UP_116__VALUE1__SHIFT 0x8
11703 #define MC_IO_DEBUG_UP_116__VALUE2_MASK 0xff0000
11704 #define MC_IO_DEBUG_UP_116__VALUE2__SHIFT 0x10
11705 #define MC_IO_DEBUG_UP_116__VALUE3_MASK 0xff000000
11706 #define MC_IO_DEBUG_UP_116__VALUE3__SHIFT 0x18
11707 #define MC_IO_DEBUG_UP_117__VALUE0_MASK 0xff
11708 #define MC_IO_DEBUG_UP_117__VALUE0__SHIFT 0x0
11709 #define MC_IO_DEBUG_UP_117__VALUE1_MASK 0xff00
11710 #define MC_IO_DEBUG_UP_117__VALUE1__SHIFT 0x8
11711 #define MC_IO_DEBUG_UP_117__VALUE2_MASK 0xff0000
11712 #define MC_IO_DEBUG_UP_117__VALUE2__SHIFT 0x10
11713 #define MC_IO_DEBUG_UP_117__VALUE3_MASK 0xff000000
11714 #define MC_IO_DEBUG_UP_117__VALUE3__SHIFT 0x18
11715 #define MC_IO_DEBUG_UP_118__VALUE0_MASK 0xff
11716 #define MC_IO_DEBUG_UP_118__VALUE0__SHIFT 0x0
11717 #define MC_IO_DEBUG_UP_118__VALUE1_MASK 0xff00
11718 #define MC_IO_DEBUG_UP_118__VALUE1__SHIFT 0x8
11719 #define MC_IO_DEBUG_UP_118__VALUE2_MASK 0xff0000
11720 #define MC_IO_DEBUG_UP_118__VALUE2__SHIFT 0x10
11721 #define MC_IO_DEBUG_UP_118__VALUE3_MASK 0xff000000
11722 #define MC_IO_DEBUG_UP_118__VALUE3__SHIFT 0x18
11723 #define MC_IO_DEBUG_UP_119__VALUE0_MASK 0xff
11724 #define MC_IO_DEBUG_UP_119__VALUE0__SHIFT 0x0
11725 #define MC_IO_DEBUG_UP_119__VALUE1_MASK 0xff00
11726 #define MC_IO_DEBUG_UP_119__VALUE1__SHIFT 0x8
11727 #define MC_IO_DEBUG_UP_119__VALUE2_MASK 0xff0000
11728 #define MC_IO_DEBUG_UP_119__VALUE2__SHIFT 0x10
11729 #define MC_IO_DEBUG_UP_119__VALUE3_MASK 0xff000000
11730 #define MC_IO_DEBUG_UP_119__VALUE3__SHIFT 0x18
11731 #define MC_IO_DEBUG_UP_120__VALUE0_MASK 0xff
11732 #define MC_IO_DEBUG_UP_120__VALUE0__SHIFT 0x0
11733 #define MC_IO_DEBUG_UP_120__VALUE1_MASK 0xff00
11734 #define MC_IO_DEBUG_UP_120__VALUE1__SHIFT 0x8
11735 #define MC_IO_DEBUG_UP_120__VALUE2_MASK 0xff0000
11736 #define MC_IO_DEBUG_UP_120__VALUE2__SHIFT 0x10
11737 #define MC_IO_DEBUG_UP_120__VALUE3_MASK 0xff000000
11738 #define MC_IO_DEBUG_UP_120__VALUE3__SHIFT 0x18
11739 #define MC_IO_DEBUG_UP_121__VALUE0_MASK 0xff
11740 #define MC_IO_DEBUG_UP_121__VALUE0__SHIFT 0x0
11741 #define MC_IO_DEBUG_UP_121__VALUE1_MASK 0xff00
11742 #define MC_IO_DEBUG_UP_121__VALUE1__SHIFT 0x8
11743 #define MC_IO_DEBUG_UP_121__VALUE2_MASK 0xff0000
11744 #define MC_IO_DEBUG_UP_121__VALUE2__SHIFT 0x10
11745 #define MC_IO_DEBUG_UP_121__VALUE3_MASK 0xff000000
11746 #define MC_IO_DEBUG_UP_121__VALUE3__SHIFT 0x18
11747 #define MC_IO_DEBUG_UP_122__VALUE0_MASK 0xff
11748 #define MC_IO_DEBUG_UP_122__VALUE0__SHIFT 0x0
11749 #define MC_IO_DEBUG_UP_122__VALUE1_MASK 0xff00
11750 #define MC_IO_DEBUG_UP_122__VALUE1__SHIFT 0x8
11751 #define MC_IO_DEBUG_UP_122__VALUE2_MASK 0xff0000
11752 #define MC_IO_DEBUG_UP_122__VALUE2__SHIFT 0x10
11753 #define MC_IO_DEBUG_UP_122__VALUE3_MASK 0xff000000
11754 #define MC_IO_DEBUG_UP_122__VALUE3__SHIFT 0x18
11755 #define MC_IO_DEBUG_UP_123__VALUE0_MASK 0xff
11756 #define MC_IO_DEBUG_UP_123__VALUE0__SHIFT 0x0
11757 #define MC_IO_DEBUG_UP_123__VALUE1_MASK 0xff00
11758 #define MC_IO_DEBUG_UP_123__VALUE1__SHIFT 0x8
11759 #define MC_IO_DEBUG_UP_123__VALUE2_MASK 0xff0000
11760 #define MC_IO_DEBUG_UP_123__VALUE2__SHIFT 0x10
11761 #define MC_IO_DEBUG_UP_123__VALUE3_MASK 0xff000000
11762 #define MC_IO_DEBUG_UP_123__VALUE3__SHIFT 0x18
11763 #define MC_IO_DEBUG_UP_124__VALUE0_MASK 0xff
11764 #define MC_IO_DEBUG_UP_124__VALUE0__SHIFT 0x0
11765 #define MC_IO_DEBUG_UP_124__VALUE1_MASK 0xff00
11766 #define MC_IO_DEBUG_UP_124__VALUE1__SHIFT 0x8
11767 #define MC_IO_DEBUG_UP_124__VALUE2_MASK 0xff0000
11768 #define MC_IO_DEBUG_UP_124__VALUE2__SHIFT 0x10
11769 #define MC_IO_DEBUG_UP_124__VALUE3_MASK 0xff000000
11770 #define MC_IO_DEBUG_UP_124__VALUE3__SHIFT 0x18
11771 #define MC_IO_DEBUG_UP_125__VALUE0_MASK 0xff
11772 #define MC_IO_DEBUG_UP_125__VALUE0__SHIFT 0x0
11773 #define MC_IO_DEBUG_UP_125__VALUE1_MASK 0xff00
11774 #define MC_IO_DEBUG_UP_125__VALUE1__SHIFT 0x8
11775 #define MC_IO_DEBUG_UP_125__VALUE2_MASK 0xff0000
11776 #define MC_IO_DEBUG_UP_125__VALUE2__SHIFT 0x10
11777 #define MC_IO_DEBUG_UP_125__VALUE3_MASK 0xff000000
11778 #define MC_IO_DEBUG_UP_125__VALUE3__SHIFT 0x18
11779 #define MC_IO_DEBUG_UP_126__VALUE0_MASK 0xff
11780 #define MC_IO_DEBUG_UP_126__VALUE0__SHIFT 0x0
11781 #define MC_IO_DEBUG_UP_126__VALUE1_MASK 0xff00
11782 #define MC_IO_DEBUG_UP_126__VALUE1__SHIFT 0x8
11783 #define MC_IO_DEBUG_UP_126__VALUE2_MASK 0xff0000
11784 #define MC_IO_DEBUG_UP_126__VALUE2__SHIFT 0x10
11785 #define MC_IO_DEBUG_UP_126__VALUE3_MASK 0xff000000
11786 #define MC_IO_DEBUG_UP_126__VALUE3__SHIFT 0x18
11787 #define MC_IO_DEBUG_UP_127__VALUE0_MASK 0xff
11788 #define MC_IO_DEBUG_UP_127__VALUE0__SHIFT 0x0
11789 #define MC_IO_DEBUG_UP_127__VALUE1_MASK 0xff00
11790 #define MC_IO_DEBUG_UP_127__VALUE1__SHIFT 0x8
11791 #define MC_IO_DEBUG_UP_127__VALUE2_MASK 0xff0000
11792 #define MC_IO_DEBUG_UP_127__VALUE2__SHIFT 0x10
11793 #define MC_IO_DEBUG_UP_127__VALUE3_MASK 0xff000000
11794 #define MC_IO_DEBUG_UP_127__VALUE3__SHIFT 0x18
11795 #define MC_IO_DEBUG_UP_128__VALUE0_MASK 0xff
11796 #define MC_IO_DEBUG_UP_128__VALUE0__SHIFT 0x0
11797 #define MC_IO_DEBUG_UP_128__VALUE1_MASK 0xff00
11798 #define MC_IO_DEBUG_UP_128__VALUE1__SHIFT 0x8
11799 #define MC_IO_DEBUG_UP_128__VALUE2_MASK 0xff0000
11800 #define MC_IO_DEBUG_UP_128__VALUE2__SHIFT 0x10
11801 #define MC_IO_DEBUG_UP_128__VALUE3_MASK 0xff000000
11802 #define MC_IO_DEBUG_UP_128__VALUE3__SHIFT 0x18
11803 #define MC_IO_DEBUG_UP_129__VALUE0_MASK 0xff
11804 #define MC_IO_DEBUG_UP_129__VALUE0__SHIFT 0x0
11805 #define MC_IO_DEBUG_UP_129__VALUE1_MASK 0xff00
11806 #define MC_IO_DEBUG_UP_129__VALUE1__SHIFT 0x8
11807 #define MC_IO_DEBUG_UP_129__VALUE2_MASK 0xff0000
11808 #define MC_IO_DEBUG_UP_129__VALUE2__SHIFT 0x10
11809 #define MC_IO_DEBUG_UP_129__VALUE3_MASK 0xff000000
11810 #define MC_IO_DEBUG_UP_129__VALUE3__SHIFT 0x18
11811 #define MC_IO_DEBUG_UP_130__VALUE0_MASK 0xff
11812 #define MC_IO_DEBUG_UP_130__VALUE0__SHIFT 0x0
11813 #define MC_IO_DEBUG_UP_130__VALUE1_MASK 0xff00
11814 #define MC_IO_DEBUG_UP_130__VALUE1__SHIFT 0x8
11815 #define MC_IO_DEBUG_UP_130__VALUE2_MASK 0xff0000
11816 #define MC_IO_DEBUG_UP_130__VALUE2__SHIFT 0x10
11817 #define MC_IO_DEBUG_UP_130__VALUE3_MASK 0xff000000
11818 #define MC_IO_DEBUG_UP_130__VALUE3__SHIFT 0x18
11819 #define MC_IO_DEBUG_UP_131__VALUE0_MASK 0xff
11820 #define MC_IO_DEBUG_UP_131__VALUE0__SHIFT 0x0
11821 #define MC_IO_DEBUG_UP_131__VALUE1_MASK 0xff00
11822 #define MC_IO_DEBUG_UP_131__VALUE1__SHIFT 0x8
11823 #define MC_IO_DEBUG_UP_131__VALUE2_MASK 0xff0000
11824 #define MC_IO_DEBUG_UP_131__VALUE2__SHIFT 0x10
11825 #define MC_IO_DEBUG_UP_131__VALUE3_MASK 0xff000000
11826 #define MC_IO_DEBUG_UP_131__VALUE3__SHIFT 0x18
11827 #define MC_IO_DEBUG_UP_132__VALUE0_MASK 0xff
11828 #define MC_IO_DEBUG_UP_132__VALUE0__SHIFT 0x0
11829 #define MC_IO_DEBUG_UP_132__VALUE1_MASK 0xff00
11830 #define MC_IO_DEBUG_UP_132__VALUE1__SHIFT 0x8
11831 #define MC_IO_DEBUG_UP_132__VALUE2_MASK 0xff0000
11832 #define MC_IO_DEBUG_UP_132__VALUE2__SHIFT 0x10
11833 #define MC_IO_DEBUG_UP_132__VALUE3_MASK 0xff000000
11834 #define MC_IO_DEBUG_UP_132__VALUE3__SHIFT 0x18
11835 #define MC_IO_DEBUG_UP_133__VALUE0_MASK 0xff
11836 #define MC_IO_DEBUG_UP_133__VALUE0__SHIFT 0x0
11837 #define MC_IO_DEBUG_UP_133__VALUE1_MASK 0xff00
11838 #define MC_IO_DEBUG_UP_133__VALUE1__SHIFT 0x8
11839 #define MC_IO_DEBUG_UP_133__VALUE2_MASK 0xff0000
11840 #define MC_IO_DEBUG_UP_133__VALUE2__SHIFT 0x10
11841 #define MC_IO_DEBUG_UP_133__VALUE3_MASK 0xff000000
11842 #define MC_IO_DEBUG_UP_133__VALUE3__SHIFT 0x18
11843 #define MC_IO_DEBUG_UP_134__VALUE0_MASK 0xff
11844 #define MC_IO_DEBUG_UP_134__VALUE0__SHIFT 0x0
11845 #define MC_IO_DEBUG_UP_134__VALUE1_MASK 0xff00
11846 #define MC_IO_DEBUG_UP_134__VALUE1__SHIFT 0x8
11847 #define MC_IO_DEBUG_UP_134__VALUE2_MASK 0xff0000
11848 #define MC_IO_DEBUG_UP_134__VALUE2__SHIFT 0x10
11849 #define MC_IO_DEBUG_UP_134__VALUE3_MASK 0xff000000
11850 #define MC_IO_DEBUG_UP_134__VALUE3__SHIFT 0x18
11851 #define MC_IO_DEBUG_UP_135__VALUE0_MASK 0xff
11852 #define MC_IO_DEBUG_UP_135__VALUE0__SHIFT 0x0
11853 #define MC_IO_DEBUG_UP_135__VALUE1_MASK 0xff00
11854 #define MC_IO_DEBUG_UP_135__VALUE1__SHIFT 0x8
11855 #define MC_IO_DEBUG_UP_135__VALUE2_MASK 0xff0000
11856 #define MC_IO_DEBUG_UP_135__VALUE2__SHIFT 0x10
11857 #define MC_IO_DEBUG_UP_135__VALUE3_MASK 0xff000000
11858 #define MC_IO_DEBUG_UP_135__VALUE3__SHIFT 0x18
11859 #define MC_IO_DEBUG_UP_136__VALUE0_MASK 0xff
11860 #define MC_IO_DEBUG_UP_136__VALUE0__SHIFT 0x0
11861 #define MC_IO_DEBUG_UP_136__VALUE1_MASK 0xff00
11862 #define MC_IO_DEBUG_UP_136__VALUE1__SHIFT 0x8
11863 #define MC_IO_DEBUG_UP_136__VALUE2_MASK 0xff0000
11864 #define MC_IO_DEBUG_UP_136__VALUE2__SHIFT 0x10
11865 #define MC_IO_DEBUG_UP_136__VALUE3_MASK 0xff000000
11866 #define MC_IO_DEBUG_UP_136__VALUE3__SHIFT 0x18
11867 #define MC_IO_DEBUG_UP_137__VALUE0_MASK 0xff
11868 #define MC_IO_DEBUG_UP_137__VALUE0__SHIFT 0x0
11869 #define MC_IO_DEBUG_UP_137__VALUE1_MASK 0xff00
11870 #define MC_IO_DEBUG_UP_137__VALUE1__SHIFT 0x8
11871 #define MC_IO_DEBUG_UP_137__VALUE2_MASK 0xff0000
11872 #define MC_IO_DEBUG_UP_137__VALUE2__SHIFT 0x10
11873 #define MC_IO_DEBUG_UP_137__VALUE3_MASK 0xff000000
11874 #define MC_IO_DEBUG_UP_137__VALUE3__SHIFT 0x18
11875 #define MC_IO_DEBUG_UP_138__VALUE0_MASK 0xff
11876 #define MC_IO_DEBUG_UP_138__VALUE0__SHIFT 0x0
11877 #define MC_IO_DEBUG_UP_138__VALUE1_MASK 0xff00
11878 #define MC_IO_DEBUG_UP_138__VALUE1__SHIFT 0x8
11879 #define MC_IO_DEBUG_UP_138__VALUE2_MASK 0xff0000
11880 #define MC_IO_DEBUG_UP_138__VALUE2__SHIFT 0x10
11881 #define MC_IO_DEBUG_UP_138__VALUE3_MASK 0xff000000
11882 #define MC_IO_DEBUG_UP_138__VALUE3__SHIFT 0x18
11883 #define MC_IO_DEBUG_UP_139__VALUE0_MASK 0xff
11884 #define MC_IO_DEBUG_UP_139__VALUE0__SHIFT 0x0
11885 #define MC_IO_DEBUG_UP_139__VALUE1_MASK 0xff00
11886 #define MC_IO_DEBUG_UP_139__VALUE1__SHIFT 0x8
11887 #define MC_IO_DEBUG_UP_139__VALUE2_MASK 0xff0000
11888 #define MC_IO_DEBUG_UP_139__VALUE2__SHIFT 0x10
11889 #define MC_IO_DEBUG_UP_139__VALUE3_MASK 0xff000000
11890 #define MC_IO_DEBUG_UP_139__VALUE3__SHIFT 0x18
11891 #define MC_IO_DEBUG_UP_140__VALUE0_MASK 0xff
11892 #define MC_IO_DEBUG_UP_140__VALUE0__SHIFT 0x0
11893 #define MC_IO_DEBUG_UP_140__VALUE1_MASK 0xff00
11894 #define MC_IO_DEBUG_UP_140__VALUE1__SHIFT 0x8
11895 #define MC_IO_DEBUG_UP_140__VALUE2_MASK 0xff0000
11896 #define MC_IO_DEBUG_UP_140__VALUE2__SHIFT 0x10
11897 #define MC_IO_DEBUG_UP_140__VALUE3_MASK 0xff000000
11898 #define MC_IO_DEBUG_UP_140__VALUE3__SHIFT 0x18
11899 #define MC_IO_DEBUG_UP_141__VALUE0_MASK 0xff
11900 #define MC_IO_DEBUG_UP_141__VALUE0__SHIFT 0x0
11901 #define MC_IO_DEBUG_UP_141__VALUE1_MASK 0xff00
11902 #define MC_IO_DEBUG_UP_141__VALUE1__SHIFT 0x8
11903 #define MC_IO_DEBUG_UP_141__VALUE2_MASK 0xff0000
11904 #define MC_IO_DEBUG_UP_141__VALUE2__SHIFT 0x10
11905 #define MC_IO_DEBUG_UP_141__VALUE3_MASK 0xff000000
11906 #define MC_IO_DEBUG_UP_141__VALUE3__SHIFT 0x18
11907 #define MC_IO_DEBUG_UP_142__VALUE0_MASK 0xff
11908 #define MC_IO_DEBUG_UP_142__VALUE0__SHIFT 0x0
11909 #define MC_IO_DEBUG_UP_142__VALUE1_MASK 0xff00
11910 #define MC_IO_DEBUG_UP_142__VALUE1__SHIFT 0x8
11911 #define MC_IO_DEBUG_UP_142__VALUE2_MASK 0xff0000
11912 #define MC_IO_DEBUG_UP_142__VALUE2__SHIFT 0x10
11913 #define MC_IO_DEBUG_UP_142__VALUE3_MASK 0xff000000
11914 #define MC_IO_DEBUG_UP_142__VALUE3__SHIFT 0x18
11915 #define MC_IO_DEBUG_UP_143__VALUE0_MASK 0xff
11916 #define MC_IO_DEBUG_UP_143__VALUE0__SHIFT 0x0
11917 #define MC_IO_DEBUG_UP_143__VALUE1_MASK 0xff00
11918 #define MC_IO_DEBUG_UP_143__VALUE1__SHIFT 0x8
11919 #define MC_IO_DEBUG_UP_143__VALUE2_MASK 0xff0000
11920 #define MC_IO_DEBUG_UP_143__VALUE2__SHIFT 0x10
11921 #define MC_IO_DEBUG_UP_143__VALUE3_MASK 0xff000000
11922 #define MC_IO_DEBUG_UP_143__VALUE3__SHIFT 0x18
11923 #define MC_IO_DEBUG_UP_144__VALUE0_MASK 0xff
11924 #define MC_IO_DEBUG_UP_144__VALUE0__SHIFT 0x0
11925 #define MC_IO_DEBUG_UP_144__VALUE1_MASK 0xff00
11926 #define MC_IO_DEBUG_UP_144__VALUE1__SHIFT 0x8
11927 #define MC_IO_DEBUG_UP_144__VALUE2_MASK 0xff0000
11928 #define MC_IO_DEBUG_UP_144__VALUE2__SHIFT 0x10
11929 #define MC_IO_DEBUG_UP_144__VALUE3_MASK 0xff000000
11930 #define MC_IO_DEBUG_UP_144__VALUE3__SHIFT 0x18
11931 #define MC_IO_DEBUG_UP_145__VALUE0_MASK 0xff
11932 #define MC_IO_DEBUG_UP_145__VALUE0__SHIFT 0x0
11933 #define MC_IO_DEBUG_UP_145__VALUE1_MASK 0xff00
11934 #define MC_IO_DEBUG_UP_145__VALUE1__SHIFT 0x8
11935 #define MC_IO_DEBUG_UP_145__VALUE2_MASK 0xff0000
11936 #define MC_IO_DEBUG_UP_145__VALUE2__SHIFT 0x10
11937 #define MC_IO_DEBUG_UP_145__VALUE3_MASK 0xff000000
11938 #define MC_IO_DEBUG_UP_145__VALUE3__SHIFT 0x18
11939 #define MC_IO_DEBUG_UP_146__VALUE0_MASK 0xff
11940 #define MC_IO_DEBUG_UP_146__VALUE0__SHIFT 0x0
11941 #define MC_IO_DEBUG_UP_146__VALUE1_MASK 0xff00
11942 #define MC_IO_DEBUG_UP_146__VALUE1__SHIFT 0x8
11943 #define MC_IO_DEBUG_UP_146__VALUE2_MASK 0xff0000
11944 #define MC_IO_DEBUG_UP_146__VALUE2__SHIFT 0x10
11945 #define MC_IO_DEBUG_UP_146__VALUE3_MASK 0xff000000
11946 #define MC_IO_DEBUG_UP_146__VALUE3__SHIFT 0x18
11947 #define MC_IO_DEBUG_UP_147__VALUE0_MASK 0xff
11948 #define MC_IO_DEBUG_UP_147__VALUE0__SHIFT 0x0
11949 #define MC_IO_DEBUG_UP_147__VALUE1_MASK 0xff00
11950 #define MC_IO_DEBUG_UP_147__VALUE1__SHIFT 0x8
11951 #define MC_IO_DEBUG_UP_147__VALUE2_MASK 0xff0000
11952 #define MC_IO_DEBUG_UP_147__VALUE2__SHIFT 0x10
11953 #define MC_IO_DEBUG_UP_147__VALUE3_MASK 0xff000000
11954 #define MC_IO_DEBUG_UP_147__VALUE3__SHIFT 0x18
11955 #define MC_IO_DEBUG_UP_148__VALUE0_MASK 0xff
11956 #define MC_IO_DEBUG_UP_148__VALUE0__SHIFT 0x0
11957 #define MC_IO_DEBUG_UP_148__VALUE1_MASK 0xff00
11958 #define MC_IO_DEBUG_UP_148__VALUE1__SHIFT 0x8
11959 #define MC_IO_DEBUG_UP_148__VALUE2_MASK 0xff0000
11960 #define MC_IO_DEBUG_UP_148__VALUE2__SHIFT 0x10
11961 #define MC_IO_DEBUG_UP_148__VALUE3_MASK 0xff000000
11962 #define MC_IO_DEBUG_UP_148__VALUE3__SHIFT 0x18
11963 #define MC_IO_DEBUG_UP_149__VALUE0_MASK 0xff
11964 #define MC_IO_DEBUG_UP_149__VALUE0__SHIFT 0x0
11965 #define MC_IO_DEBUG_UP_149__VALUE1_MASK 0xff00
11966 #define MC_IO_DEBUG_UP_149__VALUE1__SHIFT 0x8
11967 #define MC_IO_DEBUG_UP_149__VALUE2_MASK 0xff0000
11968 #define MC_IO_DEBUG_UP_149__VALUE2__SHIFT 0x10
11969 #define MC_IO_DEBUG_UP_149__VALUE3_MASK 0xff000000
11970 #define MC_IO_DEBUG_UP_149__VALUE3__SHIFT 0x18
11971 #define MC_IO_DEBUG_UP_150__VALUE0_MASK 0xff
11972 #define MC_IO_DEBUG_UP_150__VALUE0__SHIFT 0x0
11973 #define MC_IO_DEBUG_UP_150__VALUE1_MASK 0xff00
11974 #define MC_IO_DEBUG_UP_150__VALUE1__SHIFT 0x8
11975 #define MC_IO_DEBUG_UP_150__VALUE2_MASK 0xff0000
11976 #define MC_IO_DEBUG_UP_150__VALUE2__SHIFT 0x10
11977 #define MC_IO_DEBUG_UP_150__VALUE3_MASK 0xff000000
11978 #define MC_IO_DEBUG_UP_150__VALUE3__SHIFT 0x18
11979 #define MC_IO_DEBUG_UP_151__VALUE0_MASK 0xff
11980 #define MC_IO_DEBUG_UP_151__VALUE0__SHIFT 0x0
11981 #define MC_IO_DEBUG_UP_151__VALUE1_MASK 0xff00
11982 #define MC_IO_DEBUG_UP_151__VALUE1__SHIFT 0x8
11983 #define MC_IO_DEBUG_UP_151__VALUE2_MASK 0xff0000
11984 #define MC_IO_DEBUG_UP_151__VALUE2__SHIFT 0x10
11985 #define MC_IO_DEBUG_UP_151__VALUE3_MASK 0xff000000
11986 #define MC_IO_DEBUG_UP_151__VALUE3__SHIFT 0x18
11987 #define MC_IO_DEBUG_UP_152__VALUE0_MASK 0xff
11988 #define MC_IO_DEBUG_UP_152__VALUE0__SHIFT 0x0
11989 #define MC_IO_DEBUG_UP_152__VALUE1_MASK 0xff00
11990 #define MC_IO_DEBUG_UP_152__VALUE1__SHIFT 0x8
11991 #define MC_IO_DEBUG_UP_152__VALUE2_MASK 0xff0000
11992 #define MC_IO_DEBUG_UP_152__VALUE2__SHIFT 0x10
11993 #define MC_IO_DEBUG_UP_152__VALUE3_MASK 0xff000000
11994 #define MC_IO_DEBUG_UP_152__VALUE3__SHIFT 0x18
11995 #define MC_IO_DEBUG_UP_153__VALUE0_MASK 0xff
11996 #define MC_IO_DEBUG_UP_153__VALUE0__SHIFT 0x0
11997 #define MC_IO_DEBUG_UP_153__VALUE1_MASK 0xff00
11998 #define MC_IO_DEBUG_UP_153__VALUE1__SHIFT 0x8
11999 #define MC_IO_DEBUG_UP_153__VALUE2_MASK 0xff0000
12000 #define MC_IO_DEBUG_UP_153__VALUE2__SHIFT 0x10
12001 #define MC_IO_DEBUG_UP_153__VALUE3_MASK 0xff000000
12002 #define MC_IO_DEBUG_UP_153__VALUE3__SHIFT 0x18
12003 #define MC_IO_DEBUG_UP_154__VALUE0_MASK 0xff
12004 #define MC_IO_DEBUG_UP_154__VALUE0__SHIFT 0x0
12005 #define MC_IO_DEBUG_UP_154__VALUE1_MASK 0xff00
12006 #define MC_IO_DEBUG_UP_154__VALUE1__SHIFT 0x8
12007 #define MC_IO_DEBUG_UP_154__VALUE2_MASK 0xff0000
12008 #define MC_IO_DEBUG_UP_154__VALUE2__SHIFT 0x10
12009 #define MC_IO_DEBUG_UP_154__VALUE3_MASK 0xff000000
12010 #define MC_IO_DEBUG_UP_154__VALUE3__SHIFT 0x18
12011 #define MC_IO_DEBUG_UP_155__VALUE0_MASK 0xff
12012 #define MC_IO_DEBUG_UP_155__VALUE0__SHIFT 0x0
12013 #define MC_IO_DEBUG_UP_155__VALUE1_MASK 0xff00
12014 #define MC_IO_DEBUG_UP_155__VALUE1__SHIFT 0x8
12015 #define MC_IO_DEBUG_UP_155__VALUE2_MASK 0xff0000
12016 #define MC_IO_DEBUG_UP_155__VALUE2__SHIFT 0x10
12017 #define MC_IO_DEBUG_UP_155__VALUE3_MASK 0xff000000
12018 #define MC_IO_DEBUG_UP_155__VALUE3__SHIFT 0x18
12019 #define MC_IO_DEBUG_UP_156__VALUE0_MASK 0xff
12020 #define MC_IO_DEBUG_UP_156__VALUE0__SHIFT 0x0
12021 #define MC_IO_DEBUG_UP_156__VALUE1_MASK 0xff00
12022 #define MC_IO_DEBUG_UP_156__VALUE1__SHIFT 0x8
12023 #define MC_IO_DEBUG_UP_156__VALUE2_MASK 0xff0000
12024 #define MC_IO_DEBUG_UP_156__VALUE2__SHIFT 0x10
12025 #define MC_IO_DEBUG_UP_156__VALUE3_MASK 0xff000000
12026 #define MC_IO_DEBUG_UP_156__VALUE3__SHIFT 0x18
12027 #define MC_IO_DEBUG_UP_157__VALUE0_MASK 0xff
12028 #define MC_IO_DEBUG_UP_157__VALUE0__SHIFT 0x0
12029 #define MC_IO_DEBUG_UP_157__VALUE1_MASK 0xff00
12030 #define MC_IO_DEBUG_UP_157__VALUE1__SHIFT 0x8
12031 #define MC_IO_DEBUG_UP_157__VALUE2_MASK 0xff0000
12032 #define MC_IO_DEBUG_UP_157__VALUE2__SHIFT 0x10
12033 #define MC_IO_DEBUG_UP_157__VALUE3_MASK 0xff000000
12034 #define MC_IO_DEBUG_UP_157__VALUE3__SHIFT 0x18
12035 #define MC_IO_DEBUG_UP_158__VALUE0_MASK 0xff
12036 #define MC_IO_DEBUG_UP_158__VALUE0__SHIFT 0x0
12037 #define MC_IO_DEBUG_UP_158__VALUE1_MASK 0xff00
12038 #define MC_IO_DEBUG_UP_158__VALUE1__SHIFT 0x8
12039 #define MC_IO_DEBUG_UP_158__VALUE2_MASK 0xff0000
12040 #define MC_IO_DEBUG_UP_158__VALUE2__SHIFT 0x10
12041 #define MC_IO_DEBUG_UP_158__VALUE3_MASK 0xff000000
12042 #define MC_IO_DEBUG_UP_158__VALUE3__SHIFT 0x18
12043 #define MC_IO_DEBUG_UP_159__VALUE0_MASK 0xff
12044 #define MC_IO_DEBUG_UP_159__VALUE0__SHIFT 0x0
12045 #define MC_IO_DEBUG_UP_159__VALUE1_MASK 0xff00
12046 #define MC_IO_DEBUG_UP_159__VALUE1__SHIFT 0x8
12047 #define MC_IO_DEBUG_UP_159__VALUE2_MASK 0xff0000
12048 #define MC_IO_DEBUG_UP_159__VALUE2__SHIFT 0x10
12049 #define MC_IO_DEBUG_UP_159__VALUE3_MASK 0xff000000
12050 #define MC_IO_DEBUG_UP_159__VALUE3__SHIFT 0x18
12051 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0_MASK 0xff
12052 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE0__SHIFT 0x0
12053 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1_MASK 0xff00
12054 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE1__SHIFT 0x8
12055 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2_MASK 0xff0000
12056 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE2__SHIFT 0x10
12057 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3_MASK 0xff000000
12058 #define MC_IO_DEBUG_DQB0L_MISC_D0__VALUE3__SHIFT 0x18
12059 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0_MASK 0xff
12060 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE0__SHIFT 0x0
12061 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1_MASK 0xff00
12062 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE1__SHIFT 0x8
12063 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2_MASK 0xff0000
12064 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE2__SHIFT 0x10
12065 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3_MASK 0xff000000
12066 #define MC_IO_DEBUG_DQB0H_MISC_D0__VALUE3__SHIFT 0x18
12067 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0_MASK 0xff
12068 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE0__SHIFT 0x0
12069 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1_MASK 0xff00
12070 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE1__SHIFT 0x8
12071 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2_MASK 0xff0000
12072 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE2__SHIFT 0x10
12073 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3_MASK 0xff000000
12074 #define MC_IO_DEBUG_DQB1L_MISC_D0__VALUE3__SHIFT 0x18
12075 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0_MASK 0xff
12076 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE0__SHIFT 0x0
12077 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1_MASK 0xff00
12078 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE1__SHIFT 0x8
12079 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2_MASK 0xff0000
12080 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE2__SHIFT 0x10
12081 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3_MASK 0xff000000
12082 #define MC_IO_DEBUG_DQB1H_MISC_D0__VALUE3__SHIFT 0x18
12083 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0_MASK 0xff
12084 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE0__SHIFT 0x0
12085 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1_MASK 0xff00
12086 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE1__SHIFT 0x8
12087 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2_MASK 0xff0000
12088 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE2__SHIFT 0x10
12089 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3_MASK 0xff000000
12090 #define MC_IO_DEBUG_DQB2L_MISC_D0__VALUE3__SHIFT 0x18
12091 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0_MASK 0xff
12092 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE0__SHIFT 0x0
12093 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1_MASK 0xff00
12094 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE1__SHIFT 0x8
12095 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2_MASK 0xff0000
12096 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE2__SHIFT 0x10
12097 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3_MASK 0xff000000
12098 #define MC_IO_DEBUG_DQB2H_MISC_D0__VALUE3__SHIFT 0x18
12099 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0_MASK 0xff
12100 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE0__SHIFT 0x0
12101 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1_MASK 0xff00
12102 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE1__SHIFT 0x8
12103 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2_MASK 0xff0000
12104 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE2__SHIFT 0x10
12105 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3_MASK 0xff000000
12106 #define MC_IO_DEBUG_DQB3L_MISC_D0__VALUE3__SHIFT 0x18
12107 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0_MASK 0xff
12108 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE0__SHIFT 0x0
12109 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1_MASK 0xff00
12110 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE1__SHIFT 0x8
12111 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2_MASK 0xff0000
12112 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE2__SHIFT 0x10
12113 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3_MASK 0xff000000
12114 #define MC_IO_DEBUG_DQB3H_MISC_D0__VALUE3__SHIFT 0x18
12115 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE0_MASK 0xff
12116 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE0__SHIFT 0x0
12117 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE1_MASK 0xff00
12118 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE1__SHIFT 0x8
12119 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE2_MASK 0xff0000
12120 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE2__SHIFT 0x10
12121 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE3_MASK 0xff000000
12122 #define MC_IO_DEBUG_DBI_MISC_D0__VALUE3__SHIFT 0x18
12123 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE0_MASK 0xff
12124 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE0__SHIFT 0x0
12125 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE1_MASK 0xff00
12126 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE1__SHIFT 0x8
12127 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE2_MASK 0xff0000
12128 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE2__SHIFT 0x10
12129 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE3_MASK 0xff000000
12130 #define MC_IO_DEBUG_EDC_MISC_D0__VALUE3__SHIFT 0x18
12131 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE0_MASK 0xff
12132 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE0__SHIFT 0x0
12133 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE1_MASK 0xff00
12134 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE1__SHIFT 0x8
12135 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE2_MASK 0xff0000
12136 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE2__SHIFT 0x10
12137 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE3_MASK 0xff000000
12138 #define MC_IO_DEBUG_WCK_MISC_D0__VALUE3__SHIFT 0x18
12139 #define MC_IO_DEBUG_CK_MISC_D0__VALUE0_MASK 0xff
12140 #define MC_IO_DEBUG_CK_MISC_D0__VALUE0__SHIFT 0x0
12141 #define MC_IO_DEBUG_CK_MISC_D0__VALUE1_MASK 0xff00
12142 #define MC_IO_DEBUG_CK_MISC_D0__VALUE1__SHIFT 0x8
12143 #define MC_IO_DEBUG_CK_MISC_D0__VALUE2_MASK 0xff0000
12144 #define MC_IO_DEBUG_CK_MISC_D0__VALUE2__SHIFT 0x10
12145 #define MC_IO_DEBUG_CK_MISC_D0__VALUE3_MASK 0xff000000
12146 #define MC_IO_DEBUG_CK_MISC_D0__VALUE3__SHIFT 0x18
12147 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0_MASK 0xff
12148 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE0__SHIFT 0x0
12149 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1_MASK 0xff00
12150 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE1__SHIFT 0x8
12151 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2_MASK 0xff0000
12152 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE2__SHIFT 0x10
12153 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3_MASK 0xff000000
12154 #define MC_IO_DEBUG_ADDRL_MISC_D0__VALUE3__SHIFT 0x18
12155 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0_MASK 0xff
12156 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE0__SHIFT 0x0
12157 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1_MASK 0xff00
12158 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE1__SHIFT 0x8
12159 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2_MASK 0xff0000
12160 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE2__SHIFT 0x10
12161 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3_MASK 0xff000000
12162 #define MC_IO_DEBUG_ADDRH_MISC_D0__VALUE3__SHIFT 0x18
12163 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0_MASK 0xff
12164 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE0__SHIFT 0x0
12165 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1_MASK 0xff00
12166 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE1__SHIFT 0x8
12167 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2_MASK 0xff0000
12168 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE2__SHIFT 0x10
12169 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3_MASK 0xff000000
12170 #define MC_IO_DEBUG_ACMD_MISC_D0__VALUE3__SHIFT 0x18
12171 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE0_MASK 0xff
12172 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE0__SHIFT 0x0
12173 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE1_MASK 0xff00
12174 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE1__SHIFT 0x8
12175 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE2_MASK 0xff0000
12176 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE2__SHIFT 0x10
12177 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE3_MASK 0xff000000
12178 #define MC_IO_DEBUG_CMD_MISC_D0__VALUE3__SHIFT 0x18
12179 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0_MASK 0xff
12180 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE0__SHIFT 0x0
12181 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1_MASK 0xff00
12182 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE1__SHIFT 0x8
12183 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2_MASK 0xff0000
12184 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE2__SHIFT 0x10
12185 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3_MASK 0xff000000
12186 #define MC_IO_DEBUG_DQB0L_MISC_D1__VALUE3__SHIFT 0x18
12187 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0_MASK 0xff
12188 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE0__SHIFT 0x0
12189 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1_MASK 0xff00
12190 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE1__SHIFT 0x8
12191 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2_MASK 0xff0000
12192 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE2__SHIFT 0x10
12193 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3_MASK 0xff000000
12194 #define MC_IO_DEBUG_DQB0H_MISC_D1__VALUE3__SHIFT 0x18
12195 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0_MASK 0xff
12196 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE0__SHIFT 0x0
12197 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1_MASK 0xff00
12198 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE1__SHIFT 0x8
12199 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2_MASK 0xff0000
12200 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE2__SHIFT 0x10
12201 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3_MASK 0xff000000
12202 #define MC_IO_DEBUG_DQB1L_MISC_D1__VALUE3__SHIFT 0x18
12203 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0_MASK 0xff
12204 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE0__SHIFT 0x0
12205 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1_MASK 0xff00
12206 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE1__SHIFT 0x8
12207 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2_MASK 0xff0000
12208 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE2__SHIFT 0x10
12209 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3_MASK 0xff000000
12210 #define MC_IO_DEBUG_DQB1H_MISC_D1__VALUE3__SHIFT 0x18
12211 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0_MASK 0xff
12212 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE0__SHIFT 0x0
12213 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1_MASK 0xff00
12214 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE1__SHIFT 0x8
12215 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2_MASK 0xff0000
12216 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE2__SHIFT 0x10
12217 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3_MASK 0xff000000
12218 #define MC_IO_DEBUG_DQB2L_MISC_D1__VALUE3__SHIFT 0x18
12219 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0_MASK 0xff
12220 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE0__SHIFT 0x0
12221 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1_MASK 0xff00
12222 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE1__SHIFT 0x8
12223 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2_MASK 0xff0000
12224 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE2__SHIFT 0x10
12225 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3_MASK 0xff000000
12226 #define MC_IO_DEBUG_DQB2H_MISC_D1__VALUE3__SHIFT 0x18
12227 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0_MASK 0xff
12228 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE0__SHIFT 0x0
12229 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1_MASK 0xff00
12230 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE1__SHIFT 0x8
12231 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2_MASK 0xff0000
12232 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE2__SHIFT 0x10
12233 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3_MASK 0xff000000
12234 #define MC_IO_DEBUG_DQB3L_MISC_D1__VALUE3__SHIFT 0x18
12235 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0_MASK 0xff
12236 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE0__SHIFT 0x0
12237 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1_MASK 0xff00
12238 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE1__SHIFT 0x8
12239 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2_MASK 0xff0000
12240 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE2__SHIFT 0x10
12241 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3_MASK 0xff000000
12242 #define MC_IO_DEBUG_DQB3H_MISC_D1__VALUE3__SHIFT 0x18
12243 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE0_MASK 0xff
12244 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE0__SHIFT 0x0
12245 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE1_MASK 0xff00
12246 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE1__SHIFT 0x8
12247 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE2_MASK 0xff0000
12248 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE2__SHIFT 0x10
12249 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE3_MASK 0xff000000
12250 #define MC_IO_DEBUG_DBI_MISC_D1__VALUE3__SHIFT 0x18
12251 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE0_MASK 0xff
12252 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE0__SHIFT 0x0
12253 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE1_MASK 0xff00
12254 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE1__SHIFT 0x8
12255 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE2_MASK 0xff0000
12256 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE2__SHIFT 0x10
12257 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE3_MASK 0xff000000
12258 #define MC_IO_DEBUG_EDC_MISC_D1__VALUE3__SHIFT 0x18
12259 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE0_MASK 0xff
12260 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE0__SHIFT 0x0
12261 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE1_MASK 0xff00
12262 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE1__SHIFT 0x8
12263 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE2_MASK 0xff0000
12264 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE2__SHIFT 0x10
12265 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE3_MASK 0xff000000
12266 #define MC_IO_DEBUG_WCK_MISC_D1__VALUE3__SHIFT 0x18
12267 #define MC_IO_DEBUG_CK_MISC_D1__VALUE0_MASK 0xff
12268 #define MC_IO_DEBUG_CK_MISC_D1__VALUE0__SHIFT 0x0
12269 #define MC_IO_DEBUG_CK_MISC_D1__VALUE1_MASK 0xff00
12270 #define MC_IO_DEBUG_CK_MISC_D1__VALUE1__SHIFT 0x8
12271 #define MC_IO_DEBUG_CK_MISC_D1__VALUE2_MASK 0xff0000
12272 #define MC_IO_DEBUG_CK_MISC_D1__VALUE2__SHIFT 0x10
12273 #define MC_IO_DEBUG_CK_MISC_D1__VALUE3_MASK 0xff000000
12274 #define MC_IO_DEBUG_CK_MISC_D1__VALUE3__SHIFT 0x18
12275 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0_MASK 0xff
12276 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE0__SHIFT 0x0
12277 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1_MASK 0xff00
12278 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE1__SHIFT 0x8
12279 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2_MASK 0xff0000
12280 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE2__SHIFT 0x10
12281 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3_MASK 0xff000000
12282 #define MC_IO_DEBUG_ADDRL_MISC_D1__VALUE3__SHIFT 0x18
12283 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0_MASK 0xff
12284 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE0__SHIFT 0x0
12285 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1_MASK 0xff00
12286 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE1__SHIFT 0x8
12287 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2_MASK 0xff0000
12288 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE2__SHIFT 0x10
12289 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3_MASK 0xff000000
12290 #define MC_IO_DEBUG_ADDRH_MISC_D1__VALUE3__SHIFT 0x18
12291 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0_MASK 0xff
12292 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE0__SHIFT 0x0
12293 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1_MASK 0xff00
12294 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE1__SHIFT 0x8
12295 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2_MASK 0xff0000
12296 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE2__SHIFT 0x10
12297 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3_MASK 0xff000000
12298 #define MC_IO_DEBUG_ACMD_MISC_D1__VALUE3__SHIFT 0x18
12299 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE0_MASK 0xff
12300 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE0__SHIFT 0x0
12301 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE1_MASK 0xff00
12302 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE1__SHIFT 0x8
12303 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE2_MASK 0xff0000
12304 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE2__SHIFT 0x10
12305 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE3_MASK 0xff000000
12306 #define MC_IO_DEBUG_CMD_MISC_D1__VALUE3__SHIFT 0x18
12307 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0_MASK 0xff
12308 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE0__SHIFT 0x0
12309 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1_MASK 0xff00
12310 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE1__SHIFT 0x8
12311 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2_MASK 0xff0000
12312 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE2__SHIFT 0x10
12313 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3_MASK 0xff000000
12314 #define MC_IO_DEBUG_DQB0L_CLKSEL_D0__VALUE3__SHIFT 0x18
12315 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0_MASK 0xff
12316 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE0__SHIFT 0x0
12317 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1_MASK 0xff00
12318 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE1__SHIFT 0x8
12319 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2_MASK 0xff0000
12320 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE2__SHIFT 0x10
12321 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3_MASK 0xff000000
12322 #define MC_IO_DEBUG_DQB0H_CLKSEL_D0__VALUE3__SHIFT 0x18
12323 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0_MASK 0xff
12324 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE0__SHIFT 0x0
12325 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1_MASK 0xff00
12326 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE1__SHIFT 0x8
12327 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2_MASK 0xff0000
12328 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE2__SHIFT 0x10
12329 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3_MASK 0xff000000
12330 #define MC_IO_DEBUG_DQB1L_CLKSEL_D0__VALUE3__SHIFT 0x18
12331 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0_MASK 0xff
12332 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE0__SHIFT 0x0
12333 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1_MASK 0xff00
12334 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE1__SHIFT 0x8
12335 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2_MASK 0xff0000
12336 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE2__SHIFT 0x10
12337 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3_MASK 0xff000000
12338 #define MC_IO_DEBUG_DQB1H_CLKSEL_D0__VALUE3__SHIFT 0x18
12339 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0_MASK 0xff
12340 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE0__SHIFT 0x0
12341 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1_MASK 0xff00
12342 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE1__SHIFT 0x8
12343 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2_MASK 0xff0000
12344 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE2__SHIFT 0x10
12345 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3_MASK 0xff000000
12346 #define MC_IO_DEBUG_DQB2L_CLKSEL_D0__VALUE3__SHIFT 0x18
12347 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0_MASK 0xff
12348 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE0__SHIFT 0x0
12349 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1_MASK 0xff00
12350 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE1__SHIFT 0x8
12351 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2_MASK 0xff0000
12352 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE2__SHIFT 0x10
12353 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3_MASK 0xff000000
12354 #define MC_IO_DEBUG_DQB2H_CLKSEL_D0__VALUE3__SHIFT 0x18
12355 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0_MASK 0xff
12356 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE0__SHIFT 0x0
12357 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1_MASK 0xff00
12358 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE1__SHIFT 0x8
12359 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2_MASK 0xff0000
12360 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE2__SHIFT 0x10
12361 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3_MASK 0xff000000
12362 #define MC_IO_DEBUG_DQB3L_CLKSEL_D0__VALUE3__SHIFT 0x18
12363 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0_MASK 0xff
12364 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE0__SHIFT 0x0
12365 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1_MASK 0xff00
12366 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE1__SHIFT 0x8
12367 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2_MASK 0xff0000
12368 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE2__SHIFT 0x10
12369 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3_MASK 0xff000000
12370 #define MC_IO_DEBUG_DQB3H_CLKSEL_D0__VALUE3__SHIFT 0x18
12371 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0_MASK 0xff
12372 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE0__SHIFT 0x0
12373 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1_MASK 0xff00
12374 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE1__SHIFT 0x8
12375 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2_MASK 0xff0000
12376 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE2__SHIFT 0x10
12377 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3_MASK 0xff000000
12378 #define MC_IO_DEBUG_DBI_CLKSEL_D0__VALUE3__SHIFT 0x18
12379 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0_MASK 0xff
12380 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE0__SHIFT 0x0
12381 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1_MASK 0xff00
12382 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE1__SHIFT 0x8
12383 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2_MASK 0xff0000
12384 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE2__SHIFT 0x10
12385 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3_MASK 0xff000000
12386 #define MC_IO_DEBUG_EDC_CLKSEL_D0__VALUE3__SHIFT 0x18
12387 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0_MASK 0xff
12388 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE0__SHIFT 0x0
12389 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1_MASK 0xff00
12390 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE1__SHIFT 0x8
12391 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2_MASK 0xff0000
12392 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE2__SHIFT 0x10
12393 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3_MASK 0xff000000
12394 #define MC_IO_DEBUG_WCK_CLKSEL_D0__VALUE3__SHIFT 0x18
12395 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0_MASK 0xff
12396 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE0__SHIFT 0x0
12397 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1_MASK 0xff00
12398 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE1__SHIFT 0x8
12399 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2_MASK 0xff0000
12400 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE2__SHIFT 0x10
12401 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3_MASK 0xff000000
12402 #define MC_IO_DEBUG_CK_CLKSEL_D0__VALUE3__SHIFT 0x18
12403 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0_MASK 0xff
12404 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE0__SHIFT 0x0
12405 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1_MASK 0xff00
12406 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE1__SHIFT 0x8
12407 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2_MASK 0xff0000
12408 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE2__SHIFT 0x10
12409 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3_MASK 0xff000000
12410 #define MC_IO_DEBUG_ADDRL_CLKSEL_D0__VALUE3__SHIFT 0x18
12411 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0_MASK 0xff
12412 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE0__SHIFT 0x0
12413 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1_MASK 0xff00
12414 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE1__SHIFT 0x8
12415 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2_MASK 0xff0000
12416 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE2__SHIFT 0x10
12417 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3_MASK 0xff000000
12418 #define MC_IO_DEBUG_ADDRH_CLKSEL_D0__VALUE3__SHIFT 0x18
12419 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0_MASK 0xff
12420 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE0__SHIFT 0x0
12421 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1_MASK 0xff00
12422 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE1__SHIFT 0x8
12423 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2_MASK 0xff0000
12424 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE2__SHIFT 0x10
12425 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3_MASK 0xff000000
12426 #define MC_IO_DEBUG_ACMD_CLKSEL_D0__VALUE3__SHIFT 0x18
12427 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0_MASK 0xff
12428 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE0__SHIFT 0x0
12429 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1_MASK 0xff00
12430 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE1__SHIFT 0x8
12431 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2_MASK 0xff0000
12432 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE2__SHIFT 0x10
12433 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3_MASK 0xff000000
12434 #define MC_IO_DEBUG_CMD_CLKSEL_D0__VALUE3__SHIFT 0x18
12435 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0_MASK 0xff
12436 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE0__SHIFT 0x0
12437 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1_MASK 0xff00
12438 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE1__SHIFT 0x8
12439 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2_MASK 0xff0000
12440 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE2__SHIFT 0x10
12441 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3_MASK 0xff000000
12442 #define MC_IO_DEBUG_DQB0L_CLKSEL_D1__VALUE3__SHIFT 0x18
12443 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0_MASK 0xff
12444 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE0__SHIFT 0x0
12445 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1_MASK 0xff00
12446 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE1__SHIFT 0x8
12447 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2_MASK 0xff0000
12448 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE2__SHIFT 0x10
12449 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3_MASK 0xff000000
12450 #define MC_IO_DEBUG_DQB0H_CLKSEL_D1__VALUE3__SHIFT 0x18
12451 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0_MASK 0xff
12452 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE0__SHIFT 0x0
12453 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1_MASK 0xff00
12454 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE1__SHIFT 0x8
12455 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2_MASK 0xff0000
12456 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE2__SHIFT 0x10
12457 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3_MASK 0xff000000
12458 #define MC_IO_DEBUG_DQB1L_CLKSEL_D1__VALUE3__SHIFT 0x18
12459 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0_MASK 0xff
12460 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE0__SHIFT 0x0
12461 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1_MASK 0xff00
12462 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE1__SHIFT 0x8
12463 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2_MASK 0xff0000
12464 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE2__SHIFT 0x10
12465 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3_MASK 0xff000000
12466 #define MC_IO_DEBUG_DQB1H_CLKSEL_D1__VALUE3__SHIFT 0x18
12467 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0_MASK 0xff
12468 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE0__SHIFT 0x0
12469 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1_MASK 0xff00
12470 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE1__SHIFT 0x8
12471 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2_MASK 0xff0000
12472 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE2__SHIFT 0x10
12473 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3_MASK 0xff000000
12474 #define MC_IO_DEBUG_DQB2L_CLKSEL_D1__VALUE3__SHIFT 0x18
12475 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0_MASK 0xff
12476 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE0__SHIFT 0x0
12477 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1_MASK 0xff00
12478 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE1__SHIFT 0x8
12479 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2_MASK 0xff0000
12480 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE2__SHIFT 0x10
12481 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3_MASK 0xff000000
12482 #define MC_IO_DEBUG_DQB2H_CLKSEL_D1__VALUE3__SHIFT 0x18
12483 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0_MASK 0xff
12484 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE0__SHIFT 0x0
12485 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1_MASK 0xff00
12486 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE1__SHIFT 0x8
12487 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2_MASK 0xff0000
12488 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE2__SHIFT 0x10
12489 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3_MASK 0xff000000
12490 #define MC_IO_DEBUG_DQB3L_CLKSEL_D1__VALUE3__SHIFT 0x18
12491 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0_MASK 0xff
12492 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE0__SHIFT 0x0
12493 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1_MASK 0xff00
12494 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE1__SHIFT 0x8
12495 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2_MASK 0xff0000
12496 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE2__SHIFT 0x10
12497 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3_MASK 0xff000000
12498 #define MC_IO_DEBUG_DQB3H_CLKSEL_D1__VALUE3__SHIFT 0x18
12499 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0_MASK 0xff
12500 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE0__SHIFT 0x0
12501 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1_MASK 0xff00
12502 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE1__SHIFT 0x8
12503 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2_MASK 0xff0000
12504 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE2__SHIFT 0x10
12505 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3_MASK 0xff000000
12506 #define MC_IO_DEBUG_DBI_CLKSEL_D1__VALUE3__SHIFT 0x18
12507 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0_MASK 0xff
12508 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE0__SHIFT 0x0
12509 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1_MASK 0xff00
12510 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE1__SHIFT 0x8
12511 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2_MASK 0xff0000
12512 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE2__SHIFT 0x10
12513 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3_MASK 0xff000000
12514 #define MC_IO_DEBUG_EDC_CLKSEL_D1__VALUE3__SHIFT 0x18
12515 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0_MASK 0xff
12516 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE0__SHIFT 0x0
12517 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1_MASK 0xff00
12518 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE1__SHIFT 0x8
12519 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2_MASK 0xff0000
12520 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE2__SHIFT 0x10
12521 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3_MASK 0xff000000
12522 #define MC_IO_DEBUG_WCK_CLKSEL_D1__VALUE3__SHIFT 0x18
12523 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0_MASK 0xff
12524 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE0__SHIFT 0x0
12525 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1_MASK 0xff00
12526 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE1__SHIFT 0x8
12527 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2_MASK 0xff0000
12528 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE2__SHIFT 0x10
12529 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3_MASK 0xff000000
12530 #define MC_IO_DEBUG_CK_CLKSEL_D1__VALUE3__SHIFT 0x18
12531 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0_MASK 0xff
12532 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE0__SHIFT 0x0
12533 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1_MASK 0xff00
12534 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE1__SHIFT 0x8
12535 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2_MASK 0xff0000
12536 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE2__SHIFT 0x10
12537 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3_MASK 0xff000000
12538 #define MC_IO_DEBUG_ADDRL_CLKSEL_D1__VALUE3__SHIFT 0x18
12539 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0_MASK 0xff
12540 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE0__SHIFT 0x0
12541 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1_MASK 0xff00
12542 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE1__SHIFT 0x8
12543 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2_MASK 0xff0000
12544 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE2__SHIFT 0x10
12545 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3_MASK 0xff000000
12546 #define MC_IO_DEBUG_ADDRH_CLKSEL_D1__VALUE3__SHIFT 0x18
12547 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0_MASK 0xff
12548 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE0__SHIFT 0x0
12549 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1_MASK 0xff00
12550 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE1__SHIFT 0x8
12551 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2_MASK 0xff0000
12552 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE2__SHIFT 0x10
12553 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3_MASK 0xff000000
12554 #define MC_IO_DEBUG_ACMD_CLKSEL_D1__VALUE3__SHIFT 0x18
12555 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0_MASK 0xff
12556 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE0__SHIFT 0x0
12557 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1_MASK 0xff00
12558 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE1__SHIFT 0x8
12559 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2_MASK 0xff0000
12560 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE2__SHIFT 0x10
12561 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3_MASK 0xff000000
12562 #define MC_IO_DEBUG_CMD_CLKSEL_D1__VALUE3__SHIFT 0x18
12563 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0_MASK 0xff
12564 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE0__SHIFT 0x0
12565 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1_MASK 0xff00
12566 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE1__SHIFT 0x8
12567 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2_MASK 0xff0000
12568 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE2__SHIFT 0x10
12569 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3_MASK 0xff000000
12570 #define MC_IO_DEBUG_DQB0L_OFSCAL_D0__VALUE3__SHIFT 0x18
12571 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0_MASK 0xff
12572 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE0__SHIFT 0x0
12573 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1_MASK 0xff00
12574 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE1__SHIFT 0x8
12575 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2_MASK 0xff0000
12576 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE2__SHIFT 0x10
12577 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3_MASK 0xff000000
12578 #define MC_IO_DEBUG_DQB0H_OFSCAL_D0__VALUE3__SHIFT 0x18
12579 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0_MASK 0xff
12580 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE0__SHIFT 0x0
12581 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1_MASK 0xff00
12582 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE1__SHIFT 0x8
12583 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2_MASK 0xff0000
12584 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE2__SHIFT 0x10
12585 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3_MASK 0xff000000
12586 #define MC_IO_DEBUG_DQB1L_OFSCAL_D0__VALUE3__SHIFT 0x18
12587 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0_MASK 0xff
12588 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE0__SHIFT 0x0
12589 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1_MASK 0xff00
12590 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE1__SHIFT 0x8
12591 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2_MASK 0xff0000
12592 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE2__SHIFT 0x10
12593 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3_MASK 0xff000000
12594 #define MC_IO_DEBUG_DQB1H_OFSCAL_D0__VALUE3__SHIFT 0x18
12595 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0_MASK 0xff
12596 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE0__SHIFT 0x0
12597 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1_MASK 0xff00
12598 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE1__SHIFT 0x8
12599 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2_MASK 0xff0000
12600 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE2__SHIFT 0x10
12601 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3_MASK 0xff000000
12602 #define MC_IO_DEBUG_DQB2L_OFSCAL_D0__VALUE3__SHIFT 0x18
12603 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0_MASK 0xff
12604 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE0__SHIFT 0x0
12605 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1_MASK 0xff00
12606 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE1__SHIFT 0x8
12607 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2_MASK 0xff0000
12608 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE2__SHIFT 0x10
12609 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3_MASK 0xff000000
12610 #define MC_IO_DEBUG_DQB2H_OFSCAL_D0__VALUE3__SHIFT 0x18
12611 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0_MASK 0xff
12612 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE0__SHIFT 0x0
12613 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1_MASK 0xff00
12614 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE1__SHIFT 0x8
12615 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2_MASK 0xff0000
12616 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE2__SHIFT 0x10
12617 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3_MASK 0xff000000
12618 #define MC_IO_DEBUG_DQB3L_OFSCAL_D0__VALUE3__SHIFT 0x18
12619 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0_MASK 0xff
12620 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE0__SHIFT 0x0
12621 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1_MASK 0xff00
12622 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE1__SHIFT 0x8
12623 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2_MASK 0xff0000
12624 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE2__SHIFT 0x10
12625 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3_MASK 0xff000000
12626 #define MC_IO_DEBUG_DQB3H_OFSCAL_D0__VALUE3__SHIFT 0x18
12627 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0_MASK 0xff
12628 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE0__SHIFT 0x0
12629 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1_MASK 0xff00
12630 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE1__SHIFT 0x8
12631 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2_MASK 0xff0000
12632 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE2__SHIFT 0x10
12633 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3_MASK 0xff000000
12634 #define MC_IO_DEBUG_DBI_OFSCAL_D0__VALUE3__SHIFT 0x18
12635 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0_MASK 0xff
12636 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE0__SHIFT 0x0
12637 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1_MASK 0xff00
12638 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE1__SHIFT 0x8
12639 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2_MASK 0xff0000
12640 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE2__SHIFT 0x10
12641 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3_MASK 0xff000000
12642 #define MC_IO_DEBUG_EDC_OFSCAL_D0__VALUE3__SHIFT 0x18
12643 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0_MASK 0xff
12644 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE0__SHIFT 0x0
12645 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1_MASK 0xff00
12646 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE1__SHIFT 0x8
12647 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2_MASK 0xff0000
12648 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE2__SHIFT 0x10
12649 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3_MASK 0xff000000
12650 #define MC_IO_DEBUG_WCK_OFSCAL_D0__VALUE3__SHIFT 0x18
12651 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0_MASK 0xff
12652 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
12653 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1_MASK 0xff00
12654 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
12655 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
12656 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
12657 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
12658 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
12659 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0_MASK 0xff
12660 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
12661 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1_MASK 0xff00
12662 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
12663 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
12664 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
12665 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
12666 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
12667 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0_MASK 0xff
12668 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
12669 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
12670 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
12671 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
12672 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
12673 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
12674 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
12675 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0_MASK 0xff
12676 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE0__SHIFT 0x0
12677 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1_MASK 0xff00
12678 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE1__SHIFT 0x8
12679 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2_MASK 0xff0000
12680 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE2__SHIFT 0x10
12681 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3_MASK 0xff000000
12682 #define MC_IO_DEBUG_ACMD_OFSCAL_D0__VALUE3__SHIFT 0x18
12683 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0_MASK 0xff
12684 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE0__SHIFT 0x0
12685 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1_MASK 0xff00
12686 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE1__SHIFT 0x8
12687 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2_MASK 0xff0000
12688 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE2__SHIFT 0x10
12689 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3_MASK 0xff000000
12690 #define MC_IO_DEBUG_CMD_OFSCAL_D0__VALUE3__SHIFT 0x18
12691 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0_MASK 0xff
12692 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE0__SHIFT 0x0
12693 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1_MASK 0xff00
12694 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE1__SHIFT 0x8
12695 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2_MASK 0xff0000
12696 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE2__SHIFT 0x10
12697 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3_MASK 0xff000000
12698 #define MC_IO_DEBUG_DQB0L_OFSCAL_D1__VALUE3__SHIFT 0x18
12699 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0_MASK 0xff
12700 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE0__SHIFT 0x0
12701 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1_MASK 0xff00
12702 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE1__SHIFT 0x8
12703 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2_MASK 0xff0000
12704 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE2__SHIFT 0x10
12705 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3_MASK 0xff000000
12706 #define MC_IO_DEBUG_DQB0H_OFSCAL_D1__VALUE3__SHIFT 0x18
12707 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0_MASK 0xff
12708 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE0__SHIFT 0x0
12709 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1_MASK 0xff00
12710 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE1__SHIFT 0x8
12711 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2_MASK 0xff0000
12712 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE2__SHIFT 0x10
12713 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3_MASK 0xff000000
12714 #define MC_IO_DEBUG_DQB1L_OFSCAL_D1__VALUE3__SHIFT 0x18
12715 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0_MASK 0xff
12716 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE0__SHIFT 0x0
12717 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1_MASK 0xff00
12718 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE1__SHIFT 0x8
12719 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2_MASK 0xff0000
12720 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE2__SHIFT 0x10
12721 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3_MASK 0xff000000
12722 #define MC_IO_DEBUG_DQB1H_OFSCAL_D1__VALUE3__SHIFT 0x18
12723 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0_MASK 0xff
12724 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE0__SHIFT 0x0
12725 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1_MASK 0xff00
12726 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE1__SHIFT 0x8
12727 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2_MASK 0xff0000
12728 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE2__SHIFT 0x10
12729 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3_MASK 0xff000000
12730 #define MC_IO_DEBUG_DQB2L_OFSCAL_D1__VALUE3__SHIFT 0x18
12731 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0_MASK 0xff
12732 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE0__SHIFT 0x0
12733 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1_MASK 0xff00
12734 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE1__SHIFT 0x8
12735 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2_MASK 0xff0000
12736 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE2__SHIFT 0x10
12737 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3_MASK 0xff000000
12738 #define MC_IO_DEBUG_DQB2H_OFSCAL_D1__VALUE3__SHIFT 0x18
12739 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0_MASK 0xff
12740 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE0__SHIFT 0x0
12741 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1_MASK 0xff00
12742 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE1__SHIFT 0x8
12743 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2_MASK 0xff0000
12744 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE2__SHIFT 0x10
12745 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3_MASK 0xff000000
12746 #define MC_IO_DEBUG_DQB3L_OFSCAL_D1__VALUE3__SHIFT 0x18
12747 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0_MASK 0xff
12748 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE0__SHIFT 0x0
12749 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1_MASK 0xff00
12750 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE1__SHIFT 0x8
12751 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2_MASK 0xff0000
12752 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE2__SHIFT 0x10
12753 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3_MASK 0xff000000
12754 #define MC_IO_DEBUG_DQB3H_OFSCAL_D1__VALUE3__SHIFT 0x18
12755 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0_MASK 0xff
12756 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE0__SHIFT 0x0
12757 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1_MASK 0xff00
12758 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE1__SHIFT 0x8
12759 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2_MASK 0xff0000
12760 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE2__SHIFT 0x10
12761 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3_MASK 0xff000000
12762 #define MC_IO_DEBUG_DBI_OFSCAL_D1__VALUE3__SHIFT 0x18
12763 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0_MASK 0xff
12764 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE0__SHIFT 0x0
12765 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1_MASK 0xff00
12766 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE1__SHIFT 0x8
12767 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2_MASK 0xff0000
12768 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE2__SHIFT 0x10
12769 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3_MASK 0xff000000
12770 #define MC_IO_DEBUG_EDC_OFSCAL_D1__VALUE3__SHIFT 0x18
12771 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0_MASK 0xff
12772 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE0__SHIFT 0x0
12773 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1_MASK 0xff00
12774 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE1__SHIFT 0x8
12775 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2_MASK 0xff0000
12776 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE2__SHIFT 0x10
12777 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3_MASK 0xff000000
12778 #define MC_IO_DEBUG_WCK_OFSCAL_D1__VALUE3__SHIFT 0x18
12779 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0_MASK 0xff
12780 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
12781 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1_MASK 0xff00
12782 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
12783 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
12784 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
12785 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
12786 #define MC_IO_DEBUG_EDC_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
12787 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0_MASK 0xff
12788 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
12789 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1_MASK 0xff00
12790 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
12791 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
12792 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
12793 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
12794 #define MC_IO_DEBUG_EDC_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
12795 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0_MASK 0xff
12796 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
12797 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
12798 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
12799 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
12800 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
12801 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
12802 #define MC_IO_DEBUG_EDC_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
12803 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0_MASK 0xff
12804 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE0__SHIFT 0x0
12805 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1_MASK 0xff00
12806 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE1__SHIFT 0x8
12807 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2_MASK 0xff0000
12808 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE2__SHIFT 0x10
12809 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3_MASK 0xff000000
12810 #define MC_IO_DEBUG_ACMD_OFSCAL_D1__VALUE3__SHIFT 0x18
12811 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0_MASK 0xff
12812 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE0__SHIFT 0x0
12813 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1_MASK 0xff00
12814 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE1__SHIFT 0x8
12815 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2_MASK 0xff0000
12816 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE2__SHIFT 0x10
12817 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3_MASK 0xff000000
12818 #define MC_IO_DEBUG_CMD_OFSCAL_D1__VALUE3__SHIFT 0x18
12819 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0_MASK 0xff
12820 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE0__SHIFT 0x0
12821 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1_MASK 0xff00
12822 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE1__SHIFT 0x8
12823 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2_MASK 0xff0000
12824 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE2__SHIFT 0x10
12825 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3_MASK 0xff000000
12826 #define MC_IO_DEBUG_DQB0L_RXPHASE_D0__VALUE3__SHIFT 0x18
12827 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0_MASK 0xff
12828 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE0__SHIFT 0x0
12829 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1_MASK 0xff00
12830 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE1__SHIFT 0x8
12831 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2_MASK 0xff0000
12832 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE2__SHIFT 0x10
12833 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3_MASK 0xff000000
12834 #define MC_IO_DEBUG_DQB0H_RXPHASE_D0__VALUE3__SHIFT 0x18
12835 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0_MASK 0xff
12836 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE0__SHIFT 0x0
12837 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1_MASK 0xff00
12838 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE1__SHIFT 0x8
12839 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2_MASK 0xff0000
12840 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE2__SHIFT 0x10
12841 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3_MASK 0xff000000
12842 #define MC_IO_DEBUG_DQB1L_RXPHASE_D0__VALUE3__SHIFT 0x18
12843 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0_MASK 0xff
12844 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE0__SHIFT 0x0
12845 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1_MASK 0xff00
12846 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE1__SHIFT 0x8
12847 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2_MASK 0xff0000
12848 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE2__SHIFT 0x10
12849 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3_MASK 0xff000000
12850 #define MC_IO_DEBUG_DQB1H_RXPHASE_D0__VALUE3__SHIFT 0x18
12851 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0_MASK 0xff
12852 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE0__SHIFT 0x0
12853 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1_MASK 0xff00
12854 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE1__SHIFT 0x8
12855 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2_MASK 0xff0000
12856 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE2__SHIFT 0x10
12857 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3_MASK 0xff000000
12858 #define MC_IO_DEBUG_DQB2L_RXPHASE_D0__VALUE3__SHIFT 0x18
12859 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0_MASK 0xff
12860 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE0__SHIFT 0x0
12861 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1_MASK 0xff00
12862 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE1__SHIFT 0x8
12863 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2_MASK 0xff0000
12864 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE2__SHIFT 0x10
12865 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3_MASK 0xff000000
12866 #define MC_IO_DEBUG_DQB2H_RXPHASE_D0__VALUE3__SHIFT 0x18
12867 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0_MASK 0xff
12868 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE0__SHIFT 0x0
12869 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1_MASK 0xff00
12870 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE1__SHIFT 0x8
12871 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2_MASK 0xff0000
12872 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE2__SHIFT 0x10
12873 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3_MASK 0xff000000
12874 #define MC_IO_DEBUG_DQB3L_RXPHASE_D0__VALUE3__SHIFT 0x18
12875 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0_MASK 0xff
12876 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE0__SHIFT 0x0
12877 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1_MASK 0xff00
12878 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE1__SHIFT 0x8
12879 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2_MASK 0xff0000
12880 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE2__SHIFT 0x10
12881 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3_MASK 0xff000000
12882 #define MC_IO_DEBUG_DQB3H_RXPHASE_D0__VALUE3__SHIFT 0x18
12883 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0_MASK 0xff
12884 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE0__SHIFT 0x0
12885 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1_MASK 0xff00
12886 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE1__SHIFT 0x8
12887 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2_MASK 0xff0000
12888 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE2__SHIFT 0x10
12889 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3_MASK 0xff000000
12890 #define MC_IO_DEBUG_DBI_RXPHASE_D0__VALUE3__SHIFT 0x18
12891 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0_MASK 0xff
12892 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE0__SHIFT 0x0
12893 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1_MASK 0xff00
12894 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE1__SHIFT 0x8
12895 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2_MASK 0xff0000
12896 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE2__SHIFT 0x10
12897 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3_MASK 0xff000000
12898 #define MC_IO_DEBUG_EDC_RXPHASE_D0__VALUE3__SHIFT 0x18
12899 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0_MASK 0xff
12900 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE0__SHIFT 0x0
12901 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1_MASK 0xff00
12902 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE1__SHIFT 0x8
12903 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2_MASK 0xff0000
12904 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE2__SHIFT 0x10
12905 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3_MASK 0xff000000
12906 #define MC_IO_DEBUG_WCK_RXPHASE_D0__VALUE3__SHIFT 0x18
12907 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0_MASK 0xff
12908 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE0__SHIFT 0x0
12909 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1_MASK 0xff00
12910 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE1__SHIFT 0x8
12911 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2_MASK 0xff0000
12912 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE2__SHIFT 0x10
12913 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3_MASK 0xff000000
12914 #define MC_IO_DEBUG_CK_RXPHASE_D0__VALUE3__SHIFT 0x18
12915 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0_MASK 0xff
12916 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE0__SHIFT 0x0
12917 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1_MASK 0xff00
12918 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE1__SHIFT 0x8
12919 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2_MASK 0xff0000
12920 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE2__SHIFT 0x10
12921 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3_MASK 0xff000000
12922 #define MC_IO_DEBUG_ADDRL_RXPHASE_D0__VALUE3__SHIFT 0x18
12923 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0_MASK 0xff
12924 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE0__SHIFT 0x0
12925 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1_MASK 0xff00
12926 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE1__SHIFT 0x8
12927 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2_MASK 0xff0000
12928 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE2__SHIFT 0x10
12929 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3_MASK 0xff000000
12930 #define MC_IO_DEBUG_ADDRH_RXPHASE_D0__VALUE3__SHIFT 0x18
12931 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0_MASK 0xff
12932 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE0__SHIFT 0x0
12933 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1_MASK 0xff00
12934 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE1__SHIFT 0x8
12935 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2_MASK 0xff0000
12936 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE2__SHIFT 0x10
12937 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3_MASK 0xff000000
12938 #define MC_IO_DEBUG_ACMD_RXPHASE_D0__VALUE3__SHIFT 0x18
12939 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0_MASK 0xff
12940 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE0__SHIFT 0x0
12941 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1_MASK 0xff00
12942 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE1__SHIFT 0x8
12943 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2_MASK 0xff0000
12944 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE2__SHIFT 0x10
12945 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3_MASK 0xff000000
12946 #define MC_IO_DEBUG_CMD_RXPHASE_D0__VALUE3__SHIFT 0x18
12947 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0_MASK 0xff
12948 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE0__SHIFT 0x0
12949 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1_MASK 0xff00
12950 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE1__SHIFT 0x8
12951 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2_MASK 0xff0000
12952 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE2__SHIFT 0x10
12953 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3_MASK 0xff000000
12954 #define MC_IO_DEBUG_DQB0L_RXPHASE_D1__VALUE3__SHIFT 0x18
12955 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0_MASK 0xff
12956 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE0__SHIFT 0x0
12957 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1_MASK 0xff00
12958 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE1__SHIFT 0x8
12959 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2_MASK 0xff0000
12960 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE2__SHIFT 0x10
12961 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3_MASK 0xff000000
12962 #define MC_IO_DEBUG_DQB0H_RXPHASE_D1__VALUE3__SHIFT 0x18
12963 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0_MASK 0xff
12964 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE0__SHIFT 0x0
12965 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1_MASK 0xff00
12966 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE1__SHIFT 0x8
12967 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2_MASK 0xff0000
12968 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE2__SHIFT 0x10
12969 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3_MASK 0xff000000
12970 #define MC_IO_DEBUG_DQB1L_RXPHASE_D1__VALUE3__SHIFT 0x18
12971 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0_MASK 0xff
12972 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE0__SHIFT 0x0
12973 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1_MASK 0xff00
12974 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE1__SHIFT 0x8
12975 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2_MASK 0xff0000
12976 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE2__SHIFT 0x10
12977 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3_MASK 0xff000000
12978 #define MC_IO_DEBUG_DQB1H_RXPHASE_D1__VALUE3__SHIFT 0x18
12979 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0_MASK 0xff
12980 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE0__SHIFT 0x0
12981 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1_MASK 0xff00
12982 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE1__SHIFT 0x8
12983 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2_MASK 0xff0000
12984 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE2__SHIFT 0x10
12985 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3_MASK 0xff000000
12986 #define MC_IO_DEBUG_DQB2L_RXPHASE_D1__VALUE3__SHIFT 0x18
12987 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0_MASK 0xff
12988 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE0__SHIFT 0x0
12989 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1_MASK 0xff00
12990 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE1__SHIFT 0x8
12991 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2_MASK 0xff0000
12992 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE2__SHIFT 0x10
12993 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3_MASK 0xff000000
12994 #define MC_IO_DEBUG_DQB2H_RXPHASE_D1__VALUE3__SHIFT 0x18
12995 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0_MASK 0xff
12996 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE0__SHIFT 0x0
12997 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1_MASK 0xff00
12998 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE1__SHIFT 0x8
12999 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2_MASK 0xff0000
13000 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE2__SHIFT 0x10
13001 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3_MASK 0xff000000
13002 #define MC_IO_DEBUG_DQB3L_RXPHASE_D1__VALUE3__SHIFT 0x18
13003 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0_MASK 0xff
13004 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE0__SHIFT 0x0
13005 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1_MASK 0xff00
13006 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE1__SHIFT 0x8
13007 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2_MASK 0xff0000
13008 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE2__SHIFT 0x10
13009 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3_MASK 0xff000000
13010 #define MC_IO_DEBUG_DQB3H_RXPHASE_D1__VALUE3__SHIFT 0x18
13011 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0_MASK 0xff
13012 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE0__SHIFT 0x0
13013 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1_MASK 0xff00
13014 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE1__SHIFT 0x8
13015 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2_MASK 0xff0000
13016 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE2__SHIFT 0x10
13017 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3_MASK 0xff000000
13018 #define MC_IO_DEBUG_DBI_RXPHASE_D1__VALUE3__SHIFT 0x18
13019 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0_MASK 0xff
13020 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE0__SHIFT 0x0
13021 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1_MASK 0xff00
13022 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE1__SHIFT 0x8
13023 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2_MASK 0xff0000
13024 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE2__SHIFT 0x10
13025 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3_MASK 0xff000000
13026 #define MC_IO_DEBUG_EDC_RXPHASE_D1__VALUE3__SHIFT 0x18
13027 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0_MASK 0xff
13028 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE0__SHIFT 0x0
13029 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1_MASK 0xff00
13030 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE1__SHIFT 0x8
13031 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2_MASK 0xff0000
13032 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE2__SHIFT 0x10
13033 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3_MASK 0xff000000
13034 #define MC_IO_DEBUG_WCK_RXPHASE_D1__VALUE3__SHIFT 0x18
13035 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0_MASK 0xff
13036 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE0__SHIFT 0x0
13037 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1_MASK 0xff00
13038 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE1__SHIFT 0x8
13039 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2_MASK 0xff0000
13040 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE2__SHIFT 0x10
13041 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3_MASK 0xff000000
13042 #define MC_IO_DEBUG_CK_RXPHASE_D1__VALUE3__SHIFT 0x18
13043 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0_MASK 0xff
13044 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE0__SHIFT 0x0
13045 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1_MASK 0xff00
13046 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE1__SHIFT 0x8
13047 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2_MASK 0xff0000
13048 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE2__SHIFT 0x10
13049 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3_MASK 0xff000000
13050 #define MC_IO_DEBUG_ADDRL_RXPHASE_D1__VALUE3__SHIFT 0x18
13051 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0_MASK 0xff
13052 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE0__SHIFT 0x0
13053 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1_MASK 0xff00
13054 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE1__SHIFT 0x8
13055 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2_MASK 0xff0000
13056 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE2__SHIFT 0x10
13057 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3_MASK 0xff000000
13058 #define MC_IO_DEBUG_ADDRH_RXPHASE_D1__VALUE3__SHIFT 0x18
13059 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0_MASK 0xff
13060 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE0__SHIFT 0x0
13061 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1_MASK 0xff00
13062 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE1__SHIFT 0x8
13063 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2_MASK 0xff0000
13064 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE2__SHIFT 0x10
13065 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3_MASK 0xff000000
13066 #define MC_IO_DEBUG_ACMD_RXPHASE_D1__VALUE3__SHIFT 0x18
13067 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0_MASK 0xff
13068 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE0__SHIFT 0x0
13069 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1_MASK 0xff00
13070 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE1__SHIFT 0x8
13071 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2_MASK 0xff0000
13072 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE2__SHIFT 0x10
13073 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3_MASK 0xff000000
13074 #define MC_IO_DEBUG_CMD_RXPHASE_D1__VALUE3__SHIFT 0x18
13075 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0_MASK 0xff
13076 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE0__SHIFT 0x0
13077 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1_MASK 0xff00
13078 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE1__SHIFT 0x8
13079 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2_MASK 0xff0000
13080 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE2__SHIFT 0x10
13081 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3_MASK 0xff000000
13082 #define MC_IO_DEBUG_DQB0L_TXPHASE_D0__VALUE3__SHIFT 0x18
13083 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0_MASK 0xff
13084 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE0__SHIFT 0x0
13085 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1_MASK 0xff00
13086 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE1__SHIFT 0x8
13087 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2_MASK 0xff0000
13088 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE2__SHIFT 0x10
13089 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3_MASK 0xff000000
13090 #define MC_IO_DEBUG_DQB0H_TXPHASE_D0__VALUE3__SHIFT 0x18
13091 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0_MASK 0xff
13092 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE0__SHIFT 0x0
13093 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1_MASK 0xff00
13094 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE1__SHIFT 0x8
13095 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2_MASK 0xff0000
13096 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE2__SHIFT 0x10
13097 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3_MASK 0xff000000
13098 #define MC_IO_DEBUG_DQB1L_TXPHASE_D0__VALUE3__SHIFT 0x18
13099 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0_MASK 0xff
13100 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE0__SHIFT 0x0
13101 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1_MASK 0xff00
13102 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE1__SHIFT 0x8
13103 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2_MASK 0xff0000
13104 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE2__SHIFT 0x10
13105 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3_MASK 0xff000000
13106 #define MC_IO_DEBUG_DQB1H_TXPHASE_D0__VALUE3__SHIFT 0x18
13107 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0_MASK 0xff
13108 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE0__SHIFT 0x0
13109 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1_MASK 0xff00
13110 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE1__SHIFT 0x8
13111 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2_MASK 0xff0000
13112 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE2__SHIFT 0x10
13113 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3_MASK 0xff000000
13114 #define MC_IO_DEBUG_DQB2L_TXPHASE_D0__VALUE3__SHIFT 0x18
13115 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0_MASK 0xff
13116 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE0__SHIFT 0x0
13117 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1_MASK 0xff00
13118 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE1__SHIFT 0x8
13119 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2_MASK 0xff0000
13120 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE2__SHIFT 0x10
13121 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3_MASK 0xff000000
13122 #define MC_IO_DEBUG_DQB2H_TXPHASE_D0__VALUE3__SHIFT 0x18
13123 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0_MASK 0xff
13124 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE0__SHIFT 0x0
13125 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1_MASK 0xff00
13126 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE1__SHIFT 0x8
13127 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2_MASK 0xff0000
13128 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE2__SHIFT 0x10
13129 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3_MASK 0xff000000
13130 #define MC_IO_DEBUG_DQB3L_TXPHASE_D0__VALUE3__SHIFT 0x18
13131 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0_MASK 0xff
13132 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE0__SHIFT 0x0
13133 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1_MASK 0xff00
13134 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE1__SHIFT 0x8
13135 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2_MASK 0xff0000
13136 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE2__SHIFT 0x10
13137 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3_MASK 0xff000000
13138 #define MC_IO_DEBUG_DQB3H_TXPHASE_D0__VALUE3__SHIFT 0x18
13139 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0_MASK 0xff
13140 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE0__SHIFT 0x0
13141 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1_MASK 0xff00
13142 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE1__SHIFT 0x8
13143 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2_MASK 0xff0000
13144 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE2__SHIFT 0x10
13145 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3_MASK 0xff000000
13146 #define MC_IO_DEBUG_DBI_TXPHASE_D0__VALUE3__SHIFT 0x18
13147 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0_MASK 0xff
13148 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE0__SHIFT 0x0
13149 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1_MASK 0xff00
13150 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE1__SHIFT 0x8
13151 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2_MASK 0xff0000
13152 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE2__SHIFT 0x10
13153 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3_MASK 0xff000000
13154 #define MC_IO_DEBUG_EDC_TXPHASE_D0__VALUE3__SHIFT 0x18
13155 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0_MASK 0xff
13156 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE0__SHIFT 0x0
13157 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1_MASK 0xff00
13158 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE1__SHIFT 0x8
13159 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2_MASK 0xff0000
13160 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE2__SHIFT 0x10
13161 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3_MASK 0xff000000
13162 #define MC_IO_DEBUG_WCK_TXPHASE_D0__VALUE3__SHIFT 0x18
13163 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0_MASK 0xff
13164 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE0__SHIFT 0x0
13165 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1_MASK 0xff00
13166 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE1__SHIFT 0x8
13167 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2_MASK 0xff0000
13168 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE2__SHIFT 0x10
13169 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3_MASK 0xff000000
13170 #define MC_IO_DEBUG_CK_TXPHASE_D0__VALUE3__SHIFT 0x18
13171 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0_MASK 0xff
13172 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE0__SHIFT 0x0
13173 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1_MASK 0xff00
13174 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE1__SHIFT 0x8
13175 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2_MASK 0xff0000
13176 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE2__SHIFT 0x10
13177 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3_MASK 0xff000000
13178 #define MC_IO_DEBUG_ADDRL_TXPHASE_D0__VALUE3__SHIFT 0x18
13179 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0_MASK 0xff
13180 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE0__SHIFT 0x0
13181 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1_MASK 0xff00
13182 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE1__SHIFT 0x8
13183 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2_MASK 0xff0000
13184 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE2__SHIFT 0x10
13185 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3_MASK 0xff000000
13186 #define MC_IO_DEBUG_ADDRH_TXPHASE_D0__VALUE3__SHIFT 0x18
13187 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0_MASK 0xff
13188 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE0__SHIFT 0x0
13189 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1_MASK 0xff00
13190 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE1__SHIFT 0x8
13191 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2_MASK 0xff0000
13192 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE2__SHIFT 0x10
13193 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3_MASK 0xff000000
13194 #define MC_IO_DEBUG_ACMD_TXPHASE_D0__VALUE3__SHIFT 0x18
13195 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0_MASK 0xff
13196 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE0__SHIFT 0x0
13197 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1_MASK 0xff00
13198 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE1__SHIFT 0x8
13199 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2_MASK 0xff0000
13200 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE2__SHIFT 0x10
13201 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3_MASK 0xff000000
13202 #define MC_IO_DEBUG_CMD_TXPHASE_D0__VALUE3__SHIFT 0x18
13203 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0_MASK 0xff
13204 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE0__SHIFT 0x0
13205 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1_MASK 0xff00
13206 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE1__SHIFT 0x8
13207 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2_MASK 0xff0000
13208 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE2__SHIFT 0x10
13209 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3_MASK 0xff000000
13210 #define MC_IO_DEBUG_DQB0L_TXPHASE_D1__VALUE3__SHIFT 0x18
13211 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0_MASK 0xff
13212 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE0__SHIFT 0x0
13213 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1_MASK 0xff00
13214 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE1__SHIFT 0x8
13215 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2_MASK 0xff0000
13216 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE2__SHIFT 0x10
13217 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3_MASK 0xff000000
13218 #define MC_IO_DEBUG_DQB0H_TXPHASE_D1__VALUE3__SHIFT 0x18
13219 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0_MASK 0xff
13220 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE0__SHIFT 0x0
13221 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1_MASK 0xff00
13222 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE1__SHIFT 0x8
13223 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2_MASK 0xff0000
13224 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE2__SHIFT 0x10
13225 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3_MASK 0xff000000
13226 #define MC_IO_DEBUG_DQB1L_TXPHASE_D1__VALUE3__SHIFT 0x18
13227 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0_MASK 0xff
13228 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE0__SHIFT 0x0
13229 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1_MASK 0xff00
13230 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE1__SHIFT 0x8
13231 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2_MASK 0xff0000
13232 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE2__SHIFT 0x10
13233 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3_MASK 0xff000000
13234 #define MC_IO_DEBUG_DQB1H_TXPHASE_D1__VALUE3__SHIFT 0x18
13235 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0_MASK 0xff
13236 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE0__SHIFT 0x0
13237 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1_MASK 0xff00
13238 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE1__SHIFT 0x8
13239 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2_MASK 0xff0000
13240 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE2__SHIFT 0x10
13241 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3_MASK 0xff000000
13242 #define MC_IO_DEBUG_DQB2L_TXPHASE_D1__VALUE3__SHIFT 0x18
13243 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0_MASK 0xff
13244 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE0__SHIFT 0x0
13245 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1_MASK 0xff00
13246 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE1__SHIFT 0x8
13247 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2_MASK 0xff0000
13248 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE2__SHIFT 0x10
13249 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3_MASK 0xff000000
13250 #define MC_IO_DEBUG_DQB2H_TXPHASE_D1__VALUE3__SHIFT 0x18
13251 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0_MASK 0xff
13252 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE0__SHIFT 0x0
13253 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1_MASK 0xff00
13254 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE1__SHIFT 0x8
13255 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2_MASK 0xff0000
13256 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE2__SHIFT 0x10
13257 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3_MASK 0xff000000
13258 #define MC_IO_DEBUG_DQB3L_TXPHASE_D1__VALUE3__SHIFT 0x18
13259 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0_MASK 0xff
13260 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE0__SHIFT 0x0
13261 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1_MASK 0xff00
13262 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE1__SHIFT 0x8
13263 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2_MASK 0xff0000
13264 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE2__SHIFT 0x10
13265 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3_MASK 0xff000000
13266 #define MC_IO_DEBUG_DQB3H_TXPHASE_D1__VALUE3__SHIFT 0x18
13267 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0_MASK 0xff
13268 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE0__SHIFT 0x0
13269 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1_MASK 0xff00
13270 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE1__SHIFT 0x8
13271 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2_MASK 0xff0000
13272 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE2__SHIFT 0x10
13273 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3_MASK 0xff000000
13274 #define MC_IO_DEBUG_DBI_TXPHASE_D1__VALUE3__SHIFT 0x18
13275 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0_MASK 0xff
13276 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE0__SHIFT 0x0
13277 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1_MASK 0xff00
13278 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE1__SHIFT 0x8
13279 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2_MASK 0xff0000
13280 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE2__SHIFT 0x10
13281 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3_MASK 0xff000000
13282 #define MC_IO_DEBUG_EDC_TXPHASE_D1__VALUE3__SHIFT 0x18
13283 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0_MASK 0xff
13284 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE0__SHIFT 0x0
13285 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1_MASK 0xff00
13286 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE1__SHIFT 0x8
13287 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2_MASK 0xff0000
13288 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE2__SHIFT 0x10
13289 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3_MASK 0xff000000
13290 #define MC_IO_DEBUG_WCK_TXPHASE_D1__VALUE3__SHIFT 0x18
13291 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0_MASK 0xff
13292 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE0__SHIFT 0x0
13293 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1_MASK 0xff00
13294 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE1__SHIFT 0x8
13295 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2_MASK 0xff0000
13296 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE2__SHIFT 0x10
13297 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3_MASK 0xff000000
13298 #define MC_IO_DEBUG_CK_TXPHASE_D1__VALUE3__SHIFT 0x18
13299 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0_MASK 0xff
13300 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE0__SHIFT 0x0
13301 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1_MASK 0xff00
13302 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE1__SHIFT 0x8
13303 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2_MASK 0xff0000
13304 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE2__SHIFT 0x10
13305 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3_MASK 0xff000000
13306 #define MC_IO_DEBUG_ADDRL_TXPHASE_D1__VALUE3__SHIFT 0x18
13307 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0_MASK 0xff
13308 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE0__SHIFT 0x0
13309 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1_MASK 0xff00
13310 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE1__SHIFT 0x8
13311 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2_MASK 0xff0000
13312 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE2__SHIFT 0x10
13313 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3_MASK 0xff000000
13314 #define MC_IO_DEBUG_ADDRH_TXPHASE_D1__VALUE3__SHIFT 0x18
13315 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0_MASK 0xff
13316 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE0__SHIFT 0x0
13317 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1_MASK 0xff00
13318 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE1__SHIFT 0x8
13319 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2_MASK 0xff0000
13320 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE2__SHIFT 0x10
13321 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3_MASK 0xff000000
13322 #define MC_IO_DEBUG_ACMD_TXPHASE_D1__VALUE3__SHIFT 0x18
13323 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0_MASK 0xff
13324 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE0__SHIFT 0x0
13325 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1_MASK 0xff00
13326 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE1__SHIFT 0x8
13327 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2_MASK 0xff0000
13328 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE2__SHIFT 0x10
13329 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3_MASK 0xff000000
13330 #define MC_IO_DEBUG_CMD_TXPHASE_D1__VALUE3__SHIFT 0x18
13331 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13332 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13333 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13334 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13335 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13336 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13337 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13338 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13339 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13340 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13341 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13342 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13343 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13344 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13345 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13346 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13347 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13348 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13349 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13350 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13351 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13352 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13353 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13354 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13355 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13356 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13357 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13358 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13359 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13360 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13361 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13362 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13363 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13364 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13365 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13366 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13367 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13368 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13369 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13370 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13371 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13372 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13373 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13374 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13375 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13376 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13377 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13378 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13379 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13380 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13381 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13382 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13383 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13384 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13385 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13386 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13387 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13388 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13389 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13390 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13391 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13392 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13393 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13394 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13395 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13396 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13397 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13398 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13399 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13400 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13401 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13402 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13403 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13404 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13405 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13406 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13407 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13408 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13409 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13410 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13411 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0_MASK 0xff
13412 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
13413 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
13414 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
13415 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
13416 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
13417 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
13418 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
13419 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13420 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13421 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13422 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13423 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13424 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13425 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13426 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13427 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13428 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13429 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13430 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13431 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13432 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13433 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13434 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13435 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13436 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13437 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13438 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13439 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13440 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13441 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13442 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13443 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13444 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13445 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13446 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13447 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13448 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13449 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13450 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13451 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0_MASK 0xff
13452 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
13453 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
13454 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
13455 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
13456 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
13457 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
13458 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
13459 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13460 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13461 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13462 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13463 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13464 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13465 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13466 #define MC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13467 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13468 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13469 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13470 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13471 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13472 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13473 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13474 #define MC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13475 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13476 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13477 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13478 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13479 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13480 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13481 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13482 #define MC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13483 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13484 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13485 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13486 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13487 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13488 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13489 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13490 #define MC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13491 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13492 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13493 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13494 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13495 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13496 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13497 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13498 #define MC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13499 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13500 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13501 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13502 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13503 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13504 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13505 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13506 #define MC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13507 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13508 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13509 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13510 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13511 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13512 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13513 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13514 #define MC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13515 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13516 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13517 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13518 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13519 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13520 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13521 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13522 #define MC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13523 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13524 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13525 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13526 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13527 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13528 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13529 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13530 #define MC_IO_DEBUG_DBI_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13531 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13532 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13533 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13534 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13535 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13536 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13537 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13538 #define MC_IO_DEBUG_EDC_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13539 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0_MASK 0xff
13540 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
13541 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
13542 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
13543 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
13544 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
13545 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
13546 #define MC_IO_DEBUG_WCK_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
13547 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13548 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13549 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13550 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13551 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13552 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13553 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13554 #define MC_IO_DEBUG_DQB0_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13555 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13556 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13557 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13558 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13559 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13560 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13561 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13562 #define MC_IO_DEBUG_DQB1_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13563 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13564 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13565 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13566 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13567 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13568 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13569 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13570 #define MC_IO_DEBUG_DQB2_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13571 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13572 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13573 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13574 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13575 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13576 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13577 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13578 #define MC_IO_DEBUG_DQB3_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13579 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0_MASK 0xff
13580 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
13581 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
13582 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
13583 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
13584 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
13585 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
13586 #define MC_IO_DEBUG_DBI_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
13587 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0_MASK 0xff
13588 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE0__SHIFT 0x0
13589 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1_MASK 0xff00
13590 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE1__SHIFT 0x8
13591 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2_MASK 0xff0000
13592 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE2__SHIFT 0x10
13593 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3_MASK 0xff000000
13594 #define MC_IO_DEBUG_DQB0L_TXSLF_D0__VALUE3__SHIFT 0x18
13595 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0_MASK 0xff
13596 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE0__SHIFT 0x0
13597 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1_MASK 0xff00
13598 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE1__SHIFT 0x8
13599 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2_MASK 0xff0000
13600 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE2__SHIFT 0x10
13601 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3_MASK 0xff000000
13602 #define MC_IO_DEBUG_DQB0H_TXSLF_D0__VALUE3__SHIFT 0x18
13603 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0_MASK 0xff
13604 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE0__SHIFT 0x0
13605 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1_MASK 0xff00
13606 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE1__SHIFT 0x8
13607 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2_MASK 0xff0000
13608 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE2__SHIFT 0x10
13609 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3_MASK 0xff000000
13610 #define MC_IO_DEBUG_DQB1L_TXSLF_D0__VALUE3__SHIFT 0x18
13611 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0_MASK 0xff
13612 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE0__SHIFT 0x0
13613 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1_MASK 0xff00
13614 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE1__SHIFT 0x8
13615 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2_MASK 0xff0000
13616 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE2__SHIFT 0x10
13617 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3_MASK 0xff000000
13618 #define MC_IO_DEBUG_DQB1H_TXSLF_D0__VALUE3__SHIFT 0x18
13619 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0_MASK 0xff
13620 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE0__SHIFT 0x0
13621 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1_MASK 0xff00
13622 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE1__SHIFT 0x8
13623 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2_MASK 0xff0000
13624 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE2__SHIFT 0x10
13625 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3_MASK 0xff000000
13626 #define MC_IO_DEBUG_DQB2L_TXSLF_D0__VALUE3__SHIFT 0x18
13627 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0_MASK 0xff
13628 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE0__SHIFT 0x0
13629 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1_MASK 0xff00
13630 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE1__SHIFT 0x8
13631 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2_MASK 0xff0000
13632 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE2__SHIFT 0x10
13633 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3_MASK 0xff000000
13634 #define MC_IO_DEBUG_DQB2H_TXSLF_D0__VALUE3__SHIFT 0x18
13635 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0_MASK 0xff
13636 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE0__SHIFT 0x0
13637 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1_MASK 0xff00
13638 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE1__SHIFT 0x8
13639 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2_MASK 0xff0000
13640 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE2__SHIFT 0x10
13641 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3_MASK 0xff000000
13642 #define MC_IO_DEBUG_DQB3L_TXSLF_D0__VALUE3__SHIFT 0x18
13643 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0_MASK 0xff
13644 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE0__SHIFT 0x0
13645 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1_MASK 0xff00
13646 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE1__SHIFT 0x8
13647 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2_MASK 0xff0000
13648 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE2__SHIFT 0x10
13649 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3_MASK 0xff000000
13650 #define MC_IO_DEBUG_DQB3H_TXSLF_D0__VALUE3__SHIFT 0x18
13651 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0_MASK 0xff
13652 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE0__SHIFT 0x0
13653 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1_MASK 0xff00
13654 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE1__SHIFT 0x8
13655 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2_MASK 0xff0000
13656 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE2__SHIFT 0x10
13657 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3_MASK 0xff000000
13658 #define MC_IO_DEBUG_DBI_TXSLF_D0__VALUE3__SHIFT 0x18
13659 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0_MASK 0xff
13660 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE0__SHIFT 0x0
13661 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1_MASK 0xff00
13662 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE1__SHIFT 0x8
13663 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2_MASK 0xff0000
13664 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE2__SHIFT 0x10
13665 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3_MASK 0xff000000
13666 #define MC_IO_DEBUG_EDC_TXSLF_D0__VALUE3__SHIFT 0x18
13667 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0_MASK 0xff
13668 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE0__SHIFT 0x0
13669 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1_MASK 0xff00
13670 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE1__SHIFT 0x8
13671 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2_MASK 0xff0000
13672 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE2__SHIFT 0x10
13673 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3_MASK 0xff000000
13674 #define MC_IO_DEBUG_WCK_TXSLF_D0__VALUE3__SHIFT 0x18
13675 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0_MASK 0xff
13676 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE0__SHIFT 0x0
13677 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1_MASK 0xff00
13678 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE1__SHIFT 0x8
13679 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2_MASK 0xff0000
13680 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE2__SHIFT 0x10
13681 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3_MASK 0xff000000
13682 #define MC_IO_DEBUG_CK_TXSLF_D0__VALUE3__SHIFT 0x18
13683 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0_MASK 0xff
13684 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE0__SHIFT 0x0
13685 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1_MASK 0xff00
13686 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE1__SHIFT 0x8
13687 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2_MASK 0xff0000
13688 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE2__SHIFT 0x10
13689 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3_MASK 0xff000000
13690 #define MC_IO_DEBUG_ADDRL_TXSLF_D0__VALUE3__SHIFT 0x18
13691 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0_MASK 0xff
13692 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE0__SHIFT 0x0
13693 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1_MASK 0xff00
13694 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE1__SHIFT 0x8
13695 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2_MASK 0xff0000
13696 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE2__SHIFT 0x10
13697 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3_MASK 0xff000000
13698 #define MC_IO_DEBUG_ADDRH_TXSLF_D0__VALUE3__SHIFT 0x18
13699 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0_MASK 0xff
13700 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE0__SHIFT 0x0
13701 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1_MASK 0xff00
13702 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE1__SHIFT 0x8
13703 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2_MASK 0xff0000
13704 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE2__SHIFT 0x10
13705 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3_MASK 0xff000000
13706 #define MC_IO_DEBUG_ACMD_TXSLF_D0__VALUE3__SHIFT 0x18
13707 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0_MASK 0xff
13708 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE0__SHIFT 0x0
13709 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1_MASK 0xff00
13710 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE1__SHIFT 0x8
13711 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2_MASK 0xff0000
13712 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE2__SHIFT 0x10
13713 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3_MASK 0xff000000
13714 #define MC_IO_DEBUG_CMD_TXSLF_D0__VALUE3__SHIFT 0x18
13715 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0_MASK 0xff
13716 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE0__SHIFT 0x0
13717 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1_MASK 0xff00
13718 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE1__SHIFT 0x8
13719 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2_MASK 0xff0000
13720 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE2__SHIFT 0x10
13721 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3_MASK 0xff000000
13722 #define MC_IO_DEBUG_DQB0L_TXSLF_D1__VALUE3__SHIFT 0x18
13723 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0_MASK 0xff
13724 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE0__SHIFT 0x0
13725 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1_MASK 0xff00
13726 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE1__SHIFT 0x8
13727 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2_MASK 0xff0000
13728 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE2__SHIFT 0x10
13729 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3_MASK 0xff000000
13730 #define MC_IO_DEBUG_DQB0H_TXSLF_D1__VALUE3__SHIFT 0x18
13731 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0_MASK 0xff
13732 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE0__SHIFT 0x0
13733 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1_MASK 0xff00
13734 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE1__SHIFT 0x8
13735 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2_MASK 0xff0000
13736 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE2__SHIFT 0x10
13737 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3_MASK 0xff000000
13738 #define MC_IO_DEBUG_DQB1L_TXSLF_D1__VALUE3__SHIFT 0x18
13739 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0_MASK 0xff
13740 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE0__SHIFT 0x0
13741 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1_MASK 0xff00
13742 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE1__SHIFT 0x8
13743 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2_MASK 0xff0000
13744 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE2__SHIFT 0x10
13745 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3_MASK 0xff000000
13746 #define MC_IO_DEBUG_DQB1H_TXSLF_D1__VALUE3__SHIFT 0x18
13747 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0_MASK 0xff
13748 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE0__SHIFT 0x0
13749 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1_MASK 0xff00
13750 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE1__SHIFT 0x8
13751 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2_MASK 0xff0000
13752 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE2__SHIFT 0x10
13753 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3_MASK 0xff000000
13754 #define MC_IO_DEBUG_DQB2L_TXSLF_D1__VALUE3__SHIFT 0x18
13755 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0_MASK 0xff
13756 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE0__SHIFT 0x0
13757 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1_MASK 0xff00
13758 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE1__SHIFT 0x8
13759 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2_MASK 0xff0000
13760 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE2__SHIFT 0x10
13761 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3_MASK 0xff000000
13762 #define MC_IO_DEBUG_DQB2H_TXSLF_D1__VALUE3__SHIFT 0x18
13763 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0_MASK 0xff
13764 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE0__SHIFT 0x0
13765 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1_MASK 0xff00
13766 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE1__SHIFT 0x8
13767 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2_MASK 0xff0000
13768 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE2__SHIFT 0x10
13769 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3_MASK 0xff000000
13770 #define MC_IO_DEBUG_DQB3L_TXSLF_D1__VALUE3__SHIFT 0x18
13771 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0_MASK 0xff
13772 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE0__SHIFT 0x0
13773 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1_MASK 0xff00
13774 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE1__SHIFT 0x8
13775 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2_MASK 0xff0000
13776 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE2__SHIFT 0x10
13777 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3_MASK 0xff000000
13778 #define MC_IO_DEBUG_DQB3H_TXSLF_D1__VALUE3__SHIFT 0x18
13779 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0_MASK 0xff
13780 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE0__SHIFT 0x0
13781 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1_MASK 0xff00
13782 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE1__SHIFT 0x8
13783 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2_MASK 0xff0000
13784 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE2__SHIFT 0x10
13785 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3_MASK 0xff000000
13786 #define MC_IO_DEBUG_DBI_TXSLF_D1__VALUE3__SHIFT 0x18
13787 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0_MASK 0xff
13788 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE0__SHIFT 0x0
13789 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1_MASK 0xff00
13790 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE1__SHIFT 0x8
13791 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2_MASK 0xff0000
13792 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE2__SHIFT 0x10
13793 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3_MASK 0xff000000
13794 #define MC_IO_DEBUG_EDC_TXSLF_D1__VALUE3__SHIFT 0x18
13795 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0_MASK 0xff
13796 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE0__SHIFT 0x0
13797 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1_MASK 0xff00
13798 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE1__SHIFT 0x8
13799 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2_MASK 0xff0000
13800 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE2__SHIFT 0x10
13801 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3_MASK 0xff000000
13802 #define MC_IO_DEBUG_WCK_TXSLF_D1__VALUE3__SHIFT 0x18
13803 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0_MASK 0xff
13804 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE0__SHIFT 0x0
13805 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1_MASK 0xff00
13806 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE1__SHIFT 0x8
13807 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2_MASK 0xff0000
13808 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE2__SHIFT 0x10
13809 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3_MASK 0xff000000
13810 #define MC_IO_DEBUG_CK_TXSLF_D1__VALUE3__SHIFT 0x18
13811 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0_MASK 0xff
13812 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE0__SHIFT 0x0
13813 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1_MASK 0xff00
13814 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE1__SHIFT 0x8
13815 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2_MASK 0xff0000
13816 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE2__SHIFT 0x10
13817 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3_MASK 0xff000000
13818 #define MC_IO_DEBUG_ADDRL_TXSLF_D1__VALUE3__SHIFT 0x18
13819 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0_MASK 0xff
13820 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE0__SHIFT 0x0
13821 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1_MASK 0xff00
13822 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE1__SHIFT 0x8
13823 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2_MASK 0xff0000
13824 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE2__SHIFT 0x10
13825 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3_MASK 0xff000000
13826 #define MC_IO_DEBUG_ADDRH_TXSLF_D1__VALUE3__SHIFT 0x18
13827 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0_MASK 0xff
13828 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE0__SHIFT 0x0
13829 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1_MASK 0xff00
13830 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE1__SHIFT 0x8
13831 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2_MASK 0xff0000
13832 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE2__SHIFT 0x10
13833 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3_MASK 0xff000000
13834 #define MC_IO_DEBUG_ACMD_TXSLF_D1__VALUE3__SHIFT 0x18
13835 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0_MASK 0xff
13836 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE0__SHIFT 0x0
13837 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1_MASK 0xff00
13838 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE1__SHIFT 0x8
13839 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2_MASK 0xff0000
13840 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE2__SHIFT 0x10
13841 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3_MASK 0xff000000
13842 #define MC_IO_DEBUG_CMD_TXSLF_D1__VALUE3__SHIFT 0x18
13843 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0_MASK 0xff
13844 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE0__SHIFT 0x0
13845 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1_MASK 0xff00
13846 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE1__SHIFT 0x8
13847 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2_MASK 0xff0000
13848 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE2__SHIFT 0x10
13849 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3_MASK 0xff000000
13850 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D0__VALUE3__SHIFT 0x18
13851 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0_MASK 0xff
13852 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE0__SHIFT 0x0
13853 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1_MASK 0xff00
13854 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE1__SHIFT 0x8
13855 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2_MASK 0xff0000
13856 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE2__SHIFT 0x10
13857 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3_MASK 0xff000000
13858 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D0__VALUE3__SHIFT 0x18
13859 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0_MASK 0xff
13860 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE0__SHIFT 0x0
13861 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1_MASK 0xff00
13862 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE1__SHIFT 0x8
13863 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2_MASK 0xff0000
13864 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE2__SHIFT 0x10
13865 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3_MASK 0xff000000
13866 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D0__VALUE3__SHIFT 0x18
13867 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0_MASK 0xff
13868 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE0__SHIFT 0x0
13869 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1_MASK 0xff00
13870 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE1__SHIFT 0x8
13871 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2_MASK 0xff0000
13872 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE2__SHIFT 0x10
13873 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3_MASK 0xff000000
13874 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D0__VALUE3__SHIFT 0x18
13875 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0_MASK 0xff
13876 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE0__SHIFT 0x0
13877 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1_MASK 0xff00
13878 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE1__SHIFT 0x8
13879 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2_MASK 0xff0000
13880 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE2__SHIFT 0x10
13881 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3_MASK 0xff000000
13882 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D0__VALUE3__SHIFT 0x18
13883 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0_MASK 0xff
13884 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE0__SHIFT 0x0
13885 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1_MASK 0xff00
13886 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE1__SHIFT 0x8
13887 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2_MASK 0xff0000
13888 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE2__SHIFT 0x10
13889 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3_MASK 0xff000000
13890 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D0__VALUE3__SHIFT 0x18
13891 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0_MASK 0xff
13892 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE0__SHIFT 0x0
13893 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1_MASK 0xff00
13894 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE1__SHIFT 0x8
13895 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2_MASK 0xff0000
13896 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE2__SHIFT 0x10
13897 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3_MASK 0xff000000
13898 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D0__VALUE3__SHIFT 0x18
13899 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0_MASK 0xff
13900 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE0__SHIFT 0x0
13901 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1_MASK 0xff00
13902 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE1__SHIFT 0x8
13903 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2_MASK 0xff0000
13904 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE2__SHIFT 0x10
13905 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3_MASK 0xff000000
13906 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D0__VALUE3__SHIFT 0x18
13907 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0_MASK 0xff
13908 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE0__SHIFT 0x0
13909 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1_MASK 0xff00
13910 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE1__SHIFT 0x8
13911 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2_MASK 0xff0000
13912 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE2__SHIFT 0x10
13913 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3_MASK 0xff000000
13914 #define MC_IO_DEBUG_DBI_TXBST_PD_D0__VALUE3__SHIFT 0x18
13915 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0_MASK 0xff
13916 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE0__SHIFT 0x0
13917 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1_MASK 0xff00
13918 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE1__SHIFT 0x8
13919 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2_MASK 0xff0000
13920 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE2__SHIFT 0x10
13921 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3_MASK 0xff000000
13922 #define MC_IO_DEBUG_EDC_TXBST_PD_D0__VALUE3__SHIFT 0x18
13923 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0_MASK 0xff
13924 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE0__SHIFT 0x0
13925 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1_MASK 0xff00
13926 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE1__SHIFT 0x8
13927 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2_MASK 0xff0000
13928 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE2__SHIFT 0x10
13929 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3_MASK 0xff000000
13930 #define MC_IO_DEBUG_WCK_TXBST_PD_D0__VALUE3__SHIFT 0x18
13931 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0_MASK 0xff
13932 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE0__SHIFT 0x0
13933 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1_MASK 0xff00
13934 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE1__SHIFT 0x8
13935 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2_MASK 0xff0000
13936 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE2__SHIFT 0x10
13937 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3_MASK 0xff000000
13938 #define MC_IO_DEBUG_CK_TXBST_PD_D0__VALUE3__SHIFT 0x18
13939 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0_MASK 0xff
13940 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE0__SHIFT 0x0
13941 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1_MASK 0xff00
13942 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE1__SHIFT 0x8
13943 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2_MASK 0xff0000
13944 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE2__SHIFT 0x10
13945 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3_MASK 0xff000000
13946 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D0__VALUE3__SHIFT 0x18
13947 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0_MASK 0xff
13948 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE0__SHIFT 0x0
13949 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1_MASK 0xff00
13950 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE1__SHIFT 0x8
13951 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2_MASK 0xff0000
13952 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE2__SHIFT 0x10
13953 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3_MASK 0xff000000
13954 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D0__VALUE3__SHIFT 0x18
13955 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0_MASK 0xff
13956 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
13957 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1_MASK 0xff00
13958 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
13959 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
13960 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
13961 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
13962 #define MC_IO_DEBUG_ACMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
13963 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0_MASK 0xff
13964 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE0__SHIFT 0x0
13965 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1_MASK 0xff00
13966 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE1__SHIFT 0x8
13967 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2_MASK 0xff0000
13968 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE2__SHIFT 0x10
13969 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3_MASK 0xff000000
13970 #define MC_IO_DEBUG_CMD_TXBST_PD_D0__VALUE3__SHIFT 0x18
13971 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0_MASK 0xff
13972 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13973 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1_MASK 0xff00
13974 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13975 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13976 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13977 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13978 #define MC_IO_DEBUG_DQB0L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13979 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0_MASK 0xff
13980 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13981 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1_MASK 0xff00
13982 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13983 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2_MASK 0xff0000
13984 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE2__SHIFT 0x10
13985 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3_MASK 0xff000000
13986 #define MC_IO_DEBUG_DQB0H_TXBST_PD_D1__VALUE3__SHIFT 0x18
13987 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0_MASK 0xff
13988 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE0__SHIFT 0x0
13989 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1_MASK 0xff00
13990 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE1__SHIFT 0x8
13991 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2_MASK 0xff0000
13992 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE2__SHIFT 0x10
13993 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3_MASK 0xff000000
13994 #define MC_IO_DEBUG_DQB1L_TXBST_PD_D1__VALUE3__SHIFT 0x18
13995 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0_MASK 0xff
13996 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE0__SHIFT 0x0
13997 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1_MASK 0xff00
13998 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE1__SHIFT 0x8
13999 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2_MASK 0xff0000
14000 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE2__SHIFT 0x10
14001 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3_MASK 0xff000000
14002 #define MC_IO_DEBUG_DQB1H_TXBST_PD_D1__VALUE3__SHIFT 0x18
14003 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0_MASK 0xff
14004 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE0__SHIFT 0x0
14005 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1_MASK 0xff00
14006 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE1__SHIFT 0x8
14007 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2_MASK 0xff0000
14008 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE2__SHIFT 0x10
14009 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3_MASK 0xff000000
14010 #define MC_IO_DEBUG_DQB2L_TXBST_PD_D1__VALUE3__SHIFT 0x18
14011 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0_MASK 0xff
14012 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE0__SHIFT 0x0
14013 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1_MASK 0xff00
14014 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE1__SHIFT 0x8
14015 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2_MASK 0xff0000
14016 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE2__SHIFT 0x10
14017 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3_MASK 0xff000000
14018 #define MC_IO_DEBUG_DQB2H_TXBST_PD_D1__VALUE3__SHIFT 0x18
14019 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0_MASK 0xff
14020 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE0__SHIFT 0x0
14021 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1_MASK 0xff00
14022 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE1__SHIFT 0x8
14023 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2_MASK 0xff0000
14024 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE2__SHIFT 0x10
14025 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3_MASK 0xff000000
14026 #define MC_IO_DEBUG_DQB3L_TXBST_PD_D1__VALUE3__SHIFT 0x18
14027 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0_MASK 0xff
14028 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE0__SHIFT 0x0
14029 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1_MASK 0xff00
14030 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE1__SHIFT 0x8
14031 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2_MASK 0xff0000
14032 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE2__SHIFT 0x10
14033 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3_MASK 0xff000000
14034 #define MC_IO_DEBUG_DQB3H_TXBST_PD_D1__VALUE3__SHIFT 0x18
14035 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0_MASK 0xff
14036 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE0__SHIFT 0x0
14037 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1_MASK 0xff00
14038 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE1__SHIFT 0x8
14039 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2_MASK 0xff0000
14040 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE2__SHIFT 0x10
14041 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3_MASK 0xff000000
14042 #define MC_IO_DEBUG_DBI_TXBST_PD_D1__VALUE3__SHIFT 0x18
14043 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0_MASK 0xff
14044 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE0__SHIFT 0x0
14045 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1_MASK 0xff00
14046 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE1__SHIFT 0x8
14047 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2_MASK 0xff0000
14048 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE2__SHIFT 0x10
14049 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3_MASK 0xff000000
14050 #define MC_IO_DEBUG_EDC_TXBST_PD_D1__VALUE3__SHIFT 0x18
14051 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0_MASK 0xff
14052 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE0__SHIFT 0x0
14053 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1_MASK 0xff00
14054 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE1__SHIFT 0x8
14055 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2_MASK 0xff0000
14056 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE2__SHIFT 0x10
14057 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3_MASK 0xff000000
14058 #define MC_IO_DEBUG_WCK_TXBST_PD_D1__VALUE3__SHIFT 0x18
14059 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0_MASK 0xff
14060 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE0__SHIFT 0x0
14061 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1_MASK 0xff00
14062 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE1__SHIFT 0x8
14063 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2_MASK 0xff0000
14064 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE2__SHIFT 0x10
14065 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3_MASK 0xff000000
14066 #define MC_IO_DEBUG_CK_TXBST_PD_D1__VALUE3__SHIFT 0x18
14067 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0_MASK 0xff
14068 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE0__SHIFT 0x0
14069 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1_MASK 0xff00
14070 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE1__SHIFT 0x8
14071 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2_MASK 0xff0000
14072 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE2__SHIFT 0x10
14073 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3_MASK 0xff000000
14074 #define MC_IO_DEBUG_ADDRL_TXBST_PD_D1__VALUE3__SHIFT 0x18
14075 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0_MASK 0xff
14076 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE0__SHIFT 0x0
14077 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1_MASK 0xff00
14078 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE1__SHIFT 0x8
14079 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2_MASK 0xff0000
14080 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE2__SHIFT 0x10
14081 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3_MASK 0xff000000
14082 #define MC_IO_DEBUG_ADDRH_TXBST_PD_D1__VALUE3__SHIFT 0x18
14083 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0_MASK 0xff
14084 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
14085 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1_MASK 0xff00
14086 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
14087 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
14088 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
14089 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
14090 #define MC_IO_DEBUG_ACMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
14091 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0_MASK 0xff
14092 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE0__SHIFT 0x0
14093 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1_MASK 0xff00
14094 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE1__SHIFT 0x8
14095 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2_MASK 0xff0000
14096 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE2__SHIFT 0x10
14097 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3_MASK 0xff000000
14098 #define MC_IO_DEBUG_CMD_TXBST_PD_D1__VALUE3__SHIFT 0x18
14099 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0_MASK 0xff
14100 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE0__SHIFT 0x0
14101 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1_MASK 0xff00
14102 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE1__SHIFT 0x8
14103 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2_MASK 0xff0000
14104 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE2__SHIFT 0x10
14105 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3_MASK 0xff000000
14106 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D0__VALUE3__SHIFT 0x18
14107 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0_MASK 0xff
14108 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE0__SHIFT 0x0
14109 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1_MASK 0xff00
14110 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE1__SHIFT 0x8
14111 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2_MASK 0xff0000
14112 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE2__SHIFT 0x10
14113 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3_MASK 0xff000000
14114 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D0__VALUE3__SHIFT 0x18
14115 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0_MASK 0xff
14116 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE0__SHIFT 0x0
14117 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1_MASK 0xff00
14118 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE1__SHIFT 0x8
14119 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2_MASK 0xff0000
14120 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE2__SHIFT 0x10
14121 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3_MASK 0xff000000
14122 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D0__VALUE3__SHIFT 0x18
14123 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0_MASK 0xff
14124 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE0__SHIFT 0x0
14125 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1_MASK 0xff00
14126 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE1__SHIFT 0x8
14127 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2_MASK 0xff0000
14128 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE2__SHIFT 0x10
14129 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3_MASK 0xff000000
14130 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D0__VALUE3__SHIFT 0x18
14131 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0_MASK 0xff
14132 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE0__SHIFT 0x0
14133 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1_MASK 0xff00
14134 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE1__SHIFT 0x8
14135 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2_MASK 0xff0000
14136 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE2__SHIFT 0x10
14137 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3_MASK 0xff000000
14138 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D0__VALUE3__SHIFT 0x18
14139 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0_MASK 0xff
14140 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE0__SHIFT 0x0
14141 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1_MASK 0xff00
14142 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE1__SHIFT 0x8
14143 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2_MASK 0xff0000
14144 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE2__SHIFT 0x10
14145 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3_MASK 0xff000000
14146 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D0__VALUE3__SHIFT 0x18
14147 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0_MASK 0xff
14148 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE0__SHIFT 0x0
14149 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1_MASK 0xff00
14150 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE1__SHIFT 0x8
14151 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2_MASK 0xff0000
14152 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE2__SHIFT 0x10
14153 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3_MASK 0xff000000
14154 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D0__VALUE3__SHIFT 0x18
14155 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0_MASK 0xff
14156 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE0__SHIFT 0x0
14157 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1_MASK 0xff00
14158 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE1__SHIFT 0x8
14159 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2_MASK 0xff0000
14160 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE2__SHIFT 0x10
14161 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3_MASK 0xff000000
14162 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D0__VALUE3__SHIFT 0x18
14163 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0_MASK 0xff
14164 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE0__SHIFT 0x0
14165 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1_MASK 0xff00
14166 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE1__SHIFT 0x8
14167 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2_MASK 0xff0000
14168 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE2__SHIFT 0x10
14169 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3_MASK 0xff000000
14170 #define MC_IO_DEBUG_DBI_TXBST_PU_D0__VALUE3__SHIFT 0x18
14171 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0_MASK 0xff
14172 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE0__SHIFT 0x0
14173 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1_MASK 0xff00
14174 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE1__SHIFT 0x8
14175 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2_MASK 0xff0000
14176 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE2__SHIFT 0x10
14177 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3_MASK 0xff000000
14178 #define MC_IO_DEBUG_EDC_TXBST_PU_D0__VALUE3__SHIFT 0x18
14179 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0_MASK 0xff
14180 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE0__SHIFT 0x0
14181 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1_MASK 0xff00
14182 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE1__SHIFT 0x8
14183 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2_MASK 0xff0000
14184 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE2__SHIFT 0x10
14185 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3_MASK 0xff000000
14186 #define MC_IO_DEBUG_WCK_TXBST_PU_D0__VALUE3__SHIFT 0x18
14187 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0_MASK 0xff
14188 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE0__SHIFT 0x0
14189 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1_MASK 0xff00
14190 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE1__SHIFT 0x8
14191 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2_MASK 0xff0000
14192 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE2__SHIFT 0x10
14193 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3_MASK 0xff000000
14194 #define MC_IO_DEBUG_CK_TXBST_PU_D0__VALUE3__SHIFT 0x18
14195 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0_MASK 0xff
14196 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE0__SHIFT 0x0
14197 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1_MASK 0xff00
14198 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE1__SHIFT 0x8
14199 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2_MASK 0xff0000
14200 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE2__SHIFT 0x10
14201 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3_MASK 0xff000000
14202 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D0__VALUE3__SHIFT 0x18
14203 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0_MASK 0xff
14204 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE0__SHIFT 0x0
14205 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1_MASK 0xff00
14206 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE1__SHIFT 0x8
14207 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2_MASK 0xff0000
14208 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE2__SHIFT 0x10
14209 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3_MASK 0xff000000
14210 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D0__VALUE3__SHIFT 0x18
14211 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0_MASK 0xff
14212 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
14213 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1_MASK 0xff00
14214 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
14215 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
14216 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
14217 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
14218 #define MC_IO_DEBUG_ACMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
14219 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0_MASK 0xff
14220 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE0__SHIFT 0x0
14221 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1_MASK 0xff00
14222 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE1__SHIFT 0x8
14223 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2_MASK 0xff0000
14224 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE2__SHIFT 0x10
14225 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3_MASK 0xff000000
14226 #define MC_IO_DEBUG_CMD_TXBST_PU_D0__VALUE3__SHIFT 0x18
14227 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0_MASK 0xff
14228 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE0__SHIFT 0x0
14229 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1_MASK 0xff00
14230 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE1__SHIFT 0x8
14231 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2_MASK 0xff0000
14232 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE2__SHIFT 0x10
14233 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3_MASK 0xff000000
14234 #define MC_IO_DEBUG_DQB0L_TXBST_PU_D1__VALUE3__SHIFT 0x18
14235 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0_MASK 0xff
14236 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE0__SHIFT 0x0
14237 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1_MASK 0xff00
14238 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE1__SHIFT 0x8
14239 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2_MASK 0xff0000
14240 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE2__SHIFT 0x10
14241 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3_MASK 0xff000000
14242 #define MC_IO_DEBUG_DQB0H_TXBST_PU_D1__VALUE3__SHIFT 0x18
14243 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0_MASK 0xff
14244 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE0__SHIFT 0x0
14245 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1_MASK 0xff00
14246 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE1__SHIFT 0x8
14247 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2_MASK 0xff0000
14248 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE2__SHIFT 0x10
14249 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3_MASK 0xff000000
14250 #define MC_IO_DEBUG_DQB1L_TXBST_PU_D1__VALUE3__SHIFT 0x18
14251 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0_MASK 0xff
14252 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE0__SHIFT 0x0
14253 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1_MASK 0xff00
14254 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE1__SHIFT 0x8
14255 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2_MASK 0xff0000
14256 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE2__SHIFT 0x10
14257 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3_MASK 0xff000000
14258 #define MC_IO_DEBUG_DQB1H_TXBST_PU_D1__VALUE3__SHIFT 0x18
14259 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0_MASK 0xff
14260 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE0__SHIFT 0x0
14261 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1_MASK 0xff00
14262 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE1__SHIFT 0x8
14263 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2_MASK 0xff0000
14264 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE2__SHIFT 0x10
14265 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3_MASK 0xff000000
14266 #define MC_IO_DEBUG_DQB2L_TXBST_PU_D1__VALUE3__SHIFT 0x18
14267 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0_MASK 0xff
14268 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE0__SHIFT 0x0
14269 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1_MASK 0xff00
14270 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE1__SHIFT 0x8
14271 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2_MASK 0xff0000
14272 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE2__SHIFT 0x10
14273 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3_MASK 0xff000000
14274 #define MC_IO_DEBUG_DQB2H_TXBST_PU_D1__VALUE3__SHIFT 0x18
14275 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0_MASK 0xff
14276 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE0__SHIFT 0x0
14277 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1_MASK 0xff00
14278 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE1__SHIFT 0x8
14279 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2_MASK 0xff0000
14280 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE2__SHIFT 0x10
14281 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3_MASK 0xff000000
14282 #define MC_IO_DEBUG_DQB3L_TXBST_PU_D1__VALUE3__SHIFT 0x18
14283 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0_MASK 0xff
14284 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE0__SHIFT 0x0
14285 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1_MASK 0xff00
14286 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE1__SHIFT 0x8
14287 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2_MASK 0xff0000
14288 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE2__SHIFT 0x10
14289 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3_MASK 0xff000000
14290 #define MC_IO_DEBUG_DQB3H_TXBST_PU_D1__VALUE3__SHIFT 0x18
14291 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0_MASK 0xff
14292 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE0__SHIFT 0x0
14293 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1_MASK 0xff00
14294 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE1__SHIFT 0x8
14295 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2_MASK 0xff0000
14296 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE2__SHIFT 0x10
14297 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3_MASK 0xff000000
14298 #define MC_IO_DEBUG_DBI_TXBST_PU_D1__VALUE3__SHIFT 0x18
14299 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0_MASK 0xff
14300 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE0__SHIFT 0x0
14301 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1_MASK 0xff00
14302 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE1__SHIFT 0x8
14303 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2_MASK 0xff0000
14304 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE2__SHIFT 0x10
14305 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3_MASK 0xff000000
14306 #define MC_IO_DEBUG_EDC_TXBST_PU_D1__VALUE3__SHIFT 0x18
14307 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0_MASK 0xff
14308 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE0__SHIFT 0x0
14309 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1_MASK 0xff00
14310 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE1__SHIFT 0x8
14311 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2_MASK 0xff0000
14312 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE2__SHIFT 0x10
14313 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3_MASK 0xff000000
14314 #define MC_IO_DEBUG_WCK_TXBST_PU_D1__VALUE3__SHIFT 0x18
14315 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0_MASK 0xff
14316 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE0__SHIFT 0x0
14317 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1_MASK 0xff00
14318 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE1__SHIFT 0x8
14319 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2_MASK 0xff0000
14320 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE2__SHIFT 0x10
14321 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3_MASK 0xff000000
14322 #define MC_IO_DEBUG_CK_TXBST_PU_D1__VALUE3__SHIFT 0x18
14323 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0_MASK 0xff
14324 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE0__SHIFT 0x0
14325 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1_MASK 0xff00
14326 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE1__SHIFT 0x8
14327 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2_MASK 0xff0000
14328 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE2__SHIFT 0x10
14329 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3_MASK 0xff000000
14330 #define MC_IO_DEBUG_ADDRL_TXBST_PU_D1__VALUE3__SHIFT 0x18
14331 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0_MASK 0xff
14332 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE0__SHIFT 0x0
14333 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1_MASK 0xff00
14334 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE1__SHIFT 0x8
14335 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2_MASK 0xff0000
14336 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE2__SHIFT 0x10
14337 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3_MASK 0xff000000
14338 #define MC_IO_DEBUG_ADDRH_TXBST_PU_D1__VALUE3__SHIFT 0x18
14339 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0_MASK 0xff
14340 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
14341 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1_MASK 0xff00
14342 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
14343 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
14344 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
14345 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
14346 #define MC_IO_DEBUG_ACMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
14347 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0_MASK 0xff
14348 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE0__SHIFT 0x0
14349 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1_MASK 0xff00
14350 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE1__SHIFT 0x8
14351 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2_MASK 0xff0000
14352 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE2__SHIFT 0x10
14353 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3_MASK 0xff000000
14354 #define MC_IO_DEBUG_CMD_TXBST_PU_D1__VALUE3__SHIFT 0x18
14355 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0_MASK 0xff
14356 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE0__SHIFT 0x0
14357 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1_MASK 0xff00
14358 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE1__SHIFT 0x8
14359 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2_MASK 0xff0000
14360 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE2__SHIFT 0x10
14361 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3_MASK 0xff000000
14362 #define MC_IO_DEBUG_DQB0L_RX_EQ_D0__VALUE3__SHIFT 0x18
14363 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0_MASK 0xff
14364 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE0__SHIFT 0x0
14365 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1_MASK 0xff00
14366 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE1__SHIFT 0x8
14367 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2_MASK 0xff0000
14368 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE2__SHIFT 0x10
14369 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3_MASK 0xff000000
14370 #define MC_IO_DEBUG_DQB0H_RX_EQ_D0__VALUE3__SHIFT 0x18
14371 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0_MASK 0xff
14372 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE0__SHIFT 0x0
14373 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1_MASK 0xff00
14374 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE1__SHIFT 0x8
14375 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2_MASK 0xff0000
14376 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE2__SHIFT 0x10
14377 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3_MASK 0xff000000
14378 #define MC_IO_DEBUG_DQB1L_RX_EQ_D0__VALUE3__SHIFT 0x18
14379 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0_MASK 0xff
14380 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE0__SHIFT 0x0
14381 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1_MASK 0xff00
14382 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE1__SHIFT 0x8
14383 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2_MASK 0xff0000
14384 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE2__SHIFT 0x10
14385 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3_MASK 0xff000000
14386 #define MC_IO_DEBUG_DQB1H_RX_EQ_D0__VALUE3__SHIFT 0x18
14387 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0_MASK 0xff
14388 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE0__SHIFT 0x0
14389 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1_MASK 0xff00
14390 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE1__SHIFT 0x8
14391 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2_MASK 0xff0000
14392 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE2__SHIFT 0x10
14393 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3_MASK 0xff000000
14394 #define MC_IO_DEBUG_DQB2L_RX_EQ_D0__VALUE3__SHIFT 0x18
14395 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0_MASK 0xff
14396 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE0__SHIFT 0x0
14397 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1_MASK 0xff00
14398 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE1__SHIFT 0x8
14399 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2_MASK 0xff0000
14400 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE2__SHIFT 0x10
14401 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3_MASK 0xff000000
14402 #define MC_IO_DEBUG_DQB2H_RX_EQ_D0__VALUE3__SHIFT 0x18
14403 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0_MASK 0xff
14404 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE0__SHIFT 0x0
14405 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1_MASK 0xff00
14406 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE1__SHIFT 0x8
14407 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2_MASK 0xff0000
14408 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE2__SHIFT 0x10
14409 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3_MASK 0xff000000
14410 #define MC_IO_DEBUG_DQB3L_RX_EQ_D0__VALUE3__SHIFT 0x18
14411 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0_MASK 0xff
14412 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE0__SHIFT 0x0
14413 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1_MASK 0xff00
14414 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE1__SHIFT 0x8
14415 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2_MASK 0xff0000
14416 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE2__SHIFT 0x10
14417 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3_MASK 0xff000000
14418 #define MC_IO_DEBUG_DQB3H_RX_EQ_D0__VALUE3__SHIFT 0x18
14419 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0_MASK 0xff
14420 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE0__SHIFT 0x0
14421 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1_MASK 0xff00
14422 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE1__SHIFT 0x8
14423 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2_MASK 0xff0000
14424 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE2__SHIFT 0x10
14425 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3_MASK 0xff000000
14426 #define MC_IO_DEBUG_DBI_RX_EQ_D0__VALUE3__SHIFT 0x18
14427 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0_MASK 0xff
14428 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE0__SHIFT 0x0
14429 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1_MASK 0xff00
14430 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE1__SHIFT 0x8
14431 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2_MASK 0xff0000
14432 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE2__SHIFT 0x10
14433 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3_MASK 0xff000000
14434 #define MC_IO_DEBUG_EDC_RX_EQ_D0__VALUE3__SHIFT 0x18
14435 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0_MASK 0xff
14436 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE0__SHIFT 0x0
14437 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1_MASK 0xff00
14438 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE1__SHIFT 0x8
14439 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2_MASK 0xff0000
14440 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE2__SHIFT 0x10
14441 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3_MASK 0xff000000
14442 #define MC_IO_DEBUG_WCK_RX_EQ_D0__VALUE3__SHIFT 0x18
14443 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0_MASK 0xff
14444 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
14445 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1_MASK 0xff00
14446 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
14447 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
14448 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
14449 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
14450 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
14451 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0_MASK 0xff
14452 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
14453 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1_MASK 0xff00
14454 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
14455 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
14456 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
14457 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
14458 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
14459 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0_MASK 0xff
14460 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
14461 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1_MASK 0xff00
14462 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
14463 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
14464 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
14465 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
14466 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
14467 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0_MASK 0xff
14468 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
14469 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1_MASK 0xff00
14470 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
14471 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
14472 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
14473 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
14474 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
14475 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0_MASK 0xff
14476 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE0__SHIFT 0x0
14477 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1_MASK 0xff00
14478 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE1__SHIFT 0x8
14479 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2_MASK 0xff0000
14480 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE2__SHIFT 0x10
14481 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3_MASK 0xff000000
14482 #define MC_IO_DEBUG_CMD_RX_EQ_D0__VALUE3__SHIFT 0x18
14483 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0_MASK 0xff
14484 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE0__SHIFT 0x0
14485 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1_MASK 0xff00
14486 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE1__SHIFT 0x8
14487 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2_MASK 0xff0000
14488 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE2__SHIFT 0x10
14489 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3_MASK 0xff000000
14490 #define MC_IO_DEBUG_DQB0L_RX_EQ_D1__VALUE3__SHIFT 0x18
14491 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0_MASK 0xff
14492 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE0__SHIFT 0x0
14493 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1_MASK 0xff00
14494 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE1__SHIFT 0x8
14495 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2_MASK 0xff0000
14496 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE2__SHIFT 0x10
14497 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3_MASK 0xff000000
14498 #define MC_IO_DEBUG_DQB0H_RX_EQ_D1__VALUE3__SHIFT 0x18
14499 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0_MASK 0xff
14500 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE0__SHIFT 0x0
14501 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1_MASK 0xff00
14502 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE1__SHIFT 0x8
14503 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2_MASK 0xff0000
14504 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE2__SHIFT 0x10
14505 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3_MASK 0xff000000
14506 #define MC_IO_DEBUG_DQB1L_RX_EQ_D1__VALUE3__SHIFT 0x18
14507 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0_MASK 0xff
14508 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE0__SHIFT 0x0
14509 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1_MASK 0xff00
14510 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE1__SHIFT 0x8
14511 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2_MASK 0xff0000
14512 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE2__SHIFT 0x10
14513 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3_MASK 0xff000000
14514 #define MC_IO_DEBUG_DQB1H_RX_EQ_D1__VALUE3__SHIFT 0x18
14515 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0_MASK 0xff
14516 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE0__SHIFT 0x0
14517 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1_MASK 0xff00
14518 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE1__SHIFT 0x8
14519 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2_MASK 0xff0000
14520 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE2__SHIFT 0x10
14521 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3_MASK 0xff000000
14522 #define MC_IO_DEBUG_DQB2L_RX_EQ_D1__VALUE3__SHIFT 0x18
14523 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0_MASK 0xff
14524 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE0__SHIFT 0x0
14525 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1_MASK 0xff00
14526 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE1__SHIFT 0x8
14527 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2_MASK 0xff0000
14528 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE2__SHIFT 0x10
14529 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3_MASK 0xff000000
14530 #define MC_IO_DEBUG_DQB2H_RX_EQ_D1__VALUE3__SHIFT 0x18
14531 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0_MASK 0xff
14532 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE0__SHIFT 0x0
14533 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1_MASK 0xff00
14534 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE1__SHIFT 0x8
14535 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2_MASK 0xff0000
14536 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE2__SHIFT 0x10
14537 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3_MASK 0xff000000
14538 #define MC_IO_DEBUG_DQB3L_RX_EQ_D1__VALUE3__SHIFT 0x18
14539 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0_MASK 0xff
14540 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE0__SHIFT 0x0
14541 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1_MASK 0xff00
14542 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE1__SHIFT 0x8
14543 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2_MASK 0xff0000
14544 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE2__SHIFT 0x10
14545 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3_MASK 0xff000000
14546 #define MC_IO_DEBUG_DQB3H_RX_EQ_D1__VALUE3__SHIFT 0x18
14547 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0_MASK 0xff
14548 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE0__SHIFT 0x0
14549 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1_MASK 0xff00
14550 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE1__SHIFT 0x8
14551 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2_MASK 0xff0000
14552 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE2__SHIFT 0x10
14553 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3_MASK 0xff000000
14554 #define MC_IO_DEBUG_DBI_RX_EQ_D1__VALUE3__SHIFT 0x18
14555 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0_MASK 0xff
14556 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE0__SHIFT 0x0
14557 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1_MASK 0xff00
14558 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE1__SHIFT 0x8
14559 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2_MASK 0xff0000
14560 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE2__SHIFT 0x10
14561 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3_MASK 0xff000000
14562 #define MC_IO_DEBUG_EDC_RX_EQ_D1__VALUE3__SHIFT 0x18
14563 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0_MASK 0xff
14564 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE0__SHIFT 0x0
14565 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1_MASK 0xff00
14566 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE1__SHIFT 0x8
14567 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2_MASK 0xff0000
14568 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE2__SHIFT 0x10
14569 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3_MASK 0xff000000
14570 #define MC_IO_DEBUG_WCK_RX_EQ_D1__VALUE3__SHIFT 0x18
14571 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0_MASK 0xff
14572 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
14573 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1_MASK 0xff00
14574 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
14575 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
14576 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
14577 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
14578 #define MC_IO_DEBUG_DQ0_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
14579 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0_MASK 0xff
14580 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
14581 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1_MASK 0xff00
14582 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
14583 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
14584 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
14585 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
14586 #define MC_IO_DEBUG_DQ1_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
14587 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0_MASK 0xff
14588 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
14589 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1_MASK 0xff00
14590 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
14591 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
14592 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
14593 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
14594 #define MC_IO_DEBUG_DQ0_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
14595 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0_MASK 0xff
14596 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
14597 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1_MASK 0xff00
14598 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
14599 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
14600 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
14601 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
14602 #define MC_IO_DEBUG_DQ1_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
14603 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0_MASK 0xff
14604 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE0__SHIFT 0x0
14605 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1_MASK 0xff00
14606 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE1__SHIFT 0x8
14607 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2_MASK 0xff0000
14608 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE2__SHIFT 0x10
14609 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3_MASK 0xff000000
14610 #define MC_IO_DEBUG_CMD_RX_EQ_D1__VALUE3__SHIFT 0x18
14611 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0_MASK 0xff
14612 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE0__SHIFT 0x0
14613 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1_MASK 0xff00
14614 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE1__SHIFT 0x8
14615 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2_MASK 0xff0000
14616 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE2__SHIFT 0x10
14617 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3_MASK 0xff000000
14618 #define MC_IO_DEBUG_WCDR_MISC_D0__VALUE3__SHIFT 0x18
14619 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0_MASK 0xff
14620 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE0__SHIFT 0x0
14621 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1_MASK 0xff00
14622 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE1__SHIFT 0x8
14623 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2_MASK 0xff0000
14624 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE2__SHIFT 0x10
14625 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3_MASK 0xff000000
14626 #define MC_IO_DEBUG_WCDR_CLKSEL_D0__VALUE3__SHIFT 0x18
14627 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0_MASK 0xff
14628 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE0__SHIFT 0x0
14629 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1_MASK 0xff00
14630 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE1__SHIFT 0x8
14631 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2_MASK 0xff0000
14632 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE2__SHIFT 0x10
14633 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3_MASK 0xff000000
14634 #define MC_IO_DEBUG_WCDR_OFSCAL_D0__VALUE3__SHIFT 0x18
14635 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0_MASK 0xff
14636 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE0__SHIFT 0x0
14637 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1_MASK 0xff00
14638 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE1__SHIFT 0x8
14639 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2_MASK 0xff0000
14640 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE2__SHIFT 0x10
14641 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3_MASK 0xff000000
14642 #define MC_IO_DEBUG_WCDR_RXPHASE_D0__VALUE3__SHIFT 0x18
14643 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0_MASK 0xff
14644 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE0__SHIFT 0x0
14645 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1_MASK 0xff00
14646 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE1__SHIFT 0x8
14647 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2_MASK 0xff0000
14648 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE2__SHIFT 0x10
14649 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3_MASK 0xff000000
14650 #define MC_IO_DEBUG_WCDR_TXPHASE_D0__VALUE3__SHIFT 0x18
14651 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0_MASK 0xff
14652 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE0__SHIFT 0x0
14653 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1_MASK 0xff00
14654 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE1__SHIFT 0x8
14655 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2_MASK 0xff0000
14656 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE2__SHIFT 0x10
14657 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3_MASK 0xff000000
14658 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D0__VALUE3__SHIFT 0x18
14659 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0_MASK 0xff
14660 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE0__SHIFT 0x0
14661 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1_MASK 0xff00
14662 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE1__SHIFT 0x8
14663 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2_MASK 0xff0000
14664 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE2__SHIFT 0x10
14665 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3_MASK 0xff000000
14666 #define MC_IO_DEBUG_WCDR_TXSLF_D0__VALUE3__SHIFT 0x18
14667 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0_MASK 0xff
14668 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE0__SHIFT 0x0
14669 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1_MASK 0xff00
14670 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE1__SHIFT 0x8
14671 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2_MASK 0xff0000
14672 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE2__SHIFT 0x10
14673 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3_MASK 0xff000000
14674 #define MC_IO_DEBUG_WCDR_TXBST_PD_D0__VALUE3__SHIFT 0x18
14675 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0_MASK 0xff
14676 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE0__SHIFT 0x0
14677 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1_MASK 0xff00
14678 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE1__SHIFT 0x8
14679 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2_MASK 0xff0000
14680 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE2__SHIFT 0x10
14681 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3_MASK 0xff000000
14682 #define MC_IO_DEBUG_WCDR_TXBST_PU_D0__VALUE3__SHIFT 0x18
14683 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0_MASK 0xff
14684 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE0__SHIFT 0x0
14685 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1_MASK 0xff00
14686 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE1__SHIFT 0x8
14687 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2_MASK 0xff0000
14688 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE2__SHIFT 0x10
14689 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3_MASK 0xff000000
14690 #define MC_IO_DEBUG_WCDR_RX_EQ_D0__VALUE3__SHIFT 0x18
14691 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0_MASK 0xff
14692 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE0__SHIFT 0x0
14693 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1_MASK 0xff00
14694 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE1__SHIFT 0x8
14695 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2_MASK 0xff0000
14696 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE2__SHIFT 0x10
14697 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3_MASK 0xff000000
14698 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D0__VALUE3__SHIFT 0x18
14699 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0_MASK 0xff
14700 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE0__SHIFT 0x0
14701 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1_MASK 0xff00
14702 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE1__SHIFT 0x8
14703 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2_MASK 0xff0000
14704 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE2__SHIFT 0x10
14705 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3_MASK 0xff000000
14706 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D0__VALUE3__SHIFT 0x18
14707 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0_MASK 0xff
14708 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE0__SHIFT 0x0
14709 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1_MASK 0xff00
14710 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE1__SHIFT 0x8
14711 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2_MASK 0xff0000
14712 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE2__SHIFT 0x10
14713 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3_MASK 0xff000000
14714 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D0__VALUE3__SHIFT 0x18
14715 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0_MASK 0xff
14716 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE0__SHIFT 0x0
14717 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1_MASK 0xff00
14718 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE1__SHIFT 0x8
14719 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2_MASK 0xff0000
14720 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE2__SHIFT 0x10
14721 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3_MASK 0xff000000
14722 #define MC_IO_DEBUG_WCDR_MISC_D1__VALUE3__SHIFT 0x18
14723 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0_MASK 0xff
14724 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE0__SHIFT 0x0
14725 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1_MASK 0xff00
14726 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE1__SHIFT 0x8
14727 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2_MASK 0xff0000
14728 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE2__SHIFT 0x10
14729 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3_MASK 0xff000000
14730 #define MC_IO_DEBUG_WCDR_CLKSEL_D1__VALUE3__SHIFT 0x18
14731 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0_MASK 0xff
14732 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE0__SHIFT 0x0
14733 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1_MASK 0xff00
14734 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE1__SHIFT 0x8
14735 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2_MASK 0xff0000
14736 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE2__SHIFT 0x10
14737 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3_MASK 0xff000000
14738 #define MC_IO_DEBUG_WCDR_OFSCAL_D1__VALUE3__SHIFT 0x18
14739 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0_MASK 0xff
14740 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE0__SHIFT 0x0
14741 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1_MASK 0xff00
14742 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE1__SHIFT 0x8
14743 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2_MASK 0xff0000
14744 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE2__SHIFT 0x10
14745 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3_MASK 0xff000000
14746 #define MC_IO_DEBUG_WCDR_RXPHASE_D1__VALUE3__SHIFT 0x18
14747 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0_MASK 0xff
14748 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE0__SHIFT 0x0
14749 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1_MASK 0xff00
14750 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE1__SHIFT 0x8
14751 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2_MASK 0xff0000
14752 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE2__SHIFT 0x10
14753 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3_MASK 0xff000000
14754 #define MC_IO_DEBUG_WCDR_TXPHASE_D1__VALUE3__SHIFT 0x18
14755 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0_MASK 0xff
14756 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE0__SHIFT 0x0
14757 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1_MASK 0xff00
14758 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE1__SHIFT 0x8
14759 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2_MASK 0xff0000
14760 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE2__SHIFT 0x10
14761 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3_MASK 0xff000000
14762 #define MC_IO_DEBUG_WCDR_RX_VREF_CAL_D1__VALUE3__SHIFT 0x18
14763 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0_MASK 0xff
14764 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE0__SHIFT 0x0
14765 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1_MASK 0xff00
14766 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE1__SHIFT 0x8
14767 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2_MASK 0xff0000
14768 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE2__SHIFT 0x10
14769 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3_MASK 0xff000000
14770 #define MC_IO_DEBUG_WCDR_TXSLF_D1__VALUE3__SHIFT 0x18
14771 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0_MASK 0xff
14772 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE0__SHIFT 0x0
14773 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1_MASK 0xff00
14774 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE1__SHIFT 0x8
14775 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2_MASK 0xff0000
14776 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE2__SHIFT 0x10
14777 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3_MASK 0xff000000
14778 #define MC_IO_DEBUG_WCDR_TXBST_PD_D1__VALUE3__SHIFT 0x18
14779 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0_MASK 0xff
14780 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE0__SHIFT 0x0
14781 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1_MASK 0xff00
14782 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE1__SHIFT 0x8
14783 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2_MASK 0xff0000
14784 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE2__SHIFT 0x10
14785 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3_MASK 0xff000000
14786 #define MC_IO_DEBUG_WCDR_TXBST_PU_D1__VALUE3__SHIFT 0x18
14787 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0_MASK 0xff
14788 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE0__SHIFT 0x0
14789 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1_MASK 0xff00
14790 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE1__SHIFT 0x8
14791 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2_MASK 0xff0000
14792 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE2__SHIFT 0x10
14793 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3_MASK 0xff000000
14794 #define MC_IO_DEBUG_WCDR_RX_EQ_D1__VALUE3__SHIFT 0x18
14795 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0_MASK 0xff
14796 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE0__SHIFT 0x0
14797 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1_MASK 0xff00
14798 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE1__SHIFT 0x8
14799 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2_MASK 0xff0000
14800 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE2__SHIFT 0x10
14801 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3_MASK 0xff000000
14802 #define MC_IO_DEBUG_WCDR_CDR_PHSIZE_D1__VALUE3__SHIFT 0x18
14803 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0_MASK 0xff
14804 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE0__SHIFT 0x0
14805 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1_MASK 0xff00
14806 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE1__SHIFT 0x8
14807 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2_MASK 0xff0000
14808 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE2__SHIFT 0x10
14809 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3_MASK 0xff000000
14810 #define MC_IO_DEBUG_WCDR_RX_EQ_PM_D1__VALUE3__SHIFT 0x18
14811 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0_MASK 0xff
14812 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE0__SHIFT 0x0
14813 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1_MASK 0xff00
14814 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE1__SHIFT 0x8
14815 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2_MASK 0xff0000
14816 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE2__SHIFT 0x10
14817 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3_MASK 0xff000000
14818 #define MC_IO_DEBUG_WCDR_RX_DYN_PM_D1__VALUE3__SHIFT 0x18
14819 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0_MASK 0x7
14820 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D0__SHIFT 0x0
14821 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0_MASK 0x38
14822 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D0__SHIFT 0x3
14823 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1_MASK 0x1c0
14824 #define MC_SEQ_CNTL_3__PIPE_DELAY_OUT_D1__SHIFT 0x6
14825 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1_MASK 0xe00
14826 #define MC_SEQ_CNTL_3__PIPE_DELAY_IN_D1__SHIFT 0x9
14827 #define MC_SEQ_CNTL_3__REPCG_EN_D0_MASK 0x1000
14828 #define MC_SEQ_CNTL_3__REPCG_EN_D0__SHIFT 0xc
14829 #define MC_SEQ_CNTL_3__REPCG_EN_D1_MASK 0x2000
14830 #define MC_SEQ_CNTL_3__REPCG_EN_D1__SHIFT 0xd
14831 #define MC_SEQ_CNTL_3__REPCG_OFF_DLY_MASK 0xf0000
14832 #define MC_SEQ_CNTL_3__REPCG_OFF_DLY__SHIFT 0x10
14833 #define MC_SEQ_CNTL_3__FCK_FRC_MASK 0x100000
14834 #define MC_SEQ_CNTL_3__FCK_FRC__SHIFT 0x14
14835 #define MC_SEQ_CNTL_3__DBI_FRC_MASK 0x200000
14836 #define MC_SEQ_CNTL_3__DBI_FRC__SHIFT 0x15
14837 #define MC_SEQ_CNTL_3__PRGRM_CDC_MASK 0x400000
14838 #define MC_SEQ_CNTL_3__PRGRM_CDC__SHIFT 0x16
14839 #define MC_SEQ_CNTL_3__DQS_FRC_MASK 0x800000
14840 #define MC_SEQ_CNTL_3__DQS_FRC__SHIFT 0x17
14841 #define MC_SEQ_CNTL_3__DQS_FRC_PAT_MASK 0xf000000
14842 #define MC_SEQ_CNTL_3__DQS_FRC_PAT__SHIFT 0x18
14843 #define MC_SEQ_CNTL_3__IDSC_EN_MASK 0x40000000
14844 #define MC_SEQ_CNTL_3__IDSC_EN__SHIFT 0x1e
14845 #define MC_SEQ_CNTL_3__CAC_EN_MASK 0x80000000
14846 #define MC_SEQ_CNTL_3__CAC_EN__SHIFT 0x1f
14847 #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE_MASK 0x1
14848 #define MC_SEQ_G5PDX_CTRL__CH0_ENABLE__SHIFT 0x0
14849 #define MC_SEQ_G5PDX_CTRL__CH1_ENABLE_MASK 0x2
14850 #define MC_SEQ_G5PDX_CTRL__CH1_ENABLE__SHIFT 0x1
14851 #define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY_MASK 0x4
14852 #define MC_SEQ_G5PDX_CTRL__WCKOFF_EARLY__SHIFT 0x2
14853 #define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE_MASK 0x8
14854 #define MC_SEQ_G5PDX_CTRL__WCKOFF_LATE__SHIFT 0x3
14855 #define MC_SEQ_G5PDX_CTRL__TPD2MRS_MASK 0x3f0
14856 #define MC_SEQ_G5PDX_CTRL__TPD2MRS__SHIFT 0x4
14857 #define MC_SEQ_G5PDX_CTRL__TMRS2WCK_MASK 0xf000
14858 #define MC_SEQ_G5PDX_CTRL__TMRS2WCK__SHIFT 0xc
14859 #define MC_SEQ_G5PDX_CTRL__TWCK2MRS_MASK 0xf0000
14860 #define MC_SEQ_G5PDX_CTRL__TWCK2MRS__SHIFT 0x10
14861 #define MC_SEQ_G5PDX_CTRL__TMRD_MASK 0xf00000
14862 #define MC_SEQ_G5PDX_CTRL__TMRD__SHIFT 0x14
14863 #define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE_MASK 0x1
14864 #define MC_SEQ_G5PDX_CTRL_LP__CH0_ENABLE__SHIFT 0x0
14865 #define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE_MASK 0x2
14866 #define MC_SEQ_G5PDX_CTRL_LP__CH1_ENABLE__SHIFT 0x1
14867 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY_MASK 0x4
14868 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_EARLY__SHIFT 0x2
14869 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE_MASK 0x8
14870 #define MC_SEQ_G5PDX_CTRL_LP__WCKOFF_LATE__SHIFT 0x3
14871 #define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS_MASK 0x3f0
14872 #define MC_SEQ_G5PDX_CTRL_LP__TPD2MRS__SHIFT 0x4
14873 #define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK_MASK 0xf000
14874 #define MC_SEQ_G5PDX_CTRL_LP__TMRS2WCK__SHIFT 0xc
14875 #define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS_MASK 0xf0000
14876 #define MC_SEQ_G5PDX_CTRL_LP__TWCK2MRS__SHIFT 0x10
14877 #define MC_SEQ_G5PDX_CTRL_LP__TMRD_MASK 0xf00000
14878 #define MC_SEQ_G5PDX_CTRL_LP__TMRD__SHIFT 0x14
14879 #define MC_SEQ_G5PDX_CMD0__CMD_MASK 0xffffffff
14880 #define MC_SEQ_G5PDX_CMD0__CMD__SHIFT 0x0
14881 #define MC_SEQ_G5PDX_CMD0_LP__CMD_MASK 0xffffffff
14882 #define MC_SEQ_G5PDX_CMD0_LP__CMD__SHIFT 0x0
14883 #define MC_SEQ_G5PDX_CMD1__CMD_MASK 0xffffffff
14884 #define MC_SEQ_G5PDX_CMD1__CMD__SHIFT 0x0
14885 #define MC_SEQ_G5PDX_CMD1_LP__CMD_MASK 0xffffffff
14886 #define MC_SEQ_G5PDX_CMD1_LP__CMD__SHIFT 0x0
14887 #define MC_SEQ_SREG_READ__DATA_MASK 0xffffffff
14888 #define MC_SEQ_SREG_READ__DATA__SHIFT 0x0
14889 #define MC_SEQ_SREG_STATUS__AVAIL_RTN_MASK 0xf
14890 #define MC_SEQ_SREG_STATUS__AVAIL_RTN__SHIFT 0x0
14891 #define MC_SEQ_SREG_STATUS__PND_RD_MASK 0xf00
14892 #define MC_SEQ_SREG_STATUS__PND_RD__SHIFT 0x8
14893 #define MC_SEQ_SREG_STATUS__PND_WR_MASK 0xf000
14894 #define MC_SEQ_SREG_STATUS__PND_WR__SHIFT 0xc
14895 #define MC_SEQ_PHYREG_BCAST__CH0_EN_MASK 0x1
14896 #define MC_SEQ_PHYREG_BCAST__CH0_EN__SHIFT 0x0
14897 #define MC_SEQ_PHYREG_BCAST__CH1_EN_MASK 0x2
14898 #define MC_SEQ_PHYREG_BCAST__CH1_EN__SHIFT 0x1
14899 #define MC_SEQ_PHYREG_BCAST__CKE_MASK_MASK 0x80
14900 #define MC_SEQ_PHYREG_BCAST__CKE_MASK__SHIFT 0x7
14901 #define MC_SEQ_PHYREG_BCAST__DQ_MASK_MASK 0x100
14902 #define MC_SEQ_PHYREG_BCAST__DQ_MASK__SHIFT 0x8
14903 #define MC_SEQ_PHYREG_BCAST__DBI_MASK_MASK 0x200
14904 #define MC_SEQ_PHYREG_BCAST__DBI_MASK__SHIFT 0x9
14905 #define MC_SEQ_PHYREG_BCAST__EDC_MASK_MASK 0x400
14906 #define MC_SEQ_PHYREG_BCAST__EDC_MASK__SHIFT 0xa
14907 #define MC_SEQ_PHYREG_BCAST__WCK_MASK_MASK 0x800
14908 #define MC_SEQ_PHYREG_BCAST__WCK_MASK__SHIFT 0xb
14909 #define MC_SEQ_PHYREG_BCAST__WCDR_MASK_MASK 0x1000
14910 #define MC_SEQ_PHYREG_BCAST__WCDR_MASK__SHIFT 0xc
14911 #define MC_SEQ_PHYREG_BCAST__CLK_MASK_MASK 0x2000
14912 #define MC_SEQ_PHYREG_BCAST__CLK_MASK__SHIFT 0xd
14913 #define MC_SEQ_PHYREG_BCAST__CMD_MASK_MASK 0x4000
14914 #define MC_SEQ_PHYREG_BCAST__CMD_MASK__SHIFT 0xe
14915 #define MC_SEQ_PHYREG_BCAST__ADR_MASK_MASK 0x8000
14916 #define MC_SEQ_PHYREG_BCAST__ADR_MASK__SHIFT 0xf
14917 #define MC_SEQ_PMG_DVS_CTL__ENABLE_MASK 0x1
14918 #define MC_SEQ_PMG_DVS_CTL__ENABLE__SHIFT 0x0
14919 #define MC_SEQ_PMG_DVS_CTL__TDVS_MASK 0x3e
14920 #define MC_SEQ_PMG_DVS_CTL__TDVS__SHIFT 0x1
14921 #define MC_SEQ_PMG_DVS_CTL_LP__ENABLE_MASK 0x1
14922 #define MC_SEQ_PMG_DVS_CTL_LP__ENABLE__SHIFT 0x0
14923 #define MC_SEQ_PMG_DVS_CTL_LP__TDVS_MASK 0x3e
14924 #define MC_SEQ_PMG_DVS_CTL_LP__TDVS__SHIFT 0x1
14925 #define MC_SEQ_PMG_DVS_CMD__ADR_MASK 0xffff
14926 #define MC_SEQ_PMG_DVS_CMD__ADR__SHIFT 0x0
14927 #define MC_SEQ_PMG_DVS_CMD__MOP_MASK 0x70000
14928 #define MC_SEQ_PMG_DVS_CMD__MOP__SHIFT 0x10
14929 #define MC_SEQ_PMG_DVS_CMD__BNK_MSB_MASK 0x80000
14930 #define MC_SEQ_PMG_DVS_CMD__BNK_MSB__SHIFT 0x13
14931 #define MC_SEQ_PMG_DVS_CMD__END_MASK 0x100000
14932 #define MC_SEQ_PMG_DVS_CMD__END__SHIFT 0x14
14933 #define MC_SEQ_PMG_DVS_CMD__CSB_MASK 0x600000
14934 #define MC_SEQ_PMG_DVS_CMD__CSB__SHIFT 0x15
14935 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB1_MASK 0x800000
14936 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB1__SHIFT 0x17
14937 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB0_MASK 0x1000000
14938 #define MC_SEQ_PMG_DVS_CMD__ADR_MSB0__SHIFT 0x18
14939 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MASK 0xffff
14940 #define MC_SEQ_PMG_DVS_CMD_LP__ADR__SHIFT 0x0
14941 #define MC_SEQ_PMG_DVS_CMD_LP__MOP_MASK 0x70000
14942 #define MC_SEQ_PMG_DVS_CMD_LP__MOP__SHIFT 0x10
14943 #define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB_MASK 0x80000
14944 #define MC_SEQ_PMG_DVS_CMD_LP__BNK_MSB__SHIFT 0x13
14945 #define MC_SEQ_PMG_DVS_CMD_LP__END_MASK 0x100000
14946 #define MC_SEQ_PMG_DVS_CMD_LP__END__SHIFT 0x14
14947 #define MC_SEQ_PMG_DVS_CMD_LP__CSB_MASK 0x600000
14948 #define MC_SEQ_PMG_DVS_CMD_LP__CSB__SHIFT 0x15
14949 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1_MASK 0x800000
14950 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB1__SHIFT 0x17
14951 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0_MASK 0x1000000
14952 #define MC_SEQ_PMG_DVS_CMD_LP__ADR_MSB0__SHIFT 0x18
14953 #define MC_SEQ_DLL_STBY__EN_MASK 0x1
14954 #define MC_SEQ_DLL_STBY__EN__SHIFT 0x0
14955 #define MC_SEQ_DLL_STBY__VCTRLADC_FRC_MASK 0x2
14956 #define MC_SEQ_DLL_STBY__VCTRLADC_FRC__SHIFT 0x1
14957 #define MC_SEQ_DLL_STBY__VCTRLADC_VAL_MASK 0x4
14958 #define MC_SEQ_DLL_STBY__VCTRLADC_VAL__SHIFT 0x2
14959 #define MC_SEQ_DLL_STBY__MSTRSTBY_FRC_MASK 0x8
14960 #define MC_SEQ_DLL_STBY__MSTRSTBY_FRC__SHIFT 0x3
14961 #define MC_SEQ_DLL_STBY__MSTRSTBY_VAL_MASK 0x10
14962 #define MC_SEQ_DLL_STBY__MSTRSTBY_VAL__SHIFT 0x4
14963 #define MC_SEQ_DLL_STBY__ENTR_DLY_MASK 0xe0
14964 #define MC_SEQ_DLL_STBY__ENTR_DLY__SHIFT 0x5
14965 #define MC_SEQ_DLL_STBY__STBY_DLY_MASK 0xf00
14966 #define MC_SEQ_DLL_STBY__STBY_DLY__SHIFT 0x8
14967 #define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN_MASK 0xf000
14968 #define MC_SEQ_DLL_STBY__TCKE_PULSE_EXTN__SHIFT 0xc
14969 #define MC_SEQ_DLL_STBY__TCKE_EXTN_MASK 0xff0000
14970 #define MC_SEQ_DLL_STBY__TCKE_EXTN__SHIFT 0x10
14971 #define MC_SEQ_DLL_STBY__EXIT_DLY_MASK 0x3f000000
14972 #define MC_SEQ_DLL_STBY__EXIT_DLY__SHIFT 0x18
14973 #define MC_SEQ_DLL_STBY_LP__EN_MASK 0x1
14974 #define MC_SEQ_DLL_STBY_LP__EN__SHIFT 0x0
14975 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC_MASK 0x2
14976 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_FRC__SHIFT 0x1
14977 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL_MASK 0x4
14978 #define MC_SEQ_DLL_STBY_LP__VCTRLADC_VAL__SHIFT 0x2
14979 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC_MASK 0x8
14980 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_FRC__SHIFT 0x3
14981 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL_MASK 0x10
14982 #define MC_SEQ_DLL_STBY_LP__MSTRSTBY_VAL__SHIFT 0x4
14983 #define MC_SEQ_DLL_STBY_LP__ENTR_DLY_MASK 0xe0
14984 #define MC_SEQ_DLL_STBY_LP__ENTR_DLY__SHIFT 0x5
14985 #define MC_SEQ_DLL_STBY_LP__STBY_DLY_MASK 0xf00
14986 #define MC_SEQ_DLL_STBY_LP__STBY_DLY__SHIFT 0x8
14987 #define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN_MASK 0xf000
14988 #define MC_SEQ_DLL_STBY_LP__TCKE_PULSE_EXTN__SHIFT 0xc
14989 #define MC_SEQ_DLL_STBY_LP__TCKE_EXTN_MASK 0xff0000
14990 #define MC_SEQ_DLL_STBY_LP__TCKE_EXTN__SHIFT 0x10
14991 #define MC_SEQ_DLL_STBY_LP__EXIT_DLY_MASK 0x3f000000
14992 #define MC_SEQ_DLL_STBY_LP__EXIT_DLY__SHIFT 0x18
14993 #define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS_MASK 0x1
14994 #define MC_DLB_MISCCTRL0__UDD_ON_STATUS_BITS__SHIFT 0x0
14995 #define MC_DLB_MISCCTRL0__LOAD_DATA_SEL_MASK 0x2
14996 #define MC_DLB_MISCCTRL0__LOAD_DATA_SEL__SHIFT 0x1
14997 #define MC_DLB_MISCCTRL0__LOAD_UDD_MASK 0x4
14998 #define MC_DLB_MISCCTRL0__LOAD_UDD__SHIFT 0x2
14999 #define MC_DLB_MISCCTRL0__ADR_STATUS_SEL_MASK 0x8
15000 #define MC_DLB_MISCCTRL0__ADR_STATUS_SEL__SHIFT 0x3
15001 #define MC_DLB_MISCCTRL0__DATA_SEL_MASK 0xf0
15002 #define MC_DLB_MISCCTRL0__DATA_SEL__SHIFT 0x4
15003 #define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT_MASK 0x7f00
15004 #define MC_DLB_MISCCTRL0__PRBS_CHK_LOAD_CNT__SHIFT 0x8
15005 #define MC_DLB_MISCCTRL0__UDD_MASK 0xffff0000
15006 #define MC_DLB_MISCCTRL0__UDD__SHIFT 0x10
15007 #define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT_MASK 0xffffffff
15008 #define MC_DLB_MISCCTRL1__PRBS_ERR_CNT_LIMIT__SHIFT 0x0
15009 #define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH_MASK 0x1ffff
15010 #define MC_DLB_MISCCTRL2__PRBS_RUN_LENGTH__SHIFT 0x0
15011 #define MC_DLB_MISCCTRL2__PRBS_FREERUN_MASK 0x20000
15012 #define MC_DLB_MISCCTRL2__PRBS_FREERUN__SHIFT 0x11
15013 #define MC_DLB_MISCCTRL2__PRBS15_MODE_MASK 0x40000
15014 #define MC_DLB_MISCCTRL2__PRBS15_MODE__SHIFT 0x12
15015 #define MC_DLB_MISCCTRL2__PRBS23_MODE_MASK 0x80000
15016 #define MC_DLB_MISCCTRL2__PRBS23_MODE__SHIFT 0x13
15017 #define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR_MASK 0x100000
15018 #define MC_DLB_MISCCTRL2__STOP_ON_NEXT_ERR__SHIFT 0x14
15019 #define MC_DLB_MISCCTRL2__STOP_CLK_MASK 0x200000
15020 #define MC_DLB_MISCCTRL2__STOP_CLK__SHIFT 0x15
15021 #define MC_DLB_MISCCTRL2__SWEEP_DLY_MASK 0x3000000
15022 #define MC_DLB_MISCCTRL2__SWEEP_DLY__SHIFT 0x18
15023 #define MC_DLB_MISCCTRL2__GRAY_CODE_EN_MASK 0x4000000
15024 #define MC_DLB_MISCCTRL2__GRAY_CODE_EN__SHIFT 0x1a
15025 #define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK_MASK 0x10000000
15026 #define MC_DLB_MISCCTRL2__SEL_PHY_PRBS_CHK__SHIFT 0x1c
15027 #define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK_MASK 0x20000000
15028 #define MC_DLB_MISCCTRL2__SEL_AC_PRBS_CHK__SHIFT 0x1d
15029 #define MC_DLB_MISCCTRL2__STATUS_SEL_MASK 0x40000000
15030 #define MC_DLB_MISCCTRL2__STATUS_SEL__SHIFT 0x1e
15031 #define MC_DLB_CONFIG0__CONF_EN_CH0_MASK 0x1
15032 #define MC_DLB_CONFIG0__CONF_EN_CH0__SHIFT 0x0
15033 #define MC_DLB_CONFIG0__CONF_EN_CH1_MASK 0x2
15034 #define MC_DLB_CONFIG0__CONF_EN_CH1__SHIFT 0x1
15035 #define MC_DLB_CONFIG0__CONF_AUTO_EN_MASK 0x4
15036 #define MC_DLB_CONFIG0__CONF_AUTO_EN__SHIFT 0x2
15037 #define MC_DLB_CONFIG0__MASK_MASK 0xf0
15038 #define MC_DLB_CONFIG0__MASK__SHIFT 0x4
15039 #define MC_DLB_CONFIG0__PTR_MASK 0x3ff00
15040 #define MC_DLB_CONFIG0__PTR__SHIFT 0x8
15041 #define MC_DLB_CONFIG1__DATA_MASK 0xffffffff
15042 #define MC_DLB_CONFIG1__DATA__SHIFT 0x0
15043 #define MC_DLB_SETUP__DLB_EN_MASK 0x1
15044 #define MC_DLB_SETUP__DLB_EN__SHIFT 0x0
15045 #define MC_DLB_SETUP__DLB_FIFO_EN_MASK 0x2
15046 #define MC_DLB_SETUP__DLB_FIFO_EN__SHIFT 0x1
15047 #define MC_DLB_SETUP__DLB_STATUS_EN_MASK 0x4
15048 #define MC_DLB_SETUP__DLB_STATUS_EN__SHIFT 0x2
15049 #define MC_DLB_SETUP__DLB_CONFIG_EN_MASK 0x8
15050 #define MC_DLB_SETUP__DLB_CONFIG_EN__SHIFT 0x3
15051 #define MC_DLB_SETUP__DLB_PRBS_EN_MASK 0x10
15052 #define MC_DLB_SETUP__DLB_PRBS_EN__SHIFT 0x4
15053 #define MC_DLB_SETUP__PRBS_GEN_RST_MASK 0x20
15054 #define MC_DLB_SETUP__PRBS_GEN_RST__SHIFT 0x5
15055 #define MC_DLB_SETUP__PRBS_CHK_RST_MASK 0x40
15056 #define MC_DLB_SETUP__PRBS_CHK_RST__SHIFT 0x6
15057 #define MC_DLB_SETUP__PRBS_PHY_RST_MASK 0x80
15058 #define MC_DLB_SETUP__PRBS_PHY_RST__SHIFT 0x7
15059 #define MC_DLB_SETUP__QDR_MODE_MASK 0x100
15060 #define MC_DLB_SETUP__QDR_MODE__SHIFT 0x8
15061 #define MC_DLB_SETUP__CHK_DATA_BITS_MASK 0xff0000
15062 #define MC_DLB_SETUP__CHK_DATA_BITS__SHIFT 0x10
15063 #define MC_DLB_SETUP__MEM_BIT_SEL_MASK 0x1f000000
15064 #define MC_DLB_SETUP__MEM_BIT_SEL__SHIFT 0x18
15065 #define MC_DLB_SETUP__RXTXLP_EN_MASK 0x80000000
15066 #define MC_DLB_SETUP__RXTXLP_EN__SHIFT 0x1f
15067 #define MC_DLB_SETUPSWEEP__DLL_RST_MASK 0x1
15068 #define MC_DLB_SETUPSWEEP__DLL_RST__SHIFT 0x0
15069 #define MC_DLB_SETUPSWEEP__CONFIG_MASK 0x2
15070 #define MC_DLB_SETUPSWEEP__CONFIG__SHIFT 0x1
15071 #define MC_DLB_SETUPSWEEP__MASTER_MASK 0x4
15072 #define MC_DLB_SETUPSWEEP__MASTER__SHIFT 0x2
15073 #define MC_DLB_SETUPSWEEP__DLLDLY_MASK 0xf0
15074 #define MC_DLB_SETUPSWEEP__DLLDLY__SHIFT 0x4
15075 #define MC_DLB_SETUPSWEEP__DLLSTEPS_MASK 0x1f00
15076 #define MC_DLB_SETUPSWEEP__DLLSTEPS__SHIFT 0x8
15077 #define MC_DLB_SETUPFIFO__WRITE_FIFO_RST_MASK 0x1
15078 #define MC_DLB_SETUPFIFO__WRITE_FIFO_RST__SHIFT 0x0
15079 #define MC_DLB_SETUPFIFO__READ_FIFO_RST_MASK 0x2
15080 #define MC_DLB_SETUPFIFO__READ_FIFO_RST__SHIFT 0x1
15081 #define MC_DLB_SETUPFIFO__BOTH_FIFO_RST_MASK 0x4
15082 #define MC_DLB_SETUPFIFO__BOTH_FIFO_RST__SHIFT 0x2
15083 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK 0x8
15084 #define MC_DLB_SETUPFIFO__SYNC_RST__SHIFT 0x3
15085 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK_MASK 0x30
15086 #define MC_DLB_SETUPFIFO__SYNC_RST_MASK__SHIFT 0x4
15087 #define MC_DLB_SETUPFIFO__OUTPUT_EN_RST_MASK 0x40
15088 #define MC_DLB_SETUPFIFO__OUTPUT_EN_RST__SHIFT 0x6
15089 #define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR_MASK 0x300
15090 #define MC_DLB_SETUPFIFO__SHIFT_WR_FIFO_PTR__SHIFT 0x8
15091 #define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR_MASK 0x1c00
15092 #define MC_DLB_SETUPFIFO__DELAY_RD_FIFO_PTR__SHIFT 0xa
15093 #define MC_DLB_SETUPFIFO__STROBE_MASK 0xf0000
15094 #define MC_DLB_SETUPFIFO__STROBE__SHIFT 0x10
15095 #define MC_DLB_WRITE_MASK__BIT_MASK_MASK 0x3fffff
15096 #define MC_DLB_WRITE_MASK__BIT_MASK__SHIFT 0x0
15097 #define MC_DLB_WRITE_MASK__CH_MASK_MASK 0xf000000
15098 #define MC_DLB_WRITE_MASK__CH_MASK__SHIFT 0x18
15099 #define MC_DLB_STATUS__STICK_ERROR_MASK 0xf
15100 #define MC_DLB_STATUS__STICK_ERROR__SHIFT 0x0
15101 #define MC_DLB_STATUS__LOCK_MASK 0xf0
15102 #define MC_DLB_STATUS__LOCK__SHIFT 0x4
15103 #define MC_DLB_STATUS__SWEEP_DONE_MASK 0xf00
15104 #define MC_DLB_STATUS__SWEEP_DONE__SHIFT 0x8
15105 #define MC_DLB_STATUS_MISC0__DATA_MASK 0xffffffff
15106 #define MC_DLB_STATUS_MISC0__DATA__SHIFT 0x0
15107 #define MC_DLB_STATUS_MISC1__DATA_MASK 0xffffffff
15108 #define MC_DLB_STATUS_MISC1__DATA__SHIFT 0x0
15109 #define MC_DLB_STATUS_MISC2__DATA_MASK 0xffffffff
15110 #define MC_DLB_STATUS_MISC2__DATA__SHIFT 0x0
15111 #define MC_DLB_STATUS_MISC3__DATA_MASK 0xffffffff
15112 #define MC_DLB_STATUS_MISC3__DATA__SHIFT 0x0
15113 #define MC_DLB_STATUS_MISC4__DATA_MASK 0xffffffff
15114 #define MC_DLB_STATUS_MISC4__DATA__SHIFT 0x0
15115 #define MC_DLB_STATUS_MISC5__DATA_MASK 0xffffffff
15116 #define MC_DLB_STATUS_MISC5__DATA__SHIFT 0x0
15117 #define MC_DLB_STATUS_MISC6__DATA_MASK 0xffffffff
15118 #define MC_DLB_STATUS_MISC6__DATA__SHIFT 0x0
15119 #define MC_DLB_STATUS_MISC7__DATA_MASK 0xffffffff
15120 #define MC_DLB_STATUS_MISC7__DATA__SHIFT 0x0
15121 #define MC_ARB_HARSH_EN_RD__TX_PRI_MASK 0xff
15122 #define MC_ARB_HARSH_EN_RD__TX_PRI__SHIFT 0x0
15123 #define MC_ARB_HARSH_EN_RD__BW_PRI_MASK 0xff00
15124 #define MC_ARB_HARSH_EN_RD__BW_PRI__SHIFT 0x8
15125 #define MC_ARB_HARSH_EN_RD__FIX_PRI_MASK 0xff0000
15126 #define MC_ARB_HARSH_EN_RD__FIX_PRI__SHIFT 0x10
15127 #define MC_ARB_HARSH_EN_RD__ST_PRI_MASK 0xff000000
15128 #define MC_ARB_HARSH_EN_RD__ST_PRI__SHIFT 0x18
15129 #define MC_ARB_HARSH_EN_WR__TX_PRI_MASK 0xff
15130 #define MC_ARB_HARSH_EN_WR__TX_PRI__SHIFT 0x0
15131 #define MC_ARB_HARSH_EN_WR__BW_PRI_MASK 0xff00
15132 #define MC_ARB_HARSH_EN_WR__BW_PRI__SHIFT 0x8
15133 #define MC_ARB_HARSH_EN_WR__FIX_PRI_MASK 0xff0000
15134 #define MC_ARB_HARSH_EN_WR__FIX_PRI__SHIFT 0x10
15135 #define MC_ARB_HARSH_EN_WR__ST_PRI_MASK 0xff000000
15136 #define MC_ARB_HARSH_EN_WR__ST_PRI__SHIFT 0x18
15137 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0_MASK 0xff
15138 #define MC_ARB_HARSH_TX_HI0_RD__GROUP0__SHIFT 0x0
15139 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1_MASK 0xff00
15140 #define MC_ARB_HARSH_TX_HI0_RD__GROUP1__SHIFT 0x8
15141 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2_MASK 0xff0000
15142 #define MC_ARB_HARSH_TX_HI0_RD__GROUP2__SHIFT 0x10
15143 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3_MASK 0xff000000
15144 #define MC_ARB_HARSH_TX_HI0_RD__GROUP3__SHIFT 0x18
15145 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0_MASK 0xff
15146 #define MC_ARB_HARSH_TX_HI0_WR__GROUP0__SHIFT 0x0
15147 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1_MASK 0xff00
15148 #define MC_ARB_HARSH_TX_HI0_WR__GROUP1__SHIFT 0x8
15149 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2_MASK 0xff0000
15150 #define MC_ARB_HARSH_TX_HI0_WR__GROUP2__SHIFT 0x10
15151 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3_MASK 0xff000000
15152 #define MC_ARB_HARSH_TX_HI0_WR__GROUP3__SHIFT 0x18
15153 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4_MASK 0xff
15154 #define MC_ARB_HARSH_TX_HI1_RD__GROUP4__SHIFT 0x0
15155 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5_MASK 0xff00
15156 #define MC_ARB_HARSH_TX_HI1_RD__GROUP5__SHIFT 0x8
15157 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6_MASK 0xff0000
15158 #define MC_ARB_HARSH_TX_HI1_RD__GROUP6__SHIFT 0x10
15159 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7_MASK 0xff000000
15160 #define MC_ARB_HARSH_TX_HI1_RD__GROUP7__SHIFT 0x18
15161 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4_MASK 0xff
15162 #define MC_ARB_HARSH_TX_HI1_WR__GROUP4__SHIFT 0x0
15163 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5_MASK 0xff00
15164 #define MC_ARB_HARSH_TX_HI1_WR__GROUP5__SHIFT 0x8
15165 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6_MASK 0xff0000
15166 #define MC_ARB_HARSH_TX_HI1_WR__GROUP6__SHIFT 0x10
15167 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7_MASK 0xff000000
15168 #define MC_ARB_HARSH_TX_HI1_WR__GROUP7__SHIFT 0x18
15169 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0_MASK 0xff
15170 #define MC_ARB_HARSH_TX_LO0_RD__GROUP0__SHIFT 0x0
15171 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1_MASK 0xff00
15172 #define MC_ARB_HARSH_TX_LO0_RD__GROUP1__SHIFT 0x8
15173 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2_MASK 0xff0000
15174 #define MC_ARB_HARSH_TX_LO0_RD__GROUP2__SHIFT 0x10
15175 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3_MASK 0xff000000
15176 #define MC_ARB_HARSH_TX_LO0_RD__GROUP3__SHIFT 0x18
15177 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0_MASK 0xff
15178 #define MC_ARB_HARSH_TX_LO0_WR__GROUP0__SHIFT 0x0
15179 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1_MASK 0xff00
15180 #define MC_ARB_HARSH_TX_LO0_WR__GROUP1__SHIFT 0x8
15181 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2_MASK 0xff0000
15182 #define MC_ARB_HARSH_TX_LO0_WR__GROUP2__SHIFT 0x10
15183 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3_MASK 0xff000000
15184 #define MC_ARB_HARSH_TX_LO0_WR__GROUP3__SHIFT 0x18
15185 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4_MASK 0xff
15186 #define MC_ARB_HARSH_TX_LO1_RD__GROUP4__SHIFT 0x0
15187 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5_MASK 0xff00
15188 #define MC_ARB_HARSH_TX_LO1_RD__GROUP5__SHIFT 0x8
15189 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6_MASK 0xff0000
15190 #define MC_ARB_HARSH_TX_LO1_RD__GROUP6__SHIFT 0x10
15191 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7_MASK 0xff000000
15192 #define MC_ARB_HARSH_TX_LO1_RD__GROUP7__SHIFT 0x18
15193 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4_MASK 0xff
15194 #define MC_ARB_HARSH_TX_LO1_WR__GROUP4__SHIFT 0x0
15195 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5_MASK 0xff00
15196 #define MC_ARB_HARSH_TX_LO1_WR__GROUP5__SHIFT 0x8
15197 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6_MASK 0xff0000
15198 #define MC_ARB_HARSH_TX_LO1_WR__GROUP6__SHIFT 0x10
15199 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7_MASK 0xff000000
15200 #define MC_ARB_HARSH_TX_LO1_WR__GROUP7__SHIFT 0x18
15201 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0_MASK 0xff
15202 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP0__SHIFT 0x0
15203 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1_MASK 0xff00
15204 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP1__SHIFT 0x8
15205 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2_MASK 0xff0000
15206 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP2__SHIFT 0x10
15207 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3_MASK 0xff000000
15208 #define MC_ARB_HARSH_BWPERIOD0_RD__GROUP3__SHIFT 0x18
15209 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0_MASK 0xff
15210 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP0__SHIFT 0x0
15211 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1_MASK 0xff00
15212 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP1__SHIFT 0x8
15213 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2_MASK 0xff0000
15214 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP2__SHIFT 0x10
15215 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3_MASK 0xff000000
15216 #define MC_ARB_HARSH_BWPERIOD0_WR__GROUP3__SHIFT 0x18
15217 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4_MASK 0xff
15218 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP4__SHIFT 0x0
15219 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5_MASK 0xff00
15220 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP5__SHIFT 0x8
15221 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6_MASK 0xff0000
15222 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP6__SHIFT 0x10
15223 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7_MASK 0xff000000
15224 #define MC_ARB_HARSH_BWPERIOD1_RD__GROUP7__SHIFT 0x18
15225 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4_MASK 0xff
15226 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP4__SHIFT 0x0
15227 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5_MASK 0xff00
15228 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP5__SHIFT 0x8
15229 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6_MASK 0xff0000
15230 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP6__SHIFT 0x10
15231 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7_MASK 0xff000000
15232 #define MC_ARB_HARSH_BWPERIOD1_WR__GROUP7__SHIFT 0x18
15233 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0_MASK 0xff
15234 #define MC_ARB_HARSH_BWCNT0_RD__GROUP0__SHIFT 0x0
15235 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1_MASK 0xff00
15236 #define MC_ARB_HARSH_BWCNT0_RD__GROUP1__SHIFT 0x8
15237 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2_MASK 0xff0000
15238 #define MC_ARB_HARSH_BWCNT0_RD__GROUP2__SHIFT 0x10
15239 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3_MASK 0xff000000
15240 #define MC_ARB_HARSH_BWCNT0_RD__GROUP3__SHIFT 0x18
15241 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0_MASK 0xff
15242 #define MC_ARB_HARSH_BWCNT0_WR__GROUP0__SHIFT 0x0
15243 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1_MASK 0xff00
15244 #define MC_ARB_HARSH_BWCNT0_WR__GROUP1__SHIFT 0x8
15245 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2_MASK 0xff0000
15246 #define MC_ARB_HARSH_BWCNT0_WR__GROUP2__SHIFT 0x10
15247 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3_MASK 0xff000000
15248 #define MC_ARB_HARSH_BWCNT0_WR__GROUP3__SHIFT 0x18
15249 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4_MASK 0xff
15250 #define MC_ARB_HARSH_BWCNT1_RD__GROUP4__SHIFT 0x0
15251 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5_MASK 0xff00
15252 #define MC_ARB_HARSH_BWCNT1_RD__GROUP5__SHIFT 0x8
15253 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6_MASK 0xff0000
15254 #define MC_ARB_HARSH_BWCNT1_RD__GROUP6__SHIFT 0x10
15255 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7_MASK 0xff000000
15256 #define MC_ARB_HARSH_BWCNT1_RD__GROUP7__SHIFT 0x18
15257 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4_MASK 0xff
15258 #define MC_ARB_HARSH_BWCNT1_WR__GROUP4__SHIFT 0x0
15259 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5_MASK 0xff00
15260 #define MC_ARB_HARSH_BWCNT1_WR__GROUP5__SHIFT 0x8
15261 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6_MASK 0xff0000
15262 #define MC_ARB_HARSH_BWCNT1_WR__GROUP6__SHIFT 0x10
15263 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7_MASK 0xff000000
15264 #define MC_ARB_HARSH_BWCNT1_WR__GROUP7__SHIFT 0x18
15265 #define MC_ARB_HARSH_SAT0_RD__GROUP0_MASK 0xff
15266 #define MC_ARB_HARSH_SAT0_RD__GROUP0__SHIFT 0x0
15267 #define MC_ARB_HARSH_SAT0_RD__GROUP1_MASK 0xff00
15268 #define MC_ARB_HARSH_SAT0_RD__GROUP1__SHIFT 0x8
15269 #define MC_ARB_HARSH_SAT0_RD__GROUP2_MASK 0xff0000
15270 #define MC_ARB_HARSH_SAT0_RD__GROUP2__SHIFT 0x10
15271 #define MC_ARB_HARSH_SAT0_RD__GROUP3_MASK 0xff000000
15272 #define MC_ARB_HARSH_SAT0_RD__GROUP3__SHIFT 0x18
15273 #define MC_ARB_HARSH_SAT0_WR__GROUP0_MASK 0xff
15274 #define MC_ARB_HARSH_SAT0_WR__GROUP0__SHIFT 0x0
15275 #define MC_ARB_HARSH_SAT0_WR__GROUP1_MASK 0xff00
15276 #define MC_ARB_HARSH_SAT0_WR__GROUP1__SHIFT 0x8
15277 #define MC_ARB_HARSH_SAT0_WR__GROUP2_MASK 0xff0000
15278 #define MC_ARB_HARSH_SAT0_WR__GROUP2__SHIFT 0x10
15279 #define MC_ARB_HARSH_SAT0_WR__GROUP3_MASK 0xff000000
15280 #define MC_ARB_HARSH_SAT0_WR__GROUP3__SHIFT 0x18
15281 #define MC_ARB_HARSH_SAT1_RD__GROUP4_MASK 0xff
15282 #define MC_ARB_HARSH_SAT1_RD__GROUP4__SHIFT 0x0
15283 #define MC_ARB_HARSH_SAT1_RD__GROUP5_MASK 0xff00
15284 #define MC_ARB_HARSH_SAT1_RD__GROUP5__SHIFT 0x8
15285 #define MC_ARB_HARSH_SAT1_RD__GROUP6_MASK 0xff0000
15286 #define MC_ARB_HARSH_SAT1_RD__GROUP6__SHIFT 0x10
15287 #define MC_ARB_HARSH_SAT1_RD__GROUP7_MASK 0xff000000
15288 #define MC_ARB_HARSH_SAT1_RD__GROUP7__SHIFT 0x18
15289 #define MC_ARB_HARSH_SAT1_WR__GROUP4_MASK 0xff
15290 #define MC_ARB_HARSH_SAT1_WR__GROUP4__SHIFT 0x0
15291 #define MC_ARB_HARSH_SAT1_WR__GROUP5_MASK 0xff00
15292 #define MC_ARB_HARSH_SAT1_WR__GROUP5__SHIFT 0x8
15293 #define MC_ARB_HARSH_SAT1_WR__GROUP6_MASK 0xff0000
15294 #define MC_ARB_HARSH_SAT1_WR__GROUP6__SHIFT 0x10
15295 #define MC_ARB_HARSH_SAT1_WR__GROUP7_MASK 0xff000000
15296 #define MC_ARB_HARSH_SAT1_WR__GROUP7__SHIFT 0x18
15297 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST_MASK 0xff
15298 #define MC_ARB_HARSH_CTL_RD__FORCE_HIGHEST__SHIFT 0x0
15299 #define MC_ARB_HARSH_CTL_RD__HARSH_RR_MASK 0x100
15300 #define MC_ARB_HARSH_CTL_RD__HARSH_RR__SHIFT 0x8
15301 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY_MASK 0x200
15302 #define MC_ARB_HARSH_CTL_RD__BANK_AGE_ONLY__SHIFT 0x9
15303 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH_MASK 0x400
15304 #define MC_ARB_HARSH_CTL_RD__USE_LEGACY_HARSH__SHIFT 0xa
15305 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP_MASK 0x800
15306 #define MC_ARB_HARSH_CTL_RD__BWCNT_CATCHUP__SHIFT 0xb
15307 #define MC_ARB_HARSH_CTL_RD__ST_MODE_MASK 0x3000
15308 #define MC_ARB_HARSH_CTL_RD__ST_MODE__SHIFT 0xc
15309 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL_MASK 0x3fc000
15310 #define MC_ARB_HARSH_CTL_RD__FORCE_STALL__SHIFT 0xe
15311 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL_MASK 0x1c00000
15312 #define MC_ARB_HARSH_CTL_RD__PERF_MON_SEL__SHIFT 0x16
15313 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST_MASK 0xff
15314 #define MC_ARB_HARSH_CTL_WR__FORCE_HIGHEST__SHIFT 0x0
15315 #define MC_ARB_HARSH_CTL_WR__HARSH_RR_MASK 0x100
15316 #define MC_ARB_HARSH_CTL_WR__HARSH_RR__SHIFT 0x8
15317 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY_MASK 0x200
15318 #define MC_ARB_HARSH_CTL_WR__BANK_AGE_ONLY__SHIFT 0x9
15319 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH_MASK 0x400
15320 #define MC_ARB_HARSH_CTL_WR__USE_LEGACY_HARSH__SHIFT 0xa
15321 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP_MASK 0x800
15322 #define MC_ARB_HARSH_CTL_WR__BWCNT_CATCHUP__SHIFT 0xb
15323 #define MC_ARB_HARSH_CTL_WR__ST_MODE_MASK 0x3000
15324 #define MC_ARB_HARSH_CTL_WR__ST_MODE__SHIFT 0xc
15325 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL_MASK 0x3fc000
15326 #define MC_ARB_HARSH_CTL_WR__FORCE_STALL__SHIFT 0xe
15327 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL_MASK 0x1c00000
15328 #define MC_ARB_HARSH_CTL_WR__PERF_MON_SEL__SHIFT 0x16
15329 #define MC_ARB_GRUB_PRIORITY1_RD__CB0_MASK 0x3
15330 #define MC_ARB_GRUB_PRIORITY1_RD__CB0__SHIFT 0x0
15331 #define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0_MASK 0xc
15332 #define MC_ARB_GRUB_PRIORITY1_RD__CBCMASK0__SHIFT 0x2
15333 #define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0_MASK 0x30
15334 #define MC_ARB_GRUB_PRIORITY1_RD__CBFMASK0__SHIFT 0x4
15335 #define MC_ARB_GRUB_PRIORITY1_RD__DB0_MASK 0xc0
15336 #define MC_ARB_GRUB_PRIORITY1_RD__DB0__SHIFT 0x6
15337 #define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0_MASK 0x300
15338 #define MC_ARB_GRUB_PRIORITY1_RD__DBHTILE0__SHIFT 0x8
15339 #define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0_MASK 0xc00
15340 #define MC_ARB_GRUB_PRIORITY1_RD__DBSTEN0__SHIFT 0xa
15341 #define MC_ARB_GRUB_PRIORITY1_RD__TC0_MASK 0x3000
15342 #define MC_ARB_GRUB_PRIORITY1_RD__TC0__SHIFT 0xc
15343 #define MC_ARB_GRUB_PRIORITY1_RD__ACPG_MASK 0xc000
15344 #define MC_ARB_GRUB_PRIORITY1_RD__ACPG__SHIFT 0xe
15345 #define MC_ARB_GRUB_PRIORITY1_RD__ACPO_MASK 0x30000
15346 #define MC_ARB_GRUB_PRIORITY1_RD__ACPO__SHIFT 0x10
15347 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_MASK 0xc0000
15348 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF__SHIFT 0x12
15349 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0_MASK 0x300000
15350 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT0__SHIFT 0x14
15351 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1_MASK 0xc00000
15352 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_EXT1__SHIFT 0x16
15353 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW_MASK 0x3000000
15354 #define MC_ARB_GRUB_PRIORITY1_RD__DMIF_TW__SHIFT 0x18
15355 #define MC_ARB_GRUB_PRIORITY1_RD__MCIF_MASK 0xc000000
15356 #define MC_ARB_GRUB_PRIORITY1_RD__MCIF__SHIFT 0x1a
15357 #define MC_ARB_GRUB_PRIORITY1_RD__RLC_MASK 0x30000000
15358 #define MC_ARB_GRUB_PRIORITY1_RD__RLC__SHIFT 0x1c
15359 #define MC_ARB_GRUB_PRIORITY1_RD__VMC_MASK 0xc0000000
15360 #define MC_ARB_GRUB_PRIORITY1_RD__VMC__SHIFT 0x1e
15361 #define MC_ARB_GRUB_PRIORITY1_WR__CB0_MASK 0x3
15362 #define MC_ARB_GRUB_PRIORITY1_WR__CB0__SHIFT 0x0
15363 #define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0_MASK 0xc
15364 #define MC_ARB_GRUB_PRIORITY1_WR__CBCMASK0__SHIFT 0x2
15365 #define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0_MASK 0x30
15366 #define MC_ARB_GRUB_PRIORITY1_WR__CBFMASK0__SHIFT 0x4
15367 #define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0_MASK 0xc0
15368 #define MC_ARB_GRUB_PRIORITY1_WR__CBIMMED0__SHIFT 0x6
15369 #define MC_ARB_GRUB_PRIORITY1_WR__DB0_MASK 0x300
15370 #define MC_ARB_GRUB_PRIORITY1_WR__DB0__SHIFT 0x8
15371 #define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0_MASK 0xc00
15372 #define MC_ARB_GRUB_PRIORITY1_WR__DBHTILE0__SHIFT 0xa
15373 #define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0_MASK 0x3000
15374 #define MC_ARB_GRUB_PRIORITY1_WR__DBSTEN0__SHIFT 0xc
15375 #define MC_ARB_GRUB_PRIORITY1_WR__TC0_MASK 0xc000
15376 #define MC_ARB_GRUB_PRIORITY1_WR__TC0__SHIFT 0xe
15377 #define MC_ARB_GRUB_PRIORITY1_WR__SH_MASK 0x30000
15378 #define MC_ARB_GRUB_PRIORITY1_WR__SH__SHIFT 0x10
15379 #define MC_ARB_GRUB_PRIORITY1_WR__ACPG_MASK 0xc0000
15380 #define MC_ARB_GRUB_PRIORITY1_WR__ACPG__SHIFT 0x12
15381 #define MC_ARB_GRUB_PRIORITY1_WR__ACPO_MASK 0x300000
15382 #define MC_ARB_GRUB_PRIORITY1_WR__ACPO__SHIFT 0x14
15383 #define MC_ARB_GRUB_PRIORITY1_WR__MCIF_MASK 0xc00000
15384 #define MC_ARB_GRUB_PRIORITY1_WR__MCIF__SHIFT 0x16
15385 #define MC_ARB_GRUB_PRIORITY1_WR__RLC_MASK 0x3000000
15386 #define MC_ARB_GRUB_PRIORITY1_WR__RLC__SHIFT 0x18
15387 #define MC_ARB_GRUB_PRIORITY1_WR__SDMA1_MASK 0xc000000
15388 #define MC_ARB_GRUB_PRIORITY1_WR__SDMA1__SHIFT 0x1a
15389 #define MC_ARB_GRUB_PRIORITY1_WR__SMU_MASK 0x30000000
15390 #define MC_ARB_GRUB_PRIORITY1_WR__SMU__SHIFT 0x1c
15391 #define MC_ARB_GRUB_PRIORITY1_WR__VCE0_MASK 0xc0000000
15392 #define MC_ARB_GRUB_PRIORITY1_WR__VCE0__SHIFT 0x1e
15393 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA1_MASK 0x3
15394 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA1__SHIFT 0x0
15395 #define MC_ARB_GRUB_PRIORITY2_RD__SMU_MASK 0xc
15396 #define MC_ARB_GRUB_PRIORITY2_RD__SMU__SHIFT 0x2
15397 #define MC_ARB_GRUB_PRIORITY2_RD__VCE0_MASK 0x30
15398 #define MC_ARB_GRUB_PRIORITY2_RD__VCE0__SHIFT 0x4
15399 #define MC_ARB_GRUB_PRIORITY2_RD__VCE1_MASK 0xc0
15400 #define MC_ARB_GRUB_PRIORITY2_RD__VCE1__SHIFT 0x6
15401 #define MC_ARB_GRUB_PRIORITY2_RD__XDMAM_MASK 0x300
15402 #define MC_ARB_GRUB_PRIORITY2_RD__XDMAM__SHIFT 0x8
15403 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA0_MASK 0xc00
15404 #define MC_ARB_GRUB_PRIORITY2_RD__SDMA0__SHIFT 0xa
15405 #define MC_ARB_GRUB_PRIORITY2_RD__HDP_MASK 0x3000
15406 #define MC_ARB_GRUB_PRIORITY2_RD__HDP__SHIFT 0xc
15407 #define MC_ARB_GRUB_PRIORITY2_RD__UMC_MASK 0xc000
15408 #define MC_ARB_GRUB_PRIORITY2_RD__UMC__SHIFT 0xe
15409 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_MASK 0x30000
15410 #define MC_ARB_GRUB_PRIORITY2_RD__UVD__SHIFT 0x10
15411 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0_MASK 0xc0000
15412 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT0__SHIFT 0x12
15413 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1_MASK 0x300000
15414 #define MC_ARB_GRUB_PRIORITY2_RD__UVD_EXT1__SHIFT 0x14
15415 #define MC_ARB_GRUB_PRIORITY2_RD__SEM_MASK 0xc00000
15416 #define MC_ARB_GRUB_PRIORITY2_RD__SEM__SHIFT 0x16
15417 #define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP_MASK 0x3000000
15418 #define MC_ARB_GRUB_PRIORITY2_RD__SAMMSP__SHIFT 0x18
15419 #define MC_ARB_GRUB_PRIORITY2_RD__VP8_MASK 0xc000000
15420 #define MC_ARB_GRUB_PRIORITY2_RD__VP8__SHIFT 0x1a
15421 #define MC_ARB_GRUB_PRIORITY2_RD__ISP_MASK 0x30000000
15422 #define MC_ARB_GRUB_PRIORITY2_RD__ISP__SHIFT 0x1c
15423 #define MC_ARB_GRUB_PRIORITY2_RD__RSV2_MASK 0xc0000000
15424 #define MC_ARB_GRUB_PRIORITY2_RD__RSV2__SHIFT 0x1e
15425 #define MC_ARB_GRUB_PRIORITY2_WR__VCE1_MASK 0x3
15426 #define MC_ARB_GRUB_PRIORITY2_WR__VCE1__SHIFT 0x0
15427 #define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP_MASK 0xc
15428 #define MC_ARB_GRUB_PRIORITY2_WR__SAMMSP__SHIFT 0x2
15429 #define MC_ARB_GRUB_PRIORITY2_WR__XDMA_MASK 0x30
15430 #define MC_ARB_GRUB_PRIORITY2_WR__XDMA__SHIFT 0x4
15431 #define MC_ARB_GRUB_PRIORITY2_WR__XDMAM_MASK 0xc0
15432 #define MC_ARB_GRUB_PRIORITY2_WR__XDMAM__SHIFT 0x6
15433 #define MC_ARB_GRUB_PRIORITY2_WR__SDMA0_MASK 0x300
15434 #define MC_ARB_GRUB_PRIORITY2_WR__SDMA0__SHIFT 0x8
15435 #define MC_ARB_GRUB_PRIORITY2_WR__HDP_MASK 0xc00
15436 #define MC_ARB_GRUB_PRIORITY2_WR__HDP__SHIFT 0xa
15437 #define MC_ARB_GRUB_PRIORITY2_WR__UMC_MASK 0x3000
15438 #define MC_ARB_GRUB_PRIORITY2_WR__UMC__SHIFT 0xc
15439 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_MASK 0xc000
15440 #define MC_ARB_GRUB_PRIORITY2_WR__UVD__SHIFT 0xe
15441 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0_MASK 0x30000
15442 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT0__SHIFT 0x10
15443 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1_MASK 0xc0000
15444 #define MC_ARB_GRUB_PRIORITY2_WR__UVD_EXT1__SHIFT 0x12
15445 #define MC_ARB_GRUB_PRIORITY2_WR__XDP_MASK 0x300000
15446 #define MC_ARB_GRUB_PRIORITY2_WR__XDP__SHIFT 0x14
15447 #define MC_ARB_GRUB_PRIORITY2_WR__SEM_MASK 0xc00000
15448 #define MC_ARB_GRUB_PRIORITY2_WR__SEM__SHIFT 0x16
15449 #define MC_ARB_GRUB_PRIORITY2_WR__IH_MASK 0x3000000
15450 #define MC_ARB_GRUB_PRIORITY2_WR__IH__SHIFT 0x18
15451 #define MC_ARB_GRUB_PRIORITY2_WR__VP8_MASK 0xc000000
15452 #define MC_ARB_GRUB_PRIORITY2_WR__VP8__SHIFT 0x1a
15453 #define MC_ARB_GRUB_PRIORITY2_WR__ISP_MASK 0x30000000
15454 #define MC_ARB_GRUB_PRIORITY2_WR__ISP__SHIFT 0x1c
15455 #define MC_ARB_GRUB_PRIORITY2_WR__VIN0_MASK 0xc0000000
15456 #define MC_ARB_GRUB_PRIORITY2_WR__VIN0__SHIFT 0x1e
15457 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE_MASK 0x1
15458 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_ENABLE__SHIFT 0x0
15459 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ_MASK 0x2
15460 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUF_DUALSIZE_REQ__SHIFT 0x1
15461 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN_MASK 0x10
15462 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_EN__SHIFT 0x4
15463 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK_MASK 0x20
15464 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_INT_ACK__SHIFT 0x5
15465 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN_MASK 0x40
15466 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_SLICE_INT_EN__SHIFT 0x6
15467 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK_MASK 0xf00
15468 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_BUFMGR_SW_LOCK__SHIFT 0x8
15469 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID_MASK 0xf0000
15470 #define MCIF_WB_BUFMGR_SW_CONTROL__MCIF_WB_P_VMID__SHIFT 0x10
15471 #define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R_MASK 0x1fff
15472 #define MCIF_WB_BUFMGR_CUR_LINE_R__MCIF_WB_BUFMGR_CUR_LINE_R__SHIFT 0x0
15473 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS_MASK 0x1
15474 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_VCE_INT_STATUS__SHIFT 0x0
15475 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS_MASK 0x2
15476 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_SW_INT_STATUS__SHIFT 0x1
15477 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF_MASK 0x70
15478 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_BUF__SHIFT 0x4
15479 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS_MASK 0x80
15480 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUF_DUALSIZE_STATUS__SHIFT 0x7
15481 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG_MASK 0xf00
15482 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_BUFTAG__SHIFT 0x8
15483 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L_MASK 0x1fff000
15484 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_CUR_LINE_L__SHIFT 0xc
15485 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF_MASK 0x70000000
15486 #define MCIF_WB_BUFMGR_STATUS__MCIF_WB_BUFMGR_NEXT_BUF__SHIFT 0x1c
15487 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH_MASK 0xff00
15488 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_LUMA_PITCH__SHIFT 0x8
15489 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH_MASK 0xff000000
15490 #define MCIF_WB_BUF_PITCH__MCIF_WB_BUF_CHROMA_PITCH__SHIFT 0x18
15491 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE_MASK 0x1
15492 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_ACTIVE__SHIFT 0x0
15493 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED_MASK 0x2
15494 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SW_LOCKED__SHIFT 0x1
15495 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED_MASK 0x4
15496 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_VCE_LOCKED__SHIFT 0x2
15497 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW_MASK 0x8
15498 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_OVERFLOW__SHIFT 0x3
15499 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE_MASK 0x10
15500 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_DISABLE__SHIFT 0x4
15501 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE_MASK 0xe0
15502 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_MODE__SHIFT 0x5
15503 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG_MASK 0xf00
15504 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_BUFTAG__SHIFT 0x8
15505 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF_MASK 0x7000
15506 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_NXT_BUF__SHIFT 0xc
15507 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD_MASK 0x8000
15508 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FIELD__SHIFT 0xf
15509 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L_MASK 0x1fff0000
15510 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_CUR_LINE_L__SHIFT 0x10
15511 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR_MASK 0x20000000
15512 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_LONG_LINE_ERROR__SHIFT 0x1d
15513 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR_MASK 0x40000000
15514 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_SHORT_LINE_ERROR__SHIFT 0x1e
15515 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR_MASK 0x80000000
15516 #define MCIF_WB_BUF_1_STATUS__MCIF_WB_BUF_1_FRAME_LENGTH_ERROR__SHIFT 0x1f
15517 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R_MASK 0x1fff
15518 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_CUR_LINE_R__SHIFT 0x0
15519 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT_MASK 0x2000
15520 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_NEW_CONTENT__SHIFT 0xd
15521 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH_MASK 0x4000
15522 #define MCIF_WB_BUF_1_STATUS2__MCIF_WB_BUF_1_COLOR_DEPTH__SHIFT 0xe
15523 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE_MASK 0x1
15524 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_ACTIVE__SHIFT 0x0
15525 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED_MASK 0x2
15526 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SW_LOCKED__SHIFT 0x1
15527 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED_MASK 0x4
15528 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_VCE_LOCKED__SHIFT 0x2
15529 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW_MASK 0x8
15530 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_OVERFLOW__SHIFT 0x3
15531 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE_MASK 0x10
15532 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_DISABLE__SHIFT 0x4
15533 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE_MASK 0xe0
15534 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_MODE__SHIFT 0x5
15535 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG_MASK 0xf00
15536 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_BUFTAG__SHIFT 0x8
15537 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF_MASK 0x7000
15538 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_NXT_BUF__SHIFT 0xc
15539 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD_MASK 0x8000
15540 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FIELD__SHIFT 0xf
15541 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L_MASK 0x1fff0000
15542 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_CUR_LINE_L__SHIFT 0x10
15543 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR_MASK 0x20000000
15544 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_LONG_LINE_ERROR__SHIFT 0x1d
15545 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR_MASK 0x40000000
15546 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_SHORT_LINE_ERROR__SHIFT 0x1e
15547 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR_MASK 0x80000000
15548 #define MCIF_WB_BUF_2_STATUS__MCIF_WB_BUF_2_FRAME_LENGTH_ERROR__SHIFT 0x1f
15549 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R_MASK 0x1fff
15550 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_CUR_LINE_R__SHIFT 0x0
15551 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT_MASK 0x2000
15552 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_NEW_CONTENT__SHIFT 0xd
15553 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH_MASK 0x4000
15554 #define MCIF_WB_BUF_2_STATUS2__MCIF_WB_BUF_2_COLOR_DEPTH__SHIFT 0xe
15555 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE_MASK 0x1
15556 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_ACTIVE__SHIFT 0x0
15557 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED_MASK 0x2
15558 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SW_LOCKED__SHIFT 0x1
15559 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED_MASK 0x4
15560 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_VCE_LOCKED__SHIFT 0x2
15561 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW_MASK 0x8
15562 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_OVERFLOW__SHIFT 0x3
15563 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE_MASK 0x10
15564 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_DISABLE__SHIFT 0x4
15565 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE_MASK 0xe0
15566 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_MODE__SHIFT 0x5
15567 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG_MASK 0xf00
15568 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_BUFTAG__SHIFT 0x8
15569 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF_MASK 0x7000
15570 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_NXT_BUF__SHIFT 0xc
15571 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD_MASK 0x8000
15572 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FIELD__SHIFT 0xf
15573 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L_MASK 0x1fff0000
15574 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_CUR_LINE_L__SHIFT 0x10
15575 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR_MASK 0x20000000
15576 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_LONG_LINE_ERROR__SHIFT 0x1d
15577 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR_MASK 0x40000000
15578 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_SHORT_LINE_ERROR__SHIFT 0x1e
15579 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR_MASK 0x80000000
15580 #define MCIF_WB_BUF_3_STATUS__MCIF_WB_BUF_3_FRAME_LENGTH_ERROR__SHIFT 0x1f
15581 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R_MASK 0x1fff
15582 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_CUR_LINE_R__SHIFT 0x0
15583 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT_MASK 0x2000
15584 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_NEW_CONTENT__SHIFT 0xd
15585 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH_MASK 0x4000
15586 #define MCIF_WB_BUF_3_STATUS2__MCIF_WB_BUF_3_COLOR_DEPTH__SHIFT 0xe
15587 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE_MASK 0x1
15588 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_ACTIVE__SHIFT 0x0
15589 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED_MASK 0x2
15590 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SW_LOCKED__SHIFT 0x1
15591 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED_MASK 0x4
15592 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_VCE_LOCKED__SHIFT 0x2
15593 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW_MASK 0x8
15594 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_OVERFLOW__SHIFT 0x3
15595 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE_MASK 0x10
15596 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_DISABLE__SHIFT 0x4
15597 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE_MASK 0xe0
15598 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_MODE__SHIFT 0x5
15599 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG_MASK 0xf00
15600 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_BUFTAG__SHIFT 0x8
15601 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF_MASK 0x7000
15602 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_NXT_BUF__SHIFT 0xc
15603 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD_MASK 0x8000
15604 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FIELD__SHIFT 0xf
15605 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L_MASK 0x1fff0000
15606 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_CUR_LINE_L__SHIFT 0x10
15607 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR_MASK 0x20000000
15608 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_LONG_LINE_ERROR__SHIFT 0x1d
15609 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR_MASK 0x40000000
15610 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_SHORT_LINE_ERROR__SHIFT 0x1e
15611 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR_MASK 0x80000000
15612 #define MCIF_WB_BUF_4_STATUS__MCIF_WB_BUF_4_FRAME_LENGTH_ERROR__SHIFT 0x1f
15613 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R_MASK 0x1fff
15614 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_CUR_LINE_R__SHIFT 0x0
15615 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT_MASK 0x2000
15616 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_NEW_CONTENT__SHIFT 0xd
15617 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH_MASK 0x4000
15618 #define MCIF_WB_BUF_4_STATUS2__MCIF_WB_BUF_4_COLOR_DEPTH__SHIFT 0xe
15619 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE_MASK 0x3
15620 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_CLIENT_ARBITRATION_SLICE__SHIFT 0x0
15621 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL_MASK 0xfc000000
15622 #define MCIF_WB_ARBITRATION_CONTROL__MCIF_WB_TIME_PER_PIXEL__SHIFT 0x1a
15623 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK_MASK 0xffff
15624 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT0_URGENCY_WATERMARK__SHIFT 0x0
15625 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK_MASK 0xffff0000
15626 #define MCIF_WB_URGENCY_WATERMARK__MCIF_WB_CLIENT1_URGENCY_WATERMARK__SHIFT 0x10
15627 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX_MASK 0xff
15628 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_INDEX__SHIFT 0x0
15629 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN_MASK 0x100
15630 #define MCIF_WB_TEST_DEBUG_INDEX__MCIF_WB_TEST_DEBUG_WRITE_EN__SHIFT 0x8
15631 #define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA_MASK 0xffffffff
15632 #define MCIF_WB_TEST_DEBUG_DATA__MCIF_WB_TEST_DEBUG_DATA__SHIFT 0x0
15633 #define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y_MASK 0xffffffff
15634 #define MCIF_WB_BUF_1_ADDR_Y__MCIF_WB_BUF_1_ADDR_Y__SHIFT 0x0
15635 #define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET_MASK 0x3ffff
15636 #define MCIF_WB_BUF_1_ADDR_Y_OFFSET__MCIF_WB_BUF_1_ADDR_Y_OFFSET__SHIFT 0x0
15637 #define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C_MASK 0xffffffff
15638 #define MCIF_WB_BUF_1_ADDR_C__MCIF_WB_BUF_1_ADDR_C__SHIFT 0x0
15639 #define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET_MASK 0x3ffff
15640 #define MCIF_WB_BUF_1_ADDR_C_OFFSET__MCIF_WB_BUF_1_ADDR_C_OFFSET__SHIFT 0x0
15641 #define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y_MASK 0xffffffff
15642 #define MCIF_WB_BUF_2_ADDR_Y__MCIF_WB_BUF_2_ADDR_Y__SHIFT 0x0
15643 #define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET_MASK 0x3ffff
15644 #define MCIF_WB_BUF_2_ADDR_Y_OFFSET__MCIF_WB_BUF_2_ADDR_Y_OFFSET__SHIFT 0x0
15645 #define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C_MASK 0xffffffff
15646 #define MCIF_WB_BUF_2_ADDR_C__MCIF_WB_BUF_2_ADDR_C__SHIFT 0x0
15647 #define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET_MASK 0x3ffff
15648 #define MCIF_WB_BUF_2_ADDR_C_OFFSET__MCIF_WB_BUF_2_ADDR_C_OFFSET__SHIFT 0x0
15649 #define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y_MASK 0xffffffff
15650 #define MCIF_WB_BUF_3_ADDR_Y__MCIF_WB_BUF_3_ADDR_Y__SHIFT 0x0
15651 #define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET_MASK 0x3ffff
15652 #define MCIF_WB_BUF_3_ADDR_Y_OFFSET__MCIF_WB_BUF_3_ADDR_Y_OFFSET__SHIFT 0x0
15653 #define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C_MASK 0xffffffff
15654 #define MCIF_WB_BUF_3_ADDR_C__MCIF_WB_BUF_3_ADDR_C__SHIFT 0x0
15655 #define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET_MASK 0x3ffff
15656 #define MCIF_WB_BUF_3_ADDR_C_OFFSET__MCIF_WB_BUF_3_ADDR_C_OFFSET__SHIFT 0x0
15657 #define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y_MASK 0xffffffff
15658 #define MCIF_WB_BUF_4_ADDR_Y__MCIF_WB_BUF_4_ADDR_Y__SHIFT 0x0
15659 #define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET_MASK 0x3ffff
15660 #define MCIF_WB_BUF_4_ADDR_Y_OFFSET__MCIF_WB_BUF_4_ADDR_Y_OFFSET__SHIFT 0x0
15661 #define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C_MASK 0xffffffff
15662 #define MCIF_WB_BUF_4_ADDR_C__MCIF_WB_BUF_4_ADDR_C__SHIFT 0x0
15663 #define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET_MASK 0x3ffff
15664 #define MCIF_WB_BUF_4_ADDR_C_OFFSET__MCIF_WB_BUF_4_ADDR_C_OFFSET__SHIFT 0x0
15665 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE_MASK 0x1
15666 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_IGNORE__SHIFT 0x0
15667 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN_MASK 0x10
15668 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_EN__SHIFT 0x4
15669 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK_MASK 0x20
15670 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_INT_ACK__SHIFT 0x5
15671 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN_MASK 0x40
15672 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_SLICE_INT_EN__SHIFT 0x6
15673 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK_MASK 0xf00
15674 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_VCE_LOCK__SHIFT 0x8
15675 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE_MASK 0x1fff0000
15676 #define MCIF_WB_BUFMGR_VCE_CONTROL__MCIF_WB_BUFMGR_SLICE_SIZE__SHIFT 0x10
15677 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID_MASK 0xf00
15678 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_DEFAULT_VMID__SHIFT 0x8
15679 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK_MASK 0xffff0000
15680 #define MCIF_WB_HVVMID_CONTROL__MCIF_WB_ALLOWED_VMID_MASK__SHIFT 0x10
15681 
15682 #endif /* GMC_8_1_SH_MASK_H */
15683