1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _hdp_4_0_SH_MASK_HEADER 22 #define _hdp_4_0_SH_MASK_HEADER 23 24 25 // addressBlock: hdp_hdpdec 26 //HDP_MMHUB_TLVL 27 #define HDP_MMHUB_TLVL__HDP_WR_TLVL__SHIFT 0x0 28 #define HDP_MMHUB_TLVL__HDP_RD_TLVL__SHIFT 0x4 29 #define HDP_MMHUB_TLVL__XDP_WR_TLVL__SHIFT 0x8 30 #define HDP_MMHUB_TLVL__XDP_RD_TLVL__SHIFT 0xc 31 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL__SHIFT 0x10 32 #define HDP_MMHUB_TLVL__HDP_WR_TLVL_MASK 0x00000007L 33 #define HDP_MMHUB_TLVL__HDP_RD_TLVL_MASK 0x00000070L 34 #define HDP_MMHUB_TLVL__XDP_WR_TLVL_MASK 0x00000700L 35 #define HDP_MMHUB_TLVL__XDP_RD_TLVL_MASK 0x00007000L 36 #define HDP_MMHUB_TLVL__XDP_MBX_WR_TLVL_MASK 0x00070000L 37 //HDP_MMHUB_UNITID 38 #define HDP_MMHUB_UNITID__HDP_UNITID__SHIFT 0x0 39 #define HDP_MMHUB_UNITID__XDP_UNITID__SHIFT 0x8 40 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID__SHIFT 0x10 41 #define HDP_MMHUB_UNITID__HDP_UNITID_MASK 0x0000003FL 42 #define HDP_MMHUB_UNITID__XDP_UNITID_MASK 0x00003F00L 43 #define HDP_MMHUB_UNITID__XDP_MBX_UNITID_MASK 0x003F0000L 44 //HDP_NONSURFACE_BASE 45 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8__SHIFT 0x0 46 #define HDP_NONSURFACE_BASE__NONSURF_BASE_39_8_MASK 0xFFFFFFFFL 47 //HDP_NONSURFACE_INFO 48 #define HDP_NONSURFACE_INFO__NONSURF_SWAP__SHIFT 0x4 49 #define HDP_NONSURFACE_INFO__NONSURF_VMID__SHIFT 0x8 50 #define HDP_NONSURFACE_INFO__NONSURF_SWAP_MASK 0x00000030L 51 #define HDP_NONSURFACE_INFO__NONSURF_VMID_MASK 0x00000F00L 52 //HDP_NONSURFACE_BASE_HI 53 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40__SHIFT 0x0 54 #define HDP_NONSURFACE_BASE_HI__NONSURF_BASE_47_40_MASK 0x000000FFL 55 //HDP_NONSURF_FLAGS 56 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG__SHIFT 0x0 57 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG__SHIFT 0x1 58 #define HDP_NONSURF_FLAGS__NONSURF_WRITE_FLAG_MASK 0x00000001L 59 #define HDP_NONSURF_FLAGS__NONSURF_READ_FLAG_MASK 0x00000002L 60 //HDP_NONSURF_FLAGS_CLR 61 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR__SHIFT 0x0 62 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR__SHIFT 0x1 63 #define HDP_NONSURF_FLAGS_CLR__NONSURF_WRITE_FLAG_CLR_MASK 0x00000001L 64 #define HDP_NONSURF_FLAGS_CLR__NONSURF_READ_FLAG_CLR_MASK 0x00000002L 65 //HDP_HOST_PATH_CNTL 66 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER__SHIFT 0x9 67 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER__SHIFT 0xb 68 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x12 69 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER__SHIFT 0x13 70 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN__SHIFT 0x15 71 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN__SHIFT 0x16 72 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS__SHIFT 0x1d 73 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS__SHIFT 0x1e 74 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS__SHIFT 0x1f 75 #define HDP_HOST_PATH_CNTL__WR_STALL_TIMER_MASK 0x00000600L 76 #define HDP_HOST_PATH_CNTL__RD_STALL_TIMER_MASK 0x00001800L 77 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00040000L 78 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_TIMER_MASK 0x00180000L 79 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_EN_MASK 0x00200000L 80 #define HDP_HOST_PATH_CNTL__WRITE_COMBINE_64B_EN_MASK 0x00400000L 81 #define HDP_HOST_PATH_CNTL__ALL_SURFACES_DIS_MASK 0x20000000L 82 #define HDP_HOST_PATH_CNTL__WRITE_THROUGH_CACHE_DIS_MASK 0x40000000L 83 #define HDP_HOST_PATH_CNTL__LIN_RD_CACHE_DIS_MASK 0x80000000L 84 //HDP_SW_SEMAPHORE 85 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE__SHIFT 0x0 86 #define HDP_SW_SEMAPHORE__SW_SEMAPHORE_MASK 0xFFFFFFFFL 87 //HDP_DEBUG0 88 #define HDP_DEBUG0__HDP_DEBUG__SHIFT 0x0 89 #define HDP_DEBUG0__HDP_DEBUG_MASK 0xFFFFFFFFL 90 //HDP_LAST_SURFACE_HIT 91 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT__SHIFT 0x0 92 #define HDP_LAST_SURFACE_HIT__LAST_SURFACE_HIT_MASK 0x00000003L 93 //HDP_READ_CACHE_INVALIDATE 94 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE__SHIFT 0x0 95 #define HDP_READ_CACHE_INVALIDATE__READ_CACHE_INVALIDATE_MASK 0x00000001L 96 //HDP_OUTSTANDING_REQ 97 #define HDP_OUTSTANDING_REQ__WRITE_REQ__SHIFT 0x0 98 #define HDP_OUTSTANDING_REQ__READ_REQ__SHIFT 0x8 99 #define HDP_OUTSTANDING_REQ__WRITE_REQ_MASK 0x000000FFL 100 #define HDP_OUTSTANDING_REQ__READ_REQ_MASK 0x0000FF00L 101 //HDP_MISC_CNTL 102 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE__SHIFT 0x0 103 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL__SHIFT 0x2 104 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024__SHIFT 0x5 105 #define HDP_MISC_CNTL__MULTIPLE_READS__SHIFT 0x6 106 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES__SHIFT 0xb 107 #define HDP_MISC_CNTL__FED_ENABLE__SHIFT 0x15 108 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY__SHIFT 0x17 109 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE__SHIFT 0x18 110 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID__SHIFT 0x19 111 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1a 112 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK__SHIFT 0x1b 113 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE__SHIFT 0x1c 114 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE__SHIFT 0x1d 115 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE__SHIFT 0x1e 116 #define HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK 0x00000001L 117 #define HDP_MISC_CNTL__IDLE_HYSTERESIS_CNTL_MASK 0x0000000CL 118 #define HDP_MISC_CNTL__OUTSTANDING_WRITE_COUNT_1024_MASK 0x00000020L 119 #define HDP_MISC_CNTL__MULTIPLE_READS_MASK 0x00000040L 120 #define HDP_MISC_CNTL__SIMULTANEOUS_READS_WRITES_MASK 0x00000800L 121 #define HDP_MISC_CNTL__FED_ENABLE_MASK 0x00200000L 122 #define HDP_MISC_CNTL__SYSHUB_CHANNEL_PRIORITY_MASK 0x00800000L 123 #define HDP_MISC_CNTL__MMHUB_WRBURST_ENABLE_MASK 0x01000000L 124 #define HDP_MISC_CNTL__ALL_FUNCTION_CACHELINE_INVALID_MASK 0x02000000L 125 #define HDP_MISC_CNTL__HDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x04000000L 126 #define HDP_MISC_CNTL__XDP_MMHUB_PENDING_WR_TAG_CHECK_MASK 0x08000000L 127 #define HDP_MISC_CNTL__VARIABLE_CACHELINE_SIZE_MASK 0x10000000L 128 #define HDP_MISC_CNTL__ADAPTIVE_CACHELINE_SIZE_MASK 0x20000000L 129 #define HDP_MISC_CNTL__MMHUB_WRBURST_SIZE_MASK 0x40000000L 130 //HDP_MEM_POWER_LS 131 #define HDP_MEM_POWER_LS__LS_ENABLE__SHIFT 0x0 132 #define HDP_MEM_POWER_LS__LS_HOLD__SHIFT 0x7 133 #define HDP_MEM_POWER_LS__LS_ENABLE_MASK 0x00000001L 134 #define HDP_MEM_POWER_LS__LS_HOLD_MASK 0x00001F80L 135 //HDP_MMHUB_CNTL 136 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO__SHIFT 0x0 137 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC__SHIFT 0x1 138 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP__SHIFT 0x2 139 #define HDP_MMHUB_CNTL__HDP_MMHUB_RO_MASK 0x00000001L 140 #define HDP_MMHUB_CNTL__HDP_MMHUB_GCC_MASK 0x00000002L 141 #define HDP_MMHUB_CNTL__HDP_MMHUB_SNOOP_MASK 0x00000004L 142 //HDP_EDC_CNT 143 #define HDP_EDC_CNT__MEM0_SED_COUNT__SHIFT 0x0 144 #define HDP_EDC_CNT__MEM1_SED_COUNT__SHIFT 0x2 145 #define HDP_EDC_CNT__MEM0_SED_COUNT_MASK 0x00000003L 146 #define HDP_EDC_CNT__MEM1_SED_COUNT_MASK 0x0000000CL 147 //HDP_VERSION 148 #define HDP_VERSION__MINVER__SHIFT 0x0 149 #define HDP_VERSION__MAJVER__SHIFT 0x8 150 #define HDP_VERSION__REV__SHIFT 0x10 151 #define HDP_VERSION__MINVER_MASK 0x000000FFL 152 #define HDP_VERSION__MAJVER_MASK 0x0000FF00L 153 #define HDP_VERSION__REV_MASK 0x00FF0000L 154 //HDP_CLK_CNTL 155 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT__SHIFT 0x0 156 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK__SHIFT 0x4 157 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE__SHIFT 0x1c 158 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 159 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1e 160 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 161 #define HDP_CLK_CNTL__REG_CLK_ENABLE_COUNT_MASK 0x0000000FL 162 #define HDP_CLK_CNTL__REG_WAKE_DYN_CLK_MASK 0x00000010L 163 #define HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK 0x10000000L 164 #define HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 165 #define HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK 0x40000000L 166 #define HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 167 //HDP_MEMIO_CNTL 168 #define HDP_MEMIO_CNTL__MEMIO_SEND__SHIFT 0x0 169 #define HDP_MEMIO_CNTL__MEMIO_OP__SHIFT 0x1 170 #define HDP_MEMIO_CNTL__MEMIO_BE__SHIFT 0x2 171 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE__SHIFT 0x6 172 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE__SHIFT 0x7 173 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER__SHIFT 0x8 174 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR__SHIFT 0xe 175 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR__SHIFT 0xf 176 #define HDP_MEMIO_CNTL__MEMIO_VF__SHIFT 0x10 177 #define HDP_MEMIO_CNTL__MEMIO_VFID__SHIFT 0x11 178 #define HDP_MEMIO_CNTL__MEMIO_SEND_MASK 0x00000001L 179 #define HDP_MEMIO_CNTL__MEMIO_OP_MASK 0x00000002L 180 #define HDP_MEMIO_CNTL__MEMIO_BE_MASK 0x0000003CL 181 #define HDP_MEMIO_CNTL__MEMIO_WR_STROBE_MASK 0x00000040L 182 #define HDP_MEMIO_CNTL__MEMIO_RD_STROBE_MASK 0x00000080L 183 #define HDP_MEMIO_CNTL__MEMIO_ADDR_UPPER_MASK 0x00003F00L 184 #define HDP_MEMIO_CNTL__MEMIO_CLR_WR_ERROR_MASK 0x00004000L 185 #define HDP_MEMIO_CNTL__MEMIO_CLR_RD_ERROR_MASK 0x00008000L 186 #define HDP_MEMIO_CNTL__MEMIO_VF_MASK 0x00010000L 187 #define HDP_MEMIO_CNTL__MEMIO_VFID_MASK 0x003E0000L 188 //HDP_MEMIO_ADDR 189 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER__SHIFT 0x0 190 #define HDP_MEMIO_ADDR__MEMIO_ADDR_LOWER_MASK 0xFFFFFFFFL 191 //HDP_MEMIO_STATUS 192 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS__SHIFT 0x0 193 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS__SHIFT 0x1 194 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR__SHIFT 0x2 195 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR__SHIFT 0x3 196 #define HDP_MEMIO_STATUS__MEMIO_WR_STATUS_MASK 0x00000001L 197 #define HDP_MEMIO_STATUS__MEMIO_RD_STATUS_MASK 0x00000002L 198 #define HDP_MEMIO_STATUS__MEMIO_WR_ERROR_MASK 0x00000004L 199 #define HDP_MEMIO_STATUS__MEMIO_RD_ERROR_MASK 0x00000008L 200 //HDP_MEMIO_WR_DATA 201 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA__SHIFT 0x0 202 #define HDP_MEMIO_WR_DATA__MEMIO_WR_DATA_MASK 0xFFFFFFFFL 203 //HDP_MEMIO_RD_DATA 204 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA__SHIFT 0x0 205 #define HDP_MEMIO_RD_DATA__MEMIO_RD_DATA_MASK 0xFFFFFFFFL 206 //HDP_XDP_DIRECT2HDP_FIRST 207 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED__SHIFT 0x0 208 #define HDP_XDP_DIRECT2HDP_FIRST__RESERVED_MASK 0xFFFFFFFFL 209 //HDP_XDP_D2H_FLUSH 210 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM__SHIFT 0x0 211 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA__SHIFT 0x4 212 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL__SHIFT 0x8 213 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG__SHIFT 0xb 214 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST__SHIFT 0x10 215 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM__SHIFT 0x12 216 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0__SHIFT 0x13 217 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1__SHIFT 0x14 218 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_FLUSH_NUM_MASK 0x0000000FL 219 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ENC_DATA_MASK 0x000000F0L 220 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_MBX_ADDR_SEL_MASK 0x00000700L 221 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_XPB_CLG_MASK 0x0000F800L 222 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_SEND_HOST_MASK 0x00010000L 223 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_ALTER_FLUSH_NUM_MASK 0x00040000L 224 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_0_MASK 0x00080000L 225 #define HDP_XDP_D2H_FLUSH__D2H_FLUSH_RSVD_1_MASK 0x00100000L 226 //HDP_XDP_D2H_BAR_UPDATE 227 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR__SHIFT 0x0 228 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM__SHIFT 0x10 229 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM__SHIFT 0x14 230 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_ADDR_MASK 0x0000FFFFL 231 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_FLUSH_NUM_MASK 0x000F0000L 232 #define HDP_XDP_D2H_BAR_UPDATE__D2H_BAR_UPDATE_BAR_NUM_MASK 0x00700000L 233 //HDP_XDP_D2H_RSVD_3 234 #define HDP_XDP_D2H_RSVD_3__RESERVED__SHIFT 0x0 235 #define HDP_XDP_D2H_RSVD_3__RESERVED_MASK 0xFFFFFFFFL 236 //HDP_XDP_D2H_RSVD_4 237 #define HDP_XDP_D2H_RSVD_4__RESERVED__SHIFT 0x0 238 #define HDP_XDP_D2H_RSVD_4__RESERVED_MASK 0xFFFFFFFFL 239 //HDP_XDP_D2H_RSVD_5 240 #define HDP_XDP_D2H_RSVD_5__RESERVED__SHIFT 0x0 241 #define HDP_XDP_D2H_RSVD_5__RESERVED_MASK 0xFFFFFFFFL 242 //HDP_XDP_D2H_RSVD_6 243 #define HDP_XDP_D2H_RSVD_6__RESERVED__SHIFT 0x0 244 #define HDP_XDP_D2H_RSVD_6__RESERVED_MASK 0xFFFFFFFFL 245 //HDP_XDP_D2H_RSVD_7 246 #define HDP_XDP_D2H_RSVD_7__RESERVED__SHIFT 0x0 247 #define HDP_XDP_D2H_RSVD_7__RESERVED_MASK 0xFFFFFFFFL 248 //HDP_XDP_D2H_RSVD_8 249 #define HDP_XDP_D2H_RSVD_8__RESERVED__SHIFT 0x0 250 #define HDP_XDP_D2H_RSVD_8__RESERVED_MASK 0xFFFFFFFFL 251 //HDP_XDP_D2H_RSVD_9 252 #define HDP_XDP_D2H_RSVD_9__RESERVED__SHIFT 0x0 253 #define HDP_XDP_D2H_RSVD_9__RESERVED_MASK 0xFFFFFFFFL 254 //HDP_XDP_D2H_RSVD_10 255 #define HDP_XDP_D2H_RSVD_10__RESERVED__SHIFT 0x0 256 #define HDP_XDP_D2H_RSVD_10__RESERVED_MASK 0xFFFFFFFFL 257 //HDP_XDP_D2H_RSVD_11 258 #define HDP_XDP_D2H_RSVD_11__RESERVED__SHIFT 0x0 259 #define HDP_XDP_D2H_RSVD_11__RESERVED_MASK 0xFFFFFFFFL 260 //HDP_XDP_D2H_RSVD_12 261 #define HDP_XDP_D2H_RSVD_12__RESERVED__SHIFT 0x0 262 #define HDP_XDP_D2H_RSVD_12__RESERVED_MASK 0xFFFFFFFFL 263 //HDP_XDP_D2H_RSVD_13 264 #define HDP_XDP_D2H_RSVD_13__RESERVED__SHIFT 0x0 265 #define HDP_XDP_D2H_RSVD_13__RESERVED_MASK 0xFFFFFFFFL 266 //HDP_XDP_D2H_RSVD_14 267 #define HDP_XDP_D2H_RSVD_14__RESERVED__SHIFT 0x0 268 #define HDP_XDP_D2H_RSVD_14__RESERVED_MASK 0xFFFFFFFFL 269 //HDP_XDP_D2H_RSVD_15 270 #define HDP_XDP_D2H_RSVD_15__RESERVED__SHIFT 0x0 271 #define HDP_XDP_D2H_RSVD_15__RESERVED_MASK 0xFFFFFFFFL 272 //HDP_XDP_D2H_RSVD_16 273 #define HDP_XDP_D2H_RSVD_16__RESERVED__SHIFT 0x0 274 #define HDP_XDP_D2H_RSVD_16__RESERVED_MASK 0xFFFFFFFFL 275 //HDP_XDP_D2H_RSVD_17 276 #define HDP_XDP_D2H_RSVD_17__RESERVED__SHIFT 0x0 277 #define HDP_XDP_D2H_RSVD_17__RESERVED_MASK 0xFFFFFFFFL 278 //HDP_XDP_D2H_RSVD_18 279 #define HDP_XDP_D2H_RSVD_18__RESERVED__SHIFT 0x0 280 #define HDP_XDP_D2H_RSVD_18__RESERVED_MASK 0xFFFFFFFFL 281 //HDP_XDP_D2H_RSVD_19 282 #define HDP_XDP_D2H_RSVD_19__RESERVED__SHIFT 0x0 283 #define HDP_XDP_D2H_RSVD_19__RESERVED_MASK 0xFFFFFFFFL 284 //HDP_XDP_D2H_RSVD_20 285 #define HDP_XDP_D2H_RSVD_20__RESERVED__SHIFT 0x0 286 #define HDP_XDP_D2H_RSVD_20__RESERVED_MASK 0xFFFFFFFFL 287 //HDP_XDP_D2H_RSVD_21 288 #define HDP_XDP_D2H_RSVD_21__RESERVED__SHIFT 0x0 289 #define HDP_XDP_D2H_RSVD_21__RESERVED_MASK 0xFFFFFFFFL 290 //HDP_XDP_D2H_RSVD_22 291 #define HDP_XDP_D2H_RSVD_22__RESERVED__SHIFT 0x0 292 #define HDP_XDP_D2H_RSVD_22__RESERVED_MASK 0xFFFFFFFFL 293 //HDP_XDP_D2H_RSVD_23 294 #define HDP_XDP_D2H_RSVD_23__RESERVED__SHIFT 0x0 295 #define HDP_XDP_D2H_RSVD_23__RESERVED_MASK 0xFFFFFFFFL 296 //HDP_XDP_D2H_RSVD_24 297 #define HDP_XDP_D2H_RSVD_24__RESERVED__SHIFT 0x0 298 #define HDP_XDP_D2H_RSVD_24__RESERVED_MASK 0xFFFFFFFFL 299 //HDP_XDP_D2H_RSVD_25 300 #define HDP_XDP_D2H_RSVD_25__RESERVED__SHIFT 0x0 301 #define HDP_XDP_D2H_RSVD_25__RESERVED_MASK 0xFFFFFFFFL 302 //HDP_XDP_D2H_RSVD_26 303 #define HDP_XDP_D2H_RSVD_26__RESERVED__SHIFT 0x0 304 #define HDP_XDP_D2H_RSVD_26__RESERVED_MASK 0xFFFFFFFFL 305 //HDP_XDP_D2H_RSVD_27 306 #define HDP_XDP_D2H_RSVD_27__RESERVED__SHIFT 0x0 307 #define HDP_XDP_D2H_RSVD_27__RESERVED_MASK 0xFFFFFFFFL 308 //HDP_XDP_D2H_RSVD_28 309 #define HDP_XDP_D2H_RSVD_28__RESERVED__SHIFT 0x0 310 #define HDP_XDP_D2H_RSVD_28__RESERVED_MASK 0xFFFFFFFFL 311 //HDP_XDP_D2H_RSVD_29 312 #define HDP_XDP_D2H_RSVD_29__RESERVED__SHIFT 0x0 313 #define HDP_XDP_D2H_RSVD_29__RESERVED_MASK 0xFFFFFFFFL 314 //HDP_XDP_D2H_RSVD_30 315 #define HDP_XDP_D2H_RSVD_30__RESERVED__SHIFT 0x0 316 #define HDP_XDP_D2H_RSVD_30__RESERVED_MASK 0xFFFFFFFFL 317 //HDP_XDP_D2H_RSVD_31 318 #define HDP_XDP_D2H_RSVD_31__RESERVED__SHIFT 0x0 319 #define HDP_XDP_D2H_RSVD_31__RESERVED_MASK 0xFFFFFFFFL 320 //HDP_XDP_D2H_RSVD_32 321 #define HDP_XDP_D2H_RSVD_32__RESERVED__SHIFT 0x0 322 #define HDP_XDP_D2H_RSVD_32__RESERVED_MASK 0xFFFFFFFFL 323 //HDP_XDP_D2H_RSVD_33 324 #define HDP_XDP_D2H_RSVD_33__RESERVED__SHIFT 0x0 325 #define HDP_XDP_D2H_RSVD_33__RESERVED_MASK 0xFFFFFFFFL 326 //HDP_XDP_D2H_RSVD_34 327 #define HDP_XDP_D2H_RSVD_34__RESERVED__SHIFT 0x0 328 #define HDP_XDP_D2H_RSVD_34__RESERVED_MASK 0xFFFFFFFFL 329 //HDP_XDP_DIRECT2HDP_LAST 330 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED__SHIFT 0x0 331 #define HDP_XDP_DIRECT2HDP_LAST__RESERVED_MASK 0xFFFFFFFFL 332 //HDP_XDP_P2P_BAR_CFG 333 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE__SHIFT 0x0 334 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM__SHIFT 0x4 335 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_ADDR_SIZE_MASK 0x0000000FL 336 #define HDP_XDP_P2P_BAR_CFG__P2P_BAR_CFG_BAR_FROM_MASK 0x00000030L 337 //HDP_XDP_P2P_MBX_OFFSET 338 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET__SHIFT 0x0 339 #define HDP_XDP_P2P_MBX_OFFSET__P2P_MBX_OFFSET_MASK 0x0001FFFFL 340 //HDP_XDP_P2P_MBX_ADDR0 341 #define HDP_XDP_P2P_MBX_ADDR0__VALID__SHIFT 0x0 342 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19__SHIFT 0x3 343 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36__SHIFT 0x14 344 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40__SHIFT 0x18 345 #define HDP_XDP_P2P_MBX_ADDR0__VALID_MASK 0x00000001L 346 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_35_19_MASK 0x000FFFF8L 347 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_39_36_MASK 0x00F00000L 348 #define HDP_XDP_P2P_MBX_ADDR0__ADDR_47_40_MASK 0xFF000000L 349 //HDP_XDP_P2P_MBX_ADDR1 350 #define HDP_XDP_P2P_MBX_ADDR1__VALID__SHIFT 0x0 351 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19__SHIFT 0x3 352 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36__SHIFT 0x14 353 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40__SHIFT 0x18 354 #define HDP_XDP_P2P_MBX_ADDR1__VALID_MASK 0x00000001L 355 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_35_19_MASK 0x000FFFF8L 356 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_39_36_MASK 0x00F00000L 357 #define HDP_XDP_P2P_MBX_ADDR1__ADDR_47_40_MASK 0xFF000000L 358 //HDP_XDP_P2P_MBX_ADDR2 359 #define HDP_XDP_P2P_MBX_ADDR2__VALID__SHIFT 0x0 360 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19__SHIFT 0x3 361 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36__SHIFT 0x14 362 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40__SHIFT 0x18 363 #define HDP_XDP_P2P_MBX_ADDR2__VALID_MASK 0x00000001L 364 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_35_19_MASK 0x000FFFF8L 365 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_39_36_MASK 0x00F00000L 366 #define HDP_XDP_P2P_MBX_ADDR2__ADDR_47_40_MASK 0xFF000000L 367 //HDP_XDP_P2P_MBX_ADDR3 368 #define HDP_XDP_P2P_MBX_ADDR3__VALID__SHIFT 0x0 369 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19__SHIFT 0x3 370 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36__SHIFT 0x14 371 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40__SHIFT 0x18 372 #define HDP_XDP_P2P_MBX_ADDR3__VALID_MASK 0x00000001L 373 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_35_19_MASK 0x000FFFF8L 374 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_39_36_MASK 0x00F00000L 375 #define HDP_XDP_P2P_MBX_ADDR3__ADDR_47_40_MASK 0xFF000000L 376 //HDP_XDP_P2P_MBX_ADDR4 377 #define HDP_XDP_P2P_MBX_ADDR4__VALID__SHIFT 0x0 378 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19__SHIFT 0x3 379 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36__SHIFT 0x14 380 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40__SHIFT 0x18 381 #define HDP_XDP_P2P_MBX_ADDR4__VALID_MASK 0x00000001L 382 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_35_19_MASK 0x000FFFF8L 383 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_39_36_MASK 0x00F00000L 384 #define HDP_XDP_P2P_MBX_ADDR4__ADDR_47_40_MASK 0xFF000000L 385 //HDP_XDP_P2P_MBX_ADDR5 386 #define HDP_XDP_P2P_MBX_ADDR5__VALID__SHIFT 0x0 387 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19__SHIFT 0x3 388 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36__SHIFT 0x14 389 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40__SHIFT 0x18 390 #define HDP_XDP_P2P_MBX_ADDR5__VALID_MASK 0x00000001L 391 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_35_19_MASK 0x000FFFF8L 392 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_39_36_MASK 0x00F00000L 393 #define HDP_XDP_P2P_MBX_ADDR5__ADDR_47_40_MASK 0xFF000000L 394 //HDP_XDP_P2P_MBX_ADDR6 395 #define HDP_XDP_P2P_MBX_ADDR6__VALID__SHIFT 0x0 396 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19__SHIFT 0x3 397 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36__SHIFT 0x14 398 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40__SHIFT 0x18 399 #define HDP_XDP_P2P_MBX_ADDR6__VALID_MASK 0x00000001L 400 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_35_19_MASK 0x000FFFF8L 401 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_39_36_MASK 0x00F00000L 402 #define HDP_XDP_P2P_MBX_ADDR6__ADDR_47_40_MASK 0xFF000000L 403 //HDP_XDP_HDP_MBX_MC_CFG 404 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS__SHIFT 0x0 405 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP__SHIFT 0x4 406 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID__SHIFT 0x8 407 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO__SHIFT 0xc 408 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC__SHIFT 0xd 409 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP__SHIFT 0xe 410 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_QOS_MASK 0x0000000FL 411 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SWAP_MASK 0x00000030L 412 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_VMID_MASK 0x00000F00L 413 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_RO_MASK 0x00001000L 414 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_GCC_MASK 0x00002000L 415 #define HDP_XDP_HDP_MBX_MC_CFG__HDP_MBX_MC_CFG_TAP_WRREQ_SNOOP_MASK 0x00004000L 416 //HDP_XDP_HDP_MC_CFG 417 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP__SHIFT 0x3 418 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP__SHIFT 0x4 419 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID__SHIFT 0x8 420 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO__SHIFT 0xc 421 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC__SHIFT 0xd 422 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH__SHIFT 0xe 423 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SNOOP_MASK 0x00000008L 424 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_SWAP_MASK 0x00000030L 425 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_VMID_MASK 0x00000F00L 426 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_RO_MASK 0x00001000L 427 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_HST_TAP_REQ_GCC_MASK 0x00002000L 428 #define HDP_XDP_HDP_MC_CFG__HDP_MC_CFG_XDP_HIGHER_PRI_THRESH_MASK 0x000FC000L 429 //HDP_XDP_HST_CFG 430 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN__SHIFT 0x0 431 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER__SHIFT 0x1 432 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN__SHIFT 0x3 433 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN__SHIFT 0x4 434 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG__SHIFT 0x5 435 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_EN_MASK 0x00000001L 436 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_MASK 0x00000006L 437 #define HDP_XDP_HST_CFG__HST_CFG_WR_BURST_EN_MASK 0x00000008L 438 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_64B_EN_MASK 0x00000010L 439 #define HDP_XDP_HST_CFG__HST_CFG_WR_COMBINE_TIMER_PRELOAD_CFG_MASK 0x00000020L 440 //HDP_XDP_HDP_IPH_CFG 441 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE__SHIFT 0x0 442 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE__SHIFT 0x6 443 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING__SHIFT 0xc 444 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN__SHIFT 0xd 445 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_SYS_FIFO_DEPTH_OVERRIDE_MASK 0x0000003FL 446 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_XDP_FIFO_DEPTH_OVERRIDE_MASK 0x00000FC0L 447 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_INVERSE_PEER_TAG_MATCHING_MASK 0x00001000L 448 #define HDP_XDP_HDP_IPH_CFG__HDP_IPH_CFG_P2P_RD_EN_MASK 0x00002000L 449 //HDP_XDP_P2P_BAR0 450 #define HDP_XDP_P2P_BAR0__ADDR__SHIFT 0x0 451 #define HDP_XDP_P2P_BAR0__FLUSH__SHIFT 0x10 452 #define HDP_XDP_P2P_BAR0__VALID__SHIFT 0x14 453 #define HDP_XDP_P2P_BAR0__ADDR_MASK 0x0000FFFFL 454 #define HDP_XDP_P2P_BAR0__FLUSH_MASK 0x000F0000L 455 #define HDP_XDP_P2P_BAR0__VALID_MASK 0x00100000L 456 //HDP_XDP_P2P_BAR1 457 #define HDP_XDP_P2P_BAR1__ADDR__SHIFT 0x0 458 #define HDP_XDP_P2P_BAR1__FLUSH__SHIFT 0x10 459 #define HDP_XDP_P2P_BAR1__VALID__SHIFT 0x14 460 #define HDP_XDP_P2P_BAR1__ADDR_MASK 0x0000FFFFL 461 #define HDP_XDP_P2P_BAR1__FLUSH_MASK 0x000F0000L 462 #define HDP_XDP_P2P_BAR1__VALID_MASK 0x00100000L 463 //HDP_XDP_P2P_BAR2 464 #define HDP_XDP_P2P_BAR2__ADDR__SHIFT 0x0 465 #define HDP_XDP_P2P_BAR2__FLUSH__SHIFT 0x10 466 #define HDP_XDP_P2P_BAR2__VALID__SHIFT 0x14 467 #define HDP_XDP_P2P_BAR2__ADDR_MASK 0x0000FFFFL 468 #define HDP_XDP_P2P_BAR2__FLUSH_MASK 0x000F0000L 469 #define HDP_XDP_P2P_BAR2__VALID_MASK 0x00100000L 470 //HDP_XDP_P2P_BAR3 471 #define HDP_XDP_P2P_BAR3__ADDR__SHIFT 0x0 472 #define HDP_XDP_P2P_BAR3__FLUSH__SHIFT 0x10 473 #define HDP_XDP_P2P_BAR3__VALID__SHIFT 0x14 474 #define HDP_XDP_P2P_BAR3__ADDR_MASK 0x0000FFFFL 475 #define HDP_XDP_P2P_BAR3__FLUSH_MASK 0x000F0000L 476 #define HDP_XDP_P2P_BAR3__VALID_MASK 0x00100000L 477 //HDP_XDP_P2P_BAR4 478 #define HDP_XDP_P2P_BAR4__ADDR__SHIFT 0x0 479 #define HDP_XDP_P2P_BAR4__FLUSH__SHIFT 0x10 480 #define HDP_XDP_P2P_BAR4__VALID__SHIFT 0x14 481 #define HDP_XDP_P2P_BAR4__ADDR_MASK 0x0000FFFFL 482 #define HDP_XDP_P2P_BAR4__FLUSH_MASK 0x000F0000L 483 #define HDP_XDP_P2P_BAR4__VALID_MASK 0x00100000L 484 //HDP_XDP_P2P_BAR5 485 #define HDP_XDP_P2P_BAR5__ADDR__SHIFT 0x0 486 #define HDP_XDP_P2P_BAR5__FLUSH__SHIFT 0x10 487 #define HDP_XDP_P2P_BAR5__VALID__SHIFT 0x14 488 #define HDP_XDP_P2P_BAR5__ADDR_MASK 0x0000FFFFL 489 #define HDP_XDP_P2P_BAR5__FLUSH_MASK 0x000F0000L 490 #define HDP_XDP_P2P_BAR5__VALID_MASK 0x00100000L 491 //HDP_XDP_P2P_BAR6 492 #define HDP_XDP_P2P_BAR6__ADDR__SHIFT 0x0 493 #define HDP_XDP_P2P_BAR6__FLUSH__SHIFT 0x10 494 #define HDP_XDP_P2P_BAR6__VALID__SHIFT 0x14 495 #define HDP_XDP_P2P_BAR6__ADDR_MASK 0x0000FFFFL 496 #define HDP_XDP_P2P_BAR6__FLUSH_MASK 0x000F0000L 497 #define HDP_XDP_P2P_BAR6__VALID_MASK 0x00100000L 498 //HDP_XDP_P2P_BAR7 499 #define HDP_XDP_P2P_BAR7__ADDR__SHIFT 0x0 500 #define HDP_XDP_P2P_BAR7__FLUSH__SHIFT 0x10 501 #define HDP_XDP_P2P_BAR7__VALID__SHIFT 0x14 502 #define HDP_XDP_P2P_BAR7__ADDR_MASK 0x0000FFFFL 503 #define HDP_XDP_P2P_BAR7__FLUSH_MASK 0x000F0000L 504 #define HDP_XDP_P2P_BAR7__VALID_MASK 0x00100000L 505 //HDP_XDP_FLUSH_ARMED_STS 506 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS__SHIFT 0x0 507 #define HDP_XDP_FLUSH_ARMED_STS__FLUSH_ARMED_STS_MASK 0xFFFFFFFFL 508 //HDP_XDP_FLUSH_CNTR0_STS 509 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS__SHIFT 0x0 510 #define HDP_XDP_FLUSH_CNTR0_STS__FLUSH_CNTR0_STS_MASK 0x03FFFFFFL 511 //HDP_XDP_BUSY_STS 512 #define HDP_XDP_BUSY_STS__BUSY_BITS__SHIFT 0x0 513 #define HDP_XDP_BUSY_STS__BUSY_BITS_MASK 0x0003FFFFL 514 //HDP_XDP_STICKY 515 #define HDP_XDP_STICKY__STICKY_STS__SHIFT 0x0 516 #define HDP_XDP_STICKY__STICKY_W1C__SHIFT 0x10 517 #define HDP_XDP_STICKY__STICKY_STS_MASK 0x0000FFFFL 518 #define HDP_XDP_STICKY__STICKY_W1C_MASK 0xFFFF0000L 519 //HDP_XDP_CHKN 520 #define HDP_XDP_CHKN__CHKN_0_RSVD__SHIFT 0x0 521 #define HDP_XDP_CHKN__CHKN_1_RSVD__SHIFT 0x8 522 #define HDP_XDP_CHKN__CHKN_2_RSVD__SHIFT 0x10 523 #define HDP_XDP_CHKN__CHKN_3_RSVD__SHIFT 0x18 524 #define HDP_XDP_CHKN__CHKN_0_RSVD_MASK 0x000000FFL 525 #define HDP_XDP_CHKN__CHKN_1_RSVD_MASK 0x0000FF00L 526 #define HDP_XDP_CHKN__CHKN_2_RSVD_MASK 0x00FF0000L 527 #define HDP_XDP_CHKN__CHKN_3_RSVD_MASK 0xFF000000L 528 //HDP_XDP_BARS_ADDR_39_36 529 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36__SHIFT 0x0 530 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36__SHIFT 0x4 531 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36__SHIFT 0x8 532 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36__SHIFT 0xc 533 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36__SHIFT 0x10 534 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36__SHIFT 0x14 535 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36__SHIFT 0x18 536 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36__SHIFT 0x1c 537 #define HDP_XDP_BARS_ADDR_39_36__BAR0_ADDR_39_36_MASK 0x0000000FL 538 #define HDP_XDP_BARS_ADDR_39_36__BAR1_ADDR_39_36_MASK 0x000000F0L 539 #define HDP_XDP_BARS_ADDR_39_36__BAR2_ADDR_39_36_MASK 0x00000F00L 540 #define HDP_XDP_BARS_ADDR_39_36__BAR3_ADDR_39_36_MASK 0x0000F000L 541 #define HDP_XDP_BARS_ADDR_39_36__BAR4_ADDR_39_36_MASK 0x000F0000L 542 #define HDP_XDP_BARS_ADDR_39_36__BAR5_ADDR_39_36_MASK 0x00F00000L 543 #define HDP_XDP_BARS_ADDR_39_36__BAR6_ADDR_39_36_MASK 0x0F000000L 544 #define HDP_XDP_BARS_ADDR_39_36__BAR7_ADDR_39_36_MASK 0xF0000000L 545 //HDP_XDP_MC_VM_FB_LOCATION_BASE 546 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 547 #define HDP_XDP_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x03FFFFFFL 548 //HDP_XDP_GPU_IOV_VIOLATION_LOG 549 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 550 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 551 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 552 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 553 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 554 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 555 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 556 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 557 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 558 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 559 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 560 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 561 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 562 #define HDP_XDP_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 563 //HDP_XDP_MMHUB_ERROR 564 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01__SHIFT 0x1 565 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10__SHIFT 0x2 566 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11__SHIFT 0x3 567 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01__SHIFT 0x5 568 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10__SHIFT 0x6 569 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11__SHIFT 0x7 570 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01__SHIFT 0x9 571 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10__SHIFT 0xa 572 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11__SHIFT 0xb 573 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01__SHIFT 0xd 574 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10__SHIFT 0xe 575 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11__SHIFT 0xf 576 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01__SHIFT 0x11 577 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10__SHIFT 0x12 578 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11__SHIFT 0x13 579 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01__SHIFT 0x15 580 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10__SHIFT 0x16 581 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11__SHIFT 0x17 582 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_01_MASK 0x00000002L 583 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_10_MASK 0x00000004L 584 #define HDP_XDP_MMHUB_ERROR__HDP_BRESP_11_MASK 0x00000008L 585 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_01_MASK 0x00000020L 586 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_10_MASK 0x00000040L 587 #define HDP_XDP_MMHUB_ERROR__HDP_BUSER_NACK_11_MASK 0x00000080L 588 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_01_MASK 0x00000200L 589 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_10_MASK 0x00000400L 590 #define HDP_XDP_MMHUB_ERROR__HDP_RRESP_11_MASK 0x00000800L 591 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_01_MASK 0x00002000L 592 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_10_MASK 0x00004000L 593 #define HDP_XDP_MMHUB_ERROR__HDP_RUSER_NACK_11_MASK 0x00008000L 594 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_01_MASK 0x00020000L 595 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_10_MASK 0x00040000L 596 #define HDP_XDP_MMHUB_ERROR__XDP_BRESP_11_MASK 0x00080000L 597 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_01_MASK 0x00200000L 598 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_10_MASK 0x00400000L 599 #define HDP_XDP_MMHUB_ERROR__XDP_BUSER_NACK_11_MASK 0x00800000L 600 601 #endif 602