1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _mmhub_9_3_0_SH_MASK_HEADER 22 #define _mmhub_9_3_0_SH_MASK_HEADER 23 24 25 // addressBlock: mmhub_dagbdec 26 //DAGB0_RDCLI0 27 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 28 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 30 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 31 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 33 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 35 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 37 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 38 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 39 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 40 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 41 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 42 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 43 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 44 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 45 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 46 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 47 //DAGB0_RDCLI1 48 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 49 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 50 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 51 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 52 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 53 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 54 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 55 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 56 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 57 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 58 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 59 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 60 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 61 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 62 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 63 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 64 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 65 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 66 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 67 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 68 //DAGB0_RDCLI2 69 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 70 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 71 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 72 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 73 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 74 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 75 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 76 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 77 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 78 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 79 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 80 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 81 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 82 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 83 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 84 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 85 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 86 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 87 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 88 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 89 //DAGB0_RDCLI3 90 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 91 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 92 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 93 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 94 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 95 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 96 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 97 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 98 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 99 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 100 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 101 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 102 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 103 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 104 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 105 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 106 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 107 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 108 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 109 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 110 //DAGB0_RDCLI4 111 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 112 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 113 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 114 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 115 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 116 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 117 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 118 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 119 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 120 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 121 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 122 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 123 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 124 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 125 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 126 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 127 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 128 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 129 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 130 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 131 //DAGB0_RDCLI5 132 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 133 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 134 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 135 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 136 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 137 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 138 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 139 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 140 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 141 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 142 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 143 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 144 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 145 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 146 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 147 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 148 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 149 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 150 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 151 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 152 //DAGB0_RDCLI6 153 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 154 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 155 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 156 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 157 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 158 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 159 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 160 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 161 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 162 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 163 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 164 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 165 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 166 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 167 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 168 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 169 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 170 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 171 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 172 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 173 //DAGB0_RDCLI7 174 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 175 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 176 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 177 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 178 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 179 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 180 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 181 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 182 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 183 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 184 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 185 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 186 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 187 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 188 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 189 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 190 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 191 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 192 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 193 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 194 //DAGB0_RDCLI8 195 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 196 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 197 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 198 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 199 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 200 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 201 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 202 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 203 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 204 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 205 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 206 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 207 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 208 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 209 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 210 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 211 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 212 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 213 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 214 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 215 //DAGB0_RDCLI9 216 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 217 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 218 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 219 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 220 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 221 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 222 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 223 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 224 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 225 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 226 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 227 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 228 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 229 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 230 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 231 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 232 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 233 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 234 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 235 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 236 //DAGB0_RDCLI10 237 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 238 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 239 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 240 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 241 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 242 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 243 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 244 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 245 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 246 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 247 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 248 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 249 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 250 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 251 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 252 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 253 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 254 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 255 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 256 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 257 //DAGB0_RDCLI11 258 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 259 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 260 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 261 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 262 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 263 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 264 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 265 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 266 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 267 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 268 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 269 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 270 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 271 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 272 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 273 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 274 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 275 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 276 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 277 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 278 //DAGB0_RDCLI12 279 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 280 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 281 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 282 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 283 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 284 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 285 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 286 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 287 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 288 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 289 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 290 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 291 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 292 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 293 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 294 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 295 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 296 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 297 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 298 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 299 //DAGB0_RDCLI13 300 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 301 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 302 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 303 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 304 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 305 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 306 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 307 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 308 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 309 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 310 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 311 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 312 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 313 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 314 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 315 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 316 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 317 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 318 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 319 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 320 //DAGB0_RDCLI14 321 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 322 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 323 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 324 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 325 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 326 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 327 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 328 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 329 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 330 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 331 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 332 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 333 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 334 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 335 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 336 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 337 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 338 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 339 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 340 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 341 //DAGB0_RDCLI15 342 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 343 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 344 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 345 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 346 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 347 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 348 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 349 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 350 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 351 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 352 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 353 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 354 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 355 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 356 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 357 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 358 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 359 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 360 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 361 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 362 //DAGB0_RD_CNTL 363 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 364 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 365 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 366 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 367 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 368 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 369 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 370 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 371 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 372 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 373 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 374 #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 375 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 376 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 377 //DAGB0_RD_GMI_CNTL 378 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 379 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 380 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 381 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 382 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 383 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 384 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 385 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 386 //DAGB0_RD_ADDR_DAGB 387 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 388 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 389 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 390 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 391 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 392 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 393 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 394 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 395 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 396 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 397 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 398 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 399 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 400 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 401 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 402 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 403 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 404 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 405 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 406 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 407 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 408 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 409 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 410 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 411 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 412 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 413 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 414 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 415 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 416 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 417 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 418 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 419 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 420 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 421 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 422 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 423 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 424 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 425 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 426 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 427 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 428 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 429 //DAGB0_RD_CGTT_CLK_CTRL 430 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 431 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 432 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 433 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 434 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 435 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 436 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 437 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 438 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 439 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 440 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 441 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 442 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 443 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 444 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 445 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 446 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 447 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 448 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 449 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 450 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 451 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 452 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 453 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 454 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 455 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 456 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 457 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 458 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 459 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 460 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 461 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 462 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 463 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 464 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 465 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 466 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 467 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 468 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 469 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 470 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 471 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 472 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 473 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 474 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 475 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 476 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 477 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 478 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 479 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 480 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 481 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 482 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 483 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 484 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 485 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 486 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 487 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 488 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 489 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 490 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 491 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 492 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 493 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 494 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 495 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 496 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 497 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 498 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 499 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 500 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 501 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 502 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 503 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 504 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 505 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 506 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 507 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 508 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 509 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 510 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 511 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 512 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 513 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 514 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 515 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 516 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 517 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 518 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 519 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 520 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 521 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 522 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 523 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 524 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 525 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 526 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 527 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 528 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 529 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 530 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 531 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 532 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 533 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 534 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 535 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 536 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 537 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 538 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 539 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 540 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 541 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 542 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 543 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 544 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 545 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 546 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 547 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 548 //DAGB0_RD_VC0_CNTL 549 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 550 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 551 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 552 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 553 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 554 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 555 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 556 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 557 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 558 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 559 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 560 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 561 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 562 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 563 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 564 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 565 //DAGB0_RD_VC1_CNTL 566 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 567 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 568 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 569 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 570 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 571 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 572 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 573 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 574 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 575 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 576 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 577 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 578 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 579 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 580 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 581 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 582 //DAGB0_RD_VC2_CNTL 583 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 584 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 585 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 586 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 587 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 588 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 589 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 590 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 591 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 592 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 593 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 594 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 595 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 596 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 597 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 598 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 599 //DAGB0_RD_VC3_CNTL 600 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 601 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 602 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 603 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 604 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 605 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 606 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 607 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 608 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 609 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 610 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 611 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 612 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 613 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 614 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 615 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 616 //DAGB0_RD_VC4_CNTL 617 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 618 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 619 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 620 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 621 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 622 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 623 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 624 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 625 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 626 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 627 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 628 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 629 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 630 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 631 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 632 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 633 //DAGB0_RD_VC5_CNTL 634 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 635 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 636 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 637 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 638 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 639 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 640 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 641 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 642 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 643 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 644 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 645 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 646 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 647 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 648 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 649 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 650 //DAGB0_RD_VC6_CNTL 651 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 652 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 653 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 654 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 655 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 656 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 657 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 658 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 659 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 660 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 661 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 662 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 663 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 664 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 665 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 666 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 667 //DAGB0_RD_VC7_CNTL 668 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 669 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 670 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 671 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 672 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 673 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 674 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 675 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 676 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 677 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 678 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 679 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 680 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 681 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 682 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 683 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 684 //DAGB0_RD_CNTL_MISC 685 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 686 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 687 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 688 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 689 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 690 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 691 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 692 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 693 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 694 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 695 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 696 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 697 //DAGB0_RD_TLB_CREDIT 698 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 699 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 700 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 701 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 702 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 703 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 704 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 705 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 706 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 707 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 708 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 709 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 710 //DAGB0_RDCLI_ASK_PENDING 711 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 712 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 713 //DAGB0_RDCLI_GO_PENDING 714 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 715 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 716 //DAGB0_RDCLI_GBLSEND_PENDING 717 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 718 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 719 //DAGB0_RDCLI_TLB_PENDING 720 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 721 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 722 //DAGB0_RDCLI_OARB_PENDING 723 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 724 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 725 //DAGB0_RDCLI_OSD_PENDING 726 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 727 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 728 //DAGB0_WRCLI0 729 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 730 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 731 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 732 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 733 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 734 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 735 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 736 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 737 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 738 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 739 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 740 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 741 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 742 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 743 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 744 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 745 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 746 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 747 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 748 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 749 //DAGB0_WRCLI1 750 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 751 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 752 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 753 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 754 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 755 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 756 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 757 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 758 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 759 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 760 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 761 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 762 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 763 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 764 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 765 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 766 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 767 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 768 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 769 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 770 //DAGB0_WRCLI2 771 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 772 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 773 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 774 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 775 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 776 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 777 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 778 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 779 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 780 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 781 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 782 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 783 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 784 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 785 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 786 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 787 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 788 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 789 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 790 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 791 //DAGB0_WRCLI3 792 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 793 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 794 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 795 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 796 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 797 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 798 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 799 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 800 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 801 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 802 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 803 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 804 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 805 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 806 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 807 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 808 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 809 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 810 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 811 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 812 //DAGB0_WRCLI4 813 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 814 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 815 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 816 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 817 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 818 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 819 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 820 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 821 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 822 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 823 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 824 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 825 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 826 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 827 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 828 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 829 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 830 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 831 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 832 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 833 //DAGB0_WRCLI5 834 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 835 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 836 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 837 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 838 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 839 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 840 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 841 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 842 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 843 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 844 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 845 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 846 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 847 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 848 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 849 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 850 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 851 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 852 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 853 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 854 //DAGB0_WRCLI6 855 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 856 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 857 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 858 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 859 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 860 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 861 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 862 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 863 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 864 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 865 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 866 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 867 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 868 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 869 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 870 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 871 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 872 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 873 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 874 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 875 //DAGB0_WRCLI7 876 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 877 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 878 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 879 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 880 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 881 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 882 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 883 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 884 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 885 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 886 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 887 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 888 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 889 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 890 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 891 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 892 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 893 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 894 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 895 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 896 //DAGB0_WRCLI8 897 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 898 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 899 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 900 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 901 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 902 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 903 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 904 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 905 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 906 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 907 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 908 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 909 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 910 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 911 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 912 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 913 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 914 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 915 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 916 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 917 //DAGB0_WRCLI9 918 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 919 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 920 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 921 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 922 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 923 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 924 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 925 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 926 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 927 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 928 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 929 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 930 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 931 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 932 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 933 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 934 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 935 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 936 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 937 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 938 //DAGB0_WRCLI10 939 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 940 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 941 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 942 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 943 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 944 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 945 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 946 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 947 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 948 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 949 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 950 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 951 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 952 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 953 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 954 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 955 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 956 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 957 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 958 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 959 //DAGB0_WRCLI11 960 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 961 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 962 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 963 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 964 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 965 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 966 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 967 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 968 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 969 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 970 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 971 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 972 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 973 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 974 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 975 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 976 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 977 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 978 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 979 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 980 //DAGB0_WRCLI12 981 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 982 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 983 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 984 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 985 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 986 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 987 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 988 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 989 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 990 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 991 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 992 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 993 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 994 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 995 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 996 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 997 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 998 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 999 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1000 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1001 //DAGB0_WRCLI13 1002 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1003 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1004 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1005 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1006 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1007 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1008 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1009 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1010 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1011 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1012 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1013 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1014 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1015 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1016 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1017 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1018 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1019 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1020 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1021 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1022 //DAGB0_WRCLI14 1023 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1024 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1025 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1026 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1027 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1028 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1029 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1030 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1031 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1032 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1033 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1034 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1035 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1036 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1037 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1038 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1039 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1040 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1041 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1042 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1043 //DAGB0_WRCLI15 1044 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1045 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1046 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1047 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1048 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1049 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1050 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1051 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1052 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1053 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1054 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1055 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1056 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1057 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1058 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1059 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1060 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1061 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1062 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1063 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1064 //DAGB0_WR_CNTL 1065 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1066 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1067 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1068 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1069 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1070 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1071 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1072 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1073 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1074 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1075 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1076 #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1077 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1078 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1079 //DAGB0_WR_GMI_CNTL 1080 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1081 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1082 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1083 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1084 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1085 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1086 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1087 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1088 //DAGB0_WR_ADDR_DAGB 1089 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1090 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1091 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1092 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1093 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1094 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1095 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1096 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1097 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1098 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1099 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1100 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1101 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1102 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1103 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1104 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1105 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1106 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1107 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1108 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1109 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1110 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1111 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1112 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1113 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1114 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1115 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1116 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1117 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1118 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1119 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1120 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1121 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1122 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1123 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1124 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1125 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1126 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1127 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1128 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1129 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1130 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1131 //DAGB0_WR_CGTT_CLK_CTRL 1132 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1133 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1134 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1135 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1136 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1137 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1138 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1139 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1140 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1141 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1142 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1143 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1144 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1145 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1146 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1147 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1148 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1149 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1150 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1151 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1152 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1153 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1154 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1155 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1156 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1157 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1158 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1159 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1160 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1161 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1162 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1163 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1164 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1165 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1166 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1167 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1168 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1169 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1170 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1171 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1172 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1173 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1174 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1175 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1176 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1177 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1178 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1179 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1180 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1181 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1182 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1183 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1184 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1185 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1186 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1187 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1188 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1189 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1190 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1191 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1192 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1193 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1194 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1195 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1196 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1197 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1198 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1199 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1200 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1201 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1202 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1203 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1204 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1205 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1206 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1207 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1208 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1209 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1210 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1211 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1212 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1213 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1214 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1215 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1216 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1217 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1218 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1219 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1220 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1221 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1222 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1223 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1224 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1225 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1226 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1227 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1228 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1229 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1230 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1231 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1232 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1233 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1234 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1235 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1236 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1237 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1238 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1239 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1240 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1241 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1242 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1243 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1244 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1245 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1246 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1247 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1248 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1249 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1250 //DAGB0_WR_DATA_DAGB 1251 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1252 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1253 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1254 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1255 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1256 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1257 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1258 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1259 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1260 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1261 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1262 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1263 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1264 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1265 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1266 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1267 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1268 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1269 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1270 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1271 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1272 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1273 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1274 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1275 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1276 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1277 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1278 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1279 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1280 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1281 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1282 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1283 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1284 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1285 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1286 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1287 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1288 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1289 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1290 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1291 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1292 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1293 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1294 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1295 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1296 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1297 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1298 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1299 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1300 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1301 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1302 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1303 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1304 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1305 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1306 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1307 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1308 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1309 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1310 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1311 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1312 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1313 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1314 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1315 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1316 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1317 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1318 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1319 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1320 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1321 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1322 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1323 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1324 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1325 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1326 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1327 //DAGB0_WR_VC0_CNTL 1328 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1329 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1330 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1331 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1332 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1333 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1334 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1335 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1336 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1337 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1338 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1339 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1340 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1341 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1342 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1343 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1344 //DAGB0_WR_VC1_CNTL 1345 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1346 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1347 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1348 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1349 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1350 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1351 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1352 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1353 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1354 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1355 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1356 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1357 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1358 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1359 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1360 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1361 //DAGB0_WR_VC2_CNTL 1362 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1363 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1364 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1365 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1366 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1367 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1368 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1369 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1370 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1371 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1372 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1373 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1374 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1375 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1376 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1377 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1378 //DAGB0_WR_VC3_CNTL 1379 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1380 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1381 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1382 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1383 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1384 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1385 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1386 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1387 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1388 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1389 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1390 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1391 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1392 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1393 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1394 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1395 //DAGB0_WR_VC4_CNTL 1396 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1397 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1398 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1399 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1400 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1401 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1402 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1403 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1404 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1405 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1406 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1407 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1408 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1409 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1410 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1411 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1412 //DAGB0_WR_VC5_CNTL 1413 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1414 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1415 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1416 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1417 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1418 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1419 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1420 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1421 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1422 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1423 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1424 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1425 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1426 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1427 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1428 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1429 //DAGB0_WR_VC6_CNTL 1430 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1431 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1432 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1433 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1434 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1435 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1436 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1437 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1438 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1439 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1440 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1441 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1442 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1443 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1444 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1445 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1446 //DAGB0_WR_VC7_CNTL 1447 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1448 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1449 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1450 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1451 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1452 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1453 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1454 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1455 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1456 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1457 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1458 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1459 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1460 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1461 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1462 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1463 //DAGB0_WR_CNTL_MISC 1464 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1465 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1466 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1467 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1468 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1469 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1470 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1471 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1472 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1473 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1474 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1475 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1476 //DAGB0_WR_TLB_CREDIT 1477 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1478 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1479 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1480 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1481 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1482 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1483 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1484 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1485 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1486 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1487 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1488 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1489 //DAGB0_WR_DATA_CREDIT 1490 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1491 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1492 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1493 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1494 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1495 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1496 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1497 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1498 //DAGB0_WR_MISC_CREDIT 1499 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1500 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1501 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1502 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1503 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1504 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1505 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1506 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1507 //DAGB0_WRCLI_ASK_PENDING 1508 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1509 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1510 //DAGB0_WRCLI_GO_PENDING 1511 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1512 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1513 //DAGB0_WRCLI_GBLSEND_PENDING 1514 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1515 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1516 //DAGB0_WRCLI_TLB_PENDING 1517 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1518 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1519 //DAGB0_WRCLI_OARB_PENDING 1520 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1521 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1522 //DAGB0_WRCLI_OSD_PENDING 1523 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1524 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1525 //DAGB0_WRCLI_DBUS_ASK_PENDING 1526 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1527 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1528 //DAGB0_WRCLI_DBUS_GO_PENDING 1529 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1530 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1531 //DAGB0_DAGB_DLY 1532 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1533 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1534 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1535 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1536 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1537 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1538 //DAGB0_CNTL_MISC 1539 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1540 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1541 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1542 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1543 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1544 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1545 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1546 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1547 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1548 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1549 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1550 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1551 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1552 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1553 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1554 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1555 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1556 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1557 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1558 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1559 //DAGB0_CNTL_MISC2 1560 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1561 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1562 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1563 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1564 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1565 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1566 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1567 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1568 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1569 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1570 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1571 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1572 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1573 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1574 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1575 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1576 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1577 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1578 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1579 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1580 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1581 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1582 //DAGB0_FIFO_EMPTY 1583 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1584 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1585 //DAGB0_FIFO_FULL 1586 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1587 #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1588 //DAGB0_WR_CREDITS_FULL 1589 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1590 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 1591 //DAGB0_RD_CREDITS_FULL 1592 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1593 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1594 //DAGB0_PERFCOUNTER_LO 1595 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1596 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1597 //DAGB0_PERFCOUNTER_HI 1598 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1599 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1600 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1601 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1602 //DAGB0_PERFCOUNTER0_CFG 1603 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1604 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1605 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1606 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1607 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1608 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1609 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1610 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1611 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1612 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1613 //DAGB0_PERFCOUNTER1_CFG 1614 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1615 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1616 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1617 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1618 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1619 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1620 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1621 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1622 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1623 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1624 //DAGB0_PERFCOUNTER2_CFG 1625 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1626 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1627 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1628 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1629 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1630 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1631 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1632 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1633 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1634 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1635 //DAGB0_PERFCOUNTER_RSLT_CNTL 1636 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1637 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1638 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1639 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1640 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1641 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1642 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1643 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1644 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1645 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1646 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1647 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1648 //DAGB0_RESERVE0 1649 #define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1650 #define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1651 //DAGB0_RESERVE1 1652 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1653 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1654 //DAGB0_RESERVE2 1655 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1656 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1657 //DAGB0_RESERVE3 1658 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1659 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1660 //DAGB0_RESERVE4 1661 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1662 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1663 //DAGB0_RESERVE5 1664 #define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 1665 #define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 1666 //DAGB0_RESERVE6 1667 #define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 1668 #define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 1669 //DAGB0_RESERVE7 1670 #define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 1671 #define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 1672 //DAGB0_RESERVE8 1673 #define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 1674 #define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 1675 //DAGB0_RESERVE9 1676 #define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 1677 #define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 1678 //DAGB0_RESERVE10 1679 #define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 1680 #define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 1681 //DAGB0_RESERVE11 1682 #define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 1683 #define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 1684 //DAGB0_RESERVE12 1685 #define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 1686 #define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 1687 //DAGB0_RESERVE13 1688 #define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 1689 #define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 1690 //DAGB0_RESERVE14 1691 #define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 1692 #define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 1693 //DAGB0_RESERVE15 1694 #define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 1695 #define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 1696 //DAGB0_RESERVE16 1697 #define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 1698 #define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 1699 //DAGB0_RESERVE17 1700 #define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 1701 #define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 1702 //DAGB1_RDCLI0 1703 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 1704 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1705 #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 1706 #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 1707 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 1708 #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 1709 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 1710 #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 1711 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1712 #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 1713 #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 1714 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1715 #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 1716 #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 1717 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1718 #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 1719 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1720 #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 1721 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1722 #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 1723 //DAGB1_RDCLI1 1724 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 1725 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1726 #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 1727 #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 1728 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 1729 #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 1730 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 1731 #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 1732 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1733 #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 1734 #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 1735 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1736 #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 1737 #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 1738 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1739 #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 1740 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1741 #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 1742 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1743 #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 1744 //DAGB1_RDCLI2 1745 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 1746 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1747 #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 1748 #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 1749 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 1750 #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 1751 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 1752 #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 1753 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1754 #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 1755 #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 1756 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1757 #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 1758 #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 1759 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1760 #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 1761 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1762 #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 1763 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1764 #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 1765 //DAGB1_RDCLI3 1766 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 1767 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1768 #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 1769 #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 1770 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 1771 #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 1772 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 1773 #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 1774 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1775 #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 1776 #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 1777 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1778 #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 1779 #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 1780 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1781 #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 1782 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1783 #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 1784 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1785 #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 1786 //DAGB1_RDCLI4 1787 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 1788 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1789 #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 1790 #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 1791 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 1792 #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 1793 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 1794 #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 1795 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1796 #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 1797 #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 1798 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1799 #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 1800 #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 1801 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1802 #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 1803 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1804 #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 1805 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1806 #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 1807 //DAGB1_RDCLI5 1808 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 1809 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1810 #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 1811 #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 1812 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 1813 #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 1814 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 1815 #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 1816 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1817 #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 1818 #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 1819 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1820 #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 1821 #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 1822 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1823 #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 1824 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1825 #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 1826 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1827 #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 1828 //DAGB1_RDCLI6 1829 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 1830 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1831 #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 1832 #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 1833 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 1834 #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 1835 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 1836 #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 1837 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1838 #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 1839 #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 1840 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1841 #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 1842 #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 1843 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1844 #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 1845 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1846 #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 1847 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1848 #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 1849 //DAGB1_RDCLI7 1850 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 1851 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1852 #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 1853 #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 1854 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 1855 #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 1856 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 1857 #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 1858 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1859 #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 1860 #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 1861 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1862 #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 1863 #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 1864 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1865 #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 1866 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1867 #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 1868 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1869 #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 1870 //DAGB1_RDCLI8 1871 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 1872 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1873 #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 1874 #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 1875 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 1876 #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 1877 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 1878 #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 1879 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1880 #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 1881 #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 1882 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1883 #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 1884 #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 1885 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1886 #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 1887 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1888 #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 1889 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1890 #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 1891 //DAGB1_RDCLI9 1892 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 1893 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1894 #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 1895 #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 1896 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 1897 #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 1898 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 1899 #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 1900 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1901 #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 1902 #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 1903 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1904 #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 1905 #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 1906 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1907 #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 1908 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1909 #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 1910 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1911 #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 1912 //DAGB1_RDCLI10 1913 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 1914 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1915 #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 1916 #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 1917 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 1918 #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 1919 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 1920 #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 1921 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1922 #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 1923 #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 1924 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1925 #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 1926 #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 1927 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1928 #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 1929 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1930 #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 1931 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1932 #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 1933 //DAGB1_RDCLI11 1934 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 1935 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1936 #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 1937 #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 1938 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 1939 #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 1940 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 1941 #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 1942 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1943 #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 1944 #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 1945 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1946 #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 1947 #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 1948 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1949 #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 1950 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1951 #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 1952 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1953 #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 1954 //DAGB1_RDCLI12 1955 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 1956 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1957 #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 1958 #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 1959 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 1960 #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 1961 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 1962 #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 1963 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1964 #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 1965 #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 1966 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1967 #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 1968 #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 1969 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1970 #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 1971 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1972 #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 1973 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1974 #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 1975 //DAGB1_RDCLI13 1976 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 1977 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1978 #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 1979 #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 1980 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 1981 #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 1982 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 1983 #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 1984 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1985 #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 1986 #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 1987 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1988 #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 1989 #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 1990 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1991 #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 1992 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1993 #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 1994 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1995 #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 1996 //DAGB1_RDCLI14 1997 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 1998 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1999 #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2000 #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2001 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2002 #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2003 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2004 #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2005 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2006 #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2007 #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2008 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2009 #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2010 #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2011 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2012 #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2013 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2014 #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2015 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2016 #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2017 //DAGB1_RDCLI15 2018 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2019 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2020 #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2021 #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2022 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2023 #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2024 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2025 #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2026 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2027 #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2028 #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2029 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2030 #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2031 #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2032 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2033 #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2034 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2035 #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2036 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2037 #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2038 //DAGB1_RD_CNTL 2039 #define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 2040 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2041 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2042 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2043 #define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 2044 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2045 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 2046 #define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 2047 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2048 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2049 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2050 #define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 2051 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2052 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2053 //DAGB1_RD_GMI_CNTL 2054 #define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2055 #define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 2056 #define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 2057 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2058 #define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2059 #define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 2060 #define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2061 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2062 //DAGB1_RD_ADDR_DAGB 2063 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2064 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2065 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2066 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2067 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2068 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2069 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2070 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2071 //DAGB1_RD_OUTPUT_DAGB_MAX_BURST 2072 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2073 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2074 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2075 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2076 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2077 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2078 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2079 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2080 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2081 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2082 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2083 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2084 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2085 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2086 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2087 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2088 //DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 2089 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2090 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2091 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2092 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2093 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2094 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2095 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2096 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2097 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2098 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2099 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2100 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2101 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2102 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2103 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2104 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2105 //DAGB1_RD_CGTT_CLK_CTRL 2106 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2107 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2108 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2109 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2110 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2111 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2112 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2113 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2114 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2115 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2116 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2117 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2118 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2119 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2120 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2121 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2122 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2123 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2124 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2125 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2126 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2127 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2128 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2129 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2130 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2131 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2132 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2133 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2134 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2135 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2136 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2137 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2138 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2139 //DAGB1_ATCVM_RD_CGTT_CLK_CTRL 2140 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2141 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2142 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2143 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2144 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2145 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2146 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2147 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2148 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2149 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2150 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2151 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2152 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2153 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2154 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2155 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2156 //DAGB1_RD_ADDR_DAGB_MAX_BURST0 2157 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2158 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2159 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2160 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2161 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2162 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2163 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2164 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2165 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2166 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2167 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2168 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2169 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2170 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2171 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2172 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2173 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 2174 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2175 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2176 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2177 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2178 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2179 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2180 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2181 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2182 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2183 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2184 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2185 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2186 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2187 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2188 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2189 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2190 //DAGB1_RD_ADDR_DAGB_MAX_BURST1 2191 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2192 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2193 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2194 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2195 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2196 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2197 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2198 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2199 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2200 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2201 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2202 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2203 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2204 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2205 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2206 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2207 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 2208 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2209 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2210 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2211 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2212 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2213 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2214 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2215 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2216 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2217 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2218 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2219 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2220 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2221 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2222 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2223 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2224 //DAGB1_RD_VC0_CNTL 2225 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2226 #define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2227 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2228 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 2229 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2230 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 2231 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2232 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 2233 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2234 #define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2235 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2236 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2237 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2238 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2239 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2240 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2241 //DAGB1_RD_VC1_CNTL 2242 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2243 #define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2244 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2245 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 2246 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2247 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 2248 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2249 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 2250 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2251 #define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2252 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2253 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2254 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2255 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2256 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2257 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2258 //DAGB1_RD_VC2_CNTL 2259 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2260 #define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2261 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2262 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 2263 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2264 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 2265 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2266 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 2267 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2268 #define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2269 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2270 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2271 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2272 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2273 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2274 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2275 //DAGB1_RD_VC3_CNTL 2276 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2277 #define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2278 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2279 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 2280 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2281 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 2282 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2283 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 2284 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2285 #define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2286 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2287 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2288 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2289 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2290 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2291 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2292 //DAGB1_RD_VC4_CNTL 2293 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2294 #define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2295 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2296 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 2297 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2298 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 2299 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2300 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 2301 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2302 #define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2303 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2304 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2305 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2306 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2307 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2308 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2309 //DAGB1_RD_VC5_CNTL 2310 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2311 #define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2312 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2313 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 2314 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2315 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 2316 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2317 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 2318 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2319 #define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2320 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2321 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2322 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2323 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2324 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2325 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2326 //DAGB1_RD_VC6_CNTL 2327 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2328 #define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2329 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2330 #define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 2331 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2332 #define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 2333 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2334 #define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 2335 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2336 #define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2337 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2338 #define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2339 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2340 #define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2341 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2342 #define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2343 //DAGB1_RD_VC7_CNTL 2344 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2345 #define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2346 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2347 #define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 2348 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2349 #define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 2350 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2351 #define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 2352 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2353 #define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2354 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2355 #define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2356 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2357 #define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2358 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2359 #define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2360 //DAGB1_RD_CNTL_MISC 2361 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2362 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2363 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2364 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2365 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2366 #define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2367 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2368 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2369 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2370 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2371 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2372 #define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2373 //DAGB1_RD_TLB_CREDIT 2374 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 2375 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 2376 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 2377 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 2378 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 2379 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 2380 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 2381 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 2382 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 2383 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 2384 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 2385 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 2386 //DAGB1_RDCLI_ASK_PENDING 2387 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 2388 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2389 //DAGB1_RDCLI_GO_PENDING 2390 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 2391 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2392 //DAGB1_RDCLI_GBLSEND_PENDING 2393 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2394 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2395 //DAGB1_RDCLI_TLB_PENDING 2396 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 2397 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2398 //DAGB1_RDCLI_OARB_PENDING 2399 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 2400 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2401 //DAGB1_RDCLI_OSD_PENDING 2402 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 2403 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2404 //DAGB1_WRCLI0 2405 #define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 2406 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2407 #define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 2408 #define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 2409 #define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 2410 #define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd 2411 #define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 2412 #define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 2413 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2414 #define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a 2415 #define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L 2416 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2417 #define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L 2418 #define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L 2419 #define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2420 #define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L 2421 #define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2422 #define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L 2423 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2424 #define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L 2425 //DAGB1_WRCLI1 2426 #define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 2427 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2428 #define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 2429 #define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 2430 #define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 2431 #define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd 2432 #define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 2433 #define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 2434 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2435 #define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a 2436 #define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L 2437 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2438 #define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L 2439 #define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L 2440 #define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2441 #define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L 2442 #define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2443 #define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L 2444 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2445 #define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L 2446 //DAGB1_WRCLI2 2447 #define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 2448 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2449 #define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 2450 #define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 2451 #define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 2452 #define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd 2453 #define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 2454 #define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 2455 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2456 #define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a 2457 #define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L 2458 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2459 #define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L 2460 #define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L 2461 #define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2462 #define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L 2463 #define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2464 #define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L 2465 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2466 #define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L 2467 //DAGB1_WRCLI3 2468 #define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 2469 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2470 #define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 2471 #define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 2472 #define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 2473 #define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd 2474 #define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 2475 #define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 2476 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2477 #define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a 2478 #define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L 2479 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2480 #define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L 2481 #define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L 2482 #define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2483 #define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L 2484 #define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2485 #define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L 2486 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2487 #define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L 2488 //DAGB1_WRCLI4 2489 #define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 2490 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2491 #define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 2492 #define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 2493 #define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 2494 #define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd 2495 #define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 2496 #define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 2497 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2498 #define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a 2499 #define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L 2500 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2501 #define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L 2502 #define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L 2503 #define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2504 #define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L 2505 #define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2506 #define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L 2507 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2508 #define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L 2509 //DAGB1_WRCLI5 2510 #define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 2511 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2512 #define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 2513 #define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 2514 #define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 2515 #define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd 2516 #define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 2517 #define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 2518 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2519 #define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a 2520 #define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L 2521 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2522 #define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L 2523 #define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L 2524 #define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2525 #define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L 2526 #define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2527 #define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L 2528 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2529 #define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L 2530 //DAGB1_WRCLI6 2531 #define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 2532 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2533 #define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 2534 #define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 2535 #define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 2536 #define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd 2537 #define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 2538 #define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 2539 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2540 #define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a 2541 #define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L 2542 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2543 #define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L 2544 #define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L 2545 #define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2546 #define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L 2547 #define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2548 #define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L 2549 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2550 #define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L 2551 //DAGB1_WRCLI7 2552 #define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 2553 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2554 #define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 2555 #define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 2556 #define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 2557 #define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd 2558 #define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 2559 #define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 2560 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2561 #define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a 2562 #define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L 2563 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2564 #define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L 2565 #define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L 2566 #define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2567 #define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L 2568 #define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2569 #define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L 2570 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2571 #define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L 2572 //DAGB1_WRCLI8 2573 #define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 2574 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2575 #define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 2576 #define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 2577 #define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 2578 #define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd 2579 #define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 2580 #define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 2581 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2582 #define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a 2583 #define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L 2584 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2585 #define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L 2586 #define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L 2587 #define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2588 #define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L 2589 #define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2590 #define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L 2591 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2592 #define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L 2593 //DAGB1_WRCLI9 2594 #define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 2595 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2596 #define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 2597 #define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 2598 #define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 2599 #define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd 2600 #define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 2601 #define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 2602 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2603 #define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a 2604 #define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L 2605 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2606 #define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L 2607 #define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L 2608 #define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2609 #define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L 2610 #define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2611 #define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L 2612 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2613 #define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L 2614 //DAGB1_WRCLI10 2615 #define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 2616 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2617 #define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 2618 #define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 2619 #define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 2620 #define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd 2621 #define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 2622 #define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 2623 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2624 #define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a 2625 #define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L 2626 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2627 #define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L 2628 #define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L 2629 #define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2630 #define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L 2631 #define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2632 #define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L 2633 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2634 #define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L 2635 //DAGB1_WRCLI11 2636 #define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 2637 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2638 #define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 2639 #define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 2640 #define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 2641 #define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd 2642 #define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 2643 #define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 2644 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2645 #define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a 2646 #define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L 2647 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2648 #define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L 2649 #define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L 2650 #define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2651 #define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L 2652 #define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2653 #define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L 2654 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2655 #define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L 2656 //DAGB1_WRCLI12 2657 #define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 2658 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2659 #define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 2660 #define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 2661 #define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 2662 #define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd 2663 #define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 2664 #define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 2665 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2666 #define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a 2667 #define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L 2668 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2669 #define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L 2670 #define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L 2671 #define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2672 #define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L 2673 #define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2674 #define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L 2675 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2676 #define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L 2677 //DAGB1_WRCLI13 2678 #define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 2679 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2680 #define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 2681 #define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 2682 #define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 2683 #define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd 2684 #define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 2685 #define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 2686 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2687 #define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a 2688 #define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L 2689 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2690 #define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L 2691 #define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L 2692 #define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2693 #define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L 2694 #define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2695 #define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L 2696 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2697 #define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L 2698 //DAGB1_WRCLI14 2699 #define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 2700 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2701 #define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 2702 #define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 2703 #define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 2704 #define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd 2705 #define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 2706 #define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 2707 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2708 #define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a 2709 #define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L 2710 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2711 #define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L 2712 #define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L 2713 #define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2714 #define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L 2715 #define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2716 #define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L 2717 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2718 #define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L 2719 //DAGB1_WRCLI15 2720 #define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 2721 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2722 #define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 2723 #define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 2724 #define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 2725 #define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd 2726 #define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 2727 #define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 2728 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2729 #define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a 2730 #define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L 2731 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2732 #define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L 2733 #define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L 2734 #define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2735 #define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L 2736 #define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2737 #define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L 2738 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2739 #define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L 2740 //DAGB1_WR_CNTL 2741 #define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 2742 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2743 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2744 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2745 #define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 2746 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2747 #define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 2748 #define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 2749 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2750 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2751 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2752 #define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 2753 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2754 #define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2755 //DAGB1_WR_GMI_CNTL 2756 #define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2757 #define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 2758 #define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 2759 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2760 #define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2761 #define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 2762 #define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2763 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2764 //DAGB1_WR_ADDR_DAGB 2765 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2766 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2767 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2768 #define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 2769 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2770 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2771 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2772 #define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2773 //DAGB1_WR_OUTPUT_DAGB_MAX_BURST 2774 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2775 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2776 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2777 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2778 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2779 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2780 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2781 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2782 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2783 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2784 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2785 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2786 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2787 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2788 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2789 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2790 //DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 2791 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2792 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2793 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2794 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2795 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2796 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2797 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2798 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2799 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2800 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2801 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2802 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2803 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2804 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2805 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2806 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2807 //DAGB1_WR_CGTT_CLK_CTRL 2808 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2809 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2810 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2811 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2812 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2813 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2814 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2815 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2816 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2817 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2818 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2819 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2820 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2821 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2822 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2823 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2824 //DAGB1_L1TLB_WR_CGTT_CLK_CTRL 2825 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2826 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2827 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2828 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2829 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2830 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2831 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2832 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2833 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2834 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2835 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2836 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2837 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2838 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2839 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2840 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2841 //DAGB1_ATCVM_WR_CGTT_CLK_CTRL 2842 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2843 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2844 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2845 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2846 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2847 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2848 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2849 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2850 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2851 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2852 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2853 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2854 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2855 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2856 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2857 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2858 //DAGB1_WR_ADDR_DAGB_MAX_BURST0 2859 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2860 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2861 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2862 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2863 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2864 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2865 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2866 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2867 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2868 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2869 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2870 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2871 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2872 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2873 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2874 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2875 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 2876 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2877 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2878 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2879 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2880 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2881 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2882 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2883 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2884 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2885 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2886 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2887 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2888 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2889 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2890 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2891 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2892 //DAGB1_WR_ADDR_DAGB_MAX_BURST1 2893 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2894 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2895 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2896 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2897 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2898 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2899 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2900 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2901 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2902 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2903 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2904 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2905 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2906 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2907 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2908 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2909 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 2910 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2911 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2912 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2913 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2914 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2915 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2916 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2917 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2918 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2919 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2920 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2921 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2922 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2923 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2924 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2925 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2926 //DAGB1_WR_DATA_DAGB 2927 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 2928 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2929 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2930 #define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 2931 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 2932 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2933 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2934 #define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 2935 //DAGB1_WR_DATA_DAGB_MAX_BURST0 2936 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2937 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2938 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2939 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2940 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2941 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2942 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2943 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2944 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2945 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2946 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2947 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2948 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2949 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2950 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2951 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2952 //DAGB1_WR_DATA_DAGB_LAZY_TIMER0 2953 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2954 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2955 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2956 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2957 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2958 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2959 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2960 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2961 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2962 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2963 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2964 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2965 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2966 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2967 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2968 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2969 //DAGB1_WR_DATA_DAGB_MAX_BURST1 2970 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2971 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2972 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2973 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2974 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2975 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2976 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2977 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2978 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2979 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2980 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2981 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2982 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2983 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2984 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2985 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2986 //DAGB1_WR_DATA_DAGB_LAZY_TIMER1 2987 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2988 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2989 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2990 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2991 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2992 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2993 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2994 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2995 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2996 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2997 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2998 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2999 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3000 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3001 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3002 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3003 //DAGB1_WR_VC0_CNTL 3004 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3005 #define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 3006 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3007 #define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 3008 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3009 #define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 3010 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3011 #define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 3012 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3013 #define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 3014 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3015 #define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3016 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3017 #define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3018 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3019 #define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3020 //DAGB1_WR_VC1_CNTL 3021 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3022 #define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 3023 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3024 #define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 3025 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3026 #define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 3027 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3028 #define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 3029 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3030 #define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 3031 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3032 #define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3033 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3034 #define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3035 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3036 #define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3037 //DAGB1_WR_VC2_CNTL 3038 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3039 #define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 3040 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3041 #define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 3042 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3043 #define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 3044 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3045 #define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 3046 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3047 #define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 3048 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3049 #define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3050 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3051 #define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3052 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3053 #define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3054 //DAGB1_WR_VC3_CNTL 3055 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3056 #define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 3057 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3058 #define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 3059 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3060 #define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 3061 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3062 #define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 3063 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3064 #define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 3065 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3066 #define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3067 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3068 #define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3069 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3070 #define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3071 //DAGB1_WR_VC4_CNTL 3072 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3073 #define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 3074 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3075 #define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 3076 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3077 #define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 3078 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3079 #define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 3080 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3081 #define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 3082 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3083 #define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3084 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3085 #define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3086 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3087 #define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3088 //DAGB1_WR_VC5_CNTL 3089 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3090 #define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 3091 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3092 #define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 3093 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3094 #define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 3095 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3096 #define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 3097 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3098 #define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 3099 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3100 #define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3101 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3102 #define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3103 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3104 #define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3105 //DAGB1_WR_VC6_CNTL 3106 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 3107 #define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 3108 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3109 #define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 3110 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3111 #define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 3112 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3113 #define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 3114 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 3115 #define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 3116 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3117 #define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 3118 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3119 #define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 3120 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3121 #define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 3122 //DAGB1_WR_VC7_CNTL 3123 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 3124 #define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 3125 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3126 #define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 3127 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3128 #define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 3129 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3130 #define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 3131 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 3132 #define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 3133 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3134 #define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 3135 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3136 #define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 3137 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3138 #define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 3139 //DAGB1_WR_CNTL_MISC 3140 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3141 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 3142 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 3143 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 3144 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 3145 #define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 3146 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3147 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 3148 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 3149 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 3150 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 3151 #define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 3152 //DAGB1_WR_TLB_CREDIT 3153 #define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 3154 #define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 3155 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa 3156 #define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf 3157 #define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 3158 #define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 3159 #define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 3160 #define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 3161 #define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 3162 #define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 3163 #define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 3164 #define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 3165 //DAGB1_WR_DATA_CREDIT 3166 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 3167 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 3168 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 3169 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 3170 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 3171 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 3172 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 3173 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 3174 //DAGB1_WR_MISC_CREDIT 3175 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 3176 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 3177 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 3178 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 3179 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 3180 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 3181 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 3182 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 3183 //DAGB1_WRCLI_ASK_PENDING 3184 #define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 3185 #define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3186 //DAGB1_WRCLI_GO_PENDING 3187 #define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 3188 #define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3189 //DAGB1_WRCLI_GBLSEND_PENDING 3190 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3191 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3192 //DAGB1_WRCLI_TLB_PENDING 3193 #define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 3194 #define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3195 //DAGB1_WRCLI_OARB_PENDING 3196 #define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 3197 #define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3198 //DAGB1_WRCLI_OSD_PENDING 3199 #define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 3200 #define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3201 //DAGB1_WRCLI_DBUS_ASK_PENDING 3202 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 3203 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3204 //DAGB1_WRCLI_DBUS_GO_PENDING 3205 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 3206 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3207 //DAGB1_DAGB_DLY 3208 #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3209 #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3210 #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3211 #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3212 #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3213 #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3214 //DAGB1_CNTL_MISC 3215 #define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 3216 #define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 3217 #define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 3218 #define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 3219 #define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 3220 #define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 3221 #define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 3222 #define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 3223 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 3224 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 3225 #define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 3226 #define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 3227 #define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 3228 #define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 3229 #define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 3230 #define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 3231 #define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 3232 #define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 3233 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 3234 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 3235 //DAGB1_CNTL_MISC2 3236 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 3237 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 3238 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 3239 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 3240 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 3241 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 3242 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 3243 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 3244 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 3245 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 3246 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 3247 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 3248 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 3249 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 3250 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 3251 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 3252 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 3253 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 3254 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 3255 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 3256 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 3257 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 3258 //DAGB1_FIFO_EMPTY 3259 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3260 #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 3261 //DAGB1_FIFO_FULL 3262 #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3263 #define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL 3264 //DAGB1_WR_CREDITS_FULL 3265 #define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 3266 #define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 3267 //DAGB1_RD_CREDITS_FULL 3268 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3269 #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 3270 //DAGB1_PERFCOUNTER_LO 3271 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3272 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3273 //DAGB1_PERFCOUNTER_HI 3274 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3275 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3276 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3277 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3278 //DAGB1_PERFCOUNTER0_CFG 3279 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3280 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3281 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3282 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3283 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3284 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3285 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3286 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3287 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3288 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3289 //DAGB1_PERFCOUNTER1_CFG 3290 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3291 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3292 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3293 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3294 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3295 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3296 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3297 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3298 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3299 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3300 //DAGB1_PERFCOUNTER2_CFG 3301 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3302 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3303 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3304 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3305 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3306 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3307 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3308 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3309 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3310 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3311 //DAGB1_PERFCOUNTER_RSLT_CNTL 3312 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3313 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3314 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3315 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3316 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3317 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3318 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3319 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3320 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3321 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3322 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3323 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3324 //DAGB1_RESERVE0 3325 #define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 3326 #define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 3327 //DAGB1_RESERVE1 3328 #define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3329 #define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3330 //DAGB1_RESERVE2 3331 #define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3332 #define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3333 //DAGB1_RESERVE3 3334 #define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3335 #define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3336 //DAGB1_RESERVE4 3337 #define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3338 #define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3339 //DAGB1_RESERVE5 3340 #define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 3341 #define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 3342 //DAGB1_RESERVE6 3343 #define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 3344 #define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 3345 //DAGB1_RESERVE7 3346 #define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 3347 #define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 3348 //DAGB1_RESERVE8 3349 #define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 3350 #define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 3351 //DAGB1_RESERVE9 3352 #define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 3353 #define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 3354 //DAGB1_RESERVE10 3355 #define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 3356 #define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 3357 //DAGB1_RESERVE11 3358 #define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 3359 #define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 3360 //DAGB1_RESERVE12 3361 #define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 3362 #define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 3363 //DAGB1_RESERVE13 3364 #define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 3365 #define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 3366 //DAGB1_RESERVE14 3367 #define DAGB1_RESERVE14__RESERVE__SHIFT 0x0 3368 #define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 3369 //DAGB1_RESERVE15 3370 #define DAGB1_RESERVE15__RESERVE__SHIFT 0x0 3371 #define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 3372 //DAGB1_RESERVE16 3373 #define DAGB1_RESERVE16__RESERVE__SHIFT 0x0 3374 #define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 3375 //DAGB1_RESERVE17 3376 #define DAGB1_RESERVE17__RESERVE__SHIFT 0x0 3377 #define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 3378 3379 3380 // addressBlock: mmhub_ea_mmeadec 3381 //MMEA0_DRAM_RD_CLI2GRP_MAP0 3382 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3383 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3384 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3385 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3386 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3387 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3388 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3389 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3390 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3391 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3392 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3393 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3394 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3395 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3396 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3397 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3398 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3399 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3400 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3401 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3402 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3403 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3404 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3405 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3406 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3407 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3408 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3409 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3410 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3411 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3412 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3413 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3414 //MMEA0_DRAM_RD_CLI2GRP_MAP1 3415 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3416 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3417 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3418 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3419 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3420 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3421 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3422 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3423 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3424 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3425 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3426 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3427 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3428 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3429 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3430 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3431 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3432 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3433 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3434 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3435 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3436 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3437 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3438 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3439 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3440 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3441 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3442 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3443 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3444 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3445 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3446 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3447 //MMEA0_DRAM_WR_CLI2GRP_MAP0 3448 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3449 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3450 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3451 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3452 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3453 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3454 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3455 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3456 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3457 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3458 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3459 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3460 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3461 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3462 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3463 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3464 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3465 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3466 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3467 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3468 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3469 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3470 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3471 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3472 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3473 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3474 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3475 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3476 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3477 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3478 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3479 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3480 //MMEA0_DRAM_WR_CLI2GRP_MAP1 3481 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3482 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3483 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3484 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3485 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3486 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3487 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3488 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3489 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3490 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3491 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3492 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3493 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3494 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3495 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3496 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3497 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3498 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3499 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3500 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3501 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3502 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3503 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3504 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3505 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3506 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3507 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3508 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3509 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3510 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3511 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3512 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3513 //MMEA0_DRAM_RD_GRP2VC_MAP 3514 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 3515 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 3516 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 3517 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 3518 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 3519 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 3520 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 3521 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 3522 //MMEA0_DRAM_WR_GRP2VC_MAP 3523 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 3524 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 3525 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 3526 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 3527 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 3528 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 3529 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 3530 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 3531 //MMEA0_DRAM_RD_LAZY 3532 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 3533 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 3534 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 3535 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 3536 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 3537 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 3538 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 3539 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 3540 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 3541 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 3542 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 3543 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 3544 //MMEA0_DRAM_WR_LAZY 3545 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 3546 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 3547 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 3548 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 3549 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 3550 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 3551 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 3552 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 3553 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 3554 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 3555 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 3556 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 3557 //MMEA0_DRAM_RD_CAM_CNTL 3558 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3559 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3560 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3561 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3562 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3563 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3564 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3565 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3566 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3567 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3568 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3569 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3570 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3571 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3572 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3573 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3574 //MMEA0_DRAM_WR_CAM_CNTL 3575 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3576 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3577 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3578 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3579 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3580 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3581 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3582 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3583 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3584 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3585 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3586 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3587 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3588 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3589 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3590 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3591 //MMEA0_DRAM_PAGE_BURST 3592 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 3593 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 3594 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 3595 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 3596 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3597 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3598 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3599 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3600 //MMEA0_DRAM_RD_PRI_AGE 3601 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3602 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3603 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3604 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3605 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3606 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3607 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3608 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3609 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3610 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3611 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3612 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3613 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3614 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3615 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3616 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3617 //MMEA0_DRAM_WR_PRI_AGE 3618 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3619 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3620 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3621 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3622 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3623 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3624 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3625 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3626 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3627 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3628 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3629 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3630 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3631 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3632 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3633 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3634 //MMEA0_DRAM_RD_PRI_QUEUING 3635 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3636 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3637 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3638 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3639 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3640 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3641 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3642 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3643 //MMEA0_DRAM_WR_PRI_QUEUING 3644 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3645 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3646 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3647 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3648 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3649 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3650 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3651 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3652 //MMEA0_DRAM_RD_PRI_FIXED 3653 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3654 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3655 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3656 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3657 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3658 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3659 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3660 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3661 //MMEA0_DRAM_WR_PRI_FIXED 3662 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3663 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3664 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3665 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3666 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3667 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3668 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3669 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3670 //MMEA0_DRAM_RD_PRI_URGENCY 3671 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3672 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3673 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3674 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3675 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3676 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3677 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3678 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3679 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3680 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3681 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3682 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3683 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3684 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3685 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3686 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3687 //MMEA0_DRAM_WR_PRI_URGENCY 3688 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3689 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3690 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3691 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3692 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3693 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3694 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3695 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3696 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3697 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3698 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3699 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3700 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3701 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3702 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3703 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3704 //MMEA0_DRAM_RD_PRI_QUANT_PRI1 3705 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3706 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3707 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3708 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3709 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3710 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3711 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3712 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3713 //MMEA0_DRAM_RD_PRI_QUANT_PRI2 3714 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3715 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3716 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3717 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3718 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3719 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3720 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3721 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3722 //MMEA0_DRAM_RD_PRI_QUANT_PRI3 3723 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3724 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3725 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3726 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3727 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3728 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3729 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3730 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3731 //MMEA0_DRAM_WR_PRI_QUANT_PRI1 3732 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3733 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3734 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3735 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3736 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3737 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3738 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3739 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3740 //MMEA0_DRAM_WR_PRI_QUANT_PRI2 3741 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3742 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3743 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3744 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3745 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3746 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3747 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3748 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3749 //MMEA0_DRAM_WR_PRI_QUANT_PRI3 3750 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3751 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3752 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3753 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3754 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3755 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3756 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3757 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3758 //MMEA0_ADDRNORM_BASE_ADDR0 3759 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 3760 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3761 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 3762 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 3763 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 3764 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 3765 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3766 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 3767 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 3768 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 3769 //MMEA0_ADDRNORM_LIMIT_ADDR0 3770 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 3771 #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 3772 #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 3773 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 3774 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 3775 #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 3776 #define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 3777 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 3778 //MMEA0_ADDRNORM_BASE_ADDR1 3779 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 3780 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3781 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 3782 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 3783 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 3784 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 3785 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3786 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 3787 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 3788 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 3789 //MMEA0_ADDRNORM_LIMIT_ADDR1 3790 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 3791 #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 3792 #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 3793 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 3794 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 3795 #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 3796 #define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 3797 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 3798 //MMEA0_ADDRNORM_OFFSET_ADDR1 3799 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 3800 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 3801 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 3802 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 3803 //MMEA0_ADDRNORMDRAM_HOLE_CNTL 3804 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 3805 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 3806 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 3807 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 3808 //MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG 3809 #define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0 3810 #define MMEA0_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL 3811 //MMEA0_ADDRDEC_BANK_CFG 3812 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 3813 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 3814 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 3815 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 3816 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 3817 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 3818 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 3819 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 3820 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 3821 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 3822 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 3823 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 3824 //MMEA0_ADDRDEC_MISC_CFG 3825 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 3826 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 3827 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 3828 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 3829 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 3830 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 3831 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 3832 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 3833 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 3834 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 3835 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 3836 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 3837 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 3838 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 3839 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 3840 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 3841 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 3842 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 3843 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 3844 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 3845 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 3846 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 3847 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 3848 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 3849 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 3850 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 3851 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 3852 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 3853 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 3854 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 3855 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 3856 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 3857 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 3858 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 3859 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 3860 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 3861 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 3862 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 3863 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 3864 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 3865 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 3866 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 3867 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 3868 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 3869 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 3870 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 3871 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 3872 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 3873 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 3874 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 3875 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 3876 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 3877 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 3878 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 3879 //MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 3880 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 3881 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 3882 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 3883 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 3884 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 3885 #define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 3886 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC 3887 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 3888 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 3889 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 3890 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 3891 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 3892 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 3893 //MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 3894 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 3895 #define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 3896 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 3897 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 3898 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 3899 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 3900 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 3901 //MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 3902 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 3903 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 3904 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 3905 #define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 3906 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 3907 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 3908 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 3909 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 3910 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 3911 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 3912 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 3913 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 3914 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 3915 //MMEA0_ADDRDEC0_BASE_ADDR_CS0 3916 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 3917 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3918 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 3919 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3920 //MMEA0_ADDRDEC0_BASE_ADDR_CS1 3921 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 3922 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3923 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 3924 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3925 //MMEA0_ADDRDEC0_BASE_ADDR_CS2 3926 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 3927 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3928 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 3929 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3930 //MMEA0_ADDRDEC0_BASE_ADDR_CS3 3931 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 3932 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3933 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 3934 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3935 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 3936 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 3937 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3938 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 3939 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3940 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 3941 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 3942 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3943 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 3944 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3945 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 3946 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 3947 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3948 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 3949 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3950 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 3951 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 3952 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3953 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 3954 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3955 //MMEA0_ADDRDEC0_ADDR_MASK_CS01 3956 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3957 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3958 //MMEA0_ADDRDEC0_ADDR_MASK_CS23 3959 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3960 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3961 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 3962 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3963 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3964 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 3965 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3966 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3967 //MMEA0_ADDRDEC0_ADDR_CFG_CS01 3968 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3969 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3970 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3971 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3972 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3973 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3974 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 3975 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3976 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3977 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3978 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3979 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3980 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3981 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 3982 //MMEA0_ADDRDEC0_ADDR_CFG_CS23 3983 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3984 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3985 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3986 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3987 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3988 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3989 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 3990 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3991 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3992 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3993 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3994 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3995 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3996 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 3997 //MMEA0_ADDRDEC0_ADDR_SEL_CS01 3998 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3999 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 4000 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 4001 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 4002 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 4003 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 4004 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 4005 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 4006 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 4007 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 4008 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 4009 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 4010 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 4011 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 4012 //MMEA0_ADDRDEC0_ADDR_SEL_CS23 4013 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 4014 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 4015 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 4016 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 4017 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 4018 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 4019 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 4020 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 4021 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 4022 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 4023 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 4024 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 4025 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 4026 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 4027 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 4028 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 4029 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 4030 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 4031 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 4032 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 4033 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 4034 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 4035 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 4036 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 4037 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 4038 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 4039 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 4040 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 4041 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 4042 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 4043 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 4044 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 4045 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 4046 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 4047 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 4048 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 4049 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 4050 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 4051 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 4052 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 4053 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 4054 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 4055 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 4056 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 4057 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 4058 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 4059 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 4060 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 4061 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 4062 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 4063 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 4064 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 4065 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 4066 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 4067 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 4068 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 4069 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 4070 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 4071 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 4072 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 4073 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 4074 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 4075 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 4076 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 4077 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 4078 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 4079 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 4080 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 4081 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 4082 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 4083 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 4084 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 4085 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 4086 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 4087 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 4088 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 4089 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 4090 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 4091 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 4092 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 4093 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 4094 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 4095 //MMEA0_ADDRDEC0_RM_SEL_CS01 4096 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 4097 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 4098 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 4099 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 4100 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4101 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4102 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 4103 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 4104 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 4105 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 4106 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4107 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4108 //MMEA0_ADDRDEC0_RM_SEL_CS23 4109 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 4110 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 4111 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 4112 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 4113 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4114 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4115 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 4116 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 4117 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 4118 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 4119 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4120 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4121 //MMEA0_ADDRDEC0_RM_SEL_SECCS01 4122 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 4123 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 4124 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 4125 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 4126 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4127 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4128 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 4129 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 4130 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 4131 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 4132 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4133 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4134 //MMEA0_ADDRDEC0_RM_SEL_SECCS23 4135 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 4136 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 4137 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 4138 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 4139 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4140 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4141 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 4142 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 4143 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 4144 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 4145 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4146 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4147 //MMEA0_ADDRDEC1_BASE_ADDR_CS0 4148 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 4149 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 4150 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 4151 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 4152 //MMEA0_ADDRDEC1_BASE_ADDR_CS1 4153 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 4154 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 4155 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 4156 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 4157 //MMEA0_ADDRDEC1_BASE_ADDR_CS2 4158 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 4159 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 4160 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 4161 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 4162 //MMEA0_ADDRDEC1_BASE_ADDR_CS3 4163 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 4164 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 4165 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 4166 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 4167 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 4168 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 4169 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 4170 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 4171 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 4172 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 4173 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 4174 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 4175 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 4176 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 4177 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 4178 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 4179 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 4180 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 4181 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 4182 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 4183 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 4184 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 4185 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 4186 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 4187 //MMEA0_ADDRDEC1_ADDR_MASK_CS01 4188 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 4189 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 4190 //MMEA0_ADDRDEC1_ADDR_MASK_CS23 4191 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 4192 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 4193 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 4194 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 4195 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 4196 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 4197 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 4198 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 4199 //MMEA0_ADDRDEC1_ADDR_CFG_CS01 4200 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 4201 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 4202 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 4203 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 4204 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 4205 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 4206 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 4207 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 4208 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 4209 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 4210 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 4211 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 4212 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 4213 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 4214 //MMEA0_ADDRDEC1_ADDR_CFG_CS23 4215 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 4216 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 4217 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 4218 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 4219 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 4220 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 4221 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 4222 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 4223 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 4224 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 4225 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 4226 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 4227 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 4228 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 4229 //MMEA0_ADDRDEC1_ADDR_SEL_CS01 4230 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 4231 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 4232 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 4233 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 4234 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 4235 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 4236 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 4237 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 4238 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 4239 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 4240 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 4241 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 4242 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 4243 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 4244 //MMEA0_ADDRDEC1_ADDR_SEL_CS23 4245 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 4246 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 4247 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 4248 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 4249 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 4250 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 4251 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 4252 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 4253 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 4254 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 4255 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 4256 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 4257 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 4258 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 4259 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 4260 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 4261 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 4262 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 4263 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 4264 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 4265 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 4266 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 4267 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 4268 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 4269 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 4270 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 4271 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 4272 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 4273 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 4274 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 4275 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 4276 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 4277 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 4278 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 4279 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 4280 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 4281 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 4282 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 4283 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 4284 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 4285 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 4286 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 4287 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 4288 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 4289 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 4290 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 4291 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 4292 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 4293 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 4294 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 4295 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 4296 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 4297 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 4298 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 4299 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 4300 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 4301 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 4302 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 4303 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 4304 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 4305 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 4306 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 4307 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 4308 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 4309 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 4310 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 4311 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 4312 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 4313 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 4314 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 4315 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 4316 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 4317 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 4318 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 4319 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 4320 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 4321 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 4322 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 4323 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 4324 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 4325 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 4326 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 4327 //MMEA0_ADDRDEC1_RM_SEL_CS01 4328 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 4329 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 4330 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 4331 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 4332 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4333 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4334 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 4335 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 4336 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 4337 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 4338 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4339 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4340 //MMEA0_ADDRDEC1_RM_SEL_CS23 4341 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 4342 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 4343 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 4344 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 4345 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4346 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4347 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 4348 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 4349 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 4350 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 4351 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4352 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4353 //MMEA0_ADDRDEC1_RM_SEL_SECCS01 4354 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 4355 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 4356 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 4357 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 4358 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4359 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4360 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 4361 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 4362 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 4363 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 4364 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4365 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4366 //MMEA0_ADDRDEC1_RM_SEL_SECCS23 4367 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 4368 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 4369 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 4370 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 4371 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4372 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4373 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 4374 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 4375 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 4376 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 4377 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4378 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4379 //MMEA0_IO_RD_CLI2GRP_MAP0 4380 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4381 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4382 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4383 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4384 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4385 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4386 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4387 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4388 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4389 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4390 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4391 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4392 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4393 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4394 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4395 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4396 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4397 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4398 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4399 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4400 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4401 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4402 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4403 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4404 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4405 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4406 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4407 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4408 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4409 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4410 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4411 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4412 //MMEA0_IO_RD_CLI2GRP_MAP1 4413 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4414 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4415 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4416 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4417 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4418 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4419 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4420 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4421 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4422 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4423 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4424 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4425 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4426 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4427 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4428 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4429 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4430 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4431 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4432 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4433 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4434 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4435 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4436 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4437 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4438 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4439 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4440 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4441 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4442 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4443 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4444 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4445 //MMEA0_IO_WR_CLI2GRP_MAP0 4446 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4447 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4448 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4449 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4450 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4451 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4452 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4453 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4454 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4455 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4456 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4457 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4458 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4459 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4460 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4461 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4462 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4463 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4464 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4465 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4466 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4467 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4468 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4469 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4470 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4471 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4472 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4473 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4474 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4475 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4476 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4477 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4478 //MMEA0_IO_WR_CLI2GRP_MAP1 4479 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4480 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4481 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4482 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4483 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4484 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4485 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4486 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4487 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4488 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4489 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4490 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4491 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4492 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4493 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4494 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4495 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4496 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4497 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4498 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4499 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4500 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4501 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4502 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4503 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4504 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4505 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4506 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4507 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4508 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4509 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4510 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4511 //MMEA0_IO_RD_COMBINE_FLUSH 4512 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4513 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4514 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4515 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4516 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4517 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4518 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4519 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4520 //MMEA0_IO_WR_COMBINE_FLUSH 4521 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4522 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4523 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4524 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4525 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4526 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4527 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4528 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4529 //MMEA0_IO_GROUP_BURST 4530 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 4531 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 4532 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 4533 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 4534 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 4535 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 4536 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 4537 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 4538 //MMEA0_IO_RD_PRI_AGE 4539 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4540 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4541 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4542 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4543 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4544 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4545 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4546 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4547 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4548 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4549 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4550 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4551 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4552 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4553 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4554 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4555 //MMEA0_IO_WR_PRI_AGE 4556 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4557 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4558 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4559 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4560 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4561 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4562 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4563 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4564 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4565 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4566 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4567 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4568 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4569 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4570 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4571 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4572 //MMEA0_IO_RD_PRI_QUEUING 4573 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4574 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4575 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4576 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4577 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4578 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4579 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4580 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4581 //MMEA0_IO_WR_PRI_QUEUING 4582 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4583 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4584 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4585 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4586 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4587 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4588 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4589 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4590 //MMEA0_IO_RD_PRI_FIXED 4591 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4592 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4593 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4594 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4595 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4596 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4597 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4598 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4599 //MMEA0_IO_WR_PRI_FIXED 4600 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4601 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4602 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4603 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4604 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4605 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4606 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4607 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4608 //MMEA0_IO_RD_PRI_URGENCY 4609 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4610 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4611 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4612 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4613 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4614 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4615 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4616 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4617 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4618 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4619 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4620 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4621 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4622 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4623 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4624 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4625 //MMEA0_IO_WR_PRI_URGENCY 4626 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4627 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4628 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4629 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4630 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4631 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4632 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4633 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4634 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4635 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4636 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4637 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4638 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4639 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4640 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4641 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4642 //MMEA0_IO_RD_PRI_URGENCY_MASK 4643 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4644 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4645 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4646 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4647 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4648 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4649 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4650 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4651 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4652 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4653 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4654 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4655 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4656 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4657 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4658 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4659 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4660 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4661 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4662 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4663 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4664 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4665 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4666 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4667 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4668 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4669 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4670 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4671 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4672 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4673 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4674 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4675 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4676 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4677 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4678 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4679 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4680 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4681 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4682 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4683 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4684 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4685 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4686 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4687 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4688 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4689 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4690 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4691 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4692 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4693 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4694 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4695 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4696 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4697 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4698 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4699 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4700 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4701 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4702 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4703 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4704 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4705 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4706 #define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4707 //MMEA0_IO_WR_PRI_URGENCY_MASK 4708 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4709 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4710 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4711 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4712 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4713 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4714 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4715 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4716 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4717 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4718 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4719 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4720 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4721 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4722 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4723 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4724 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4725 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4726 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4727 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4728 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4729 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4730 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4731 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4732 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4733 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4734 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4735 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4736 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4737 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4738 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4739 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4740 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4741 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4742 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4743 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4744 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4745 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4746 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4747 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4748 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4749 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4750 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4751 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4752 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4753 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4754 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4755 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4756 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4757 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4758 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4759 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4760 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4761 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4762 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4763 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4764 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4765 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4766 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4767 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4768 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4769 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4770 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4771 #define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4772 //MMEA0_IO_RD_PRI_QUANT_PRI1 4773 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4774 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4775 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4776 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4777 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4778 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4779 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4780 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4781 //MMEA0_IO_RD_PRI_QUANT_PRI2 4782 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4783 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4784 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4785 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4786 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4787 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4788 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4789 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4790 //MMEA0_IO_RD_PRI_QUANT_PRI3 4791 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4792 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4793 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4794 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4795 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4796 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4797 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4798 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4799 //MMEA0_IO_WR_PRI_QUANT_PRI1 4800 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4801 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4802 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4803 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4804 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4805 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4806 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4807 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4808 //MMEA0_IO_WR_PRI_QUANT_PRI2 4809 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4810 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4811 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4812 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4813 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4814 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4815 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4816 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4817 //MMEA0_IO_WR_PRI_QUANT_PRI3 4818 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4819 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4820 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4821 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4822 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4823 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4824 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4825 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4826 //MMEA0_SDP_ARB_DRAM 4827 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 4828 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 4829 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 4830 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 4831 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 4832 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 4833 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 4834 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 4835 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 4836 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 4837 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 4838 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 4839 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 4840 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 4841 //MMEA0_SDP_ARB_FINAL 4842 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 4843 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 4844 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 4845 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 4846 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 4847 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 4848 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 4849 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 4850 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 4851 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 4852 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 4853 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 4854 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 4855 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 4856 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 4857 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 4858 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 4859 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 4860 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 4861 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 4862 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 4863 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 4864 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 4865 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 4866 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 4867 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 4868 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 4869 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 4870 //MMEA0_SDP_DRAM_PRIORITY 4871 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4872 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4873 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4874 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4875 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4876 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4877 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4878 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4879 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4880 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4881 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4882 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4883 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4884 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4885 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4886 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4887 //MMEA0_SDP_IO_PRIORITY 4888 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4889 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4890 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4891 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4892 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4893 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4894 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4895 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4896 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4897 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4898 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4899 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4900 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4901 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4902 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4903 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4904 //MMEA0_SDP_CREDITS 4905 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 4906 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 4907 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 4908 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 4909 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 4910 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 4911 //MMEA0_SDP_TAG_RESERVE0 4912 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 4913 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 4914 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 4915 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 4916 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 4917 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 4918 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 4919 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 4920 //MMEA0_SDP_TAG_RESERVE1 4921 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 4922 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 4923 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 4924 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 4925 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 4926 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 4927 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 4928 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 4929 //MMEA0_SDP_VCC_RESERVE0 4930 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 4931 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 4932 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 4933 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 4934 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 4935 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4936 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4937 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4938 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4939 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4940 //MMEA0_SDP_VCC_RESERVE1 4941 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 4942 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 4943 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 4944 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4945 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4946 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4947 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4948 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4949 //MMEA0_SDP_VCD_RESERVE0 4950 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 4951 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 4952 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 4953 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 4954 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 4955 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4956 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4957 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4958 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4959 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4960 //MMEA0_SDP_VCD_RESERVE1 4961 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 4962 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 4963 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 4964 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4965 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4966 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4967 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4968 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4969 //MMEA0_SDP_REQ_CNTL 4970 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 4971 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 4972 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 4973 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 4974 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 4975 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 4976 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 4977 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 4978 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 4979 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 4980 //MMEA0_MISC 4981 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 4982 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 4983 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 4984 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 4985 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 4986 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 4987 #define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 4988 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 4989 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 4990 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 4991 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 4992 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 4993 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 4994 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 4995 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 4996 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 4997 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 4998 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 4999 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 5000 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 5001 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 5002 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 5003 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 5004 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 5005 #define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L 5006 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 5007 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 5008 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 5009 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 5010 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 5011 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 5012 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 5013 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 5014 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 5015 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 5016 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 5017 //MMEA0_LATENCY_SAMPLING 5018 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 5019 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 5020 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 5021 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 5022 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 5023 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 5024 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 5025 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 5026 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 5027 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 5028 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 5029 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 5030 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 5031 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 5032 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 5033 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 5034 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 5035 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 5036 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 5037 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 5038 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 5039 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 5040 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 5041 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 5042 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 5043 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 5044 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 5045 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 5046 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 5047 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 5048 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 5049 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 5050 //MMEA0_PERFCOUNTER_LO 5051 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5052 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 5053 //MMEA0_PERFCOUNTER_HI 5054 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5055 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5056 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 5057 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 5058 //MMEA0_PERFCOUNTER0_CFG 5059 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5060 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5061 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5062 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5063 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5064 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5065 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5066 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5067 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5068 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5069 //MMEA0_PERFCOUNTER1_CFG 5070 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5071 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5072 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5073 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5074 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5075 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5076 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5077 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5078 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5079 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5080 //MMEA0_PERFCOUNTER_RSLT_CNTL 5081 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5082 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5083 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5084 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5085 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5086 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5087 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5088 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5089 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5090 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5091 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5092 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5093 //MMEA0_EDC_CNT 5094 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5095 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 5096 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5097 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 5098 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5099 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 5100 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 5101 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 5102 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 5103 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 5104 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 5105 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 5106 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 5107 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 5108 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 5109 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5110 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5111 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5112 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5113 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5114 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5115 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 5116 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 5117 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 5118 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 5119 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 5120 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 5121 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 5122 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 5123 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 5124 //MMEA0_EDC_CNT2 5125 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5126 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 5127 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5128 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 5129 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5130 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 5131 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 5132 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 5133 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5134 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5135 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5136 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5137 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5138 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5139 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 5140 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 5141 //MMEA0_DSM_CNTL 5142 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5143 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5144 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5145 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5146 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5147 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5148 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5149 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5150 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5151 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5152 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5153 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5154 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5155 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5156 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 5157 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 5158 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5159 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5160 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5161 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5162 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5163 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5164 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5165 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5166 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5167 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5168 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5169 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5170 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5171 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5172 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 5173 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 5174 //MMEA0_DSM_CNTLA 5175 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5176 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5177 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5178 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5179 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5180 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5181 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5182 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5183 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5184 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5185 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5186 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5187 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5188 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5189 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5190 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5191 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5192 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5193 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5194 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5195 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5196 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5197 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5198 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5199 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5200 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5201 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5202 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5203 //MMEA0_DSM_CNTLB 5204 //MMEA0_DSM_CNTL2 5205 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5206 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5207 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5208 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5209 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5210 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5211 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5212 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5213 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5214 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5215 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5216 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5217 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5218 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5219 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 5220 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 5221 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 5222 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5223 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5224 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5225 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5226 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5227 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5228 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5229 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5230 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5231 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5232 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5233 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5234 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5235 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5236 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 5237 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 5238 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 5239 //MMEA0_DSM_CNTL2A 5240 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5241 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5242 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5243 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5244 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5245 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5246 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5247 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5248 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5249 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5250 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5251 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5252 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5253 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5254 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5255 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5256 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5257 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5258 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5259 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5260 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5261 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5262 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5263 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5264 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5265 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5266 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5267 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5268 //MMEA0_DSM_CNTL2B 5269 //MMEA0_CGTT_CLK_CTRL 5270 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5271 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5272 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 5273 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 5274 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 5275 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5276 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 5277 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 5278 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 5279 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 5280 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5281 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5282 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 5283 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 5284 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 5285 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5286 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 5287 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 5288 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 5289 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 5290 //MMEA0_EDC_MODE 5291 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 5292 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 5293 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 5294 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 5295 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 5296 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 5297 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 5298 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 5299 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 5300 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 5301 //MMEA0_ERR_STATUS 5302 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 5303 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 5304 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 5305 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 5306 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 5307 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 5308 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 5309 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 5310 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 5311 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 5312 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 5313 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 5314 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 5315 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 5316 //MMEA0_MISC2 5317 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 5318 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 5319 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 5320 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 5321 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 5322 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 5323 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 5324 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 5325 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 5326 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 5327 //MMEA1_DRAM_RD_CLI2GRP_MAP0 5328 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5329 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5330 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5331 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5332 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5333 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5334 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5335 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5336 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5337 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5338 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5339 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5340 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5341 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5342 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5343 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5344 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5345 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5346 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5347 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5348 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5349 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5350 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5351 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5352 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5353 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5354 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5355 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5356 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5357 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5358 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5359 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5360 //MMEA1_DRAM_RD_CLI2GRP_MAP1 5361 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5362 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5363 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5364 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5365 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5366 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5367 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5368 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5369 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5370 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5371 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5372 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5373 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5374 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5375 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5376 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5377 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5378 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5379 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5380 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5381 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5382 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5383 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5384 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5385 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5386 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5387 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5388 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5389 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5390 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5391 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5392 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5393 //MMEA1_DRAM_WR_CLI2GRP_MAP0 5394 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5395 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5396 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5397 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5398 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5399 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5400 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5401 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5402 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5403 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5404 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5405 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5406 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5407 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5408 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5409 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5410 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5411 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5412 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5413 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5414 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5415 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5416 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5417 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5418 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5419 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5420 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5421 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5422 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5423 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5424 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5425 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5426 //MMEA1_DRAM_WR_CLI2GRP_MAP1 5427 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5428 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5429 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5430 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5431 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5432 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5433 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5434 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5435 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5436 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5437 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5438 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5439 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5440 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5441 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5442 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5443 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5444 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5445 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5446 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5447 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5448 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5449 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5450 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5451 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5452 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5453 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5454 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5455 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5456 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5457 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5458 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5459 //MMEA1_DRAM_RD_GRP2VC_MAP 5460 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 5461 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 5462 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 5463 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 5464 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 5465 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 5466 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 5467 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 5468 //MMEA1_DRAM_WR_GRP2VC_MAP 5469 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 5470 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 5471 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 5472 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 5473 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 5474 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 5475 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 5476 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 5477 //MMEA1_DRAM_RD_LAZY 5478 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 5479 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 5480 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 5481 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 5482 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 5483 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 5484 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 5485 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 5486 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 5487 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 5488 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 5489 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 5490 //MMEA1_DRAM_WR_LAZY 5491 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 5492 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 5493 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 5494 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 5495 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 5496 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 5497 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 5498 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 5499 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 5500 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 5501 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 5502 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 5503 //MMEA1_DRAM_RD_CAM_CNTL 5504 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 5505 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 5506 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 5507 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 5508 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 5509 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 5510 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 5511 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 5512 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 5513 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 5514 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 5515 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 5516 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 5517 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 5518 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 5519 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 5520 //MMEA1_DRAM_WR_CAM_CNTL 5521 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 5522 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 5523 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 5524 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 5525 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 5526 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 5527 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 5528 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 5529 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 5530 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 5531 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 5532 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 5533 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 5534 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 5535 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 5536 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 5537 //MMEA1_DRAM_PAGE_BURST 5538 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 5539 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 5540 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 5541 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 5542 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 5543 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 5544 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 5545 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 5546 //MMEA1_DRAM_RD_PRI_AGE 5547 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5548 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5549 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5550 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5551 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5552 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5553 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5554 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5555 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5556 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5557 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5558 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5559 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5560 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5561 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5562 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5563 //MMEA1_DRAM_WR_PRI_AGE 5564 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5565 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5566 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5567 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5568 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5569 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5570 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5571 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5572 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5573 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5574 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5575 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5576 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5577 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5578 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5579 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5580 //MMEA1_DRAM_RD_PRI_QUEUING 5581 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5582 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5583 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5584 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5585 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5586 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5587 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5588 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5589 //MMEA1_DRAM_WR_PRI_QUEUING 5590 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5591 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5592 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5593 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5594 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5595 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5596 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5597 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5598 //MMEA1_DRAM_RD_PRI_FIXED 5599 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5600 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5601 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5602 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5603 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5604 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5605 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5606 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5607 //MMEA1_DRAM_WR_PRI_FIXED 5608 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5609 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5610 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5611 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5612 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5613 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5614 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5615 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5616 //MMEA1_DRAM_RD_PRI_URGENCY 5617 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5618 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5619 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5620 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5621 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5622 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5623 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5624 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5625 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5626 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5627 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5628 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5629 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5630 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5631 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5632 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5633 //MMEA1_DRAM_WR_PRI_URGENCY 5634 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5635 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5636 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5637 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5638 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5639 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5640 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5641 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5642 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5643 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5644 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5645 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5646 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5647 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5648 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5649 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5650 //MMEA1_DRAM_RD_PRI_QUANT_PRI1 5651 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5652 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5653 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5654 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5655 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5656 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5657 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5658 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5659 //MMEA1_DRAM_RD_PRI_QUANT_PRI2 5660 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5661 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5662 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5663 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5664 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5665 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5666 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5667 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5668 //MMEA1_DRAM_RD_PRI_QUANT_PRI3 5669 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5670 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5671 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5672 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5673 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5674 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5675 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5676 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5677 //MMEA1_DRAM_WR_PRI_QUANT_PRI1 5678 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5679 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5680 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5681 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5682 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5683 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5684 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5685 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5686 //MMEA1_DRAM_WR_PRI_QUANT_PRI2 5687 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5688 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5689 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5690 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5691 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5692 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5693 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5694 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5695 //MMEA1_DRAM_WR_PRI_QUANT_PRI3 5696 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5697 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5698 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5699 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5700 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5701 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5702 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5703 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5704 //MMEA1_ADDRNORM_BASE_ADDR0 5705 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 5706 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5707 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 5708 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 5709 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 5710 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 5711 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5712 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 5713 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 5714 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 5715 //MMEA1_ADDRNORM_LIMIT_ADDR0 5716 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 5717 #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 5718 #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 5719 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 5720 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 5721 #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 5722 #define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 5723 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 5724 //MMEA1_ADDRNORM_BASE_ADDR1 5725 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 5726 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5727 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 5728 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 5729 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 5730 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 5731 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5732 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 5733 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 5734 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 5735 //MMEA1_ADDRNORM_LIMIT_ADDR1 5736 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 5737 #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 5738 #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 5739 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 5740 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 5741 #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 5742 #define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 5743 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 5744 //MMEA1_ADDRNORM_OFFSET_ADDR1 5745 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 5746 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 5747 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 5748 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 5749 //MMEA1_ADDRNORMDRAM_HOLE_CNTL 5750 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 5751 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 5752 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 5753 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 5754 //MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG 5755 #define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE__SHIFT 0x0 5756 #define MMEA1_ADDRNORMDRAM_TRICHANNEL_CFG__LOG2_ADDR64K_SPACE_MASK 0x0000003FL 5757 //MMEA1_ADDRDEC_BANK_CFG 5758 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 5759 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 5760 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 5761 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 5762 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 5763 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 5764 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 5765 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 5766 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 5767 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 5768 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 5769 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 5770 //MMEA1_ADDRDEC_MISC_CFG 5771 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 5772 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 5773 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 5774 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 5775 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 5776 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 5777 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 5778 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 5779 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 5780 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 5781 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 5782 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 5783 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 5784 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 5785 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 5786 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 5787 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 5788 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 5789 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 5790 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 5791 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 5792 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 5793 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 5794 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 5795 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 5796 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 5797 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 5798 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 5799 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 5800 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 5801 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 5802 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 5803 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 5804 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 5805 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 5806 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 5807 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 5808 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 5809 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 5810 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 5811 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 5812 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 5813 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 5814 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 5815 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 5816 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 5817 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 5818 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 5819 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 5820 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 5821 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 5822 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 5823 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 5824 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 5825 //MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 5826 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 5827 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 5828 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 5829 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 5830 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 5831 #define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 5832 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC 5833 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 5834 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 5835 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 5836 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 5837 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 5838 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 5839 //MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 5840 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 5841 #define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 5842 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 5843 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 5844 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 5845 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 5846 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 5847 //MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 5848 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 5849 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 5850 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 5851 #define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 5852 //MMEA1_ADDRDECDRAM_HARVEST_ENABLE 5853 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 5854 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 5855 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 5856 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 5857 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 5858 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 5859 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 5860 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 5861 //MMEA1_ADDRDEC0_BASE_ADDR_CS0 5862 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 5863 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 5864 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 5865 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 5866 //MMEA1_ADDRDEC0_BASE_ADDR_CS1 5867 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 5868 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 5869 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 5870 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 5871 //MMEA1_ADDRDEC0_BASE_ADDR_CS2 5872 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 5873 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 5874 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 5875 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 5876 //MMEA1_ADDRDEC0_BASE_ADDR_CS3 5877 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 5878 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 5879 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 5880 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 5881 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 5882 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 5883 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 5884 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 5885 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 5886 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 5887 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 5888 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 5889 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 5890 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 5891 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 5892 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 5893 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 5894 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 5895 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 5896 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 5897 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 5898 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 5899 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 5900 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 5901 //MMEA1_ADDRDEC0_ADDR_MASK_CS01 5902 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 5903 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 5904 //MMEA1_ADDRDEC0_ADDR_MASK_CS23 5905 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 5906 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 5907 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 5908 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 5909 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 5910 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 5911 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 5912 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 5913 //MMEA1_ADDRDEC0_ADDR_CFG_CS01 5914 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 5915 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 5916 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 5917 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 5918 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 5919 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 5920 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 5921 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 5922 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 5923 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 5924 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 5925 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 5926 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 5927 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 5928 //MMEA1_ADDRDEC0_ADDR_CFG_CS23 5929 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 5930 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 5931 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 5932 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 5933 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 5934 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 5935 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 5936 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 5937 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 5938 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 5939 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 5940 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 5941 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 5942 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 5943 //MMEA1_ADDRDEC0_ADDR_SEL_CS01 5944 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 5945 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 5946 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 5947 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 5948 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 5949 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 5950 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 5951 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 5952 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 5953 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 5954 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 5955 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 5956 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 5957 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 5958 //MMEA1_ADDRDEC0_ADDR_SEL_CS23 5959 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 5960 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 5961 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 5962 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 5963 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 5964 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 5965 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 5966 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 5967 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 5968 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 5969 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 5970 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 5971 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 5972 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 5973 //MMEA1_ADDRDEC0_COL_SEL_LO_CS01 5974 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 5975 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 5976 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 5977 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 5978 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 5979 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 5980 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 5981 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 5982 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 5983 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 5984 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 5985 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 5986 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 5987 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 5988 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 5989 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 5990 //MMEA1_ADDRDEC0_COL_SEL_LO_CS23 5991 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 5992 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 5993 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 5994 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 5995 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 5996 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 5997 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 5998 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 5999 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 6000 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 6001 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 6002 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 6003 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 6004 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 6005 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 6006 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 6007 //MMEA1_ADDRDEC0_COL_SEL_HI_CS01 6008 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 6009 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 6010 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 6011 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 6012 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 6013 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 6014 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 6015 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 6016 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 6017 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 6018 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 6019 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 6020 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 6021 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 6022 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 6023 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 6024 //MMEA1_ADDRDEC0_COL_SEL_HI_CS23 6025 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 6026 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 6027 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 6028 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 6029 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 6030 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 6031 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 6032 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 6033 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 6034 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 6035 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 6036 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 6037 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 6038 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 6039 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 6040 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 6041 //MMEA1_ADDRDEC0_RM_SEL_CS01 6042 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 6043 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 6044 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 6045 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 6046 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6047 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6048 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 6049 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 6050 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 6051 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 6052 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6053 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6054 //MMEA1_ADDRDEC0_RM_SEL_CS23 6055 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 6056 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 6057 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 6058 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 6059 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6060 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6061 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 6062 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 6063 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 6064 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 6065 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6066 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6067 //MMEA1_ADDRDEC0_RM_SEL_SECCS01 6068 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 6069 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 6070 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 6071 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 6072 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6073 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6074 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 6075 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 6076 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 6077 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 6078 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6079 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6080 //MMEA1_ADDRDEC0_RM_SEL_SECCS23 6081 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 6082 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 6083 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 6084 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 6085 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6086 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6087 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 6088 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 6089 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 6090 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 6091 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6092 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6093 //MMEA1_ADDRDEC1_BASE_ADDR_CS0 6094 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 6095 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 6096 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 6097 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 6098 //MMEA1_ADDRDEC1_BASE_ADDR_CS1 6099 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 6100 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 6101 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 6102 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 6103 //MMEA1_ADDRDEC1_BASE_ADDR_CS2 6104 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 6105 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 6106 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 6107 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 6108 //MMEA1_ADDRDEC1_BASE_ADDR_CS3 6109 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 6110 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 6111 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 6112 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 6113 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 6114 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 6115 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 6116 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 6117 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 6118 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 6119 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 6120 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 6121 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 6122 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 6123 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 6124 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 6125 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 6126 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 6127 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 6128 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 6129 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 6130 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 6131 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 6132 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 6133 //MMEA1_ADDRDEC1_ADDR_MASK_CS01 6134 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 6135 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 6136 //MMEA1_ADDRDEC1_ADDR_MASK_CS23 6137 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 6138 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 6139 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 6140 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 6141 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 6142 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 6143 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 6144 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 6145 //MMEA1_ADDRDEC1_ADDR_CFG_CS01 6146 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 6147 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 6148 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 6149 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 6150 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 6151 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 6152 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 6153 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 6154 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 6155 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 6156 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 6157 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 6158 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 6159 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 6160 //MMEA1_ADDRDEC1_ADDR_CFG_CS23 6161 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 6162 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 6163 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 6164 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 6165 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 6166 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 6167 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 6168 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 6169 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 6170 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 6171 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 6172 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 6173 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 6174 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 6175 //MMEA1_ADDRDEC1_ADDR_SEL_CS01 6176 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 6177 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 6178 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 6179 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 6180 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 6181 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 6182 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 6183 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 6184 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 6185 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 6186 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 6187 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 6188 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 6189 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 6190 //MMEA1_ADDRDEC1_ADDR_SEL_CS23 6191 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 6192 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 6193 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 6194 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 6195 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 6196 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 6197 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 6198 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 6199 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 6200 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 6201 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 6202 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 6203 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 6204 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 6205 //MMEA1_ADDRDEC1_COL_SEL_LO_CS01 6206 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 6207 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 6208 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 6209 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 6210 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 6211 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 6212 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 6213 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 6214 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 6215 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 6216 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 6217 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 6218 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 6219 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 6220 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 6221 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 6222 //MMEA1_ADDRDEC1_COL_SEL_LO_CS23 6223 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 6224 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 6225 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 6226 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 6227 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 6228 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 6229 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 6230 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 6231 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 6232 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 6233 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 6234 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 6235 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 6236 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 6237 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 6238 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 6239 //MMEA1_ADDRDEC1_COL_SEL_HI_CS01 6240 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 6241 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 6242 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 6243 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 6244 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 6245 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 6246 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 6247 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 6248 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 6249 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 6250 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 6251 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 6252 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 6253 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 6254 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 6255 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 6256 //MMEA1_ADDRDEC1_COL_SEL_HI_CS23 6257 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 6258 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 6259 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 6260 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 6261 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 6262 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 6263 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 6264 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 6265 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 6266 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 6267 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 6268 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 6269 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 6270 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 6271 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 6272 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 6273 //MMEA1_ADDRDEC1_RM_SEL_CS01 6274 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 6275 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 6276 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 6277 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 6278 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6279 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6280 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 6281 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 6282 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 6283 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 6284 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6285 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6286 //MMEA1_ADDRDEC1_RM_SEL_CS23 6287 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 6288 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 6289 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 6290 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 6291 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6292 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6293 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 6294 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 6295 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 6296 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 6297 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6298 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6299 //MMEA1_ADDRDEC1_RM_SEL_SECCS01 6300 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 6301 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 6302 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 6303 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 6304 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6305 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6306 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 6307 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 6308 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 6309 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 6310 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6311 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6312 //MMEA1_ADDRDEC1_RM_SEL_SECCS23 6313 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 6314 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 6315 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 6316 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 6317 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6318 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6319 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 6320 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 6321 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 6322 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 6323 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6324 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6325 //MMEA1_IO_RD_CLI2GRP_MAP0 6326 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 6327 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 6328 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 6329 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 6330 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 6331 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 6332 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 6333 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 6334 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 6335 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 6336 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 6337 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 6338 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 6339 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 6340 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 6341 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 6342 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 6343 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 6344 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 6345 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 6346 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 6347 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 6348 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 6349 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 6350 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 6351 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 6352 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 6353 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 6354 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 6355 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 6356 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 6357 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 6358 //MMEA1_IO_RD_CLI2GRP_MAP1 6359 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 6360 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 6361 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 6362 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 6363 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 6364 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 6365 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 6366 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 6367 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 6368 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 6369 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 6370 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 6371 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 6372 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 6373 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 6374 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 6375 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 6376 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 6377 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 6378 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 6379 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 6380 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 6381 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 6382 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 6383 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 6384 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 6385 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 6386 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 6387 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 6388 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 6389 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 6390 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 6391 //MMEA1_IO_WR_CLI2GRP_MAP0 6392 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 6393 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 6394 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 6395 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 6396 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 6397 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 6398 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 6399 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 6400 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 6401 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 6402 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 6403 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 6404 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 6405 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 6406 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 6407 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 6408 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 6409 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 6410 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 6411 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 6412 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 6413 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 6414 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 6415 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 6416 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 6417 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 6418 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 6419 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 6420 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 6421 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 6422 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 6423 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 6424 //MMEA1_IO_WR_CLI2GRP_MAP1 6425 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 6426 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 6427 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 6428 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 6429 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 6430 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 6431 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 6432 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 6433 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 6434 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 6435 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 6436 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 6437 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 6438 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 6439 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 6440 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 6441 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 6442 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 6443 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 6444 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 6445 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 6446 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 6447 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 6448 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 6449 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 6450 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 6451 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 6452 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 6453 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 6454 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 6455 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 6456 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 6457 //MMEA1_IO_RD_COMBINE_FLUSH 6458 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 6459 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 6460 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 6461 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 6462 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 6463 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 6464 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 6465 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 6466 //MMEA1_IO_WR_COMBINE_FLUSH 6467 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 6468 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 6469 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 6470 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 6471 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 6472 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 6473 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 6474 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 6475 //MMEA1_IO_GROUP_BURST 6476 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 6477 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 6478 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 6479 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 6480 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 6481 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 6482 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 6483 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 6484 //MMEA1_IO_RD_PRI_AGE 6485 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 6486 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 6487 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 6488 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 6489 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 6490 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 6491 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 6492 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 6493 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 6494 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 6495 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 6496 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 6497 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 6498 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 6499 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 6500 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 6501 //MMEA1_IO_WR_PRI_AGE 6502 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 6503 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 6504 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 6505 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 6506 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 6507 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 6508 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 6509 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 6510 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 6511 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 6512 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 6513 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 6514 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 6515 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 6516 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 6517 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 6518 //MMEA1_IO_RD_PRI_QUEUING 6519 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 6520 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 6521 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 6522 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 6523 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 6524 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 6525 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 6526 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 6527 //MMEA1_IO_WR_PRI_QUEUING 6528 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 6529 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 6530 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 6531 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 6532 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 6533 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 6534 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 6535 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 6536 //MMEA1_IO_RD_PRI_FIXED 6537 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 6538 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 6539 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 6540 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 6541 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 6542 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 6543 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 6544 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 6545 //MMEA1_IO_WR_PRI_FIXED 6546 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 6547 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 6548 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 6549 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 6550 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 6551 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 6552 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 6553 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 6554 //MMEA1_IO_RD_PRI_URGENCY 6555 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 6556 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 6557 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 6558 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 6559 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 6560 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 6561 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 6562 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 6563 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 6564 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 6565 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 6566 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 6567 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 6568 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 6569 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 6570 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 6571 //MMEA1_IO_WR_PRI_URGENCY 6572 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 6573 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 6574 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 6575 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 6576 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 6577 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 6578 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 6579 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 6580 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 6581 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 6582 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 6583 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 6584 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 6585 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 6586 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 6587 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 6588 //MMEA1_IO_RD_PRI_URGENCY_MASK 6589 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 6590 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 6591 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 6592 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 6593 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6594 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6595 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6596 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6597 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6598 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6599 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6600 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6601 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6602 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6603 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6604 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6605 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6606 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6607 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6608 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6609 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6610 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6611 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6612 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6613 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6614 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6615 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6616 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6617 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6618 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6619 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6620 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6621 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6622 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6623 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6624 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6625 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6626 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6627 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6628 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6629 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6630 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6631 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6632 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6633 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6634 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6635 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6636 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6637 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6638 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6639 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6640 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6641 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6642 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6643 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6644 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6645 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6646 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6647 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6648 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6649 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6650 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6651 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6652 #define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6653 //MMEA1_IO_WR_PRI_URGENCY_MASK 6654 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 6655 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 6656 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 6657 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 6658 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6659 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6660 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6661 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6662 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6663 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6664 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6665 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6666 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6667 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6668 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6669 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6670 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6671 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6672 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6673 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6674 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6675 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6676 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6677 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6678 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6679 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6680 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6681 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6682 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6683 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6684 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6685 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6686 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6687 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6688 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6689 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6690 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6691 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6692 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6693 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6694 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6695 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6696 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6697 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6698 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6699 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6700 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6701 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6702 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6703 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6704 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6705 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6706 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6707 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6708 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6709 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6710 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6711 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6712 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6713 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6714 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6715 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6716 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6717 #define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6718 //MMEA1_IO_RD_PRI_QUANT_PRI1 6719 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6720 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6721 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6722 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6723 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6724 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6725 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6726 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6727 //MMEA1_IO_RD_PRI_QUANT_PRI2 6728 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6729 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6730 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6731 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6732 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6733 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6734 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6735 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6736 //MMEA1_IO_RD_PRI_QUANT_PRI3 6737 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6738 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6739 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6740 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6741 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6742 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6743 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6744 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6745 //MMEA1_IO_WR_PRI_QUANT_PRI1 6746 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6747 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6748 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6749 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6750 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6751 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6752 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6753 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6754 //MMEA1_IO_WR_PRI_QUANT_PRI2 6755 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6756 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6757 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6758 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6759 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6760 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6761 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6762 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6763 //MMEA1_IO_WR_PRI_QUANT_PRI3 6764 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6765 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6766 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6767 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6768 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6769 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6770 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6771 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6772 //MMEA1_SDP_ARB_DRAM 6773 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 6774 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 6775 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 6776 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 6777 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 6778 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 6779 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 6780 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 6781 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 6782 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 6783 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 6784 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 6785 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 6786 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 6787 //MMEA1_SDP_ARB_FINAL 6788 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 6789 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 6790 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 6791 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 6792 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 6793 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 6794 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 6795 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 6796 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 6797 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 6798 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 6799 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 6800 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 6801 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 6802 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 6803 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 6804 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 6805 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 6806 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 6807 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 6808 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 6809 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 6810 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 6811 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 6812 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 6813 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 6814 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 6815 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 6816 //MMEA1_SDP_DRAM_PRIORITY 6817 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6818 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6819 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6820 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6821 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6822 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6823 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6824 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6825 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6826 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6827 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6828 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6829 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6830 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6831 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6832 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6833 //MMEA1_SDP_IO_PRIORITY 6834 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6835 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6836 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6837 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6838 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6839 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6840 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6841 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6842 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6843 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6844 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6845 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6846 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6847 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6848 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6849 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6850 //MMEA1_SDP_CREDITS 6851 #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 6852 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 6853 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 6854 #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 6855 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 6856 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 6857 //MMEA1_SDP_TAG_RESERVE0 6858 #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 6859 #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 6860 #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 6861 #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 6862 #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 6863 #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 6864 #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 6865 #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 6866 //MMEA1_SDP_TAG_RESERVE1 6867 #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 6868 #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 6869 #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 6870 #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 6871 #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 6872 #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 6873 #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 6874 #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 6875 //MMEA1_SDP_VCC_RESERVE0 6876 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 6877 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 6878 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 6879 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 6880 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 6881 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6882 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6883 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6884 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6885 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6886 //MMEA1_SDP_VCC_RESERVE1 6887 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 6888 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 6889 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 6890 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6891 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6892 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6893 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6894 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6895 //MMEA1_SDP_VCD_RESERVE0 6896 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 6897 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 6898 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 6899 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 6900 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 6901 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6902 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6903 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6904 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6905 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6906 //MMEA1_SDP_VCD_RESERVE1 6907 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 6908 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 6909 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 6910 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6911 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6912 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6913 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6914 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6915 //MMEA1_SDP_REQ_CNTL 6916 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 6917 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 6918 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 6919 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 6920 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 6921 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 6922 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 6923 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 6924 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 6925 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 6926 //MMEA1_MISC 6927 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 6928 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 6929 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 6930 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 6931 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 6932 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 6933 #define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 6934 #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 6935 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 6936 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 6937 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 6938 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 6939 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 6940 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 6941 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 6942 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 6943 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 6944 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 6945 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 6946 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 6947 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 6948 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 6949 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 6950 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 6951 #define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L 6952 #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 6953 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 6954 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 6955 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 6956 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 6957 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 6958 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 6959 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 6960 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 6961 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 6962 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 6963 //MMEA1_LATENCY_SAMPLING 6964 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 6965 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 6966 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 6967 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 6968 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 6969 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 6970 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 6971 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 6972 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 6973 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 6974 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 6975 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 6976 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 6977 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 6978 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 6979 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 6980 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 6981 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 6982 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 6983 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 6984 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 6985 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 6986 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 6987 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 6988 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 6989 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 6990 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 6991 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 6992 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 6993 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 6994 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 6995 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 6996 //MMEA1_PERFCOUNTER_LO 6997 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6998 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6999 //MMEA1_PERFCOUNTER_HI 7000 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7001 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7002 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7003 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7004 //MMEA1_PERFCOUNTER0_CFG 7005 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7006 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7007 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7008 #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7009 #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7010 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7011 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7012 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7013 #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7014 #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7015 //MMEA1_PERFCOUNTER1_CFG 7016 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7017 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7018 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7019 #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7020 #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7021 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7022 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7023 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7024 #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7025 #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7026 //MMEA1_PERFCOUNTER_RSLT_CNTL 7027 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7028 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7029 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7030 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7031 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7032 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7033 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7034 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7035 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7036 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7037 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7038 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7039 //MMEA1_EDC_CNT 7040 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 7041 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 7042 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 7043 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 7044 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 7045 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 7046 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 7047 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 7048 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 7049 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 7050 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 7051 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 7052 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 7053 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 7054 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 7055 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 7056 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 7057 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 7058 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 7059 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 7060 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 7061 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 7062 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 7063 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 7064 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 7065 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 7066 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 7067 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 7068 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 7069 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 7070 //MMEA1_EDC_CNT2 7071 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 7072 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 7073 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 7074 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 7075 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 7076 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 7077 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 7078 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 7079 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 7080 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 7081 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 7082 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 7083 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 7084 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 7085 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 7086 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 7087 //MMEA1_DSM_CNTL 7088 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 7089 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 7090 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 7091 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 7092 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 7093 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 7094 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 7095 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 7096 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 7097 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 7098 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 7099 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 7100 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 7101 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 7102 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 7103 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 7104 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 7105 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 7106 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 7107 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 7108 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 7109 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 7110 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 7111 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 7112 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 7113 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 7114 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 7115 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 7116 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 7117 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 7118 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 7119 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 7120 //MMEA1_DSM_CNTLA 7121 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 7122 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 7123 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 7124 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 7125 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 7126 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 7127 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 7128 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 7129 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 7130 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 7131 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 7132 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 7133 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 7134 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 7135 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 7136 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 7137 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 7138 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 7139 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 7140 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 7141 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 7142 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 7143 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 7144 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 7145 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 7146 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 7147 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 7148 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 7149 //MMEA1_DSM_CNTLB 7150 //MMEA1_DSM_CNTL2 7151 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 7152 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 7153 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 7154 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 7155 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 7156 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 7157 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 7158 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 7159 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 7160 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 7161 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 7162 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 7163 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 7164 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 7165 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 7166 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 7167 #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 7168 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 7169 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 7170 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 7171 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 7172 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 7173 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 7174 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 7175 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 7176 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 7177 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 7178 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 7179 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 7180 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 7181 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 7182 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 7183 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 7184 #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 7185 //MMEA1_DSM_CNTL2A 7186 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 7187 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 7188 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 7189 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 7190 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 7191 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 7192 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 7193 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 7194 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 7195 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 7196 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 7197 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 7198 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 7199 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 7200 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 7201 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 7202 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 7203 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 7204 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 7205 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 7206 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 7207 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 7208 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 7209 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 7210 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 7211 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 7212 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 7213 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 7214 //MMEA1_DSM_CNTL2B 7215 //MMEA1_CGTT_CLK_CTRL 7216 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7217 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7218 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 7219 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 7220 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 7221 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7222 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 7223 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 7224 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 7225 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 7226 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7227 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7228 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 7229 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 7230 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 7231 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7232 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 7233 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 7234 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 7235 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 7236 //MMEA1_EDC_MODE 7237 #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 7238 #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 7239 #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 7240 #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 7241 #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 7242 #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 7243 #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 7244 #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 7245 #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 7246 #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 7247 //MMEA1_ERR_STATUS 7248 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 7249 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 7250 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 7251 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 7252 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 7253 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 7254 #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd 7255 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 7256 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 7257 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 7258 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 7259 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 7260 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 7261 #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 7262 //MMEA1_MISC2 7263 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 7264 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 7265 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 7266 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 7267 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 7268 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 7269 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 7270 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 7271 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 7272 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 7273 7274 7275 // addressBlock: mmhub_pctldec 7276 //PCTL_MISC 7277 #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 7278 #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 7279 #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 7280 #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 7281 #define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc 7282 #define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd 7283 #define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe 7284 #define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 7285 #define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 7286 #define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 7287 #define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 7288 #define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L 7289 #define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L 7290 #define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L 7291 //PCTL_MMHUB_DEEPSLEEP 7292 #define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 7293 #define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 7294 #define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 7295 #define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 7296 #define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 7297 #define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 7298 #define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 7299 #define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 7300 #define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 7301 #define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 7302 #define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 7303 #define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 7304 #define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 7305 #define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 7306 #define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 7307 #define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 7308 #define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 7309 #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 7310 #define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 7311 #define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 7312 #define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 7313 #define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 7314 #define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 7315 #define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 7316 #define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 7317 #define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 7318 #define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 7319 #define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 7320 #define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 7321 #define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 7322 #define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 7323 #define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 7324 #define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 7325 #define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 7326 #define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 7327 #define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 7328 //PCTL_MMHUB_DEEPSLEEP_OVERRIDE 7329 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 7330 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 7331 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 7332 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 7333 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 7334 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 7335 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 7336 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 7337 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 7338 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 7339 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 7340 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 7341 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 7342 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 7343 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 7344 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 7345 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 7346 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 7347 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 7348 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 7349 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 7350 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 7351 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 7352 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 7353 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 7354 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 7355 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 7356 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 7357 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 7358 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 7359 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 7360 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 7361 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 7362 #define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 7363 //PCTL_PG_IGNORE_DEEPSLEEP 7364 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 7365 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 7366 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 7367 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 7368 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 7369 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 7370 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 7371 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 7372 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 7373 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 7374 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 7375 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 7376 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 7377 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 7378 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 7379 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 7380 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 7381 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 7382 #define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 7383 #define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 7384 #define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 7385 #define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 7386 #define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 7387 #define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 7388 #define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 7389 #define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 7390 #define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 7391 #define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 7392 #define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 7393 #define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 7394 #define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 7395 #define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 7396 #define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 7397 #define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 7398 #define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 7399 #define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 7400 //PCTL_PG_DAGB 7401 #define PCTL_PG_DAGB__DS0__SHIFT 0x0 7402 #define PCTL_PG_DAGB__DS1__SHIFT 0x1 7403 #define PCTL_PG_DAGB__DS2__SHIFT 0x2 7404 #define PCTL_PG_DAGB__DS3__SHIFT 0x3 7405 #define PCTL_PG_DAGB__DS4__SHIFT 0x4 7406 #define PCTL_PG_DAGB__DS5__SHIFT 0x5 7407 #define PCTL_PG_DAGB__DS6__SHIFT 0x6 7408 #define PCTL_PG_DAGB__DS7__SHIFT 0x7 7409 #define PCTL_PG_DAGB__DS8__SHIFT 0x8 7410 #define PCTL_PG_DAGB__DS9__SHIFT 0x9 7411 #define PCTL_PG_DAGB__DS10__SHIFT 0xa 7412 #define PCTL_PG_DAGB__DS11__SHIFT 0xb 7413 #define PCTL_PG_DAGB__DS12__SHIFT 0xc 7414 #define PCTL_PG_DAGB__DS13__SHIFT 0xd 7415 #define PCTL_PG_DAGB__DS14__SHIFT 0xe 7416 #define PCTL_PG_DAGB__DS15__SHIFT 0xf 7417 #define PCTL_PG_DAGB__DS16__SHIFT 0x10 7418 #define PCTL_PG_DAGB__DS0_MASK 0x00000001L 7419 #define PCTL_PG_DAGB__DS1_MASK 0x00000002L 7420 #define PCTL_PG_DAGB__DS2_MASK 0x00000004L 7421 #define PCTL_PG_DAGB__DS3_MASK 0x00000008L 7422 #define PCTL_PG_DAGB__DS4_MASK 0x00000010L 7423 #define PCTL_PG_DAGB__DS5_MASK 0x00000020L 7424 #define PCTL_PG_DAGB__DS6_MASK 0x00000040L 7425 #define PCTL_PG_DAGB__DS7_MASK 0x00000080L 7426 #define PCTL_PG_DAGB__DS8_MASK 0x00000100L 7427 #define PCTL_PG_DAGB__DS9_MASK 0x00000200L 7428 #define PCTL_PG_DAGB__DS10_MASK 0x00000400L 7429 #define PCTL_PG_DAGB__DS11_MASK 0x00000800L 7430 #define PCTL_PG_DAGB__DS12_MASK 0x00001000L 7431 #define PCTL_PG_DAGB__DS13_MASK 0x00002000L 7432 #define PCTL_PG_DAGB__DS14_MASK 0x00004000L 7433 #define PCTL_PG_DAGB__DS15_MASK 0x00008000L 7434 #define PCTL_PG_DAGB__DS16_MASK 0x00010000L 7435 //PCTL0_RENG_RAM_INDEX 7436 #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7437 #define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 7438 //PCTL0_RENG_RAM_DATA 7439 #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7440 #define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7441 //PCTL0_RENG_EXECUTE 7442 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7443 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7444 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7445 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7446 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe 7447 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 7448 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7449 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7450 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7451 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L 7452 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L 7453 #define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L 7454 //PCTL0_MISC 7455 #define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 7456 #define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 7457 #define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 7458 #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 7459 #define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 7460 #define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 7461 #define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 7462 #define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 7463 //PCTL0_STCTRL_REGISTER_SAVE_RANGE0 7464 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7465 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7466 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7467 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7468 //PCTL0_STCTRL_REGISTER_SAVE_RANGE1 7469 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7470 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7471 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7472 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7473 //PCTL0_STCTRL_REGISTER_SAVE_RANGE2 7474 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7475 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7476 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7477 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7478 //PCTL0_STCTRL_REGISTER_SAVE_RANGE3 7479 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7480 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7481 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7482 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7483 //PCTL0_STCTRL_REGISTER_SAVE_RANGE4 7484 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7485 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7486 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7487 #define PCTL0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7488 //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 7489 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7490 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7491 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7492 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7493 //PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 7494 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7495 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7496 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7497 #define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7498 //PCTL1_RENG_RAM_INDEX 7499 #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7500 #define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 7501 //PCTL1_RENG_RAM_DATA 7502 #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7503 #define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7504 //PCTL1_RENG_EXECUTE 7505 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7506 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7507 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7508 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7509 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 7510 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 7511 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7512 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7513 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7514 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 7515 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 7516 #define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 7517 //PCTL1_MISC 7518 #define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 7519 #define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 7520 #define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 7521 #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 7522 #define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 7523 #define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 7524 #define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 7525 #define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 7526 #define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 7527 #define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 7528 //PCTL1_STCTRL_REGISTER_SAVE_RANGE0 7529 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7530 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7531 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7532 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7533 //PCTL1_STCTRL_REGISTER_SAVE_RANGE1 7534 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7535 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7536 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7537 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7538 //PCTL1_STCTRL_REGISTER_SAVE_RANGE2 7539 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7540 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7541 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7542 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7543 //PCTL1_STCTRL_REGISTER_SAVE_RANGE3 7544 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7545 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7546 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7547 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7548 //PCTL1_STCTRL_REGISTER_SAVE_RANGE4 7549 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7550 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7551 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7552 #define PCTL1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7553 //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 7554 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7555 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7556 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7557 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7558 //PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 7559 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7560 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7561 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7562 #define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7563 //PCTL2_RENG_RAM_INDEX 7564 #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7565 #define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 7566 //PCTL2_RENG_RAM_DATA 7567 #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7568 #define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7569 //PCTL2_RENG_EXECUTE 7570 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7571 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7572 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7573 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7574 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 7575 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 7576 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7577 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7578 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7579 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 7580 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 7581 #define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 7582 //PCTL2_MISC 7583 #define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 7584 #define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 7585 #define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 7586 #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 7587 #define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 7588 #define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 7589 #define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 7590 #define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 7591 #define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 7592 #define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 7593 //PCTL2_STCTRL_REGISTER_SAVE_RANGE0 7594 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7595 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7596 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7597 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7598 //PCTL2_STCTRL_REGISTER_SAVE_RANGE1 7599 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7600 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7601 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7602 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7603 //PCTL2_STCTRL_REGISTER_SAVE_RANGE2 7604 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7605 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7606 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7607 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7608 //PCTL2_STCTRL_REGISTER_SAVE_RANGE3 7609 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7610 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7611 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7612 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7613 //PCTL2_STCTRL_REGISTER_SAVE_RANGE4 7614 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7615 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7616 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7617 #define PCTL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7618 //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 7619 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7620 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7621 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7622 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7623 //PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 7624 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7625 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7626 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7627 #define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7628 7629 7630 // addressBlock: mmhub_l1tlb_vml1dec 7631 //MC_VM_MX_L1_TLB0_STATUS 7632 #define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 7633 #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7634 #define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 7635 #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7636 //MC_VM_MX_L1_TLB1_STATUS 7637 #define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 7638 #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7639 #define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 7640 #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7641 //MC_VM_MX_L1_TLB2_STATUS 7642 #define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 7643 #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7644 #define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 7645 #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7646 //MC_VM_MX_L1_TLB3_STATUS 7647 #define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 7648 #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7649 #define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 7650 #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7651 //MC_VM_MX_L1_TLB4_STATUS 7652 #define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 7653 #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7654 #define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 7655 #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7656 //MC_VM_MX_L1_TLB5_STATUS 7657 #define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 7658 #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7659 #define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 7660 #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7661 //MC_VM_MX_L1_TLB6_STATUS 7662 #define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 7663 #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7664 #define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 7665 #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7666 //MC_VM_MX_L1_TLB7_STATUS 7667 #define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 7668 #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7669 #define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 7670 #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7671 7672 7673 // addressBlock: mmhub_l1tlb_vml1pldec 7674 //MC_VM_MX_L1_PERFCOUNTER0_CFG 7675 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7676 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7677 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7678 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7679 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7680 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7681 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7682 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7683 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7684 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7685 //MC_VM_MX_L1_PERFCOUNTER1_CFG 7686 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7687 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7688 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7689 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7690 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7691 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7692 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7693 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7694 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7695 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7696 //MC_VM_MX_L1_PERFCOUNTER2_CFG 7697 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7698 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7699 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7700 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7701 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7702 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7703 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7704 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7705 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7706 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7707 //MC_VM_MX_L1_PERFCOUNTER3_CFG 7708 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7709 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7710 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7711 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7712 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7713 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7714 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7715 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7716 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7717 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7718 //MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 7719 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7720 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7721 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7722 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7723 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7724 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7725 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7726 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7727 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7728 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7729 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7730 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7731 7732 7733 // addressBlock: mmhub_l1tlb_vml1prdec 7734 //MC_VM_MX_L1_PERFCOUNTER_LO 7735 #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7736 #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7737 //MC_VM_MX_L1_PERFCOUNTER_HI 7738 #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7739 #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7740 #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7741 #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7742 7743 7744 // addressBlock: mmhub_utcl2_atcl2dec 7745 //ATC_L2_CNTL 7746 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 7747 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 7748 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 7749 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 7750 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 7751 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7752 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 7753 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 7754 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 7755 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 7756 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 7757 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7758 //ATC_L2_CNTL2 7759 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 7760 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7761 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 7762 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 7763 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 7764 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 7765 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 7766 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7767 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 7768 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 7769 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 7770 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 7771 //ATC_L2_CACHE_DATA0 7772 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 7773 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 7774 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 7775 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 7776 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 7777 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 7778 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 7779 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 7780 //ATC_L2_CACHE_DATA1 7781 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 7782 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 7783 //ATC_L2_CACHE_DATA2 7784 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 7785 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 7786 //ATC_L2_CNTL3 7787 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 7788 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 7789 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x9 7790 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 7791 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 7792 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x00000E00L 7793 //ATC_L2_STATUS 7794 #define ATC_L2_STATUS__BUSY__SHIFT 0x0 7795 #define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 7796 #define ATC_L2_STATUS__BUSY_MASK 0x00000001L 7797 #define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 7798 //ATC_L2_STATUS2 7799 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 7800 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 7801 #define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 7802 #define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 7803 //ATC_L2_MISC_CG 7804 #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 7805 #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 7806 #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 7807 #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 7808 #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 7809 #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 7810 //ATC_L2_MEM_POWER_LS 7811 #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7812 #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7813 #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7814 #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7815 //ATC_L2_CGTT_CLK_CTRL 7816 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7817 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7818 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7819 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7820 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7821 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7822 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7823 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7824 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7825 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7826 7827 7828 // addressBlock: mmhub_utcl2_vml2pfdec 7829 //VM_L2_CNTL 7830 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 7831 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 7832 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 7833 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 7834 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 7835 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 7836 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 7837 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7838 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 7839 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 7840 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 7841 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 7842 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 7843 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 7844 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 7845 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 7846 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 7847 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 7848 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 7849 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 7850 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 7851 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7852 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 7853 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 7854 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 7855 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 7856 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 7857 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 7858 //VM_L2_CNTL2 7859 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 7860 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 7861 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 7862 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 7863 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 7864 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 7865 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 7866 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 7867 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 7868 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 7869 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 7870 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 7871 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 7872 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 7873 //VM_L2_CNTL3 7874 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 7875 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7876 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 7877 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 7878 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 7879 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 7880 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 7881 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 7882 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 7883 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 7884 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 7885 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 7886 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7887 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 7888 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 7889 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 7890 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 7891 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 7892 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 7893 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 7894 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 7895 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 7896 //VM_L2_STATUS 7897 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 7898 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 7899 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 7900 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 7901 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 7902 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 7903 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 7904 #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 7905 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 7906 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 7907 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 7908 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 7909 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 7910 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 7911 //VM_DUMMY_PAGE_FAULT_CNTL 7912 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 7913 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 7914 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 7915 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 7916 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 7917 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 7918 //VM_DUMMY_PAGE_FAULT_ADDR_LO32 7919 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 7920 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7921 //VM_DUMMY_PAGE_FAULT_ADDR_HI32 7922 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 7923 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 7924 //VM_L2_PROTECTION_FAULT_CNTL 7925 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 7926 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 7927 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 7928 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 7929 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 7930 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 7931 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 7932 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 7933 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 7934 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 7935 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7936 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 7937 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7938 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 7939 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 7940 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 7941 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 7942 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 7943 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 7944 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 7945 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 7946 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 7947 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 7948 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 7949 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 7950 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 7951 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 7952 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7953 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 7954 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7955 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 7956 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 7957 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 7958 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 7959 //VM_L2_PROTECTION_FAULT_CNTL2 7960 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 7961 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 7962 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 7963 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 7964 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 7965 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 7966 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 7967 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 7968 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 7969 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 7970 //VM_L2_PROTECTION_FAULT_MM_CNTL3 7971 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7972 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7973 //VM_L2_PROTECTION_FAULT_MM_CNTL4 7974 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7975 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7976 //VM_L2_PROTECTION_FAULT_STATUS 7977 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 7978 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 7979 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 7980 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 7981 #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 7982 #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 7983 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 7984 #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 7985 #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 7986 #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 7987 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 7988 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 7989 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 7990 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 7991 #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 7992 #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 7993 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 7994 #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 7995 #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 7996 #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 7997 //VM_L2_PROTECTION_FAULT_ADDR_LO32 7998 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 7999 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 8000 //VM_L2_PROTECTION_FAULT_ADDR_HI32 8001 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 8002 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 8003 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 8004 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 8005 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 8006 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 8007 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 8008 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 8009 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 8010 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8011 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8012 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 8013 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8014 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8015 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 8016 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 8017 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 8018 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 8019 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 8020 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 8021 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 8022 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 8023 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 8024 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 8025 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 8026 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 8027 //VM_L2_CNTL4 8028 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 8029 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 8030 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 8031 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 8032 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 8033 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 8034 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 8035 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 8036 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 8037 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 8038 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 8039 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 8040 //VM_L2_MM_GROUP_RT_CLASSES 8041 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 8042 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 8043 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 8044 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 8045 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 8046 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 8047 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 8048 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 8049 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 8050 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 8051 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 8052 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 8053 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 8054 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 8055 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 8056 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 8057 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 8058 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 8059 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 8060 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 8061 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 8062 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 8063 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 8064 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 8065 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 8066 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 8067 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 8068 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 8069 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 8070 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 8071 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 8072 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 8073 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 8074 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 8075 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 8076 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 8077 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 8078 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 8079 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 8080 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 8081 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 8082 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 8083 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 8084 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 8085 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 8086 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 8087 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 8088 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 8089 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 8090 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 8091 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 8092 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 8093 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 8094 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 8095 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 8096 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 8097 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 8098 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 8099 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 8100 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 8101 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 8102 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 8103 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 8104 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 8105 //VM_L2_BANK_SELECT_RESERVED_CID 8106 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 8107 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 8108 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 8109 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 8110 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 8111 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 8112 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 8113 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 8114 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 8115 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 8116 //VM_L2_BANK_SELECT_RESERVED_CID2 8117 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 8118 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 8119 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 8120 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 8121 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 8122 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 8123 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 8124 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 8125 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 8126 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 8127 //VM_L2_CACHE_PARITY_CNTL 8128 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 8129 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 8130 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 8131 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 8132 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 8133 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 8134 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 8135 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 8136 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 8137 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 8138 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 8139 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 8140 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 8141 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 8142 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 8143 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 8144 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 8145 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 8146 //VM_L2_CGTT_CLK_CTRL 8147 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8148 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8149 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 8150 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 8151 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 8152 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8153 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8154 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 8155 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 8156 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 8157 8158 8159 // addressBlock: mmhub_utcl2_vml2vcdec 8160 //VM_CONTEXT0_CNTL 8161 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8162 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8163 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8164 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8165 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8166 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8167 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8168 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8169 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8170 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8171 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8172 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8173 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8174 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8175 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8176 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8177 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8178 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8179 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8180 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8181 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8182 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8183 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8184 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8185 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8186 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8187 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8188 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8189 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8190 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8191 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8192 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8193 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8194 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8195 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8196 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8197 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8198 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8199 //VM_CONTEXT1_CNTL 8200 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8201 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8202 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8203 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8204 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8205 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8206 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8207 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8208 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8209 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8210 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8211 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8212 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8213 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8214 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8215 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8216 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8217 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8218 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8219 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8220 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8221 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8222 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8223 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8224 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8225 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8226 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8227 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8228 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8229 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8230 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8231 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8232 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8233 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8234 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8235 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8236 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8237 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8238 //VM_CONTEXT2_CNTL 8239 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8240 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8241 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8242 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8243 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8244 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8245 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8246 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8247 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8248 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8249 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8250 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8251 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8252 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8253 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8254 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8255 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8256 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8257 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8258 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8259 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8260 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8261 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8262 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8263 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8264 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8265 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8266 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8267 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8268 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8269 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8270 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8271 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8272 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8273 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8274 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8275 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8276 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8277 //VM_CONTEXT3_CNTL 8278 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8279 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8280 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8281 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8282 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8283 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8284 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8285 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8286 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8287 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8288 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8289 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8290 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8291 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8292 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8293 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8294 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8295 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8296 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8297 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8298 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8299 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8300 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8301 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8302 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8303 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8304 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8305 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8306 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8307 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8308 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8309 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8310 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8311 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8312 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8313 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8314 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8315 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8316 //VM_CONTEXT4_CNTL 8317 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8318 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8319 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8320 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8321 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8322 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8323 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8324 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8325 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8326 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8327 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8328 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8329 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8330 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8331 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8332 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8333 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8334 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8335 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8336 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8337 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8338 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8339 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8340 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8341 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8342 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8343 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8344 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8345 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8346 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8347 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8348 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8349 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8350 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8351 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8352 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8353 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8354 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8355 //VM_CONTEXT5_CNTL 8356 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8357 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8358 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8359 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8360 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8361 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8362 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8363 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8364 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8365 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8366 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8367 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8368 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8369 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8370 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8371 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8372 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8373 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8374 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8375 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8376 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8377 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8378 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8379 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8380 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8381 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8382 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8383 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8384 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8385 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8386 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8387 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8388 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8389 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8390 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8391 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8392 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8393 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8394 //VM_CONTEXT6_CNTL 8395 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8396 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8397 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8398 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8399 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8400 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8401 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8402 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8403 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8404 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8405 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8406 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8407 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8408 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8409 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8410 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8411 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8412 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8413 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8414 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8415 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8416 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8417 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8418 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8419 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8420 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8421 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8422 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8423 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8424 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8425 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8426 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8427 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8428 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8429 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8430 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8431 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8432 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8433 //VM_CONTEXT7_CNTL 8434 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8435 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8436 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8437 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8438 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8439 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8440 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8441 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8442 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8443 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8444 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8445 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8446 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8447 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8448 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8449 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8450 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8451 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8452 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8453 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8454 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8455 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8456 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8457 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8458 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8459 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8460 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8461 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8462 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8463 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8464 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8465 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8466 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8467 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8468 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8469 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8470 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8471 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8472 //VM_CONTEXT8_CNTL 8473 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8474 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8475 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8476 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8477 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8478 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8479 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8480 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8481 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8482 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8483 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8484 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8485 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8486 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8487 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8488 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8489 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8490 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8491 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8492 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8493 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8494 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8495 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8496 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8497 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8498 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8499 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8500 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8501 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8502 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8503 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8504 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8505 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8506 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8507 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8508 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8509 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8510 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8511 //VM_CONTEXT9_CNTL 8512 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8513 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8514 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8515 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8516 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8517 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8518 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8519 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8520 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8521 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8522 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8523 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8524 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8525 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8526 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8527 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8528 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8529 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8530 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8531 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8532 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8533 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8534 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8535 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8536 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8537 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8538 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8539 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8540 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8541 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8542 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8543 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8544 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8545 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8546 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8547 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8548 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8549 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8550 //VM_CONTEXT10_CNTL 8551 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8552 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8553 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8554 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8555 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8556 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8557 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8558 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8559 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8560 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8561 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8562 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8563 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8564 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8565 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8566 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8567 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8568 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8569 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8570 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8571 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8572 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8573 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8574 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8575 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8576 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8577 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8578 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8579 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8580 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8581 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8582 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8583 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8584 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8585 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8586 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8587 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8588 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8589 //VM_CONTEXT11_CNTL 8590 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8591 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8592 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8593 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8594 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8595 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8596 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8597 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8598 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8599 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8600 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8601 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8602 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8603 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8604 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8605 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8606 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8607 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8608 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8609 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8610 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8611 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8612 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8613 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8614 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8615 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8616 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8617 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8618 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8619 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8620 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8621 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8622 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8623 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8624 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8625 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8626 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8627 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8628 //VM_CONTEXT12_CNTL 8629 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8630 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8631 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8632 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8633 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8634 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8635 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8636 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8637 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8638 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8639 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8640 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8641 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8642 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8643 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8644 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8645 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8646 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8647 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8648 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8649 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8650 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8651 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8652 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8653 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8654 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8655 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8656 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8657 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8658 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8659 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8660 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8661 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8662 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8663 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8664 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8665 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8666 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8667 //VM_CONTEXT13_CNTL 8668 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8669 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8670 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8671 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8672 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8673 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8674 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8675 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8676 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8677 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8678 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8679 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8680 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8681 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8682 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8683 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8684 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8685 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8686 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8687 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8688 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8689 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8690 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8691 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8692 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8693 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8694 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8695 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8696 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8697 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8698 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8699 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8700 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8701 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8702 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8703 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8704 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8705 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8706 //VM_CONTEXT14_CNTL 8707 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8708 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8709 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8710 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8711 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8712 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8713 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8714 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8715 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8716 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8717 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8718 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8719 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8720 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8721 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8722 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8723 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8724 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8725 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8726 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8727 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8728 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8729 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8730 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8731 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8732 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8733 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8734 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8735 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8736 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8737 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8738 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8739 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8740 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8741 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8742 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8743 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8744 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8745 //VM_CONTEXT15_CNTL 8746 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8747 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8748 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8749 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8750 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8751 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8752 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8753 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8754 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8755 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8756 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8757 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8758 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8759 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8760 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8761 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8762 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8763 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8764 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8765 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8766 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8767 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8768 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8769 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8770 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8771 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8772 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8773 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8774 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8775 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8776 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8777 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8778 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8779 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8780 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8781 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8782 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8783 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8784 //VM_CONTEXTS_DISABLE 8785 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 8786 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 8787 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 8788 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 8789 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 8790 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 8791 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 8792 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 8793 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 8794 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 8795 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 8796 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 8797 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 8798 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 8799 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 8800 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 8801 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 8802 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 8803 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 8804 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 8805 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 8806 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 8807 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 8808 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 8809 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 8810 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 8811 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 8812 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 8813 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 8814 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 8815 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 8816 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 8817 //VM_INVALIDATE_ENG0_SEM 8818 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 8819 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 8820 //VM_INVALIDATE_ENG1_SEM 8821 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 8822 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 8823 //VM_INVALIDATE_ENG2_SEM 8824 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 8825 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 8826 //VM_INVALIDATE_ENG3_SEM 8827 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 8828 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 8829 //VM_INVALIDATE_ENG4_SEM 8830 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 8831 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 8832 //VM_INVALIDATE_ENG5_SEM 8833 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 8834 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 8835 //VM_INVALIDATE_ENG6_SEM 8836 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 8837 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 8838 //VM_INVALIDATE_ENG7_SEM 8839 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 8840 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 8841 //VM_INVALIDATE_ENG8_SEM 8842 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 8843 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 8844 //VM_INVALIDATE_ENG9_SEM 8845 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 8846 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 8847 //VM_INVALIDATE_ENG10_SEM 8848 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 8849 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 8850 //VM_INVALIDATE_ENG11_SEM 8851 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 8852 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 8853 //VM_INVALIDATE_ENG12_SEM 8854 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 8855 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 8856 //VM_INVALIDATE_ENG13_SEM 8857 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 8858 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 8859 //VM_INVALIDATE_ENG14_SEM 8860 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 8861 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 8862 //VM_INVALIDATE_ENG15_SEM 8863 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 8864 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 8865 //VM_INVALIDATE_ENG16_SEM 8866 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 8867 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 8868 //VM_INVALIDATE_ENG17_SEM 8869 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 8870 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 8871 //VM_INVALIDATE_ENG0_REQ 8872 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8873 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 8874 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8875 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8876 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8877 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8878 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8879 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8880 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8881 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 8882 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8883 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8884 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8885 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8886 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8887 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8888 //VM_INVALIDATE_ENG1_REQ 8889 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8890 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 8891 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8892 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8893 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8894 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8895 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8896 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8897 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8898 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 8899 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8900 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8901 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8902 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8903 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8904 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8905 //VM_INVALIDATE_ENG2_REQ 8906 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8907 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 8908 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8909 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8910 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8911 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8912 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8913 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8914 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8915 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 8916 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8917 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8918 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8919 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8920 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8921 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8922 //VM_INVALIDATE_ENG3_REQ 8923 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8924 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 8925 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8926 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8927 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8928 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8929 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8930 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8931 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8932 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 8933 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8934 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8935 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8936 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8937 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8938 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8939 //VM_INVALIDATE_ENG4_REQ 8940 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8941 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 8942 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8943 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8944 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8945 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8946 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8947 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8948 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8949 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 8950 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8951 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8952 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8953 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8954 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8955 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8956 //VM_INVALIDATE_ENG5_REQ 8957 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8958 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 8959 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8960 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8961 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8962 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8963 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8964 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8965 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8966 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 8967 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8968 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8969 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8970 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8971 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8972 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8973 //VM_INVALIDATE_ENG6_REQ 8974 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8975 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 8976 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8977 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8978 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8979 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8980 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8981 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8982 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8983 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 8984 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8985 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8986 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8987 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8988 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8989 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8990 //VM_INVALIDATE_ENG7_REQ 8991 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8992 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 8993 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8994 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8995 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8996 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8997 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8998 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8999 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9000 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 9001 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9002 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9003 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9004 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9005 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9006 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9007 //VM_INVALIDATE_ENG8_REQ 9008 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9009 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 9010 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9011 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9012 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9013 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9014 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9015 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9016 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9017 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 9018 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9019 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9020 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9021 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9022 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9023 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9024 //VM_INVALIDATE_ENG9_REQ 9025 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9026 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 9027 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9028 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9029 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9030 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9031 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9032 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9033 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9034 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 9035 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9036 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9037 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9038 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9039 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9040 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9041 //VM_INVALIDATE_ENG10_REQ 9042 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9043 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 9044 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9045 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9046 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9047 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9048 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9049 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9050 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9051 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 9052 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9053 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9054 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9055 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9056 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9057 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9058 //VM_INVALIDATE_ENG11_REQ 9059 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9060 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 9061 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9062 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9063 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9064 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9065 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9066 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9067 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9068 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 9069 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9070 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9071 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9072 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9073 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9074 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9075 //VM_INVALIDATE_ENG12_REQ 9076 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9077 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 9078 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9079 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9080 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9081 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9082 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9083 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9084 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9085 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 9086 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9087 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9088 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9089 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9090 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9091 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9092 //VM_INVALIDATE_ENG13_REQ 9093 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9094 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 9095 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9096 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9097 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9098 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9099 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9100 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9101 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9102 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 9103 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9104 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9105 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9106 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9107 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9108 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9109 //VM_INVALIDATE_ENG14_REQ 9110 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9111 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 9112 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9113 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9114 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9115 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9116 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9117 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9118 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9119 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 9120 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9121 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9122 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9123 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9124 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9125 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9126 //VM_INVALIDATE_ENG15_REQ 9127 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9128 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 9129 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9130 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9131 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9132 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9133 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9134 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9135 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9136 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 9137 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9138 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9139 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9140 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9141 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9142 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9143 //VM_INVALIDATE_ENG16_REQ 9144 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9145 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 9146 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9147 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9148 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9149 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9150 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9151 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9152 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9153 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 9154 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9155 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9156 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9157 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9158 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9159 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9160 //VM_INVALIDATE_ENG17_REQ 9161 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9162 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 9163 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9164 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9165 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9166 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9167 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9168 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9169 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9170 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 9171 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9172 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9173 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9174 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9175 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9176 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9177 //VM_INVALIDATE_ENG0_ACK 9178 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9179 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 9180 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9181 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 9182 //VM_INVALIDATE_ENG1_ACK 9183 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9184 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 9185 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9186 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 9187 //VM_INVALIDATE_ENG2_ACK 9188 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9189 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 9190 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9191 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 9192 //VM_INVALIDATE_ENG3_ACK 9193 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9194 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 9195 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9196 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 9197 //VM_INVALIDATE_ENG4_ACK 9198 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9199 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 9200 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9201 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 9202 //VM_INVALIDATE_ENG5_ACK 9203 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9204 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 9205 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9206 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 9207 //VM_INVALIDATE_ENG6_ACK 9208 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9209 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 9210 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9211 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 9212 //VM_INVALIDATE_ENG7_ACK 9213 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9214 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 9215 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9216 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 9217 //VM_INVALIDATE_ENG8_ACK 9218 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9219 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 9220 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9221 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 9222 //VM_INVALIDATE_ENG9_ACK 9223 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9224 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 9225 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9226 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 9227 //VM_INVALIDATE_ENG10_ACK 9228 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9229 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 9230 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9231 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 9232 //VM_INVALIDATE_ENG11_ACK 9233 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9234 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 9235 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9236 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 9237 //VM_INVALIDATE_ENG12_ACK 9238 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9239 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 9240 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9241 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 9242 //VM_INVALIDATE_ENG13_ACK 9243 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9244 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 9245 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9246 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 9247 //VM_INVALIDATE_ENG14_ACK 9248 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9249 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 9250 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9251 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 9252 //VM_INVALIDATE_ENG15_ACK 9253 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9254 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 9255 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9256 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 9257 //VM_INVALIDATE_ENG16_ACK 9258 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9259 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 9260 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9261 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 9262 //VM_INVALIDATE_ENG17_ACK 9263 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9264 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 9265 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9266 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 9267 //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 9268 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9269 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9270 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9271 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9272 //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 9273 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9274 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9275 //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 9276 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9277 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9278 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9279 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9280 //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 9281 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9282 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9283 //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 9284 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9285 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9286 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9287 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9288 //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 9289 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9290 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9291 //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 9292 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9293 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9294 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9295 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9296 //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 9297 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9298 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9299 //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 9300 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9301 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9302 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9303 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9304 //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 9305 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9306 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9307 //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 9308 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9309 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9310 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9311 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9312 //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 9313 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9314 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9315 //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 9316 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9317 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9318 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9319 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9320 //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 9321 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9322 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9323 //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 9324 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9325 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9326 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9327 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9328 //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 9329 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9330 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9331 //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 9332 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9333 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9334 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9335 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9336 //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 9337 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9338 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9339 //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 9340 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9341 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9342 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9343 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9344 //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 9345 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9346 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9347 //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 9348 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9349 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9350 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9351 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9352 //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 9353 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9354 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9355 //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 9356 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9357 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9358 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9359 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9360 //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 9361 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9362 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9363 //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 9364 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9365 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9366 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9367 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9368 //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 9369 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9370 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9371 //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 9372 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9373 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9374 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9375 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9376 //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 9377 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9378 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9379 //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 9380 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9381 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9382 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9383 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9384 //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 9385 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9386 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9387 //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 9388 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9389 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9390 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9391 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9392 //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 9393 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9394 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9395 //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 9396 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9397 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9398 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9399 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9400 //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 9401 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9402 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9403 //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 9404 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9405 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9406 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9407 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9408 //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 9409 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9410 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9411 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 9412 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9413 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9414 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 9415 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9416 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9417 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 9418 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9419 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9420 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 9421 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9422 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9423 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 9424 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9425 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9426 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 9427 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9428 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9429 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 9430 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9431 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9432 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 9433 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9434 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9435 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 9436 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9437 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9438 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 9439 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9440 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9441 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 9442 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9443 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9444 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 9445 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9446 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9447 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 9448 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9449 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9450 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 9451 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9452 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9453 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 9454 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9455 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9456 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 9457 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9458 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9459 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 9460 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9461 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9462 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 9463 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9464 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9465 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 9466 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9467 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9468 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 9469 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9470 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9471 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 9472 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9473 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9474 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 9475 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9476 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9477 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 9478 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9479 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9480 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 9481 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9482 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9483 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 9484 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9485 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9486 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 9487 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9488 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9489 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 9490 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9491 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9492 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 9493 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9494 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9495 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 9496 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9497 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9498 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 9499 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9500 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9501 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 9502 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9503 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9504 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 9505 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9506 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9507 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 9508 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9509 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9510 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 9511 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9512 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9513 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 9514 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9515 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9516 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 9517 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9518 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9519 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 9520 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9521 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9522 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 9523 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9524 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9525 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 9526 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9527 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9528 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 9529 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9530 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9531 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 9532 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9533 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9534 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 9535 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9536 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9537 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 9538 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9539 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9540 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 9541 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9542 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9543 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 9544 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9545 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9546 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 9547 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9548 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9549 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 9550 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9551 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9552 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 9553 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9554 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9555 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 9556 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9557 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9558 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 9559 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9560 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9561 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 9562 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9563 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9564 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 9565 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9566 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9567 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 9568 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9569 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9570 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 9571 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9572 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9573 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 9574 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9575 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9576 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 9577 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9578 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9579 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 9580 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9581 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9582 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 9583 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9584 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9585 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 9586 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9587 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9588 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 9589 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9590 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9591 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 9592 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9593 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9594 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 9595 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9596 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9597 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 9598 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9599 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9600 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 9601 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9602 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9603 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 9604 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9605 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9606 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 9607 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9608 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9609 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 9610 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9611 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9612 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 9613 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9614 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9615 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 9616 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9617 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9618 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 9619 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9620 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9621 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 9622 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9623 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9624 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 9625 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9626 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9627 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 9628 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9629 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9630 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 9631 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9632 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9633 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 9634 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9635 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9636 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 9637 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9638 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9639 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 9640 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9641 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9642 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 9643 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9644 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9645 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 9646 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9647 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9648 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 9649 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9650 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9651 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 9652 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9653 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9654 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 9655 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9656 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9657 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 9658 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9659 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9660 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 9661 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9662 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9663 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 9664 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9665 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9666 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 9667 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9668 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9669 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 9670 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9671 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9672 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 9673 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9674 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9675 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 9676 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9677 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9678 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 9679 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9680 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9681 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 9682 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9683 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9684 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 9685 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9686 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9687 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 9688 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9689 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9690 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 9691 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9692 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9693 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 9694 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9695 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9696 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 9697 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9698 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9699 9700 9701 // addressBlock: mmhub_utcl2_vml2pldec 9702 //MC_VM_L2_PERFCOUNTER0_CFG 9703 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9704 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9705 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9706 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9707 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9708 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9709 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9710 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9711 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9712 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9713 //MC_VM_L2_PERFCOUNTER1_CFG 9714 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9715 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9716 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9717 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9718 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9719 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9720 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9721 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9722 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9723 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9724 //MC_VM_L2_PERFCOUNTER2_CFG 9725 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 9726 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 9727 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 9728 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 9729 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 9730 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 9731 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 9732 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 9733 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 9734 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 9735 //MC_VM_L2_PERFCOUNTER3_CFG 9736 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 9737 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 9738 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 9739 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 9740 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 9741 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 9742 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 9743 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 9744 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 9745 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 9746 //MC_VM_L2_PERFCOUNTER4_CFG 9747 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 9748 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 9749 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 9750 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 9751 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 9752 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 9753 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 9754 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 9755 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 9756 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 9757 //MC_VM_L2_PERFCOUNTER5_CFG 9758 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 9759 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 9760 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 9761 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 9762 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 9763 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 9764 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 9765 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 9766 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 9767 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 9768 //MC_VM_L2_PERFCOUNTER6_CFG 9769 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 9770 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 9771 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 9772 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 9773 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 9774 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 9775 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 9776 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 9777 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 9778 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 9779 //MC_VM_L2_PERFCOUNTER7_CFG 9780 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 9781 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 9782 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 9783 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 9784 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 9785 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 9786 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 9787 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 9788 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 9789 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 9790 //MC_VM_L2_PERFCOUNTER_RSLT_CNTL 9791 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9792 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9793 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9794 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9795 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9796 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9797 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9798 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9799 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9800 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9801 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9802 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9803 9804 9805 // addressBlock: mmhub_utcl2_vml2prdec 9806 //MC_VM_L2_PERFCOUNTER_LO 9807 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 9808 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 9809 //MC_VM_L2_PERFCOUNTER_HI 9810 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 9811 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 9812 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 9813 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 9814 9815 9816 // addressBlock: mmhub_utcl2_vmsharedhvdec 9817 //MC_VM_FB_SIZE_OFFSET_VF0 9818 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 9819 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 9820 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 9821 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 9822 //MC_VM_FB_SIZE_OFFSET_VF1 9823 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 9824 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 9825 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 9826 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 9827 //MC_VM_FB_SIZE_OFFSET_VF2 9828 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 9829 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 9830 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 9831 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 9832 //MC_VM_FB_SIZE_OFFSET_VF3 9833 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 9834 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 9835 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 9836 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 9837 //MC_VM_FB_SIZE_OFFSET_VF4 9838 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 9839 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 9840 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 9841 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 9842 //MC_VM_FB_SIZE_OFFSET_VF5 9843 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 9844 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 9845 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 9846 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 9847 //MC_VM_FB_SIZE_OFFSET_VF6 9848 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 9849 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 9850 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 9851 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 9852 //MC_VM_FB_SIZE_OFFSET_VF7 9853 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 9854 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 9855 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 9856 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 9857 //MC_VM_FB_SIZE_OFFSET_VF8 9858 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 9859 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 9860 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 9861 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 9862 //MC_VM_FB_SIZE_OFFSET_VF9 9863 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 9864 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 9865 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 9866 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 9867 //MC_VM_FB_SIZE_OFFSET_VF10 9868 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 9869 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 9870 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 9871 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 9872 //MC_VM_FB_SIZE_OFFSET_VF11 9873 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 9874 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 9875 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 9876 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 9877 //MC_VM_FB_SIZE_OFFSET_VF12 9878 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 9879 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 9880 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 9881 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 9882 //MC_VM_FB_SIZE_OFFSET_VF13 9883 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 9884 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 9885 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 9886 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 9887 //MC_VM_FB_SIZE_OFFSET_VF14 9888 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 9889 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 9890 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 9891 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 9892 //MC_VM_FB_SIZE_OFFSET_VF15 9893 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 9894 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 9895 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 9896 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 9897 //VM_IOMMU_MMIO_CNTRL_1 9898 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 9899 #define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 9900 //MC_VM_MARC_BASE_LO_0 9901 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 9902 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 9903 //MC_VM_MARC_BASE_LO_1 9904 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 9905 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 9906 //MC_VM_MARC_BASE_LO_2 9907 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 9908 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 9909 //MC_VM_MARC_BASE_LO_3 9910 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 9911 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 9912 //MC_VM_MARC_BASE_HI_0 9913 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 9914 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 9915 //MC_VM_MARC_BASE_HI_1 9916 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 9917 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 9918 //MC_VM_MARC_BASE_HI_2 9919 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 9920 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 9921 //MC_VM_MARC_BASE_HI_3 9922 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 9923 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 9924 //MC_VM_MARC_RELOC_LO_0 9925 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 9926 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 9927 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 9928 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 9929 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 9930 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 9931 //MC_VM_MARC_RELOC_LO_1 9932 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 9933 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 9934 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 9935 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 9936 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 9937 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 9938 //MC_VM_MARC_RELOC_LO_2 9939 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 9940 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 9941 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 9942 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 9943 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 9944 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 9945 //MC_VM_MARC_RELOC_LO_3 9946 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 9947 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 9948 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 9949 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 9950 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 9951 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 9952 //MC_VM_MARC_RELOC_HI_0 9953 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 9954 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 9955 //MC_VM_MARC_RELOC_HI_1 9956 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 9957 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 9958 //MC_VM_MARC_RELOC_HI_2 9959 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 9960 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 9961 //MC_VM_MARC_RELOC_HI_3 9962 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 9963 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 9964 //MC_VM_MARC_LEN_LO_0 9965 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 9966 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 9967 //MC_VM_MARC_LEN_LO_1 9968 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 9969 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 9970 //MC_VM_MARC_LEN_LO_2 9971 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 9972 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 9973 //MC_VM_MARC_LEN_LO_3 9974 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 9975 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 9976 //MC_VM_MARC_LEN_HI_0 9977 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 9978 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 9979 //MC_VM_MARC_LEN_HI_1 9980 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 9981 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 9982 //MC_VM_MARC_LEN_HI_2 9983 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 9984 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 9985 //MC_VM_MARC_LEN_HI_3 9986 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 9987 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 9988 //VM_IOMMU_CONTROL_REGISTER 9989 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 9990 #define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 9991 //VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 9992 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 9993 #define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 9994 //VM_PCIE_ATS_CNTL 9995 #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 9996 #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 9997 #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 9998 #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 9999 //VM_PCIE_ATS_CNTL_VF_0 10000 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 10001 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 10002 //VM_PCIE_ATS_CNTL_VF_1 10003 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 10004 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 10005 //VM_PCIE_ATS_CNTL_VF_2 10006 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 10007 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 10008 //VM_PCIE_ATS_CNTL_VF_3 10009 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 10010 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 10011 //VM_PCIE_ATS_CNTL_VF_4 10012 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 10013 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 10014 //VM_PCIE_ATS_CNTL_VF_5 10015 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 10016 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 10017 //VM_PCIE_ATS_CNTL_VF_6 10018 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 10019 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 10020 //VM_PCIE_ATS_CNTL_VF_7 10021 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 10022 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 10023 //VM_PCIE_ATS_CNTL_VF_8 10024 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 10025 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 10026 //VM_PCIE_ATS_CNTL_VF_9 10027 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 10028 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 10029 //VM_PCIE_ATS_CNTL_VF_10 10030 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 10031 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 10032 //VM_PCIE_ATS_CNTL_VF_11 10033 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 10034 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 10035 //VM_PCIE_ATS_CNTL_VF_12 10036 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 10037 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 10038 //VM_PCIE_ATS_CNTL_VF_13 10039 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 10040 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 10041 //VM_PCIE_ATS_CNTL_VF_14 10042 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 10043 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 10044 //VM_PCIE_ATS_CNTL_VF_15 10045 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 10046 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 10047 //UTCL2_CGTT_CLK_CTRL 10048 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 10049 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10050 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 10051 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 10052 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 10053 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 10054 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 10055 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 10056 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 10057 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 10058 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 10059 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 10060 //MC_SHARED_ACTIVE_FCN_ID 10061 #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 10062 #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 10063 #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 10064 #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 10065 //MC_VM_XGMI_GPUIOV_ENABLE 10066 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 10067 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 10068 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 10069 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 10070 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 10071 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 10072 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 10073 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 10074 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 10075 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 10076 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa 10077 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb 10078 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc 10079 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd 10080 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe 10081 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf 10082 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f 10083 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L 10084 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L 10085 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L 10086 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L 10087 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L 10088 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L 10089 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L 10090 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L 10091 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L 10092 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L 10093 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L 10094 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L 10095 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L 10096 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L 10097 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L 10098 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L 10099 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L 10100 10101 10102 // addressBlock: mmhub_utcl2_vmsharedpfdec 10103 //MC_VM_NB_MMIOBASE 10104 #define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 10105 #define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 10106 //MC_VM_NB_MMIOLIMIT 10107 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 10108 #define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 10109 //MC_VM_NB_PCI_CTRL 10110 #define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 10111 #define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 10112 //MC_VM_NB_PCI_ARB 10113 #define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 10114 #define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 10115 //MC_VM_NB_TOP_OF_DRAM_SLOT1 10116 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 10117 #define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 10118 //MC_VM_NB_LOWER_TOP_OF_DRAM2 10119 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 10120 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 10121 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 10122 #define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 10123 //MC_VM_NB_UPPER_TOP_OF_DRAM2 10124 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 10125 #define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 10126 //MC_VM_FB_OFFSET 10127 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 10128 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 10129 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 10130 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 10131 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 10132 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 10133 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 10134 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 10135 //MC_VM_STEERING 10136 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 10137 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 10138 //MC_SHARED_VIRT_RESET_REQ 10139 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 10140 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 10141 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 10142 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 10143 //MC_MEM_POWER_LS 10144 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 10145 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 10146 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 10147 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 10148 //MC_VM_CACHEABLE_DRAM_ADDRESS_START 10149 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 10150 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 10151 //MC_VM_CACHEABLE_DRAM_ADDRESS_END 10152 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 10153 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 10154 //MC_VM_APT_CNTL 10155 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 10156 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 10157 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 10158 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 10159 //MC_VM_LOCAL_HBM_ADDRESS_START 10160 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 10161 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 10162 //MC_VM_LOCAL_HBM_ADDRESS_END 10163 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 10164 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 10165 //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 10166 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 10167 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 10168 //MC_VM_XGMI_LFB_CNTL 10169 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 10170 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x3 10171 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 10172 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000038L 10173 //MC_VM_XGMI_LFB_SIZE 10174 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 10175 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 10176 10177 10178 // addressBlock: mmhub_utcl2_vmsharedvcdec 10179 //MC_VM_FB_LOCATION_BASE 10180 #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 10181 #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 10182 //MC_VM_FB_LOCATION_TOP 10183 #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 10184 #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 10185 //MC_VM_AGP_TOP 10186 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 10187 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 10188 //MC_VM_AGP_BOT 10189 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 10190 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 10191 //MC_VM_AGP_BASE 10192 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 10193 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 10194 //MC_VM_SYSTEM_APERTURE_LOW_ADDR 10195 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 10196 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 10197 //MC_VM_SYSTEM_APERTURE_HIGH_ADDR 10198 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 10199 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 10200 //MC_VM_MX_L1_TLB_CNTL 10201 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 10202 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 10203 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 10204 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 10205 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 10206 #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 10207 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 10208 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 10209 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 10210 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 10211 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 10212 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 10213 #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 10214 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 10215 10216 10217 // addressBlock: mmhub_utcl2_atcl2pfcntrdec 10218 //ATC_L2_PERFCOUNTER_LO 10219 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 10220 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 10221 //ATC_L2_PERFCOUNTER_HI 10222 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 10223 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 10224 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 10225 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 10226 10227 10228 // addressBlock: mmhub_utcl2_atcl2pfcntldec 10229 //ATC_L2_PERFCOUNTER0_CFG 10230 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 10231 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 10232 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 10233 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 10234 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 10235 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 10236 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 10237 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 10238 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 10239 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 10240 //ATC_L2_PERFCOUNTER1_CFG 10241 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 10242 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 10243 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 10244 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 10245 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 10246 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 10247 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 10248 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 10249 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 10250 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 10251 //ATC_L2_PERFCOUNTER_RSLT_CNTL 10252 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 10253 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 10254 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 10255 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 10256 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 10257 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 10258 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 10259 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 10260 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 10261 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 10262 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10263 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10264 10265 #endif 10266