1 /* 2 * OSS_3_0_1 Register documentation 3 * 4 * Copyright (C) 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef OSS_3_0_1_ENUM_H 25 #define OSS_3_0_1_ENUM_H 26 27 typedef enum IH_CLIENT_ID { 28 DC_IH_SRC_ID_START = 0x1, 29 DC_IH_SRC_ID_END = 0x1f, 30 VGA_IH_SRC_ID_START = 0x20, 31 VGA_IH_SRC_ID_END = 0x27, 32 CAP_IH_SRC_ID_START = 0x28, 33 CAP_IH_SRC_ID_END = 0x2f, 34 VIP_IH_SRC_ID_START = 0x30, 35 VIP_IH_SRC_ID_END = 0x3f, 36 ROM_IH_SRC_ID_START = 0x40, 37 ROM_IH_SRC_ID_END = 0x5d, 38 BIF_IH_SRC_ID_START = 0x5e, 39 SAM_IH_SRC_ID_START = 0x5f, 40 SRBM_IH_SRC_ID_START = 0x60, 41 SRBM_IH_SRC_ID_END = 0x67, 42 UVD_IH_SRC_ID_START = 0x72, 43 UVD_IH_SRC_ID_END = 0x85, 44 VMC_IH_SRC_ID_START = 0x86, 45 VMC_IH_SRC_ID_END = 0x8f, 46 RLC_IH_SRC_ID_START = 0x90, 47 RLC_IH_SRC_ID_END = 0xf3, 48 PDMA_IH_SRC_ID_START = 0xf4, 49 PDMA_IH_SRC_ID_END = 0xf7, 50 CG_IH_SRC_ID_START = 0xf8, 51 CG_IH_SRC_ID_END = 0xff, 52 } IH_CLIENT_ID; 53 typedef enum IH_PERF_SEL { 54 IH_PERF_SEL_CYCLE = 0x0, 55 IH_PERF_SEL_IDLE = 0x1, 56 IH_PERF_SEL_INPUT_IDLE = 0x2, 57 IH_PERF_SEL_CLIENT0_IH_STALL = 0x3, 58 IH_PERF_SEL_CLIENT1_IH_STALL = 0x4, 59 IH_PERF_SEL_CLIENT2_IH_STALL = 0x5, 60 IH_PERF_SEL_CLIENT3_IH_STALL = 0x6, 61 IH_PERF_SEL_CLIENT4_IH_STALL = 0x7, 62 IH_PERF_SEL_CLIENT5_IH_STALL = 0x8, 63 IH_PERF_SEL_CLIENT6_IH_STALL = 0x9, 64 IH_PERF_SEL_CLIENT7_IH_STALL = 0xa, 65 IH_PERF_SEL_RB_IDLE = 0xb, 66 IH_PERF_SEL_RB_FULL = 0xc, 67 IH_PERF_SEL_RB_OVERFLOW = 0xd, 68 IH_PERF_SEL_RB_WPTR_WRITEBACK = 0xe, 69 IH_PERF_SEL_RB_WPTR_WRAP = 0xf, 70 IH_PERF_SEL_RB_RPTR_WRAP = 0x10, 71 IH_PERF_SEL_MC_WR_IDLE = 0x11, 72 IH_PERF_SEL_MC_WR_COUNT = 0x12, 73 IH_PERF_SEL_MC_WR_STALL = 0x13, 74 IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x14, 75 IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x15, 76 IH_PERF_SEL_BIF_RISING = 0x16, 77 IH_PERF_SEL_BIF_FALLING = 0x17, 78 IH_PERF_SEL_CLIENT8_IH_STALL = 0x18, 79 IH_PERF_SEL_CLIENT9_IH_STALL = 0x19, 80 IH_PERF_SEL_CLIENT10_IH_STALL = 0x1a, 81 IH_PERF_SEL_CLIENT11_IH_STALL = 0x1b, 82 IH_PERF_SEL_CLIENT12_IH_STALL = 0x1c, 83 IH_PERF_SEL_CLIENT13_IH_STALL = 0x1d, 84 IH_PERF_SEL_CLIENT14_IH_STALL = 0x1e, 85 IH_PERF_SEL_CLIENT15_IH_STALL = 0x1f, 86 IH_PERF_SEL_CLIENT16_IH_STALL = 0x20, 87 IH_PERF_SEL_CLIENT17_IH_STALL = 0x21, 88 IH_PERF_SEL_CLIENT18_IH_STALL = 0x22, 89 IH_PERF_SEL_CLIENT19_IH_STALL = 0x23, 90 IH_PERF_SEL_CLIENT20_IH_STALL = 0x24, 91 IH_PERF_SEL_CLIENT21_IH_STALL = 0x25, 92 IH_PERF_SEL_CLIENT22_IH_STALL = 0x26, 93 IH_PERF_SEL_CLIENT23_IH_STALL = 0x27, 94 } IH_PERF_SEL; 95 typedef enum SEM_PERF_SEL { 96 SEM_PERF_SEL_CYCLE = 0x0, 97 SEM_PERF_SEL_IDLE = 0x1, 98 SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x2, 99 SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x3, 100 SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x4, 101 SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x5, 102 SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x6, 103 SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x7, 104 SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x8, 105 SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x9, 106 SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0xa, 107 SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0xb, 108 SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0xc, 109 SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0xd, 110 SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0xe, 111 SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0xf, 112 SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x10, 113 SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x11, 114 SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x12, 115 SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x13, 116 SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x14, 117 SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x15, 118 SEM_PERF_SEL_UVD_REQ_WAIT = 0x16, 119 SEM_PERF_SEL_VCE0_REQ_WAIT = 0x17, 120 SEM_PERF_SEL_ACP_REQ_WAIT = 0x18, 121 SEM_PERF_SEL_ISP_REQ_WAIT = 0x19, 122 SEM_PERF_SEL_VCE1_REQ_WAIT = 0x1a, 123 SEM_PERF_SEL_VP8_REQ_WAIT = 0x1b, 124 SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x1c, 125 SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x1d, 126 SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x1e, 127 SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x1f, 128 SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x20, 129 SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x21, 130 SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x22, 131 SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x23, 132 SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x24, 133 SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x25, 134 SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x26, 135 SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x27, 136 SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x28, 137 SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x29, 138 SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x2a, 139 SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x2b, 140 SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x2c, 141 SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x2d, 142 SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x2e, 143 SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x2f, 144 SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x30, 145 SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x31, 146 SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x32, 147 SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x33, 148 SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x34, 149 SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x35, 150 SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x36, 151 SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x37, 152 SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x38, 153 SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x39, 154 SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x3a, 155 SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x3b, 156 SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x3c, 157 SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x3d, 158 SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x3e, 159 SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x3f, 160 SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x40, 161 SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x41, 162 SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x42, 163 SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x43, 164 SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x44, 165 SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x45, 166 SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x46, 167 SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x47, 168 SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x48, 169 SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x49, 170 SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x4a, 171 SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x4b, 172 SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x4c, 173 SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x4d, 174 SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x4e, 175 SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x4f, 176 SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x50, 177 SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x51, 178 SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x52, 179 SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x53, 180 SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x54, 181 SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x55, 182 SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x56, 183 SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x57, 184 SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x58, 185 SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x59, 186 SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x5a, 187 SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x5b, 188 SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x5c, 189 SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x5d, 190 SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x5e, 191 SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x5f, 192 SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x60, 193 SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x61, 194 SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x62, 195 SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x63, 196 SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x64, 197 SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x65, 198 SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x66, 199 SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x67, 200 SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x68, 201 SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x69, 202 SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x6a, 203 SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x6b, 204 SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x6c, 205 SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x6d, 206 SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x6e, 207 SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x6f, 208 SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x70, 209 SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x71, 210 SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x72, 211 SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x73, 212 SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x74, 213 SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x75, 214 SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x76, 215 SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x77, 216 SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x78, 217 SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x79, 218 SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x7a, 219 SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x7b, 220 SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x7c, 221 SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x7d, 222 SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x7e, 223 SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x7f, 224 SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x80, 225 SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x81, 226 SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x82, 227 SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x83, 228 SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x84, 229 SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x85, 230 SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x86, 231 SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x87, 232 SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x88, 233 SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x89, 234 SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x8a, 235 SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x8b, 236 SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x8c, 237 SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x8d, 238 SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x8e, 239 SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x8f, 240 SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x90, 241 SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x91, 242 SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x92, 243 SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x93, 244 SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x94, 245 SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x95, 246 SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x96, 247 SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x97, 248 SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x98, 249 SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x99, 250 SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x9a, 251 SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x9b, 252 SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x9c, 253 SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x9d, 254 SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x9e, 255 SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x9f, 256 SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0xa0, 257 SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0xa1, 258 SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0xa2, 259 SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0xa3, 260 SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0xa4, 261 SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0xa5, 262 SEM_PERF_SEL_MC_RD_REQ = 0xa6, 263 SEM_PERF_SEL_MC_RD_RET = 0xa7, 264 SEM_PERF_SEL_MC_WR_REQ = 0xa8, 265 SEM_PERF_SEL_MC_WR_RET = 0xa9, 266 SEM_PERF_SEL_ATC_REQ = 0xaa, 267 SEM_PERF_SEL_ATC_RET = 0xab, 268 SEM_PERF_SEL_ATC_XNACK = 0xac, 269 SEM_PERF_SEL_ATC_INVALIDATION = 0xad, 270 } SEM_PERF_SEL; 271 typedef enum SRBM_PERFCOUNT1_SEL { 272 SRBM_PERF_SEL_COUNT = 0x0, 273 SRBM_PERF_SEL_BIF_BUSY = 0x1, 274 SRBM_PERF_SEL_SDMA0_BUSY = 0x3, 275 SRBM_PERF_SEL_IH_BUSY = 0x4, 276 SRBM_PERF_SEL_MCB_BUSY = 0x5, 277 SRBM_PERF_SEL_MCB_NON_DISPLAY_BUSY = 0x6, 278 SRBM_PERF_SEL_MCC_BUSY = 0x7, 279 SRBM_PERF_SEL_MCD_BUSY = 0x8, 280 SRBM_PERF_SEL_CHUB_BUSY = 0x9, 281 SRBM_PERF_SEL_SEM_BUSY = 0xa, 282 SRBM_PERF_SEL_UVD_BUSY = 0xb, 283 SRBM_PERF_SEL_VMC_BUSY = 0xc, 284 SRBM_PERF_SEL_ODE_BUSY = 0xd, 285 SRBM_PERF_SEL_SDMA1_BUSY = 0xe, 286 SRBM_PERF_SEL_SAMMSP_BUSY = 0xf, 287 SRBM_PERF_SEL_VCE0_BUSY = 0x10, 288 SRBM_PERF_SEL_XDMA_BUSY = 0x11, 289 SRBM_PERF_SEL_ACP_BUSY = 0x12, 290 SRBM_PERF_SEL_SDMA2_BUSY = 0x13, 291 SRBM_PERF_SEL_SDMA3_BUSY = 0x14, 292 RESERVED0 = 0x15, 293 SRBM_PERF_SEL_VMC1_BUSY = 0x16, 294 SRBM_PERF_SEL_ISP_BUSY = 0x17, 295 SRBM_PERF_SEL_VCE1_BUSY = 0x18, 296 SRBM_PERF_SEL_GCATCL2_BUSY = 0x19, 297 SRBM_PERF_SEL_OSATCL2_BUSY = 0x1a, 298 SRBM_PERF_SEL_VP8_BUSY = 0x1b, 299 } SRBM_PERFCOUNT1_SEL; 300 typedef enum SYS_GRBM_GFX_INDEX_SEL { 301 GRBM_GFX_INDEX_BIF = 0x0, 302 GRBM_GFX_INDEX_SDMA0 = 0x1, 303 GRBM_GFX_INDEX_SDMA1 = 0x2, 304 RESEVERED0 = 0x3, 305 GRBM_GFX_INDEX_UVD = 0x4, 306 GRBM_GFX_INDEX_VCE0 = 0x5, 307 GRBM_GFX_INDEX_VCE1 = 0x6, 308 GRBM_GFX_INDEX_ACP = 0x7, 309 GRBM_GFX_INDEX_SMU = 0x8, 310 GRBM_GFX_INDEX_SAMMSP = 0x9, 311 GRBM_GFX_INDEX_VP8 = 0xa, 312 GRBM_GFX_INDEX_ISP = 0xb, 313 GRBM_GFX_INDEX_TST = 0xc, 314 GRBM_GFX_INDEX_SDMA2 = 0xd, 315 GRBM_GFX_INDEX_SDMA3 = 0xe, 316 } SYS_GRBM_GFX_INDEX_SEL; 317 typedef enum SRBM_GFX_CNTL_SEL { 318 SRBM_GFX_CNTL_BIF = 0x0, 319 SRBM_GFX_CNTL_SDMA0 = 0x1, 320 SRBM_GFX_CNTL_SDMA1 = 0x2, 321 SRBM_GFX_CNTL_GRBM = 0x3, 322 SRBM_GFX_CNTL_UVD = 0x4, 323 SRBM_GFX_CNTL_VCE0 = 0x5, 324 SRBM_GFX_CNTL_VCE1 = 0x6, 325 SRBM_GFX_CNTL_ACP = 0x7, 326 SRBM_GFX_CNTL_SMU = 0x8, 327 SRBM_GFX_CNTL_SAMMSP = 0x9, 328 SRBM_GFX_CNTL_VP8 = 0xa, 329 SRBM_GFX_CNTL_ISP = 0xb, 330 SRBM_GFX_CNTL_TST = 0xc, 331 SRBM_GFX_CNTL_SDMA2 = 0xd, 332 SRBM_GFX_CNTL_SDMA3 = 0xe, 333 } SRBM_GFX_CNTL_SEL; 334 typedef enum SDMA_PERF_SEL { 335 SDMA_PERF_SEL_CYCLE = 0x0, 336 SDMA_PERF_SEL_IDLE = 0x1, 337 SDMA_PERF_SEL_REG_IDLE = 0x2, 338 SDMA_PERF_SEL_RB_EMPTY = 0x3, 339 SDMA_PERF_SEL_RB_FULL = 0x4, 340 SDMA_PERF_SEL_RB_WPTR_WRAP = 0x5, 341 SDMA_PERF_SEL_RB_RPTR_WRAP = 0x6, 342 SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x7, 343 SDMA_PERF_SEL_RB_RPTR_WB = 0x8, 344 SDMA_PERF_SEL_RB_CMD_IDLE = 0x9, 345 SDMA_PERF_SEL_RB_CMD_FULL = 0xa, 346 SDMA_PERF_SEL_IB_CMD_IDLE = 0xb, 347 SDMA_PERF_SEL_IB_CMD_FULL = 0xc, 348 SDMA_PERF_SEL_EX_IDLE = 0xd, 349 SDMA_PERF_SEL_SRBM_REG_SEND = 0xe, 350 SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0xf, 351 SDMA_PERF_SEL_MC_WR_IDLE = 0x10, 352 SDMA_PERF_SEL_MC_WR_COUNT = 0x11, 353 SDMA_PERF_SEL_MC_RD_IDLE = 0x12, 354 SDMA_PERF_SEL_MC_RD_COUNT = 0x13, 355 SDMA_PERF_SEL_MC_RD_RET_STALL = 0x14, 356 SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x15, 357 SDMA_PERF_SEL_SEM_IDLE = 0x18, 358 SDMA_PERF_SEL_SEM_REQ_STALL = 0x19, 359 SDMA_PERF_SEL_SEM_REQ_COUNT = 0x1a, 360 SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x1b, 361 SDMA_PERF_SEL_SEM_RESP_FAIL = 0x1c, 362 SDMA_PERF_SEL_SEM_RESP_PASS = 0x1d, 363 SDMA_PERF_SEL_INT_IDLE = 0x1e, 364 SDMA_PERF_SEL_INT_REQ_STALL = 0x1f, 365 SDMA_PERF_SEL_INT_REQ_COUNT = 0x20, 366 SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x21, 367 SDMA_PERF_SEL_INT_RESP_RETRY = 0x22, 368 SDMA_PERF_SEL_NUM_PACKET = 0x23, 369 SDMA_PERF_SEL_CE_WREQ_IDLE = 0x25, 370 SDMA_PERF_SEL_CE_WR_IDLE = 0x26, 371 SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x27, 372 SDMA_PERF_SEL_CE_RREQ_IDLE = 0x28, 373 SDMA_PERF_SEL_CE_OUT_IDLE = 0x29, 374 SDMA_PERF_SEL_CE_IN_IDLE = 0x2a, 375 SDMA_PERF_SEL_CE_DST_IDLE = 0x2b, 376 SDMA_PERF_SEL_CE_AFIFO_FULL = 0x2e, 377 SDMA_PERF_SEL_CE_INFO_FULL = 0x31, 378 SDMA_PERF_SEL_CE_INFO1_FULL = 0x32, 379 SDMA_PERF_SEL_CE_RD_STALL = 0x33, 380 SDMA_PERF_SEL_CE_WR_STALL = 0x34, 381 SDMA_PERF_SEL_GFX_SELECT = 0x35, 382 SDMA_PERF_SEL_RLC0_SELECT = 0x36, 383 SDMA_PERF_SEL_RLC1_SELECT = 0x37, 384 SDMA_PERF_SEL_CTX_CHANGE = 0x38, 385 SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x39, 386 SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x3a, 387 SDMA_PERF_SEL_DOORBELL = 0x3b, 388 SDMA_PERF_SEL_RD_BA_RTR = 0x3c, 389 SDMA_PERF_SEL_WR_BA_RTR = 0x3d, 390 SDMA_PERF_SEL_F32_L1_WR_VLD = 0x3e, 391 SDMA_PERF_SEL_CE_L1_WR_VLD = 0x3f, 392 SDMA_PERF_SEL_CE_L1_STALL = 0x40, 393 SDMA_PERF_SEL_SDMA_INVACK_NFLUSH = 0x41, 394 SDMA_PERF_SEL_SDMA_INVACK_FLUSH = 0x42, 395 SDMA_PERF_SEL_ATCL2_INVREQ_NFLUSH = 0x43, 396 SDMA_PERF_SEL_ATCL2_INVREQ_FLUSH = 0x44, 397 SDMA_PERF_SEL_ATCL2_RET_XNACK = 0x45, 398 SDMA_PERF_SEL_ATCL2_RET_ACK = 0x46, 399 SDMA_PERF_SEL_ATCL2_FREE = 0x47, 400 SDMA_PERF_SEL_SDMA_ATCL2_SEND = 0x48, 401 SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x49, 402 SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x4a, 403 SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x4b, 404 SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x4c, 405 SDMA_PERF_SEL_L1_WR_FIFO_IDLE = 0x4d, 406 SDMA_PERF_SEL_L1_RD_FIFO_IDLE = 0x4e, 407 SDMA_PERF_SEL_L1_WRL2_IDLE = 0x4f, 408 SDMA_PERF_SEL_L1_RDL2_IDLE = 0x50, 409 SDMA_PERF_SEL_L1_WRMC_IDLE = 0x51, 410 SDMA_PERF_SEL_L1_RDMC_IDLE = 0x52, 411 SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x53, 412 SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x54, 413 SDMA_PERF_SEL_L1_WR_INV_EN = 0x55, 414 SDMA_PERF_SEL_L1_RD_INV_EN = 0x56, 415 SDMA_PERF_SEL_L1_WR_WAIT_INVADR = 0x57, 416 SDMA_PERF_SEL_L1_RD_WAIT_INVADR = 0x58, 417 SDMA_PERF_SEL_IS_INVREQ_ADDR_WR = 0x59, 418 SDMA_PERF_SEL_IS_INVREQ_ADDR_RD = 0x5a, 419 SDMA_PERF_SEL_L1_WR_XNACK_TIMEOUT = 0x5b, 420 SDMA_PERF_SEL_L1_RD_XNACK_TIMEOUT = 0x5c, 421 SDMA_PERF_SEL_L1_INV_MIDDLE = 0x5d, 422 } SDMA_PERF_SEL; 423 typedef enum DebugBlockId { 424 DBG_BLOCK_ID_RESERVED = 0x0, 425 DBG_BLOCK_ID_DBG = 0x1, 426 DBG_BLOCK_ID_VMC = 0x2, 427 DBG_BLOCK_ID_PDMA = 0x3, 428 DBG_BLOCK_ID_CG = 0x4, 429 DBG_BLOCK_ID_SRBM = 0x5, 430 DBG_BLOCK_ID_GRBM = 0x6, 431 DBG_BLOCK_ID_RLC = 0x7, 432 DBG_BLOCK_ID_CSC = 0x8, 433 DBG_BLOCK_ID_SEM = 0x9, 434 DBG_BLOCK_ID_IH = 0xa, 435 DBG_BLOCK_ID_SC = 0xb, 436 DBG_BLOCK_ID_SQ = 0xc, 437 DBG_BLOCK_ID_UVDU = 0xd, 438 DBG_BLOCK_ID_SQA = 0xe, 439 DBG_BLOCK_ID_SDMA0 = 0xf, 440 DBG_BLOCK_ID_SDMA1 = 0x10, 441 DBG_BLOCK_ID_SPIM = 0x11, 442 DBG_BLOCK_ID_GDS = 0x12, 443 DBG_BLOCK_ID_VC0 = 0x13, 444 DBG_BLOCK_ID_VC1 = 0x14, 445 DBG_BLOCK_ID_PA0 = 0x15, 446 DBG_BLOCK_ID_PA1 = 0x16, 447 DBG_BLOCK_ID_CP0 = 0x17, 448 DBG_BLOCK_ID_CP1 = 0x18, 449 DBG_BLOCK_ID_CP2 = 0x19, 450 DBG_BLOCK_ID_XBR = 0x1a, 451 DBG_BLOCK_ID_UVDM = 0x1b, 452 DBG_BLOCK_ID_VGT0 = 0x1c, 453 DBG_BLOCK_ID_VGT1 = 0x1d, 454 DBG_BLOCK_ID_IA = 0x1e, 455 DBG_BLOCK_ID_SXM0 = 0x1f, 456 DBG_BLOCK_ID_SXM1 = 0x20, 457 DBG_BLOCK_ID_SCT0 = 0x21, 458 DBG_BLOCK_ID_SCT1 = 0x22, 459 DBG_BLOCK_ID_SPM0 = 0x23, 460 DBG_BLOCK_ID_SPM1 = 0x24, 461 DBG_BLOCK_ID_UNUSED0 = 0x25, 462 DBG_BLOCK_ID_UNUSED1 = 0x26, 463 DBG_BLOCK_ID_TCAA = 0x27, 464 DBG_BLOCK_ID_TCAB = 0x28, 465 DBG_BLOCK_ID_TCCA = 0x29, 466 DBG_BLOCK_ID_TCCB = 0x2a, 467 DBG_BLOCK_ID_MCC0 = 0x2b, 468 DBG_BLOCK_ID_MCC1 = 0x2c, 469 DBG_BLOCK_ID_MCC2 = 0x2d, 470 DBG_BLOCK_ID_MCC3 = 0x2e, 471 DBG_BLOCK_ID_SXS0 = 0x2f, 472 DBG_BLOCK_ID_SXS1 = 0x30, 473 DBG_BLOCK_ID_SXS2 = 0x31, 474 DBG_BLOCK_ID_SXS3 = 0x32, 475 DBG_BLOCK_ID_SXS4 = 0x33, 476 DBG_BLOCK_ID_SXS5 = 0x34, 477 DBG_BLOCK_ID_SXS6 = 0x35, 478 DBG_BLOCK_ID_SXS7 = 0x36, 479 DBG_BLOCK_ID_SXS8 = 0x37, 480 DBG_BLOCK_ID_SXS9 = 0x38, 481 DBG_BLOCK_ID_BCI0 = 0x39, 482 DBG_BLOCK_ID_BCI1 = 0x3a, 483 DBG_BLOCK_ID_BCI2 = 0x3b, 484 DBG_BLOCK_ID_BCI3 = 0x3c, 485 DBG_BLOCK_ID_MCB = 0x3d, 486 DBG_BLOCK_ID_UNUSED6 = 0x3e, 487 DBG_BLOCK_ID_SQA00 = 0x3f, 488 DBG_BLOCK_ID_SQA01 = 0x40, 489 DBG_BLOCK_ID_SQA02 = 0x41, 490 DBG_BLOCK_ID_SQA10 = 0x42, 491 DBG_BLOCK_ID_SQA11 = 0x43, 492 DBG_BLOCK_ID_SQA12 = 0x44, 493 DBG_BLOCK_ID_UNUSED7 = 0x45, 494 DBG_BLOCK_ID_UNUSED8 = 0x46, 495 DBG_BLOCK_ID_SQB00 = 0x47, 496 DBG_BLOCK_ID_SQB01 = 0x48, 497 DBG_BLOCK_ID_SQB10 = 0x49, 498 DBG_BLOCK_ID_SQB11 = 0x4a, 499 DBG_BLOCK_ID_SQ00 = 0x4b, 500 DBG_BLOCK_ID_SQ01 = 0x4c, 501 DBG_BLOCK_ID_SQ10 = 0x4d, 502 DBG_BLOCK_ID_SQ11 = 0x4e, 503 DBG_BLOCK_ID_CB00 = 0x4f, 504 DBG_BLOCK_ID_CB01 = 0x50, 505 DBG_BLOCK_ID_CB02 = 0x51, 506 DBG_BLOCK_ID_CB03 = 0x52, 507 DBG_BLOCK_ID_CB04 = 0x53, 508 DBG_BLOCK_ID_UNUSED9 = 0x54, 509 DBG_BLOCK_ID_UNUSED10 = 0x55, 510 DBG_BLOCK_ID_UNUSED11 = 0x56, 511 DBG_BLOCK_ID_CB10 = 0x57, 512 DBG_BLOCK_ID_CB11 = 0x58, 513 DBG_BLOCK_ID_CB12 = 0x59, 514 DBG_BLOCK_ID_CB13 = 0x5a, 515 DBG_BLOCK_ID_CB14 = 0x5b, 516 DBG_BLOCK_ID_UNUSED12 = 0x5c, 517 DBG_BLOCK_ID_UNUSED13 = 0x5d, 518 DBG_BLOCK_ID_UNUSED14 = 0x5e, 519 DBG_BLOCK_ID_TCP0 = 0x5f, 520 DBG_BLOCK_ID_TCP1 = 0x60, 521 DBG_BLOCK_ID_TCP2 = 0x61, 522 DBG_BLOCK_ID_TCP3 = 0x62, 523 DBG_BLOCK_ID_TCP4 = 0x63, 524 DBG_BLOCK_ID_TCP5 = 0x64, 525 DBG_BLOCK_ID_TCP6 = 0x65, 526 DBG_BLOCK_ID_TCP7 = 0x66, 527 DBG_BLOCK_ID_TCP8 = 0x67, 528 DBG_BLOCK_ID_TCP9 = 0x68, 529 DBG_BLOCK_ID_TCP10 = 0x69, 530 DBG_BLOCK_ID_TCP11 = 0x6a, 531 DBG_BLOCK_ID_TCP12 = 0x6b, 532 DBG_BLOCK_ID_TCP13 = 0x6c, 533 DBG_BLOCK_ID_TCP14 = 0x6d, 534 DBG_BLOCK_ID_TCP15 = 0x6e, 535 DBG_BLOCK_ID_TCP16 = 0x6f, 536 DBG_BLOCK_ID_TCP17 = 0x70, 537 DBG_BLOCK_ID_TCP18 = 0x71, 538 DBG_BLOCK_ID_TCP19 = 0x72, 539 DBG_BLOCK_ID_TCP20 = 0x73, 540 DBG_BLOCK_ID_TCP21 = 0x74, 541 DBG_BLOCK_ID_TCP22 = 0x75, 542 DBG_BLOCK_ID_TCP23 = 0x76, 543 DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, 544 DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, 545 DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, 546 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, 547 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, 548 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, 549 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, 550 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, 551 DBG_BLOCK_ID_DB00 = 0x7f, 552 DBG_BLOCK_ID_DB01 = 0x80, 553 DBG_BLOCK_ID_DB02 = 0x81, 554 DBG_BLOCK_ID_DB03 = 0x82, 555 DBG_BLOCK_ID_DB04 = 0x83, 556 DBG_BLOCK_ID_UNUSED15 = 0x84, 557 DBG_BLOCK_ID_UNUSED16 = 0x85, 558 DBG_BLOCK_ID_UNUSED17 = 0x86, 559 DBG_BLOCK_ID_DB10 = 0x87, 560 DBG_BLOCK_ID_DB11 = 0x88, 561 DBG_BLOCK_ID_DB12 = 0x89, 562 DBG_BLOCK_ID_DB13 = 0x8a, 563 DBG_BLOCK_ID_DB14 = 0x8b, 564 DBG_BLOCK_ID_UNUSED18 = 0x8c, 565 DBG_BLOCK_ID_UNUSED19 = 0x8d, 566 DBG_BLOCK_ID_UNUSED20 = 0x8e, 567 DBG_BLOCK_ID_TCC0 = 0x8f, 568 DBG_BLOCK_ID_TCC1 = 0x90, 569 DBG_BLOCK_ID_TCC2 = 0x91, 570 DBG_BLOCK_ID_TCC3 = 0x92, 571 DBG_BLOCK_ID_TCC4 = 0x93, 572 DBG_BLOCK_ID_TCC5 = 0x94, 573 DBG_BLOCK_ID_TCC6 = 0x95, 574 DBG_BLOCK_ID_TCC7 = 0x96, 575 DBG_BLOCK_ID_SPS00 = 0x97, 576 DBG_BLOCK_ID_SPS01 = 0x98, 577 DBG_BLOCK_ID_SPS02 = 0x99, 578 DBG_BLOCK_ID_SPS10 = 0x9a, 579 DBG_BLOCK_ID_SPS11 = 0x9b, 580 DBG_BLOCK_ID_SPS12 = 0x9c, 581 DBG_BLOCK_ID_UNUSED21 = 0x9d, 582 DBG_BLOCK_ID_UNUSED22 = 0x9e, 583 DBG_BLOCK_ID_TA00 = 0x9f, 584 DBG_BLOCK_ID_TA01 = 0xa0, 585 DBG_BLOCK_ID_TA02 = 0xa1, 586 DBG_BLOCK_ID_TA03 = 0xa2, 587 DBG_BLOCK_ID_TA04 = 0xa3, 588 DBG_BLOCK_ID_TA05 = 0xa4, 589 DBG_BLOCK_ID_TA06 = 0xa5, 590 DBG_BLOCK_ID_TA07 = 0xa6, 591 DBG_BLOCK_ID_TA08 = 0xa7, 592 DBG_BLOCK_ID_TA09 = 0xa8, 593 DBG_BLOCK_ID_TA0A = 0xa9, 594 DBG_BLOCK_ID_TA0B = 0xaa, 595 DBG_BLOCK_ID_UNUSED23 = 0xab, 596 DBG_BLOCK_ID_UNUSED24 = 0xac, 597 DBG_BLOCK_ID_UNUSED25 = 0xad, 598 DBG_BLOCK_ID_UNUSED26 = 0xae, 599 DBG_BLOCK_ID_TA10 = 0xaf, 600 DBG_BLOCK_ID_TA11 = 0xb0, 601 DBG_BLOCK_ID_TA12 = 0xb1, 602 DBG_BLOCK_ID_TA13 = 0xb2, 603 DBG_BLOCK_ID_TA14 = 0xb3, 604 DBG_BLOCK_ID_TA15 = 0xb4, 605 DBG_BLOCK_ID_TA16 = 0xb5, 606 DBG_BLOCK_ID_TA17 = 0xb6, 607 DBG_BLOCK_ID_TA18 = 0xb7, 608 DBG_BLOCK_ID_TA19 = 0xb8, 609 DBG_BLOCK_ID_TA1A = 0xb9, 610 DBG_BLOCK_ID_TA1B = 0xba, 611 DBG_BLOCK_ID_UNUSED27 = 0xbb, 612 DBG_BLOCK_ID_UNUSED28 = 0xbc, 613 DBG_BLOCK_ID_UNUSED29 = 0xbd, 614 DBG_BLOCK_ID_UNUSED30 = 0xbe, 615 DBG_BLOCK_ID_TD00 = 0xbf, 616 DBG_BLOCK_ID_TD01 = 0xc0, 617 DBG_BLOCK_ID_TD02 = 0xc1, 618 DBG_BLOCK_ID_TD03 = 0xc2, 619 DBG_BLOCK_ID_TD04 = 0xc3, 620 DBG_BLOCK_ID_TD05 = 0xc4, 621 DBG_BLOCK_ID_TD06 = 0xc5, 622 DBG_BLOCK_ID_TD07 = 0xc6, 623 DBG_BLOCK_ID_TD08 = 0xc7, 624 DBG_BLOCK_ID_TD09 = 0xc8, 625 DBG_BLOCK_ID_TD0A = 0xc9, 626 DBG_BLOCK_ID_TD0B = 0xca, 627 DBG_BLOCK_ID_UNUSED31 = 0xcb, 628 DBG_BLOCK_ID_UNUSED32 = 0xcc, 629 DBG_BLOCK_ID_UNUSED33 = 0xcd, 630 DBG_BLOCK_ID_UNUSED34 = 0xce, 631 DBG_BLOCK_ID_TD10 = 0xcf, 632 DBG_BLOCK_ID_TD11 = 0xd0, 633 DBG_BLOCK_ID_TD12 = 0xd1, 634 DBG_BLOCK_ID_TD13 = 0xd2, 635 DBG_BLOCK_ID_TD14 = 0xd3, 636 DBG_BLOCK_ID_TD15 = 0xd4, 637 DBG_BLOCK_ID_TD16 = 0xd5, 638 DBG_BLOCK_ID_TD17 = 0xd6, 639 DBG_BLOCK_ID_TD18 = 0xd7, 640 DBG_BLOCK_ID_TD19 = 0xd8, 641 DBG_BLOCK_ID_TD1A = 0xd9, 642 DBG_BLOCK_ID_TD1B = 0xda, 643 DBG_BLOCK_ID_UNUSED35 = 0xdb, 644 DBG_BLOCK_ID_UNUSED36 = 0xdc, 645 DBG_BLOCK_ID_UNUSED37 = 0xdd, 646 DBG_BLOCK_ID_UNUSED38 = 0xde, 647 DBG_BLOCK_ID_LDS00 = 0xdf, 648 DBG_BLOCK_ID_LDS01 = 0xe0, 649 DBG_BLOCK_ID_LDS02 = 0xe1, 650 DBG_BLOCK_ID_LDS03 = 0xe2, 651 DBG_BLOCK_ID_LDS04 = 0xe3, 652 DBG_BLOCK_ID_LDS05 = 0xe4, 653 DBG_BLOCK_ID_LDS06 = 0xe5, 654 DBG_BLOCK_ID_LDS07 = 0xe6, 655 DBG_BLOCK_ID_LDS08 = 0xe7, 656 DBG_BLOCK_ID_LDS09 = 0xe8, 657 DBG_BLOCK_ID_LDS0A = 0xe9, 658 DBG_BLOCK_ID_LDS0B = 0xea, 659 DBG_BLOCK_ID_UNUSED39 = 0xeb, 660 DBG_BLOCK_ID_UNUSED40 = 0xec, 661 DBG_BLOCK_ID_UNUSED41 = 0xed, 662 DBG_BLOCK_ID_UNUSED42 = 0xee, 663 DBG_BLOCK_ID_LDS10 = 0xef, 664 DBG_BLOCK_ID_LDS11 = 0xf0, 665 DBG_BLOCK_ID_LDS12 = 0xf1, 666 DBG_BLOCK_ID_LDS13 = 0xf2, 667 DBG_BLOCK_ID_LDS14 = 0xf3, 668 DBG_BLOCK_ID_LDS15 = 0xf4, 669 DBG_BLOCK_ID_LDS16 = 0xf5, 670 DBG_BLOCK_ID_LDS17 = 0xf6, 671 DBG_BLOCK_ID_LDS18 = 0xf7, 672 DBG_BLOCK_ID_LDS19 = 0xf8, 673 DBG_BLOCK_ID_LDS1A = 0xf9, 674 DBG_BLOCK_ID_LDS1B = 0xfa, 675 DBG_BLOCK_ID_UNUSED43 = 0xfb, 676 DBG_BLOCK_ID_UNUSED44 = 0xfc, 677 DBG_BLOCK_ID_UNUSED45 = 0xfd, 678 DBG_BLOCK_ID_UNUSED46 = 0xfe, 679 } DebugBlockId; 680 typedef enum DebugBlockId_BY2 { 681 DBG_BLOCK_ID_RESERVED_BY2 = 0x0, 682 DBG_BLOCK_ID_VMC_BY2 = 0x1, 683 DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, 684 DBG_BLOCK_ID_GRBM_BY2 = 0x3, 685 DBG_BLOCK_ID_CSC_BY2 = 0x4, 686 DBG_BLOCK_ID_IH_BY2 = 0x5, 687 DBG_BLOCK_ID_SQ_BY2 = 0x6, 688 DBG_BLOCK_ID_UVD_BY2 = 0x7, 689 DBG_BLOCK_ID_SDMA0_BY2 = 0x8, 690 DBG_BLOCK_ID_SPIM_BY2 = 0x9, 691 DBG_BLOCK_ID_VC0_BY2 = 0xa, 692 DBG_BLOCK_ID_PA_BY2 = 0xb, 693 DBG_BLOCK_ID_CP0_BY2 = 0xc, 694 DBG_BLOCK_ID_CP2_BY2 = 0xd, 695 DBG_BLOCK_ID_PC0_BY2 = 0xe, 696 DBG_BLOCK_ID_BCI0_BY2 = 0xf, 697 DBG_BLOCK_ID_SXM0_BY2 = 0x10, 698 DBG_BLOCK_ID_SCT0_BY2 = 0x11, 699 DBG_BLOCK_ID_SPM0_BY2 = 0x12, 700 DBG_BLOCK_ID_BCI2_BY2 = 0x13, 701 DBG_BLOCK_ID_TCA_BY2 = 0x14, 702 DBG_BLOCK_ID_TCCA_BY2 = 0x15, 703 DBG_BLOCK_ID_MCC_BY2 = 0x16, 704 DBG_BLOCK_ID_MCC2_BY2 = 0x17, 705 DBG_BLOCK_ID_MCD_BY2 = 0x18, 706 DBG_BLOCK_ID_MCD2_BY2 = 0x19, 707 DBG_BLOCK_ID_MCD4_BY2 = 0x1a, 708 DBG_BLOCK_ID_MCB_BY2 = 0x1b, 709 DBG_BLOCK_ID_SQA_BY2 = 0x1c, 710 DBG_BLOCK_ID_SQA02_BY2 = 0x1d, 711 DBG_BLOCK_ID_SQA11_BY2 = 0x1e, 712 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, 713 DBG_BLOCK_ID_SQB_BY2 = 0x20, 714 DBG_BLOCK_ID_SQB10_BY2 = 0x21, 715 DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, 716 DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, 717 DBG_BLOCK_ID_CB_BY2 = 0x24, 718 DBG_BLOCK_ID_CB02_BY2 = 0x25, 719 DBG_BLOCK_ID_CB10_BY2 = 0x26, 720 DBG_BLOCK_ID_CB12_BY2 = 0x27, 721 DBG_BLOCK_ID_SXS_BY2 = 0x28, 722 DBG_BLOCK_ID_SXS2_BY2 = 0x29, 723 DBG_BLOCK_ID_SXS4_BY2 = 0x2a, 724 DBG_BLOCK_ID_SXS6_BY2 = 0x2b, 725 DBG_BLOCK_ID_DB_BY2 = 0x2c, 726 DBG_BLOCK_ID_DB02_BY2 = 0x2d, 727 DBG_BLOCK_ID_DB10_BY2 = 0x2e, 728 DBG_BLOCK_ID_DB12_BY2 = 0x2f, 729 DBG_BLOCK_ID_TCP_BY2 = 0x30, 730 DBG_BLOCK_ID_TCP2_BY2 = 0x31, 731 DBG_BLOCK_ID_TCP4_BY2 = 0x32, 732 DBG_BLOCK_ID_TCP6_BY2 = 0x33, 733 DBG_BLOCK_ID_TCP8_BY2 = 0x34, 734 DBG_BLOCK_ID_TCP10_BY2 = 0x35, 735 DBG_BLOCK_ID_TCP12_BY2 = 0x36, 736 DBG_BLOCK_ID_TCP14_BY2 = 0x37, 737 DBG_BLOCK_ID_TCP16_BY2 = 0x38, 738 DBG_BLOCK_ID_TCP18_BY2 = 0x39, 739 DBG_BLOCK_ID_TCP20_BY2 = 0x3a, 740 DBG_BLOCK_ID_TCP22_BY2 = 0x3b, 741 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, 742 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, 743 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, 744 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, 745 DBG_BLOCK_ID_TCC_BY2 = 0x40, 746 DBG_BLOCK_ID_TCC2_BY2 = 0x41, 747 DBG_BLOCK_ID_TCC4_BY2 = 0x42, 748 DBG_BLOCK_ID_TCC6_BY2 = 0x43, 749 DBG_BLOCK_ID_SPS_BY2 = 0x44, 750 DBG_BLOCK_ID_SPS02_BY2 = 0x45, 751 DBG_BLOCK_ID_SPS11_BY2 = 0x46, 752 DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, 753 DBG_BLOCK_ID_TA_BY2 = 0x48, 754 DBG_BLOCK_ID_TA02_BY2 = 0x49, 755 DBG_BLOCK_ID_TA04_BY2 = 0x4a, 756 DBG_BLOCK_ID_TA06_BY2 = 0x4b, 757 DBG_BLOCK_ID_TA08_BY2 = 0x4c, 758 DBG_BLOCK_ID_TA0A_BY2 = 0x4d, 759 DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, 760 DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, 761 DBG_BLOCK_ID_TA10_BY2 = 0x50, 762 DBG_BLOCK_ID_TA12_BY2 = 0x51, 763 DBG_BLOCK_ID_TA14_BY2 = 0x52, 764 DBG_BLOCK_ID_TA16_BY2 = 0x53, 765 DBG_BLOCK_ID_TA18_BY2 = 0x54, 766 DBG_BLOCK_ID_TA1A_BY2 = 0x55, 767 DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, 768 DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, 769 DBG_BLOCK_ID_TD_BY2 = 0x58, 770 DBG_BLOCK_ID_TD02_BY2 = 0x59, 771 DBG_BLOCK_ID_TD04_BY2 = 0x5a, 772 DBG_BLOCK_ID_TD06_BY2 = 0x5b, 773 DBG_BLOCK_ID_TD08_BY2 = 0x5c, 774 DBG_BLOCK_ID_TD0A_BY2 = 0x5d, 775 DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, 776 DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, 777 DBG_BLOCK_ID_TD10_BY2 = 0x60, 778 DBG_BLOCK_ID_TD12_BY2 = 0x61, 779 DBG_BLOCK_ID_TD14_BY2 = 0x62, 780 DBG_BLOCK_ID_TD16_BY2 = 0x63, 781 DBG_BLOCK_ID_TD18_BY2 = 0x64, 782 DBG_BLOCK_ID_TD1A_BY2 = 0x65, 783 DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, 784 DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, 785 DBG_BLOCK_ID_LDS_BY2 = 0x68, 786 DBG_BLOCK_ID_LDS02_BY2 = 0x69, 787 DBG_BLOCK_ID_LDS04_BY2 = 0x6a, 788 DBG_BLOCK_ID_LDS06_BY2 = 0x6b, 789 DBG_BLOCK_ID_LDS08_BY2 = 0x6c, 790 DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, 791 DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, 792 DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, 793 DBG_BLOCK_ID_LDS10_BY2 = 0x70, 794 DBG_BLOCK_ID_LDS12_BY2 = 0x71, 795 DBG_BLOCK_ID_LDS14_BY2 = 0x72, 796 DBG_BLOCK_ID_LDS16_BY2 = 0x73, 797 DBG_BLOCK_ID_LDS18_BY2 = 0x74, 798 DBG_BLOCK_ID_LDS1A_BY2 = 0x75, 799 DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, 800 DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, 801 } DebugBlockId_BY2; 802 typedef enum DebugBlockId_BY4 { 803 DBG_BLOCK_ID_RESERVED_BY4 = 0x0, 804 DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, 805 DBG_BLOCK_ID_CSC_BY4 = 0x2, 806 DBG_BLOCK_ID_SQ_BY4 = 0x3, 807 DBG_BLOCK_ID_SDMA0_BY4 = 0x4, 808 DBG_BLOCK_ID_VC0_BY4 = 0x5, 809 DBG_BLOCK_ID_CP0_BY4 = 0x6, 810 DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, 811 DBG_BLOCK_ID_SXM0_BY4 = 0x8, 812 DBG_BLOCK_ID_SPM0_BY4 = 0x9, 813 DBG_BLOCK_ID_TCAA_BY4 = 0xa, 814 DBG_BLOCK_ID_MCC_BY4 = 0xb, 815 DBG_BLOCK_ID_MCD_BY4 = 0xc, 816 DBG_BLOCK_ID_MCD4_BY4 = 0xd, 817 DBG_BLOCK_ID_SQA_BY4 = 0xe, 818 DBG_BLOCK_ID_SQA11_BY4 = 0xf, 819 DBG_BLOCK_ID_SQB_BY4 = 0x10, 820 DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, 821 DBG_BLOCK_ID_CB_BY4 = 0x12, 822 DBG_BLOCK_ID_CB10_BY4 = 0x13, 823 DBG_BLOCK_ID_SXS_BY4 = 0x14, 824 DBG_BLOCK_ID_SXS4_BY4 = 0x15, 825 DBG_BLOCK_ID_DB_BY4 = 0x16, 826 DBG_BLOCK_ID_DB10_BY4 = 0x17, 827 DBG_BLOCK_ID_TCP_BY4 = 0x18, 828 DBG_BLOCK_ID_TCP4_BY4 = 0x19, 829 DBG_BLOCK_ID_TCP8_BY4 = 0x1a, 830 DBG_BLOCK_ID_TCP12_BY4 = 0x1b, 831 DBG_BLOCK_ID_TCP16_BY4 = 0x1c, 832 DBG_BLOCK_ID_TCP20_BY4 = 0x1d, 833 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, 834 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, 835 DBG_BLOCK_ID_TCC_BY4 = 0x20, 836 DBG_BLOCK_ID_TCC4_BY4 = 0x21, 837 DBG_BLOCK_ID_SPS_BY4 = 0x22, 838 DBG_BLOCK_ID_SPS11_BY4 = 0x23, 839 DBG_BLOCK_ID_TA_BY4 = 0x24, 840 DBG_BLOCK_ID_TA04_BY4 = 0x25, 841 DBG_BLOCK_ID_TA08_BY4 = 0x26, 842 DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, 843 DBG_BLOCK_ID_TA10_BY4 = 0x28, 844 DBG_BLOCK_ID_TA14_BY4 = 0x29, 845 DBG_BLOCK_ID_TA18_BY4 = 0x2a, 846 DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, 847 DBG_BLOCK_ID_TD_BY4 = 0x2c, 848 DBG_BLOCK_ID_TD04_BY4 = 0x2d, 849 DBG_BLOCK_ID_TD08_BY4 = 0x2e, 850 DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, 851 DBG_BLOCK_ID_TD10_BY4 = 0x30, 852 DBG_BLOCK_ID_TD14_BY4 = 0x31, 853 DBG_BLOCK_ID_TD18_BY4 = 0x32, 854 DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, 855 DBG_BLOCK_ID_LDS_BY4 = 0x34, 856 DBG_BLOCK_ID_LDS04_BY4 = 0x35, 857 DBG_BLOCK_ID_LDS08_BY4 = 0x36, 858 DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, 859 DBG_BLOCK_ID_LDS10_BY4 = 0x38, 860 DBG_BLOCK_ID_LDS14_BY4 = 0x39, 861 DBG_BLOCK_ID_LDS18_BY4 = 0x3a, 862 DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, 863 } DebugBlockId_BY4; 864 typedef enum DebugBlockId_BY8 { 865 DBG_BLOCK_ID_RESERVED_BY8 = 0x0, 866 DBG_BLOCK_ID_CSC_BY8 = 0x1, 867 DBG_BLOCK_ID_SDMA0_BY8 = 0x2, 868 DBG_BLOCK_ID_CP0_BY8 = 0x3, 869 DBG_BLOCK_ID_SXM0_BY8 = 0x4, 870 DBG_BLOCK_ID_TCA_BY8 = 0x5, 871 DBG_BLOCK_ID_MCD_BY8 = 0x6, 872 DBG_BLOCK_ID_SQA_BY8 = 0x7, 873 DBG_BLOCK_ID_SQB_BY8 = 0x8, 874 DBG_BLOCK_ID_CB_BY8 = 0x9, 875 DBG_BLOCK_ID_SXS_BY8 = 0xa, 876 DBG_BLOCK_ID_DB_BY8 = 0xb, 877 DBG_BLOCK_ID_TCP_BY8 = 0xc, 878 DBG_BLOCK_ID_TCP8_BY8 = 0xd, 879 DBG_BLOCK_ID_TCP16_BY8 = 0xe, 880 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, 881 DBG_BLOCK_ID_TCC_BY8 = 0x10, 882 DBG_BLOCK_ID_SPS_BY8 = 0x11, 883 DBG_BLOCK_ID_TA_BY8 = 0x12, 884 DBG_BLOCK_ID_TA08_BY8 = 0x13, 885 DBG_BLOCK_ID_TA10_BY8 = 0x14, 886 DBG_BLOCK_ID_TA18_BY8 = 0x15, 887 DBG_BLOCK_ID_TD_BY8 = 0x16, 888 DBG_BLOCK_ID_TD08_BY8 = 0x17, 889 DBG_BLOCK_ID_TD10_BY8 = 0x18, 890 DBG_BLOCK_ID_TD18_BY8 = 0x19, 891 DBG_BLOCK_ID_LDS_BY8 = 0x1a, 892 DBG_BLOCK_ID_LDS08_BY8 = 0x1b, 893 DBG_BLOCK_ID_LDS10_BY8 = 0x1c, 894 DBG_BLOCK_ID_LDS18_BY8 = 0x1d, 895 } DebugBlockId_BY8; 896 typedef enum DebugBlockId_BY16 { 897 DBG_BLOCK_ID_RESERVED_BY16 = 0x0, 898 DBG_BLOCK_ID_SDMA0_BY16 = 0x1, 899 DBG_BLOCK_ID_SXM_BY16 = 0x2, 900 DBG_BLOCK_ID_MCD_BY16 = 0x3, 901 DBG_BLOCK_ID_SQB_BY16 = 0x4, 902 DBG_BLOCK_ID_SXS_BY16 = 0x5, 903 DBG_BLOCK_ID_TCP_BY16 = 0x6, 904 DBG_BLOCK_ID_TCP16_BY16 = 0x7, 905 DBG_BLOCK_ID_TCC_BY16 = 0x8, 906 DBG_BLOCK_ID_TA_BY16 = 0x9, 907 DBG_BLOCK_ID_TA10_BY16 = 0xa, 908 DBG_BLOCK_ID_TD_BY16 = 0xb, 909 DBG_BLOCK_ID_TD10_BY16 = 0xc, 910 DBG_BLOCK_ID_LDS_BY16 = 0xd, 911 DBG_BLOCK_ID_LDS10_BY16 = 0xe, 912 } DebugBlockId_BY16; 913 typedef enum SurfaceEndian { 914 ENDIAN_NONE = 0x0, 915 ENDIAN_8IN16 = 0x1, 916 ENDIAN_8IN32 = 0x2, 917 ENDIAN_8IN64 = 0x3, 918 } SurfaceEndian; 919 typedef enum ArrayMode { 920 ARRAY_LINEAR_GENERAL = 0x0, 921 ARRAY_LINEAR_ALIGNED = 0x1, 922 ARRAY_1D_TILED_THIN1 = 0x2, 923 ARRAY_1D_TILED_THICK = 0x3, 924 ARRAY_2D_TILED_THIN1 = 0x4, 925 ARRAY_PRT_TILED_THIN1 = 0x5, 926 ARRAY_PRT_2D_TILED_THIN1 = 0x6, 927 ARRAY_2D_TILED_THICK = 0x7, 928 ARRAY_2D_TILED_XTHICK = 0x8, 929 ARRAY_PRT_TILED_THICK = 0x9, 930 ARRAY_PRT_2D_TILED_THICK = 0xa, 931 ARRAY_PRT_3D_TILED_THIN1 = 0xb, 932 ARRAY_3D_TILED_THIN1 = 0xc, 933 ARRAY_3D_TILED_THICK = 0xd, 934 ARRAY_3D_TILED_XTHICK = 0xe, 935 ARRAY_PRT_3D_TILED_THICK = 0xf, 936 } ArrayMode; 937 typedef enum PipeTiling { 938 CONFIG_1_PIPE = 0x0, 939 CONFIG_2_PIPE = 0x1, 940 CONFIG_4_PIPE = 0x2, 941 CONFIG_8_PIPE = 0x3, 942 } PipeTiling; 943 typedef enum BankTiling { 944 CONFIG_4_BANK = 0x0, 945 CONFIG_8_BANK = 0x1, 946 } BankTiling; 947 typedef enum GroupInterleave { 948 CONFIG_256B_GROUP = 0x0, 949 CONFIG_512B_GROUP = 0x1, 950 } GroupInterleave; 951 typedef enum RowTiling { 952 CONFIG_1KB_ROW = 0x0, 953 CONFIG_2KB_ROW = 0x1, 954 CONFIG_4KB_ROW = 0x2, 955 CONFIG_8KB_ROW = 0x3, 956 CONFIG_1KB_ROW_OPT = 0x4, 957 CONFIG_2KB_ROW_OPT = 0x5, 958 CONFIG_4KB_ROW_OPT = 0x6, 959 CONFIG_8KB_ROW_OPT = 0x7, 960 } RowTiling; 961 typedef enum BankSwapBytes { 962 CONFIG_128B_SWAPS = 0x0, 963 CONFIG_256B_SWAPS = 0x1, 964 CONFIG_512B_SWAPS = 0x2, 965 CONFIG_1KB_SWAPS = 0x3, 966 } BankSwapBytes; 967 typedef enum SampleSplitBytes { 968 CONFIG_1KB_SPLIT = 0x0, 969 CONFIG_2KB_SPLIT = 0x1, 970 CONFIG_4KB_SPLIT = 0x2, 971 CONFIG_8KB_SPLIT = 0x3, 972 } SampleSplitBytes; 973 typedef enum NumPipes { 974 ADDR_CONFIG_1_PIPE = 0x0, 975 ADDR_CONFIG_2_PIPE = 0x1, 976 ADDR_CONFIG_4_PIPE = 0x2, 977 ADDR_CONFIG_8_PIPE = 0x3, 978 } NumPipes; 979 typedef enum PipeInterleaveSize { 980 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, 981 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, 982 } PipeInterleaveSize; 983 typedef enum BankInterleaveSize { 984 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, 985 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, 986 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, 987 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, 988 } BankInterleaveSize; 989 typedef enum NumShaderEngines { 990 ADDR_CONFIG_1_SHADER_ENGINE = 0x0, 991 ADDR_CONFIG_2_SHADER_ENGINE = 0x1, 992 } NumShaderEngines; 993 typedef enum ShaderEngineTileSize { 994 ADDR_CONFIG_SE_TILE_16 = 0x0, 995 ADDR_CONFIG_SE_TILE_32 = 0x1, 996 } ShaderEngineTileSize; 997 typedef enum NumGPUs { 998 ADDR_CONFIG_1_GPU = 0x0, 999 ADDR_CONFIG_2_GPU = 0x1, 1000 ADDR_CONFIG_4_GPU = 0x2, 1001 } NumGPUs; 1002 typedef enum MultiGPUTileSize { 1003 ADDR_CONFIG_GPU_TILE_16 = 0x0, 1004 ADDR_CONFIG_GPU_TILE_32 = 0x1, 1005 ADDR_CONFIG_GPU_TILE_64 = 0x2, 1006 ADDR_CONFIG_GPU_TILE_128 = 0x3, 1007 } MultiGPUTileSize; 1008 typedef enum RowSize { 1009 ADDR_CONFIG_1KB_ROW = 0x0, 1010 ADDR_CONFIG_2KB_ROW = 0x1, 1011 ADDR_CONFIG_4KB_ROW = 0x2, 1012 } RowSize; 1013 typedef enum NumLowerPipes { 1014 ADDR_CONFIG_1_LOWER_PIPES = 0x0, 1015 ADDR_CONFIG_2_LOWER_PIPES = 0x1, 1016 } NumLowerPipes; 1017 typedef enum ColorTransform { 1018 DCC_CT_AUTO = 0x0, 1019 DCC_CT_NONE = 0x1, 1020 ABGR_TO_A_BG_G_RB = 0x2, 1021 BGRA_TO_BG_G_RB_A = 0x3, 1022 } ColorTransform; 1023 typedef enum CompareRef { 1024 REF_NEVER = 0x0, 1025 REF_LESS = 0x1, 1026 REF_EQUAL = 0x2, 1027 REF_LEQUAL = 0x3, 1028 REF_GREATER = 0x4, 1029 REF_NOTEQUAL = 0x5, 1030 REF_GEQUAL = 0x6, 1031 REF_ALWAYS = 0x7, 1032 } CompareRef; 1033 typedef enum ReadSize { 1034 READ_256_BITS = 0x0, 1035 READ_512_BITS = 0x1, 1036 } ReadSize; 1037 typedef enum DepthFormat { 1038 DEPTH_INVALID = 0x0, 1039 DEPTH_16 = 0x1, 1040 DEPTH_X8_24 = 0x2, 1041 DEPTH_8_24 = 0x3, 1042 DEPTH_X8_24_FLOAT = 0x4, 1043 DEPTH_8_24_FLOAT = 0x5, 1044 DEPTH_32_FLOAT = 0x6, 1045 DEPTH_X24_8_32_FLOAT = 0x7, 1046 } DepthFormat; 1047 typedef enum ZFormat { 1048 Z_INVALID = 0x0, 1049 Z_16 = 0x1, 1050 Z_24 = 0x2, 1051 Z_32_FLOAT = 0x3, 1052 } ZFormat; 1053 typedef enum StencilFormat { 1054 STENCIL_INVALID = 0x0, 1055 STENCIL_8 = 0x1, 1056 } StencilFormat; 1057 typedef enum CmaskMode { 1058 CMASK_CLEAR_NONE = 0x0, 1059 CMASK_CLEAR_ONE = 0x1, 1060 CMASK_CLEAR_ALL = 0x2, 1061 CMASK_ANY_EXPANDED = 0x3, 1062 CMASK_ALPHA0_FRAG1 = 0x4, 1063 CMASK_ALPHA0_FRAG2 = 0x5, 1064 CMASK_ALPHA0_FRAG4 = 0x6, 1065 CMASK_ALPHA0_FRAGS = 0x7, 1066 CMASK_ALPHA1_FRAG1 = 0x8, 1067 CMASK_ALPHA1_FRAG2 = 0x9, 1068 CMASK_ALPHA1_FRAG4 = 0xa, 1069 CMASK_ALPHA1_FRAGS = 0xb, 1070 CMASK_ALPHAX_FRAG1 = 0xc, 1071 CMASK_ALPHAX_FRAG2 = 0xd, 1072 CMASK_ALPHAX_FRAG4 = 0xe, 1073 CMASK_ALPHAX_FRAGS = 0xf, 1074 } CmaskMode; 1075 typedef enum QuadExportFormat { 1076 EXPORT_UNUSED = 0x0, 1077 EXPORT_32_R = 0x1, 1078 EXPORT_32_GR = 0x2, 1079 EXPORT_32_AR = 0x3, 1080 EXPORT_FP16_ABGR = 0x4, 1081 EXPORT_UNSIGNED16_ABGR = 0x5, 1082 EXPORT_SIGNED16_ABGR = 0x6, 1083 EXPORT_32_ABGR = 0x7, 1084 } QuadExportFormat; 1085 typedef enum QuadExportFormatOld { 1086 EXPORT_4P_32BPC_ABGR = 0x0, 1087 EXPORT_4P_16BPC_ABGR = 0x1, 1088 EXPORT_4P_32BPC_GR = 0x2, 1089 EXPORT_4P_32BPC_AR = 0x3, 1090 EXPORT_2P_32BPC_ABGR = 0x4, 1091 EXPORT_8P_32BPC_R = 0x5, 1092 } QuadExportFormatOld; 1093 typedef enum ColorFormat { 1094 COLOR_INVALID = 0x0, 1095 COLOR_8 = 0x1, 1096 COLOR_16 = 0x2, 1097 COLOR_8_8 = 0x3, 1098 COLOR_32 = 0x4, 1099 COLOR_16_16 = 0x5, 1100 COLOR_10_11_11 = 0x6, 1101 COLOR_11_11_10 = 0x7, 1102 COLOR_10_10_10_2 = 0x8, 1103 COLOR_2_10_10_10 = 0x9, 1104 COLOR_8_8_8_8 = 0xa, 1105 COLOR_32_32 = 0xb, 1106 COLOR_16_16_16_16 = 0xc, 1107 COLOR_RESERVED_13 = 0xd, 1108 COLOR_32_32_32_32 = 0xe, 1109 COLOR_RESERVED_15 = 0xf, 1110 COLOR_5_6_5 = 0x10, 1111 COLOR_1_5_5_5 = 0x11, 1112 COLOR_5_5_5_1 = 0x12, 1113 COLOR_4_4_4_4 = 0x13, 1114 COLOR_8_24 = 0x14, 1115 COLOR_24_8 = 0x15, 1116 COLOR_X24_8_32_FLOAT = 0x16, 1117 COLOR_RESERVED_23 = 0x17, 1118 } ColorFormat; 1119 typedef enum SurfaceFormat { 1120 FMT_INVALID = 0x0, 1121 FMT_8 = 0x1, 1122 FMT_16 = 0x2, 1123 FMT_8_8 = 0x3, 1124 FMT_32 = 0x4, 1125 FMT_16_16 = 0x5, 1126 FMT_10_11_11 = 0x6, 1127 FMT_11_11_10 = 0x7, 1128 FMT_10_10_10_2 = 0x8, 1129 FMT_2_10_10_10 = 0x9, 1130 FMT_8_8_8_8 = 0xa, 1131 FMT_32_32 = 0xb, 1132 FMT_16_16_16_16 = 0xc, 1133 FMT_32_32_32 = 0xd, 1134 FMT_32_32_32_32 = 0xe, 1135 FMT_RESERVED_4 = 0xf, 1136 FMT_5_6_5 = 0x10, 1137 FMT_1_5_5_5 = 0x11, 1138 FMT_5_5_5_1 = 0x12, 1139 FMT_4_4_4_4 = 0x13, 1140 FMT_8_24 = 0x14, 1141 FMT_24_8 = 0x15, 1142 FMT_X24_8_32_FLOAT = 0x16, 1143 FMT_RESERVED_33 = 0x17, 1144 FMT_11_11_10_FLOAT = 0x18, 1145 FMT_16_FLOAT = 0x19, 1146 FMT_32_FLOAT = 0x1a, 1147 FMT_16_16_FLOAT = 0x1b, 1148 FMT_8_24_FLOAT = 0x1c, 1149 FMT_24_8_FLOAT = 0x1d, 1150 FMT_32_32_FLOAT = 0x1e, 1151 FMT_10_11_11_FLOAT = 0x1f, 1152 FMT_16_16_16_16_FLOAT = 0x20, 1153 FMT_3_3_2 = 0x21, 1154 FMT_6_5_5 = 0x22, 1155 FMT_32_32_32_32_FLOAT = 0x23, 1156 FMT_RESERVED_36 = 0x24, 1157 FMT_1 = 0x25, 1158 FMT_1_REVERSED = 0x26, 1159 FMT_GB_GR = 0x27, 1160 FMT_BG_RG = 0x28, 1161 FMT_32_AS_8 = 0x29, 1162 FMT_32_AS_8_8 = 0x2a, 1163 FMT_5_9_9_9_SHAREDEXP = 0x2b, 1164 FMT_8_8_8 = 0x2c, 1165 FMT_16_16_16 = 0x2d, 1166 FMT_16_16_16_FLOAT = 0x2e, 1167 FMT_4_4 = 0x2f, 1168 FMT_32_32_32_FLOAT = 0x30, 1169 FMT_BC1 = 0x31, 1170 FMT_BC2 = 0x32, 1171 FMT_BC3 = 0x33, 1172 FMT_BC4 = 0x34, 1173 FMT_BC5 = 0x35, 1174 FMT_BC6 = 0x36, 1175 FMT_BC7 = 0x37, 1176 FMT_32_AS_32_32_32_32 = 0x38, 1177 FMT_APC3 = 0x39, 1178 FMT_APC4 = 0x3a, 1179 FMT_APC5 = 0x3b, 1180 FMT_APC6 = 0x3c, 1181 FMT_APC7 = 0x3d, 1182 FMT_CTX1 = 0x3e, 1183 FMT_RESERVED_63 = 0x3f, 1184 } SurfaceFormat; 1185 typedef enum BUF_DATA_FORMAT { 1186 BUF_DATA_FORMAT_INVALID = 0x0, 1187 BUF_DATA_FORMAT_8 = 0x1, 1188 BUF_DATA_FORMAT_16 = 0x2, 1189 BUF_DATA_FORMAT_8_8 = 0x3, 1190 BUF_DATA_FORMAT_32 = 0x4, 1191 BUF_DATA_FORMAT_16_16 = 0x5, 1192 BUF_DATA_FORMAT_10_11_11 = 0x6, 1193 BUF_DATA_FORMAT_11_11_10 = 0x7, 1194 BUF_DATA_FORMAT_10_10_10_2 = 0x8, 1195 BUF_DATA_FORMAT_2_10_10_10 = 0x9, 1196 BUF_DATA_FORMAT_8_8_8_8 = 0xa, 1197 BUF_DATA_FORMAT_32_32 = 0xb, 1198 BUF_DATA_FORMAT_16_16_16_16 = 0xc, 1199 BUF_DATA_FORMAT_32_32_32 = 0xd, 1200 BUF_DATA_FORMAT_32_32_32_32 = 0xe, 1201 BUF_DATA_FORMAT_RESERVED_15 = 0xf, 1202 } BUF_DATA_FORMAT; 1203 typedef enum IMG_DATA_FORMAT { 1204 IMG_DATA_FORMAT_INVALID = 0x0, 1205 IMG_DATA_FORMAT_8 = 0x1, 1206 IMG_DATA_FORMAT_16 = 0x2, 1207 IMG_DATA_FORMAT_8_8 = 0x3, 1208 IMG_DATA_FORMAT_32 = 0x4, 1209 IMG_DATA_FORMAT_16_16 = 0x5, 1210 IMG_DATA_FORMAT_10_11_11 = 0x6, 1211 IMG_DATA_FORMAT_11_11_10 = 0x7, 1212 IMG_DATA_FORMAT_10_10_10_2 = 0x8, 1213 IMG_DATA_FORMAT_2_10_10_10 = 0x9, 1214 IMG_DATA_FORMAT_8_8_8_8 = 0xa, 1215 IMG_DATA_FORMAT_32_32 = 0xb, 1216 IMG_DATA_FORMAT_16_16_16_16 = 0xc, 1217 IMG_DATA_FORMAT_32_32_32 = 0xd, 1218 IMG_DATA_FORMAT_32_32_32_32 = 0xe, 1219 IMG_DATA_FORMAT_RESERVED_15 = 0xf, 1220 IMG_DATA_FORMAT_5_6_5 = 0x10, 1221 IMG_DATA_FORMAT_1_5_5_5 = 0x11, 1222 IMG_DATA_FORMAT_5_5_5_1 = 0x12, 1223 IMG_DATA_FORMAT_4_4_4_4 = 0x13, 1224 IMG_DATA_FORMAT_8_24 = 0x14, 1225 IMG_DATA_FORMAT_24_8 = 0x15, 1226 IMG_DATA_FORMAT_X24_8_32 = 0x16, 1227 IMG_DATA_FORMAT_RESERVED_23 = 0x17, 1228 IMG_DATA_FORMAT_RESERVED_24 = 0x18, 1229 IMG_DATA_FORMAT_RESERVED_25 = 0x19, 1230 IMG_DATA_FORMAT_RESERVED_26 = 0x1a, 1231 IMG_DATA_FORMAT_RESERVED_27 = 0x1b, 1232 IMG_DATA_FORMAT_RESERVED_28 = 0x1c, 1233 IMG_DATA_FORMAT_RESERVED_29 = 0x1d, 1234 IMG_DATA_FORMAT_RESERVED_30 = 0x1e, 1235 IMG_DATA_FORMAT_RESERVED_31 = 0x1f, 1236 IMG_DATA_FORMAT_GB_GR = 0x20, 1237 IMG_DATA_FORMAT_BG_RG = 0x21, 1238 IMG_DATA_FORMAT_5_9_9_9 = 0x22, 1239 IMG_DATA_FORMAT_BC1 = 0x23, 1240 IMG_DATA_FORMAT_BC2 = 0x24, 1241 IMG_DATA_FORMAT_BC3 = 0x25, 1242 IMG_DATA_FORMAT_BC4 = 0x26, 1243 IMG_DATA_FORMAT_BC5 = 0x27, 1244 IMG_DATA_FORMAT_BC6 = 0x28, 1245 IMG_DATA_FORMAT_BC7 = 0x29, 1246 IMG_DATA_FORMAT_RESERVED_42 = 0x2a, 1247 IMG_DATA_FORMAT_RESERVED_43 = 0x2b, 1248 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, 1249 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, 1250 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, 1251 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, 1252 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, 1253 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, 1254 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, 1255 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, 1256 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, 1257 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, 1258 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, 1259 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, 1260 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, 1261 IMG_DATA_FORMAT_4_4 = 0x39, 1262 IMG_DATA_FORMAT_6_5_5 = 0x3a, 1263 IMG_DATA_FORMAT_1 = 0x3b, 1264 IMG_DATA_FORMAT_1_REVERSED = 0x3c, 1265 IMG_DATA_FORMAT_32_AS_8 = 0x3d, 1266 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e, 1267 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, 1268 } IMG_DATA_FORMAT; 1269 typedef enum BUF_NUM_FORMAT { 1270 BUF_NUM_FORMAT_UNORM = 0x0, 1271 BUF_NUM_FORMAT_SNORM = 0x1, 1272 BUF_NUM_FORMAT_USCALED = 0x2, 1273 BUF_NUM_FORMAT_SSCALED = 0x3, 1274 BUF_NUM_FORMAT_UINT = 0x4, 1275 BUF_NUM_FORMAT_SINT = 0x5, 1276 BUF_NUM_FORMAT_RESERVED_6 = 0x6, 1277 BUF_NUM_FORMAT_FLOAT = 0x7, 1278 } BUF_NUM_FORMAT; 1279 typedef enum IMG_NUM_FORMAT { 1280 IMG_NUM_FORMAT_UNORM = 0x0, 1281 IMG_NUM_FORMAT_SNORM = 0x1, 1282 IMG_NUM_FORMAT_USCALED = 0x2, 1283 IMG_NUM_FORMAT_SSCALED = 0x3, 1284 IMG_NUM_FORMAT_UINT = 0x4, 1285 IMG_NUM_FORMAT_SINT = 0x5, 1286 IMG_NUM_FORMAT_RESERVED_6 = 0x6, 1287 IMG_NUM_FORMAT_FLOAT = 0x7, 1288 IMG_NUM_FORMAT_RESERVED_8 = 0x8, 1289 IMG_NUM_FORMAT_SRGB = 0x9, 1290 IMG_NUM_FORMAT_RESERVED_10 = 0xa, 1291 IMG_NUM_FORMAT_RESERVED_11 = 0xb, 1292 IMG_NUM_FORMAT_RESERVED_12 = 0xc, 1293 IMG_NUM_FORMAT_RESERVED_13 = 0xd, 1294 IMG_NUM_FORMAT_RESERVED_14 = 0xe, 1295 IMG_NUM_FORMAT_RESERVED_15 = 0xf, 1296 } IMG_NUM_FORMAT; 1297 typedef enum TileType { 1298 ARRAY_COLOR_TILE = 0x0, 1299 ARRAY_DEPTH_TILE = 0x1, 1300 } TileType; 1301 typedef enum NonDispTilingOrder { 1302 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, 1303 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, 1304 } NonDispTilingOrder; 1305 typedef enum MicroTileMode { 1306 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, 1307 ADDR_SURF_THIN_MICRO_TILING = 0x1, 1308 ADDR_SURF_DEPTH_MICRO_TILING = 0x2, 1309 ADDR_SURF_ROTATED_MICRO_TILING = 0x3, 1310 ADDR_SURF_THICK_MICRO_TILING = 0x4, 1311 } MicroTileMode; 1312 typedef enum TileSplit { 1313 ADDR_SURF_TILE_SPLIT_64B = 0x0, 1314 ADDR_SURF_TILE_SPLIT_128B = 0x1, 1315 ADDR_SURF_TILE_SPLIT_256B = 0x2, 1316 ADDR_SURF_TILE_SPLIT_512B = 0x3, 1317 ADDR_SURF_TILE_SPLIT_1KB = 0x4, 1318 ADDR_SURF_TILE_SPLIT_2KB = 0x5, 1319 ADDR_SURF_TILE_SPLIT_4KB = 0x6, 1320 } TileSplit; 1321 typedef enum SampleSplit { 1322 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, 1323 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, 1324 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, 1325 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, 1326 } SampleSplit; 1327 typedef enum PipeConfig { 1328 ADDR_SURF_P2 = 0x0, 1329 ADDR_SURF_P2_RESERVED0 = 0x1, 1330 ADDR_SURF_P2_RESERVED1 = 0x2, 1331 ADDR_SURF_P2_RESERVED2 = 0x3, 1332 ADDR_SURF_P4_8x16 = 0x4, 1333 ADDR_SURF_P4_16x16 = 0x5, 1334 ADDR_SURF_P4_16x32 = 0x6, 1335 ADDR_SURF_P4_32x32 = 0x7, 1336 ADDR_SURF_P8_16x16_8x16 = 0x8, 1337 ADDR_SURF_P8_16x32_8x16 = 0x9, 1338 ADDR_SURF_P8_32x32_8x16 = 0xa, 1339 ADDR_SURF_P8_16x32_16x16 = 0xb, 1340 ADDR_SURF_P8_32x32_16x16 = 0xc, 1341 ADDR_SURF_P8_32x32_16x32 = 0xd, 1342 ADDR_SURF_P8_32x64_32x32 = 0xe, 1343 ADDR_SURF_P8_RESERVED0 = 0xf, 1344 ADDR_SURF_P16_32x32_8x16 = 0x10, 1345 ADDR_SURF_P16_32x32_16x16 = 0x11, 1346 } PipeConfig; 1347 typedef enum NumBanks { 1348 ADDR_SURF_2_BANK = 0x0, 1349 ADDR_SURF_4_BANK = 0x1, 1350 ADDR_SURF_8_BANK = 0x2, 1351 ADDR_SURF_16_BANK = 0x3, 1352 } NumBanks; 1353 typedef enum BankWidth { 1354 ADDR_SURF_BANK_WIDTH_1 = 0x0, 1355 ADDR_SURF_BANK_WIDTH_2 = 0x1, 1356 ADDR_SURF_BANK_WIDTH_4 = 0x2, 1357 ADDR_SURF_BANK_WIDTH_8 = 0x3, 1358 } BankWidth; 1359 typedef enum BankHeight { 1360 ADDR_SURF_BANK_HEIGHT_1 = 0x0, 1361 ADDR_SURF_BANK_HEIGHT_2 = 0x1, 1362 ADDR_SURF_BANK_HEIGHT_4 = 0x2, 1363 ADDR_SURF_BANK_HEIGHT_8 = 0x3, 1364 } BankHeight; 1365 typedef enum BankWidthHeight { 1366 ADDR_SURF_BANK_WH_1 = 0x0, 1367 ADDR_SURF_BANK_WH_2 = 0x1, 1368 ADDR_SURF_BANK_WH_4 = 0x2, 1369 ADDR_SURF_BANK_WH_8 = 0x3, 1370 } BankWidthHeight; 1371 typedef enum MacroTileAspect { 1372 ADDR_SURF_MACRO_ASPECT_1 = 0x0, 1373 ADDR_SURF_MACRO_ASPECT_2 = 0x1, 1374 ADDR_SURF_MACRO_ASPECT_4 = 0x2, 1375 ADDR_SURF_MACRO_ASPECT_8 = 0x3, 1376 } MacroTileAspect; 1377 typedef enum GATCL1RequestType { 1378 GATCL1_TYPE_NORMAL = 0x0, 1379 GATCL1_TYPE_SHOOTDOWN = 0x1, 1380 GATCL1_TYPE_BYPASS = 0x2, 1381 } GATCL1RequestType; 1382 typedef enum TCC_CACHE_POLICIES { 1383 TCC_CACHE_POLICY_LRU = 0x0, 1384 TCC_CACHE_POLICY_STREAM = 0x1, 1385 } TCC_CACHE_POLICIES; 1386 typedef enum MTYPE { 1387 MTYPE_NC_NV = 0x0, 1388 MTYPE_NC = 0x1, 1389 MTYPE_CC = 0x2, 1390 MTYPE_UC = 0x3, 1391 } MTYPE; 1392 typedef enum PERFMON_COUNTER_MODE { 1393 PERFMON_COUNTER_MODE_ACCUM = 0x0, 1394 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, 1395 PERFMON_COUNTER_MODE_MAX = 0x2, 1396 PERFMON_COUNTER_MODE_DIRTY = 0x3, 1397 PERFMON_COUNTER_MODE_SAMPLE = 0x4, 1398 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, 1399 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, 1400 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, 1401 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, 1402 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, 1403 PERFMON_COUNTER_MODE_RESERVED = 0xf, 1404 } PERFMON_COUNTER_MODE; 1405 typedef enum PERFMON_SPM_MODE { 1406 PERFMON_SPM_MODE_OFF = 0x0, 1407 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, 1408 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, 1409 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, 1410 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, 1411 PERFMON_SPM_MODE_RESERVED_5 = 0x5, 1412 PERFMON_SPM_MODE_RESERVED_6 = 0x6, 1413 PERFMON_SPM_MODE_RESERVED_7 = 0x7, 1414 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, 1415 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, 1416 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, 1417 } PERFMON_SPM_MODE; 1418 typedef enum SurfaceTiling { 1419 ARRAY_LINEAR = 0x0, 1420 ARRAY_TILED = 0x1, 1421 } SurfaceTiling; 1422 typedef enum SurfaceArray { 1423 ARRAY_1D = 0x0, 1424 ARRAY_2D = 0x1, 1425 ARRAY_3D = 0x2, 1426 ARRAY_3D_SLICE = 0x3, 1427 } SurfaceArray; 1428 typedef enum ColorArray { 1429 ARRAY_2D_ALT_COLOR = 0x0, 1430 ARRAY_2D_COLOR = 0x1, 1431 ARRAY_3D_SLICE_COLOR = 0x3, 1432 } ColorArray; 1433 typedef enum DepthArray { 1434 ARRAY_2D_ALT_DEPTH = 0x0, 1435 ARRAY_2D_DEPTH = 0x1, 1436 } DepthArray; 1437 typedef enum ENUM_NUM_SIMD_PER_CU { 1438 NUM_SIMD_PER_CU = 0x4, 1439 } ENUM_NUM_SIMD_PER_CU; 1440 typedef enum MEM_PWR_FORCE_CTRL { 1441 NO_FORCE_REQUEST = 0x0, 1442 FORCE_LIGHT_SLEEP_REQUEST = 0x1, 1443 FORCE_DEEP_SLEEP_REQUEST = 0x2, 1444 FORCE_SHUT_DOWN_REQUEST = 0x3, 1445 } MEM_PWR_FORCE_CTRL; 1446 typedef enum MEM_PWR_FORCE_CTRL2 { 1447 NO_FORCE_REQ = 0x0, 1448 FORCE_LIGHT_SLEEP_REQ = 0x1, 1449 } MEM_PWR_FORCE_CTRL2; 1450 typedef enum MEM_PWR_DIS_CTRL { 1451 ENABLE_MEM_PWR_CTRL = 0x0, 1452 DISABLE_MEM_PWR_CTRL = 0x1, 1453 } MEM_PWR_DIS_CTRL; 1454 typedef enum MEM_PWR_SEL_CTRL { 1455 DYNAMIC_SHUT_DOWN_ENABLE = 0x0, 1456 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, 1457 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, 1458 } MEM_PWR_SEL_CTRL; 1459 typedef enum MEM_PWR_SEL_CTRL2 { 1460 DYNAMIC_DEEP_SLEEP_EN = 0x0, 1461 DYNAMIC_LIGHT_SLEEP_EN = 0x1, 1462 } MEM_PWR_SEL_CTRL2; 1463 1464 #endif /* OSS_3_0_1_ENUM_H */ 1465