1 /* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21 #ifndef _osssys_4_0_1_SH_MASK_HEADER 22 #define _osssys_4_0_1_SH_MASK_HEADER 23 24 25 // addressBlock: osssys_osssysdec 26 //IH_VMID_0_LUT 27 #define IH_VMID_0_LUT__PASID__SHIFT 0x0 28 #define IH_VMID_0_LUT__PASID_MASK 0x0000FFFFL 29 //IH_VMID_1_LUT 30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0 31 #define IH_VMID_1_LUT__PASID_MASK 0x0000FFFFL 32 //IH_VMID_2_LUT 33 #define IH_VMID_2_LUT__PASID__SHIFT 0x0 34 #define IH_VMID_2_LUT__PASID_MASK 0x0000FFFFL 35 //IH_VMID_3_LUT 36 #define IH_VMID_3_LUT__PASID__SHIFT 0x0 37 #define IH_VMID_3_LUT__PASID_MASK 0x0000FFFFL 38 //IH_VMID_4_LUT 39 #define IH_VMID_4_LUT__PASID__SHIFT 0x0 40 #define IH_VMID_4_LUT__PASID_MASK 0x0000FFFFL 41 //IH_VMID_5_LUT 42 #define IH_VMID_5_LUT__PASID__SHIFT 0x0 43 #define IH_VMID_5_LUT__PASID_MASK 0x0000FFFFL 44 //IH_VMID_6_LUT 45 #define IH_VMID_6_LUT__PASID__SHIFT 0x0 46 #define IH_VMID_6_LUT__PASID_MASK 0x0000FFFFL 47 //IH_VMID_7_LUT 48 #define IH_VMID_7_LUT__PASID__SHIFT 0x0 49 #define IH_VMID_7_LUT__PASID_MASK 0x0000FFFFL 50 //IH_VMID_8_LUT 51 #define IH_VMID_8_LUT__PASID__SHIFT 0x0 52 #define IH_VMID_8_LUT__PASID_MASK 0x0000FFFFL 53 //IH_VMID_9_LUT 54 #define IH_VMID_9_LUT__PASID__SHIFT 0x0 55 #define IH_VMID_9_LUT__PASID_MASK 0x0000FFFFL 56 //IH_VMID_10_LUT 57 #define IH_VMID_10_LUT__PASID__SHIFT 0x0 58 #define IH_VMID_10_LUT__PASID_MASK 0x0000FFFFL 59 //IH_VMID_11_LUT 60 #define IH_VMID_11_LUT__PASID__SHIFT 0x0 61 #define IH_VMID_11_LUT__PASID_MASK 0x0000FFFFL 62 //IH_VMID_12_LUT 63 #define IH_VMID_12_LUT__PASID__SHIFT 0x0 64 #define IH_VMID_12_LUT__PASID_MASK 0x0000FFFFL 65 //IH_VMID_13_LUT 66 #define IH_VMID_13_LUT__PASID__SHIFT 0x0 67 #define IH_VMID_13_LUT__PASID_MASK 0x0000FFFFL 68 //IH_VMID_14_LUT 69 #define IH_VMID_14_LUT__PASID__SHIFT 0x0 70 #define IH_VMID_14_LUT__PASID_MASK 0x0000FFFFL 71 //IH_VMID_15_LUT 72 #define IH_VMID_15_LUT__PASID__SHIFT 0x0 73 #define IH_VMID_15_LUT__PASID_MASK 0x0000FFFFL 74 //IH_VMID_0_LUT_MM 75 #define IH_VMID_0_LUT_MM__PASID__SHIFT 0x0 76 #define IH_VMID_0_LUT_MM__PASID_MASK 0x0000FFFFL 77 //IH_VMID_1_LUT_MM 78 #define IH_VMID_1_LUT_MM__PASID__SHIFT 0x0 79 #define IH_VMID_1_LUT_MM__PASID_MASK 0x0000FFFFL 80 //IH_VMID_2_LUT_MM 81 #define IH_VMID_2_LUT_MM__PASID__SHIFT 0x0 82 #define IH_VMID_2_LUT_MM__PASID_MASK 0x0000FFFFL 83 //IH_VMID_3_LUT_MM 84 #define IH_VMID_3_LUT_MM__PASID__SHIFT 0x0 85 #define IH_VMID_3_LUT_MM__PASID_MASK 0x0000FFFFL 86 //IH_VMID_4_LUT_MM 87 #define IH_VMID_4_LUT_MM__PASID__SHIFT 0x0 88 #define IH_VMID_4_LUT_MM__PASID_MASK 0x0000FFFFL 89 //IH_VMID_5_LUT_MM 90 #define IH_VMID_5_LUT_MM__PASID__SHIFT 0x0 91 #define IH_VMID_5_LUT_MM__PASID_MASK 0x0000FFFFL 92 //IH_VMID_6_LUT_MM 93 #define IH_VMID_6_LUT_MM__PASID__SHIFT 0x0 94 #define IH_VMID_6_LUT_MM__PASID_MASK 0x0000FFFFL 95 //IH_VMID_7_LUT_MM 96 #define IH_VMID_7_LUT_MM__PASID__SHIFT 0x0 97 #define IH_VMID_7_LUT_MM__PASID_MASK 0x0000FFFFL 98 //IH_VMID_8_LUT_MM 99 #define IH_VMID_8_LUT_MM__PASID__SHIFT 0x0 100 #define IH_VMID_8_LUT_MM__PASID_MASK 0x0000FFFFL 101 //IH_VMID_9_LUT_MM 102 #define IH_VMID_9_LUT_MM__PASID__SHIFT 0x0 103 #define IH_VMID_9_LUT_MM__PASID_MASK 0x0000FFFFL 104 //IH_VMID_10_LUT_MM 105 #define IH_VMID_10_LUT_MM__PASID__SHIFT 0x0 106 #define IH_VMID_10_LUT_MM__PASID_MASK 0x0000FFFFL 107 //IH_VMID_11_LUT_MM 108 #define IH_VMID_11_LUT_MM__PASID__SHIFT 0x0 109 #define IH_VMID_11_LUT_MM__PASID_MASK 0x0000FFFFL 110 //IH_VMID_12_LUT_MM 111 #define IH_VMID_12_LUT_MM__PASID__SHIFT 0x0 112 #define IH_VMID_12_LUT_MM__PASID_MASK 0x0000FFFFL 113 //IH_VMID_13_LUT_MM 114 #define IH_VMID_13_LUT_MM__PASID__SHIFT 0x0 115 #define IH_VMID_13_LUT_MM__PASID_MASK 0x0000FFFFL 116 //IH_VMID_14_LUT_MM 117 #define IH_VMID_14_LUT_MM__PASID__SHIFT 0x0 118 #define IH_VMID_14_LUT_MM__PASID_MASK 0x0000FFFFL 119 //IH_VMID_15_LUT_MM 120 #define IH_VMID_15_LUT_MM__PASID__SHIFT 0x0 121 #define IH_VMID_15_LUT_MM__PASID_MASK 0x0000FFFFL 122 //IH_COOKIE_0 123 #define IH_COOKIE_0__CLIENT_ID__SHIFT 0x0 124 #define IH_COOKIE_0__SOURCE_ID__SHIFT 0x8 125 #define IH_COOKIE_0__RING_ID__SHIFT 0x10 126 #define IH_COOKIE_0__VM_ID__SHIFT 0x18 127 #define IH_COOKIE_0__RESERVED__SHIFT 0x1c 128 #define IH_COOKIE_0__VMID_TYPE__SHIFT 0x1f 129 #define IH_COOKIE_0__CLIENT_ID_MASK 0x000000FFL 130 #define IH_COOKIE_0__SOURCE_ID_MASK 0x0000FF00L 131 #define IH_COOKIE_0__RING_ID_MASK 0x00FF0000L 132 #define IH_COOKIE_0__VM_ID_MASK 0x0F000000L 133 #define IH_COOKIE_0__RESERVED_MASK 0x70000000L 134 #define IH_COOKIE_0__VMID_TYPE_MASK 0x80000000L 135 //IH_COOKIE_1 136 #define IH_COOKIE_1__TIMESTAMP_31_0__SHIFT 0x0 137 #define IH_COOKIE_1__TIMESTAMP_31_0_MASK 0xFFFFFFFFL 138 //IH_COOKIE_2 139 #define IH_COOKIE_2__TIMESTAMP_47_32__SHIFT 0x0 140 #define IH_COOKIE_2__RESERVED__SHIFT 0x10 141 #define IH_COOKIE_2__TIMESTAMP_SRC__SHIFT 0x1f 142 #define IH_COOKIE_2__TIMESTAMP_47_32_MASK 0x0000FFFFL 143 #define IH_COOKIE_2__RESERVED_MASK 0x7FFF0000L 144 #define IH_COOKIE_2__TIMESTAMP_SRC_MASK 0x80000000L 145 //IH_COOKIE_3 146 #define IH_COOKIE_3__PAS_ID__SHIFT 0x0 147 #define IH_COOKIE_3__RESERVED__SHIFT 0x10 148 #define IH_COOKIE_3__PASID_SRC__SHIFT 0x1f 149 #define IH_COOKIE_3__PAS_ID_MASK 0x0000FFFFL 150 #define IH_COOKIE_3__RESERVED_MASK 0x7FFF0000L 151 #define IH_COOKIE_3__PASID_SRC_MASK 0x80000000L 152 //IH_COOKIE_4 153 #define IH_COOKIE_4__CONTEXT_ID_31_0__SHIFT 0x0 154 #define IH_COOKIE_4__CONTEXT_ID_31_0_MASK 0xFFFFFFFFL 155 //IH_COOKIE_5 156 #define IH_COOKIE_5__CONTEXT_ID_63_32__SHIFT 0x0 157 #define IH_COOKIE_5__CONTEXT_ID_63_32_MASK 0xFFFFFFFFL 158 //IH_COOKIE_6 159 #define IH_COOKIE_6__CONTEXT_ID_95_64__SHIFT 0x0 160 #define IH_COOKIE_6__CONTEXT_ID_95_64_MASK 0xFFFFFFFFL 161 //IH_COOKIE_7 162 #define IH_COOKIE_7__CONTEXT_ID_128_96__SHIFT 0x0 163 #define IH_COOKIE_7__CONTEXT_ID_128_96_MASK 0xFFFFFFFFL 164 //IH_REGISTER_LAST_PART0 165 #define IH_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 166 #define IH_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 167 //SEM_REQ_INPUT_0 168 #define SEM_REQ_INPUT_0__DATA__SHIFT 0x0 169 #define SEM_REQ_INPUT_0__DATA_MASK 0xFFFFFFFFL 170 //SEM_REQ_INPUT_1 171 #define SEM_REQ_INPUT_1__DATA__SHIFT 0x0 172 #define SEM_REQ_INPUT_1__DATA_MASK 0xFFFFFFFFL 173 //SEM_REQ_INPUT_2 174 #define SEM_REQ_INPUT_2__DATA__SHIFT 0x0 175 #define SEM_REQ_INPUT_2__DATA_MASK 0xFFFFFFFFL 176 //SEM_REQ_INPUT_3 177 #define SEM_REQ_INPUT_3__DATA__SHIFT 0x0 178 #define SEM_REQ_INPUT_3__DATA_MASK 0xFFFFFFFFL 179 //SEM_REGISTER_LAST_PART0 180 #define SEM_REGISTER_LAST_PART0__RESERVED__SHIFT 0x0 181 #define SEM_REGISTER_LAST_PART0__RESERVED_MASK 0xFFFFFFFFL 182 //IH_RB_CNTL 183 #define IH_RB_CNTL__RB_ENABLE__SHIFT 0x0 184 #define IH_RB_CNTL__RB_SIZE__SHIFT 0x1 185 #define IH_RB_CNTL__RB_GPU_TS_ENABLE__SHIFT 0x7 186 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 187 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 188 #define IH_RB_CNTL__FULL_DRAIN_CLEAR__SHIFT 0xa 189 #define IH_RB_CNTL__PAGE_RB_CLEAR__SHIFT 0xb 190 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD__SHIFT 0xc 191 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 192 #define IH_RB_CNTL__ENABLE_INTR__SHIFT 0x11 193 #define IH_RB_CNTL__MC_SWAP__SHIFT 0x12 194 #define IH_RB_CNTL__MC_SNOOP__SHIFT 0x14 195 #define IH_RB_CNTL__RPTR_REARM__SHIFT 0x15 196 #define IH_RB_CNTL__MC_RO__SHIFT 0x16 197 #define IH_RB_CNTL__MC_VMID__SHIFT 0x18 198 #define IH_RB_CNTL__MC_SPACE__SHIFT 0x1c 199 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 200 #define IH_RB_CNTL__RB_ENABLE_MASK 0x00000001L 201 #define IH_RB_CNTL__RB_SIZE_MASK 0x0000003EL 202 #define IH_RB_CNTL__RB_GPU_TS_ENABLE_MASK 0x00000080L 203 #define IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK 0x00000100L 204 #define IH_RB_CNTL__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 205 #define IH_RB_CNTL__FULL_DRAIN_CLEAR_MASK 0x00000400L 206 #define IH_RB_CNTL__PAGE_RB_CLEAR_MASK 0x00000800L 207 #define IH_RB_CNTL__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 208 #define IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 209 #define IH_RB_CNTL__ENABLE_INTR_MASK 0x00020000L 210 #define IH_RB_CNTL__MC_SWAP_MASK 0x000C0000L 211 #define IH_RB_CNTL__MC_SNOOP_MASK 0x00100000L 212 #define IH_RB_CNTL__RPTR_REARM_MASK 0x00200000L 213 #define IH_RB_CNTL__MC_RO_MASK 0x00400000L 214 #define IH_RB_CNTL__MC_VMID_MASK 0x0F000000L 215 #define IH_RB_CNTL__MC_SPACE_MASK 0x70000000L 216 #define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 217 //IH_RB_BASE 218 #define IH_RB_BASE__ADDR__SHIFT 0x0 219 #define IH_RB_BASE__ADDR_MASK 0xFFFFFFFFL 220 //IH_RB_BASE_HI 221 #define IH_RB_BASE_HI__ADDR__SHIFT 0x0 222 #define IH_RB_BASE_HI__ADDR_MASK 0x000000FFL 223 //IH_RB_RPTR 224 #define IH_RB_RPTR__OFFSET__SHIFT 0x2 225 #define IH_RB_RPTR__OFFSET_MASK 0x0003FFFCL 226 //IH_RB_WPTR 227 #define IH_RB_WPTR__RB_OVERFLOW__SHIFT 0x0 228 #define IH_RB_WPTR__OFFSET__SHIFT 0x2 229 #define IH_RB_WPTR__RB_LEFT_NONE__SHIFT 0x12 230 #define IH_RB_WPTR__RB_MAY_OVERFLOW__SHIFT 0x13 231 #define IH_RB_WPTR__RB_OVERFLOW_MASK 0x00000001L 232 #define IH_RB_WPTR__OFFSET_MASK 0x0003FFFCL 233 #define IH_RB_WPTR__RB_LEFT_NONE_MASK 0x00040000L 234 #define IH_RB_WPTR__RB_MAY_OVERFLOW_MASK 0x00080000L 235 //IH_RB_WPTR_ADDR_HI 236 #define IH_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 237 #define IH_RB_WPTR_ADDR_HI__ADDR_MASK 0x0000FFFFL 238 //IH_RB_WPTR_ADDR_LO 239 #define IH_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 240 #define IH_RB_WPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 241 //IH_DOORBELL_RPTR 242 #define IH_DOORBELL_RPTR__OFFSET__SHIFT 0x0 243 #define IH_DOORBELL_RPTR__ENABLE__SHIFT 0x1c 244 #define IH_DOORBELL_RPTR__OFFSET_MASK 0x03FFFFFFL 245 #define IH_DOORBELL_RPTR__ENABLE_MASK 0x10000000L 246 //IH_RB_CNTL_RING1 247 #define IH_RB_CNTL_RING1__RB_ENABLE__SHIFT 0x0 248 #define IH_RB_CNTL_RING1__RB_SIZE__SHIFT 0x1 249 #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE__SHIFT 0x7 250 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 251 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR__SHIFT 0xa 252 #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR__SHIFT 0xb 253 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD__SHIFT 0xc 254 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 255 #define IH_RB_CNTL_RING1__MC_SWAP__SHIFT 0x12 256 #define IH_RB_CNTL_RING1__MC_SNOOP__SHIFT 0x14 257 #define IH_RB_CNTL_RING1__MC_RO__SHIFT 0x16 258 #define IH_RB_CNTL_RING1__MC_VMID__SHIFT 0x18 259 #define IH_RB_CNTL_RING1__MC_SPACE__SHIFT 0x1c 260 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 261 #define IH_RB_CNTL_RING1__RB_ENABLE_MASK 0x00000001L 262 #define IH_RB_CNTL_RING1__RB_SIZE_MASK 0x0000003EL 263 #define IH_RB_CNTL_RING1__RB_GPU_TS_ENABLE_MASK 0x00000080L 264 #define IH_RB_CNTL_RING1__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 265 #define IH_RB_CNTL_RING1__FULL_DRAIN_CLEAR_MASK 0x00000400L 266 #define IH_RB_CNTL_RING1__PAGE_RB_CLEAR_MASK 0x00000800L 267 #define IH_RB_CNTL_RING1__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 268 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 269 #define IH_RB_CNTL_RING1__MC_SWAP_MASK 0x000C0000L 270 #define IH_RB_CNTL_RING1__MC_SNOOP_MASK 0x00100000L 271 #define IH_RB_CNTL_RING1__MC_RO_MASK 0x00400000L 272 #define IH_RB_CNTL_RING1__MC_VMID_MASK 0x0F000000L 273 #define IH_RB_CNTL_RING1__MC_SPACE_MASK 0x70000000L 274 #define IH_RB_CNTL_RING1__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 275 //IH_RB_BASE_RING1 276 #define IH_RB_BASE_RING1__ADDR__SHIFT 0x0 277 #define IH_RB_BASE_RING1__ADDR_MASK 0xFFFFFFFFL 278 //IH_RB_BASE_HI_RING1 279 #define IH_RB_BASE_HI_RING1__ADDR__SHIFT 0x0 280 #define IH_RB_BASE_HI_RING1__ADDR_MASK 0x000000FFL 281 //IH_RB_RPTR_RING1 282 #define IH_RB_RPTR_RING1__OFFSET__SHIFT 0x2 283 #define IH_RB_RPTR_RING1__OFFSET_MASK 0x0003FFFCL 284 //IH_RB_WPTR_RING1 285 #define IH_RB_WPTR_RING1__RB_OVERFLOW__SHIFT 0x0 286 #define IH_RB_WPTR_RING1__OFFSET__SHIFT 0x2 287 #define IH_RB_WPTR_RING1__RB_LEFT_NONE__SHIFT 0x12 288 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW__SHIFT 0x13 289 #define IH_RB_WPTR_RING1__RB_OVERFLOW_MASK 0x00000001L 290 #define IH_RB_WPTR_RING1__OFFSET_MASK 0x0003FFFCL 291 #define IH_RB_WPTR_RING1__RB_LEFT_NONE_MASK 0x00040000L 292 #define IH_RB_WPTR_RING1__RB_MAY_OVERFLOW_MASK 0x00080000L 293 //IH_DOORBELL_RPTR_RING1 294 #define IH_DOORBELL_RPTR_RING1__OFFSET__SHIFT 0x0 295 #define IH_DOORBELL_RPTR_RING1__ENABLE__SHIFT 0x1c 296 #define IH_DOORBELL_RPTR_RING1__OFFSET_MASK 0x03FFFFFFL 297 #define IH_DOORBELL_RPTR_RING1__ENABLE_MASK 0x10000000L 298 //IH_RB_CNTL_RING2 299 #define IH_RB_CNTL_RING2__RB_ENABLE__SHIFT 0x0 300 #define IH_RB_CNTL_RING2__RB_SIZE__SHIFT 0x1 301 #define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE__SHIFT 0x7 302 #define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE__SHIFT 0x9 303 #define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR__SHIFT 0xa 304 #define IH_RB_CNTL_RING2__PAGE_RB_CLEAR__SHIFT 0xb 305 #define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD__SHIFT 0xc 306 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE__SHIFT 0x10 307 #define IH_RB_CNTL_RING2__MC_SWAP__SHIFT 0x12 308 #define IH_RB_CNTL_RING2__MC_SNOOP__SHIFT 0x14 309 #define IH_RB_CNTL_RING2__MC_RO__SHIFT 0x16 310 #define IH_RB_CNTL_RING2__MC_VMID__SHIFT 0x18 311 #define IH_RB_CNTL_RING2__MC_SPACE__SHIFT 0x1c 312 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 313 #define IH_RB_CNTL_RING2__RB_ENABLE_MASK 0x00000001L 314 #define IH_RB_CNTL_RING2__RB_SIZE_MASK 0x0000003EL 315 #define IH_RB_CNTL_RING2__RB_GPU_TS_ENABLE_MASK 0x00000080L 316 #define IH_RB_CNTL_RING2__RB_FULL_DRAIN_ENABLE_MASK 0x00000200L 317 #define IH_RB_CNTL_RING2__FULL_DRAIN_CLEAR_MASK 0x00000400L 318 #define IH_RB_CNTL_RING2__PAGE_RB_CLEAR_MASK 0x00000800L 319 #define IH_RB_CNTL_RING2__RB_USED_INT_THRESHOLD_MASK 0x0000F000L 320 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_ENABLE_MASK 0x00010000L 321 #define IH_RB_CNTL_RING2__MC_SWAP_MASK 0x000C0000L 322 #define IH_RB_CNTL_RING2__MC_SNOOP_MASK 0x00100000L 323 #define IH_RB_CNTL_RING2__MC_RO_MASK 0x00400000L 324 #define IH_RB_CNTL_RING2__MC_VMID_MASK 0x0F000000L 325 #define IH_RB_CNTL_RING2__MC_SPACE_MASK 0x70000000L 326 #define IH_RB_CNTL_RING2__WPTR_OVERFLOW_CLEAR_MASK 0x80000000L 327 //IH_RB_BASE_RING2 328 #define IH_RB_BASE_RING2__ADDR__SHIFT 0x0 329 #define IH_RB_BASE_RING2__ADDR_MASK 0xFFFFFFFFL 330 //IH_RB_BASE_HI_RING2 331 #define IH_RB_BASE_HI_RING2__ADDR__SHIFT 0x0 332 #define IH_RB_BASE_HI_RING2__ADDR_MASK 0x000000FFL 333 //IH_RB_RPTR_RING2 334 #define IH_RB_RPTR_RING2__OFFSET__SHIFT 0x2 335 #define IH_RB_RPTR_RING2__OFFSET_MASK 0x0003FFFCL 336 //IH_RB_WPTR_RING2 337 #define IH_RB_WPTR_RING2__RB_OVERFLOW__SHIFT 0x0 338 #define IH_RB_WPTR_RING2__OFFSET__SHIFT 0x2 339 #define IH_RB_WPTR_RING2__RB_LEFT_NONE__SHIFT 0x12 340 #define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW__SHIFT 0x13 341 #define IH_RB_WPTR_RING2__RB_OVERFLOW_MASK 0x00000001L 342 #define IH_RB_WPTR_RING2__OFFSET_MASK 0x0003FFFCL 343 #define IH_RB_WPTR_RING2__RB_LEFT_NONE_MASK 0x00040000L 344 #define IH_RB_WPTR_RING2__RB_MAY_OVERFLOW_MASK 0x00080000L 345 //IH_DOORBELL_RPTR_RING2 346 #define IH_DOORBELL_RPTR_RING2__OFFSET__SHIFT 0x0 347 #define IH_DOORBELL_RPTR_RING2__ENABLE__SHIFT 0x1c 348 #define IH_DOORBELL_RPTR_RING2__OFFSET_MASK 0x03FFFFFFL 349 #define IH_DOORBELL_RPTR_RING2__ENABLE_MASK 0x10000000L 350 //IH_VERSION 351 #define IH_VERSION__MINVER__SHIFT 0x0 352 #define IH_VERSION__MAJVER__SHIFT 0x8 353 #define IH_VERSION__REV__SHIFT 0x10 354 #define IH_VERSION__MINVER_MASK 0x0000007FL 355 #define IH_VERSION__MAJVER_MASK 0x00007F00L 356 #define IH_VERSION__REV_MASK 0x003F0000L 357 //IH_CNTL 358 #define IH_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x0 359 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL__SHIFT 0x6 360 #define IH_CNTL__IH_FIFO_HIGHWATER__SHIFT 0x8 361 #define IH_CNTL__MC_WR_CLEAN_CNT__SHIFT 0x14 362 #define IH_CNTL__WPTR_WRITEBACK_TIMER_MASK 0x0000001FL 363 #define IH_CNTL__IH_IDLE_HYSTERESIS_CNTL_MASK 0x000000C0L 364 #define IH_CNTL__IH_FIFO_HIGHWATER_MASK 0x00007F00L 365 #define IH_CNTL__MC_WR_CLEAN_CNT_MASK 0x01F00000L 366 //IH_CNTL2 367 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT__SHIFT 0x0 368 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE__SHIFT 0x8 369 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT_MASK 0x0000001FL 370 #define IH_CNTL2__SELF_IV_FORCE_WPTR_UPDATE_ENABLE_MASK 0x00000100L 371 //IH_STATUS 372 #define IH_STATUS__IDLE__SHIFT 0x0 373 #define IH_STATUS__INPUT_IDLE__SHIFT 0x1 374 #define IH_STATUS__BUFFER_IDLE__SHIFT 0x2 375 #define IH_STATUS__RB_FULL__SHIFT 0x3 376 #define IH_STATUS__RB_FULL_DRAIN__SHIFT 0x4 377 #define IH_STATUS__RB_OVERFLOW__SHIFT 0x5 378 #define IH_STATUS__MC_WR_IDLE__SHIFT 0x6 379 #define IH_STATUS__MC_WR_STALL__SHIFT 0x7 380 #define IH_STATUS__MC_WR_CLEAN_PENDING__SHIFT 0x8 381 #define IH_STATUS__MC_WR_CLEAN_STALL__SHIFT 0x9 382 #define IH_STATUS__BIF_INTERRUPT_LINE__SHIFT 0xa 383 #define IH_STATUS__SWITCH_READY__SHIFT 0xb 384 #define IH_STATUS__RB1_FULL__SHIFT 0xc 385 #define IH_STATUS__RB1_FULL_DRAIN__SHIFT 0xd 386 #define IH_STATUS__RB1_OVERFLOW__SHIFT 0xe 387 #define IH_STATUS__RB2_FULL__SHIFT 0xf 388 #define IH_STATUS__RB2_FULL_DRAIN__SHIFT 0x10 389 #define IH_STATUS__RB2_OVERFLOW__SHIFT 0x11 390 #define IH_STATUS__SELF_INT_GEN_IDLE__SHIFT 0x12 391 #define IH_STATUS__IDLE_MASK 0x00000001L 392 #define IH_STATUS__INPUT_IDLE_MASK 0x00000002L 393 #define IH_STATUS__BUFFER_IDLE_MASK 0x00000004L 394 #define IH_STATUS__RB_FULL_MASK 0x00000008L 395 #define IH_STATUS__RB_FULL_DRAIN_MASK 0x00000010L 396 #define IH_STATUS__RB_OVERFLOW_MASK 0x00000020L 397 #define IH_STATUS__MC_WR_IDLE_MASK 0x00000040L 398 #define IH_STATUS__MC_WR_STALL_MASK 0x00000080L 399 #define IH_STATUS__MC_WR_CLEAN_PENDING_MASK 0x00000100L 400 #define IH_STATUS__MC_WR_CLEAN_STALL_MASK 0x00000200L 401 #define IH_STATUS__BIF_INTERRUPT_LINE_MASK 0x00000400L 402 #define IH_STATUS__SWITCH_READY_MASK 0x00000800L 403 #define IH_STATUS__RB1_FULL_MASK 0x00001000L 404 #define IH_STATUS__RB1_FULL_DRAIN_MASK 0x00002000L 405 #define IH_STATUS__RB1_OVERFLOW_MASK 0x00004000L 406 #define IH_STATUS__RB2_FULL_MASK 0x00008000L 407 #define IH_STATUS__RB2_FULL_DRAIN_MASK 0x00010000L 408 #define IH_STATUS__RB2_OVERFLOW_MASK 0x00020000L 409 #define IH_STATUS__SELF_INT_GEN_IDLE_MASK 0x00040000L 410 //IH_PERFMON_CNTL 411 #define IH_PERFMON_CNTL__ENABLE0__SHIFT 0x0 412 #define IH_PERFMON_CNTL__CLEAR0__SHIFT 0x1 413 #define IH_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 414 #define IH_PERFMON_CNTL__ENABLE1__SHIFT 0x10 415 #define IH_PERFMON_CNTL__CLEAR1__SHIFT 0x11 416 #define IH_PERFMON_CNTL__PERF_SEL1__SHIFT 0x12 417 #define IH_PERFMON_CNTL__ENABLE0_MASK 0x00000001L 418 #define IH_PERFMON_CNTL__CLEAR0_MASK 0x00000002L 419 #define IH_PERFMON_CNTL__PERF_SEL0_MASK 0x000007FCL 420 #define IH_PERFMON_CNTL__ENABLE1_MASK 0x00010000L 421 #define IH_PERFMON_CNTL__CLEAR1_MASK 0x00020000L 422 #define IH_PERFMON_CNTL__PERF_SEL1_MASK 0x07FC0000L 423 //IH_PERFCOUNTER0_RESULT 424 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 425 #define IH_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 426 //IH_PERFCOUNTER1_RESULT 427 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 428 #define IH_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 429 //IH_DSM_MATCH_VALUE_BIT_31_0 430 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE__SHIFT 0x0 431 #define IH_DSM_MATCH_VALUE_BIT_31_0__VALUE_MASK 0xFFFFFFFFL 432 //IH_DSM_MATCH_VALUE_BIT_63_32 433 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE__SHIFT 0x0 434 #define IH_DSM_MATCH_VALUE_BIT_63_32__VALUE_MASK 0xFFFFFFFFL 435 //IH_DSM_MATCH_VALUE_BIT_95_64 436 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE__SHIFT 0x0 437 #define IH_DSM_MATCH_VALUE_BIT_95_64__VALUE_MASK 0xFFFFFFFFL 438 //IH_DSM_MATCH_FIELD_CONTROL 439 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN__SHIFT 0x0 440 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN__SHIFT 0x1 441 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN__SHIFT 0x2 442 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN__SHIFT 0x3 443 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN__SHIFT 0x4 444 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN__SHIFT 0x5 445 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN__SHIFT 0x6 446 #define IH_DSM_MATCH_FIELD_CONTROL__SRC_EN_MASK 0x00000001L 447 #define IH_DSM_MATCH_FIELD_CONTROL__FCNID_EN_MASK 0x00000002L 448 #define IH_DSM_MATCH_FIELD_CONTROL__TIMESTAMP_EN_MASK 0x00000004L 449 #define IH_DSM_MATCH_FIELD_CONTROL__RINGID_EN_MASK 0x00000008L 450 #define IH_DSM_MATCH_FIELD_CONTROL__VMID_EN_MASK 0x00000010L 451 #define IH_DSM_MATCH_FIELD_CONTROL__PASID_EN_MASK 0x00000020L 452 #define IH_DSM_MATCH_FIELD_CONTROL__CLIENT_ID_EN_MASK 0x00000040L 453 //IH_DSM_MATCH_DATA_CONTROL 454 #define IH_DSM_MATCH_DATA_CONTROL__VALUE__SHIFT 0x0 455 #define IH_DSM_MATCH_DATA_CONTROL__VALUE_MASK 0x0FFFFFFFL 456 //IH_DSM_MATCH_FCN_ID 457 #define IH_DSM_MATCH_FCN_ID__PF_VF__SHIFT 0x0 458 #define IH_DSM_MATCH_FCN_ID__VF_ID__SHIFT 0x1 459 #define IH_DSM_MATCH_FCN_ID__PF_VF_MASK 0x00000001L 460 #define IH_DSM_MATCH_FCN_ID__VF_ID_MASK 0x0000001EL 461 //IH_LIMIT_INT_RATE_CNTL 462 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE__SHIFT 0x0 463 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL__SHIFT 0x1 464 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD__SHIFT 0x5 465 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY__SHIFT 0x11 466 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT__SHIFT 0x15 467 #define IH_LIMIT_INT_RATE_CNTL__LIMIT_ENABLE_MASK 0x00000001L 468 #define IH_LIMIT_INT_RATE_CNTL__PERF_INTERVAL_MASK 0x0000001EL 469 #define IH_LIMIT_INT_RATE_CNTL__PERF_THRESHOLD_MASK 0x0000FFE0L 470 #define IH_LIMIT_INT_RATE_CNTL__RETURN_DELAY_MASK 0x001E0000L 471 #define IH_LIMIT_INT_RATE_CNTL__PERF_RESULT_MASK 0xFFE00000L 472 //IH_VF_RB_STATUS 473 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 474 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 475 #define IH_VF_RB_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 476 #define IH_VF_RB_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 477 //IH_VF_RB_STATUS2 478 #define IH_VF_RB_STATUS2__RB_FULL_VF__SHIFT 0x0 479 #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF__SHIFT 0x10 480 #define IH_VF_RB_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 481 #define IH_VF_RB_STATUS2__BIF_INTERRUPT_LINE_VF_MASK 0xFFFF0000L 482 //IH_VF_RB1_STATUS 483 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 484 #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 485 #define IH_VF_RB1_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 486 #define IH_VF_RB1_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 487 //IH_VF_RB1_STATUS2 488 #define IH_VF_RB1_STATUS2__RB_FULL_VF__SHIFT 0x0 489 #define IH_VF_RB1_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 490 //IH_VF_RB2_STATUS 491 #define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF__SHIFT 0x0 492 #define IH_VF_RB2_STATUS__RB_OVERFLOW_VF__SHIFT 0x10 493 #define IH_VF_RB2_STATUS__RB_FULL_DRAIN_VF_MASK 0x0000FFFFL 494 #define IH_VF_RB2_STATUS__RB_OVERFLOW_VF_MASK 0xFFFF0000L 495 //IH_VF_RB2_STATUS2 496 #define IH_VF_RB2_STATUS2__RB_FULL_VF__SHIFT 0x0 497 #define IH_VF_RB2_STATUS2__RB_FULL_VF_MASK 0x0000FFFFL 498 //IH_INT_FLOOD_CNTL 499 #define IH_INT_FLOOD_CNTL__HIGHWATER__SHIFT 0x0 500 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE__SHIFT 0x3 501 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS__SHIFT 0x4 502 #define IH_INT_FLOOD_CNTL__HIGHWATER_MASK 0x00000007L 503 #define IH_INT_FLOOD_CNTL__FLOOD_CNTL_ENABLE_MASK 0x00000008L 504 #define IH_INT_FLOOD_CNTL__CLEAR_INT_FLOOD_STATUS_MASK 0x00000010L 505 //IH_RB0_INT_FLOOD_STATUS 506 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 507 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 508 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 509 #define IH_RB0_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 510 //IH_RB1_INT_FLOOD_STATUS 511 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 512 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 513 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 514 #define IH_RB1_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 515 //IH_RB2_INT_FLOOD_STATUS 516 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF__SHIFT 0x0 517 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED__SHIFT 0x1f 518 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_VF_MASK 0x0000FFFFL 519 #define IH_RB2_INT_FLOOD_STATUS__RB_INT_DROPPED_MASK 0x80000000L 520 //IH_INT_FLOOD_STATUS 521 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT__SHIFT 0x0 522 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID__SHIFT 0x8 523 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID__SHIFT 0x10 524 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID__SHIFT 0x18 525 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF__SHIFT 0x1c 526 #define IH_INT_FLOOD_STATUS__INT_DROPPED__SHIFT 0x1e 527 #define IH_INT_FLOOD_STATUS__INT_DROP_CNT_MASK 0x000000FFL 528 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_CLIENT_ID_MASK 0x0000FF00L 529 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_SOURCE_ID_MASK 0x00FF0000L 530 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_ID_MASK 0x0F000000L 531 #define IH_INT_FLOOD_STATUS__FIRST_DROP_INT_VF_MASK 0x10000000L 532 #define IH_INT_FLOOD_STATUS__INT_DROPPED_MASK 0x40000000L 533 //IH_STORM_CLIENT_LIST_CNTL 534 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT__SHIFT 0x1 535 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT__SHIFT 0x2 536 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT__SHIFT 0x3 537 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT__SHIFT 0x4 538 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT__SHIFT 0x5 539 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT__SHIFT 0x6 540 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT__SHIFT 0x7 541 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT__SHIFT 0x8 542 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT__SHIFT 0x9 543 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT__SHIFT 0xa 544 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT__SHIFT 0xb 545 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT__SHIFT 0xc 546 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT__SHIFT 0xd 547 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT__SHIFT 0xe 548 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT__SHIFT 0xf 549 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT__SHIFT 0x10 550 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT__SHIFT 0x11 551 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT__SHIFT 0x12 552 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT__SHIFT 0x13 553 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT__SHIFT 0x14 554 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT__SHIFT 0x15 555 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT__SHIFT 0x16 556 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT__SHIFT 0x17 557 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT__SHIFT 0x18 558 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT__SHIFT 0x19 559 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT__SHIFT 0x1a 560 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT__SHIFT 0x1b 561 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT__SHIFT 0x1c 562 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT__SHIFT 0x1d 563 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT__SHIFT 0x1e 564 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT__SHIFT 0x1f 565 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT1_IS_STORM_CLIENT_MASK 0x00000002L 566 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT2_IS_STORM_CLIENT_MASK 0x00000004L 567 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT3_IS_STORM_CLIENT_MASK 0x00000008L 568 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT4_IS_STORM_CLIENT_MASK 0x00000010L 569 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT5_IS_STORM_CLIENT_MASK 0x00000020L 570 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT6_IS_STORM_CLIENT_MASK 0x00000040L 571 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT7_IS_STORM_CLIENT_MASK 0x00000080L 572 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT8_IS_STORM_CLIENT_MASK 0x00000100L 573 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT9_IS_STORM_CLIENT_MASK 0x00000200L 574 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT10_IS_STORM_CLIENT_MASK 0x00000400L 575 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT11_IS_STORM_CLIENT_MASK 0x00000800L 576 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT12_IS_STORM_CLIENT_MASK 0x00001000L 577 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT13_IS_STORM_CLIENT_MASK 0x00002000L 578 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT14_IS_STORM_CLIENT_MASK 0x00004000L 579 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT15_IS_STORM_CLIENT_MASK 0x00008000L 580 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT16_IS_STORM_CLIENT_MASK 0x00010000L 581 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT17_IS_STORM_CLIENT_MASK 0x00020000L 582 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT18_IS_STORM_CLIENT_MASK 0x00040000L 583 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT19_IS_STORM_CLIENT_MASK 0x00080000L 584 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT20_IS_STORM_CLIENT_MASK 0x00100000L 585 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT21_IS_STORM_CLIENT_MASK 0x00200000L 586 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT22_IS_STORM_CLIENT_MASK 0x00400000L 587 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT23_IS_STORM_CLIENT_MASK 0x00800000L 588 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT24_IS_STORM_CLIENT_MASK 0x01000000L 589 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT25_IS_STORM_CLIENT_MASK 0x02000000L 590 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT26_IS_STORM_CLIENT_MASK 0x04000000L 591 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT27_IS_STORM_CLIENT_MASK 0x08000000L 592 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT28_IS_STORM_CLIENT_MASK 0x10000000L 593 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT29_IS_STORM_CLIENT_MASK 0x20000000L 594 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT30_IS_STORM_CLIENT_MASK 0x40000000L 595 #define IH_STORM_CLIENT_LIST_CNTL__CLIENT31_IS_STORM_CLIENT_MASK 0x80000000L 596 //IH_CLK_CTRL 597 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE__SHIFT 0x1b 598 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE__SHIFT 0x1c 599 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE__SHIFT 0x1d 600 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE__SHIFT 0x1e 601 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE__SHIFT 0x1f 602 #define IH_CLK_CTRL__DBUS_MUX_CLK_SOFT_OVERRIDE_MASK 0x08000000L 603 #define IH_CLK_CTRL__OSSSYS_SHARE_CLK_SOFT_OVERRIDE_MASK 0x10000000L 604 #define IH_CLK_CTRL__LIMIT_SMN_CLK_SOFT_OVERRIDE_MASK 0x20000000L 605 #define IH_CLK_CTRL__DYN_CLK_SOFT_OVERRIDE_MASK 0x40000000L 606 #define IH_CLK_CTRL__REG_CLK_SOFT_OVERRIDE_MASK 0x80000000L 607 //IH_INT_FLAGS 608 #define IH_INT_FLAGS__CLIENT_0_FLAG__SHIFT 0x0 609 #define IH_INT_FLAGS__CLIENT_1_FLAG__SHIFT 0x1 610 #define IH_INT_FLAGS__CLIENT_2_FLAG__SHIFT 0x2 611 #define IH_INT_FLAGS__CLIENT_3_FLAG__SHIFT 0x3 612 #define IH_INT_FLAGS__CLIENT_4_FLAG__SHIFT 0x4 613 #define IH_INT_FLAGS__CLIENT_5_FLAG__SHIFT 0x5 614 #define IH_INT_FLAGS__CLIENT_6_FLAG__SHIFT 0x6 615 #define IH_INT_FLAGS__CLIENT_7_FLAG__SHIFT 0x7 616 #define IH_INT_FLAGS__CLIENT_8_FLAG__SHIFT 0x8 617 #define IH_INT_FLAGS__CLIENT_9_FLAG__SHIFT 0x9 618 #define IH_INT_FLAGS__CLIENT_10_FLAG__SHIFT 0xa 619 #define IH_INT_FLAGS__CLIENT_11_FLAG__SHIFT 0xb 620 #define IH_INT_FLAGS__CLIENT_12_FLAG__SHIFT 0xc 621 #define IH_INT_FLAGS__CLIENT_13_FLAG__SHIFT 0xd 622 #define IH_INT_FLAGS__CLIENT_14_FLAG__SHIFT 0xe 623 #define IH_INT_FLAGS__CLIENT_15_FLAG__SHIFT 0xf 624 #define IH_INT_FLAGS__CLIENT_16_FLAG__SHIFT 0x10 625 #define IH_INT_FLAGS__CLIENT_17_FLAG__SHIFT 0x11 626 #define IH_INT_FLAGS__CLIENT_18_FLAG__SHIFT 0x12 627 #define IH_INT_FLAGS__CLIENT_19_FLAG__SHIFT 0x13 628 #define IH_INT_FLAGS__CLIENT_20_FLAG__SHIFT 0x14 629 #define IH_INT_FLAGS__CLIENT_21_FLAG__SHIFT 0x15 630 #define IH_INT_FLAGS__CLIENT_22_FLAG__SHIFT 0x16 631 #define IH_INT_FLAGS__CLIENT_23_FLAG__SHIFT 0x17 632 #define IH_INT_FLAGS__CLIENT_24_FLAG__SHIFT 0x18 633 #define IH_INT_FLAGS__CLIENT_25_FLAG__SHIFT 0x19 634 #define IH_INT_FLAGS__CLIENT_26_FLAG__SHIFT 0x1a 635 #define IH_INT_FLAGS__CLIENT_27_FLAG__SHIFT 0x1b 636 #define IH_INT_FLAGS__CLIENT_28_FLAG__SHIFT 0x1c 637 #define IH_INT_FLAGS__CLIENT_29_FLAG__SHIFT 0x1d 638 #define IH_INT_FLAGS__CLIENT_30_FLAG__SHIFT 0x1e 639 #define IH_INT_FLAGS__CLIENT_31_FLAG__SHIFT 0x1f 640 #define IH_INT_FLAGS__CLIENT_0_FLAG_MASK 0x00000001L 641 #define IH_INT_FLAGS__CLIENT_1_FLAG_MASK 0x00000002L 642 #define IH_INT_FLAGS__CLIENT_2_FLAG_MASK 0x00000004L 643 #define IH_INT_FLAGS__CLIENT_3_FLAG_MASK 0x00000008L 644 #define IH_INT_FLAGS__CLIENT_4_FLAG_MASK 0x00000010L 645 #define IH_INT_FLAGS__CLIENT_5_FLAG_MASK 0x00000020L 646 #define IH_INT_FLAGS__CLIENT_6_FLAG_MASK 0x00000040L 647 #define IH_INT_FLAGS__CLIENT_7_FLAG_MASK 0x00000080L 648 #define IH_INT_FLAGS__CLIENT_8_FLAG_MASK 0x00000100L 649 #define IH_INT_FLAGS__CLIENT_9_FLAG_MASK 0x00000200L 650 #define IH_INT_FLAGS__CLIENT_10_FLAG_MASK 0x00000400L 651 #define IH_INT_FLAGS__CLIENT_11_FLAG_MASK 0x00000800L 652 #define IH_INT_FLAGS__CLIENT_12_FLAG_MASK 0x00001000L 653 #define IH_INT_FLAGS__CLIENT_13_FLAG_MASK 0x00002000L 654 #define IH_INT_FLAGS__CLIENT_14_FLAG_MASK 0x00004000L 655 #define IH_INT_FLAGS__CLIENT_15_FLAG_MASK 0x00008000L 656 #define IH_INT_FLAGS__CLIENT_16_FLAG_MASK 0x00010000L 657 #define IH_INT_FLAGS__CLIENT_17_FLAG_MASK 0x00020000L 658 #define IH_INT_FLAGS__CLIENT_18_FLAG_MASK 0x00040000L 659 #define IH_INT_FLAGS__CLIENT_19_FLAG_MASK 0x00080000L 660 #define IH_INT_FLAGS__CLIENT_20_FLAG_MASK 0x00100000L 661 #define IH_INT_FLAGS__CLIENT_21_FLAG_MASK 0x00200000L 662 #define IH_INT_FLAGS__CLIENT_22_FLAG_MASK 0x00400000L 663 #define IH_INT_FLAGS__CLIENT_23_FLAG_MASK 0x00800000L 664 #define IH_INT_FLAGS__CLIENT_24_FLAG_MASK 0x01000000L 665 #define IH_INT_FLAGS__CLIENT_25_FLAG_MASK 0x02000000L 666 #define IH_INT_FLAGS__CLIENT_26_FLAG_MASK 0x04000000L 667 #define IH_INT_FLAGS__CLIENT_27_FLAG_MASK 0x08000000L 668 #define IH_INT_FLAGS__CLIENT_28_FLAG_MASK 0x10000000L 669 #define IH_INT_FLAGS__CLIENT_29_FLAG_MASK 0x20000000L 670 #define IH_INT_FLAGS__CLIENT_30_FLAG_MASK 0x40000000L 671 #define IH_INT_FLAGS__CLIENT_31_FLAG_MASK 0x80000000L 672 //IH_LAST_INT_INFO0 673 #define IH_LAST_INT_INFO0__CLIENT_ID__SHIFT 0x0 674 #define IH_LAST_INT_INFO0__SOURCE_ID__SHIFT 0x8 675 #define IH_LAST_INT_INFO0__RING_ID__SHIFT 0x10 676 #define IH_LAST_INT_INFO0__VM_ID__SHIFT 0x18 677 #define IH_LAST_INT_INFO0__VMID_TYPE__SHIFT 0x1f 678 #define IH_LAST_INT_INFO0__CLIENT_ID_MASK 0x000000FFL 679 #define IH_LAST_INT_INFO0__SOURCE_ID_MASK 0x0000FF00L 680 #define IH_LAST_INT_INFO0__RING_ID_MASK 0x00FF0000L 681 #define IH_LAST_INT_INFO0__VM_ID_MASK 0x0F000000L 682 #define IH_LAST_INT_INFO0__VMID_TYPE_MASK 0x80000000L 683 //IH_LAST_INT_INFO1 684 #define IH_LAST_INT_INFO1__CONTEXT_ID__SHIFT 0x0 685 #define IH_LAST_INT_INFO1__CONTEXT_ID_MASK 0xFFFFFFFFL 686 //IH_LAST_INT_INFO2 687 #define IH_LAST_INT_INFO2__PAS_ID__SHIFT 0x0 688 #define IH_LAST_INT_INFO2__VF_ID__SHIFT 0x10 689 #define IH_LAST_INT_INFO2__VF__SHIFT 0x14 690 #define IH_LAST_INT_INFO2__PAS_ID_MASK 0x0000FFFFL 691 #define IH_LAST_INT_INFO2__VF_ID_MASK 0x000F0000L 692 #define IH_LAST_INT_INFO2__VF_MASK 0x00100000L 693 //IH_SCRATCH 694 #define IH_SCRATCH__DATA__SHIFT 0x0 695 #define IH_SCRATCH__DATA_MASK 0xFFFFFFFFL 696 //IH_CLIENT_CREDIT_ERROR 697 #define IH_CLIENT_CREDIT_ERROR__CLEAR__SHIFT 0x0 698 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR__SHIFT 0x1 699 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR__SHIFT 0x2 700 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR__SHIFT 0x3 701 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR__SHIFT 0x4 702 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR__SHIFT 0x5 703 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR__SHIFT 0x6 704 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR__SHIFT 0x7 705 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR__SHIFT 0x8 706 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR__SHIFT 0x9 707 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR__SHIFT 0xa 708 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR__SHIFT 0xb 709 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR__SHIFT 0xc 710 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR__SHIFT 0xd 711 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR__SHIFT 0xe 712 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR__SHIFT 0xf 713 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR__SHIFT 0x10 714 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR__SHIFT 0x11 715 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR__SHIFT 0x12 716 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR__SHIFT 0x13 717 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR__SHIFT 0x14 718 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR__SHIFT 0x15 719 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR__SHIFT 0x16 720 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR__SHIFT 0x17 721 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR__SHIFT 0x18 722 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR__SHIFT 0x19 723 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR__SHIFT 0x1a 724 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR__SHIFT 0x1b 725 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR__SHIFT 0x1c 726 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR__SHIFT 0x1d 727 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR__SHIFT 0x1e 728 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR__SHIFT 0x1f 729 #define IH_CLIENT_CREDIT_ERROR__CLEAR_MASK 0x00000001L 730 #define IH_CLIENT_CREDIT_ERROR__CLIENT_1_ERROR_MASK 0x00000002L 731 #define IH_CLIENT_CREDIT_ERROR__CLIENT_2_ERROR_MASK 0x00000004L 732 #define IH_CLIENT_CREDIT_ERROR__CLIENT_3_ERROR_MASK 0x00000008L 733 #define IH_CLIENT_CREDIT_ERROR__CLIENT_4_ERROR_MASK 0x00000010L 734 #define IH_CLIENT_CREDIT_ERROR__CLIENT_5_ERROR_MASK 0x00000020L 735 #define IH_CLIENT_CREDIT_ERROR__CLIENT_6_ERROR_MASK 0x00000040L 736 #define IH_CLIENT_CREDIT_ERROR__CLIENT_7_ERROR_MASK 0x00000080L 737 #define IH_CLIENT_CREDIT_ERROR__CLIENT_8_ERROR_MASK 0x00000100L 738 #define IH_CLIENT_CREDIT_ERROR__CLIENT_9_ERROR_MASK 0x00000200L 739 #define IH_CLIENT_CREDIT_ERROR__CLIENT_10_ERROR_MASK 0x00000400L 740 #define IH_CLIENT_CREDIT_ERROR__CLIENT_11_ERROR_MASK 0x00000800L 741 #define IH_CLIENT_CREDIT_ERROR__CLIENT_12_ERROR_MASK 0x00001000L 742 #define IH_CLIENT_CREDIT_ERROR__CLIENT_13_ERROR_MASK 0x00002000L 743 #define IH_CLIENT_CREDIT_ERROR__CLIENT_14_ERROR_MASK 0x00004000L 744 #define IH_CLIENT_CREDIT_ERROR__CLIENT_15_ERROR_MASK 0x00008000L 745 #define IH_CLIENT_CREDIT_ERROR__CLIENT_16_ERROR_MASK 0x00010000L 746 #define IH_CLIENT_CREDIT_ERROR__CLIENT_17_ERROR_MASK 0x00020000L 747 #define IH_CLIENT_CREDIT_ERROR__CLIENT_18_ERROR_MASK 0x00040000L 748 #define IH_CLIENT_CREDIT_ERROR__CLIENT_19_ERROR_MASK 0x00080000L 749 #define IH_CLIENT_CREDIT_ERROR__CLIENT_20_ERROR_MASK 0x00100000L 750 #define IH_CLIENT_CREDIT_ERROR__CLIENT_21_ERROR_MASK 0x00200000L 751 #define IH_CLIENT_CREDIT_ERROR__CLIENT_22_ERROR_MASK 0x00400000L 752 #define IH_CLIENT_CREDIT_ERROR__CLIENT_23_ERROR_MASK 0x00800000L 753 #define IH_CLIENT_CREDIT_ERROR__CLIENT_24_ERROR_MASK 0x01000000L 754 #define IH_CLIENT_CREDIT_ERROR__CLIENT_25_ERROR_MASK 0x02000000L 755 #define IH_CLIENT_CREDIT_ERROR__CLIENT_26_ERROR_MASK 0x04000000L 756 #define IH_CLIENT_CREDIT_ERROR__CLIENT_27_ERROR_MASK 0x08000000L 757 #define IH_CLIENT_CREDIT_ERROR__CLIENT_28_ERROR_MASK 0x10000000L 758 #define IH_CLIENT_CREDIT_ERROR__CLIENT_29_ERROR_MASK 0x20000000L 759 #define IH_CLIENT_CREDIT_ERROR__CLIENT_30_ERROR_MASK 0x40000000L 760 #define IH_CLIENT_CREDIT_ERROR__CLIENT_31_ERROR_MASK 0x80000000L 761 //IH_GPU_IOV_VIOLATION_LOG 762 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 763 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 764 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 765 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 766 #define IH_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 767 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 768 #define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 769 #define IH_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 770 #define IH_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 771 #define IH_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 772 #define IH_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 773 #define IH_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 774 #define IH_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 775 #define IH_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 776 //IH_COOKIE_REC_VIOLATION_LOG 777 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 778 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID__SHIFT 0x10 779 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 780 #define IH_COOKIE_REC_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 781 #define IH_COOKIE_REC_VIOLATION_LOG__CLIENT_ID_MASK 0x00FF0000L 782 #define IH_COOKIE_REC_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 783 //IH_CREDIT_STATUS 784 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED__SHIFT 0x1 785 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED__SHIFT 0x2 786 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED__SHIFT 0x3 787 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED__SHIFT 0x4 788 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED__SHIFT 0x5 789 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED__SHIFT 0x6 790 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED__SHIFT 0x7 791 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED__SHIFT 0x8 792 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED__SHIFT 0x9 793 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED__SHIFT 0xa 794 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED__SHIFT 0xb 795 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED__SHIFT 0xc 796 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED__SHIFT 0xd 797 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED__SHIFT 0xe 798 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED__SHIFT 0xf 799 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED__SHIFT 0x10 800 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED__SHIFT 0x11 801 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED__SHIFT 0x12 802 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED__SHIFT 0x13 803 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED__SHIFT 0x14 804 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED__SHIFT 0x15 805 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED__SHIFT 0x16 806 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED__SHIFT 0x17 807 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED__SHIFT 0x18 808 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED__SHIFT 0x19 809 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED__SHIFT 0x1a 810 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED__SHIFT 0x1b 811 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED__SHIFT 0x1c 812 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED__SHIFT 0x1d 813 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED__SHIFT 0x1e 814 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED__SHIFT 0x1f 815 #define IH_CREDIT_STATUS__CLIENT_1_CREDIT_RETURNED_MASK 0x00000002L 816 #define IH_CREDIT_STATUS__CLIENT_2_CREDIT_RETURNED_MASK 0x00000004L 817 #define IH_CREDIT_STATUS__CLIENT_3_CREDIT_RETURNED_MASK 0x00000008L 818 #define IH_CREDIT_STATUS__CLIENT_4_CREDIT_RETURNED_MASK 0x00000010L 819 #define IH_CREDIT_STATUS__CLIENT_5_CREDIT_RETURNED_MASK 0x00000020L 820 #define IH_CREDIT_STATUS__CLIENT_6_CREDIT_RETURNED_MASK 0x00000040L 821 #define IH_CREDIT_STATUS__CLIENT_7_CREDIT_RETURNED_MASK 0x00000080L 822 #define IH_CREDIT_STATUS__CLIENT_8_CREDIT_RETURNED_MASK 0x00000100L 823 #define IH_CREDIT_STATUS__CLIENT_9_CREDIT_RETURNED_MASK 0x00000200L 824 #define IH_CREDIT_STATUS__CLIENT_10_CREDIT_RETURNED_MASK 0x00000400L 825 #define IH_CREDIT_STATUS__CLIENT_11_CREDIT_RETURNED_MASK 0x00000800L 826 #define IH_CREDIT_STATUS__CLIENT_12_CREDIT_RETURNED_MASK 0x00001000L 827 #define IH_CREDIT_STATUS__CLIENT_13_CREDIT_RETURNED_MASK 0x00002000L 828 #define IH_CREDIT_STATUS__CLIENT_14_CREDIT_RETURNED_MASK 0x00004000L 829 #define IH_CREDIT_STATUS__CLIENT_15_CREDIT_RETURNED_MASK 0x00008000L 830 #define IH_CREDIT_STATUS__CLIENT_16_CREDIT_RETURNED_MASK 0x00010000L 831 #define IH_CREDIT_STATUS__CLIENT_17_CREDIT_RETURNED_MASK 0x00020000L 832 #define IH_CREDIT_STATUS__CLIENT_18_CREDIT_RETURNED_MASK 0x00040000L 833 #define IH_CREDIT_STATUS__CLIENT_19_CREDIT_RETURNED_MASK 0x00080000L 834 #define IH_CREDIT_STATUS__CLIENT_20_CREDIT_RETURNED_MASK 0x00100000L 835 #define IH_CREDIT_STATUS__CLIENT_21_CREDIT_RETURNED_MASK 0x00200000L 836 #define IH_CREDIT_STATUS__CLIENT_22_CREDIT_RETURNED_MASK 0x00400000L 837 #define IH_CREDIT_STATUS__CLIENT_23_CREDIT_RETURNED_MASK 0x00800000L 838 #define IH_CREDIT_STATUS__CLIENT_24_CREDIT_RETURNED_MASK 0x01000000L 839 #define IH_CREDIT_STATUS__CLIENT_25_CREDIT_RETURNED_MASK 0x02000000L 840 #define IH_CREDIT_STATUS__CLIENT_26_CREDIT_RETURNED_MASK 0x04000000L 841 #define IH_CREDIT_STATUS__CLIENT_27_CREDIT_RETURNED_MASK 0x08000000L 842 #define IH_CREDIT_STATUS__CLIENT_28_CREDIT_RETURNED_MASK 0x10000000L 843 #define IH_CREDIT_STATUS__CLIENT_29_CREDIT_RETURNED_MASK 0x20000000L 844 #define IH_CREDIT_STATUS__CLIENT_30_CREDIT_RETURNED_MASK 0x40000000L 845 #define IH_CREDIT_STATUS__CLIENT_31_CREDIT_RETURNED_MASK 0x80000000L 846 //IH_MMHUB_ERROR 847 #define IH_MMHUB_ERROR__IH_BRESP_01__SHIFT 0x1 848 #define IH_MMHUB_ERROR__IH_BRESP_10__SHIFT 0x2 849 #define IH_MMHUB_ERROR__IH_BRESP_11__SHIFT 0x3 850 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01__SHIFT 0x5 851 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10__SHIFT 0x6 852 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11__SHIFT 0x7 853 #define IH_MMHUB_ERROR__IH_BRESP_01_MASK 0x00000002L 854 #define IH_MMHUB_ERROR__IH_BRESP_10_MASK 0x00000004L 855 #define IH_MMHUB_ERROR__IH_BRESP_11_MASK 0x00000008L 856 #define IH_MMHUB_ERROR__IH_BUSER_NACK_01_MASK 0x00000020L 857 #define IH_MMHUB_ERROR__IH_BUSER_NACK_10_MASK 0x00000040L 858 #define IH_MMHUB_ERROR__IH_BUSER_NACK_11_MASK 0x00000080L 859 //IH_REGISTER_LAST_PART2 860 #define IH_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 861 #define IH_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 862 //SEM_CLK_CTRL 863 #define SEM_CLK_CTRL__ON_DELAY__SHIFT 0x0 864 #define SEM_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 865 #define SEM_CLK_CTRL__RESERVED__SHIFT 0xc 866 #define SEM_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 867 #define SEM_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 868 #define SEM_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 869 #define SEM_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 870 #define SEM_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 871 #define SEM_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 872 #define SEM_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 873 #define SEM_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 874 #define SEM_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 875 #define SEM_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 876 #define SEM_CLK_CTRL__RESERVED_MASK 0x00FFF000L 877 #define SEM_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 878 #define SEM_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 879 #define SEM_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 880 #define SEM_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 881 #define SEM_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 882 #define SEM_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 883 #define SEM_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 884 #define SEM_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 885 //SEM_UTC_CREDIT 886 #define SEM_UTC_CREDIT__UTCL2_CREDIT__SHIFT 0x0 887 #define SEM_UTC_CREDIT__WATERMARK__SHIFT 0x8 888 #define SEM_UTC_CREDIT__UTCL2_CREDIT_MASK 0x0000001FL 889 #define SEM_UTC_CREDIT__WATERMARK_MASK 0x00000F00L 890 //SEM_UTC_CONFIG 891 #define SEM_UTC_CONFIG__USE_MTYPE__SHIFT 0x0 892 #define SEM_UTC_CONFIG__FORCE_SNOOP__SHIFT 0x3 893 #define SEM_UTC_CONFIG__FORCE_GCC__SHIFT 0x4 894 #define SEM_UTC_CONFIG__USE_PT_SNOOP__SHIFT 0x5 895 #define SEM_UTC_CONFIG__USE_MTYPE_MASK 0x00000007L 896 #define SEM_UTC_CONFIG__FORCE_SNOOP_MASK 0x00000008L 897 #define SEM_UTC_CONFIG__FORCE_GCC_MASK 0x00000010L 898 #define SEM_UTC_CONFIG__USE_PT_SNOOP_MASK 0x00000020L 899 //SEM_UTCL2_TRAN_EN_LUT 900 #define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN__SHIFT 0x0 901 #define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN__SHIFT 0x1 902 #define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN__SHIFT 0x2 903 #define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN__SHIFT 0x3 904 #define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN__SHIFT 0x4 905 #define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN__SHIFT 0x5 906 #define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN__SHIFT 0x6 907 #define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN__SHIFT 0x7 908 #define SEM_UTCL2_TRAN_EN_LUT__RESERVED__SHIFT 0x8 909 #define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN__SHIFT 0x1f 910 #define SEM_UTCL2_TRAN_EN_LUT__SDMA0_UTCL2_EN_MASK 0x00000001L 911 #define SEM_UTCL2_TRAN_EN_LUT__SDMA1_UTCL2_EN_MASK 0x00000002L 912 #define SEM_UTCL2_TRAN_EN_LUT__UVD_UTCL2_EN_MASK 0x00000004L 913 #define SEM_UTCL2_TRAN_EN_LUT__VCE0_UTCL2_EN_MASK 0x00000008L 914 #define SEM_UTCL2_TRAN_EN_LUT__ACP_UTCL2_EN_MASK 0x00000010L 915 #define SEM_UTCL2_TRAN_EN_LUT__ISP_UTCL2_EN_MASK 0x00000020L 916 #define SEM_UTCL2_TRAN_EN_LUT__VCE1_UTCL2_EN_MASK 0x00000040L 917 #define SEM_UTCL2_TRAN_EN_LUT__VP8_UTCL2_EN_MASK 0x00000080L 918 #define SEM_UTCL2_TRAN_EN_LUT__RESERVED_MASK 0x7FFFFF00L 919 #define SEM_UTCL2_TRAN_EN_LUT__CP_UTCL2_EN_MASK 0x80000000L 920 //SEM_MCIF_CONFIG 921 #define SEM_MCIF_CONFIG__MC_REQ_SWAP__SHIFT 0x0 922 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT__SHIFT 0x2 923 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT__SHIFT 0x8 924 #define SEM_MCIF_CONFIG__MC_REQ_SWAP_MASK 0x00000003L 925 #define SEM_MCIF_CONFIG__MC_WRREQ_CREDIT_MASK 0x000000FCL 926 #define SEM_MCIF_CONFIG__MC_RDREQ_CREDIT_MASK 0x00003F00L 927 //SEM_PERFMON_CNTL 928 #define SEM_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 929 #define SEM_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 930 #define SEM_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 931 #define SEM_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 932 #define SEM_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 933 #define SEM_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 934 #define SEM_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 935 #define SEM_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 936 #define SEM_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 937 #define SEM_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 938 #define SEM_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 939 #define SEM_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 940 //SEM_PERFCOUNTER0_RESULT 941 #define SEM_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 942 #define SEM_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 943 //SEM_PERFCOUNTER1_RESULT 944 #define SEM_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 945 #define SEM_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 946 //SEM_STATUS 947 #define SEM_STATUS__SEM_IDLE__SHIFT 0x0 948 #define SEM_STATUS__SEM_INTERNAL_IDLE__SHIFT 0x1 949 #define SEM_STATUS__MC_RDREQ_FIFO_FULL__SHIFT 0x2 950 #define SEM_STATUS__MC_WRREQ_FIFO_FULL__SHIFT 0x3 951 #define SEM_STATUS__WRITE1_FIFO_FULL__SHIFT 0x4 952 #define SEM_STATUS__CHECK0_FIFO_FULL__SHIFT 0x5 953 #define SEM_STATUS__MC_RDREQ_PENDING__SHIFT 0x6 954 #define SEM_STATUS__MC_WRREQ_PENDING__SHIFT 0x7 955 #define SEM_STATUS__SDMA0_MAILBOX_PENDING__SHIFT 0x8 956 #define SEM_STATUS__SDMA1_MAILBOX_PENDING__SHIFT 0x9 957 #define SEM_STATUS__UVD_MAILBOX_PENDING__SHIFT 0xa 958 #define SEM_STATUS__VCE_MAILBOX_PENDING__SHIFT 0xb 959 #define SEM_STATUS__CPG1_MAILBOX_PENDING__SHIFT 0xc 960 #define SEM_STATUS__CPG2_MAILBOX_PENDING__SHIFT 0xd 961 #define SEM_STATUS__VCE1_MAILBOX_PENDING__SHIFT 0xe 962 #define SEM_STATUS__ATC_REQ_PENDING__SHIFT 0xf 963 #define SEM_STATUS__OUTSTANDING_CLEAN__SHIFT 0x10 964 #define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH__SHIFT 0x11 965 #define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH__SHIFT 0x12 966 #define SEM_STATUS__INVREQ_CNT_IDLE__SHIFT 0x13 967 #define SEM_STATUS__ENTRYLIST_IDLE__SHIFT 0x14 968 #define SEM_STATUS__MIF_IDLE__SHIFT 0x15 969 #define SEM_STATUS__REGISTER_IDLE__SHIFT 0x16 970 #define SEM_STATUS__ATCL2_INVREQ_IDLE__SHIFT 0x17 971 #define SEM_STATUS__SWITCH_READY__SHIFT 0x1f 972 #define SEM_STATUS__SEM_IDLE_MASK 0x00000001L 973 #define SEM_STATUS__SEM_INTERNAL_IDLE_MASK 0x00000002L 974 #define SEM_STATUS__MC_RDREQ_FIFO_FULL_MASK 0x00000004L 975 #define SEM_STATUS__MC_WRREQ_FIFO_FULL_MASK 0x00000008L 976 #define SEM_STATUS__WRITE1_FIFO_FULL_MASK 0x00000010L 977 #define SEM_STATUS__CHECK0_FIFO_FULL_MASK 0x00000020L 978 #define SEM_STATUS__MC_RDREQ_PENDING_MASK 0x00000040L 979 #define SEM_STATUS__MC_WRREQ_PENDING_MASK 0x00000080L 980 #define SEM_STATUS__SDMA0_MAILBOX_PENDING_MASK 0x00000100L 981 #define SEM_STATUS__SDMA1_MAILBOX_PENDING_MASK 0x00000200L 982 #define SEM_STATUS__UVD_MAILBOX_PENDING_MASK 0x00000400L 983 #define SEM_STATUS__VCE_MAILBOX_PENDING_MASK 0x00000800L 984 #define SEM_STATUS__CPG1_MAILBOX_PENDING_MASK 0x00001000L 985 #define SEM_STATUS__CPG2_MAILBOX_PENDING_MASK 0x00002000L 986 #define SEM_STATUS__VCE1_MAILBOX_PENDING_MASK 0x00004000L 987 #define SEM_STATUS__ATC_REQ_PENDING_MASK 0x00008000L 988 #define SEM_STATUS__OUTSTANDING_CLEAN_MASK 0x00010000L 989 #define SEM_STATUS__INVREQ_FLUSH_VF_MISMATCH_MASK 0x00020000L 990 #define SEM_STATUS__INVREQ_NONFLUSH_VF_MISMATCH_MASK 0x00040000L 991 #define SEM_STATUS__INVREQ_CNT_IDLE_MASK 0x00080000L 992 #define SEM_STATUS__ENTRYLIST_IDLE_MASK 0x00100000L 993 #define SEM_STATUS__MIF_IDLE_MASK 0x00200000L 994 #define SEM_STATUS__REGISTER_IDLE_MASK 0x00400000L 995 #define SEM_STATUS__ATCL2_INVREQ_IDLE_MASK 0x00800000L 996 #define SEM_STATUS__SWITCH_READY_MASK 0x80000000L 997 //SEM_MAILBOX_CLIENTCONFIG 998 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0__SHIFT 0x0 999 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1__SHIFT 0x3 1000 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2__SHIFT 0x6 1001 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3__SHIFT 0x9 1002 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0__SHIFT 0xc 1003 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0__SHIFT 0xf 1004 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0__SHIFT 0x12 1005 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0__SHIFT 0x15 1006 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT0_MASK 0x00000007L 1007 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT1_MASK 0x00000038L 1008 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT2_MASK 0x000001C0L 1009 #define SEM_MAILBOX_CLIENTCONFIG__CP_CLIENT3_MASK 0x00000E00L 1010 #define SEM_MAILBOX_CLIENTCONFIG__SDMA_CLIENT0_MASK 0x00007000L 1011 #define SEM_MAILBOX_CLIENTCONFIG__UVD_CLIENT0_MASK 0x00038000L 1012 #define SEM_MAILBOX_CLIENTCONFIG__SDMA1_CLIENT0_MASK 0x001C0000L 1013 #define SEM_MAILBOX_CLIENTCONFIG__VCE_CLIENT0_MASK 0x00E00000L 1014 //SEM_MAILBOX 1015 #define SEM_MAILBOX__HOSTPORT__SHIFT 0x0 1016 #define SEM_MAILBOX__RESERVED__SHIFT 0x10 1017 #define SEM_MAILBOX__HOSTPORT_MASK 0x0000FFFFL 1018 #define SEM_MAILBOX__RESERVED_MASK 0xFFFF0000L 1019 //SEM_MAILBOX_CONTROL 1020 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE__SHIFT 0x0 1021 #define SEM_MAILBOX_CONTROL__RESERVED__SHIFT 0x10 1022 #define SEM_MAILBOX_CONTROL__HOSTPORT_ENABLE_MASK 0x0000FFFFL 1023 #define SEM_MAILBOX_CONTROL__RESERVED_MASK 0xFFFF0000L 1024 //SEM_CHICKEN_BITS 1025 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN__SHIFT 0x0 1026 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN__SHIFT 0x1 1027 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN__SHIFT 0x2 1028 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR__SHIFT 0x3 1029 #define SEM_CHICKEN_BITS__PHY_TRAN_EN__SHIFT 0x6 1030 #define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN__SHIFT 0x7 1031 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX__SHIFT 0x8 1032 #define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX__SHIFT 0xa 1033 #define SEM_CHICKEN_BITS__ATCL2_BUS_ID__SHIFT 0xc 1034 #define SEM_CHICKEN_BITS__ATOMIC_EN__SHIFT 0xe 1035 #define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK__SHIFT 0xf 1036 #define SEM_CHICKEN_BITS__CLEAR_MAILBOX__SHIFT 0x10 1037 #define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN__SHIFT 0x12 1038 #define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK__SHIFT 0x13 1039 #define SEM_CHICKEN_BITS__VMID_PIPELINE_EN_MASK 0x00000001L 1040 #define SEM_CHICKEN_BITS__ENTRY_PIPELINE_EN_MASK 0x00000002L 1041 #define SEM_CHICKEN_BITS__CHECK_COUNTER_EN_MASK 0x00000004L 1042 #define SEM_CHICKEN_BITS__ECC_BEHAVIOR_MASK 0x00000018L 1043 #define SEM_CHICKEN_BITS__PHY_TRAN_EN_MASK 0x00000040L 1044 #define SEM_CHICKEN_BITS__ADDR_CMP_UNTRAN_EN_MASK 0x00000080L 1045 #define SEM_CHICKEN_BITS__IDLE_COUNTER_INDEX_MASK 0x00000300L 1046 #define SEM_CHICKEN_BITS__OUTSTANDING_CLEAN_COUNTER_INDEX_MASK 0x00000C00L 1047 #define SEM_CHICKEN_BITS__ATCL2_BUS_ID_MASK 0x00003000L 1048 #define SEM_CHICKEN_BITS__ATOMIC_EN_MASK 0x00004000L 1049 #define SEM_CHICKEN_BITS__EXTERNAL_ATOMIC_CHECK_MASK 0x00008000L 1050 #define SEM_CHICKEN_BITS__CLEAR_MAILBOX_MASK 0x00030000L 1051 #define SEM_CHICKEN_BITS__INVACK_AFTER_OUTSTANDING_CLEAN_MASK 0x00040000L 1052 #define SEM_CHICKEN_BITS__UTC_TAG_CONFLICT_CHECK_MASK 0x00080000L 1053 //SEM_MAILBOX_CLIENTCONFIG_EXTRA 1054 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0__SHIFT 0x0 1055 #define SEM_MAILBOX_CLIENTCONFIG_EXTRA__VCE1_CLIENT0_MASK 0x0000000FL 1056 //SEM_GPU_IOV_VIOLATION_LOG 1057 #define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1058 #define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1059 #define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1060 #define SEM_GPU_IOV_VIOLATION_LOG__OPCODE__SHIFT 0x12 1061 #define SEM_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1062 #define SEM_GPU_IOV_VIOLATION_LOG__VF_ID__SHIFT 0x14 1063 #define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1064 #define SEM_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1065 #define SEM_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1066 #define SEM_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1067 #define SEM_GPU_IOV_VIOLATION_LOG__OPCODE_MASK 0x00040000L 1068 #define SEM_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1069 #define SEM_GPU_IOV_VIOLATION_LOG__VF_ID_MASK 0x00F00000L 1070 #define SEM_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1071 //SEM_OUTSTANDING_THRESHOLD 1072 #define SEM_OUTSTANDING_THRESHOLD__VALUE__SHIFT 0x0 1073 #define SEM_OUTSTANDING_THRESHOLD__VALUE_MASK 0x000000FFL 1074 //SEM_REGISTER_LAST_PART2 1075 #define SEM_REGISTER_LAST_PART2__RESERVED__SHIFT 0x0 1076 #define SEM_REGISTER_LAST_PART2__RESERVED_MASK 0xFFFFFFFFL 1077 //IH_ACTIVE_FCN_ID 1078 #define IH_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 1079 #define IH_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 1080 #define IH_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f 1081 #define IH_ACTIVE_FCN_ID__VF_ID_MASK 0x0000000FL 1082 #define IH_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 1083 #define IH_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000L 1084 //IH_VIRT_RESET_REQ 1085 #define IH_VIRT_RESET_REQ__VF__SHIFT 0x0 1086 #define IH_VIRT_RESET_REQ__PF__SHIFT 0x1f 1087 #define IH_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1088 #define IH_VIRT_RESET_REQ__PF_MASK 0x80000000L 1089 //IH_CLIENT_CFG 1090 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM__SHIFT 0x0 1091 #define IH_CLIENT_CFG__TOTAL_CLIENT_NUM_MASK 0x0000001FL 1092 //IH_CLIENT_CFG_INDEX 1093 #define IH_CLIENT_CFG_INDEX__INDEX__SHIFT 0x0 1094 #define IH_CLIENT_CFG_INDEX__INDEX_MASK 0x0000001FL 1095 //IH_CLIENT_CFG_DATA 1096 #define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR__SHIFT 0x0 1097 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE__SHIFT 0x12 1098 #define IH_CLIENT_CFG_DATA__RING_ID__SHIFT 0x14 1099 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT__SHIFT 0x16 1100 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID__SHIFT 0x18 1101 #define IH_CLIENT_CFG_DATA__CREDIT_RETURN_ADDR_MASK 0x0001FFFFL 1102 #define IH_CLIENT_CFG_DATA__CLIENT_TYPE_MASK 0x000C0000L 1103 #define IH_CLIENT_CFG_DATA__RING_ID_MASK 0x00300000L 1104 #define IH_CLIENT_CFG_DATA__VF_RB_SELECT_MASK 0x00C00000L 1105 #define IH_CLIENT_CFG_DATA__OVERWRITE_RING_ID_WITH_ACTIVE_FCN_ID_MASK 0x01000000L 1106 //IH_CID_REMAP_INDEX 1107 #define IH_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1108 #define IH_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1109 //IH_CID_REMAP_DATA 1110 #define IH_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1111 #define IH_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1112 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1113 #define IH_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1114 #define IH_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1115 #define IH_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1116 //IH_CHICKEN 1117 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1118 #define IH_CHICKEN__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1119 //IH_MMHUB_CNTL 1120 #define IH_MMHUB_CNTL__UNITID__SHIFT 0x0 1121 #define IH_MMHUB_CNTL__IV_TLVL__SHIFT 0x8 1122 #define IH_MMHUB_CNTL__WPTR_WB_TLVL__SHIFT 0xc 1123 #define IH_MMHUB_CNTL__UNITID_MASK 0x0000003FL 1124 #define IH_MMHUB_CNTL__IV_TLVL_MASK 0x00000700L 1125 #define IH_MMHUB_CNTL__WPTR_WB_TLVL_MASK 0x00007000L 1126 //IH_INT_DROP_CNTL 1127 #define IH_INT_DROP_CNTL__INT_DROP_EN__SHIFT 0x0 1128 #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN__SHIFT 0x1 1129 #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN__SHIFT 0x2 1130 #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN__SHIFT 0x3 1131 #define IH_INT_DROP_CNTL__VF_MATCH_EN__SHIFT 0x4 1132 #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN__SHIFT 0x5 1133 #define IH_INT_DROP_CNTL__INT_DROP_MODE__SHIFT 0x6 1134 #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN__SHIFT 0x8 1135 #define IH_INT_DROP_CNTL__INT_DROPPED__SHIFT 0x10 1136 #define IH_INT_DROP_CNTL__INT_DROP_EN_MASK 0x00000001L 1137 #define IH_INT_DROP_CNTL__CLIENT_ID_MATCH_EN_MASK 0x00000002L 1138 #define IH_INT_DROP_CNTL__SOURCE_ID_MATCH_EN_MASK 0x00000004L 1139 #define IH_INT_DROP_CNTL__VF_ID_MATCH_EN_MASK 0x00000008L 1140 #define IH_INT_DROP_CNTL__VF_MATCH_EN_MASK 0x00000010L 1141 #define IH_INT_DROP_CNTL__CONTEXT_ID_MATCH_EN_MASK 0x00000020L 1142 #define IH_INT_DROP_CNTL__INT_DROP_MODE_MASK 0x000000C0L 1143 #define IH_INT_DROP_CNTL__UTCL2_RETRY_INT_DROP_EN_MASK 0x00000100L 1144 #define IH_INT_DROP_CNTL__INT_DROPPED_MASK 0x00010000L 1145 //IH_INT_DROP_MATCH_VALUE0 1146 #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE__SHIFT 0x0 1147 #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE__SHIFT 0x8 1148 #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE__SHIFT 0x10 1149 #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE__SHIFT 0x17 1150 #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE__SHIFT 0x18 1151 #define IH_INT_DROP_MATCH_VALUE0__CLIENT_ID_MATCH_VALUE_MASK 0x000000FFL 1152 #define IH_INT_DROP_MATCH_VALUE0__SOURCE_ID_MATCH_VALUE_MASK 0x0000FF00L 1153 #define IH_INT_DROP_MATCH_VALUE0__VF_ID_MATCH_VALUE_MASK 0x000F0000L 1154 #define IH_INT_DROP_MATCH_VALUE0__VF_MATCH_VALUE_MASK 0x00800000L 1155 #define IH_INT_DROP_MATCH_VALUE0__CONTEXT_ID_39_32_MATCH_VALUE_MASK 0xFF000000L 1156 //IH_INT_DROP_MATCH_VALUE1 1157 #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE__SHIFT 0x0 1158 #define IH_INT_DROP_MATCH_VALUE1__CONTEXT_ID_31_0_MATCH_VALUE_MASK 0xFFFFFFFFL 1159 //IH_INT_DROP_MATCH_MASK0 1160 #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK__SHIFT 0x0 1161 #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK__SHIFT 0x8 1162 #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK__SHIFT 0x10 1163 #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK__SHIFT 0x17 1164 #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK__SHIFT 0x18 1165 #define IH_INT_DROP_MATCH_MASK0__CLIENT_ID_MATCH_MASK_MASK 0x000000FFL 1166 #define IH_INT_DROP_MATCH_MASK0__SOURCE_ID_MATCH_MASK_MASK 0x0000FF00L 1167 #define IH_INT_DROP_MATCH_MASK0__VF_ID_MATCH_MASK_MASK 0x000F0000L 1168 #define IH_INT_DROP_MATCH_MASK0__VF_MATCH_MASK_MASK 0x00800000L 1169 #define IH_INT_DROP_MATCH_MASK0__CONTEXT_ID_39_32_MATCH_MASK_MASK 0xFF000000L 1170 //IH_INT_DROP_MATCH_MASK1 1171 #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK__SHIFT 0x0 1172 #define IH_INT_DROP_MATCH_MASK1__CONTEXT_ID_31_0_MATCH_MASK_MASK 0xFFFFFFFFL 1173 //IH_REGISTER_LAST_PART1 1174 #define IH_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1175 #define IH_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1176 //SEM_ACTIVE_FCN_ID 1177 #define SEM_ACTIVE_FCN_ID__VFID__SHIFT 0x0 1178 #define SEM_ACTIVE_FCN_ID__VF__SHIFT 0x1f 1179 #define SEM_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 1180 #define SEM_ACTIVE_FCN_ID__VF_MASK 0x80000000L 1181 //SEM_VIRT_RESET_REQ 1182 #define SEM_VIRT_RESET_REQ__VF__SHIFT 0x0 1183 #define SEM_VIRT_RESET_REQ__PF__SHIFT 0x1f 1184 #define SEM_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 1185 #define SEM_VIRT_RESET_REQ__PF_MASK 0x80000000L 1186 //SEM_RESP_SDMA0 1187 #define SEM_RESP_SDMA0__ADDR__SHIFT 0x2 1188 #define SEM_RESP_SDMA0__ADDR_MASK 0x000FFFFCL 1189 //SEM_RESP_SDMA1 1190 #define SEM_RESP_SDMA1__ADDR__SHIFT 0x2 1191 #define SEM_RESP_SDMA1__ADDR_MASK 0x000FFFFCL 1192 //SEM_RESP_UVD 1193 #define SEM_RESP_UVD__ADDR__SHIFT 0x2 1194 #define SEM_RESP_UVD__ADDR_MASK 0x000FFFFCL 1195 //SEM_RESP_VCE_0 1196 #define SEM_RESP_VCE_0__ADDR__SHIFT 0x2 1197 #define SEM_RESP_VCE_0__ADDR_MASK 0x000FFFFCL 1198 //SEM_RESP_ACP 1199 #define SEM_RESP_ACP__ADDR__SHIFT 0x2 1200 #define SEM_RESP_ACP__ADDR_MASK 0x000FFFFCL 1201 //SEM_RESP_ISP 1202 #define SEM_RESP_ISP__ADDR__SHIFT 0x2 1203 #define SEM_RESP_ISP__ADDR_MASK 0x000FFFFCL 1204 //SEM_RESP_VCE_1 1205 #define SEM_RESP_VCE_1__ADDR__SHIFT 0x2 1206 #define SEM_RESP_VCE_1__ADDR_MASK 0x000FFFFCL 1207 //SEM_RESP_VP8 1208 #define SEM_RESP_VP8__ADDR__SHIFT 0x2 1209 #define SEM_RESP_VP8__ADDR_MASK 0x000FFFFCL 1210 //SEM_RESP_GC 1211 #define SEM_RESP_GC__ADDR__SHIFT 0x2 1212 #define SEM_RESP_GC__ADDR_MASK 0x000FFFFCL 1213 //SEM_CID_REMAP_INDEX 1214 #define SEM_CID_REMAP_INDEX__INDEX__SHIFT 0x0 1215 #define SEM_CID_REMAP_INDEX__INDEX_MASK 0x00000003L 1216 //SEM_CID_REMAP_DATA 1217 #define SEM_CID_REMAP_DATA__CLIENT_ID__SHIFT 0x0 1218 #define SEM_CID_REMAP_DATA__INITIATOR_ID__SHIFT 0x8 1219 #define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP__SHIFT 0x10 1220 #define SEM_CID_REMAP_DATA__CLIENT_ID_MASK 0x000000FFL 1221 #define SEM_CID_REMAP_DATA__INITIATOR_ID_MASK 0x0000FF00L 1222 #define SEM_CID_REMAP_DATA__CLIENT_ID_REMAP_MASK 0x00FF0000L 1223 //SEM_ATOMIC_OP_LUT 1224 #define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL__SHIFT 0x0 1225 #define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1__SHIFT 0x7 1226 #define SEM_ATOMIC_OP_LUT__WAIT_NORMAL__SHIFT 0xe 1227 #define SEM_ATOMIC_OP_LUT__WAIT_CHECK0__SHIFT 0x15 1228 #define SEM_ATOMIC_OP_LUT__SIGNAL_NORMAL_MASK 0x0000007FL 1229 #define SEM_ATOMIC_OP_LUT__SIGNAL_WRITE1_MASK 0x00003F80L 1230 #define SEM_ATOMIC_OP_LUT__WAIT_NORMAL_MASK 0x001FC000L 1231 #define SEM_ATOMIC_OP_LUT__WAIT_CHECK0_MASK 0x0FE00000L 1232 //SEM_EDC_CONFIG 1233 #define SEM_EDC_CONFIG__DIS_EDC__SHIFT 0x1 1234 #define SEM_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 1235 //SEM_CHICKEN_BITS2 1236 #define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE__SHIFT 0x0 1237 #define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID__SHIFT 0x1 1238 #define SEM_CHICKEN_BITS2__ACTIVE_FCN_ID_PROT_ENABLE_MASK 0x00000001L 1239 #define SEM_CHICKEN_BITS2__MM_CLIENT_USE_CONFIG_VFID_MASK 0x00000002L 1240 //SEM_MMHUB_CNTL 1241 #define SEM_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 1242 #define SEM_MMHUB_CNTL__TLVL_VALUE__SHIFT 0x8 1243 #define SEM_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 1244 #define SEM_MMHUB_CNTL__TLVL_VALUE_MASK 0x00000700L 1245 //SEM_REGISTER_LAST_PART1 1246 #define SEM_REGISTER_LAST_PART1__RESERVED__SHIFT 0x0 1247 #define SEM_REGISTER_LAST_PART1__RESERVED_MASK 0xFFFFFFFFL 1248 1249 #endif 1250