1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright (C) 2017 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included 12*b843c749SSergey Zigachev * in all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15*b843c749SSergey Zigachev * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18*b843c749SSergey Zigachev * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19*b843c749SSergey Zigachev * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20*b843c749SSergey Zigachev */ 21*b843c749SSergey Zigachev #ifndef _sdma0_4_1_SH_MASK_HEADER 22*b843c749SSergey Zigachev #define _sdma0_4_1_SH_MASK_HEADER 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev 25*b843c749SSergey Zigachev // addressBlock: sdma0_sdma0dec 26*b843c749SSergey Zigachev //SDMA0_UCODE_ADDR 27*b843c749SSergey Zigachev #define SDMA0_UCODE_ADDR__VALUE__SHIFT 0x0 28*b843c749SSergey Zigachev #define SDMA0_UCODE_ADDR__VALUE_MASK 0x00001FFFL 29*b843c749SSergey Zigachev //SDMA0_UCODE_DATA 30*b843c749SSergey Zigachev #define SDMA0_UCODE_DATA__VALUE__SHIFT 0x0 31*b843c749SSergey Zigachev #define SDMA0_UCODE_DATA__VALUE_MASK 0xFFFFFFFFL 32*b843c749SSergey Zigachev //SDMA0_VM_CNTL 33*b843c749SSergey Zigachev #define SDMA0_VM_CNTL__CMD__SHIFT 0x0 34*b843c749SSergey Zigachev #define SDMA0_VM_CNTL__CMD_MASK 0x0000000FL 35*b843c749SSergey Zigachev //SDMA0_VM_CTX_LO 36*b843c749SSergey Zigachev #define SDMA0_VM_CTX_LO__ADDR__SHIFT 0x2 37*b843c749SSergey Zigachev #define SDMA0_VM_CTX_LO__ADDR_MASK 0xFFFFFFFCL 38*b843c749SSergey Zigachev //SDMA0_VM_CTX_HI 39*b843c749SSergey Zigachev #define SDMA0_VM_CTX_HI__ADDR__SHIFT 0x0 40*b843c749SSergey Zigachev #define SDMA0_VM_CTX_HI__ADDR_MASK 0xFFFFFFFFL 41*b843c749SSergey Zigachev //SDMA0_ACTIVE_FCN_ID 42*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__VFID__SHIFT 0x0 43*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 44*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__VF__SHIFT 0x1f 45*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 46*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__RESERVED_MASK 0x7FFFFFF0L 47*b843c749SSergey Zigachev #define SDMA0_ACTIVE_FCN_ID__VF_MASK 0x80000000L 48*b843c749SSergey Zigachev //SDMA0_VM_CTX_CNTL 49*b843c749SSergey Zigachev #define SDMA0_VM_CTX_CNTL__PRIV__SHIFT 0x0 50*b843c749SSergey Zigachev #define SDMA0_VM_CTX_CNTL__VMID__SHIFT 0x4 51*b843c749SSergey Zigachev #define SDMA0_VM_CTX_CNTL__PRIV_MASK 0x00000001L 52*b843c749SSergey Zigachev #define SDMA0_VM_CTX_CNTL__VMID_MASK 0x000000F0L 53*b843c749SSergey Zigachev //SDMA0_VIRT_RESET_REQ 54*b843c749SSergey Zigachev #define SDMA0_VIRT_RESET_REQ__VF__SHIFT 0x0 55*b843c749SSergey Zigachev #define SDMA0_VIRT_RESET_REQ__PF__SHIFT 0x1f 56*b843c749SSergey Zigachev #define SDMA0_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 57*b843c749SSergey Zigachev #define SDMA0_VIRT_RESET_REQ__PF_MASK 0x80000000L 58*b843c749SSergey Zigachev //SDMA0_CONTEXT_REG_TYPE0 59*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL__SHIFT 0x0 60*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE__SHIFT 0x1 61*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI__SHIFT 0x2 62*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR__SHIFT 0x3 63*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI__SHIFT 0x4 64*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR__SHIFT 0x5 65*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI__SHIFT 0x6 66*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL__SHIFT 0x7 67*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI__SHIFT 0x8 68*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO__SHIFT 0x9 69*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL__SHIFT 0xa 70*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR__SHIFT 0xb 71*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET__SHIFT 0xc 72*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO__SHIFT 0xd 73*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI__SHIFT 0xe 74*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE__SHIFT 0xf 75*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL__SHIFT 0x10 76*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS__SHIFT 0x11 77*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL__SHIFT 0x12 78*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL__SHIFT 0x13 79*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_CNTL_MASK 0x00000001L 80*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_MASK 0x00000002L 81*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_BASE_HI_MASK 0x00000004L 82*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_MASK 0x00000008L 83*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_HI_MASK 0x00000010L 84*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_MASK 0x00000020L 85*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_HI_MASK 0x00000040L 86*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_WPTR_POLL_CNTL_MASK 0x00000080L 87*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_HI_MASK 0x00000100L 88*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_RB_RPTR_ADDR_LO_MASK 0x00000200L 89*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_CNTL_MASK 0x00000400L 90*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_RPTR_MASK 0x00000800L 91*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_OFFSET_MASK 0x00001000L 92*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_LO_MASK 0x00002000L 93*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_BASE_HI_MASK 0x00004000L 94*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_IB_SIZE_MASK 0x00008000L 95*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_SKIP_CNTL_MASK 0x00010000L 96*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_STATUS_MASK 0x00020000L 97*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_DOORBELL_MASK 0x00040000L 98*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE0__SDMA0_GFX_CONTEXT_CNTL_MASK 0x00080000L 99*b843c749SSergey Zigachev //SDMA0_CONTEXT_REG_TYPE1 100*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS__SHIFT 0x8 101*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG__SHIFT 0x9 102*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK__SHIFT 0xa 103*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET__SHIFT 0xb 104*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO__SHIFT 0xc 105*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI__SHIFT 0xd 106*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2__SHIFT 0xe 107*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN__SHIFT 0xf 108*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT__SHIFT 0x10 109*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG__SHIFT 0x11 110*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__SHIFT 0x12 111*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__SHIFT 0x13 112*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL__SHIFT 0x14 113*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE__SHIFT 0x15 114*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x16 115*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_STATUS_MASK 0x00000100L 116*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_LOG_MASK 0x00000200L 117*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_WATERMARK_MASK 0x00000400L 118*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DOORBELL_OFFSET_MASK 0x00000800L 119*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_LO_MASK 0x00001000L 120*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_CSA_ADDR_HI_MASK 0x00002000L 121*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__VOID_REG2_MASK 0x00004000L 122*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_IB_SUB_REMAIN_MASK 0x00008000L 123*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_PREEMPT_MASK 0x00010000L 124*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_DUMMY_REG_MASK 0x00020000L 125*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_HI_MASK 0x00040000L 126*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_WPTR_POLL_ADDR_LO_MASK 0x00080000L 127*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_RB_AQL_CNTL_MASK 0x00100000L 128*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__SDMA0_GFX_MINOR_PTR_UPDATE_MASK 0x00200000L 129*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE1__RESERVED_MASK 0xFFC00000L 130*b843c749SSergey Zigachev //SDMA0_CONTEXT_REG_TYPE2 131*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0__SHIFT 0x0 132*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1__SHIFT 0x1 133*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2__SHIFT 0x2 134*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3__SHIFT 0x3 135*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4__SHIFT 0x4 136*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5__SHIFT 0x5 137*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6__SHIFT 0x6 138*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7__SHIFT 0x7 139*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8__SHIFT 0x8 140*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL__SHIFT 0x9 141*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa 142*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA0_MASK 0x00000001L 143*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA1_MASK 0x00000002L 144*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA2_MASK 0x00000004L 145*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA3_MASK 0x00000008L 146*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA4_MASK 0x00000010L 147*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA5_MASK 0x00000020L 148*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA6_MASK 0x00000040L 149*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA7_MASK 0x00000080L 150*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_DATA8_MASK 0x00000100L 151*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__SDMA0_GFX_MIDCMD_CNTL_MASK 0x00000200L 152*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE2__RESERVED_MASK 0xFFFFFC00L 153*b843c749SSergey Zigachev //SDMA0_CONTEXT_REG_TYPE3 154*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE3__RESERVED__SHIFT 0x0 155*b843c749SSergey Zigachev #define SDMA0_CONTEXT_REG_TYPE3__RESERVED_MASK 0xFFFFFFFFL 156*b843c749SSergey Zigachev //SDMA0_PUB_REG_TYPE0 157*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0 158*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1 159*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED3__SHIFT 0x3 160*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL__SHIFT 0x4 161*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO__SHIFT 0x5 162*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI__SHIFT 0x6 163*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID__SHIFT 0x7 164*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL__SHIFT 0x8 165*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ__SHIFT 0x9 166*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED10__SHIFT 0xa 167*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0__SHIFT 0xb 168*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1__SHIFT 0xc 169*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2__SHIFT 0xd 170*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3__SHIFT 0xe 171*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0__SHIFT 0xf 172*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1__SHIFT 0x10 173*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2__SHIFT 0x11 174*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3__SHIFT 0x12 175*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL__SHIFT 0x13 176*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY__SHIFT 0x14 177*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY__SHIFT 0x19 178*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x1a 179*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL__SHIFT 0x1b 180*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL__SHIFT 0x1c 181*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS__SHIFT 0x1d 182*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG__SHIFT 0x1e 183*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ__SHIFT 0x1f 184*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR_MASK 0x00000001L 185*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA_MASK 0x00000002L 186*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED3_MASK 0x00000008L 187*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CNTL_MASK 0x00000010L 188*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_LO_MASK 0x00000020L 189*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_HI_MASK 0x00000040L 190*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_ACTIVE_FCN_ID_MASK 0x00000080L 191*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VM_CTX_CNTL_MASK 0x00000100L 192*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_VIRT_RESET_REQ_MASK 0x00000200L 193*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED10_MASK 0x00000400L 194*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE0_MASK 0x00000800L 195*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE1_MASK 0x00001000L 196*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE2_MASK 0x00002000L 197*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_REG_TYPE3_MASK 0x00004000L 198*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE0_MASK 0x00008000L 199*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE1_MASK 0x00010000L 200*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE2_MASK 0x00020000L 201*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_PUB_REG_TYPE3_MASK 0x00040000L 202*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_MMHUB_CNTL_MASK 0x00080000L 203*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__RESERVED_FOR_PSPSMU_ACCESS_ONLY_MASK 0x01F00000L 204*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CONTEXT_GROUP_BOUNDARY_MASK 0x02000000L 205*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL_MASK 0x04000000L 206*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CLK_CTRL_MASK 0x08000000L 207*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CNTL_MASK 0x10000000L 208*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_CHICKEN_BITS_MASK 0x20000000L 209*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_MASK 0x40000000L 210*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE0__SDMA0_GB_ADDR_CONFIG_READ_MASK 0x80000000L 211*b843c749SSergey Zigachev //SDMA0_PUB_REG_TYPE1 212*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI__SHIFT 0x0 213*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__SHIFT 0x1 214*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH__SHIFT 0x2 215*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH__SHIFT 0x3 216*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM__SHIFT 0x4 217*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG__SHIFT 0x5 218*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG__SHIFT 0x6 219*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL__SHIFT 0x7 220*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG__SHIFT 0x8 221*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM__SHIFT 0x9 222*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL__SHIFT 0xa 223*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE__SHIFT 0xb 224*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM__SHIFT 0xc 225*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM__SHIFT 0xd 226*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING__SHIFT 0xe 227*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG__SHIFT 0xf 228*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE__SHIFT 0x10 229*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ__SHIFT 0x11 230*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG__SHIFT 0x12 231*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD__SHIFT 0x13 232*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ID__SHIFT 0x14 233*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION__SHIFT 0x15 234*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER__SHIFT 0x16 235*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR__SHIFT 0x17 236*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x18 237*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x19 238*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO__SHIFT 0x1a 239*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI__SHIFT 0x1b 240*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL__SHIFT 0x1c 241*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK__SHIFT 0x1d 242*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS__SHIFT 0x1e 243*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT 0x1f 244*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_HI_MASK 0x00000001L 245*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_SEM_WAIT_FAIL_TIMER_CNTL_MASK 0x00000002L 246*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RB_RPTR_FETCH_MASK 0x00000004L 247*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_IB_OFFSET_FETCH_MASK 0x00000008L 248*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PROGRAM_MASK 0x00000010L 249*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS_REG_MASK 0x00000020L 250*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS1_REG_MASK 0x00000040L 251*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_RD_BURST_CNTL_MASK 0x00000080L 252*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_HBM_PAGE_CONFIG_MASK 0x00000100L 253*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UCODE_CHECKSUM_MASK 0x00000200L 254*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_F32_CNTL_MASK 0x00000400L 255*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_FREEZE_MASK 0x00000800L 256*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE0_QUANTUM_MASK 0x00001000L 257*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_PHASE1_QUANTUM_MASK 0x00002000L 258*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_POWER_GATING_MASK 0x00004000L 259*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_CONFIG_MASK 0x00008000L 260*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_WRITE_MASK 0x00010000L 261*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA_PGFSM_READ_MASK 0x00020000L 262*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_CONFIG_MASK 0x00040000L 263*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_BA_THRESHOLD_MASK 0x00080000L 264*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ID_MASK 0x00100000L 265*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_VERSION_MASK 0x00200000L 266*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_MASK 0x00400000L 267*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_EDC_COUNTER_CLEAR_MASK 0x00800000L 268*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG_MASK 0x01000000L 269*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL_MASK 0x02000000L 270*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_LO_MASK 0x04000000L 271*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_PREOP_HI_MASK 0x08000000L 272*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_CNTL_MASK 0x10000000L 273*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WATERMK_MASK 0x20000000L 274*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_RD_STATUS_MASK 0x40000000L 275*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS_MASK 0x80000000L 276*b843c749SSergey Zigachev //SDMA0_PUB_REG_TYPE2 277*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0__SHIFT 0x0 278*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1__SHIFT 0x1 279*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2__SHIFT 0x2 280*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0__SHIFT 0x3 281*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1__SHIFT 0x4 282*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0__SHIFT 0x5 283*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1__SHIFT 0x6 284*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT__SHIFT 0x7 285*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE__SHIFT 0x8 286*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE__SHIFT 0x9 287*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT__SHIFT 0xa 288*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2__SHIFT 0xb 289*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG__SHIFT 0xc 290*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO__SHIFT 0xd 291*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI__SHIFT 0xe 292*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG__SHIFT 0x10 293*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0__SHIFT 0x11 294*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1__SHIFT 0x12 295*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2__SHIFT 0x13 296*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3__SHIFT 0x14 297*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER__SHIFT 0x15 298*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE__SHIFT 0x16 299*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL__SHIFT 0x17 300*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT__SHIFT 0x18 301*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT__SHIFT 0x19 302*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SHIFT 0x1a 303*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL__SHIFT 0x1b 304*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL__SHIFT 0x1c 305*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG__SHIFT 0x1d 306*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL__SHIFT 0x1e 307*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__RESERVED__SHIFT 0x1f 308*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV0_MASK 0x00000001L 309*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV1_MASK 0x00000002L 310*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_INV2_MASK 0x00000004L 311*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK0_MASK 0x00000008L 312*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_RD_XNACK1_MASK 0x00000010L 313*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK0_MASK 0x00000020L 314*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_WR_XNACK1_MASK 0x00000040L 315*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_TIMEOUT_MASK 0x00000080L 316*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UTCL1_PAGE_MASK 0x00000100L 317*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_POWER_CNTL_IDLE_MASK 0x00000200L 318*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_RELAX_ORDERING_LUT_MASK 0x00000400L 319*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_CHICKEN_BITS_2_MASK 0x00000800L 320*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_STATUS3_REG_MASK 0x00001000L 321*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_LO_MASK 0x00002000L 322*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PHYSICAL_ADDR_HI_MASK 0x00004000L 323*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_ERROR_LOG_MASK 0x00010000L 324*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG0_MASK 0x00020000L 325*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG1_MASK 0x00040000L 326*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG2_MASK 0x00080000L 327*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PUB_DUMMY_REG3_MASK 0x00100000L 328*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_F32_COUNTER_MASK 0x00200000L 329*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_UNBREAKABLE_MASK 0x00400000L 330*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFMON_CNTL_MASK 0x00800000L 331*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER0_RESULT_MASK 0x01000000L 332*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER1_RESULT_MASK 0x02000000L 333*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_PERFCOUNTER_TAG_DELAY_RANGE_MASK 0x04000000L 334*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_CRD_CNTL_MASK 0x08000000L 335*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_MMHUB_TRUSTLVL_MASK 0x10000000L 336*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_GPU_IOV_VIOLATION_LOG_MASK 0x20000000L 337*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__SDMA0_ULV_CNTL_MASK 0x40000000L 338*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE2__RESERVED_MASK 0x80000000L 339*b843c749SSergey Zigachev //SDMA0_PUB_REG_TYPE3 340*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA__SHIFT 0x0 341*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX__SHIFT 0x1 342*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__RESERVED__SHIFT 0x2 343*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_DATA_MASK 0x00000001L 344*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__SDMA0_EA_DBIT_ADDR_INDEX_MASK 0x00000002L 345*b843c749SSergey Zigachev #define SDMA0_PUB_REG_TYPE3__RESERVED_MASK 0xFFFFFFFCL 346*b843c749SSergey Zigachev //SDMA0_MMHUB_CNTL 347*b843c749SSergey Zigachev #define SDMA0_MMHUB_CNTL__UNIT_ID__SHIFT 0x0 348*b843c749SSergey Zigachev #define SDMA0_MMHUB_CNTL__UNIT_ID_MASK 0x0000003FL 349*b843c749SSergey Zigachev //SDMA0_CONTEXT_GROUP_BOUNDARY 350*b843c749SSergey Zigachev #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED__SHIFT 0x0 351*b843c749SSergey Zigachev #define SDMA0_CONTEXT_GROUP_BOUNDARY__RESERVED_MASK 0xFFFFFFFFL 352*b843c749SSergey Zigachev //SDMA0_POWER_CNTL 353*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE__SHIFT 0x0 354*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ__SHIFT 0x1 355*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ__SHIFT 0x2 356*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME__SHIFT 0x3 357*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE__SHIFT 0x8 358*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN__SHIFT 0x9 359*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN__SHIFT 0xa 360*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN__SHIFT 0xb 361*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_DELAY__SHIFT 0xc 362*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME__SHIFT 0x1a 363*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__PG_CNTL_ENABLE_MASK 0x00000001L 364*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__EXT_PG_POWER_ON_REQ_MASK 0x00000002L 365*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__EXT_PG_POWER_OFF_REQ_MASK 0x00000004L 366*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L 367*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK 0x00000100L 368*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_LS_EN_MASK 0x00000200L 369*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_DS_EN_MASK 0x00000400L 370*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_SD_EN_MASK 0x00000800L 371*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__MEM_POWER_DELAY_MASK 0x003FF000L 372*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L 373*b843c749SSergey Zigachev //SDMA0_CLK_CTRL 374*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__ON_DELAY__SHIFT 0x0 375*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 376*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__RESERVED__SHIFT 0xc 377*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 378*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 379*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a 380*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b 381*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c 382*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d 383*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e 384*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f 385*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 386*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 387*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__RESERVED_MASK 0x00FFF000L 388*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x01000000L 389*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x02000000L 390*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x04000000L 391*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x08000000L 392*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000L 393*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000L 394*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000L 395*b843c749SSergey Zigachev #define SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000L 396*b843c749SSergey Zigachev //SDMA0_CNTL 397*b843c749SSergey Zigachev #define SDMA0_CNTL__TRAP_ENABLE__SHIFT 0x0 398*b843c749SSergey Zigachev #define SDMA0_CNTL__UTC_L1_ENABLE__SHIFT 0x1 399*b843c749SSergey Zigachev #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2 400*b843c749SSergey Zigachev #define SDMA0_CNTL__DATA_SWAP_ENABLE__SHIFT 0x3 401*b843c749SSergey Zigachev #define SDMA0_CNTL__FENCE_SWAP_ENABLE__SHIFT 0x4 402*b843c749SSergey Zigachev #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE__SHIFT 0x5 403*b843c749SSergey Zigachev #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE__SHIFT 0x11 404*b843c749SSergey Zigachev #define SDMA0_CNTL__AUTO_CTXSW_ENABLE__SHIFT 0x12 405*b843c749SSergey Zigachev #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE__SHIFT 0x1c 406*b843c749SSergey Zigachev #define SDMA0_CNTL__FROZEN_INT_ENABLE__SHIFT 0x1d 407*b843c749SSergey Zigachev #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE__SHIFT 0x1e 408*b843c749SSergey Zigachev #define SDMA0_CNTL__TRAP_ENABLE_MASK 0x00000001L 409*b843c749SSergey Zigachev #define SDMA0_CNTL__UTC_L1_ENABLE_MASK 0x00000002L 410*b843c749SSergey Zigachev #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE_MASK 0x00000004L 411*b843c749SSergey Zigachev #define SDMA0_CNTL__DATA_SWAP_ENABLE_MASK 0x00000008L 412*b843c749SSergey Zigachev #define SDMA0_CNTL__FENCE_SWAP_ENABLE_MASK 0x00000010L 413*b843c749SSergey Zigachev #define SDMA0_CNTL__MIDCMD_PREEMPT_ENABLE_MASK 0x00000020L 414*b843c749SSergey Zigachev #define SDMA0_CNTL__MIDCMD_WORLDSWITCH_ENABLE_MASK 0x00020000L 415*b843c749SSergey Zigachev #define SDMA0_CNTL__AUTO_CTXSW_ENABLE_MASK 0x00040000L 416*b843c749SSergey Zigachev #define SDMA0_CNTL__CTXEMPTY_INT_ENABLE_MASK 0x10000000L 417*b843c749SSergey Zigachev #define SDMA0_CNTL__FROZEN_INT_ENABLE_MASK 0x20000000L 418*b843c749SSergey Zigachev #define SDMA0_CNTL__IB_PREEMPT_INT_ENABLE_MASK 0x40000000L 419*b843c749SSergey Zigachev //SDMA0_CHICKEN_BITS 420*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE__SHIFT 0x0 421*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE__SHIFT 0x1 422*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE__SHIFT 0x2 423*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH__SHIFT 0x8 424*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE__SHIFT 0xa 425*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE__SHIFT 0x10 426*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE__SHIFT 0x11 427*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING__SHIFT 0x14 428*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT__SHIFT 0x17 429*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS__SHIFT 0x19 430*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK__SHIFT 0x1a 431*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c 432*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK__SHIFT 0x1e 433*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__COPY_EFFICIENCY_ENABLE_MASK 0x00000001L 434*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__STALL_ON_TRANS_FULL_ENABLE_MASK 0x00000002L 435*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__STALL_ON_NO_FREE_DATA_BUFFER_ENABLE_MASK 0x00000004L 436*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__WRITE_BURST_LENGTH_MASK 0x00000300L 437*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__WRITE_BURST_WAIT_CYCLE_MASK 0x00001C00L 438*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__COPY_OVERLAP_ENABLE_MASK 0x00010000L 439*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__RAW_CHECK_ENABLE_MASK 0x00020000L 440*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__SRBM_POLL_RETRYING_MASK 0x00100000L 441*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CG_STATUS_OUTPUT_MASK 0x00800000L 442*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__TIME_BASED_QOS_MASK 0x02000000L 443*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_AFIFO_WATERMARK_MASK 0x0C000000L 444*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK_MASK 0x30000000L 445*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS__CE_LFIFO_WATERMARK_MASK 0xC0000000L 446*b843c749SSergey Zigachev //SDMA0_GB_ADDR_CONFIG 447*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 448*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 449*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 450*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 451*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 452*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 453*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 454*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 455*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 456*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 457*b843c749SSergey Zigachev //SDMA0_GB_ADDR_CONFIG_READ 458*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES__SHIFT 0x0 459*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 460*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE__SHIFT 0x8 461*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS__SHIFT 0xc 462*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES__SHIFT 0x13 463*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_PIPES_MASK 0x00000007L 464*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 465*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 466*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_BANKS_MASK 0x00007000L 467*b843c749SSergey Zigachev #define SDMA0_GB_ADDR_CONFIG_READ__NUM_SHADER_ENGINES_MASK 0x00180000L 468*b843c749SSergey Zigachev //SDMA0_RB_RPTR_FETCH_HI 469*b843c749SSergey Zigachev #define SDMA0_RB_RPTR_FETCH_HI__OFFSET__SHIFT 0x0 470*b843c749SSergey Zigachev #define SDMA0_RB_RPTR_FETCH_HI__OFFSET_MASK 0xFFFFFFFFL 471*b843c749SSergey Zigachev //SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 472*b843c749SSergey Zigachev #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0 473*b843c749SSergey Zigachev #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER_MASK 0xFFFFFFFFL 474*b843c749SSergey Zigachev //SDMA0_RB_RPTR_FETCH 475*b843c749SSergey Zigachev #define SDMA0_RB_RPTR_FETCH__OFFSET__SHIFT 0x2 476*b843c749SSergey Zigachev #define SDMA0_RB_RPTR_FETCH__OFFSET_MASK 0xFFFFFFFCL 477*b843c749SSergey Zigachev //SDMA0_IB_OFFSET_FETCH 478*b843c749SSergey Zigachev #define SDMA0_IB_OFFSET_FETCH__OFFSET__SHIFT 0x2 479*b843c749SSergey Zigachev #define SDMA0_IB_OFFSET_FETCH__OFFSET_MASK 0x003FFFFCL 480*b843c749SSergey Zigachev //SDMA0_PROGRAM 481*b843c749SSergey Zigachev #define SDMA0_PROGRAM__STREAM__SHIFT 0x0 482*b843c749SSergey Zigachev #define SDMA0_PROGRAM__STREAM_MASK 0xFFFFFFFFL 483*b843c749SSergey Zigachev //SDMA0_STATUS_REG 484*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IDLE__SHIFT 0x0 485*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__REG_IDLE__SHIFT 0x1 486*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_EMPTY__SHIFT 0x2 487*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_FULL__SHIFT 0x3 488*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT 0x4 489*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_CMD_FULL__SHIFT 0x5 490*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_CMD_IDLE__SHIFT 0x6 491*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_CMD_FULL__SHIFT 0x7 492*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__BLOCK_IDLE__SHIFT 0x8 493*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INSIDE_IB__SHIFT 0x9 494*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__EX_IDLE__SHIFT 0xa 495*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE__SHIFT 0xb 496*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__PACKET_READY__SHIFT 0xc 497*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_WR_IDLE__SHIFT 0xd 498*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SRBM_IDLE__SHIFT 0xe 499*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__CONTEXT_EMPTY__SHIFT 0xf 500*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__DELTA_RPTR_FULL__SHIFT 0x10 501*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE__SHIFT 0x11 502*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE__SHIFT 0x12 503*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_IDLE__SHIFT 0x13 504*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY__SHIFT 0x14 505*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_RET_STALL__SHIFT 0x15 506*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE__SHIFT 0x16 507*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__PREV_CMD_IDLE__SHIFT 0x19 508*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_IDLE__SHIFT 0x1a 509*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_REQ_STALL__SHIFT 0x1b 510*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_RESP_STATE__SHIFT 0x1c 511*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INT_IDLE__SHIFT 0x1e 512*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INT_REQ_STALL__SHIFT 0x1f 513*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IDLE_MASK 0x00000001L 514*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__REG_IDLE_MASK 0x00000002L 515*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_EMPTY_MASK 0x00000004L 516*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_FULL_MASK 0x00000008L 517*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_CMD_IDLE_MASK 0x00000010L 518*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_CMD_FULL_MASK 0x00000020L 519*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_CMD_IDLE_MASK 0x00000040L 520*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_CMD_FULL_MASK 0x00000080L 521*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__BLOCK_IDLE_MASK 0x00000100L 522*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INSIDE_IB_MASK 0x00000200L 523*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__EX_IDLE_MASK 0x00000400L 524*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__EX_IDLE_POLL_TIMER_EXPIRE_MASK 0x00000800L 525*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__PACKET_READY_MASK 0x00001000L 526*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_WR_IDLE_MASK 0x00002000L 527*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SRBM_IDLE_MASK 0x00004000L 528*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__CONTEXT_EMPTY_MASK 0x00008000L 529*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__DELTA_RPTR_FULL_MASK 0x00010000L 530*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__RB_MC_RREQ_IDLE_MASK 0x00020000L 531*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__IB_MC_RREQ_IDLE_MASK 0x00040000L 532*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_IDLE_MASK 0x00080000L 533*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__DELTA_RPTR_EMPTY_MASK 0x00100000L 534*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_RET_STALL_MASK 0x00200000L 535*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__MC_RD_NO_POLL_IDLE_MASK 0x00400000L 536*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__PREV_CMD_IDLE_MASK 0x02000000L 537*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_IDLE_MASK 0x04000000L 538*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_REQ_STALL_MASK 0x08000000L 539*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__SEM_RESP_STATE_MASK 0x30000000L 540*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INT_IDLE_MASK 0x40000000L 541*b843c749SSergey Zigachev #define SDMA0_STATUS_REG__INT_REQ_STALL_MASK 0x80000000L 542*b843c749SSergey Zigachev //SDMA0_STATUS1_REG 543*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0 544*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1 545*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE__SHIFT 0x2 546*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3 547*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4 548*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5 549*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_DST_IDLE__SHIFT 0x6 550*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_CMD_IDLE__SHIFT 0x9 551*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa 552*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_INFO_FULL__SHIFT 0xd 553*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_INFO1_FULL__SHIFT 0xe 554*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__EX_START__SHIFT 0xf 555*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_RD_STALL__SHIFT 0x11 556*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WR_STALL__SHIFT 0x12 557*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WREQ_IDLE_MASK 0x00000001L 558*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WR_IDLE_MASK 0x00000002L 559*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_SPLIT_IDLE_MASK 0x00000004L 560*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_RREQ_IDLE_MASK 0x00000008L 561*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_OUT_IDLE_MASK 0x00000010L 562*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_IN_IDLE_MASK 0x00000020L 563*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_DST_IDLE_MASK 0x00000040L 564*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_CMD_IDLE_MASK 0x00000200L 565*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_AFIFO_FULL_MASK 0x00000400L 566*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_INFO_FULL_MASK 0x00002000L 567*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_INFO1_FULL_MASK 0x00004000L 568*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__EX_START_MASK 0x00008000L 569*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_RD_STALL_MASK 0x00020000L 570*b843c749SSergey Zigachev #define SDMA0_STATUS1_REG__CE_WR_STALL_MASK 0x00040000L 571*b843c749SSergey Zigachev //SDMA0_RD_BURST_CNTL 572*b843c749SSergey Zigachev #define SDMA0_RD_BURST_CNTL__RD_BURST__SHIFT 0x0 573*b843c749SSergey Zigachev #define SDMA0_RD_BURST_CNTL__RD_BURST_MASK 0x00000003L 574*b843c749SSergey Zigachev //SDMA0_HBM_PAGE_CONFIG 575*b843c749SSergey Zigachev #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT__SHIFT 0x0 576*b843c749SSergey Zigachev #define SDMA0_HBM_PAGE_CONFIG__PAGE_SIZE_EXPONENT_MASK 0x00000003L 577*b843c749SSergey Zigachev //SDMA0_UCODE_CHECKSUM 578*b843c749SSergey Zigachev #define SDMA0_UCODE_CHECKSUM__DATA__SHIFT 0x0 579*b843c749SSergey Zigachev #define SDMA0_UCODE_CHECKSUM__DATA_MASK 0xFFFFFFFFL 580*b843c749SSergey Zigachev //SDMA0_F32_CNTL 581*b843c749SSergey Zigachev #define SDMA0_F32_CNTL__HALT__SHIFT 0x0 582*b843c749SSergey Zigachev #define SDMA0_F32_CNTL__STEP__SHIFT 0x1 583*b843c749SSergey Zigachev #define SDMA0_F32_CNTL__HALT_MASK 0x00000001L 584*b843c749SSergey Zigachev #define SDMA0_F32_CNTL__STEP_MASK 0x00000002L 585*b843c749SSergey Zigachev //SDMA0_FREEZE 586*b843c749SSergey Zigachev #define SDMA0_FREEZE__PREEMPT__SHIFT 0x0 587*b843c749SSergey Zigachev #define SDMA0_FREEZE__FREEZE__SHIFT 0x4 588*b843c749SSergey Zigachev #define SDMA0_FREEZE__FROZEN__SHIFT 0x5 589*b843c749SSergey Zigachev #define SDMA0_FREEZE__F32_FREEZE__SHIFT 0x6 590*b843c749SSergey Zigachev #define SDMA0_FREEZE__PREEMPT_MASK 0x00000001L 591*b843c749SSergey Zigachev #define SDMA0_FREEZE__FREEZE_MASK 0x00000010L 592*b843c749SSergey Zigachev #define SDMA0_FREEZE__FROZEN_MASK 0x00000020L 593*b843c749SSergey Zigachev #define SDMA0_FREEZE__F32_FREEZE_MASK 0x00000040L 594*b843c749SSergey Zigachev //SDMA0_PHASE0_QUANTUM 595*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0 596*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 597*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__PREFER__SHIFT 0x1e 598*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__UNIT_MASK 0x0000000FL 599*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L 600*b843c749SSergey Zigachev #define SDMA0_PHASE0_QUANTUM__PREFER_MASK 0x40000000L 601*b843c749SSergey Zigachev //SDMA0_PHASE1_QUANTUM 602*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0 603*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8 604*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__PREFER__SHIFT 0x1e 605*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__UNIT_MASK 0x0000000FL 606*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__VALUE_MASK 0x00FFFF00L 607*b843c749SSergey Zigachev #define SDMA0_PHASE1_QUANTUM__PREFER_MASK 0x40000000L 608*b843c749SSergey Zigachev //SDMA_POWER_GATING 609*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION__SHIFT 0x0 610*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION__SHIFT 0x1 611*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ__SHIFT 0x2 612*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ__SHIFT 0x3 613*b843c749SSergey Zigachev #define SDMA_POWER_GATING__PG_CNTL_STATUS__SHIFT 0x4 614*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_OFF_CONDITION_MASK 0x00000001L 615*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_ON_CONDITION_MASK 0x00000002L 616*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_OFF_REQ_MASK 0x00000004L 617*b843c749SSergey Zigachev #define SDMA_POWER_GATING__SDMA0_POWER_ON_REQ_MASK 0x00000008L 618*b843c749SSergey Zigachev #define SDMA_POWER_GATING__PG_CNTL_STATUS_MASK 0x00000030L 619*b843c749SSergey Zigachev //SDMA_PGFSM_CONFIG 620*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__FSM_ADDR__SHIFT 0x0 621*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__POWER_DOWN__SHIFT 0x8 622*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__POWER_UP__SHIFT 0x9 623*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa 624*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__P2_SELECT__SHIFT 0xb 625*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__WRITE__SHIFT 0xc 626*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__READ__SHIFT 0xd 627*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE__SHIFT 0x1b 628*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__REG_ADDR__SHIFT 0x1c 629*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__FSM_ADDR_MASK 0x000000FFL 630*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__POWER_DOWN_MASK 0x00000100L 631*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__POWER_UP_MASK 0x00000200L 632*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__P1_SELECT_MASK 0x00000400L 633*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__P2_SELECT_MASK 0x00000800L 634*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__WRITE_MASK 0x00001000L 635*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__READ_MASK 0x00002000L 636*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__SRBM_OVERRIDE_MASK 0x08000000L 637*b843c749SSergey Zigachev #define SDMA_PGFSM_CONFIG__REG_ADDR_MASK 0xF0000000L 638*b843c749SSergey Zigachev //SDMA_PGFSM_WRITE 639*b843c749SSergey Zigachev #define SDMA_PGFSM_WRITE__VALUE__SHIFT 0x0 640*b843c749SSergey Zigachev #define SDMA_PGFSM_WRITE__VALUE_MASK 0xFFFFFFFFL 641*b843c749SSergey Zigachev //SDMA_PGFSM_READ 642*b843c749SSergey Zigachev #define SDMA_PGFSM_READ__VALUE__SHIFT 0x0 643*b843c749SSergey Zigachev #define SDMA_PGFSM_READ__VALUE_MASK 0x00FFFFFFL 644*b843c749SSergey Zigachev //SDMA0_EDC_CONFIG 645*b843c749SSergey Zigachev #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 646*b843c749SSergey Zigachev #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE__SHIFT 0x2 647*b843c749SSergey Zigachev #define SDMA0_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 648*b843c749SSergey Zigachev #define SDMA0_EDC_CONFIG__ECC_INT_ENABLE_MASK 0x00000004L 649*b843c749SSergey Zigachev //SDMA0_BA_THRESHOLD 650*b843c749SSergey Zigachev #define SDMA0_BA_THRESHOLD__READ_THRES__SHIFT 0x0 651*b843c749SSergey Zigachev #define SDMA0_BA_THRESHOLD__WRITE_THRES__SHIFT 0x10 652*b843c749SSergey Zigachev #define SDMA0_BA_THRESHOLD__READ_THRES_MASK 0x000003FFL 653*b843c749SSergey Zigachev #define SDMA0_BA_THRESHOLD__WRITE_THRES_MASK 0x03FF0000L 654*b843c749SSergey Zigachev //SDMA0_ID 655*b843c749SSergey Zigachev #define SDMA0_ID__DEVICE_ID__SHIFT 0x0 656*b843c749SSergey Zigachev #define SDMA0_ID__DEVICE_ID_MASK 0x000000FFL 657*b843c749SSergey Zigachev //SDMA0_VERSION 658*b843c749SSergey Zigachev #define SDMA0_VERSION__MINVER__SHIFT 0x0 659*b843c749SSergey Zigachev #define SDMA0_VERSION__MAJVER__SHIFT 0x8 660*b843c749SSergey Zigachev #define SDMA0_VERSION__REV__SHIFT 0x10 661*b843c749SSergey Zigachev #define SDMA0_VERSION__MINVER_MASK 0x0000007FL 662*b843c749SSergey Zigachev #define SDMA0_VERSION__MAJVER_MASK 0x00007F00L 663*b843c749SSergey Zigachev #define SDMA0_VERSION__REV_MASK 0x003F0000L 664*b843c749SSergey Zigachev //SDMA0_EDC_COUNTER 665*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED__SHIFT 0x0 666*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC__SHIFT 0x1 667*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED__SHIFT 0x2 668*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED__SHIFT 0x3 669*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED__SHIFT 0x4 670*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED__SHIFT 0x5 671*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED__SHIFT 0x6 672*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED__SHIFT 0x7 673*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED__SHIFT 0x8 674*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED__SHIFT 0x9 675*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT 0xa 676*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED__SHIFT 0xb 677*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xc 678*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED__SHIFT 0xd 679*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED__SHIFT 0xe 680*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED__SHIFT 0xf 681*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED__SHIFT 0x10 682*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_DED_MASK 0x00000001L 683*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UCODE_BUF_SEC_MASK 0x00000002L 684*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_RB_CMD_BUF_SED_MASK 0x00000004L 685*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_IB_CMD_BUF_SED_MASK 0x00000008L 686*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RD_FIFO_SED_MASK 0x00000010L 687*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_UTCL1_RDBST_FIFO_SED_MASK 0x00000020L 688*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_DATA_LUT_FIFO_SED_MASK 0x00000040L 689*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF0_SED_MASK 0x00000080L 690*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF1_SED_MASK 0x00000100L 691*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF2_SED_MASK 0x00000200L 692*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED_MASK 0x00000400L 693*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF4_SED_MASK 0x00000800L 694*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED_MASK 0x00001000L 695*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF6_SED_MASK 0x00002000L 696*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF7_SED_MASK 0x00004000L 697*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_SPLIT_DAT_BUF_SED_MASK 0x00008000L 698*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER__SDMA_MC_WR_ADDR_FIFO_SED_MASK 0x00010000L 699*b843c749SSergey Zigachev //SDMA0_EDC_COUNTER_CLEAR 700*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER_CLEAR__DUMMY__SHIFT 0x0 701*b843c749SSergey Zigachev #define SDMA0_EDC_COUNTER_CLEAR__DUMMY_MASK 0x00000001L 702*b843c749SSergey Zigachev //SDMA0_STATUS2_REG 703*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__ID__SHIFT 0x0 704*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__F32_INSTR_PTR__SHIFT 0x2 705*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__CMD_OP__SHIFT 0x10 706*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__ID_MASK 0x00000003L 707*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__F32_INSTR_PTR_MASK 0x00000FFCL 708*b843c749SSergey Zigachev #define SDMA0_STATUS2_REG__CMD_OP_MASK 0xFFFF0000L 709*b843c749SSergey Zigachev //SDMA0_ATOMIC_CNTL 710*b843c749SSergey Zigachev #define SDMA0_ATOMIC_CNTL__LOOP_TIMER__SHIFT 0x0 711*b843c749SSergey Zigachev #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE__SHIFT 0x1f 712*b843c749SSergey Zigachev #define SDMA0_ATOMIC_CNTL__LOOP_TIMER_MASK 0x7FFFFFFFL 713*b843c749SSergey Zigachev #define SDMA0_ATOMIC_CNTL__ATOMIC_RTN_INT_ENABLE_MASK 0x80000000L 714*b843c749SSergey Zigachev //SDMA0_ATOMIC_PREOP_LO 715*b843c749SSergey Zigachev #define SDMA0_ATOMIC_PREOP_LO__DATA__SHIFT 0x0 716*b843c749SSergey Zigachev #define SDMA0_ATOMIC_PREOP_LO__DATA_MASK 0xFFFFFFFFL 717*b843c749SSergey Zigachev //SDMA0_ATOMIC_PREOP_HI 718*b843c749SSergey Zigachev #define SDMA0_ATOMIC_PREOP_HI__DATA__SHIFT 0x0 719*b843c749SSergey Zigachev #define SDMA0_ATOMIC_PREOP_HI__DATA_MASK 0xFFFFFFFFL 720*b843c749SSergey Zigachev //SDMA0_UTCL1_CNTL 721*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_ENABLE__SHIFT 0x0 722*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_DELAY__SHIFT 0x1 723*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_WATERMK__SHIFT 0xb 724*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__INVACK_DELAY__SHIFT 0xe 725*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REQL2_CREDIT__SHIFT 0x18 726*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__VADDR_WATERMK__SHIFT 0x1d 727*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_ENABLE_MASK 0x00000001L 728*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_DELAY_MASK 0x000007FEL 729*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REDO_WATERMK_MASK 0x00003800L 730*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__INVACK_DELAY_MASK 0x00FFC000L 731*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__REQL2_CREDIT_MASK 0x1F000000L 732*b843c749SSergey Zigachev #define SDMA0_UTCL1_CNTL__VADDR_WATERMK_MASK 0xE0000000L 733*b843c749SSergey Zigachev //SDMA0_UTCL1_WATERMK 734*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK__SHIFT 0x0 735*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK__SHIFT 0xa 736*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK__SHIFT 0x12 737*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK__SHIFT 0x1a 738*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__REQMC_WATERMK_MASK 0x000003FFL 739*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__REQPG_WATERMK_MASK 0x0003FC00L 740*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__INVREQ_WATERMK_MASK 0x03FC0000L 741*b843c749SSergey Zigachev #define SDMA0_UTCL1_WATERMK__XNACK_WATERMK_MASK 0xFC000000L 742*b843c749SSergey Zigachev //SDMA0_UTCL1_RD_STATUS 743*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 744*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 745*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 746*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 747*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 748*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 749*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 750*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 751*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 752*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 753*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 754*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 755*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 756*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 757*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 758*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 759*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 760*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 761*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT__SHIFT 0x12 762*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL__SHIFT 0x13 763*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE__SHIFT 0x14 764*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL__SHIFT 0x15 765*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR__SHIFT 0x16 766*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE__SHIFT 0x1a 767*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR__SHIFT 0x1d 768*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING__SHIFT 0x1e 769*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE__SHIFT 0x1f 770*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 771*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 772*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 773*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 774*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 775*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 776*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 777*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 778*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 779*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 780*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 781*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 782*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 783*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 784*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 785*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 786*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 787*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 788*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__PAGE_FAULT_MASK 0x00040000L 789*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__PAGE_NULL_MASK 0x00080000L 790*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__REQL2_IDLE_MASK 0x00100000L 791*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__CE_L1_STALL_MASK 0x00200000L 792*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__NEXT_RD_VECTOR_MASK 0x03C00000L 793*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__MERGE_STATE_MASK 0x1C000000L 794*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__ADDR_RD_RTR_MASK 0x20000000L 795*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__WPTR_POLLING_MASK 0x40000000L 796*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_STATUS__INVREQ_SIZE_MASK 0x80000000L 797*b843c749SSergey Zigachev //SDMA0_UTCL1_WR_STATUS 798*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY__SHIFT 0x0 799*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY__SHIFT 0x1 800*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY__SHIFT 0x2 801*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY__SHIFT 0x3 802*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY__SHIFT 0x4 803*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY__SHIFT 0x5 804*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY__SHIFT 0x6 805*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY__SHIFT 0x7 806*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY__SHIFT 0x8 807*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL__SHIFT 0x9 808*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL__SHIFT 0xa 809*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL__SHIFT 0xb 810*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL__SHIFT 0xc 811*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL__SHIFT 0xd 812*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL__SHIFT 0xe 813*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL__SHIFT 0xf 814*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL__SHIFT 0x10 815*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL__SHIFT 0x11 816*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT__SHIFT 0x12 817*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL__SHIFT 0x13 818*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE__SHIFT 0x14 819*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR__SHIFT 0x15 820*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR__SHIFT 0x16 821*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE__SHIFT 0x19 822*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY__SHIFT 0x1c 823*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL__SHIFT 0x1d 824*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY__SHIFT 0x1e 825*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL__SHIFT 0x1f 826*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_EMPTY_MASK 0x00000001L 827*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_EMPTY_MASK 0x00000002L 828*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_EMPTY_MASK 0x00000004L 829*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_EMPTY_MASK 0x00000008L 830*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_EMPTY_MASK 0x00000010L 831*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_EMPTY_MASK 0x00000020L 832*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_EMPTY_MASK 0x00000040L 833*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_EMPTY_MASK 0x00000080L 834*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_EMPTY_MASK 0x00000100L 835*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_RET_ADDR_FIFO_FULL_MASK 0x00000200L 836*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQMC_REQ_FIFO_FULL_MASK 0x00000400L 837*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_RET_BUF_FULL_MASK 0x00000800L 838*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RTPG_VADDR_FIFO_FULL_MASK 0x00001000L 839*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_HEAD_VIRT_FIFO_FULL_MASK 0x00002000L 840*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REDO_FIFO_FULL_MASK 0x00004000L 841*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_REQPAGE_FIFO_FULL_MASK 0x00008000L 842*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_XNACK_FIFO_FULL_MASK 0x00010000L 843*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RQPG_INVREQ_FIFO_FULL_MASK 0x00020000L 844*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__PAGE_FAULT_MASK 0x00040000L 845*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__PAGE_NULL_MASK 0x00080000L 846*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__REQL2_IDLE_MASK 0x00100000L 847*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__F32_WR_RTR_MASK 0x00200000L 848*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__NEXT_WR_VECTOR_MASK 0x01C00000L 849*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__MERGE_STATE_MASK 0x0E000000L 850*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_EMPTY_MASK 0x10000000L 851*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__RPTR_DATA_FIFO_FULL_MASK 0x20000000L 852*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_EMPTY_MASK 0x40000000L 853*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_STATUS__WRREQ_DATA_FIFO_FULL_MASK 0x80000000L 854*b843c749SSergey Zigachev //SDMA0_UTCL1_INV0 855*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_MIDDLE__SHIFT 0x0 856*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__RD_TIMEOUT__SHIFT 0x1 857*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__WR_TIMEOUT__SHIFT 0x2 858*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__RD_IN_INVADR__SHIFT 0x3 859*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__WR_IN_INVADR__SHIFT 0x4 860*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__PAGE_NULL_SW__SHIFT 0x5 861*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR__SHIFT 0x6 862*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INVREQ_ENABLE__SHIFT 0x7 863*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW__SHIFT 0x8 864*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE__SHIFT 0x9 865*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE__SHIFT 0xa 866*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE__SHIFT 0xb 867*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_VMID_VEC__SHIFT 0xc 868*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_ADDR_HI__SHIFT 0x1c 869*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_MIDDLE_MASK 0x00000001L 870*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__RD_TIMEOUT_MASK 0x00000002L 871*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__WR_TIMEOUT_MASK 0x00000004L 872*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__RD_IN_INVADR_MASK 0x00000008L 873*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__WR_IN_INVADR_MASK 0x00000010L 874*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__PAGE_NULL_SW_MASK 0x00000020L 875*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__XNACK_IS_INVADR_MASK 0x00000040L 876*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INVREQ_ENABLE_MASK 0x00000080L 877*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__NACK_TIMEOUT_SW_MASK 0x00000100L 878*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__NFLUSH_INV_IDLE_MASK 0x00000200L 879*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__FLUSH_INV_IDLE_MASK 0x00000400L 880*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_FLUSHTYPE_MASK 0x00000800L 881*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_VMID_VEC_MASK 0x0FFFF000L 882*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV0__INV_ADDR_HI_MASK 0xF0000000L 883*b843c749SSergey Zigachev //SDMA0_UTCL1_INV1 884*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV1__INV_ADDR_LO__SHIFT 0x0 885*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV1__INV_ADDR_LO_MASK 0xFFFFFFFFL 886*b843c749SSergey Zigachev //SDMA0_UTCL1_INV2 887*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC__SHIFT 0x0 888*b843c749SSergey Zigachev #define SDMA0_UTCL1_INV2__INV_NFLUSH_VMID_VEC_MASK 0xFFFFFFFFL 889*b843c749SSergey Zigachev //SDMA0_UTCL1_RD_XNACK0 890*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 891*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 892*b843c749SSergey Zigachev //SDMA0_UTCL1_RD_XNACK1 893*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 894*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID__SHIFT 0x4 895*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR__SHIFT 0x8 896*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK__SHIFT 0x1a 897*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 898*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_VMID_MASK 0x000000F0L 899*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 900*b843c749SSergey Zigachev #define SDMA0_UTCL1_RD_XNACK1__IS_XNACK_MASK 0x0C000000L 901*b843c749SSergey Zigachev //SDMA0_UTCL1_WR_XNACK0 902*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO__SHIFT 0x0 903*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK0__XNACK_ADDR_LO_MASK 0xFFFFFFFFL 904*b843c749SSergey Zigachev //SDMA0_UTCL1_WR_XNACK1 905*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI__SHIFT 0x0 906*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID__SHIFT 0x4 907*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR__SHIFT 0x8 908*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK__SHIFT 0x1a 909*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_ADDR_HI_MASK 0x0000000FL 910*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_VMID_MASK 0x000000F0L 911*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__XNACK_VECTOR_MASK 0x03FFFF00L 912*b843c749SSergey Zigachev #define SDMA0_UTCL1_WR_XNACK1__IS_XNACK_MASK 0x0C000000L 913*b843c749SSergey Zigachev //SDMA0_UTCL1_TIMEOUT 914*b843c749SSergey Zigachev #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT__SHIFT 0x0 915*b843c749SSergey Zigachev #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT__SHIFT 0x10 916*b843c749SSergey Zigachev #define SDMA0_UTCL1_TIMEOUT__RD_XNACK_LIMIT_MASK 0x0000FFFFL 917*b843c749SSergey Zigachev #define SDMA0_UTCL1_TIMEOUT__WR_XNACK_LIMIT_MASK 0xFFFF0000L 918*b843c749SSergey Zigachev //SDMA0_UTCL1_PAGE 919*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__VM_HOLE__SHIFT 0x0 920*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__REQ_TYPE__SHIFT 0x1 921*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__USE_MTYPE__SHIFT 0x6 922*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP__SHIFT 0x9 923*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__VM_HOLE_MASK 0x00000001L 924*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__REQ_TYPE_MASK 0x0000001EL 925*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__USE_MTYPE_MASK 0x000001C0L 926*b843c749SSergey Zigachev #define SDMA0_UTCL1_PAGE__USE_PT_SNOOP_MASK 0x00000200L 927*b843c749SSergey Zigachev //SDMA0_POWER_CNTL_IDLE 928*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY0__SHIFT 0x0 929*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY1__SHIFT 0x10 930*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY2__SHIFT 0x18 931*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY0_MASK 0x0000FFFFL 932*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY1_MASK 0x00FF0000L 933*b843c749SSergey Zigachev #define SDMA0_POWER_CNTL_IDLE__DELAY2_MASK 0xFF000000L 934*b843c749SSergey Zigachev //SDMA0_RELAX_ORDERING_LUT 935*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED0__SHIFT 0x0 936*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__COPY__SHIFT 0x1 937*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WRITE__SHIFT 0x2 938*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED3__SHIFT 0x3 939*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED4__SHIFT 0x4 940*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__FENCE__SHIFT 0x5 941*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED76__SHIFT 0x6 942*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM__SHIFT 0x8 943*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__COND_EXE__SHIFT 0x9 944*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__ATOMIC__SHIFT 0xa 945*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL__SHIFT 0xb 946*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__PTEPDE__SHIFT 0xc 947*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP__SHIFT 0xd 948*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED__SHIFT 0xe 949*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH__SHIFT 0x1b 950*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB__SHIFT 0x1c 951*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL__SHIFT 0x1d 952*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH__SHIFT 0x1e 953*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH__SHIFT 0x1f 954*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED0_MASK 0x00000001L 955*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__COPY_MASK 0x00000002L 956*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WRITE_MASK 0x00000004L 957*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED3_MASK 0x00000008L 958*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED4_MASK 0x00000010L 959*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__FENCE_MASK 0x00000020L 960*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED76_MASK 0x000000C0L 961*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__POLL_MEM_MASK 0x00000100L 962*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__COND_EXE_MASK 0x00000200L 963*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__ATOMIC_MASK 0x00000400L 964*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__CONST_FILL_MASK 0x00000800L 965*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__PTEPDE_MASK 0x00001000L 966*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__TIMESTAMP_MASK 0x00002000L 967*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RESERVED_MASK 0x07FFC000L 968*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WORLD_SWITCH_MASK 0x08000000L 969*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RPTR_WRB_MASK 0x10000000L 970*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__WPTR_POLL_MASK 0x20000000L 971*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__IB_FETCH_MASK 0x40000000L 972*b843c749SSergey Zigachev #define SDMA0_RELAX_ORDERING_LUT__RB_FETCH_MASK 0x80000000L 973*b843c749SSergey Zigachev //SDMA0_CHICKEN_BITS_2 974*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY__SHIFT 0x0 975*b843c749SSergey Zigachev #define SDMA0_CHICKEN_BITS_2__F32_CMD_PROC_DELAY_MASK 0x0000000FL 976*b843c749SSergey Zigachev //SDMA0_STATUS3_REG 977*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__CMD_OP_STATUS__SHIFT 0x0 978*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__PREV_VM_CMD__SHIFT 0x10 979*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__EXCEPTION_IDLE__SHIFT 0x14 980*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__CMD_OP_STATUS_MASK 0x0000FFFFL 981*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__PREV_VM_CMD_MASK 0x000F0000L 982*b843c749SSergey Zigachev #define SDMA0_STATUS3_REG__EXCEPTION_IDLE_MASK 0x00100000L 983*b843c749SSergey Zigachev //SDMA0_PHYSICAL_ADDR_LO 984*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__D_VALID__SHIFT 0x0 985*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__DIRTY__SHIFT 0x1 986*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID__SHIFT 0x2 987*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__ADDR__SHIFT 0xc 988*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__D_VALID_MASK 0x00000001L 989*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__DIRTY_MASK 0x00000002L 990*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__PHY_VALID_MASK 0x00000004L 991*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_LO__ADDR_MASK 0xFFFFF000L 992*b843c749SSergey Zigachev //SDMA0_PHYSICAL_ADDR_HI 993*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_HI__ADDR__SHIFT 0x0 994*b843c749SSergey Zigachev #define SDMA0_PHYSICAL_ADDR_HI__ADDR_MASK 0x0000FFFFL 995*b843c749SSergey Zigachev //SDMA0_ERROR_LOG 996*b843c749SSergey Zigachev #define SDMA0_ERROR_LOG__OVERRIDE__SHIFT 0x0 997*b843c749SSergey Zigachev #define SDMA0_ERROR_LOG__STATUS__SHIFT 0x10 998*b843c749SSergey Zigachev #define SDMA0_ERROR_LOG__OVERRIDE_MASK 0x0000FFFFL 999*b843c749SSergey Zigachev #define SDMA0_ERROR_LOG__STATUS_MASK 0xFFFF0000L 1000*b843c749SSergey Zigachev //SDMA0_PUB_DUMMY_REG0 1001*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG0__VALUE__SHIFT 0x0 1002*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG0__VALUE_MASK 0xFFFFFFFFL 1003*b843c749SSergey Zigachev //SDMA0_PUB_DUMMY_REG1 1004*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG1__VALUE__SHIFT 0x0 1005*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG1__VALUE_MASK 0xFFFFFFFFL 1006*b843c749SSergey Zigachev //SDMA0_PUB_DUMMY_REG2 1007*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG2__VALUE__SHIFT 0x0 1008*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG2__VALUE_MASK 0xFFFFFFFFL 1009*b843c749SSergey Zigachev //SDMA0_PUB_DUMMY_REG3 1010*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG3__VALUE__SHIFT 0x0 1011*b843c749SSergey Zigachev #define SDMA0_PUB_DUMMY_REG3__VALUE_MASK 0xFFFFFFFFL 1012*b843c749SSergey Zigachev //SDMA0_F32_COUNTER 1013*b843c749SSergey Zigachev #define SDMA0_F32_COUNTER__VALUE__SHIFT 0x0 1014*b843c749SSergey Zigachev #define SDMA0_F32_COUNTER__VALUE_MASK 0xFFFFFFFFL 1015*b843c749SSergey Zigachev //SDMA0_UNBREAKABLE 1016*b843c749SSergey Zigachev #define SDMA0_UNBREAKABLE__VALUE__SHIFT 0x0 1017*b843c749SSergey Zigachev #define SDMA0_UNBREAKABLE__VALUE_MASK 0x00000001L 1018*b843c749SSergey Zigachev //SDMA0_PERFMON_CNTL 1019*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_ENABLE0__SHIFT 0x0 1020*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_CLEAR0__SHIFT 0x1 1021*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_SEL0__SHIFT 0x2 1022*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_ENABLE1__SHIFT 0xa 1023*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_CLEAR1__SHIFT 0xb 1024*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_SEL1__SHIFT 0xc 1025*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_ENABLE0_MASK 0x00000001L 1026*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_CLEAR0_MASK 0x00000002L 1027*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_SEL0_MASK 0x000003FCL 1028*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_ENABLE1_MASK 0x00000400L 1029*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_CLEAR1_MASK 0x00000800L 1030*b843c749SSergey Zigachev #define SDMA0_PERFMON_CNTL__PERF_SEL1_MASK 0x000FF000L 1031*b843c749SSergey Zigachev //SDMA0_PERFCOUNTER0_RESULT 1032*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT__SHIFT 0x0 1033*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER0_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1034*b843c749SSergey Zigachev //SDMA0_PERFCOUNTER1_RESULT 1035*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT__SHIFT 0x0 1036*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER1_RESULT__PERF_COUNT_MASK 0xFFFFFFFFL 1037*b843c749SSergey Zigachev //SDMA0_PERFCOUNTER_TAG_DELAY_RANGE 1038*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW__SHIFT 0x0 1039*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH__SHIFT 0xe 1040*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW__SHIFT 0x1c 1041*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_LOW_MASK 0x00003FFFL 1042*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__RANGE_HIGH_MASK 0x0FFFC000L 1043*b843c749SSergey Zigachev #define SDMA0_PERFCOUNTER_TAG_DELAY_RANGE__SELECT_RW_MASK 0x10000000L 1044*b843c749SSergey Zigachev //SDMA0_CRD_CNTL 1045*b843c749SSergey Zigachev #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT__SHIFT 0x7 1046*b843c749SSergey Zigachev #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT__SHIFT 0xd 1047*b843c749SSergey Zigachev #define SDMA0_CRD_CNTL__MC_WRREQ_CREDIT_MASK 0x00001F80L 1048*b843c749SSergey Zigachev #define SDMA0_CRD_CNTL__MC_RDREQ_CREDIT_MASK 0x0007E000L 1049*b843c749SSergey Zigachev //SDMA0_MMHUB_TRUSTLVL 1050*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0__SHIFT 0x0 1051*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1__SHIFT 0x3 1052*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2__SHIFT 0x6 1053*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3__SHIFT 0x9 1054*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4__SHIFT 0xc 1055*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5__SHIFT 0xf 1056*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6__SHIFT 0x12 1057*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7__SHIFT 0x15 1058*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG0_MASK 0x00000007L 1059*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG1_MASK 0x00000038L 1060*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG2_MASK 0x000001C0L 1061*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG3_MASK 0x00000E00L 1062*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG4_MASK 0x00007000L 1063*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG5_MASK 0x00038000L 1064*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG6_MASK 0x001C0000L 1065*b843c749SSergey Zigachev #define SDMA0_MMHUB_TRUSTLVL__SECFLAG7_MASK 0x00E00000L 1066*b843c749SSergey Zigachev //SDMA0_GPU_IOV_VIOLATION_LOG 1067*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS__SHIFT 0x0 1068*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS__SHIFT 0x1 1069*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS__SHIFT 0x2 1070*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION__SHIFT 0x12 1071*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VF__SHIFT 0x13 1072*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID__SHIFT 0x14 1073*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID__SHIFT 0x18 1074*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VIOLATION_STATUS_MASK 0x00000001L 1075*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__MULTIPLE_VIOLATION_STATUS_MASK 0x00000002L 1076*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__ADDRESS_MASK 0x0003FFFCL 1077*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__WRITE_OPERATION_MASK 0x00040000L 1078*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VF_MASK 0x00080000L 1079*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__VFID_MASK 0x00F00000L 1080*b843c749SSergey Zigachev #define SDMA0_GPU_IOV_VIOLATION_LOG__INITIATOR_ID_MASK 0xFF000000L 1081*b843c749SSergey Zigachev //SDMA0_ULV_CNTL 1082*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__HYSTERESIS__SHIFT 0x0 1083*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__ENTER_ULV_INT__SHIFT 0x1d 1084*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__EXIT_ULV_INT__SHIFT 0x1e 1085*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__ULV_STATUS__SHIFT 0x1f 1086*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__HYSTERESIS_MASK 0x0000001FL 1087*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__ENTER_ULV_INT_MASK 0x20000000L 1088*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__EXIT_ULV_INT_MASK 0x40000000L 1089*b843c749SSergey Zigachev #define SDMA0_ULV_CNTL__ULV_STATUS_MASK 0x80000000L 1090*b843c749SSergey Zigachev //SDMA0_EA_DBIT_ADDR_DATA 1091*b843c749SSergey Zigachev #define SDMA0_EA_DBIT_ADDR_DATA__VALUE__SHIFT 0x0 1092*b843c749SSergey Zigachev #define SDMA0_EA_DBIT_ADDR_DATA__VALUE_MASK 0xFFFFFFFFL 1093*b843c749SSergey Zigachev //SDMA0_EA_DBIT_ADDR_INDEX 1094*b843c749SSergey Zigachev #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE__SHIFT 0x0 1095*b843c749SSergey Zigachev #define SDMA0_EA_DBIT_ADDR_INDEX__VALUE_MASK 0x00000007L 1096*b843c749SSergey Zigachev //SDMA0_GFX_RB_CNTL 1097*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_ENABLE__SHIFT 0x0 1098*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_SIZE__SHIFT 0x1 1099*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1100*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1101*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1102*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1103*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_PRIV__SHIFT 0x17 1104*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_VMID__SHIFT 0x18 1105*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1106*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1107*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1108*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1109*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1110*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1111*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_PRIV_MASK 0x00800000L 1112*b843c749SSergey Zigachev #define SDMA0_GFX_RB_CNTL__RB_VMID_MASK 0x0F000000L 1113*b843c749SSergey Zigachev //SDMA0_GFX_RB_BASE 1114*b843c749SSergey Zigachev #define SDMA0_GFX_RB_BASE__ADDR__SHIFT 0x0 1115*b843c749SSergey Zigachev #define SDMA0_GFX_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1116*b843c749SSergey Zigachev //SDMA0_GFX_RB_BASE_HI 1117*b843c749SSergey Zigachev #define SDMA0_GFX_RB_BASE_HI__ADDR__SHIFT 0x0 1118*b843c749SSergey Zigachev #define SDMA0_GFX_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1119*b843c749SSergey Zigachev //SDMA0_GFX_RB_RPTR 1120*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR__OFFSET__SHIFT 0x0 1121*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1122*b843c749SSergey Zigachev //SDMA0_GFX_RB_RPTR_HI 1123*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_HI__OFFSET__SHIFT 0x0 1124*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1125*b843c749SSergey Zigachev //SDMA0_GFX_RB_WPTR 1126*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR__OFFSET__SHIFT 0x0 1127*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1128*b843c749SSergey Zigachev //SDMA0_GFX_RB_WPTR_HI 1129*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_HI__OFFSET__SHIFT 0x0 1130*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1131*b843c749SSergey Zigachev //SDMA0_GFX_RB_WPTR_POLL_CNTL 1132*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1133*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1134*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1135*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1136*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1137*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1138*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1139*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1140*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1141*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1142*b843c749SSergey Zigachev //SDMA0_GFX_RB_RPTR_ADDR_HI 1143*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1144*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1145*b843c749SSergey Zigachev //SDMA0_GFX_RB_RPTR_ADDR_LO 1146*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1147*b843c749SSergey Zigachev #define SDMA0_GFX_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1148*b843c749SSergey Zigachev //SDMA0_GFX_IB_CNTL 1149*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__IB_ENABLE__SHIFT 0x0 1150*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1151*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1152*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__CMD_VMID__SHIFT 0x10 1153*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1154*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1155*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1156*b843c749SSergey Zigachev #define SDMA0_GFX_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1157*b843c749SSergey Zigachev //SDMA0_GFX_IB_RPTR 1158*b843c749SSergey Zigachev #define SDMA0_GFX_IB_RPTR__OFFSET__SHIFT 0x2 1159*b843c749SSergey Zigachev #define SDMA0_GFX_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1160*b843c749SSergey Zigachev //SDMA0_GFX_IB_OFFSET 1161*b843c749SSergey Zigachev #define SDMA0_GFX_IB_OFFSET__OFFSET__SHIFT 0x2 1162*b843c749SSergey Zigachev #define SDMA0_GFX_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1163*b843c749SSergey Zigachev //SDMA0_GFX_IB_BASE_LO 1164*b843c749SSergey Zigachev #define SDMA0_GFX_IB_BASE_LO__ADDR__SHIFT 0x5 1165*b843c749SSergey Zigachev #define SDMA0_GFX_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1166*b843c749SSergey Zigachev //SDMA0_GFX_IB_BASE_HI 1167*b843c749SSergey Zigachev #define SDMA0_GFX_IB_BASE_HI__ADDR__SHIFT 0x0 1168*b843c749SSergey Zigachev #define SDMA0_GFX_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1169*b843c749SSergey Zigachev //SDMA0_GFX_IB_SIZE 1170*b843c749SSergey Zigachev #define SDMA0_GFX_IB_SIZE__SIZE__SHIFT 0x0 1171*b843c749SSergey Zigachev #define SDMA0_GFX_IB_SIZE__SIZE_MASK 0x000FFFFFL 1172*b843c749SSergey Zigachev //SDMA0_GFX_SKIP_CNTL 1173*b843c749SSergey Zigachev #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1174*b843c749SSergey Zigachev #define SDMA0_GFX_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1175*b843c749SSergey Zigachev //SDMA0_GFX_CONTEXT_STATUS 1176*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1177*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__IDLE__SHIFT 0x2 1178*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1179*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1180*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1181*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1182*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1183*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1184*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1185*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1186*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1187*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1188*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1189*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1190*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1191*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1192*b843c749SSergey Zigachev //SDMA0_GFX_DOORBELL 1193*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL__ENABLE__SHIFT 0x1c 1194*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL__CAPTURED__SHIFT 0x1e 1195*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL__ENABLE_MASK 0x10000000L 1196*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL__CAPTURED_MASK 0x40000000L 1197*b843c749SSergey Zigachev //SDMA0_GFX_CONTEXT_CNTL 1198*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX__SHIFT 0x10 1199*b843c749SSergey Zigachev #define SDMA0_GFX_CONTEXT_CNTL__RESUME_CTX_MASK 0x00010000L 1200*b843c749SSergey Zigachev //SDMA0_GFX_STATUS 1201*b843c749SSergey Zigachev #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1202*b843c749SSergey Zigachev #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1203*b843c749SSergey Zigachev #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1204*b843c749SSergey Zigachev #define SDMA0_GFX_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1205*b843c749SSergey Zigachev //SDMA0_GFX_DOORBELL_LOG 1206*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1207*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_LOG__DATA__SHIFT 0x2 1208*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1209*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1210*b843c749SSergey Zigachev //SDMA0_GFX_WATERMARK 1211*b843c749SSergey Zigachev #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1212*b843c749SSergey Zigachev #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1213*b843c749SSergey Zigachev #define SDMA0_GFX_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1214*b843c749SSergey Zigachev #define SDMA0_GFX_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1215*b843c749SSergey Zigachev //SDMA0_GFX_DOORBELL_OFFSET 1216*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1217*b843c749SSergey Zigachev #define SDMA0_GFX_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1218*b843c749SSergey Zigachev //SDMA0_GFX_CSA_ADDR_LO 1219*b843c749SSergey Zigachev #define SDMA0_GFX_CSA_ADDR_LO__ADDR__SHIFT 0x2 1220*b843c749SSergey Zigachev #define SDMA0_GFX_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1221*b843c749SSergey Zigachev //SDMA0_GFX_CSA_ADDR_HI 1222*b843c749SSergey Zigachev #define SDMA0_GFX_CSA_ADDR_HI__ADDR__SHIFT 0x0 1223*b843c749SSergey Zigachev #define SDMA0_GFX_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1224*b843c749SSergey Zigachev //SDMA0_GFX_IB_SUB_REMAIN 1225*b843c749SSergey Zigachev #define SDMA0_GFX_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1226*b843c749SSergey Zigachev #define SDMA0_GFX_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1227*b843c749SSergey Zigachev //SDMA0_GFX_PREEMPT 1228*b843c749SSergey Zigachev #define SDMA0_GFX_PREEMPT__IB_PREEMPT__SHIFT 0x0 1229*b843c749SSergey Zigachev #define SDMA0_GFX_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1230*b843c749SSergey Zigachev //SDMA0_GFX_DUMMY_REG 1231*b843c749SSergey Zigachev #define SDMA0_GFX_DUMMY_REG__DUMMY__SHIFT 0x0 1232*b843c749SSergey Zigachev #define SDMA0_GFX_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1233*b843c749SSergey Zigachev //SDMA0_GFX_RB_WPTR_POLL_ADDR_HI 1234*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1235*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1236*b843c749SSergey Zigachev //SDMA0_GFX_RB_WPTR_POLL_ADDR_LO 1237*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1238*b843c749SSergey Zigachev #define SDMA0_GFX_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1239*b843c749SSergey Zigachev //SDMA0_GFX_RB_AQL_CNTL 1240*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1241*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1242*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1243*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1244*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1245*b843c749SSergey Zigachev #define SDMA0_GFX_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1246*b843c749SSergey Zigachev //SDMA0_GFX_MINOR_PTR_UPDATE 1247*b843c749SSergey Zigachev #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1248*b843c749SSergey Zigachev #define SDMA0_GFX_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1249*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA0 1250*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA0__DATA0__SHIFT 0x0 1251*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1252*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA1 1253*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA1__DATA1__SHIFT 0x0 1254*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1255*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA2 1256*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA2__DATA2__SHIFT 0x0 1257*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1258*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA3 1259*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA3__DATA3__SHIFT 0x0 1260*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1261*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA4 1262*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA4__DATA4__SHIFT 0x0 1263*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1264*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA5 1265*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA5__DATA5__SHIFT 0x0 1266*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1267*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA6 1268*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA6__DATA6__SHIFT 0x0 1269*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1270*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA7 1271*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA7__DATA7__SHIFT 0x0 1272*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1273*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_DATA8 1274*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA8__DATA8__SHIFT 0x0 1275*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1276*b843c749SSergey Zigachev //SDMA0_GFX_MIDCMD_CNTL 1277*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1278*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1279*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1280*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1281*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1282*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1283*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1284*b843c749SSergey Zigachev #define SDMA0_GFX_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1285*b843c749SSergey Zigachev //SDMA0_RLC0_RB_CNTL 1286*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_ENABLE__SHIFT 0x0 1287*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT 0x1 1288*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1289*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1290*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1291*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1292*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT 0x17 1293*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_VMID__SHIFT 0x18 1294*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1295*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1296*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1297*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1298*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1299*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1300*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_PRIV_MASK 0x00800000L 1301*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_CNTL__RB_VMID_MASK 0x0F000000L 1302*b843c749SSergey Zigachev //SDMA0_RLC0_RB_BASE 1303*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_BASE__ADDR__SHIFT 0x0 1304*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1305*b843c749SSergey Zigachev //SDMA0_RLC0_RB_BASE_HI 1306*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_BASE_HI__ADDR__SHIFT 0x0 1307*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1308*b843c749SSergey Zigachev //SDMA0_RLC0_RB_RPTR 1309*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR__OFFSET__SHIFT 0x0 1310*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1311*b843c749SSergey Zigachev //SDMA0_RLC0_RB_RPTR_HI 1312*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_HI__OFFSET__SHIFT 0x0 1313*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1314*b843c749SSergey Zigachev //SDMA0_RLC0_RB_WPTR 1315*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR__OFFSET__SHIFT 0x0 1316*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1317*b843c749SSergey Zigachev //SDMA0_RLC0_RB_WPTR_HI 1318*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_HI__OFFSET__SHIFT 0x0 1319*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1320*b843c749SSergey Zigachev //SDMA0_RLC0_RB_WPTR_POLL_CNTL 1321*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1322*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1323*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1324*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1325*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1326*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1327*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1328*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1329*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1330*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1331*b843c749SSergey Zigachev //SDMA0_RLC0_RB_RPTR_ADDR_HI 1332*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1333*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1334*b843c749SSergey Zigachev //SDMA0_RLC0_RB_RPTR_ADDR_LO 1335*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1336*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1337*b843c749SSergey Zigachev //SDMA0_RLC0_IB_CNTL 1338*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__IB_ENABLE__SHIFT 0x0 1339*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1340*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1341*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__CMD_VMID__SHIFT 0x10 1342*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1343*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1344*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1345*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1346*b843c749SSergey Zigachev //SDMA0_RLC0_IB_RPTR 1347*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_RPTR__OFFSET__SHIFT 0x2 1348*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1349*b843c749SSergey Zigachev //SDMA0_RLC0_IB_OFFSET 1350*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_OFFSET__OFFSET__SHIFT 0x2 1351*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1352*b843c749SSergey Zigachev //SDMA0_RLC0_IB_BASE_LO 1353*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_BASE_LO__ADDR__SHIFT 0x5 1354*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1355*b843c749SSergey Zigachev //SDMA0_RLC0_IB_BASE_HI 1356*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_BASE_HI__ADDR__SHIFT 0x0 1357*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1358*b843c749SSergey Zigachev //SDMA0_RLC0_IB_SIZE 1359*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_SIZE__SIZE__SHIFT 0x0 1360*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_SIZE__SIZE_MASK 0x000FFFFFL 1361*b843c749SSergey Zigachev //SDMA0_RLC0_SKIP_CNTL 1362*b843c749SSergey Zigachev #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1363*b843c749SSergey Zigachev #define SDMA0_RLC0_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1364*b843c749SSergey Zigachev //SDMA0_RLC0_CONTEXT_STATUS 1365*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1366*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__IDLE__SHIFT 0x2 1367*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1368*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1369*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1370*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1371*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1372*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1373*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1374*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1375*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1376*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1377*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1378*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1379*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1380*b843c749SSergey Zigachev #define SDMA0_RLC0_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1381*b843c749SSergey Zigachev //SDMA0_RLC0_DOORBELL 1382*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL__ENABLE__SHIFT 0x1c 1383*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL__CAPTURED__SHIFT 0x1e 1384*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL__ENABLE_MASK 0x10000000L 1385*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL__CAPTURED_MASK 0x40000000L 1386*b843c749SSergey Zigachev //SDMA0_RLC0_STATUS 1387*b843c749SSergey Zigachev #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1388*b843c749SSergey Zigachev #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1389*b843c749SSergey Zigachev #define SDMA0_RLC0_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1390*b843c749SSergey Zigachev #define SDMA0_RLC0_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1391*b843c749SSergey Zigachev //SDMA0_RLC0_DOORBELL_LOG 1392*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1393*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_LOG__DATA__SHIFT 0x2 1394*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1395*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1396*b843c749SSergey Zigachev //SDMA0_RLC0_WATERMARK 1397*b843c749SSergey Zigachev #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1398*b843c749SSergey Zigachev #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1399*b843c749SSergey Zigachev #define SDMA0_RLC0_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1400*b843c749SSergey Zigachev #define SDMA0_RLC0_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1401*b843c749SSergey Zigachev //SDMA0_RLC0_DOORBELL_OFFSET 1402*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1403*b843c749SSergey Zigachev #define SDMA0_RLC0_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1404*b843c749SSergey Zigachev //SDMA0_RLC0_CSA_ADDR_LO 1405*b843c749SSergey Zigachev #define SDMA0_RLC0_CSA_ADDR_LO__ADDR__SHIFT 0x2 1406*b843c749SSergey Zigachev #define SDMA0_RLC0_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1407*b843c749SSergey Zigachev //SDMA0_RLC0_CSA_ADDR_HI 1408*b843c749SSergey Zigachev #define SDMA0_RLC0_CSA_ADDR_HI__ADDR__SHIFT 0x0 1409*b843c749SSergey Zigachev #define SDMA0_RLC0_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1410*b843c749SSergey Zigachev //SDMA0_RLC0_IB_SUB_REMAIN 1411*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1412*b843c749SSergey Zigachev #define SDMA0_RLC0_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1413*b843c749SSergey Zigachev //SDMA0_RLC0_PREEMPT 1414*b843c749SSergey Zigachev #define SDMA0_RLC0_PREEMPT__IB_PREEMPT__SHIFT 0x0 1415*b843c749SSergey Zigachev #define SDMA0_RLC0_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1416*b843c749SSergey Zigachev //SDMA0_RLC0_DUMMY_REG 1417*b843c749SSergey Zigachev #define SDMA0_RLC0_DUMMY_REG__DUMMY__SHIFT 0x0 1418*b843c749SSergey Zigachev #define SDMA0_RLC0_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1419*b843c749SSergey Zigachev //SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 1420*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1421*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1422*b843c749SSergey Zigachev //SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 1423*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1424*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1425*b843c749SSergey Zigachev //SDMA0_RLC0_RB_AQL_CNTL 1426*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1427*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1428*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1429*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1430*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1431*b843c749SSergey Zigachev #define SDMA0_RLC0_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1432*b843c749SSergey Zigachev //SDMA0_RLC0_MINOR_PTR_UPDATE 1433*b843c749SSergey Zigachev #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1434*b843c749SSergey Zigachev #define SDMA0_RLC0_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1435*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA0 1436*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA0__DATA0__SHIFT 0x0 1437*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1438*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA1 1439*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA1__DATA1__SHIFT 0x0 1440*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1441*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA2 1442*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA2__DATA2__SHIFT 0x0 1443*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1444*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA3 1445*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA3__DATA3__SHIFT 0x0 1446*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1447*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA4 1448*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA4__DATA4__SHIFT 0x0 1449*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1450*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA5 1451*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA5__DATA5__SHIFT 0x0 1452*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1453*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA6 1454*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA6__DATA6__SHIFT 0x0 1455*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1456*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA7 1457*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA7__DATA7__SHIFT 0x0 1458*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1459*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_DATA8 1460*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA8__DATA8__SHIFT 0x0 1461*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1462*b843c749SSergey Zigachev //SDMA0_RLC0_MIDCMD_CNTL 1463*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1464*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1465*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1466*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1467*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1468*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1469*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1470*b843c749SSergey Zigachev #define SDMA0_RLC0_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1471*b843c749SSergey Zigachev //SDMA0_RLC1_RB_CNTL 1472*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_ENABLE__SHIFT 0x0 1473*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_SIZE__SHIFT 0x1 1474*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE__SHIFT 0x9 1475*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT 0xc 1476*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE__SHIFT 0xd 1477*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10 1478*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_PRIV__SHIFT 0x17 1479*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_VMID__SHIFT 0x18 1480*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_ENABLE_MASK 0x00000001L 1481*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_SIZE_MASK 0x0000007EL 1482*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_SWAP_ENABLE_MASK 0x00000200L 1483*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK 0x00001000L 1484*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK 0x00002000L 1485*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RPTR_WRITEBACK_TIMER_MASK 0x001F0000L 1486*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_PRIV_MASK 0x00800000L 1487*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_CNTL__RB_VMID_MASK 0x0F000000L 1488*b843c749SSergey Zigachev //SDMA0_RLC1_RB_BASE 1489*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_BASE__ADDR__SHIFT 0x0 1490*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_BASE__ADDR_MASK 0xFFFFFFFFL 1491*b843c749SSergey Zigachev //SDMA0_RLC1_RB_BASE_HI 1492*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_BASE_HI__ADDR__SHIFT 0x0 1493*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_BASE_HI__ADDR_MASK 0x00FFFFFFL 1494*b843c749SSergey Zigachev //SDMA0_RLC1_RB_RPTR 1495*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR__OFFSET__SHIFT 0x0 1496*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR__OFFSET_MASK 0xFFFFFFFFL 1497*b843c749SSergey Zigachev //SDMA0_RLC1_RB_RPTR_HI 1498*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_HI__OFFSET__SHIFT 0x0 1499*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1500*b843c749SSergey Zigachev //SDMA0_RLC1_RB_WPTR 1501*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR__OFFSET__SHIFT 0x0 1502*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR__OFFSET_MASK 0xFFFFFFFFL 1503*b843c749SSergey Zigachev //SDMA0_RLC1_RB_WPTR_HI 1504*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_HI__OFFSET__SHIFT 0x0 1505*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_HI__OFFSET_MASK 0xFFFFFFFFL 1506*b843c749SSergey Zigachev //SDMA0_RLC1_RB_WPTR_POLL_CNTL 1507*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 1508*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE__SHIFT 0x1 1509*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE__SHIFT 0x2 1510*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4 1511*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1512*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE_MASK 0x00000001L 1513*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__SWAP_ENABLE_MASK 0x00000002L 1514*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__F32_POLL_ENABLE_MASK 0x00000004L 1515*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__FREQUENCY_MASK 0x0000FFF0L 1516*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1517*b843c749SSergey Zigachev //SDMA0_RLC1_RB_RPTR_ADDR_HI 1518*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR__SHIFT 0x0 1519*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1520*b843c749SSergey Zigachev //SDMA0_RLC1_RB_RPTR_ADDR_LO 1521*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR__SHIFT 0x2 1522*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_RPTR_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1523*b843c749SSergey Zigachev //SDMA0_RLC1_IB_CNTL 1524*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__IB_ENABLE__SHIFT 0x0 1525*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE__SHIFT 0x4 1526*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB__SHIFT 0x8 1527*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__CMD_VMID__SHIFT 0x10 1528*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__IB_ENABLE_MASK 0x00000001L 1529*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__IB_SWAP_ENABLE_MASK 0x00000010L 1530*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__SWITCH_INSIDE_IB_MASK 0x00000100L 1531*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_CNTL__CMD_VMID_MASK 0x000F0000L 1532*b843c749SSergey Zigachev //SDMA0_RLC1_IB_RPTR 1533*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_RPTR__OFFSET__SHIFT 0x2 1534*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_RPTR__OFFSET_MASK 0x003FFFFCL 1535*b843c749SSergey Zigachev //SDMA0_RLC1_IB_OFFSET 1536*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_OFFSET__OFFSET__SHIFT 0x2 1537*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_OFFSET__OFFSET_MASK 0x003FFFFCL 1538*b843c749SSergey Zigachev //SDMA0_RLC1_IB_BASE_LO 1539*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_BASE_LO__ADDR__SHIFT 0x5 1540*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_BASE_LO__ADDR_MASK 0xFFFFFFE0L 1541*b843c749SSergey Zigachev //SDMA0_RLC1_IB_BASE_HI 1542*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_BASE_HI__ADDR__SHIFT 0x0 1543*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_BASE_HI__ADDR_MASK 0xFFFFFFFFL 1544*b843c749SSergey Zigachev //SDMA0_RLC1_IB_SIZE 1545*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_SIZE__SIZE__SHIFT 0x0 1546*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_SIZE__SIZE_MASK 0x000FFFFFL 1547*b843c749SSergey Zigachev //SDMA0_RLC1_SKIP_CNTL 1548*b843c749SSergey Zigachev #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT__SHIFT 0x0 1549*b843c749SSergey Zigachev #define SDMA0_RLC1_SKIP_CNTL__SKIP_COUNT_MASK 0x00003FFFL 1550*b843c749SSergey Zigachev //SDMA0_RLC1_CONTEXT_STATUS 1551*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED__SHIFT 0x0 1552*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2 1553*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED__SHIFT 0x3 1554*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION__SHIFT 0x4 1555*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE__SHIFT 0x7 1556*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY__SHIFT 0x8 1557*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED__SHIFT 0x9 1558*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE__SHIFT 0xa 1559*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__SELECTED_MASK 0x00000001L 1560*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__IDLE_MASK 0x00000004L 1561*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__EXPIRED_MASK 0x00000008L 1562*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__EXCEPTION_MASK 0x00000070L 1563*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_ABLE_MASK 0x00000080L 1564*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__CTXSW_READY_MASK 0x00000100L 1565*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPTED_MASK 0x00000200L 1566*b843c749SSergey Zigachev #define SDMA0_RLC1_CONTEXT_STATUS__PREEMPT_DISABLE_MASK 0x00000400L 1567*b843c749SSergey Zigachev //SDMA0_RLC1_DOORBELL 1568*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL__ENABLE__SHIFT 0x1c 1569*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL__CAPTURED__SHIFT 0x1e 1570*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL__ENABLE_MASK 0x10000000L 1571*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL__CAPTURED_MASK 0x40000000L 1572*b843c749SSergey Zigachev //SDMA0_RLC1_STATUS 1573*b843c749SSergey Zigachev #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 1574*b843c749SSergey Zigachev #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 0x8 1575*b843c749SSergey Zigachev #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT_MASK 0x000000FFL 1576*b843c749SSergey Zigachev #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING_MASK 0x00000100L 1577*b843c749SSergey Zigachev //SDMA0_RLC1_DOORBELL_LOG 1578*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR__SHIFT 0x0 1579*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_LOG__DATA__SHIFT 0x2 1580*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_LOG__BE_ERROR_MASK 0x00000001L 1581*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_LOG__DATA_MASK 0xFFFFFFFCL 1582*b843c749SSergey Zigachev //SDMA0_RLC1_WATERMARK 1583*b843c749SSergey Zigachev #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING__SHIFT 0x0 1584*b843c749SSergey Zigachev #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING__SHIFT 0x10 1585*b843c749SSergey Zigachev #define SDMA0_RLC1_WATERMARK__RD_OUTSTANDING_MASK 0x00000FFFL 1586*b843c749SSergey Zigachev #define SDMA0_RLC1_WATERMARK__WR_OUTSTANDING_MASK 0x03FF0000L 1587*b843c749SSergey Zigachev //SDMA0_RLC1_DOORBELL_OFFSET 1588*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET__SHIFT 0x2 1589*b843c749SSergey Zigachev #define SDMA0_RLC1_DOORBELL_OFFSET__OFFSET_MASK 0x0FFFFFFCL 1590*b843c749SSergey Zigachev //SDMA0_RLC1_CSA_ADDR_LO 1591*b843c749SSergey Zigachev #define SDMA0_RLC1_CSA_ADDR_LO__ADDR__SHIFT 0x2 1592*b843c749SSergey Zigachev #define SDMA0_RLC1_CSA_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1593*b843c749SSergey Zigachev //SDMA0_RLC1_CSA_ADDR_HI 1594*b843c749SSergey Zigachev #define SDMA0_RLC1_CSA_ADDR_HI__ADDR__SHIFT 0x0 1595*b843c749SSergey Zigachev #define SDMA0_RLC1_CSA_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1596*b843c749SSergey Zigachev //SDMA0_RLC1_IB_SUB_REMAIN 1597*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE__SHIFT 0x0 1598*b843c749SSergey Zigachev #define SDMA0_RLC1_IB_SUB_REMAIN__SIZE_MASK 0x00003FFFL 1599*b843c749SSergey Zigachev //SDMA0_RLC1_PREEMPT 1600*b843c749SSergey Zigachev #define SDMA0_RLC1_PREEMPT__IB_PREEMPT__SHIFT 0x0 1601*b843c749SSergey Zigachev #define SDMA0_RLC1_PREEMPT__IB_PREEMPT_MASK 0x00000001L 1602*b843c749SSergey Zigachev //SDMA0_RLC1_DUMMY_REG 1603*b843c749SSergey Zigachev #define SDMA0_RLC1_DUMMY_REG__DUMMY__SHIFT 0x0 1604*b843c749SSergey Zigachev #define SDMA0_RLC1_DUMMY_REG__DUMMY_MASK 0xFFFFFFFFL 1605*b843c749SSergey Zigachev //SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI 1606*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0 1607*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_HI__ADDR_MASK 0xFFFFFFFFL 1608*b843c749SSergey Zigachev //SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO 1609*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 1610*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_WPTR_POLL_ADDR_LO__ADDR_MASK 0xFFFFFFFCL 1611*b843c749SSergey Zigachev //SDMA0_RLC1_RB_AQL_CNTL 1612*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE__SHIFT 0x0 1613*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE__SHIFT 0x1 1614*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP__SHIFT 0x8 1615*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__AQL_ENABLE_MASK 0x00000001L 1616*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__AQL_PACKET_SIZE_MASK 0x000000FEL 1617*b843c749SSergey Zigachev #define SDMA0_RLC1_RB_AQL_CNTL__PACKET_STEP_MASK 0x0000FF00L 1618*b843c749SSergey Zigachev //SDMA0_RLC1_MINOR_PTR_UPDATE 1619*b843c749SSergey Zigachev #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE__SHIFT 0x0 1620*b843c749SSergey Zigachev #define SDMA0_RLC1_MINOR_PTR_UPDATE__ENABLE_MASK 0x00000001L 1621*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA0 1622*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA0__DATA0__SHIFT 0x0 1623*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA0__DATA0_MASK 0xFFFFFFFFL 1624*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA1 1625*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA1__DATA1__SHIFT 0x0 1626*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA1__DATA1_MASK 0xFFFFFFFFL 1627*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA2 1628*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA2__DATA2__SHIFT 0x0 1629*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA2__DATA2_MASK 0xFFFFFFFFL 1630*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA3 1631*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA3__DATA3__SHIFT 0x0 1632*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA3__DATA3_MASK 0xFFFFFFFFL 1633*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA4 1634*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA4__DATA4__SHIFT 0x0 1635*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA4__DATA4_MASK 0xFFFFFFFFL 1636*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA5 1637*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA5__DATA5__SHIFT 0x0 1638*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA5__DATA5_MASK 0xFFFFFFFFL 1639*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA6 1640*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA6__DATA6__SHIFT 0x0 1641*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA6__DATA6_MASK 0xFFFFFFFFL 1642*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA7 1643*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA7__DATA7__SHIFT 0x0 1644*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA7__DATA7_MASK 0xFFFFFFFFL 1645*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_DATA8 1646*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA8__DATA8__SHIFT 0x0 1647*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_DATA8__DATA8_MASK 0xFFFFFFFFL 1648*b843c749SSergey Zigachev //SDMA0_RLC1_MIDCMD_CNTL 1649*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID__SHIFT 0x0 1650*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE__SHIFT 0x1 1651*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 1652*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT__SHIFT 0x8 1653*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__DATA_VALID_MASK 0x00000001L 1654*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__COPY_MODE_MASK 0x00000002L 1655*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__SPLIT_STATE_MASK 0x000000F0L 1656*b843c749SSergey Zigachev #define SDMA0_RLC1_MIDCMD_CNTL__ALLOW_PREEMPT_MASK 0x00000100L 1657*b843c749SSergey Zigachev 1658*b843c749SSergey Zigachev #endif 1659