1*c59a5c48SFrançois Tigeot /* 2*c59a5c48SFrançois Tigeot * UVD_4_2 Register documentation 3*c59a5c48SFrançois Tigeot * 4*c59a5c48SFrançois Tigeot * Copyright (C) 2014 Advanced Micro Devices, Inc. 5*c59a5c48SFrançois Tigeot * 6*c59a5c48SFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 7*c59a5c48SFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 8*c59a5c48SFrançois Tigeot * to deal in the Software without restriction, including without limitation 9*c59a5c48SFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*c59a5c48SFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 11*c59a5c48SFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 12*c59a5c48SFrançois Tigeot * 13*c59a5c48SFrançois Tigeot * The above copyright notice and this permission notice shall be included 14*c59a5c48SFrançois Tigeot * in all copies or substantial portions of the Software. 15*c59a5c48SFrançois Tigeot * 16*c59a5c48SFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17*c59a5c48SFrançois Tigeot * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*c59a5c48SFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*c59a5c48SFrançois Tigeot * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20*c59a5c48SFrançois Tigeot * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21*c59a5c48SFrançois Tigeot * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22*c59a5c48SFrançois Tigeot */ 23*c59a5c48SFrançois Tigeot 24*c59a5c48SFrançois Tigeot #ifndef UVD_4_2_SH_MASK_H 25*c59a5c48SFrançois Tigeot #define UVD_4_2_SH_MASK_H 26*c59a5c48SFrançois Tigeot 27*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__MODE_MASK 0x40 36*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__MODE__SHIFT 0x6 37*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_MASK 0xf00 40*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID__SHIFT 0x8 41*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 110*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 111*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 112*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 113*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 114*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 115*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 116*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 117*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 118*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 119*c59a5c48SFrançois Tigeot #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 120*c59a5c48SFrançois Tigeot #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 121*c59a5c48SFrançois Tigeot #define UVD_CTX_DATA__DATA_MASK 0xffffffff 122*c59a5c48SFrançois Tigeot #define UVD_CTX_DATA__DATA__SHIFT 0x0 123*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SYS_MASK 0x1 124*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SYS__SHIFT 0x0 125*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MASK 0x2 126*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC__SHIFT 0x1 127*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPEG2_MASK 0x4 128*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 129*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__REGS_MASK 0x8 130*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__REGS__SHIFT 0x3 131*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__RBC_MASK 0x10 132*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__RBC__SHIFT 0x4 133*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_MC_MASK 0x20 134*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 135*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 136*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 137*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__IDCT_MASK 0x80 138*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__IDCT__SHIFT 0x7 139*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPRD_MASK 0x100 140*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPRD__SHIFT 0x8 141*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPC_MASK 0x200 142*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPC__SHIFT 0x9 143*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LBSI_MASK 0x400 144*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LBSI__SHIFT 0xa 145*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LRBBM_MASK 0x800 146*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 147*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 148*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 149*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 150*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 151*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 152*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 153*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 154*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 155*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 156*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 157*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__WCB_MASK 0x20000 158*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__WCB__SHIFT 0x11 159*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__VCPU_MASK 0x40000 160*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__VCPU__SHIFT 0x12 161*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SCPU_MASK 0x80000 162*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SCPU__SHIFT 0x13 163*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 164*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 165*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 166*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 167*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 168*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 169*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 170*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 171*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 172*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 173*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 174*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 175*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 176*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 177*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 178*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 179*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 180*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 181*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 182*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 183*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 184*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 185*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 186*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 187*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 188*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 189*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 190*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 191*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 192*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 193*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 194*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 195*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 196*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 197*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 198*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 199*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 200*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 201*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 202*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 203*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 204*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 205*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 206*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 207*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 208*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 209*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 210*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 211*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 212*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 213*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 214*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 215*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 216*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 217*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 218*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 219*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 220*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 221*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 222*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 223*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 224*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 225*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 226*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 227*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 228*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 229*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 230*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 231*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 232*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 233*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 234*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 235*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 236*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 237*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 238*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 239*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 240*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 241*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 242*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 243*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 244*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 245*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 246*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 247*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 248*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 249*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 250*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 251*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 252*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 253*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 254*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 255*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 256*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 257*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 258*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 259*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 260*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 261*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 262*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 263*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 264*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 265*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 266*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 267*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 268*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 269*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 270*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 271*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 272*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 273*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 274*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 275*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 276*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 277*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 278*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 279*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 280*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 281*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 282*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 283*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 284*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 285*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 286*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 287*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 288*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 289*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 290*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 291*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 292*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 293*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 294*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 295*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 296*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 297*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 298*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 299*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 300*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 301*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 302*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 303*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 304*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 305*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 306*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 307*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 308*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 309*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 310*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 311*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 312*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 313*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 314*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 315*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 316*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 317*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 318*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 319*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 320*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 321*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 322*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 323*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 324*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 325*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 326*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 327*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 328*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 329*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 330*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 331*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 332*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 333*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 334*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 335*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 336*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 337*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 338*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 339*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 340*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 341*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 342*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 343*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 344*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 345*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 346*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 347*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 348*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 349*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 350*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 351*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 352*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 353*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 354*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 355*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 356*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 357*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 358*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 359*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 360*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 361*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 362*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 363*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 364*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 365*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 366*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 367*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 368*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 369*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 370*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 371*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 372*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 373*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 374*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 375*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 376*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 377*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 378*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 379*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 380*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 381*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 382*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 383*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 384*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 385*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 386*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 387*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 388*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 389*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 390*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 391*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 392*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 393*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 394*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 395*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 396*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 397*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 398*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 399*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 400*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 401*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 402*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 403*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 404*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 405*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 406*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 407*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 408*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 409*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 410*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 411*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 412*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 413*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 414*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 415*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 416*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 417*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 418*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 419*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 420*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 421*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 422*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 423*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 424*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 425*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 426*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 427*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 428*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 429*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 430*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 431*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 432*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 433*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 434*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 435*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 436*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 437*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 438*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 439*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 440*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 441*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 442*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 443*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 444*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 445*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 446*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 447*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 448*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 449*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 450*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 451*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 452*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 453*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 454*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 455*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 456*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 457*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 458*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 459*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 460*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 461*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 462*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 463*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 464*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 465*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 466*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 467*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 468*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 469*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 470*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 471*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 472*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 473*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 474*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 475*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__DBG_MUX_MASK 0x700 476*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 477*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 478*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 479*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 480*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 481*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 482*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 483*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 484*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 485*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 486*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 487*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 488*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 489*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 490*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 491*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 492*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 493*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 494*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 495*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 496*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 497*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 498*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 499*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 500*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 501*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 502*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 503*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 504*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 505*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 506*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 507*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 508*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 509*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 510*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 511*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 512*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 513*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 514*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 515*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 516*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 517*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 518*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 519*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 520*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 521*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 522*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 523*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 524*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 525*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 526*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 527*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 528*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 529*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 530*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 531*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 532*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 533*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 534*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 535*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 536*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 537*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 538*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 539*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 540*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 541*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 542*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 543*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 544*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 545*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 546*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 547*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 548*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 549*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 550*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 551*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 552*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 553*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 554*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 555*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 556*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 557*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_ACTIVE_MASK 0x20000 558*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_ACTIVE__SHIFT 0x11 559*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 560*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 561*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 562*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 563*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 564*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 565*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ECPU_AM32_EN_MASK 0x20000000 566*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ECPU_AM32_EN__SHIFT 0x1d 567*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 568*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 569*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 570*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 571*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 572*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 573*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 574*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 575*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 576*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 577*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 578*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 579*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 580*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 581*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 582*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 583*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 584*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 585*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 586*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 587*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 588*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 589*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__FWV_SOFT_RESET_MASK 0x200 590*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__FWV_SOFT_RESET__SHIFT 0x9 591*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 592*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 593*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 594*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 595*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 596*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 597*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 598*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 599*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 600*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 601*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 602*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 603*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 604*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 605*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_BASE__IB_BASE_MASK 0xffffffc0 606*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_BASE__IB_BASE__SHIFT 0x6 607*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 608*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 609*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_BASE__RB_BASE_MASK 0xffffffc0 610*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_BASE__RB_BASE__SHIFT 0x6 611*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 612*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 613*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 614*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 615*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 616*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 617*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 618*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 619*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 620*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 621*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 622*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 623*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 624*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 625*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 626*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 627*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 628*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 629*c59a5c48SFrançois Tigeot #define UVD_STATUS__RBC_BUSY_MASK 0x1 630*c59a5c48SFrançois Tigeot #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 631*c59a5c48SFrançois Tigeot #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 632*c59a5c48SFrançois Tigeot #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 633*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 634*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 635*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 636*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 637*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 638*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 639*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 640*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 641*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 642*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 643*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 644*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 645*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 646*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 647*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 648*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 649*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 650*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 651*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 652*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 653*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 654*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 655*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 656*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 657*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 658*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 659*c59a5c48SFrançois Tigeot #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 660*c59a5c48SFrançois Tigeot #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 661*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 662*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 663*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 664*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 665*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 666*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 667*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 668*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 669*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 670*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 671*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 672*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 673*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 674*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 675*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 676*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 677*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 678*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 679*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 680*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 681*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 682*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 683*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 684*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 685*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 686*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 687*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 688*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 689*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 690*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 691*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 692*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 693*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 694*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 695*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 696*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 697*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 698*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 699*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 700*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 701*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 702*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 703*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 704*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 705*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 706*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 707*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 708*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 709*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 710*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 711*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 712*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 713*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 714*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 715*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 716*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 717*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 718*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 719*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 720*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 721*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 722*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 723*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 724*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 725*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 726*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 727*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 728*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 729*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 730*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 731*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 732*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 733*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 734*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 735*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 736*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 737*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 738*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 739*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 740*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 741*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 742*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 743*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x1 744*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 745*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 746*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 747*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 748*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 749*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 750*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 751*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 752*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 753*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 754*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 755*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 756*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 757*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 758*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 759*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 760*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 761*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 762*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 763*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 764*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 765*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 766*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 767*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 768*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 769*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 770*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 771*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 772*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 773*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 774*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 775*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 776*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 777*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 778*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 779*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 780*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 781*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 782*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 783*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 784*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 785*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 786*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 787*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 788*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 789*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 790*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 791*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 792*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 793*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 794*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 795*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 796*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 797*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 798*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 799*c59a5c48SFrançois Tigeot 800*c59a5c48SFrançois Tigeot #endif /* UVD_4_2_SH_MASK_H */ 801