1*c59a5c48SFrançois Tigeot /* 2*c59a5c48SFrançois Tigeot * UVD_5_0 Register documentation 3*c59a5c48SFrançois Tigeot * 4*c59a5c48SFrançois Tigeot * Copyright (C) 2014 Advanced Micro Devices, Inc. 5*c59a5c48SFrançois Tigeot * 6*c59a5c48SFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 7*c59a5c48SFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 8*c59a5c48SFrançois Tigeot * to deal in the Software without restriction, including without limitation 9*c59a5c48SFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10*c59a5c48SFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 11*c59a5c48SFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 12*c59a5c48SFrançois Tigeot * 13*c59a5c48SFrançois Tigeot * The above copyright notice and this permission notice shall be included 14*c59a5c48SFrançois Tigeot * in all copies or substantial portions of the Software. 15*c59a5c48SFrançois Tigeot * 16*c59a5c48SFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17*c59a5c48SFrançois Tigeot * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18*c59a5c48SFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19*c59a5c48SFrançois Tigeot * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20*c59a5c48SFrançois Tigeot * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21*c59a5c48SFrançois Tigeot * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22*c59a5c48SFrançois Tigeot */ 23*c59a5c48SFrançois Tigeot 24*c59a5c48SFrançois Tigeot #ifndef UVD_5_0_SH_MASK_H 25*c59a5c48SFrançois Tigeot #define UVD_5_0_SH_MASK_H 26*c59a5c48SFrançois Tigeot 27*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30*c59a5c48SFrançois Tigeot #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__MODE_MASK 0x40 36*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__MODE__SHIFT 0x6 37*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_EN_MASK 0x80 38*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 39*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID_MASK 0xf00 40*c59a5c48SFrançois Tigeot #define UVD_SEMA_CMD__VMID__SHIFT 0x8 41*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1 42*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 43*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe 44*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 45*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000 46*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 47*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff 48*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 49*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff 50*c59a5c48SFrançois Tigeot #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 51*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 52*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 53*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 54*c59a5c48SFrançois Tigeot #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 55*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7 56*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 57*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 58*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 59*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 60*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 61*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 62*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 63*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 64*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 65*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 66*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 67*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 68*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 69*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 70*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 71*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 72*c59a5c48SFrançois Tigeot #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 73*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 74*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 75*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 76*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 77*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 78*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 79*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 80*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 81*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 82*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 83*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 84*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 85*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 86*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 87*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 88*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 89*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 90*c59a5c48SFrançois Tigeot #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 91*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7 92*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 93*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 94*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 95*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 96*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 97*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 98*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 99*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 100*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 101*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 102*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 103*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 104*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 105*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 106*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 107*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 108*c59a5c48SFrançois Tigeot #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 109*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 110*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 111*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 112*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 113*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 114*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 115*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 116*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 117*c59a5c48SFrançois Tigeot #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff 118*c59a5c48SFrançois Tigeot #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 119*c59a5c48SFrançois Tigeot #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff 120*c59a5c48SFrançois Tigeot #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 121*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1 122*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 123*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2 124*c59a5c48SFrançois Tigeot #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 125*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff 126*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0 127*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000 128*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10 129*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000 130*c59a5c48SFrançois Tigeot #define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f 131*c59a5c48SFrançois Tigeot #define UVD_CTX_INDEX__INDEX_MASK 0x1ff 132*c59a5c48SFrançois Tigeot #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 133*c59a5c48SFrançois Tigeot #define UVD_CTX_DATA__DATA_MASK 0xffffffff 134*c59a5c48SFrançois Tigeot #define UVD_CTX_DATA__DATA__SHIFT 0x0 135*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SYS_MASK 0x1 136*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SYS__SHIFT 0x0 137*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MASK 0x2 138*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC__SHIFT 0x1 139*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPEG2_MASK 0x4 140*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 141*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__REGS_MASK 0x8 142*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__REGS__SHIFT 0x3 143*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__RBC_MASK 0x10 144*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__RBC__SHIFT 0x4 145*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_MC_MASK 0x20 146*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 147*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_UMC_MASK 0x40 148*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 149*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__IDCT_MASK 0x80 150*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__IDCT__SHIFT 0x7 151*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPRD_MASK 0x100 152*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPRD__SHIFT 0x8 153*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPC_MASK 0x200 154*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__MPC__SHIFT 0x9 155*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LBSI_MASK 0x400 156*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LBSI__SHIFT 0xa 157*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LRBBM_MASK 0x800 158*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 159*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_RE_MASK 0x1000 160*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 161*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_CM_MASK 0x2000 162*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 163*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 164*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 165*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_DB_MASK 0x8000 166*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 167*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MP_MASK 0x10000 168*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 169*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__WCB_MASK 0x20000 170*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__WCB__SHIFT 0x11 171*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__VCPU_MASK 0x40000 172*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__VCPU__SHIFT 0x12 173*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SCPU_MASK 0x80000 174*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__SCPU__SHIFT 0x13 175*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__JPEG_MASK 0x100000 176*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__JPEG__SHIFT 0x14 177*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__JPEG2_MASK 0x200000 178*c59a5c48SFrançois Tigeot #define UVD_CGC_GATE__JPEG2__SHIFT 0x15 179*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1 180*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 181*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2 182*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 183*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4 184*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 185*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8 186*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 187*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10 188*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 189*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20 190*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 191*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40 192*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 193*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80 194*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 195*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100 196*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 197*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200 198*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 199*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400 200*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 201*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800 202*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 203*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000 204*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 205*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000 206*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 207*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000 208*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 209*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000 210*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 211*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000 212*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 213*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000 214*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 215*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000 216*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 217*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000 218*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 219*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000 220*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 221*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000 222*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 223*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000 224*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 225*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000 226*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 227*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000 228*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 229*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000 230*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 231*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000 232*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 233*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000 234*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 235*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000 236*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 237*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000 238*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 239*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000 240*c59a5c48SFrançois Tigeot #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 241*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1 242*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 243*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2 244*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 245*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c 246*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 247*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0 248*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 249*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800 250*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 251*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000 252*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 253*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000 254*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 255*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000 256*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 257*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000 258*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 259*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000 260*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 261*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000 262*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 263*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000 264*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 265*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000 266*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 267*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000 268*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 269*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000 270*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 271*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000 272*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 273*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000 274*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 275*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000 276*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 277*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000 278*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 279*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000 280*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 281*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000 282*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 283*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000 284*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 285*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000 286*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 287*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000 288*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 289*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000 290*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 291*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1 292*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0 293*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2 294*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1 295*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4 296*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2 297*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8 298*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3 299*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10 300*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 301*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20 302*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5 303*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40 304*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6 305*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80 306*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7 307*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100 308*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8 309*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200 310*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9 311*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400 312*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa 313*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800 314*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb 315*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000 316*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc 317*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000 318*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd 319*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000 320*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe 321*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000 322*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf 323*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000 324*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10 325*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000 326*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11 327*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000 328*c59a5c48SFrançois Tigeot #define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12 329*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1 330*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 331*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2 332*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 333*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4 334*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 335*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8 336*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 337*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70 338*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4 339*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80 340*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 341*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100 342*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 343*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600 344*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 345*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800 346*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 347*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000 348*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd 349*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000 350*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe 351*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000 352*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf 353*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000 354*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10 355*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000 356*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 357*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1 358*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 359*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__VCPU_EN_MASK 0x2 360*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 361*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__SYS_EN_MASK 0x4 362*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 363*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0 364*c59a5c48SFrançois Tigeot #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 365*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf 366*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0 367*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0 368*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4 369*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00 370*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8 371*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000 372*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc 373*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000 374*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10 375*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000 376*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14 377*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000 378*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18 379*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000 380*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c 381*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff 382*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 383*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100 384*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 385*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__REQ_MODE_MASK 0x200 386*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 387*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800 388*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 389*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000 390*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 391*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000 392*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 393*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000 394*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 395*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000 396*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 397*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000 398*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14 399*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000 400*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 401*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000 402*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 403*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000 404*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 405*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000 406*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 407*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000 408*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 409*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000 410*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a 411*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__RFU_MASK 0xf8000000 412*c59a5c48SFrançois Tigeot #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 413*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1 414*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 415*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2 416*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 417*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4 418*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 419*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8 420*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 421*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10 422*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4 423*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20 424*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5 425*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40 426*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 427*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80 428*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7 429*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100 430*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8 431*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200 432*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 433*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400 434*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa 435*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800 436*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb 437*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000 438*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc 439*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000 440*c59a5c48SFrançois Tigeot #define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd 441*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3 442*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 443*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc 444*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 445*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30 446*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 447*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0 448*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 449*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300 450*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 451*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00 452*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 453*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000 454*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 455*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000 456*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 457*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000 458*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 459*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000 460*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 461*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000 462*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 463*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000 464*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 465*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000 466*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 467*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000 468*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 469*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000 470*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 471*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3 472*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0 473*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc 474*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2 475*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30 476*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4 477*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0 478*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6 479*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300 480*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8 481*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00 482*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa 483*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000 484*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc 485*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000 486*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe 487*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000 488*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10 489*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000 490*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12 491*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000 492*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14 493*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000 494*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16 495*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000 496*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18 497*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000 498*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a 499*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000 500*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c 501*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000 502*c59a5c48SFrançois Tigeot #define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e 503*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38 504*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 505*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__PERF_RST_MASK 0x40 506*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6 507*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00 508*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8 509*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000 510*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10 511*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000 512*c59a5c48SFrançois Tigeot #define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12 513*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f 514*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 515*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0 516*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 517*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000 518*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 519*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 520*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 521*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000 522*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 523*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f 524*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 525*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0 526*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 527*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 528*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 529*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f 530*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 531*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0 532*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 533*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000 534*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 535*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000 536*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 537*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000 538*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 539*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f 540*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 541*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0 542*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 543*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000 544*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 545*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_0_MASK 0x7 546*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 547*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_1_MASK 0x38 548*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 549*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0 550*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 551*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__FUNCT_MASK 0x7 552*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 553*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0 554*c59a5c48SFrançois Tigeot #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 555*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff 556*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 557*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff 558*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 559*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff 560*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 561*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff 562*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 563*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff 564*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 565*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff 566*c59a5c48SFrançois Tigeot #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 567*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf 568*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0 569*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10 570*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4 571*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20 572*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5 573*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40 574*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6 575*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80 576*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 577*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100 578*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8 579*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_EN_MASK 0x200 580*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 581*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400 582*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa 583*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800 584*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb 585*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000 586*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd 587*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000 588*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10 589*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000 590*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 591*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000 592*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12 593*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000 594*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13 595*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000 596*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 597*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000 598*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c 599*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000 600*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e 601*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000 602*c59a5c48SFrançois Tigeot #define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f 603*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1 604*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 605*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2 606*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 607*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4 608*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 609*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8 610*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 611*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10 612*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 613*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20 614*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 615*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40 616*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 617*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80 618*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 619*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100 620*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 621*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200 622*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9 623*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400 624*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 625*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800 626*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb 627*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000 628*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc 629*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000 630*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 631*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000 632*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 633*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000 634*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 635*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000 636*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 637*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000 638*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 639*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000 640*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 641*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000 642*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 643*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000 644*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 645*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000 646*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 647*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000 648*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 649*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000 650*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17 651*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000 652*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18 653*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000 654*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19 655*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000 656*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 657*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000 658*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 659*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000 660*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 661*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000 662*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 663*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000 664*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 665*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000 666*c59a5c48SFrançois Tigeot #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 667*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf 668*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 669*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0 670*c59a5c48SFrançois Tigeot #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 671*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf 672*c59a5c48SFrançois Tigeot #define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0 673*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0 674*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 675*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0 676*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 677*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f 678*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 679*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00 680*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 681*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000 682*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 683*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000 684*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 685*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000 686*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 687*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 688*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 689*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff 690*c59a5c48SFrançois Tigeot #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 691*c59a5c48SFrançois Tigeot #define UVD_STATUS__RBC_BUSY_MASK 0x1 692*c59a5c48SFrançois Tigeot #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 693*c59a5c48SFrançois Tigeot #define UVD_STATUS__VCPU_REPORT_MASK 0xfe 694*c59a5c48SFrançois Tigeot #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 695*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1 696*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 697*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2 698*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 699*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4 700*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 701*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8 702*c59a5c48SFrançois Tigeot #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 703*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1 704*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 705*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe 706*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 707*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 708*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 709*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1 710*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 711*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe 712*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 713*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 714*c59a5c48SFrançois Tigeot #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 715*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1 716*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 717*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe 718*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 719*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000 720*c59a5c48SFrançois Tigeot #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 721*c59a5c48SFrançois Tigeot #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff 722*c59a5c48SFrançois Tigeot #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 723*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 724*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 725*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT_MASK 0x2 726*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 727*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 728*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 729*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM_MASK 0x8 730*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 731*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB_MASK 0x10 732*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 733*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 734*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 735*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40 736*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 737*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80 738*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 739*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100 740*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 741*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200 742*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 743*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400 744*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 745*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800 746*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 747*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000 748*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 749*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000 750*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 751*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000 752*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 753*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1 754*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 755*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 756*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 757*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4 758*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 759*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8 760*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 761*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10 762*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 763*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20 764*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 765*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40 766*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 767*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80 768*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 769*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100 770*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 771*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200 772*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 773*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400 774*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 775*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800 776*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 777*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000 778*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 779*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000 780*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 781*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000 782*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 783*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000 784*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 785*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1 786*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 787*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2 788*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 789*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4 790*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 791*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8 792*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 793*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10 794*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 795*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 796*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 797*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40 798*c59a5c48SFrançois Tigeot #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 799*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf 800*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0 801*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0 802*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4 803*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00 804*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8 805*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000 806*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc 807*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000 808*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10 809*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000 810*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14 811*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000 812*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18 813*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000 814*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c 815*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf 816*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0 817*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0 818*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4 819*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00 820*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8 821*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000 822*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc 823*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000 824*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10 825*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000 826*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14 827*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000 828*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18 829*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000 830*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c 831*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1 832*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0 833*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2 834*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1 835*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4 836*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2 837*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8 838*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3 839*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10 840*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4 841*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20 842*c59a5c48SFrançois Tigeot #define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5 843*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3 844*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0 845*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc 846*c59a5c48SFrançois Tigeot #define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2 847*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf 848*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0 849*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0 850*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4 851*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00 852*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8 853*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000 854*c59a5c48SFrançois Tigeot #define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc 855*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1 856*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0 857*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2 858*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1 859*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4 860*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2 861*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8 862*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3 863*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10 864*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4 865*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20 866*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5 867*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40 868*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6 869*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80 870*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7 871*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100 872*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8 873*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200 874*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9 875*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400 876*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa 877*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800 878*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb 879*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000 880*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc 881*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000 882*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd 883*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000 884*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe 885*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000 886*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf 887*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000 888*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10 889*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000 890*c59a5c48SFrançois Tigeot #define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14 891*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1 892*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0 893*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2 894*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1 895*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c 896*c59a5c48SFrançois Tigeot #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2 897*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf 898*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0 899*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0 900*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4 901*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00 902*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8 903*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000 904*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc 905*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000 906*c59a5c48SFrançois Tigeot #define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10 907*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff 908*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0 909*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100 910*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8 911*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200 912*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9 913*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400 914*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa 915*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800 916*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb 917*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000 918*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc 919*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000 920*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd 921*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000 922*c59a5c48SFrançois Tigeot #define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c 923*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff 924*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0 925*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff 926*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0 927*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3 928*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 929*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4 930*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 931*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8 932*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3 933*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10 934*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4 935*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20 936*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5 937*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0 938*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6 939*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 940*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 941*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200 942*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9 943*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400 944*c59a5c48SFrançois Tigeot #define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa 945*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff 946*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0 947*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff 948*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0 949*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff 950*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0 951*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff 952*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0 953*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff 954*c59a5c48SFrançois Tigeot #define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0 955*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 956*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 957*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 958*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 959*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 960*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 961*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 962*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 963*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 964*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 965*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 966*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 967*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 968*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 969*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 970*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 971*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 972*c59a5c48SFrançois Tigeot #define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 973*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7 974*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 975*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 976*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 977*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 978*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 979*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 980*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 981*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 982*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 983*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 984*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 985*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 986*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 987*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 988*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 989*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 990*c59a5c48SFrançois Tigeot #define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 991*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7 992*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 993*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 994*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 995*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 996*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 997*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 998*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 999*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1000*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1001*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1002*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1003*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1004*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1005*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1006*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1007*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1008*c59a5c48SFrançois Tigeot #define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1009*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1010*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1011*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1012*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1013*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1014*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1015*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1016*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1017*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1018*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1019*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1020*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1021*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1022*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1023*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1024*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1025*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1026*c59a5c48SFrançois Tigeot #define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1027*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7 1028*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 1029*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 1030*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 1031*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 1032*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 1033*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 1034*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc 1035*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 1036*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 1037*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 1038*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 1039*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 1040*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 1041*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 1042*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 1043*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 1044*c59a5c48SFrançois Tigeot #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 1045*c59a5c48SFrançois Tigeot 1046*c59a5c48SFrançois Tigeot #endif /* UVD_5_0_SH_MASK_H */ 1047