1c59a5c48SFrançois Tigeot /* 2c59a5c48SFrançois Tigeot * Copyright 2006-2007 Advanced Micro Devices, Inc. 3c59a5c48SFrançois Tigeot * 4c59a5c48SFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 5c59a5c48SFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 6c59a5c48SFrançois Tigeot * to deal in the Software without restriction, including without limitation 7c59a5c48SFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c59a5c48SFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 9c59a5c48SFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 10c59a5c48SFrançois Tigeot * 11c59a5c48SFrançois Tigeot * The above copyright notice and this permission notice shall be included in 12c59a5c48SFrançois Tigeot * all copies or substantial portions of the Software. 13c59a5c48SFrançois Tigeot * 14c59a5c48SFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15c59a5c48SFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c59a5c48SFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c59a5c48SFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18c59a5c48SFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19c59a5c48SFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20c59a5c48SFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 21c59a5c48SFrançois Tigeot */ 22c59a5c48SFrançois Tigeot 23c59a5c48SFrançois Tigeot 24c59a5c48SFrançois Tigeot /****************************************************************************/ 25c59a5c48SFrançois Tigeot /*Portion I: Definitions shared between VBIOS and Driver */ 26c59a5c48SFrançois Tigeot /****************************************************************************/ 27c59a5c48SFrançois Tigeot 28c59a5c48SFrançois Tigeot #ifndef _ATOMBIOS_H 29c59a5c48SFrançois Tigeot #define _ATOMBIOS_H 30c59a5c48SFrançois Tigeot 31c59a5c48SFrançois Tigeot #define ATOM_VERSION_MAJOR 0x00020000 32c59a5c48SFrançois Tigeot #define ATOM_VERSION_MINOR 0x00000002 33c59a5c48SFrançois Tigeot 34c59a5c48SFrançois Tigeot #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 35c59a5c48SFrançois Tigeot 36c59a5c48SFrançois Tigeot /* Endianness should be specified before inclusion, 37c59a5c48SFrançois Tigeot * default to little endian 38c59a5c48SFrançois Tigeot */ 39c59a5c48SFrançois Tigeot #ifndef ATOM_BIG_ENDIAN 40c59a5c48SFrançois Tigeot #error Endian not specified 41c59a5c48SFrançois Tigeot #endif 42c59a5c48SFrançois Tigeot 43c59a5c48SFrançois Tigeot #ifdef _H2INC 44c59a5c48SFrançois Tigeot #ifndef ULONG 45c59a5c48SFrançois Tigeot typedef unsigned long ULONG; 46c59a5c48SFrançois Tigeot #endif 47c59a5c48SFrançois Tigeot 48c59a5c48SFrançois Tigeot #ifndef UCHAR 49c59a5c48SFrançois Tigeot typedef unsigned char UCHAR; 50c59a5c48SFrançois Tigeot #endif 51c59a5c48SFrançois Tigeot 52c59a5c48SFrançois Tigeot #ifndef USHORT 53c59a5c48SFrançois Tigeot typedef unsigned short USHORT; 54c59a5c48SFrançois Tigeot #endif 55c59a5c48SFrançois Tigeot #endif 56c59a5c48SFrançois Tigeot 57c59a5c48SFrançois Tigeot #define ATOM_DAC_A 0 58c59a5c48SFrançois Tigeot #define ATOM_DAC_B 1 59c59a5c48SFrançois Tigeot #define ATOM_EXT_DAC 2 60c59a5c48SFrançois Tigeot 61c59a5c48SFrançois Tigeot #define ATOM_CRTC1 0 62c59a5c48SFrançois Tigeot #define ATOM_CRTC2 1 63c59a5c48SFrançois Tigeot #define ATOM_CRTC3 2 64c59a5c48SFrançois Tigeot #define ATOM_CRTC4 3 65c59a5c48SFrançois Tigeot #define ATOM_CRTC5 4 66c59a5c48SFrançois Tigeot #define ATOM_CRTC6 5 67c59a5c48SFrançois Tigeot 68c59a5c48SFrançois Tigeot #define ATOM_UNDERLAY_PIPE0 16 69c59a5c48SFrançois Tigeot #define ATOM_UNDERLAY_PIPE1 17 70c59a5c48SFrançois Tigeot 71c59a5c48SFrançois Tigeot #define ATOM_CRTC_INVALID 0xFF 72c59a5c48SFrançois Tigeot 73c59a5c48SFrançois Tigeot #define ATOM_DIGA 0 74c59a5c48SFrançois Tigeot #define ATOM_DIGB 1 75c59a5c48SFrançois Tigeot 76c59a5c48SFrançois Tigeot #define ATOM_PPLL1 0 77c59a5c48SFrançois Tigeot #define ATOM_PPLL2 1 78c59a5c48SFrançois Tigeot #define ATOM_DCPLL 2 79c59a5c48SFrançois Tigeot #define ATOM_PPLL0 2 80c59a5c48SFrançois Tigeot #define ATOM_PPLL3 3 81c59a5c48SFrançois Tigeot 82d78d3a22SFrançois Tigeot #define ATOM_PHY_PLL0 4 83d78d3a22SFrançois Tigeot #define ATOM_PHY_PLL1 5 84d78d3a22SFrançois Tigeot 85c59a5c48SFrançois Tigeot #define ATOM_EXT_PLL1 8 86d78d3a22SFrançois Tigeot #define ATOM_GCK_DFS 8 87c59a5c48SFrançois Tigeot #define ATOM_EXT_PLL2 9 88d78d3a22SFrançois Tigeot #define ATOM_FCH_CLK 9 89c59a5c48SFrançois Tigeot #define ATOM_EXT_CLOCK 10 90d78d3a22SFrançois Tigeot #define ATOM_DP_DTO 11 91d78d3a22SFrançois Tigeot 92d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL0 20 93d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL1 21 94d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL2 22 95d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL3 23 96d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL4 24 97d78d3a22SFrançois Tigeot #define ATOM_COMBOPHY_PLL5 25 98d78d3a22SFrançois Tigeot 99c59a5c48SFrançois Tigeot #define ATOM_PPLL_INVALID 0xFF 100c59a5c48SFrançois Tigeot 101c59a5c48SFrançois Tigeot #define ENCODER_REFCLK_SRC_P1PLL 0 102c59a5c48SFrançois Tigeot #define ENCODER_REFCLK_SRC_P2PLL 1 103c59a5c48SFrançois Tigeot #define ENCODER_REFCLK_SRC_DCPLL 2 104c59a5c48SFrançois Tigeot #define ENCODER_REFCLK_SRC_EXTCLK 3 105c59a5c48SFrançois Tigeot #define ENCODER_REFCLK_SRC_INVALID 0xFF 106c59a5c48SFrançois Tigeot 107c59a5c48SFrançois Tigeot #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 108c59a5c48SFrançois Tigeot #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 109c59a5c48SFrançois Tigeot #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 110c59a5c48SFrançois Tigeot #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 111c59a5c48SFrançois Tigeot 112c59a5c48SFrançois Tigeot #define ATOM_DISABLE 0 113c59a5c48SFrançois Tigeot #define ATOM_ENABLE 1 114c59a5c48SFrançois Tigeot #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 115c59a5c48SFrançois Tigeot #define ATOM_LCD_BLON (ATOM_ENABLE+2) 116c59a5c48SFrançois Tigeot #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 117c59a5c48SFrançois Tigeot #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 118c59a5c48SFrançois Tigeot #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 119c59a5c48SFrançois Tigeot #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 120c59a5c48SFrançois Tigeot #define ATOM_INIT (ATOM_DISABLE+7) 121c59a5c48SFrançois Tigeot #define ATOM_GET_STATUS (ATOM_DISABLE+8) 122c59a5c48SFrançois Tigeot 123c59a5c48SFrançois Tigeot #define ATOM_BLANKING 1 124c59a5c48SFrançois Tigeot #define ATOM_BLANKING_OFF 0 125c59a5c48SFrançois Tigeot 126c59a5c48SFrançois Tigeot 127c59a5c48SFrançois Tigeot #define ATOM_CRT1 0 128c59a5c48SFrançois Tigeot #define ATOM_CRT2 1 129c59a5c48SFrançois Tigeot 130c59a5c48SFrançois Tigeot #define ATOM_TV_NTSC 1 131c59a5c48SFrançois Tigeot #define ATOM_TV_NTSCJ 2 132c59a5c48SFrançois Tigeot #define ATOM_TV_PAL 3 133c59a5c48SFrançois Tigeot #define ATOM_TV_PALM 4 134c59a5c48SFrançois Tigeot #define ATOM_TV_PALCN 5 135c59a5c48SFrançois Tigeot #define ATOM_TV_PALN 6 136c59a5c48SFrançois Tigeot #define ATOM_TV_PAL60 7 137c59a5c48SFrançois Tigeot #define ATOM_TV_SECAM 8 138c59a5c48SFrançois Tigeot #define ATOM_TV_CV 16 139c59a5c48SFrançois Tigeot 140c59a5c48SFrançois Tigeot #define ATOM_DAC1_PS2 1 141c59a5c48SFrançois Tigeot #define ATOM_DAC1_CV 2 142c59a5c48SFrançois Tigeot #define ATOM_DAC1_NTSC 3 143c59a5c48SFrançois Tigeot #define ATOM_DAC1_PAL 4 144c59a5c48SFrançois Tigeot 145c59a5c48SFrançois Tigeot #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 146c59a5c48SFrançois Tigeot #define ATOM_DAC2_CV ATOM_DAC1_CV 147c59a5c48SFrançois Tigeot #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 148c59a5c48SFrançois Tigeot #define ATOM_DAC2_PAL ATOM_DAC1_PAL 149c59a5c48SFrançois Tigeot 150c59a5c48SFrançois Tigeot #define ATOM_PM_ON 0 151c59a5c48SFrançois Tigeot #define ATOM_PM_STANDBY 1 152c59a5c48SFrançois Tigeot #define ATOM_PM_SUSPEND 2 153c59a5c48SFrançois Tigeot #define ATOM_PM_OFF 3 154c59a5c48SFrançois Tigeot 155c59a5c48SFrançois Tigeot // For ATOM_LVDS_INFO_V12 156c59a5c48SFrançois Tigeot // Bit0:{=0:single, =1:dual}, 157c59a5c48SFrançois Tigeot // Bit1 {=0:666RGB, =1:888RGB}, 158c59a5c48SFrançois Tigeot // Bit2:3:{Grey level} 159c59a5c48SFrançois Tigeot // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 160c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_DUAL 0x00000001 161c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_888RGB 0x00000002 162c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 163c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_FPDI 0x00000010 164c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 165c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_SPATIAL 0x00000020 166c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 167c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 168c59a5c48SFrançois Tigeot 169c59a5c48SFrançois Tigeot #define MEMTYPE_DDR1 "DDR1" 170c59a5c48SFrançois Tigeot #define MEMTYPE_DDR2 "DDR2" 171c59a5c48SFrançois Tigeot #define MEMTYPE_DDR3 "DDR3" 172c59a5c48SFrançois Tigeot #define MEMTYPE_DDR4 "DDR4" 173c59a5c48SFrançois Tigeot 174c59a5c48SFrançois Tigeot #define ASIC_BUS_TYPE_PCI "PCI" 175c59a5c48SFrançois Tigeot #define ASIC_BUS_TYPE_AGP "AGP" 176c59a5c48SFrançois Tigeot #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 177c59a5c48SFrançois Tigeot 178c59a5c48SFrançois Tigeot //Maximum size of that FireGL flag string 179c59a5c48SFrançois Tigeot #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 180c59a5c48SFrançois Tigeot #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 181c59a5c48SFrançois Tigeot 182c59a5c48SFrançois Tigeot #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 183c59a5c48SFrançois Tigeot #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 184c59a5c48SFrançois Tigeot 185c59a5c48SFrançois Tigeot #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 186c59a5c48SFrançois Tigeot #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 187c59a5c48SFrançois Tigeot 188c59a5c48SFrançois Tigeot #define HW_ASSISTED_I2C_STATUS_FAILURE 2 189c59a5c48SFrançois Tigeot #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 190c59a5c48SFrançois Tigeot 191*b843c749SSergey Zigachev #pragma pack(1) // BIOS data must use byte alignment 192c59a5c48SFrançois Tigeot 193c59a5c48SFrançois Tigeot // Define offset to location of ROM header. 194c59a5c48SFrançois Tigeot #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 195c59a5c48SFrançois Tigeot #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 196c59a5c48SFrançois Tigeot 197c59a5c48SFrançois Tigeot #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 198c59a5c48SFrançois Tigeot #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 199c59a5c48SFrançois Tigeot #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 200c59a5c48SFrançois Tigeot #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 201c59a5c48SFrançois Tigeot 202c59a5c48SFrançois Tigeot /****************************************************************************/ 203c59a5c48SFrançois Tigeot // Common header for all tables (Data table, Command table). 204c59a5c48SFrançois Tigeot // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 205c59a5c48SFrançois Tigeot // And the pointer actually points to this header. 206c59a5c48SFrançois Tigeot /****************************************************************************/ 207c59a5c48SFrançois Tigeot 208c59a5c48SFrançois Tigeot typedef struct _ATOM_COMMON_TABLE_HEADER 209c59a5c48SFrançois Tigeot { 210c59a5c48SFrançois Tigeot USHORT usStructureSize; 211c59a5c48SFrançois Tigeot UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 212c59a5c48SFrançois Tigeot UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 213c59a5c48SFrançois Tigeot //Image can't be updated, while Driver needs to carry the new table! 214c59a5c48SFrançois Tigeot }ATOM_COMMON_TABLE_HEADER; 215c59a5c48SFrançois Tigeot 216c59a5c48SFrançois Tigeot /****************************************************************************/ 217c59a5c48SFrançois Tigeot // Structure stores the ROM header. 218c59a5c48SFrançois Tigeot /****************************************************************************/ 219c59a5c48SFrançois Tigeot typedef struct _ATOM_ROM_HEADER 220c59a5c48SFrançois Tigeot { 221c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 222c59a5c48SFrançois Tigeot UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 223c59a5c48SFrançois Tigeot //atombios should init it as "ATOM", don't change the position 224c59a5c48SFrançois Tigeot USHORT usBiosRuntimeSegmentAddress; 225c59a5c48SFrançois Tigeot USHORT usProtectedModeInfoOffset; 226c59a5c48SFrançois Tigeot USHORT usConfigFilenameOffset; 227c59a5c48SFrançois Tigeot USHORT usCRC_BlockOffset; 228c59a5c48SFrançois Tigeot USHORT usBIOS_BootupMessageOffset; 229c59a5c48SFrançois Tigeot USHORT usInt10Offset; 230c59a5c48SFrançois Tigeot USHORT usPciBusDevInitCode; 231c59a5c48SFrançois Tigeot USHORT usIoBaseAddress; 232c59a5c48SFrançois Tigeot USHORT usSubsystemVendorID; 233c59a5c48SFrançois Tigeot USHORT usSubsystemID; 234c59a5c48SFrançois Tigeot USHORT usPCI_InfoOffset; 235c59a5c48SFrançois Tigeot USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 236c59a5c48SFrançois Tigeot USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 237c59a5c48SFrançois Tigeot UCHAR ucExtendedFunctionCode; 238c59a5c48SFrançois Tigeot UCHAR ucReserved; 239c59a5c48SFrançois Tigeot }ATOM_ROM_HEADER; 240c59a5c48SFrançois Tigeot 241d78d3a22SFrançois Tigeot 242d78d3a22SFrançois Tigeot typedef struct _ATOM_ROM_HEADER_V2_1 243d78d3a22SFrançois Tigeot { 244d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 245d78d3a22SFrançois Tigeot UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 246d78d3a22SFrançois Tigeot //atombios should init it as "ATOM", don't change the position 247d78d3a22SFrançois Tigeot USHORT usBiosRuntimeSegmentAddress; 248d78d3a22SFrançois Tigeot USHORT usProtectedModeInfoOffset; 249d78d3a22SFrançois Tigeot USHORT usConfigFilenameOffset; 250d78d3a22SFrançois Tigeot USHORT usCRC_BlockOffset; 251d78d3a22SFrançois Tigeot USHORT usBIOS_BootupMessageOffset; 252d78d3a22SFrançois Tigeot USHORT usInt10Offset; 253d78d3a22SFrançois Tigeot USHORT usPciBusDevInitCode; 254d78d3a22SFrançois Tigeot USHORT usIoBaseAddress; 255d78d3a22SFrançois Tigeot USHORT usSubsystemVendorID; 256d78d3a22SFrançois Tigeot USHORT usSubsystemID; 257d78d3a22SFrançois Tigeot USHORT usPCI_InfoOffset; 258d78d3a22SFrançois Tigeot USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 259d78d3a22SFrançois Tigeot USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 260d78d3a22SFrançois Tigeot UCHAR ucExtendedFunctionCode; 261d78d3a22SFrançois Tigeot UCHAR ucReserved; 262d78d3a22SFrançois Tigeot ULONG ulPSPDirTableOffset; 263d78d3a22SFrançois Tigeot }ATOM_ROM_HEADER_V2_1; 264d78d3a22SFrançois Tigeot 265d78d3a22SFrançois Tigeot 266c59a5c48SFrançois Tigeot //==============================Command Table Portion==================================== 267c59a5c48SFrançois Tigeot 268c59a5c48SFrançois Tigeot 269c59a5c48SFrançois Tigeot /****************************************************************************/ 270c59a5c48SFrançois Tigeot // Structures used in Command.mtb 271c59a5c48SFrançois Tigeot /****************************************************************************/ 272c59a5c48SFrançois Tigeot typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 273c59a5c48SFrançois Tigeot USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 274c59a5c48SFrançois Tigeot USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 275c59a5c48SFrançois Tigeot USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 276c59a5c48SFrançois Tigeot USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 277c59a5c48SFrançois Tigeot USHORT DIGxEncoderControl; //Only used by Bios 278c59a5c48SFrançois Tigeot USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 279c59a5c48SFrançois Tigeot USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 280c59a5c48SFrançois Tigeot USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 281c59a5c48SFrançois Tigeot USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 282c59a5c48SFrançois Tigeot USHORT GPIOPinControl; //Atomic Table, only used by Bios 283c59a5c48SFrançois Tigeot USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 284c59a5c48SFrançois Tigeot USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 285c59a5c48SFrançois Tigeot USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 286c59a5c48SFrançois Tigeot USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 287c59a5c48SFrançois Tigeot USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 288c59a5c48SFrançois Tigeot USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 289c59a5c48SFrançois Tigeot USHORT MemoryPLLInit; //Atomic Table, used only by Bios 290c59a5c48SFrançois Tigeot USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 291c59a5c48SFrançois Tigeot USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 292c59a5c48SFrançois Tigeot USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 293c59a5c48SFrançois Tigeot USHORT SetUniphyInstance; //Atomic Table, only used by Bios 294c59a5c48SFrançois Tigeot USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 295c59a5c48SFrançois Tigeot USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 296c59a5c48SFrançois Tigeot USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 297c59a5c48SFrançois Tigeot USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 298c59a5c48SFrançois Tigeot USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 299c59a5c48SFrançois Tigeot USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 300c59a5c48SFrançois Tigeot USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 301c59a5c48SFrançois Tigeot USHORT GetConditionalGoldenSetting; //Only used by Bios 302c59a5c48SFrançois Tigeot USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 303c59a5c48SFrançois Tigeot USHORT PatchMCSetting; //only used by BIOS 304c59a5c48SFrançois Tigeot USHORT MC_SEQ_Control; //only used by BIOS 305c59a5c48SFrançois Tigeot USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 306c59a5c48SFrançois Tigeot USHORT EnableScaler; //Atomic Table, used only by Bios 307c59a5c48SFrançois Tigeot USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 308c59a5c48SFrançois Tigeot USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 309c59a5c48SFrançois Tigeot USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 310c59a5c48SFrançois Tigeot USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 311c59a5c48SFrançois Tigeot USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 312c59a5c48SFrançois Tigeot USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 313c59a5c48SFrançois Tigeot USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 314d78d3a22SFrançois Tigeot USHORT GetSMUClockInfo; //Atomic Table, used only by Bios 315c59a5c48SFrançois Tigeot USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 316c59a5c48SFrançois Tigeot USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 317c59a5c48SFrançois Tigeot USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 318c59a5c48SFrançois Tigeot USHORT LUT_AutoFill; //Atomic Table, only used by Bios 319d78d3a22SFrançois Tigeot USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK 320c59a5c48SFrançois Tigeot USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 321c59a5c48SFrançois Tigeot USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 322c59a5c48SFrançois Tigeot USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 323c59a5c48SFrançois Tigeot USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 324c59a5c48SFrançois Tigeot USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 325c59a5c48SFrançois Tigeot USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 326c59a5c48SFrançois Tigeot USHORT MemoryCleanUp; //Atomic Table, only used by Bios 327c59a5c48SFrançois Tigeot USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 328c59a5c48SFrançois Tigeot USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 329c59a5c48SFrançois Tigeot USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 330c59a5c48SFrançois Tigeot USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 331c59a5c48SFrançois Tigeot USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 332c59a5c48SFrançois Tigeot USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 333c59a5c48SFrançois Tigeot USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 334d78d3a22SFrançois Tigeot USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 335c59a5c48SFrançois Tigeot USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 336c59a5c48SFrançois Tigeot USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 337c59a5c48SFrançois Tigeot USHORT MemoryTraining; //Atomic Table, used only by Bios 338c59a5c48SFrançois Tigeot USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 339c59a5c48SFrançois Tigeot USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 340c59a5c48SFrançois Tigeot USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 341c59a5c48SFrançois Tigeot USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 342c59a5c48SFrançois Tigeot USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 343c59a5c48SFrançois Tigeot USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 344c59a5c48SFrançois Tigeot USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 345c59a5c48SFrançois Tigeot USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 346c59a5c48SFrançois Tigeot USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 347c59a5c48SFrançois Tigeot USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 348c59a5c48SFrançois Tigeot USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 349c59a5c48SFrançois Tigeot USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 350c59a5c48SFrançois Tigeot USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 351c59a5c48SFrançois Tigeot USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 352c59a5c48SFrançois Tigeot USHORT DPEncoderService; //Function Table,only used by Bios 353c59a5c48SFrançois Tigeot USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 354c59a5c48SFrançois Tigeot }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 355c59a5c48SFrançois Tigeot 356c59a5c48SFrançois Tigeot // For backward compatible 357c59a5c48SFrançois Tigeot #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 358c59a5c48SFrançois Tigeot #define DPTranslatorControl DIG2EncoderControl 359c59a5c48SFrançois Tigeot #define UNIPHYTransmitterControl DIG1TransmitterControl 360c59a5c48SFrançois Tigeot #define LVTMATransmitterControl DIG2TransmitterControl 361c59a5c48SFrançois Tigeot #define SetCRTC_DPM_State GetConditionalGoldenSetting 362c59a5c48SFrançois Tigeot #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 363c59a5c48SFrançois Tigeot #define HPDInterruptService ReadHWAssistedI2CStatus 364c59a5c48SFrançois Tigeot #define EnableVGA_Access GetSCLKOverMCLKRatio 365c59a5c48SFrançois Tigeot #define EnableYUV GetDispObjectInfo 366c59a5c48SFrançois Tigeot #define DynamicClockGating EnableDispPowerGating 367c59a5c48SFrançois Tigeot #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 368c59a5c48SFrançois Tigeot #define DAC2OutputControl ReadEfuseValue 369c59a5c48SFrançois Tigeot 370c59a5c48SFrançois Tigeot #define TMDSAEncoderControl PatchMCSetting 371c59a5c48SFrançois Tigeot #define LVDSEncoderControl MC_SEQ_Control 372c59a5c48SFrançois Tigeot #define LCD1OutputControl HW_Misc_Operation 373c59a5c48SFrançois Tigeot #define TV1OutputControl Gfx_Harvesting 374c59a5c48SFrançois Tigeot #define TVEncoderControl SMC_Init 375d78d3a22SFrançois Tigeot #define EnableHW_IconCursor SetDCEClock 376d78d3a22SFrançois Tigeot #define SetCRTC_Replication GetSMUClockInfo 377d78d3a22SFrançois Tigeot 378d78d3a22SFrançois Tigeot #define MemoryRefreshConversion Gfx_Init 379c59a5c48SFrançois Tigeot 380c59a5c48SFrançois Tigeot typedef struct _ATOM_MASTER_COMMAND_TABLE 381c59a5c48SFrançois Tigeot { 382c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 383c59a5c48SFrançois Tigeot ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 384c59a5c48SFrançois Tigeot }ATOM_MASTER_COMMAND_TABLE; 385c59a5c48SFrançois Tigeot 386c59a5c48SFrançois Tigeot /****************************************************************************/ 387c59a5c48SFrançois Tigeot // Structures used in every command table 388c59a5c48SFrançois Tigeot /****************************************************************************/ 389c59a5c48SFrançois Tigeot typedef struct _ATOM_TABLE_ATTRIBUTE 390c59a5c48SFrançois Tigeot { 391c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 392c59a5c48SFrançois Tigeot USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 393c59a5c48SFrançois Tigeot USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 394c59a5c48SFrançois Tigeot USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 395c59a5c48SFrançois Tigeot #else 396c59a5c48SFrançois Tigeot USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 397c59a5c48SFrançois Tigeot USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 398c59a5c48SFrançois Tigeot USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 399c59a5c48SFrançois Tigeot #endif 400c59a5c48SFrançois Tigeot }ATOM_TABLE_ATTRIBUTE; 401c59a5c48SFrançois Tigeot 402c59a5c48SFrançois Tigeot /****************************************************************************/ 403c59a5c48SFrançois Tigeot // Common header for all command tables. 404c59a5c48SFrançois Tigeot // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 405c59a5c48SFrançois Tigeot // And the pointer actually points to this header. 406c59a5c48SFrançois Tigeot /****************************************************************************/ 407c59a5c48SFrançois Tigeot typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 408c59a5c48SFrançois Tigeot { 409c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER CommonHeader; 410c59a5c48SFrançois Tigeot ATOM_TABLE_ATTRIBUTE TableAttribute; 411c59a5c48SFrançois Tigeot }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 412c59a5c48SFrançois Tigeot 413c59a5c48SFrançois Tigeot /****************************************************************************/ 414c59a5c48SFrançois Tigeot // Structures used by ComputeMemoryEnginePLLTable 415c59a5c48SFrançois Tigeot /****************************************************************************/ 416c59a5c48SFrançois Tigeot 417c59a5c48SFrançois Tigeot #define COMPUTE_MEMORY_PLL_PARAM 1 418c59a5c48SFrançois Tigeot #define COMPUTE_ENGINE_PLL_PARAM 2 419c59a5c48SFrançois Tigeot #define ADJUST_MC_SETTING_PARAM 3 420c59a5c48SFrançois Tigeot 421c59a5c48SFrançois Tigeot /****************************************************************************/ 422c59a5c48SFrançois Tigeot // Structures used by AdjustMemoryControllerTable 423c59a5c48SFrançois Tigeot /****************************************************************************/ 424c59a5c48SFrançois Tigeot typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 425c59a5c48SFrançois Tigeot { 426c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 427c59a5c48SFrançois Tigeot ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 428c59a5c48SFrançois Tigeot ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 429c59a5c48SFrançois Tigeot ULONG ulClockFreq:24; 430c59a5c48SFrançois Tigeot #else 431c59a5c48SFrançois Tigeot ULONG ulClockFreq:24; 432c59a5c48SFrançois Tigeot ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 433c59a5c48SFrançois Tigeot ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 434c59a5c48SFrançois Tigeot #endif 435c59a5c48SFrançois Tigeot }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 436c59a5c48SFrançois Tigeot #define POINTER_RETURN_FLAG 0x80 437c59a5c48SFrançois Tigeot 438c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 439c59a5c48SFrançois Tigeot { 440c59a5c48SFrançois Tigeot ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 441c59a5c48SFrançois Tigeot UCHAR ucAction; //0:reserved //1:Memory //2:Engine 442c59a5c48SFrançois Tigeot UCHAR ucReserved; //may expand to return larger Fbdiv later 443c59a5c48SFrançois Tigeot UCHAR ucFbDiv; //return value 444c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //return value 445c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 446c59a5c48SFrançois Tigeot 447c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 448c59a5c48SFrançois Tigeot { 449c59a5c48SFrançois Tigeot ULONG ulClock; //When return, [23:0] return real clock 450c59a5c48SFrançois Tigeot UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 451c59a5c48SFrançois Tigeot USHORT usFbDiv; //return Feedback value to be written to register 452c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //return post div to be written to register 453c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 454c59a5c48SFrançois Tigeot 455c59a5c48SFrançois Tigeot #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 456c59a5c48SFrançois Tigeot 457c59a5c48SFrançois Tigeot #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 458c59a5c48SFrançois Tigeot #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 459c59a5c48SFrançois Tigeot #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 460c59a5c48SFrançois Tigeot #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 461c59a5c48SFrançois Tigeot #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 462c59a5c48SFrançois Tigeot #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 463c59a5c48SFrançois Tigeot #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 464c59a5c48SFrançois Tigeot 465c59a5c48SFrançois Tigeot #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 466c59a5c48SFrançois Tigeot #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 467c59a5c48SFrançois Tigeot #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 468c59a5c48SFrançois Tigeot #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 469c59a5c48SFrançois Tigeot #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 470c59a5c48SFrançois Tigeot #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 471d78d3a22SFrançois Tigeot #define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 472d78d3a22SFrançois Tigeot #define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 473d78d3a22SFrançois Tigeot #define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only 474c59a5c48SFrançois Tigeot 475c59a5c48SFrançois Tigeot typedef struct _ATOM_COMPUTE_CLOCK_FREQ 476c59a5c48SFrançois Tigeot { 477c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 478c59a5c48SFrançois Tigeot ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 479c59a5c48SFrançois Tigeot ULONG ulClockFreq:24; // in unit of 10kHz 480c59a5c48SFrançois Tigeot #else 481c59a5c48SFrançois Tigeot ULONG ulClockFreq:24; // in unit of 10kHz 482c59a5c48SFrançois Tigeot ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 483c59a5c48SFrançois Tigeot #endif 484c59a5c48SFrançois Tigeot }ATOM_COMPUTE_CLOCK_FREQ; 485c59a5c48SFrançois Tigeot 486c59a5c48SFrançois Tigeot typedef struct _ATOM_S_MPLL_FB_DIVIDER 487c59a5c48SFrançois Tigeot { 488c59a5c48SFrançois Tigeot USHORT usFbDivFrac; 489c59a5c48SFrançois Tigeot USHORT usFbDiv; 490c59a5c48SFrançois Tigeot }ATOM_S_MPLL_FB_DIVIDER; 491c59a5c48SFrançois Tigeot 492c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 493c59a5c48SFrançois Tigeot { 494c59a5c48SFrançois Tigeot union 495c59a5c48SFrançois Tigeot { 496c59a5c48SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 497*b843c749SSergey Zigachev ULONG ulClockParams; //ULONG access for BE 498c59a5c48SFrançois Tigeot ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 499c59a5c48SFrançois Tigeot }; 500c59a5c48SFrançois Tigeot UCHAR ucRefDiv; //Output Parameter 501c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //Output Parameter 502c59a5c48SFrançois Tigeot UCHAR ucCntlFlag; //Output Parameter 503c59a5c48SFrançois Tigeot UCHAR ucReserved; 504c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 505c59a5c48SFrançois Tigeot 506c59a5c48SFrançois Tigeot // ucCntlFlag 507c59a5c48SFrançois Tigeot #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 508c59a5c48SFrançois Tigeot #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 509c59a5c48SFrançois Tigeot #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 510c59a5c48SFrançois Tigeot #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 511c59a5c48SFrançois Tigeot 512c59a5c48SFrançois Tigeot 513c59a5c48SFrançois Tigeot // V4 are only used for APU which PLL outside GPU 514c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 515c59a5c48SFrançois Tigeot { 516c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 517c59a5c48SFrançois Tigeot ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 518c59a5c48SFrançois Tigeot ULONG ulClock:24; //Input= target clock, output = actual clock 519c59a5c48SFrançois Tigeot #else 520c59a5c48SFrançois Tigeot ULONG ulClock:24; //Input= target clock, output = actual clock 521c59a5c48SFrançois Tigeot ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 522c59a5c48SFrançois Tigeot #endif 523c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 524c59a5c48SFrançois Tigeot 525c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 526c59a5c48SFrançois Tigeot { 527c59a5c48SFrançois Tigeot union 528c59a5c48SFrançois Tigeot { 529c59a5c48SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 530*b843c749SSergey Zigachev ULONG ulClockParams; //ULONG access for BE 531c59a5c48SFrançois Tigeot ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 532c59a5c48SFrançois Tigeot }; 533c59a5c48SFrançois Tigeot UCHAR ucRefDiv; //Output Parameter 534c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //Output Parameter 535c59a5c48SFrançois Tigeot union 536c59a5c48SFrançois Tigeot { 537c59a5c48SFrançois Tigeot UCHAR ucCntlFlag; //Output Flags 538c59a5c48SFrançois Tigeot UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 539c59a5c48SFrançois Tigeot }; 540c59a5c48SFrançois Tigeot UCHAR ucReserved; 541c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 542c59a5c48SFrançois Tigeot 543c59a5c48SFrançois Tigeot 544c59a5c48SFrançois Tigeot typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 545c59a5c48SFrançois Tigeot { 546c59a5c48SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 547c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 548c59a5c48SFrançois Tigeot }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 549c59a5c48SFrançois Tigeot 550c59a5c48SFrançois Tigeot //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 551c59a5c48SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 552c59a5c48SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 553c59a5c48SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 554c59a5c48SFrançois Tigeot 555c59a5c48SFrançois Tigeot 556c59a5c48SFrançois Tigeot typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 557c59a5c48SFrançois Tigeot { 558c59a5c48SFrançois Tigeot COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 559c59a5c48SFrançois Tigeot ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 560c59a5c48SFrançois Tigeot UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 561c59a5c48SFrançois Tigeot UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 562c59a5c48SFrançois Tigeot UCHAR ucPllCntlFlag; //Output Flags: control flag 563c59a5c48SFrançois Tigeot UCHAR ucReserved; 564c59a5c48SFrançois Tigeot }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 565c59a5c48SFrançois Tigeot 566c59a5c48SFrançois Tigeot //ucPllCntlFlag 567c59a5c48SFrançois Tigeot #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 568c59a5c48SFrançois Tigeot 569d78d3a22SFrançois Tigeot typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 570d78d3a22SFrançois Tigeot { 571d78d3a22SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 572d78d3a22SFrançois Tigeot ULONG ulReserved[5]; 573d78d3a22SFrançois Tigeot }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; 574d78d3a22SFrançois Tigeot 575d78d3a22SFrançois Tigeot //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 576d78d3a22SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 577d78d3a22SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 578d78d3a22SFrançois Tigeot #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 579d78d3a22SFrançois Tigeot 580d78d3a22SFrançois Tigeot typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 581d78d3a22SFrançois Tigeot { 582d78d3a22SFrançois Tigeot COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 583d78d3a22SFrançois Tigeot USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 584d78d3a22SFrançois Tigeot USHORT usSclk_fcw_int; //integer divider of fcwc 585d78d3a22SFrançois Tigeot UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv 586d78d3a22SFrançois Tigeot UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved 587d78d3a22SFrançois Tigeot UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 ) 588d78d3a22SFrançois Tigeot UCHAR ucSscEnable; 589d78d3a22SFrançois Tigeot USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable 590d78d3a22SFrançois Tigeot USHORT usSsc_fcw1_int; //fcw1_int when SSC enable 591d78d3a22SFrançois Tigeot USHORT usReserved; 592d78d3a22SFrançois Tigeot USHORT usPcc_fcw_int; 593d78d3a22SFrançois Tigeot USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable 594d78d3a22SFrançois Tigeot USHORT usPcc_fcw_slew_frac; 595d78d3a22SFrançois Tigeot }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; 596c59a5c48SFrançois Tigeot 597c59a5c48SFrançois Tigeot // ucInputFlag 598c59a5c48SFrançois Tigeot #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 599c59a5c48SFrançois Tigeot 600c59a5c48SFrançois Tigeot // use for ComputeMemoryClockParamTable 601c59a5c48SFrançois Tigeot typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 602c59a5c48SFrançois Tigeot { 603c59a5c48SFrançois Tigeot union 604c59a5c48SFrançois Tigeot { 605c59a5c48SFrançois Tigeot ULONG ulClock; 606c59a5c48SFrançois Tigeot ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 607c59a5c48SFrançois Tigeot }; 608c59a5c48SFrançois Tigeot UCHAR ucDllSpeed; //Output 609c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //Output 610c59a5c48SFrançois Tigeot union{ 611c59a5c48SFrançois Tigeot UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 612c59a5c48SFrançois Tigeot UCHAR ucPllCntlFlag; //Output: 613c59a5c48SFrançois Tigeot }; 614c59a5c48SFrançois Tigeot UCHAR ucBWCntl; 615c59a5c48SFrançois Tigeot }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 616c59a5c48SFrançois Tigeot 617c59a5c48SFrançois Tigeot // definition of ucInputFlag 618c59a5c48SFrançois Tigeot #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 619c59a5c48SFrançois Tigeot // definition of ucPllCntlFlag 620c59a5c48SFrançois Tigeot #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 621c59a5c48SFrançois Tigeot #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 622c59a5c48SFrançois Tigeot #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 623c59a5c48SFrançois Tigeot #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 624c59a5c48SFrançois Tigeot 625c59a5c48SFrançois Tigeot //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 626c59a5c48SFrançois Tigeot #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 627c59a5c48SFrançois Tigeot 628d78d3a22SFrançois Tigeot // use for ComputeMemoryClockParamTable 629d78d3a22SFrançois Tigeot typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 630d78d3a22SFrançois Tigeot { 631d78d3a22SFrançois Tigeot COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 632d78d3a22SFrançois Tigeot ULONG ulReserved; 633d78d3a22SFrançois Tigeot }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; 634d78d3a22SFrançois Tigeot 635*b843c749SSergey Zigachev typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 636*b843c749SSergey Zigachev { 637*b843c749SSergey Zigachev COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 638*b843c749SSergey Zigachev USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 639*b843c749SSergey Zigachev USHORT usMclk_fcw_int; //integer divider of fcwc 640*b843c749SSergey Zigachev }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3; 641*b843c749SSergey Zigachev 642d78d3a22SFrançois Tigeot //Input parameter of DynamicMemorySettingsTable 643d78d3a22SFrançois Tigeot //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM 644c59a5c48SFrançois Tigeot typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 645c59a5c48SFrançois Tigeot { 646c59a5c48SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; 647c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 648c59a5c48SFrançois Tigeot }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 649c59a5c48SFrançois Tigeot 650d78d3a22SFrançois Tigeot //Input parameter of DynamicMemorySettingsTable 651d78d3a22SFrançois Tigeot //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM 652c59a5c48SFrançois Tigeot typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 653c59a5c48SFrançois Tigeot { 654c59a5c48SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; 655c59a5c48SFrançois Tigeot ULONG ulMemoryClock; 656c59a5c48SFrançois Tigeot ULONG ulReserved; 657c59a5c48SFrançois Tigeot }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 658c59a5c48SFrançois Tigeot 659d78d3a22SFrançois Tigeot //Input parameter of DynamicMemorySettingsTable ver2.1 and above 660d78d3a22SFrançois Tigeot //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM 661d78d3a22SFrançois Tigeot typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER 662d78d3a22SFrançois Tigeot { 663d78d3a22SFrançois Tigeot ATOM_COMPUTE_CLOCK_FREQ ulClock; 664d78d3a22SFrançois Tigeot UCHAR ucMclkDPMState; 665d78d3a22SFrançois Tigeot UCHAR ucReserved[3]; 666d78d3a22SFrançois Tigeot ULONG ulReserved; 667d78d3a22SFrançois Tigeot }DYNAMICE_MC_DPM_SETTINGS_PARAMETER; 668d78d3a22SFrançois Tigeot 669d78d3a22SFrançois Tigeot //ucMclkDPMState 670d78d3a22SFrançois Tigeot #define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0 671d78d3a22SFrançois Tigeot #define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1 672d78d3a22SFrançois Tigeot #define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2 673d78d3a22SFrançois Tigeot 674d78d3a22SFrançois Tigeot typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 675d78d3a22SFrançois Tigeot { 676d78d3a22SFrançois Tigeot DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg; 677d78d3a22SFrançois Tigeot DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg; 678d78d3a22SFrançois Tigeot DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg; 679d78d3a22SFrançois Tigeot }DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; 680d78d3a22SFrançois Tigeot 681d78d3a22SFrançois Tigeot 682c59a5c48SFrançois Tigeot /****************************************************************************/ 683c59a5c48SFrançois Tigeot // Structures used by SetEngineClockTable 684c59a5c48SFrançois Tigeot /****************************************************************************/ 685c59a5c48SFrançois Tigeot typedef struct _SET_ENGINE_CLOCK_PARAMETERS 686c59a5c48SFrançois Tigeot { 687c59a5c48SFrançois Tigeot ULONG ulTargetEngineClock; //In 10Khz unit 688c59a5c48SFrançois Tigeot }SET_ENGINE_CLOCK_PARAMETERS; 689c59a5c48SFrançois Tigeot 690c59a5c48SFrançois Tigeot typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 691c59a5c48SFrançois Tigeot { 692c59a5c48SFrançois Tigeot ULONG ulTargetEngineClock; //In 10Khz unit 693c59a5c48SFrançois Tigeot COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 694c59a5c48SFrançois Tigeot }SET_ENGINE_CLOCK_PS_ALLOCATION; 695c59a5c48SFrançois Tigeot 696d78d3a22SFrançois Tigeot typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 697d78d3a22SFrançois Tigeot { 698d78d3a22SFrançois Tigeot ULONG ulTargetEngineClock; //In 10Khz unit 699d78d3a22SFrançois Tigeot COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved; 700d78d3a22SFrançois Tigeot }SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; 701d78d3a22SFrançois Tigeot 702d78d3a22SFrançois Tigeot 703c59a5c48SFrançois Tigeot /****************************************************************************/ 704c59a5c48SFrançois Tigeot // Structures used by SetMemoryClockTable 705c59a5c48SFrançois Tigeot /****************************************************************************/ 706c59a5c48SFrançois Tigeot typedef struct _SET_MEMORY_CLOCK_PARAMETERS 707c59a5c48SFrançois Tigeot { 708c59a5c48SFrançois Tigeot ULONG ulTargetMemoryClock; //In 10Khz unit 709c59a5c48SFrançois Tigeot }SET_MEMORY_CLOCK_PARAMETERS; 710c59a5c48SFrançois Tigeot 711c59a5c48SFrançois Tigeot typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 712c59a5c48SFrançois Tigeot { 713c59a5c48SFrançois Tigeot ULONG ulTargetMemoryClock; //In 10Khz unit 714c59a5c48SFrançois Tigeot COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 715c59a5c48SFrançois Tigeot }SET_MEMORY_CLOCK_PS_ALLOCATION; 716c59a5c48SFrançois Tigeot 717c59a5c48SFrançois Tigeot /****************************************************************************/ 718c59a5c48SFrançois Tigeot // Structures used by ASIC_Init.ctb 719c59a5c48SFrançois Tigeot /****************************************************************************/ 720c59a5c48SFrançois Tigeot typedef struct _ASIC_INIT_PARAMETERS 721c59a5c48SFrançois Tigeot { 722c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 723c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 724c59a5c48SFrançois Tigeot }ASIC_INIT_PARAMETERS; 725c59a5c48SFrançois Tigeot 726c59a5c48SFrançois Tigeot typedef struct _ASIC_INIT_PS_ALLOCATION 727c59a5c48SFrançois Tigeot { 728c59a5c48SFrançois Tigeot ASIC_INIT_PARAMETERS sASICInitClocks; 729c59a5c48SFrançois Tigeot SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 730c59a5c48SFrançois Tigeot }ASIC_INIT_PS_ALLOCATION; 731c59a5c48SFrançois Tigeot 732c59a5c48SFrançois Tigeot typedef struct _ASIC_INIT_CLOCK_PARAMETERS 733c59a5c48SFrançois Tigeot { 734c59a5c48SFrançois Tigeot ULONG ulClkFreqIn10Khz:24; 735c59a5c48SFrançois Tigeot ULONG ucClkFlag:8; 736c59a5c48SFrançois Tigeot }ASIC_INIT_CLOCK_PARAMETERS; 737c59a5c48SFrançois Tigeot 738c59a5c48SFrançois Tigeot typedef struct _ASIC_INIT_PARAMETERS_V1_2 739c59a5c48SFrançois Tigeot { 740c59a5c48SFrançois Tigeot ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 741c59a5c48SFrançois Tigeot ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 742c59a5c48SFrançois Tigeot }ASIC_INIT_PARAMETERS_V1_2; 743c59a5c48SFrançois Tigeot 744c59a5c48SFrançois Tigeot typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 745c59a5c48SFrançois Tigeot { 746c59a5c48SFrançois Tigeot ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 747c59a5c48SFrançois Tigeot ULONG ulReserved[8]; 748c59a5c48SFrançois Tigeot }ASIC_INIT_PS_ALLOCATION_V1_2; 749c59a5c48SFrançois Tigeot 750c59a5c48SFrançois Tigeot /****************************************************************************/ 751c59a5c48SFrançois Tigeot // Structure used by DynamicClockGatingTable.ctb 752c59a5c48SFrançois Tigeot /****************************************************************************/ 753c59a5c48SFrançois Tigeot typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 754c59a5c48SFrançois Tigeot { 755c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 756c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 757c59a5c48SFrançois Tigeot }DYNAMIC_CLOCK_GATING_PARAMETERS; 758c59a5c48SFrançois Tigeot #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 759c59a5c48SFrançois Tigeot 760c59a5c48SFrançois Tigeot /****************************************************************************/ 761c59a5c48SFrançois Tigeot // Structure used by EnableDispPowerGatingTable.ctb 762c59a5c48SFrançois Tigeot /****************************************************************************/ 763c59a5c48SFrançois Tigeot typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 764c59a5c48SFrançois Tigeot { 765c59a5c48SFrançois Tigeot UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 766c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 767c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 768c59a5c48SFrançois Tigeot }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 769c59a5c48SFrançois Tigeot 770c59a5c48SFrançois Tigeot typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 771c59a5c48SFrançois Tigeot { 772c59a5c48SFrançois Tigeot UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 773c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 774c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 775c59a5c48SFrançois Tigeot ULONG ulReserved[4]; 776c59a5c48SFrançois Tigeot }ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 777c59a5c48SFrançois Tigeot 778c59a5c48SFrançois Tigeot /****************************************************************************/ 779c59a5c48SFrançois Tigeot // Structure used by EnableASIC_StaticPwrMgtTable.ctb 780c59a5c48SFrançois Tigeot /****************************************************************************/ 781c59a5c48SFrançois Tigeot typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 782c59a5c48SFrançois Tigeot { 783c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 784c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 785c59a5c48SFrançois Tigeot }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 786c59a5c48SFrançois Tigeot #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 787c59a5c48SFrançois Tigeot 788c59a5c48SFrançois Tigeot /****************************************************************************/ 789c59a5c48SFrançois Tigeot // Structures used by DAC_LoadDetectionTable.ctb 790c59a5c48SFrançois Tigeot /****************************************************************************/ 791c59a5c48SFrançois Tigeot typedef struct _DAC_LOAD_DETECTION_PARAMETERS 792c59a5c48SFrançois Tigeot { 793c59a5c48SFrançois Tigeot USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 794c59a5c48SFrançois Tigeot UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 795c59a5c48SFrançois Tigeot UCHAR ucMisc; //Valid only when table revision =1.3 and above 796c59a5c48SFrançois Tigeot }DAC_LOAD_DETECTION_PARAMETERS; 797c59a5c48SFrançois Tigeot 798c59a5c48SFrançois Tigeot // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 799c59a5c48SFrançois Tigeot #define DAC_LOAD_MISC_YPrPb 0x01 800c59a5c48SFrançois Tigeot 801c59a5c48SFrançois Tigeot typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 802c59a5c48SFrançois Tigeot { 803c59a5c48SFrançois Tigeot DAC_LOAD_DETECTION_PARAMETERS sDacload; 804c59a5c48SFrançois Tigeot ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 805c59a5c48SFrançois Tigeot }DAC_LOAD_DETECTION_PS_ALLOCATION; 806c59a5c48SFrançois Tigeot 807c59a5c48SFrançois Tigeot /****************************************************************************/ 808c59a5c48SFrançois Tigeot // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 809c59a5c48SFrançois Tigeot /****************************************************************************/ 810c59a5c48SFrançois Tigeot typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 811c59a5c48SFrançois Tigeot { 812c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 813c59a5c48SFrançois Tigeot UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 814c59a5c48SFrançois Tigeot UCHAR ucAction; // 0: turn off encoder 815c59a5c48SFrançois Tigeot // 1: setup and turn on encoder 816c59a5c48SFrançois Tigeot // 7: ATOM_ENCODER_INIT Initialize DAC 817c59a5c48SFrançois Tigeot }DAC_ENCODER_CONTROL_PARAMETERS; 818c59a5c48SFrançois Tigeot 819c59a5c48SFrançois Tigeot #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 820c59a5c48SFrançois Tigeot 821c59a5c48SFrançois Tigeot /****************************************************************************/ 822c59a5c48SFrançois Tigeot // Structures used by DIG1EncoderControlTable 823c59a5c48SFrançois Tigeot // DIG2EncoderControlTable 824c59a5c48SFrançois Tigeot // ExternalEncoderControlTable 825c59a5c48SFrançois Tigeot /****************************************************************************/ 826c59a5c48SFrançois Tigeot typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 827c59a5c48SFrançois Tigeot { 828c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 829c59a5c48SFrançois Tigeot UCHAR ucConfig; 830c59a5c48SFrançois Tigeot // [2] Link Select: 831c59a5c48SFrançois Tigeot // =0: PHY linkA if bfLane<3 832c59a5c48SFrançois Tigeot // =1: PHY linkB if bfLanes<3 833c59a5c48SFrançois Tigeot // =0: PHY linkA+B if bfLanes=3 834c59a5c48SFrançois Tigeot // [3] Transmitter Sel 835c59a5c48SFrançois Tigeot // =0: UNIPHY or PCIEPHY 836c59a5c48SFrançois Tigeot // =1: LVTMA 837c59a5c48SFrançois Tigeot UCHAR ucAction; // =0: turn off encoder 838c59a5c48SFrançois Tigeot // =1: turn on encoder 839c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; 840c59a5c48SFrançois Tigeot // =0: DP encoder 841c59a5c48SFrançois Tigeot // =1: LVDS encoder 842c59a5c48SFrançois Tigeot // =2: DVI encoder 843c59a5c48SFrançois Tigeot // =3: HDMI encoder 844c59a5c48SFrançois Tigeot // =4: SDVO encoder 845c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // how many lanes to enable 846c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 847c59a5c48SFrançois Tigeot }DIG_ENCODER_CONTROL_PARAMETERS; 848c59a5c48SFrançois Tigeot #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 849c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 850c59a5c48SFrançois Tigeot 851c59a5c48SFrançois Tigeot //ucConfig 852c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 853c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 854c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 855c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 856c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 857c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LINKA 0x00 858c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LINKB 0x04 859c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 860c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 861c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 862c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 863c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_LVTMA 0x08 864c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 865c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 866c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 867c59a5c48SFrançois Tigeot // ucAction 868c59a5c48SFrançois Tigeot // ATOM_ENABLE: Enable Encoder 869c59a5c48SFrançois Tigeot // ATOM_DISABLE: Disable Encoder 870c59a5c48SFrançois Tigeot 871c59a5c48SFrançois Tigeot //ucEncoderMode 872c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DP 0 873c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_LVDS 1 874c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DVI 2 875c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_HDMI 3 876c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_SDVO 4 877c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DP_AUDIO 5 878c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_TV 13 879c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_CV 14 880c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_CRT 15 881c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DVO 16 882c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 883c59a5c48SFrançois Tigeot #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 884c59a5c48SFrançois Tigeot 885c59a5c48SFrançois Tigeot 886c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 887c59a5c48SFrançois Tigeot { 888c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 889c59a5c48SFrançois Tigeot UCHAR ucReserved1:2; 890c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 891c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 892c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 893c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 894c59a5c48SFrançois Tigeot #else 895c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 896c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 897c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 898c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 899c59a5c48SFrançois Tigeot UCHAR ucReserved1:2; 900c59a5c48SFrançois Tigeot #endif 901c59a5c48SFrançois Tigeot }ATOM_DIG_ENCODER_CONFIG_V2; 902c59a5c48SFrançois Tigeot 903c59a5c48SFrançois Tigeot 904c59a5c48SFrançois Tigeot typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 905c59a5c48SFrançois Tigeot { 906c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 907c59a5c48SFrançois Tigeot ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 908c59a5c48SFrançois Tigeot UCHAR ucAction; 909c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; 910c59a5c48SFrançois Tigeot // =0: DP encoder 911c59a5c48SFrançois Tigeot // =1: LVDS encoder 912c59a5c48SFrançois Tigeot // =2: DVI encoder 913c59a5c48SFrançois Tigeot // =3: HDMI encoder 914c59a5c48SFrançois Tigeot // =4: SDVO encoder 915c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // how many lanes to enable 916c59a5c48SFrançois Tigeot UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 917c59a5c48SFrançois Tigeot UCHAR ucReserved; 918c59a5c48SFrançois Tigeot }DIG_ENCODER_CONTROL_PARAMETERS_V2; 919c59a5c48SFrançois Tigeot 920c59a5c48SFrançois Tigeot //ucConfig 921c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 922c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 923c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 924c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 925c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 926c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 927c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 928c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 929c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 930c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 931c59a5c48SFrançois Tigeot 932c59a5c48SFrançois Tigeot // ucAction: 933c59a5c48SFrançois Tigeot // ATOM_DISABLE 934c59a5c48SFrançois Tigeot // ATOM_ENABLE 935c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 936c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 937c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 938c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 939c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 940c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 941c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 942c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 943c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_SETUP 0x0f 944c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 945c59a5c48SFrançois Tigeot 946d78d3a22SFrançois Tigeot // New Command for DIGxEncoderControlTable v1.5 947d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 948d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP 949d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table 950d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table 951d78d3a22SFrançois Tigeot 952c59a5c48SFrançois Tigeot // ucStatus 953c59a5c48SFrançois Tigeot #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 954c59a5c48SFrançois Tigeot #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 955c59a5c48SFrançois Tigeot 956c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 957c59a5c48SFrançois Tigeot //ucTableContentRevision=3 958c59a5c48SFrançois Tigeot // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 959c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 960c59a5c48SFrançois Tigeot { 961c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 962c59a5c48SFrançois Tigeot UCHAR ucReserved1:1; 963c59a5c48SFrançois Tigeot UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 964c59a5c48SFrançois Tigeot UCHAR ucReserved:3; 965c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 966c59a5c48SFrançois Tigeot #else 967c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 968c59a5c48SFrançois Tigeot UCHAR ucReserved:3; 969c59a5c48SFrançois Tigeot UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 970c59a5c48SFrançois Tigeot UCHAR ucReserved1:1; 971c59a5c48SFrançois Tigeot #endif 972c59a5c48SFrançois Tigeot }ATOM_DIG_ENCODER_CONFIG_V3; 973c59a5c48SFrançois Tigeot 974c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 975c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 976c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 977c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 978c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 979c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 980c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 981c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 982c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 983c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 984c59a5c48SFrançois Tigeot 985c59a5c48SFrançois Tigeot typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 986c59a5c48SFrançois Tigeot { 987c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 988c59a5c48SFrançois Tigeot ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 989c59a5c48SFrançois Tigeot UCHAR ucAction; 990c59a5c48SFrançois Tigeot union{ 991c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; 992c59a5c48SFrançois Tigeot // =0: DP encoder 993c59a5c48SFrançois Tigeot // =1: LVDS encoder 994c59a5c48SFrançois Tigeot // =2: DVI encoder 995c59a5c48SFrançois Tigeot // =3: HDMI encoder 996c59a5c48SFrançois Tigeot // =4: SDVO encoder 997c59a5c48SFrançois Tigeot // =5: DP audio 998c59a5c48SFrançois Tigeot UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 999c59a5c48SFrançois Tigeot // =0: external DP 1000c59a5c48SFrançois Tigeot // =0x1: internal DP2 1001c59a5c48SFrançois Tigeot // =0x11: internal DP1 for NutMeg/Travis DP translator 1002c59a5c48SFrançois Tigeot }; 1003c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // how many lanes to enable 1004c59a5c48SFrançois Tigeot UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1005c59a5c48SFrançois Tigeot UCHAR ucReserved; 1006c59a5c48SFrançois Tigeot }DIG_ENCODER_CONTROL_PARAMETERS_V3; 1007c59a5c48SFrançois Tigeot 1008c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 1009c59a5c48SFrançois Tigeot //ucTableContentRevision=4 1010c59a5c48SFrançois Tigeot // start from NI 1011c59a5c48SFrançois Tigeot // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 1012c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 1013c59a5c48SFrançois Tigeot { 1014c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1015c59a5c48SFrançois Tigeot UCHAR ucReserved1:1; 1016c59a5c48SFrançois Tigeot UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1017c59a5c48SFrançois Tigeot UCHAR ucReserved:2; 1018c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1019c59a5c48SFrançois Tigeot #else 1020c59a5c48SFrançois Tigeot UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1021c59a5c48SFrançois Tigeot UCHAR ucReserved:2; 1022c59a5c48SFrançois Tigeot UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1023c59a5c48SFrançois Tigeot UCHAR ucReserved1:1; 1024c59a5c48SFrançois Tigeot #endif 1025c59a5c48SFrançois Tigeot }ATOM_DIG_ENCODER_CONFIG_V4; 1026c59a5c48SFrançois Tigeot 1027c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 1028c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 1029c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 1030c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 1031c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 1032c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 1033c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 1034c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 1035c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 1036c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 1037c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 1038c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 1039c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 1040c59a5c48SFrançois Tigeot 1041c59a5c48SFrançois Tigeot typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 1042c59a5c48SFrançois Tigeot { 1043c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 1044c59a5c48SFrançois Tigeot union{ 1045c59a5c48SFrançois Tigeot ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 1046c59a5c48SFrançois Tigeot UCHAR ucConfig; 1047c59a5c48SFrançois Tigeot }; 1048c59a5c48SFrançois Tigeot UCHAR ucAction; 1049c59a5c48SFrançois Tigeot union{ 1050c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; 1051c59a5c48SFrançois Tigeot // =0: DP encoder 1052c59a5c48SFrançois Tigeot // =1: LVDS encoder 1053c59a5c48SFrançois Tigeot // =2: DVI encoder 1054c59a5c48SFrançois Tigeot // =3: HDMI encoder 1055c59a5c48SFrançois Tigeot // =4: SDVO encoder 1056c59a5c48SFrançois Tigeot // =5: DP audio 1057c59a5c48SFrançois Tigeot UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1058c59a5c48SFrançois Tigeot // =0: external DP 1059c59a5c48SFrançois Tigeot // =0x1: internal DP2 1060c59a5c48SFrançois Tigeot // =0x11: internal DP1 for NutMeg/Travis DP translator 1061c59a5c48SFrançois Tigeot }; 1062c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // how many lanes to enable 1063c59a5c48SFrançois Tigeot UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1064c59a5c48SFrançois Tigeot UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 1065c59a5c48SFrançois Tigeot }DIG_ENCODER_CONTROL_PARAMETERS_V4; 1066c59a5c48SFrançois Tigeot 1067c59a5c48SFrançois Tigeot // define ucBitPerColor: 1068c59a5c48SFrançois Tigeot #define PANEL_BPC_UNDEFINE 0x00 1069c59a5c48SFrançois Tigeot #define PANEL_6BIT_PER_COLOR 0x01 1070c59a5c48SFrançois Tigeot #define PANEL_8BIT_PER_COLOR 0x02 1071c59a5c48SFrançois Tigeot #define PANEL_10BIT_PER_COLOR 0x03 1072c59a5c48SFrançois Tigeot #define PANEL_12BIT_PER_COLOR 0x04 1073c59a5c48SFrançois Tigeot #define PANEL_16BIT_PER_COLOR 0x05 1074c59a5c48SFrançois Tigeot 1075c59a5c48SFrançois Tigeot //define ucPanelMode 1076c59a5c48SFrançois Tigeot #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 1077c59a5c48SFrançois Tigeot #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 1078c59a5c48SFrançois Tigeot #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 1079c59a5c48SFrançois Tigeot 1080d78d3a22SFrançois Tigeot 1081d78d3a22SFrançois Tigeot typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5 1082d78d3a22SFrançois Tigeot { 1083d78d3a22SFrançois Tigeot UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1084d78d3a22SFrançois Tigeot UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP 1085d78d3a22SFrançois Tigeot UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1086d78d3a22SFrançois Tigeot UCHAR ucLaneNum; // Lane number 1087d78d3a22SFrançois Tigeot ULONG ulPixelClock; // Pixel Clock in 10Khz 1088d78d3a22SFrançois Tigeot UCHAR ucBitPerColor; 1089d78d3a22SFrançois Tigeot UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 1090d78d3a22SFrançois Tigeot UCHAR ucReserved[2]; 1091d78d3a22SFrançois Tigeot }ENCODER_STREAM_SETUP_PARAMETERS_V5; 1092d78d3a22SFrançois Tigeot 1093d78d3a22SFrançois Tigeot typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5 1094d78d3a22SFrançois Tigeot { 1095d78d3a22SFrançois Tigeot UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1096d78d3a22SFrançois Tigeot UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP 1097d78d3a22SFrançois Tigeot UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1098d78d3a22SFrançois Tigeot UCHAR ucLaneNum; // Lane number 1099d78d3a22SFrançois Tigeot ULONG ulSymClock; // Symbol Clock in 10Khz 1100d78d3a22SFrançois Tigeot UCHAR ucHPDSel; 1101d78d3a22SFrançois Tigeot UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1102d78d3a22SFrançois Tigeot UCHAR ucReserved[2]; 1103d78d3a22SFrançois Tigeot }ENCODER_LINK_SETUP_PARAMETERS_V5; 1104d78d3a22SFrançois Tigeot 1105d78d3a22SFrançois Tigeot typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5 1106d78d3a22SFrançois Tigeot { 1107d78d3a22SFrançois Tigeot UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1108d78d3a22SFrançois Tigeot UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP 1109d78d3a22SFrançois Tigeot UCHAR ucPanelMode; // =0: external DP 1110d78d3a22SFrançois Tigeot // =0x1: internal DP2 1111d78d3a22SFrançois Tigeot // =0x11: internal DP1 NutMeg/Travis DP Translator 1112d78d3a22SFrançois Tigeot UCHAR ucReserved; 1113d78d3a22SFrançois Tigeot ULONG ulReserved[2]; 1114d78d3a22SFrançois Tigeot }DP_PANEL_MODE_SETUP_PARAMETERS_V5; 1115d78d3a22SFrançois Tigeot 1116d78d3a22SFrançois Tigeot typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5 1117d78d3a22SFrançois Tigeot { 1118d78d3a22SFrançois Tigeot UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1119d78d3a22SFrançois Tigeot UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters 1120d78d3a22SFrançois Tigeot UCHAR ucReserved[2]; 1121d78d3a22SFrançois Tigeot ULONG ulReserved[2]; 1122d78d3a22SFrançois Tigeot }ENCODER_GENERIC_CMD_PARAMETERS_V5; 1123d78d3a22SFrançois Tigeot 1124d78d3a22SFrançois Tigeot //ucDigId 1125d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00 1126d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01 1127d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02 1128d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03 1129d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04 1130d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05 1131d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06 1132d78d3a22SFrançois Tigeot 1133d78d3a22SFrançois Tigeot 1134d78d3a22SFrançois Tigeot typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5 1135d78d3a22SFrançois Tigeot { 1136d78d3a22SFrançois Tigeot ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam; 1137d78d3a22SFrançois Tigeot ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam; 1138d78d3a22SFrançois Tigeot ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam; 1139d78d3a22SFrançois Tigeot DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam; 1140d78d3a22SFrançois Tigeot }DIG_ENCODER_CONTROL_PARAMETERS_V5; 1141d78d3a22SFrançois Tigeot 1142d78d3a22SFrançois Tigeot 1143c59a5c48SFrançois Tigeot /****************************************************************************/ 1144c59a5c48SFrançois Tigeot // Structures used by UNIPHYTransmitterControlTable 1145c59a5c48SFrançois Tigeot // LVTMATransmitterControlTable 1146c59a5c48SFrançois Tigeot // DVOOutputControlTable 1147c59a5c48SFrançois Tigeot /****************************************************************************/ 1148c59a5c48SFrançois Tigeot typedef struct _ATOM_DP_VS_MODE 1149c59a5c48SFrançois Tigeot { 1150c59a5c48SFrançois Tigeot UCHAR ucLaneSel; 1151c59a5c48SFrançois Tigeot UCHAR ucLaneSet; 1152c59a5c48SFrançois Tigeot }ATOM_DP_VS_MODE; 1153c59a5c48SFrançois Tigeot 1154c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 1155c59a5c48SFrançois Tigeot { 1156c59a5c48SFrançois Tigeot union 1157c59a5c48SFrançois Tigeot { 1158c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 1159c59a5c48SFrançois Tigeot USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1160c59a5c48SFrançois Tigeot ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1161c59a5c48SFrançois Tigeot }; 1162c59a5c48SFrançois Tigeot UCHAR ucConfig; 1163c59a5c48SFrançois Tigeot // [0]=0: 4 lane Link, 1164c59a5c48SFrançois Tigeot // =1: 8 lane Link ( Dual Links TMDS ) 1165c59a5c48SFrançois Tigeot // [1]=0: InCoherent mode 1166c59a5c48SFrançois Tigeot // =1: Coherent Mode 1167c59a5c48SFrançois Tigeot // [2] Link Select: 1168c59a5c48SFrançois Tigeot // =0: PHY linkA if bfLane<3 1169c59a5c48SFrançois Tigeot // =1: PHY linkB if bfLanes<3 1170c59a5c48SFrançois Tigeot // =0: PHY linkA+B if bfLanes=3 1171c59a5c48SFrançois Tigeot // [5:4]PCIE lane Sel 1172c59a5c48SFrançois Tigeot // =0: lane 0~3 or 0~7 1173c59a5c48SFrançois Tigeot // =1: lane 4~7 1174c59a5c48SFrançois Tigeot // =2: lane 8~11 or 8~15 1175c59a5c48SFrançois Tigeot // =3: lane 12~15 1176c59a5c48SFrançois Tigeot UCHAR ucAction; // =0: turn off encoder 1177c59a5c48SFrançois Tigeot // =1: turn on encoder 1178c59a5c48SFrançois Tigeot UCHAR ucReserved[4]; 1179c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS; 1180c59a5c48SFrançois Tigeot 1181c59a5c48SFrançois Tigeot #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 1182c59a5c48SFrançois Tigeot 1183c59a5c48SFrançois Tigeot //ucInitInfo 1184c59a5c48SFrançois Tigeot #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 1185c59a5c48SFrançois Tigeot 1186c59a5c48SFrançois Tigeot //ucConfig 1187c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 1188c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 1189c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1190c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1191c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1192c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1193c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1194c59a5c48SFrançois Tigeot 1195c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1196c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1197c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1198c59a5c48SFrançois Tigeot 1199c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1200c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1201c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1202c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1203c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1204c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1205c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1206c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1207c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1208c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1209c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1210c59a5c48SFrançois Tigeot 1211c59a5c48SFrançois Tigeot //ucAction 1212c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_DISABLE 0 1213c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_ENABLE 1 1214c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1215c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1216c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1217c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1218c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1219c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_INIT 7 1220c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1221c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1222c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_SETUP 10 1223c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1224c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1225c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1226c59a5c48SFrançois Tigeot 1227c59a5c48SFrançois Tigeot // Following are used for DigTransmitterControlTable ver1.2 1228c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1229c59a5c48SFrançois Tigeot { 1230c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1231c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1232c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1233c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1234c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 1235c59a5c48SFrançois Tigeot UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1236c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1237c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1238c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1239c59a5c48SFrançois Tigeot 1240c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1241c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1242c59a5c48SFrançois Tigeot #else 1243c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1244c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1245c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1246c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1247c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1248c59a5c48SFrançois Tigeot UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1249c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 1250c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1251c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1252c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1253c59a5c48SFrançois Tigeot #endif 1254c59a5c48SFrançois Tigeot }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1255c59a5c48SFrançois Tigeot 1256c59a5c48SFrançois Tigeot //ucConfig 1257c59a5c48SFrançois Tigeot //Bit0 1258c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1259c59a5c48SFrançois Tigeot 1260c59a5c48SFrançois Tigeot //Bit1 1261c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1262c59a5c48SFrançois Tigeot 1263c59a5c48SFrançois Tigeot //Bit2 1264c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1265c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1266c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1267c59a5c48SFrançois Tigeot 1268c59a5c48SFrançois Tigeot // Bit3 1269c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1270c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1271c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1272c59a5c48SFrançois Tigeot 1273c59a5c48SFrançois Tigeot // Bit4 1274c59a5c48SFrançois Tigeot #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1275c59a5c48SFrançois Tigeot 1276c59a5c48SFrançois Tigeot // Bit7:6 1277c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1278c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1279c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1280c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1281c59a5c48SFrançois Tigeot 1282c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1283c59a5c48SFrançois Tigeot { 1284c59a5c48SFrançois Tigeot union 1285c59a5c48SFrançois Tigeot { 1286c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 1287c59a5c48SFrançois Tigeot USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1288c59a5c48SFrançois Tigeot ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1289c59a5c48SFrançois Tigeot }; 1290c59a5c48SFrançois Tigeot ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1291c59a5c48SFrançois Tigeot UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1292c59a5c48SFrançois Tigeot UCHAR ucReserved[4]; 1293c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1294c59a5c48SFrançois Tigeot 1295c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1296c59a5c48SFrançois Tigeot { 1297c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1298c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1299c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1300c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1301c59a5c48SFrançois Tigeot UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1302c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1303c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1304c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1305c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1306c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1307c59a5c48SFrançois Tigeot #else 1308c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1309c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1310c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1311c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1312c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1313c59a5c48SFrançois Tigeot UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1314c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1315c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1316c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1317c59a5c48SFrançois Tigeot #endif 1318c59a5c48SFrançois Tigeot }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1319c59a5c48SFrançois Tigeot 1320c59a5c48SFrançois Tigeot 1321c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1322c59a5c48SFrançois Tigeot { 1323c59a5c48SFrançois Tigeot union 1324c59a5c48SFrançois Tigeot { 1325c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 1326c59a5c48SFrançois Tigeot USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1327c59a5c48SFrançois Tigeot ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1328c59a5c48SFrançois Tigeot }; 1329c59a5c48SFrançois Tigeot ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1330c59a5c48SFrançois Tigeot UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1331c59a5c48SFrançois Tigeot UCHAR ucLaneNum; 1332c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 1333c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1334c59a5c48SFrançois Tigeot 1335c59a5c48SFrançois Tigeot //ucConfig 1336c59a5c48SFrançois Tigeot //Bit0 1337c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1338c59a5c48SFrançois Tigeot 1339c59a5c48SFrançois Tigeot //Bit1 1340c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1341c59a5c48SFrançois Tigeot 1342c59a5c48SFrançois Tigeot //Bit2 1343c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1344c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1345c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1346c59a5c48SFrançois Tigeot 1347c59a5c48SFrançois Tigeot // Bit3 1348c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1349c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1350c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1351c59a5c48SFrançois Tigeot 1352c59a5c48SFrançois Tigeot // Bit5:4 1353c59a5c48SFrançois Tigeot #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1354c59a5c48SFrançois Tigeot #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1355c59a5c48SFrançois Tigeot #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1356c59a5c48SFrançois Tigeot #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1357c59a5c48SFrançois Tigeot 1358c59a5c48SFrançois Tigeot // Bit7:6 1359c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1360c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1361c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1362c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1363c59a5c48SFrançois Tigeot 1364c59a5c48SFrançois Tigeot 1365c59a5c48SFrançois Tigeot /****************************************************************************/ 1366c59a5c48SFrançois Tigeot // Structures used by UNIPHYTransmitterControlTable V1.4 1367c59a5c48SFrançois Tigeot // ASIC Families: NI 1368c59a5c48SFrançois Tigeot // ucTableFormatRevision=1 1369c59a5c48SFrançois Tigeot // ucTableContentRevision=4 1370c59a5c48SFrançois Tigeot /****************************************************************************/ 1371c59a5c48SFrançois Tigeot typedef struct _ATOM_DP_VS_MODE_V4 1372c59a5c48SFrançois Tigeot { 1373c59a5c48SFrançois Tigeot UCHAR ucLaneSel; 1374c59a5c48SFrançois Tigeot union 1375c59a5c48SFrançois Tigeot { 1376c59a5c48SFrançois Tigeot UCHAR ucLaneSet; 1377c59a5c48SFrançois Tigeot struct { 1378c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1379c59a5c48SFrançois Tigeot UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1380c59a5c48SFrançois Tigeot UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1381c59a5c48SFrançois Tigeot UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1382c59a5c48SFrançois Tigeot #else 1383c59a5c48SFrançois Tigeot UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1384c59a5c48SFrançois Tigeot UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1385c59a5c48SFrançois Tigeot UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1386c59a5c48SFrançois Tigeot #endif 1387c59a5c48SFrançois Tigeot }; 1388c59a5c48SFrançois Tigeot }; 1389c59a5c48SFrançois Tigeot }ATOM_DP_VS_MODE_V4; 1390c59a5c48SFrançois Tigeot 1391c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1392c59a5c48SFrançois Tigeot { 1393c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1394c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1395c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1396c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1397c59a5c48SFrançois Tigeot UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1398c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1399c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1400c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1401c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1402c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1403c59a5c48SFrançois Tigeot #else 1404c59a5c48SFrançois Tigeot UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1405c59a5c48SFrançois Tigeot UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1406c59a5c48SFrançois Tigeot UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1407c59a5c48SFrançois Tigeot // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1408c59a5c48SFrançois Tigeot UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1409c59a5c48SFrançois Tigeot UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1410c59a5c48SFrançois Tigeot UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1411c59a5c48SFrançois Tigeot // =1 Dig Transmitter 2 ( Uniphy CD ) 1412c59a5c48SFrançois Tigeot // =2 Dig Transmitter 3 ( Uniphy EF ) 1413c59a5c48SFrançois Tigeot #endif 1414c59a5c48SFrançois Tigeot }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1415c59a5c48SFrançois Tigeot 1416c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1417c59a5c48SFrançois Tigeot { 1418c59a5c48SFrançois Tigeot union 1419c59a5c48SFrançois Tigeot { 1420c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 1421c59a5c48SFrançois Tigeot USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1422c59a5c48SFrançois Tigeot ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1423c59a5c48SFrançois Tigeot }; 1424c59a5c48SFrançois Tigeot union 1425c59a5c48SFrançois Tigeot { 1426c59a5c48SFrançois Tigeot ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1427c59a5c48SFrançois Tigeot UCHAR ucConfig; 1428c59a5c48SFrançois Tigeot }; 1429c59a5c48SFrançois Tigeot UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1430c59a5c48SFrançois Tigeot UCHAR ucLaneNum; 1431c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 1432c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1433c59a5c48SFrançois Tigeot 1434c59a5c48SFrançois Tigeot //ucConfig 1435c59a5c48SFrançois Tigeot //Bit0 1436c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1437c59a5c48SFrançois Tigeot //Bit1 1438c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1439c59a5c48SFrançois Tigeot //Bit2 1440c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1441c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1442c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1443c59a5c48SFrançois Tigeot // Bit3 1444c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1445c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1446c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1447c59a5c48SFrançois Tigeot // Bit5:4 1448c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1449c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1450c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1451c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1452c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1453c59a5c48SFrançois Tigeot // Bit7:6 1454c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1455c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1456c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1457c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1458c59a5c48SFrançois Tigeot 1459c59a5c48SFrançois Tigeot 1460c59a5c48SFrançois Tigeot typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1461c59a5c48SFrançois Tigeot { 1462c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1463c59a5c48SFrançois Tigeot UCHAR ucReservd1:1; 1464c59a5c48SFrançois Tigeot UCHAR ucHPDSel:3; 1465c59a5c48SFrançois Tigeot UCHAR ucPhyClkSrcId:2; 1466c59a5c48SFrançois Tigeot UCHAR ucCoherentMode:1; 1467c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 1468c59a5c48SFrançois Tigeot #else 1469c59a5c48SFrançois Tigeot UCHAR ucReserved:1; 1470c59a5c48SFrançois Tigeot UCHAR ucCoherentMode:1; 1471c59a5c48SFrançois Tigeot UCHAR ucPhyClkSrcId:2; 1472c59a5c48SFrançois Tigeot UCHAR ucHPDSel:3; 1473c59a5c48SFrançois Tigeot UCHAR ucReservd1:1; 1474c59a5c48SFrançois Tigeot #endif 1475c59a5c48SFrançois Tigeot }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1476c59a5c48SFrançois Tigeot 1477c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1478c59a5c48SFrançois Tigeot { 1479c59a5c48SFrançois Tigeot USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1480c59a5c48SFrançois Tigeot UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1481c59a5c48SFrançois Tigeot UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1482c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // indicate lane number 1-8 1483c59a5c48SFrançois Tigeot UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1484c59a5c48SFrançois Tigeot UCHAR ucDigMode; // indicate DIG mode 1485c59a5c48SFrançois Tigeot union{ 1486c59a5c48SFrançois Tigeot ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1487c59a5c48SFrançois Tigeot UCHAR ucConfig; 1488c59a5c48SFrançois Tigeot }; 1489c59a5c48SFrançois Tigeot UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1490c59a5c48SFrançois Tigeot UCHAR ucDPLaneSet; 1491c59a5c48SFrançois Tigeot UCHAR ucReserved; 1492c59a5c48SFrançois Tigeot UCHAR ucReserved1; 1493c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1494c59a5c48SFrançois Tigeot 1495c59a5c48SFrançois Tigeot //ucPhyId 1496c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYA 0 1497c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYB 1 1498c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYC 2 1499c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYD 3 1500c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYE 4 1501c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYF 5 1502c59a5c48SFrançois Tigeot #define ATOM_PHY_ID_UNIPHYG 6 1503c59a5c48SFrançois Tigeot 1504c59a5c48SFrançois Tigeot // ucDigEncoderSel 1505c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1506c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1507c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1508c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1509c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1510c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1511c59a5c48SFrançois Tigeot #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1512c59a5c48SFrançois Tigeot 1513c59a5c48SFrançois Tigeot // ucDigMode 1514c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1515c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1516c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1517c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1518c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1519c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1520c59a5c48SFrançois Tigeot 1521c59a5c48SFrançois Tigeot // ucDPLaneSet 1522c59a5c48SFrançois Tigeot #define DP_LANE_SET__0DB_0_4V 0x00 1523c59a5c48SFrançois Tigeot #define DP_LANE_SET__0DB_0_6V 0x01 1524c59a5c48SFrançois Tigeot #define DP_LANE_SET__0DB_0_8V 0x02 1525c59a5c48SFrançois Tigeot #define DP_LANE_SET__0DB_1_2V 0x03 1526c59a5c48SFrançois Tigeot #define DP_LANE_SET__3_5DB_0_4V 0x08 1527c59a5c48SFrançois Tigeot #define DP_LANE_SET__3_5DB_0_6V 0x09 1528c59a5c48SFrançois Tigeot #define DP_LANE_SET__3_5DB_0_8V 0x0a 1529c59a5c48SFrançois Tigeot #define DP_LANE_SET__6DB_0_4V 0x10 1530c59a5c48SFrançois Tigeot #define DP_LANE_SET__6DB_0_6V 0x11 1531c59a5c48SFrançois Tigeot #define DP_LANE_SET__9_5DB_0_4V 0x18 1532c59a5c48SFrançois Tigeot 1533c59a5c48SFrançois Tigeot // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1534c59a5c48SFrançois Tigeot // Bit1 1535c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1536c59a5c48SFrançois Tigeot 1537c59a5c48SFrançois Tigeot // Bit3:2 1538c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1539c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1540c59a5c48SFrançois Tigeot 1541c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1542c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1543c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1544c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1545c59a5c48SFrançois Tigeot // Bit6:4 1546c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1547c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1548c59a5c48SFrançois Tigeot 1549c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1550c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1551c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1552c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1553c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1554c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1555c59a5c48SFrançois Tigeot #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1556c59a5c48SFrançois Tigeot 1557c59a5c48SFrançois Tigeot #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1558c59a5c48SFrançois Tigeot 1559d78d3a22SFrançois Tigeot typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 1560d78d3a22SFrançois Tigeot { 1561d78d3a22SFrançois Tigeot UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1562d78d3a22SFrançois Tigeot UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1563d78d3a22SFrançois Tigeot union 1564d78d3a22SFrançois Tigeot { 1565d78d3a22SFrançois Tigeot UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1566d78d3a22SFrançois Tigeot UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 1567d78d3a22SFrançois Tigeot }; 1568d78d3a22SFrançois Tigeot UCHAR ucLaneNum; // Lane number 1569d78d3a22SFrançois Tigeot ULONG ulSymClock; // Symbol Clock in 10Khz 1570d78d3a22SFrançois Tigeot UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 1571d78d3a22SFrançois Tigeot UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1572d78d3a22SFrançois Tigeot UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1573d78d3a22SFrançois Tigeot UCHAR ucReserved; 1574d78d3a22SFrançois Tigeot ULONG ulReserved; 1575d78d3a22SFrançois Tigeot }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; 1576d78d3a22SFrançois Tigeot 1577d78d3a22SFrançois Tigeot 1578d78d3a22SFrançois Tigeot // ucDigEncoderSel 1579d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01 1580d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02 1581d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04 1582d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08 1583d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10 1584d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20 1585d78d3a22SFrançois Tigeot #define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40 1586d78d3a22SFrançois Tigeot 1587d78d3a22SFrançois Tigeot // ucDigMode 1588d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 1589d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 1590d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 1591d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 1592d78d3a22SFrançois Tigeot 1593d78d3a22SFrançois Tigeot //ucHPDSel 1594d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00 1595d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01 1596d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02 1597d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03 1598d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04 1599d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05 1600d78d3a22SFrançois Tigeot #define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06 1601d78d3a22SFrançois Tigeot 1602c59a5c48SFrançois Tigeot 1603c59a5c48SFrançois Tigeot /****************************************************************************/ 1604c59a5c48SFrançois Tigeot // Structures used by ExternalEncoderControlTable V1.3 1605c59a5c48SFrançois Tigeot // ASIC Families: Evergreen, Llano, NI 1606c59a5c48SFrançois Tigeot // ucTableFormatRevision=1 1607c59a5c48SFrançois Tigeot // ucTableContentRevision=3 1608c59a5c48SFrançois Tigeot /****************************************************************************/ 1609c59a5c48SFrançois Tigeot 1610c59a5c48SFrançois Tigeot typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1611c59a5c48SFrançois Tigeot { 1612c59a5c48SFrançois Tigeot union{ 1613c59a5c48SFrançois Tigeot USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1614c59a5c48SFrançois Tigeot USHORT usConnectorId; // connector id, valid when ucAction = INIT 1615c59a5c48SFrançois Tigeot }; 1616c59a5c48SFrançois Tigeot UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1617c59a5c48SFrançois Tigeot UCHAR ucAction; // 1618c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1619c59a5c48SFrançois Tigeot UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1620c59a5c48SFrançois Tigeot UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1621c59a5c48SFrançois Tigeot UCHAR ucReserved; 1622c59a5c48SFrançois Tigeot }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1623c59a5c48SFrançois Tigeot 1624c59a5c48SFrançois Tigeot // ucAction 1625c59a5c48SFrançois Tigeot #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1626c59a5c48SFrançois Tigeot #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1627c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1628c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1629c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1630c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1631c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1632c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1633c59a5c48SFrançois Tigeot 1634c59a5c48SFrançois Tigeot // ucConfig 1635c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1636c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1637c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1638c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1639c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1640c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1641c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1642c59a5c48SFrançois Tigeot #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1643c59a5c48SFrançois Tigeot 1644c59a5c48SFrançois Tigeot typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1645c59a5c48SFrançois Tigeot { 1646c59a5c48SFrançois Tigeot EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1647c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 1648c59a5c48SFrançois Tigeot }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1649c59a5c48SFrançois Tigeot 1650c59a5c48SFrançois Tigeot 1651c59a5c48SFrançois Tigeot /****************************************************************************/ 1652c59a5c48SFrançois Tigeot // Structures used by DAC1OuputControlTable 1653c59a5c48SFrançois Tigeot // DAC2OuputControlTable 1654c59a5c48SFrançois Tigeot // LVTMAOutputControlTable (Before DEC30) 1655c59a5c48SFrançois Tigeot // TMDSAOutputControlTable (Before DEC30) 1656c59a5c48SFrançois Tigeot /****************************************************************************/ 1657c59a5c48SFrançois Tigeot typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1658c59a5c48SFrançois Tigeot { 1659c59a5c48SFrançois Tigeot UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1660c59a5c48SFrançois Tigeot // When the display is LCD, in addition to above: 1661c59a5c48SFrançois Tigeot // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1662c59a5c48SFrançois Tigeot // ATOM_LCD_SELFTEST_STOP 1663c59a5c48SFrançois Tigeot 1664c59a5c48SFrançois Tigeot UCHAR aucPadding[3]; // padding to DWORD aligned 1665c59a5c48SFrançois Tigeot }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1666c59a5c48SFrançois Tigeot 1667c59a5c48SFrançois Tigeot #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1668c59a5c48SFrançois Tigeot 1669c59a5c48SFrançois Tigeot 1670c59a5c48SFrançois Tigeot #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1671c59a5c48SFrançois Tigeot #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1672c59a5c48SFrançois Tigeot 1673c59a5c48SFrançois Tigeot #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1674c59a5c48SFrançois Tigeot #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1675c59a5c48SFrançois Tigeot 1676c59a5c48SFrançois Tigeot #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1677c59a5c48SFrançois Tigeot #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1678c59a5c48SFrançois Tigeot 1679c59a5c48SFrançois Tigeot #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1680c59a5c48SFrançois Tigeot #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1681c59a5c48SFrançois Tigeot 1682c59a5c48SFrançois Tigeot #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1683c59a5c48SFrançois Tigeot #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1684c59a5c48SFrançois Tigeot 1685c59a5c48SFrançois Tigeot #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1686c59a5c48SFrançois Tigeot #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1687c59a5c48SFrançois Tigeot 1688c59a5c48SFrançois Tigeot #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1689c59a5c48SFrançois Tigeot #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1690c59a5c48SFrançois Tigeot 1691c59a5c48SFrançois Tigeot #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1692c59a5c48SFrançois Tigeot #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1693c59a5c48SFrançois Tigeot #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1694c59a5c48SFrançois Tigeot 1695c59a5c48SFrançois Tigeot 1696c59a5c48SFrançois Tigeot typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1697c59a5c48SFrançois Tigeot { 1698c59a5c48SFrançois Tigeot // Possible value of ucAction 1699c59a5c48SFrançois Tigeot // ATOM_TRANSMITTER_ACTION_LCD_BLON 1700c59a5c48SFrançois Tigeot // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1701c59a5c48SFrançois Tigeot // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1702c59a5c48SFrançois Tigeot // ATOM_TRANSMITTER_ACTION_POWER_ON 1703c59a5c48SFrançois Tigeot // ATOM_TRANSMITTER_ACTION_POWER_OFF 1704c59a5c48SFrançois Tigeot UCHAR ucAction; 1705c59a5c48SFrançois Tigeot UCHAR ucBriLevel; 1706c59a5c48SFrançois Tigeot USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1707c59a5c48SFrançois Tigeot }LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1708c59a5c48SFrançois Tigeot 1709c59a5c48SFrançois Tigeot 1710c59a5c48SFrançois Tigeot 1711c59a5c48SFrançois Tigeot /****************************************************************************/ 1712c59a5c48SFrançois Tigeot // Structures used by BlankCRTCTable 1713c59a5c48SFrançois Tigeot /****************************************************************************/ 1714c59a5c48SFrançois Tigeot typedef struct _BLANK_CRTC_PARAMETERS 1715c59a5c48SFrançois Tigeot { 1716c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1717c59a5c48SFrançois Tigeot UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1718c59a5c48SFrançois Tigeot USHORT usBlackColorRCr; 1719c59a5c48SFrançois Tigeot USHORT usBlackColorGY; 1720c59a5c48SFrançois Tigeot USHORT usBlackColorBCb; 1721c59a5c48SFrançois Tigeot }BLANK_CRTC_PARAMETERS; 1722c59a5c48SFrançois Tigeot #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1723c59a5c48SFrançois Tigeot 1724c59a5c48SFrançois Tigeot /****************************************************************************/ 1725c59a5c48SFrançois Tigeot // Structures used by EnableCRTCTable 1726c59a5c48SFrançois Tigeot // EnableCRTCMemReqTable 1727c59a5c48SFrançois Tigeot // UpdateCRTC_DoubleBufferRegistersTable 1728c59a5c48SFrançois Tigeot /****************************************************************************/ 1729c59a5c48SFrançois Tigeot typedef struct _ENABLE_CRTC_PARAMETERS 1730c59a5c48SFrançois Tigeot { 1731c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1732c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1733c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 1734c59a5c48SFrançois Tigeot }ENABLE_CRTC_PARAMETERS; 1735c59a5c48SFrançois Tigeot #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1736c59a5c48SFrançois Tigeot 1737c59a5c48SFrançois Tigeot /****************************************************************************/ 1738c59a5c48SFrançois Tigeot // Structures used by SetCRTC_OverScanTable 1739c59a5c48SFrançois Tigeot /****************************************************************************/ 1740c59a5c48SFrançois Tigeot typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1741c59a5c48SFrançois Tigeot { 1742c59a5c48SFrançois Tigeot USHORT usOverscanRight; // right 1743c59a5c48SFrançois Tigeot USHORT usOverscanLeft; // left 1744c59a5c48SFrançois Tigeot USHORT usOverscanBottom; // bottom 1745c59a5c48SFrançois Tigeot USHORT usOverscanTop; // top 1746c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1747c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 1748c59a5c48SFrançois Tigeot }SET_CRTC_OVERSCAN_PARAMETERS; 1749c59a5c48SFrançois Tigeot #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1750c59a5c48SFrançois Tigeot 1751c59a5c48SFrançois Tigeot /****************************************************************************/ 1752c59a5c48SFrançois Tigeot // Structures used by SetCRTC_ReplicationTable 1753c59a5c48SFrançois Tigeot /****************************************************************************/ 1754c59a5c48SFrançois Tigeot typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1755c59a5c48SFrançois Tigeot { 1756c59a5c48SFrançois Tigeot UCHAR ucH_Replication; // horizontal replication 1757c59a5c48SFrançois Tigeot UCHAR ucV_Replication; // vertical replication 1758c59a5c48SFrançois Tigeot UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1759c59a5c48SFrançois Tigeot UCHAR ucPadding; 1760c59a5c48SFrançois Tigeot }SET_CRTC_REPLICATION_PARAMETERS; 1761c59a5c48SFrançois Tigeot #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1762c59a5c48SFrançois Tigeot 1763c59a5c48SFrançois Tigeot /****************************************************************************/ 1764c59a5c48SFrançois Tigeot // Structures used by SelectCRTC_SourceTable 1765c59a5c48SFrançois Tigeot /****************************************************************************/ 1766c59a5c48SFrançois Tigeot typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1767c59a5c48SFrançois Tigeot { 1768c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1769c59a5c48SFrançois Tigeot UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1770c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 1771c59a5c48SFrançois Tigeot }SELECT_CRTC_SOURCE_PARAMETERS; 1772c59a5c48SFrançois Tigeot #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1773c59a5c48SFrançois Tigeot 1774c59a5c48SFrançois Tigeot typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1775c59a5c48SFrançois Tigeot { 1776c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1777c59a5c48SFrançois Tigeot UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1778c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1779c59a5c48SFrançois Tigeot UCHAR ucPadding; 1780c59a5c48SFrançois Tigeot }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1781c59a5c48SFrançois Tigeot 1782c59a5c48SFrançois Tigeot //ucEncoderID 1783c59a5c48SFrançois Tigeot //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1784c59a5c48SFrançois Tigeot //#define ASIC_INT_TV_ENCODER_ID 0x02 1785c59a5c48SFrançois Tigeot //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1786c59a5c48SFrançois Tigeot //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1787c59a5c48SFrançois Tigeot //#define ASIC_EXT_TV_ENCODER_ID 0x06 1788c59a5c48SFrançois Tigeot //#define ASIC_INT_DVO_ENCODER_ID 0x07 1789c59a5c48SFrançois Tigeot //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1790c59a5c48SFrançois Tigeot //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1791c59a5c48SFrançois Tigeot 1792c59a5c48SFrançois Tigeot //ucEncodeMode 1793c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_DP 0 1794c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_LVDS 1 1795c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_DVI 2 1796c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_HDMI 3 1797c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_SDVO 4 1798c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_TV 13 1799c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_CV 14 1800c59a5c48SFrançois Tigeot //#define ATOM_ENCODER_MODE_CRT 15 1801c59a5c48SFrançois Tigeot 1802c59a5c48SFrançois Tigeot 1803c59a5c48SFrançois Tigeot typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1804c59a5c48SFrançois Tigeot { 1805c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1806c59a5c48SFrançois Tigeot UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1807c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1808c59a5c48SFrançois Tigeot UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1809c59a5c48SFrançois Tigeot }SELECT_CRTC_SOURCE_PARAMETERS_V3; 1810c59a5c48SFrançois Tigeot 1811c59a5c48SFrançois Tigeot 1812c59a5c48SFrançois Tigeot /****************************************************************************/ 1813c59a5c48SFrançois Tigeot // Structures used by SetPixelClockTable 1814c59a5c48SFrançois Tigeot // GetPixelClockTable 1815c59a5c48SFrançois Tigeot /****************************************************************************/ 1816c59a5c48SFrançois Tigeot //Major revision=1., Minor revision=1 1817c59a5c48SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS 1818c59a5c48SFrançois Tigeot { 1819c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1820c59a5c48SFrançois Tigeot // 0 means disable PPLL 1821c59a5c48SFrançois Tigeot USHORT usRefDiv; // Reference divider 1822c59a5c48SFrançois Tigeot USHORT usFbDiv; // feedback divider 1823c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // post divider 1824c59a5c48SFrançois Tigeot UCHAR ucFracFbDiv; // fractional feedback divider 1825c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1826c59a5c48SFrançois Tigeot UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1827c59a5c48SFrançois Tigeot UCHAR ucCRTC; // Which CRTC uses this Ppll 1828c59a5c48SFrançois Tigeot UCHAR ucPadding; 1829c59a5c48SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS; 1830c59a5c48SFrançois Tigeot 1831c59a5c48SFrançois Tigeot //Major revision=1., Minor revision=2, add ucMiscIfno 1832c59a5c48SFrançois Tigeot //ucMiscInfo: 1833c59a5c48SFrançois Tigeot #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1834c59a5c48SFrançois Tigeot #define MISC_DEVICE_INDEX_MASK 0xF0 1835c59a5c48SFrançois Tigeot #define MISC_DEVICE_INDEX_SHIFT 4 1836c59a5c48SFrançois Tigeot 1837c59a5c48SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1838c59a5c48SFrançois Tigeot { 1839c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1840c59a5c48SFrançois Tigeot // 0 means disable PPLL 1841c59a5c48SFrançois Tigeot USHORT usRefDiv; // Reference divider 1842c59a5c48SFrançois Tigeot USHORT usFbDiv; // feedback divider 1843c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // post divider 1844c59a5c48SFrançois Tigeot UCHAR ucFracFbDiv; // fractional feedback divider 1845c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1846c59a5c48SFrançois Tigeot UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1847c59a5c48SFrançois Tigeot UCHAR ucCRTC; // Which CRTC uses this Ppll 1848c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1849c59a5c48SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS_V2; 1850c59a5c48SFrançois Tigeot 1851c59a5c48SFrançois Tigeot //Major revision=1., Minor revision=3, structure/definition change 1852c59a5c48SFrançois Tigeot //ucEncoderMode: 1853c59a5c48SFrançois Tigeot //ATOM_ENCODER_MODE_DP 1854c59a5c48SFrançois Tigeot //ATOM_ENOCDER_MODE_LVDS 1855c59a5c48SFrançois Tigeot //ATOM_ENOCDER_MODE_DVI 1856c59a5c48SFrançois Tigeot //ATOM_ENOCDER_MODE_HDMI 1857c59a5c48SFrançois Tigeot //ATOM_ENOCDER_MODE_SDVO 1858c59a5c48SFrançois Tigeot //ATOM_ENCODER_MODE_TV 13 1859c59a5c48SFrançois Tigeot //ATOM_ENCODER_MODE_CV 14 1860c59a5c48SFrançois Tigeot //ATOM_ENCODER_MODE_CRT 15 1861c59a5c48SFrançois Tigeot 1862c59a5c48SFrançois Tigeot //ucDVOConfig 1863c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1864c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1865c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1866c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1867c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1868c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1869c59a5c48SFrançois Tigeot //#define DVO_ENCODER_CONFIG_24BIT 0x08 1870c59a5c48SFrançois Tigeot 1871c59a5c48SFrançois Tigeot //ucMiscInfo: also changed, see below 1872c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1873c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1874c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1875c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1876c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1877c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1878c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1879c59a5c48SFrançois Tigeot // V1.4 for RoadRunner 1880c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1881c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1882c59a5c48SFrançois Tigeot 1883c59a5c48SFrançois Tigeot 1884c59a5c48SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1885c59a5c48SFrançois Tigeot { 1886c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1887c59a5c48SFrançois Tigeot // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1888c59a5c48SFrançois Tigeot USHORT usRefDiv; // Reference divider 1889c59a5c48SFrançois Tigeot USHORT usFbDiv; // feedback divider 1890c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // post divider 1891c59a5c48SFrançois Tigeot UCHAR ucFracFbDiv; // fractional feedback divider 1892c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1893c59a5c48SFrançois Tigeot UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1894c59a5c48SFrançois Tigeot union 1895c59a5c48SFrançois Tigeot { 1896c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1897c59a5c48SFrançois Tigeot UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1898c59a5c48SFrançois Tigeot }; 1899c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1900c59a5c48SFrançois Tigeot // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1901c59a5c48SFrançois Tigeot // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1902c59a5c48SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS_V3; 1903c59a5c48SFrançois Tigeot 1904c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1905c59a5c48SFrançois Tigeot #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1906c59a5c48SFrançois Tigeot 1907c59a5c48SFrançois Tigeot 1908c59a5c48SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1909c59a5c48SFrançois Tigeot { 1910c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1911c59a5c48SFrançois Tigeot // drive the pixel clock. not used for DCPLL case. 1912c59a5c48SFrançois Tigeot union{ 1913c59a5c48SFrançois Tigeot UCHAR ucReserved; 1914c59a5c48SFrançois Tigeot UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1915c59a5c48SFrançois Tigeot }; 1916c59a5c48SFrançois Tigeot USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1917c59a5c48SFrançois Tigeot // 0 means disable PPLL/DCPLL. 1918c59a5c48SFrançois Tigeot USHORT usFbDiv; // feedback divider integer part. 1919c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // post divider. 1920c59a5c48SFrançois Tigeot UCHAR ucRefDiv; // Reference divider 1921c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1922c59a5c48SFrançois Tigeot UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1923c59a5c48SFrançois Tigeot // indicate which graphic encoder will be used. 1924c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; // Encoder mode: 1925c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1926c59a5c48SFrançois Tigeot // bit[1]= when VGA timing is used. 1927c59a5c48SFrançois Tigeot // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1928c59a5c48SFrançois Tigeot // bit[4]= RefClock source for PPLL. 1929c59a5c48SFrançois Tigeot // =0: XTLAIN( default mode ) 1930c59a5c48SFrançois Tigeot // =1: other external clock source, which is pre-defined 1931c59a5c48SFrançois Tigeot // by VBIOS depend on the feature required. 1932c59a5c48SFrançois Tigeot // bit[7:5]: reserved. 1933c59a5c48SFrançois Tigeot ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1934c59a5c48SFrançois Tigeot 1935c59a5c48SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS_V5; 1936c59a5c48SFrançois Tigeot 1937c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1938c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1939c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1940c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1941c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1942c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1943c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1944c59a5c48SFrançois Tigeot 1945c59a5c48SFrançois Tigeot typedef struct _CRTC_PIXEL_CLOCK_FREQ 1946c59a5c48SFrançois Tigeot { 1947c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 1948c59a5c48SFrançois Tigeot ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1949c59a5c48SFrançois Tigeot // drive the pixel clock. not used for DCPLL case. 1950c59a5c48SFrançois Tigeot ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1951c59a5c48SFrançois Tigeot // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1952c59a5c48SFrançois Tigeot #else 1953c59a5c48SFrançois Tigeot ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1954c59a5c48SFrançois Tigeot // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1955c59a5c48SFrançois Tigeot ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1956c59a5c48SFrançois Tigeot // drive the pixel clock. not used for DCPLL case. 1957c59a5c48SFrançois Tigeot #endif 1958c59a5c48SFrançois Tigeot }CRTC_PIXEL_CLOCK_FREQ; 1959c59a5c48SFrançois Tigeot 1960c59a5c48SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1961c59a5c48SFrançois Tigeot { 1962c59a5c48SFrançois Tigeot union{ 1963c59a5c48SFrançois Tigeot CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1964c59a5c48SFrançois Tigeot ULONG ulDispEngClkFreq; // dispclk frequency 1965c59a5c48SFrançois Tigeot }; 1966c59a5c48SFrançois Tigeot USHORT usFbDiv; // feedback divider integer part. 1967c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // post divider. 1968c59a5c48SFrançois Tigeot UCHAR ucRefDiv; // Reference divider 1969c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1970c59a5c48SFrançois Tigeot UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1971c59a5c48SFrançois Tigeot // indicate which graphic encoder will be used. 1972c59a5c48SFrançois Tigeot UCHAR ucEncoderMode; // Encoder mode: 1973c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1974c59a5c48SFrançois Tigeot // bit[1]= when VGA timing is used. 1975c59a5c48SFrançois Tigeot // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1976c59a5c48SFrançois Tigeot // bit[4]= RefClock source for PPLL. 1977c59a5c48SFrançois Tigeot // =0: XTLAIN( default mode ) 1978c59a5c48SFrançois Tigeot // =1: other external clock source, which is pre-defined 1979c59a5c48SFrançois Tigeot // by VBIOS depend on the feature required. 1980c59a5c48SFrançois Tigeot // bit[7:5]: reserved. 1981c59a5c48SFrançois Tigeot ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1982c59a5c48SFrançois Tigeot 1983c59a5c48SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS_V6; 1984c59a5c48SFrançois Tigeot 1985c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1986c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1987c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1988c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1989c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1990c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1991c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1992c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1993c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1994c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1995c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1996c59a5c48SFrançois Tigeot #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 1997c59a5c48SFrançois Tigeot 1998c59a5c48SFrançois Tigeot typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1999c59a5c48SFrançois Tigeot { 2000c59a5c48SFrançois Tigeot PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 2001c59a5c48SFrançois Tigeot }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 2002c59a5c48SFrançois Tigeot 2003c59a5c48SFrançois Tigeot typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 2004c59a5c48SFrançois Tigeot { 2005c59a5c48SFrançois Tigeot UCHAR ucStatus; 2006c59a5c48SFrançois Tigeot UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 2007c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 2008c59a5c48SFrançois Tigeot }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 2009c59a5c48SFrançois Tigeot 2010c59a5c48SFrançois Tigeot typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 2011c59a5c48SFrançois Tigeot { 2012c59a5c48SFrançois Tigeot PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 2013c59a5c48SFrançois Tigeot }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 2014c59a5c48SFrançois Tigeot 2015d78d3a22SFrançois Tigeot typedef struct _PIXEL_CLOCK_PARAMETERS_V7 2016d78d3a22SFrançois Tigeot { 2017d78d3a22SFrançois Tigeot ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2018d78d3a22SFrançois Tigeot 2019d78d3a22SFrançois Tigeot UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2020d78d3a22SFrançois Tigeot UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 2021d78d3a22SFrançois Tigeot // indicate which graphic encoder will be used. 2022d78d3a22SFrançois Tigeot UCHAR ucEncoderMode; // Encoder mode: 2023d78d3a22SFrançois Tigeot UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk 2024d78d3a22SFrançois Tigeot // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) 2025d78d3a22SFrançois Tigeot // bit[5:4]= RefClock source for PPLL. 2026d78d3a22SFrançois Tigeot // =0: XTLAIN( default mode ) 2027d78d3a22SFrançois Tigeot // =1: pcie 2028d78d3a22SFrançois Tigeot // =2: GENLK 2029d78d3a22SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 2030d78d3a22SFrançois Tigeot UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp 2031d78d3a22SFrançois Tigeot UCHAR ucReserved[2]; 2032d78d3a22SFrançois Tigeot ULONG ulReserved; 2033d78d3a22SFrançois Tigeot }PIXEL_CLOCK_PARAMETERS_V7; 2034d78d3a22SFrançois Tigeot 2035d78d3a22SFrançois Tigeot //ucMiscInfo 2036d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01 2037d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02 2038d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04 2039d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08 2040d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30 2041d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00 2042d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10 2043d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20 2044d78d3a22SFrançois Tigeot 2045d78d3a22SFrançois Tigeot //ucDeepColorRatio 2046d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2047d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2048d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2049d78d3a22SFrançois Tigeot #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2050d78d3a22SFrançois Tigeot 2051d78d3a22SFrançois Tigeot // SetDCEClockTable input parameter for DCE11.1 2052d78d3a22SFrançois Tigeot typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1 2053d78d3a22SFrançois Tigeot { 2054d78d3a22SFrançois Tigeot ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz. 2055d78d3a22SFrançois Tigeot UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS 2056d78d3a22SFrançois Tigeot UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1 2057d78d3a22SFrançois Tigeot UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1 2058d78d3a22SFrançois Tigeot UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1 2059d78d3a22SFrançois Tigeot }SET_DCE_CLOCK_PARAMETERS_V1_1; 2060d78d3a22SFrançois Tigeot 2061d78d3a22SFrançois Tigeot 2062d78d3a22SFrançois Tigeot typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 2063d78d3a22SFrançois Tigeot { 2064d78d3a22SFrançois Tigeot SET_DCE_CLOCK_PARAMETERS_V1_1 asParam; 2065d78d3a22SFrançois Tigeot ULONG ulReserved[2]; 2066d78d3a22SFrançois Tigeot }SET_DCE_CLOCK_PS_ALLOCATION_V1_1; 2067d78d3a22SFrançois Tigeot 2068d78d3a22SFrançois Tigeot //SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag 2069d78d3a22SFrançois Tigeot #define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01 2070d78d3a22SFrançois Tigeot #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 2071d78d3a22SFrançois Tigeot #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 2072d78d3a22SFrançois Tigeot 2073d78d3a22SFrançois Tigeot // SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above 2074d78d3a22SFrançois Tigeot typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 2075d78d3a22SFrançois Tigeot { 2076d78d3a22SFrançois Tigeot ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2077d78d3a22SFrançois Tigeot UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2078d78d3a22SFrançois Tigeot UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2079d78d3a22SFrançois Tigeot UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2080d78d3a22SFrançois Tigeot UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2081d78d3a22SFrançois Tigeot }SET_DCE_CLOCK_PARAMETERS_V2_1; 2082d78d3a22SFrançois Tigeot 2083d78d3a22SFrançois Tigeot //ucDCEClkType 2084d78d3a22SFrançois Tigeot #define DCE_CLOCK_TYPE_DISPCLK 0 2085d78d3a22SFrançois Tigeot #define DCE_CLOCK_TYPE_DPREFCLK 1 2086d78d3a22SFrançois Tigeot #define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable 2087d78d3a22SFrançois Tigeot 2088d78d3a22SFrançois Tigeot //ucDCEClkFlag when ucDCEClkType == DPREFCLK 2089d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03 2090d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00 2091d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01 2092d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02 2093d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03 2094d78d3a22SFrançois Tigeot 2095d78d3a22SFrançois Tigeot //ucDCEClkFlag when ucDCEClkType == PIXCLK 2096d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 2097d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2098d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2099d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2100d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2101d78d3a22SFrançois Tigeot #define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04 2102d78d3a22SFrançois Tigeot 2103d78d3a22SFrançois Tigeot typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 2104d78d3a22SFrançois Tigeot { 2105d78d3a22SFrançois Tigeot SET_DCE_CLOCK_PARAMETERS_V2_1 asParam; 2106d78d3a22SFrançois Tigeot ULONG ulReserved[2]; 2107d78d3a22SFrançois Tigeot }SET_DCE_CLOCK_PS_ALLOCATION_V2_1; 2108d78d3a22SFrançois Tigeot 2109d78d3a22SFrançois Tigeot 2110c59a5c48SFrançois Tigeot 2111c59a5c48SFrançois Tigeot /****************************************************************************/ 2112c59a5c48SFrançois Tigeot // Structures used by AdjustDisplayPllTable 2113c59a5c48SFrançois Tigeot /****************************************************************************/ 2114c59a5c48SFrançois Tigeot typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 2115c59a5c48SFrançois Tigeot { 2116c59a5c48SFrançois Tigeot USHORT usPixelClock; 2117c59a5c48SFrançois Tigeot UCHAR ucTransmitterID; 2118c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; 2119c59a5c48SFrançois Tigeot union 2120c59a5c48SFrançois Tigeot { 2121c59a5c48SFrançois Tigeot UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 2122c59a5c48SFrançois Tigeot UCHAR ucConfig; //if none DVO, not defined yet 2123c59a5c48SFrançois Tigeot }; 2124c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 2125c59a5c48SFrançois Tigeot }ADJUST_DISPLAY_PLL_PARAMETERS; 2126c59a5c48SFrançois Tigeot 2127c59a5c48SFrançois Tigeot #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 2128c59a5c48SFrançois Tigeot #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 2129c59a5c48SFrançois Tigeot 2130c59a5c48SFrançois Tigeot typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 2131c59a5c48SFrançois Tigeot { 2132c59a5c48SFrançois Tigeot USHORT usPixelClock; // target pixel clock 2133c59a5c48SFrançois Tigeot UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 2134c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 2135c59a5c48SFrançois Tigeot UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 2136c59a5c48SFrançois Tigeot UCHAR ucExtTransmitterID; // external encoder id. 2137c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 2138c59a5c48SFrançois Tigeot }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 2139c59a5c48SFrançois Tigeot 2140c59a5c48SFrançois Tigeot // usDispPllConfig v1.2 for RoadRunner 2141c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 2142c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 2143c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 2144c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 2145c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 2146c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 2147c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 2148c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 2149c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 2150c59a5c48SFrançois Tigeot #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 2151c59a5c48SFrançois Tigeot 2152c59a5c48SFrançois Tigeot 2153c59a5c48SFrançois Tigeot typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 2154c59a5c48SFrançois Tigeot { 2155c59a5c48SFrançois Tigeot ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 2156c59a5c48SFrançois Tigeot UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 2157c59a5c48SFrançois Tigeot UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 2158c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 2159c59a5c48SFrançois Tigeot }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 2160c59a5c48SFrançois Tigeot 2161c59a5c48SFrançois Tigeot typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 2162c59a5c48SFrançois Tigeot { 2163c59a5c48SFrançois Tigeot union 2164c59a5c48SFrançois Tigeot { 2165c59a5c48SFrançois Tigeot ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 2166c59a5c48SFrançois Tigeot ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 2167c59a5c48SFrançois Tigeot }; 2168c59a5c48SFrançois Tigeot } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 2169c59a5c48SFrançois Tigeot 2170c59a5c48SFrançois Tigeot /****************************************************************************/ 2171c59a5c48SFrançois Tigeot // Structures used by EnableYUVTable 2172c59a5c48SFrançois Tigeot /****************************************************************************/ 2173c59a5c48SFrançois Tigeot typedef struct _ENABLE_YUV_PARAMETERS 2174c59a5c48SFrançois Tigeot { 2175c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 2176c59a5c48SFrançois Tigeot UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 2177c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 2178c59a5c48SFrançois Tigeot }ENABLE_YUV_PARAMETERS; 2179c59a5c48SFrançois Tigeot #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 2180c59a5c48SFrançois Tigeot 2181c59a5c48SFrançois Tigeot /****************************************************************************/ 2182c59a5c48SFrançois Tigeot // Structures used by GetMemoryClockTable 2183c59a5c48SFrançois Tigeot /****************************************************************************/ 2184c59a5c48SFrançois Tigeot typedef struct _GET_MEMORY_CLOCK_PARAMETERS 2185c59a5c48SFrançois Tigeot { 2186c59a5c48SFrançois Tigeot ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 2187c59a5c48SFrançois Tigeot } GET_MEMORY_CLOCK_PARAMETERS; 2188c59a5c48SFrançois Tigeot #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 2189c59a5c48SFrançois Tigeot 2190c59a5c48SFrançois Tigeot /****************************************************************************/ 2191c59a5c48SFrançois Tigeot // Structures used by GetEngineClockTable 2192c59a5c48SFrançois Tigeot /****************************************************************************/ 2193c59a5c48SFrançois Tigeot typedef struct _GET_ENGINE_CLOCK_PARAMETERS 2194c59a5c48SFrançois Tigeot { 2195c59a5c48SFrançois Tigeot ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 2196c59a5c48SFrançois Tigeot } GET_ENGINE_CLOCK_PARAMETERS; 2197c59a5c48SFrançois Tigeot #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 2198c59a5c48SFrançois Tigeot 2199c59a5c48SFrançois Tigeot /****************************************************************************/ 2200c59a5c48SFrançois Tigeot // Following Structures and constant may be obsolete 2201c59a5c48SFrançois Tigeot /****************************************************************************/ 2202c59a5c48SFrançois Tigeot //Maxium 8 bytes,the data read in will be placed in the parameter space. 2203c59a5c48SFrançois Tigeot //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 2204c59a5c48SFrançois Tigeot typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2205c59a5c48SFrançois Tigeot { 2206c59a5c48SFrançois Tigeot USHORT usPrescale; //Ratio between Engine clock and I2C clock 2207c59a5c48SFrançois Tigeot USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 2208c59a5c48SFrançois Tigeot USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 2209c59a5c48SFrançois Tigeot //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 2210c59a5c48SFrançois Tigeot UCHAR ucSlaveAddr; //Read from which slave 2211c59a5c48SFrançois Tigeot UCHAR ucLineNumber; //Read from which HW assisted line 2212c59a5c48SFrançois Tigeot }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 2213c59a5c48SFrançois Tigeot #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2214c59a5c48SFrançois Tigeot 2215c59a5c48SFrançois Tigeot 2216c59a5c48SFrançois Tigeot #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 2217c59a5c48SFrançois Tigeot #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 2218c59a5c48SFrançois Tigeot #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 2219c59a5c48SFrançois Tigeot #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 2220c59a5c48SFrançois Tigeot #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 2221c59a5c48SFrançois Tigeot 2222c59a5c48SFrançois Tigeot typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2223c59a5c48SFrançois Tigeot { 2224c59a5c48SFrançois Tigeot USHORT usPrescale; //Ratio between Engine clock and I2C clock 2225c59a5c48SFrançois Tigeot USHORT usByteOffset; //Write to which byte 2226c59a5c48SFrançois Tigeot //Upper portion of usByteOffset is Format of data 2227c59a5c48SFrançois Tigeot //1bytePS+offsetPS 2228c59a5c48SFrançois Tigeot //2bytesPS+offsetPS 2229c59a5c48SFrançois Tigeot //blockID+offsetPS 2230c59a5c48SFrançois Tigeot //blockID+offsetID 2231c59a5c48SFrançois Tigeot //blockID+counterID+offsetID 2232c59a5c48SFrançois Tigeot UCHAR ucData; //PS data1 2233c59a5c48SFrançois Tigeot UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 2234c59a5c48SFrançois Tigeot UCHAR ucSlaveAddr; //Write to which slave 2235c59a5c48SFrançois Tigeot UCHAR ucLineNumber; //Write from which HW assisted line 2236c59a5c48SFrançois Tigeot }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 2237c59a5c48SFrançois Tigeot 2238c59a5c48SFrançois Tigeot #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2239c59a5c48SFrançois Tigeot 2240c59a5c48SFrançois Tigeot typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 2241c59a5c48SFrançois Tigeot { 2242c59a5c48SFrançois Tigeot USHORT usPrescale; //Ratio between Engine clock and I2C clock 2243c59a5c48SFrançois Tigeot UCHAR ucSlaveAddr; //Write to which slave 2244c59a5c48SFrançois Tigeot UCHAR ucLineNumber; //Write from which HW assisted line 2245c59a5c48SFrançois Tigeot }SET_UP_HW_I2C_DATA_PARAMETERS; 2246c59a5c48SFrançois Tigeot 2247c59a5c48SFrançois Tigeot /**************************************************************************/ 2248c59a5c48SFrançois Tigeot #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2249c59a5c48SFrançois Tigeot 2250c59a5c48SFrançois Tigeot 2251c59a5c48SFrançois Tigeot /****************************************************************************/ 2252c59a5c48SFrançois Tigeot // Structures used by PowerConnectorDetectionTable 2253c59a5c48SFrançois Tigeot /****************************************************************************/ 2254c59a5c48SFrançois Tigeot typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 2255c59a5c48SFrançois Tigeot { 2256c59a5c48SFrançois Tigeot UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2257c59a5c48SFrançois Tigeot UCHAR ucPwrBehaviorId; 2258c59a5c48SFrançois Tigeot USHORT usPwrBudget; //how much power currently boot to in unit of watt 2259c59a5c48SFrançois Tigeot }POWER_CONNECTOR_DETECTION_PARAMETERS; 2260c59a5c48SFrançois Tigeot 2261c59a5c48SFrançois Tigeot typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 2262c59a5c48SFrançois Tigeot { 2263c59a5c48SFrançois Tigeot UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2264c59a5c48SFrançois Tigeot UCHAR ucReserved; 2265c59a5c48SFrançois Tigeot USHORT usPwrBudget; //how much power currently boot to in unit of watt 2266c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2267c59a5c48SFrançois Tigeot }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 2268c59a5c48SFrançois Tigeot 2269c59a5c48SFrançois Tigeot 2270c59a5c48SFrançois Tigeot /****************************LVDS SS Command Table Definitions**********************/ 2271c59a5c48SFrançois Tigeot 2272c59a5c48SFrançois Tigeot /****************************************************************************/ 2273c59a5c48SFrançois Tigeot // Structures used by EnableSpreadSpectrumOnPPLLTable 2274c59a5c48SFrançois Tigeot /****************************************************************************/ 2275c59a5c48SFrançois Tigeot typedef struct _ENABLE_LVDS_SS_PARAMETERS 2276c59a5c48SFrançois Tigeot { 2277c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; 2278c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2279c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 2280c59a5c48SFrançois Tigeot UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2281c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 2282c59a5c48SFrançois Tigeot }ENABLE_LVDS_SS_PARAMETERS; 2283c59a5c48SFrançois Tigeot 2284c59a5c48SFrançois Tigeot //ucTableFormatRevision=1,ucTableContentRevision=2 2285c59a5c48SFrançois Tigeot typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 2286c59a5c48SFrançois Tigeot { 2287c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; 2288c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2289c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumStep; // 2290c59a5c48SFrançois Tigeot UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2291c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumDelay; 2292c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumRange; 2293c59a5c48SFrançois Tigeot UCHAR ucPadding; 2294c59a5c48SFrançois Tigeot }ENABLE_LVDS_SS_PARAMETERS_V2; 2295c59a5c48SFrançois Tigeot 2296c59a5c48SFrançois Tigeot //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 2297c59a5c48SFrançois Tigeot typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 2298c59a5c48SFrançois Tigeot { 2299c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; 2300c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2301c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumStep; // 2302c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2303c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumDelay; 2304c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumRange; 2305c59a5c48SFrançois Tigeot UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 2306c59a5c48SFrançois Tigeot }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 2307c59a5c48SFrançois Tigeot 2308c59a5c48SFrançois Tigeot typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 2309c59a5c48SFrançois Tigeot { 2310c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; 2311c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2312c59a5c48SFrançois Tigeot // Bit[1]: 1-Ext. 0-Int. 2313c59a5c48SFrançois Tigeot // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2314c59a5c48SFrançois Tigeot // Bits[7:4] reserved 2315c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2316c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2317c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2318c59a5c48SFrançois Tigeot }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 2319c59a5c48SFrançois Tigeot 2320c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 2321c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 2322c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 2323c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 2324c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 2325c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 2326c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 2327c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2328c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2329c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2330c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2331c59a5c48SFrançois Tigeot 2332c59a5c48SFrançois Tigeot // Used by DCE5.0 2333c59a5c48SFrançois Tigeot typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2334c59a5c48SFrançois Tigeot { 2335c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2336c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2337c59a5c48SFrançois Tigeot // Bit[1]: 1-Ext. 0-Int. 2338c59a5c48SFrançois Tigeot // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2339c59a5c48SFrançois Tigeot // Bits[7:4] reserved 2340c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2341c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2342c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2343c59a5c48SFrançois Tigeot }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2344c59a5c48SFrançois Tigeot 2345c59a5c48SFrançois Tigeot 2346c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2347c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2348c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2349c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2350c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2351c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2352c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2353c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2354c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2355c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2356c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2357c59a5c48SFrançois Tigeot #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2358c59a5c48SFrançois Tigeot 2359c59a5c48SFrançois Tigeot #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2360c59a5c48SFrançois Tigeot 2361c59a5c48SFrançois Tigeot typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2362c59a5c48SFrançois Tigeot { 2363c59a5c48SFrançois Tigeot PIXEL_CLOCK_PARAMETERS sPCLKInput; 2364c59a5c48SFrançois Tigeot ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2365c59a5c48SFrançois Tigeot }SET_PIXEL_CLOCK_PS_ALLOCATION; 2366c59a5c48SFrançois Tigeot 2367c59a5c48SFrançois Tigeot 2368c59a5c48SFrançois Tigeot 2369c59a5c48SFrançois Tigeot #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2370c59a5c48SFrançois Tigeot 2371c59a5c48SFrançois Tigeot /****************************************************************************/ 2372c59a5c48SFrançois Tigeot // Structures used by ### 2373c59a5c48SFrançois Tigeot /****************************************************************************/ 2374c59a5c48SFrançois Tigeot typedef struct _MEMORY_TRAINING_PARAMETERS 2375c59a5c48SFrançois Tigeot { 2376c59a5c48SFrançois Tigeot ULONG ulTargetMemoryClock; //In 10Khz unit 2377c59a5c48SFrançois Tigeot }MEMORY_TRAINING_PARAMETERS; 2378c59a5c48SFrançois Tigeot #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2379c59a5c48SFrançois Tigeot 2380c59a5c48SFrançois Tigeot 2381c59a5c48SFrançois Tigeot typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2382c59a5c48SFrançois Tigeot { 2383c59a5c48SFrançois Tigeot USHORT usMemTrainingMode; 2384c59a5c48SFrançois Tigeot USHORT usReserved; 2385c59a5c48SFrançois Tigeot }MEMORY_TRAINING_PARAMETERS_V1_2; 2386c59a5c48SFrançois Tigeot 2387c59a5c48SFrançois Tigeot //usMemTrainingMode 2388c59a5c48SFrançois Tigeot #define NORMAL_MEMORY_TRAINING_MODE 0 2389c59a5c48SFrançois Tigeot #define ENTER_DRAM_SELFREFRESH_MODE 1 2390c59a5c48SFrançois Tigeot #define EXIT_DRAM_SELFRESH_MODE 2 2391c59a5c48SFrançois Tigeot 2392c59a5c48SFrançois Tigeot /****************************LVDS and other encoder command table definitions **********************/ 2393c59a5c48SFrançois Tigeot 2394c59a5c48SFrançois Tigeot 2395c59a5c48SFrançois Tigeot /****************************************************************************/ 2396c59a5c48SFrançois Tigeot // Structures used by LVDSEncoderControlTable (Before DEC30) 2397c59a5c48SFrançois Tigeot // LVTMAEncoderControlTable (Before DEC30) 2398c59a5c48SFrançois Tigeot // TMDSAEncoderControlTable (Before DEC30) 2399c59a5c48SFrançois Tigeot /****************************************************************************/ 2400c59a5c48SFrançois Tigeot typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2401c59a5c48SFrançois Tigeot { 2402c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 2403c59a5c48SFrançois Tigeot UCHAR ucMisc; // bit0=0: Enable single link 2404c59a5c48SFrançois Tigeot // =1: Enable dual link 2405c59a5c48SFrançois Tigeot // Bit1=0: 666RGB 2406c59a5c48SFrançois Tigeot // =1: 888RGB 2407c59a5c48SFrançois Tigeot UCHAR ucAction; // 0: turn off encoder 2408c59a5c48SFrançois Tigeot // 1: setup and turn on encoder 2409c59a5c48SFrançois Tigeot }LVDS_ENCODER_CONTROL_PARAMETERS; 2410c59a5c48SFrançois Tigeot 2411c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2412c59a5c48SFrançois Tigeot 2413c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2414c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2415c59a5c48SFrançois Tigeot 2416c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2417c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2418c59a5c48SFrançois Tigeot 2419c59a5c48SFrançois Tigeot //ucTableFormatRevision=1,ucTableContentRevision=2 2420c59a5c48SFrançois Tigeot typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2421c59a5c48SFrançois Tigeot { 2422c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 2423c59a5c48SFrançois Tigeot UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2424c59a5c48SFrançois Tigeot UCHAR ucAction; // 0: turn off encoder 2425c59a5c48SFrançois Tigeot // 1: setup and turn on encoder 2426c59a5c48SFrançois Tigeot UCHAR ucTruncate; // bit0=0: Disable truncate 2427c59a5c48SFrançois Tigeot // =1: Enable truncate 2428c59a5c48SFrançois Tigeot // bit4=0: 666RGB 2429c59a5c48SFrançois Tigeot // =1: 888RGB 2430c59a5c48SFrançois Tigeot UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2431c59a5c48SFrançois Tigeot // =1: Enable spatial dithering 2432c59a5c48SFrançois Tigeot // bit4=0: 666RGB 2433c59a5c48SFrançois Tigeot // =1: 888RGB 2434c59a5c48SFrançois Tigeot UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2435c59a5c48SFrançois Tigeot // =1: Enable temporal dithering 2436c59a5c48SFrançois Tigeot // bit4=0: 666RGB 2437c59a5c48SFrançois Tigeot // =1: 888RGB 2438c59a5c48SFrançois Tigeot // bit5=0: Gray level 2 2439c59a5c48SFrançois Tigeot // =1: Gray level 4 2440c59a5c48SFrançois Tigeot UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2441c59a5c48SFrançois Tigeot // =1: 25FRC_SEL pattern F 2442c59a5c48SFrançois Tigeot // bit6:5=0: 50FRC_SEL pattern A 2443c59a5c48SFrançois Tigeot // =1: 50FRC_SEL pattern B 2444c59a5c48SFrançois Tigeot // =2: 50FRC_SEL pattern C 2445c59a5c48SFrançois Tigeot // =3: 50FRC_SEL pattern D 2446c59a5c48SFrançois Tigeot // bit7=0: 75FRC_SEL pattern E 2447c59a5c48SFrançois Tigeot // =1: 75FRC_SEL pattern F 2448c59a5c48SFrançois Tigeot }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2449c59a5c48SFrançois Tigeot 2450c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2451c59a5c48SFrançois Tigeot 2452c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2453c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2454c59a5c48SFrançois Tigeot 2455c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2456c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2457c59a5c48SFrançois Tigeot 2458c59a5c48SFrançois Tigeot 2459c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2460c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2461c59a5c48SFrançois Tigeot 2462c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2463c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2464c59a5c48SFrançois Tigeot 2465c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2466c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2467c59a5c48SFrançois Tigeot 2468c59a5c48SFrançois Tigeot /****************************************************************************/ 2469c59a5c48SFrançois Tigeot // Structures used by ### 2470c59a5c48SFrançois Tigeot /****************************************************************************/ 2471c59a5c48SFrançois Tigeot typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2472c59a5c48SFrançois Tigeot { 2473c59a5c48SFrançois Tigeot UCHAR ucEnable; // Enable or Disable External TMDS encoder 2474c59a5c48SFrançois Tigeot UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2475c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 2476c59a5c48SFrançois Tigeot }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2477c59a5c48SFrançois Tigeot 2478c59a5c48SFrançois Tigeot typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2479c59a5c48SFrançois Tigeot { 2480c59a5c48SFrançois Tigeot ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2481c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2482c59a5c48SFrançois Tigeot }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2483c59a5c48SFrançois Tigeot 2484c59a5c48SFrançois Tigeot #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2485c59a5c48SFrançois Tigeot typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2486c59a5c48SFrançois Tigeot { 2487c59a5c48SFrançois Tigeot ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2488c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2489c59a5c48SFrançois Tigeot }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2490c59a5c48SFrançois Tigeot 2491c59a5c48SFrançois Tigeot typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2492c59a5c48SFrançois Tigeot { 2493c59a5c48SFrançois Tigeot DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2494c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2495c59a5c48SFrançois Tigeot }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2496c59a5c48SFrançois Tigeot 2497c59a5c48SFrançois Tigeot /****************************************************************************/ 2498c59a5c48SFrançois Tigeot // Structures used by DVOEncoderControlTable 2499c59a5c48SFrançois Tigeot /****************************************************************************/ 2500c59a5c48SFrançois Tigeot //ucTableFormatRevision=1,ucTableContentRevision=3 2501c59a5c48SFrançois Tigeot //ucDVOConfig: 2502c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2503c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2504c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2505c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2506c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2507c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2508c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONFIG_24BIT 0x08 2509c59a5c48SFrançois Tigeot 2510c59a5c48SFrançois Tigeot typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2511c59a5c48SFrançois Tigeot { 2512c59a5c48SFrançois Tigeot USHORT usPixelClock; 2513c59a5c48SFrançois Tigeot UCHAR ucDVOConfig; 2514c59a5c48SFrançois Tigeot UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2515c59a5c48SFrançois Tigeot UCHAR ucReseved[4]; 2516c59a5c48SFrançois Tigeot }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2517c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2518c59a5c48SFrançois Tigeot 2519c59a5c48SFrançois Tigeot typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2520c59a5c48SFrançois Tigeot { 2521c59a5c48SFrançois Tigeot USHORT usPixelClock; 2522c59a5c48SFrançois Tigeot UCHAR ucDVOConfig; 2523c59a5c48SFrançois Tigeot UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2524c59a5c48SFrançois Tigeot UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2525c59a5c48SFrançois Tigeot UCHAR ucReseved[3]; 2526c59a5c48SFrançois Tigeot }DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2527c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2528c59a5c48SFrançois Tigeot 2529c59a5c48SFrançois Tigeot 2530c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 2531c59a5c48SFrançois Tigeot //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2532c59a5c48SFrançois Tigeot // bit1=0: non-coherent mode 2533c59a5c48SFrançois Tigeot // =1: coherent mode 2534c59a5c48SFrançois Tigeot 2535c59a5c48SFrançois Tigeot //========================================================================================== 2536c59a5c48SFrançois Tigeot //Only change is here next time when changing encoder parameter definitions again! 2537c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2538c59a5c48SFrançois Tigeot #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2539c59a5c48SFrançois Tigeot 2540c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2541c59a5c48SFrançois Tigeot #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2542c59a5c48SFrançois Tigeot 2543c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2544c59a5c48SFrançois Tigeot #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2545c59a5c48SFrançois Tigeot 2546c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2547c59a5c48SFrançois Tigeot #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2548c59a5c48SFrançois Tigeot 2549c59a5c48SFrançois Tigeot //========================================================================================== 2550c59a5c48SFrançois Tigeot #define PANEL_ENCODER_MISC_DUAL 0x01 2551c59a5c48SFrançois Tigeot #define PANEL_ENCODER_MISC_COHERENT 0x02 2552c59a5c48SFrançois Tigeot #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2553c59a5c48SFrançois Tigeot #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2554c59a5c48SFrançois Tigeot 2555c59a5c48SFrançois Tigeot #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2556c59a5c48SFrançois Tigeot #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2557c59a5c48SFrançois Tigeot #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2558c59a5c48SFrançois Tigeot 2559c59a5c48SFrançois Tigeot #define PANEL_ENCODER_TRUNCATE_EN 0x01 2560c59a5c48SFrançois Tigeot #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2561c59a5c48SFrançois Tigeot #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2562c59a5c48SFrançois Tigeot #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2563c59a5c48SFrançois Tigeot #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2564c59a5c48SFrançois Tigeot #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2565c59a5c48SFrançois Tigeot #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2566c59a5c48SFrançois Tigeot #define PANEL_ENCODER_25FRC_MASK 0x10 2567c59a5c48SFrançois Tigeot #define PANEL_ENCODER_25FRC_E 0x00 2568c59a5c48SFrançois Tigeot #define PANEL_ENCODER_25FRC_F 0x10 2569c59a5c48SFrançois Tigeot #define PANEL_ENCODER_50FRC_MASK 0x60 2570c59a5c48SFrançois Tigeot #define PANEL_ENCODER_50FRC_A 0x00 2571c59a5c48SFrançois Tigeot #define PANEL_ENCODER_50FRC_B 0x20 2572c59a5c48SFrançois Tigeot #define PANEL_ENCODER_50FRC_C 0x40 2573c59a5c48SFrançois Tigeot #define PANEL_ENCODER_50FRC_D 0x60 2574c59a5c48SFrançois Tigeot #define PANEL_ENCODER_75FRC_MASK 0x80 2575c59a5c48SFrançois Tigeot #define PANEL_ENCODER_75FRC_E 0x00 2576c59a5c48SFrançois Tigeot #define PANEL_ENCODER_75FRC_F 0x80 2577c59a5c48SFrançois Tigeot 2578c59a5c48SFrançois Tigeot /****************************************************************************/ 2579c59a5c48SFrançois Tigeot // Structures used by SetVoltageTable 2580c59a5c48SFrançois Tigeot /****************************************************************************/ 2581c59a5c48SFrançois Tigeot #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2582c59a5c48SFrançois Tigeot #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2583c59a5c48SFrançois Tigeot #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2584c59a5c48SFrançois Tigeot #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2585c59a5c48SFrançois Tigeot #define SET_VOLTAGE_INIT_MODE 5 2586c59a5c48SFrançois Tigeot #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2587c59a5c48SFrançois Tigeot 2588c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2589c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2590c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2591c59a5c48SFrançois Tigeot 2592c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2593c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2594c59a5c48SFrançois Tigeot #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2595c59a5c48SFrançois Tigeot 2596c59a5c48SFrançois Tigeot typedef struct _SET_VOLTAGE_PARAMETERS 2597c59a5c48SFrançois Tigeot { 2598c59a5c48SFrançois Tigeot UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2599c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2600c59a5c48SFrançois Tigeot UCHAR ucVoltageIndex; // An index to tell which voltage level 2601c59a5c48SFrançois Tigeot UCHAR ucReserved; 2602c59a5c48SFrançois Tigeot }SET_VOLTAGE_PARAMETERS; 2603c59a5c48SFrançois Tigeot 2604c59a5c48SFrançois Tigeot typedef struct _SET_VOLTAGE_PARAMETERS_V2 2605c59a5c48SFrançois Tigeot { 2606c59a5c48SFrançois Tigeot UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2607c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2608c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // real voltage level 2609c59a5c48SFrançois Tigeot }SET_VOLTAGE_PARAMETERS_V2; 2610c59a5c48SFrançois Tigeot 2611c59a5c48SFrançois Tigeot // used by both SetVoltageTable v1.3 and v1.4 2612c59a5c48SFrançois Tigeot typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2613c59a5c48SFrançois Tigeot { 2614c59a5c48SFrançois Tigeot UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2615c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; // Indicate action: Set voltage level 2616c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2617c59a5c48SFrançois Tigeot }SET_VOLTAGE_PARAMETERS_V1_3; 2618c59a5c48SFrançois Tigeot 2619c59a5c48SFrançois Tigeot //ucVoltageType 2620c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_VDDC 1 2621c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_MVDDC 2 2622c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_MVDDQ 3 2623c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_VDDCI 4 2624c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_VDDGFX 5 2625c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_PCC 6 2626d78d3a22SFrançois Tigeot #define VOLTAGE_TYPE_MVPP 7 2627d78d3a22SFrançois Tigeot #define VOLTAGE_TYPE_LEDDPM 8 2628d78d3a22SFrançois Tigeot #define VOLTAGE_TYPE_PCC_MVDD 9 2629d78d3a22SFrançois Tigeot #define VOLTAGE_TYPE_PCIE_VDDC 10 2630d78d3a22SFrançois Tigeot #define VOLTAGE_TYPE_PCIE_VDDR 11 2631c59a5c48SFrançois Tigeot 2632c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2633c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2634c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2635c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2636c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2637c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2638c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2639c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2640c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2641c59a5c48SFrançois Tigeot #define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2642c59a5c48SFrançois Tigeot 2643c59a5c48SFrançois Tigeot //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2644c59a5c48SFrançois Tigeot #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2645c59a5c48SFrançois Tigeot #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2646c59a5c48SFrançois Tigeot #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2647c59a5c48SFrançois Tigeot #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2648c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2649c59a5c48SFrançois Tigeot #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2650c59a5c48SFrançois Tigeot 2651c59a5c48SFrançois Tigeot // define vitual voltage id in usVoltageLevel 2652c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2653c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2654c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2655c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2656c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2657c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2658c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2659c59a5c48SFrançois Tigeot #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2660c59a5c48SFrançois Tigeot 2661c59a5c48SFrançois Tigeot typedef struct _SET_VOLTAGE_PS_ALLOCATION 2662c59a5c48SFrançois Tigeot { 2663c59a5c48SFrançois Tigeot SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2664c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2665c59a5c48SFrançois Tigeot }SET_VOLTAGE_PS_ALLOCATION; 2666c59a5c48SFrançois Tigeot 2667c59a5c48SFrançois Tigeot // New Added from SI for GetVoltageInfoTable, input parameter structure 2668c59a5c48SFrançois Tigeot typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2669c59a5c48SFrançois Tigeot { 2670c59a5c48SFrançois Tigeot UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2671c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2672c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2673c59a5c48SFrançois Tigeot ULONG ulReserved; 2674c59a5c48SFrançois Tigeot }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2675c59a5c48SFrançois Tigeot 2676c59a5c48SFrançois Tigeot // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2677c59a5c48SFrançois Tigeot typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2678c59a5c48SFrançois Tigeot { 2679c59a5c48SFrançois Tigeot ULONG ulVotlageGpioState; 2680c59a5c48SFrançois Tigeot ULONG ulVoltageGPioMask; 2681c59a5c48SFrançois Tigeot }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2682c59a5c48SFrançois Tigeot 2683c59a5c48SFrançois Tigeot // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2684c59a5c48SFrançois Tigeot typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2685c59a5c48SFrançois Tigeot { 2686c59a5c48SFrançois Tigeot USHORT usVoltageLevel; 2687c59a5c48SFrançois Tigeot USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2688c59a5c48SFrançois Tigeot ULONG ulReseved; 2689c59a5c48SFrançois Tigeot }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2690c59a5c48SFrançois Tigeot 2691c59a5c48SFrançois Tigeot // GetVoltageInfo v1.1 ucVoltageMode 2692c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_VID 0x00 2693c59a5c48SFrançois Tigeot #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2694c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2695c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2696c59a5c48SFrançois Tigeot 2697c59a5c48SFrançois Tigeot // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2698c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2699c59a5c48SFrançois Tigeot // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2700c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2701c59a5c48SFrançois Tigeot 2702c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2703c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2704c59a5c48SFrançois Tigeot 2705c59a5c48SFrançois Tigeot 2706c59a5c48SFrançois Tigeot // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2707c59a5c48SFrançois Tigeot typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2708c59a5c48SFrançois Tigeot { 2709c59a5c48SFrançois Tigeot UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2710c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2711c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2712c59a5c48SFrançois Tigeot ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2713c59a5c48SFrançois Tigeot }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2714c59a5c48SFrançois Tigeot 2715c59a5c48SFrançois Tigeot // New in GetVoltageInfo v1.2 ucVoltageMode 2716c59a5c48SFrançois Tigeot #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2717c59a5c48SFrançois Tigeot 2718c59a5c48SFrançois Tigeot // New Added from CI Hawaii for EVV feature 2719c59a5c48SFrançois Tigeot typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2720c59a5c48SFrançois Tigeot { 2721c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // real voltage level in unit of mv 2722c59a5c48SFrançois Tigeot USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2723c59a5c48SFrançois Tigeot USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2724c59a5c48SFrançois Tigeot USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2725c59a5c48SFrançois Tigeot }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2726c59a5c48SFrançois Tigeot 2727d78d3a22SFrançois Tigeot 2728d78d3a22SFrançois Tigeot // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2729d78d3a22SFrançois Tigeot typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 2730d78d3a22SFrançois Tigeot { 2731d78d3a22SFrançois Tigeot UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2732d78d3a22SFrançois Tigeot UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2733d78d3a22SFrançois Tigeot USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2734d78d3a22SFrançois Tigeot ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2735d78d3a22SFrançois Tigeot ULONG ulReserved[3]; 2736d78d3a22SFrançois Tigeot }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; 2737d78d3a22SFrançois Tigeot 2738d78d3a22SFrançois Tigeot // New Added from CI Hawaii for EVV feature 2739d78d3a22SFrançois Tigeot typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 2740d78d3a22SFrançois Tigeot { 2741d78d3a22SFrançois Tigeot ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv 2742d78d3a22SFrançois Tigeot ULONG ulReserved[4]; 2743d78d3a22SFrançois Tigeot }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; 2744d78d3a22SFrançois Tigeot 2745d78d3a22SFrançois Tigeot 2746d78d3a22SFrançois Tigeot /****************************************************************************/ 2747d78d3a22SFrançois Tigeot // Structures used by GetSMUClockInfo 2748d78d3a22SFrançois Tigeot /****************************************************************************/ 2749d78d3a22SFrançois Tigeot typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 2750d78d3a22SFrançois Tigeot { 2751d78d3a22SFrançois Tigeot ULONG ulDfsPllOutputFreq:24; 2752d78d3a22SFrançois Tigeot ULONG ucDfsDivider:8; 2753d78d3a22SFrançois Tigeot }GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; 2754d78d3a22SFrançois Tigeot 2755d78d3a22SFrançois Tigeot typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 2756d78d3a22SFrançois Tigeot { 2757d78d3a22SFrançois Tigeot ULONG ulDfsOutputFreq; 2758d78d3a22SFrançois Tigeot }GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; 2759d78d3a22SFrançois Tigeot 2760c59a5c48SFrançois Tigeot /****************************************************************************/ 2761c59a5c48SFrançois Tigeot // Structures used by TVEncoderControlTable 2762c59a5c48SFrançois Tigeot /****************************************************************************/ 2763c59a5c48SFrançois Tigeot typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2764c59a5c48SFrançois Tigeot { 2765c59a5c48SFrançois Tigeot USHORT usPixelClock; // in 10KHz; for bios convenient 2766c59a5c48SFrançois Tigeot UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2767c59a5c48SFrançois Tigeot UCHAR ucAction; // 0: turn off encoder 2768c59a5c48SFrançois Tigeot // 1: setup and turn on encoder 2769c59a5c48SFrançois Tigeot }TV_ENCODER_CONTROL_PARAMETERS; 2770c59a5c48SFrançois Tigeot 2771c59a5c48SFrançois Tigeot typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2772c59a5c48SFrançois Tigeot { 2773c59a5c48SFrançois Tigeot TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2774c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2775c59a5c48SFrançois Tigeot }TV_ENCODER_CONTROL_PS_ALLOCATION; 2776c59a5c48SFrançois Tigeot 2777c59a5c48SFrançois Tigeot //==============================Data Table Portion==================================== 2778c59a5c48SFrançois Tigeot 2779c59a5c48SFrançois Tigeot 2780c59a5c48SFrançois Tigeot /****************************************************************************/ 2781c59a5c48SFrançois Tigeot // Structure used in Data.mtb 2782c59a5c48SFrançois Tigeot /****************************************************************************/ 2783c59a5c48SFrançois Tigeot typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2784c59a5c48SFrançois Tigeot { 2785c59a5c48SFrançois Tigeot USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2786c59a5c48SFrançois Tigeot USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2787c59a5c48SFrançois Tigeot USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2788c59a5c48SFrançois Tigeot USHORT StandardVESA_Timing; // Only used by Bios 2789c59a5c48SFrançois Tigeot USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2790c59a5c48SFrançois Tigeot USHORT PaletteData; // Only used by BIOS 2791c59a5c48SFrançois Tigeot USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2792c59a5c48SFrançois Tigeot USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2793d78d3a22SFrançois Tigeot USHORT SMU_Info; // Shared by various SW components,latest version 1.1 2794c59a5c48SFrançois Tigeot USHORT SupportedDevicesInfo; // Will be obsolete from R600 2795c59a5c48SFrançois Tigeot USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2796c59a5c48SFrançois Tigeot USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2797c59a5c48SFrançois Tigeot USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2798c59a5c48SFrançois Tigeot USHORT VESA_ToInternalModeLUT; // Only used by Bios 2799d78d3a22SFrançois Tigeot USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600 2800c59a5c48SFrançois Tigeot USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2801c59a5c48SFrançois Tigeot USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2802c59a5c48SFrançois Tigeot USHORT SaveRestoreInfo; // Only used by Bios 2803c59a5c48SFrançois Tigeot USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2804c59a5c48SFrançois Tigeot USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2805c59a5c48SFrançois Tigeot USHORT XTMDS_Info; // Will be obsolete from R600 2806c59a5c48SFrançois Tigeot USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2807c59a5c48SFrançois Tigeot USHORT Object_Header; // Shared by various SW components,latest version 1.1 2808c59a5c48SFrançois Tigeot USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2809c59a5c48SFrançois Tigeot USHORT MC_InitParameter; // Only used by command table 2810c59a5c48SFrançois Tigeot USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2811c59a5c48SFrançois Tigeot USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2812c59a5c48SFrançois Tigeot USHORT TV_VideoMode; // Only used by command table 2813c59a5c48SFrançois Tigeot USHORT VRAM_Info; // Only used by command table, latest version 1.3 2814c59a5c48SFrançois Tigeot USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2815c59a5c48SFrançois Tigeot USHORT IntegratedSystemInfo; // Shared by various SW components 2816c59a5c48SFrançois Tigeot USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2817c59a5c48SFrançois Tigeot USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2818c59a5c48SFrançois Tigeot USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2819c59a5c48SFrançois Tigeot USHORT ServiceInfo; 2820c59a5c48SFrançois Tigeot }ATOM_MASTER_LIST_OF_DATA_TABLES; 2821c59a5c48SFrançois Tigeot 2822c59a5c48SFrançois Tigeot typedef struct _ATOM_MASTER_DATA_TABLE 2823c59a5c48SFrançois Tigeot { 2824c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 2825c59a5c48SFrançois Tigeot ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2826c59a5c48SFrançois Tigeot }ATOM_MASTER_DATA_TABLE; 2827c59a5c48SFrançois Tigeot 2828c59a5c48SFrançois Tigeot // For backward compatible 2829c59a5c48SFrançois Tigeot #define LVDS_Info LCD_Info 2830c59a5c48SFrançois Tigeot #define DAC_Info PaletteData 2831c59a5c48SFrançois Tigeot #define TMDS_Info DIGTransmitterInfo 2832c59a5c48SFrançois Tigeot #define CompassionateData GPUVirtualizationInfo 2833d78d3a22SFrançois Tigeot #define AnalogTV_Info SMU_Info 2834d78d3a22SFrançois Tigeot #define ComponentVideoInfo GFX_Info 2835c59a5c48SFrançois Tigeot 2836c59a5c48SFrançois Tigeot /****************************************************************************/ 2837c59a5c48SFrançois Tigeot // Structure used in MultimediaCapabilityInfoTable 2838c59a5c48SFrançois Tigeot /****************************************************************************/ 2839c59a5c48SFrançois Tigeot typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2840c59a5c48SFrançois Tigeot { 2841c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 2842c59a5c48SFrançois Tigeot ULONG ulSignature; // HW info table signature string "$ATI" 2843c59a5c48SFrançois Tigeot UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2844c59a5c48SFrançois Tigeot UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2845c59a5c48SFrançois Tigeot UCHAR ucVideoPortInfo; // Provides the video port capabilities 2846c59a5c48SFrançois Tigeot UCHAR ucHostPortInfo; // Provides host port configuration information 2847c59a5c48SFrançois Tigeot }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2848c59a5c48SFrançois Tigeot 2849c59a5c48SFrançois Tigeot 2850c59a5c48SFrançois Tigeot /****************************************************************************/ 2851c59a5c48SFrançois Tigeot // Structure used in MultimediaConfigInfoTable 2852c59a5c48SFrançois Tigeot /****************************************************************************/ 2853c59a5c48SFrançois Tigeot typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2854c59a5c48SFrançois Tigeot { 2855c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 2856c59a5c48SFrançois Tigeot ULONG ulSignature; // MM info table signature sting "$MMT" 2857c59a5c48SFrançois Tigeot UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2858c59a5c48SFrançois Tigeot UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2859c59a5c48SFrançois Tigeot UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2860c59a5c48SFrançois Tigeot UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2861c59a5c48SFrançois Tigeot UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2862c59a5c48SFrançois Tigeot UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2863c59a5c48SFrançois Tigeot UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2864c59a5c48SFrançois Tigeot UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2865c59a5c48SFrançois Tigeot UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2866c59a5c48SFrançois Tigeot UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2867c59a5c48SFrançois Tigeot UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2868c59a5c48SFrançois Tigeot UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2869c59a5c48SFrançois Tigeot }ATOM_MULTIMEDIA_CONFIG_INFO; 2870c59a5c48SFrançois Tigeot 2871c59a5c48SFrançois Tigeot 2872c59a5c48SFrançois Tigeot /****************************************************************************/ 2873c59a5c48SFrançois Tigeot // Structures used in FirmwareInfoTable 2874c59a5c48SFrançois Tigeot /****************************************************************************/ 2875c59a5c48SFrançois Tigeot 2876c59a5c48SFrançois Tigeot // usBIOSCapability Defintion: 2877c59a5c48SFrançois Tigeot // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2878c59a5c48SFrançois Tigeot // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2879c59a5c48SFrançois Tigeot // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2880c59a5c48SFrançois Tigeot // Others: Reserved 2881c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2882c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2883c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2884c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2885c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2886c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2887c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2888c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2889c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2890c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2891c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2892c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2893c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2894c59a5c48SFrançois Tigeot #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2895c59a5c48SFrançois Tigeot 2896c59a5c48SFrançois Tigeot 2897c59a5c48SFrançois Tigeot #ifndef _H2INC 2898c59a5c48SFrançois Tigeot 2899c59a5c48SFrançois Tigeot //Please don't add or expand this bitfield structure below, this one will retire soon.! 2900c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_CAPABILITY 2901c59a5c48SFrançois Tigeot { 2902c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 2903c59a5c48SFrançois Tigeot USHORT Reserved:1; 2904c59a5c48SFrançois Tigeot USHORT SCL2Redefined:1; 2905c59a5c48SFrançois Tigeot USHORT PostWithoutModeSet:1; 2906c59a5c48SFrançois Tigeot USHORT HyperMemory_Size:4; 2907c59a5c48SFrançois Tigeot USHORT HyperMemory_Support:1; 2908c59a5c48SFrançois Tigeot USHORT PPMode_Assigned:1; 2909c59a5c48SFrançois Tigeot USHORT WMI_SUPPORT:1; 2910c59a5c48SFrançois Tigeot USHORT GPUControlsBL:1; 2911c59a5c48SFrançois Tigeot USHORT EngineClockSS_Support:1; 2912c59a5c48SFrançois Tigeot USHORT MemoryClockSS_Support:1; 2913c59a5c48SFrançois Tigeot USHORT ExtendedDesktopSupport:1; 2914c59a5c48SFrançois Tigeot USHORT DualCRTC_Support:1; 2915c59a5c48SFrançois Tigeot USHORT FirmwarePosted:1; 2916c59a5c48SFrançois Tigeot #else 2917c59a5c48SFrançois Tigeot USHORT FirmwarePosted:1; 2918c59a5c48SFrançois Tigeot USHORT DualCRTC_Support:1; 2919c59a5c48SFrançois Tigeot USHORT ExtendedDesktopSupport:1; 2920c59a5c48SFrançois Tigeot USHORT MemoryClockSS_Support:1; 2921c59a5c48SFrançois Tigeot USHORT EngineClockSS_Support:1; 2922c59a5c48SFrançois Tigeot USHORT GPUControlsBL:1; 2923c59a5c48SFrançois Tigeot USHORT WMI_SUPPORT:1; 2924c59a5c48SFrançois Tigeot USHORT PPMode_Assigned:1; 2925c59a5c48SFrançois Tigeot USHORT HyperMemory_Support:1; 2926c59a5c48SFrançois Tigeot USHORT HyperMemory_Size:4; 2927c59a5c48SFrançois Tigeot USHORT PostWithoutModeSet:1; 2928c59a5c48SFrançois Tigeot USHORT SCL2Redefined:1; 2929c59a5c48SFrançois Tigeot USHORT Reserved:1; 2930c59a5c48SFrançois Tigeot #endif 2931c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_CAPABILITY; 2932c59a5c48SFrançois Tigeot 2933c59a5c48SFrançois Tigeot typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2934c59a5c48SFrançois Tigeot { 2935c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY sbfAccess; 2936c59a5c48SFrançois Tigeot USHORT susAccess; 2937c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2938c59a5c48SFrançois Tigeot 2939c59a5c48SFrançois Tigeot #else 2940c59a5c48SFrançois Tigeot 2941c59a5c48SFrançois Tigeot typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2942c59a5c48SFrançois Tigeot { 2943c59a5c48SFrançois Tigeot USHORT susAccess; 2944c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2945c59a5c48SFrançois Tigeot 2946c59a5c48SFrançois Tigeot #endif 2947c59a5c48SFrançois Tigeot 2948c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO 2949c59a5c48SFrançois Tigeot { 2950c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 2951c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 2952c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 2953c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 2954c59a5c48SFrançois Tigeot ULONG ulDriverTargetEngineClock; //In 10Khz unit 2955c59a5c48SFrançois Tigeot ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2956c59a5c48SFrançois Tigeot ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2957c59a5c48SFrançois Tigeot ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2958c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2959c59a5c48SFrançois Tigeot ULONG ulASICMaxEngineClock; //In 10Khz unit 2960c59a5c48SFrançois Tigeot ULONG ulASICMaxMemoryClock; //In 10Khz unit 2961c59a5c48SFrançois Tigeot UCHAR ucASICMaxTemperature; 2962c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; //Don't use them 2963c59a5c48SFrançois Tigeot ULONG aulReservedForBIOS[3]; //Don't use them 2964c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2965c59a5c48SFrançois Tigeot USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2966c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2967c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2968c59a5c48SFrançois Tigeot USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2969c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2970c59a5c48SFrançois Tigeot USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2971c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2972c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2973c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2974c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2975c59a5c48SFrançois Tigeot USHORT usReferenceClock; //In 10Khz unit 2976c59a5c48SFrançois Tigeot USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2977c59a5c48SFrançois Tigeot UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2978c59a5c48SFrançois Tigeot UCHAR ucDesign_ID; //Indicate what is the board design 2979c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 2980c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO; 2981c59a5c48SFrançois Tigeot 2982c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO_V1_2 2983c59a5c48SFrançois Tigeot { 2984c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 2985c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 2986c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 2987c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 2988c59a5c48SFrançois Tigeot ULONG ulDriverTargetEngineClock; //In 10Khz unit 2989c59a5c48SFrançois Tigeot ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2990c59a5c48SFrançois Tigeot ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2991c59a5c48SFrançois Tigeot ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2992c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2993c59a5c48SFrançois Tigeot ULONG ulASICMaxEngineClock; //In 10Khz unit 2994c59a5c48SFrançois Tigeot ULONG ulASICMaxMemoryClock; //In 10Khz unit 2995c59a5c48SFrançois Tigeot UCHAR ucASICMaxTemperature; 2996c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 2997c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; //Don't use them 2998c59a5c48SFrançois Tigeot ULONG aulReservedForBIOS[2]; //Don't use them 2999c59a5c48SFrançois Tigeot ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3000c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3001c59a5c48SFrançois Tigeot USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3002c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3003c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3004c59a5c48SFrançois Tigeot USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3005c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3006c59a5c48SFrançois Tigeot USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3007c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3008c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3009c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3010c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3011c59a5c48SFrançois Tigeot USHORT usReferenceClock; //In 10Khz unit 3012c59a5c48SFrançois Tigeot USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3013c59a5c48SFrançois Tigeot UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3014c59a5c48SFrançois Tigeot UCHAR ucDesign_ID; //Indicate what is the board design 3015c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 3016c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO_V1_2; 3017c59a5c48SFrançois Tigeot 3018c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO_V1_3 3019c59a5c48SFrançois Tigeot { 3020c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3021c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 3022c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 3023c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 3024c59a5c48SFrançois Tigeot ULONG ulDriverTargetEngineClock; //In 10Khz unit 3025c59a5c48SFrançois Tigeot ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3026c59a5c48SFrançois Tigeot ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3027c59a5c48SFrançois Tigeot ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3028c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3029c59a5c48SFrançois Tigeot ULONG ulASICMaxEngineClock; //In 10Khz unit 3030c59a5c48SFrançois Tigeot ULONG ulASICMaxMemoryClock; //In 10Khz unit 3031c59a5c48SFrançois Tigeot UCHAR ucASICMaxTemperature; 3032c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 3033c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; //Don't use them 3034c59a5c48SFrançois Tigeot ULONG aulReservedForBIOS; //Don't use them 3035c59a5c48SFrançois Tigeot ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3036c59a5c48SFrançois Tigeot ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3037c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3038c59a5c48SFrançois Tigeot USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3039c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3040c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3041c59a5c48SFrançois Tigeot USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3042c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3043c59a5c48SFrançois Tigeot USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3044c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3045c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3046c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3047c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3048c59a5c48SFrançois Tigeot USHORT usReferenceClock; //In 10Khz unit 3049c59a5c48SFrançois Tigeot USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3050c59a5c48SFrançois Tigeot UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3051c59a5c48SFrançois Tigeot UCHAR ucDesign_ID; //Indicate what is the board design 3052c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 3053c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO_V1_3; 3054c59a5c48SFrançois Tigeot 3055c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO_V1_4 3056c59a5c48SFrançois Tigeot { 3057c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3058c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 3059c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 3060c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 3061c59a5c48SFrançois Tigeot ULONG ulDriverTargetEngineClock; //In 10Khz unit 3062c59a5c48SFrançois Tigeot ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3063c59a5c48SFrançois Tigeot ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3064c59a5c48SFrançois Tigeot ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3065c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3066c59a5c48SFrançois Tigeot ULONG ulASICMaxEngineClock; //In 10Khz unit 3067c59a5c48SFrançois Tigeot ULONG ulASICMaxMemoryClock; //In 10Khz unit 3068c59a5c48SFrançois Tigeot UCHAR ucASICMaxTemperature; 3069c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 3070c59a5c48SFrançois Tigeot USHORT usBootUpVDDCVoltage; //In MV unit 3071c59a5c48SFrançois Tigeot USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3072c59a5c48SFrançois Tigeot USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3073c59a5c48SFrançois Tigeot ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3074c59a5c48SFrançois Tigeot ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3075c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3076c59a5c48SFrançois Tigeot USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3077c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3078c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3079c59a5c48SFrançois Tigeot USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3080c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3081c59a5c48SFrançois Tigeot USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3082c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3083c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3084c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3085c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3086c59a5c48SFrançois Tigeot USHORT usReferenceClock; //In 10Khz unit 3087c59a5c48SFrançois Tigeot USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3088c59a5c48SFrançois Tigeot UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3089c59a5c48SFrançois Tigeot UCHAR ucDesign_ID; //Indicate what is the board design 3090c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 3091c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO_V1_4; 3092c59a5c48SFrançois Tigeot 3093c59a5c48SFrançois Tigeot //the structure below to be used from Cypress 3094c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO_V2_1 3095c59a5c48SFrançois Tigeot { 3096c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3097c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 3098c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 3099c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 3100c59a5c48SFrançois Tigeot ULONG ulReserved1; 3101c59a5c48SFrançois Tigeot ULONG ulReserved2; 3102c59a5c48SFrançois Tigeot ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3103c59a5c48SFrançois Tigeot ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3104c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3105c59a5c48SFrançois Tigeot ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 3106c59a5c48SFrançois Tigeot ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 3107c59a5c48SFrançois Tigeot UCHAR ucReserved1; //Was ucASICMaxTemperature; 3108c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 3109c59a5c48SFrançois Tigeot USHORT usBootUpVDDCVoltage; //In MV unit 3110c59a5c48SFrançois Tigeot USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3111c59a5c48SFrançois Tigeot USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3112c59a5c48SFrançois Tigeot ULONG ulReserved4; //Was ulAsicMaximumVoltage 3113c59a5c48SFrançois Tigeot ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3114c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3115c59a5c48SFrançois Tigeot USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3116c59a5c48SFrançois Tigeot USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3117c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3118c59a5c48SFrançois Tigeot USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3119c59a5c48SFrançois Tigeot USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3120c59a5c48SFrançois Tigeot USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3121c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3122c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3123c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3124c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3125c59a5c48SFrançois Tigeot USHORT usCoreReferenceClock; //In 10Khz unit 3126c59a5c48SFrançois Tigeot USHORT usMemoryReferenceClock; //In 10Khz unit 3127c59a5c48SFrançois Tigeot USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3128c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 3129c59a5c48SFrançois Tigeot UCHAR ucReserved4[3]; 3130c59a5c48SFrançois Tigeot 3131c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO_V2_1; 3132c59a5c48SFrançois Tigeot 3133c59a5c48SFrançois Tigeot //the structure below to be used from NI 3134c59a5c48SFrançois Tigeot //ucTableFormatRevision=2 3135c59a5c48SFrançois Tigeot //ucTableContentRevision=2 3136c59a5c48SFrançois Tigeot 3137c59a5c48SFrançois Tigeot typedef struct _PRODUCT_BRANDING 3138c59a5c48SFrançois Tigeot { 3139c59a5c48SFrançois Tigeot UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 3140c59a5c48SFrançois Tigeot UCHAR ucReserved:2; // Bit[3:2] Reserved 3141c59a5c48SFrançois Tigeot UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 3142c59a5c48SFrançois Tigeot }PRODUCT_BRANDING; 3143c59a5c48SFrançois Tigeot 3144c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_INFO_V2_2 3145c59a5c48SFrançois Tigeot { 3146c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3147c59a5c48SFrançois Tigeot ULONG ulFirmwareRevision; 3148c59a5c48SFrançois Tigeot ULONG ulDefaultEngineClock; //In 10Khz unit 3149c59a5c48SFrançois Tigeot ULONG ulDefaultMemoryClock; //In 10Khz unit 3150c59a5c48SFrançois Tigeot ULONG ulSPLL_OutputFreq; //In 10Khz unit 3151c59a5c48SFrançois Tigeot ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 3152c59a5c48SFrançois Tigeot ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 3153c59a5c48SFrançois Tigeot ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 3154c59a5c48SFrançois Tigeot ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3155c59a5c48SFrançois Tigeot ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 3156c59a5c48SFrançois Tigeot ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 3157c59a5c48SFrançois Tigeot UCHAR ucReserved3; //Was ucASICMaxTemperature; 3158c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 3159c59a5c48SFrançois Tigeot USHORT usBootUpVDDCVoltage; //In MV unit 3160c59a5c48SFrançois Tigeot USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3161c59a5c48SFrançois Tigeot USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3162c59a5c48SFrançois Tigeot ULONG ulReserved4; //Was ulAsicMaximumVoltage 3163c59a5c48SFrançois Tigeot ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3164c59a5c48SFrançois Tigeot UCHAR ucRemoteDisplayConfig; 3165c59a5c48SFrançois Tigeot UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 3166c59a5c48SFrançois Tigeot ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 3167c59a5c48SFrançois Tigeot ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 3168c59a5c48SFrançois Tigeot USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 3169c59a5c48SFrançois Tigeot USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3170c59a5c48SFrançois Tigeot USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3171c59a5c48SFrançois Tigeot USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3172c59a5c48SFrançois Tigeot ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3173c59a5c48SFrançois Tigeot USHORT usCoreReferenceClock; //In 10Khz unit 3174c59a5c48SFrançois Tigeot USHORT usMemoryReferenceClock; //In 10Khz unit 3175c59a5c48SFrançois Tigeot USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3176c59a5c48SFrançois Tigeot UCHAR ucMemoryModule_ID; //Indicate what is the board design 3177c59a5c48SFrançois Tigeot UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 3178c59a5c48SFrançois Tigeot PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 3179c59a5c48SFrançois Tigeot UCHAR ucReserved9; 3180c59a5c48SFrançois Tigeot USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3181c59a5c48SFrançois Tigeot USHORT usBootUpVDDGFXVoltage; //In unit of mv; 3182c59a5c48SFrançois Tigeot ULONG ulReserved10[3]; // New added comparing to previous version 3183c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_INFO_V2_2; 3184c59a5c48SFrançois Tigeot 3185c59a5c48SFrançois Tigeot #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 3186c59a5c48SFrançois Tigeot 3187c59a5c48SFrançois Tigeot 3188c59a5c48SFrançois Tigeot // definition of ucRemoteDisplayConfig 3189c59a5c48SFrançois Tigeot #define REMOTE_DISPLAY_DISABLE 0x00 3190c59a5c48SFrançois Tigeot #define REMOTE_DISPLAY_ENABLE 0x01 3191c59a5c48SFrançois Tigeot 3192c59a5c48SFrançois Tigeot /****************************************************************************/ 3193c59a5c48SFrançois Tigeot // Structures used in IntegratedSystemInfoTable 3194c59a5c48SFrançois Tigeot /****************************************************************************/ 3195c59a5c48SFrançois Tigeot #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 3196c59a5c48SFrançois Tigeot #define IGP_CAP_FLAG_AC_CARD 0x4 3197c59a5c48SFrançois Tigeot #define IGP_CAP_FLAG_SDVO_CARD 0x8 3198c59a5c48SFrançois Tigeot #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 3199c59a5c48SFrançois Tigeot 3200c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 3201c59a5c48SFrançois Tigeot { 3202c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3203c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; //in 10kHz unit 3204c59a5c48SFrançois Tigeot ULONG ulBootUpMemoryClock; //in 10kHz unit 3205c59a5c48SFrançois Tigeot ULONG ulMaxSystemMemoryClock; //in 10kHz unit 3206c59a5c48SFrançois Tigeot ULONG ulMinSystemMemoryClock; //in 10kHz unit 3207c59a5c48SFrançois Tigeot UCHAR ucNumberOfCyclesInPeriodHi; 3208c59a5c48SFrançois Tigeot UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 3209c59a5c48SFrançois Tigeot USHORT usReserved1; 3210c59a5c48SFrançois Tigeot USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 3211c59a5c48SFrançois Tigeot USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 3212c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 3213c59a5c48SFrançois Tigeot 3214c59a5c48SFrançois Tigeot USHORT usFSBClock; //In MHz unit 3215c59a5c48SFrançois Tigeot USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 3216c59a5c48SFrançois Tigeot //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 3217c59a5c48SFrançois Tigeot //Bit[4]==1: P/2 mode, ==0: P/1 mode 3218c59a5c48SFrançois Tigeot USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 3219c59a5c48SFrançois Tigeot USHORT usK8MemoryClock; //in MHz unit 3220c59a5c48SFrançois Tigeot USHORT usK8SyncStartDelay; //in 0.01 us unit 3221c59a5c48SFrançois Tigeot USHORT usK8DataReturnTime; //in 0.01 us unit 3222c59a5c48SFrançois Tigeot UCHAR ucMaxNBVoltage; 3223c59a5c48SFrançois Tigeot UCHAR ucMinNBVoltage; 3224c59a5c48SFrançois Tigeot UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 3225c59a5c48SFrançois Tigeot UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 3226c59a5c48SFrançois Tigeot UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 3227c59a5c48SFrançois Tigeot UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 3228c59a5c48SFrançois Tigeot UCHAR ucMaxNBVoltageHigh; 3229c59a5c48SFrançois Tigeot UCHAR ucMinNBVoltageHigh; 3230c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO; 3231c59a5c48SFrançois Tigeot 3232c59a5c48SFrançois Tigeot /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 3233c59a5c48SFrançois Tigeot ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 3234c59a5c48SFrançois Tigeot For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 3235c59a5c48SFrançois Tigeot ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3236c59a5c48SFrançois Tigeot For AMD IGP,for now this can be 0 3237c59a5c48SFrançois Tigeot ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3238c59a5c48SFrançois Tigeot For AMD IGP,for now this can be 0 3239c59a5c48SFrançois Tigeot 3240c59a5c48SFrançois Tigeot usFSBClock: For Intel IGP,it's FSB Freq 3241c59a5c48SFrançois Tigeot For AMD IGP,it's HT Link Speed 3242c59a5c48SFrançois Tigeot 3243c59a5c48SFrançois Tigeot usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 3244c59a5c48SFrançois Tigeot usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3245c59a5c48SFrançois Tigeot usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3246c59a5c48SFrançois Tigeot 3247c59a5c48SFrançois Tigeot VC:Voltage Control 3248c59a5c48SFrançois Tigeot ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3249c59a5c48SFrançois Tigeot ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3250c59a5c48SFrançois Tigeot 3251c59a5c48SFrançois Tigeot ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 3252c59a5c48SFrançois Tigeot ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 3253c59a5c48SFrançois Tigeot 3254c59a5c48SFrançois Tigeot ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3255c59a5c48SFrançois Tigeot ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3256c59a5c48SFrançois Tigeot 3257c59a5c48SFrançois Tigeot 3258c59a5c48SFrançois Tigeot usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 3259c59a5c48SFrançois Tigeot usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 3260c59a5c48SFrançois Tigeot */ 3261c59a5c48SFrançois Tigeot 3262c59a5c48SFrançois Tigeot 3263c59a5c48SFrançois Tigeot /* 3264c59a5c48SFrançois Tigeot The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 3265c59a5c48SFrançois Tigeot Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 3266c59a5c48SFrançois Tigeot The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 3267c59a5c48SFrançois Tigeot 3268c59a5c48SFrançois Tigeot SW components can access the IGP system infor structure in the same way as before 3269c59a5c48SFrançois Tigeot */ 3270c59a5c48SFrançois Tigeot 3271c59a5c48SFrançois Tigeot 3272c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 3273c59a5c48SFrançois Tigeot { 3274c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3275c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; //in 10kHz unit 3276c59a5c48SFrançois Tigeot ULONG ulReserved1[2]; //must be 0x0 for the reserved 3277c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; //in 10kHz unit 3278c59a5c48SFrançois Tigeot ULONG ulBootUpSidePortClock; //in 10kHz unit 3279c59a5c48SFrançois Tigeot ULONG ulMinSidePortClock; //in 10kHz unit 3280c59a5c48SFrançois Tigeot ULONG ulReserved2[6]; //must be 0x0 for the reserved 3281c59a5c48SFrançois Tigeot ULONG ulSystemConfig; //see explanation below 3282c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 3283c59a5c48SFrançois Tigeot ULONG ulOtherDisplayMisc; 3284c59a5c48SFrançois Tigeot ULONG ulDDISlot1Config; 3285c59a5c48SFrançois Tigeot ULONG ulDDISlot2Config; 3286c59a5c48SFrançois Tigeot UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3287c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 3288c59a5c48SFrançois Tigeot UCHAR ucDockingPinBit; 3289c59a5c48SFrançois Tigeot UCHAR ucDockingPinPolarity; 3290c59a5c48SFrançois Tigeot ULONG ulDockingPinCFGInfo; 3291c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 3292c59a5c48SFrançois Tigeot USHORT usNumberOfCyclesInPeriod; 3293c59a5c48SFrançois Tigeot USHORT usMaxNBVoltage; 3294c59a5c48SFrançois Tigeot USHORT usMinNBVoltage; 3295c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 3296c59a5c48SFrançois Tigeot ULONG ulHTLinkFreq; //in 10Khz 3297c59a5c48SFrançois Tigeot USHORT usMinHTLinkWidth; 3298c59a5c48SFrançois Tigeot USHORT usMaxHTLinkWidth; 3299c59a5c48SFrançois Tigeot USHORT usUMASyncStartDelay; 3300c59a5c48SFrançois Tigeot USHORT usUMADataReturnTime; 3301c59a5c48SFrançois Tigeot USHORT usLinkStatusZeroTime; 3302c59a5c48SFrançois Tigeot USHORT usDACEfuse; //for storing badgap value (for RS880 only) 3303c59a5c48SFrançois Tigeot ULONG ulHighVoltageHTLinkFreq; // in 10Khz 3304c59a5c48SFrançois Tigeot ULONG ulLowVoltageHTLinkFreq; // in 10Khz 3305c59a5c48SFrançois Tigeot USHORT usMaxUpStreamHTLinkWidth; 3306c59a5c48SFrançois Tigeot USHORT usMaxDownStreamHTLinkWidth; 3307c59a5c48SFrançois Tigeot USHORT usMinUpStreamHTLinkWidth; 3308c59a5c48SFrançois Tigeot USHORT usMinDownStreamHTLinkWidth; 3309c59a5c48SFrançois Tigeot USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 3310c59a5c48SFrançois Tigeot USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 3311c59a5c48SFrançois Tigeot ULONG ulReserved3[96]; //must be 0x0 3312c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V2; 3313c59a5c48SFrançois Tigeot 3314c59a5c48SFrançois Tigeot /* 3315c59a5c48SFrançois Tigeot ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 3316c59a5c48SFrançois Tigeot ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 3317c59a5c48SFrançois Tigeot ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 3318c59a5c48SFrançois Tigeot 3319c59a5c48SFrançois Tigeot ulSystemConfig: 3320c59a5c48SFrançois Tigeot Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 3321c59a5c48SFrançois Tigeot Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 3322c59a5c48SFrançois Tigeot =0: system boots up at driver control state. Power state depends on PowerPlay table. 3323c59a5c48SFrançois Tigeot Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 3324c59a5c48SFrançois Tigeot Bit[3]=1: Only one power state(Performance) will be supported. 3325c59a5c48SFrançois Tigeot =0: Multiple power states supported from PowerPlay table. 3326c59a5c48SFrançois Tigeot Bit[4]=1: CLMC is supported and enabled on current system. 3327c59a5c48SFrançois Tigeot =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 3328c59a5c48SFrançois Tigeot Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 3329c59a5c48SFrançois Tigeot =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 3330c59a5c48SFrançois Tigeot Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 3331c59a5c48SFrançois Tigeot =0: Voltage settings is determined by powerplay table. 3332c59a5c48SFrançois Tigeot Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 3333c59a5c48SFrançois Tigeot =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 3334c59a5c48SFrançois Tigeot Bit[8]=1: CDLF is supported and enabled on current system. 3335c59a5c48SFrançois Tigeot =0: CDLF is not supported or enabled on current system. 3336c59a5c48SFrançois Tigeot Bit[9]=1: DLL Shut Down feature is enabled on current system. 3337c59a5c48SFrançois Tigeot =0: DLL Shut Down feature is not enabled or supported on current system. 3338c59a5c48SFrançois Tigeot 3339c59a5c48SFrançois Tigeot ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 3340c59a5c48SFrançois Tigeot 3341c59a5c48SFrançois Tigeot ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 3342c59a5c48SFrançois Tigeot [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 3343c59a5c48SFrançois Tigeot 3344c59a5c48SFrançois Tigeot ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 3345c59a5c48SFrançois Tigeot [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 3346c59a5c48SFrançois Tigeot [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 3347c59a5c48SFrançois Tigeot When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 3348c59a5c48SFrançois Tigeot in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 3349c59a5c48SFrançois Tigeot one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 3350c59a5c48SFrançois Tigeot 3351c59a5c48SFrançois Tigeot [15:8] - Lane configuration attribute; 3352c59a5c48SFrançois Tigeot [23:16]- Connector type, possible value: 3353c59a5c48SFrançois Tigeot CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 3354c59a5c48SFrançois Tigeot CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 3355c59a5c48SFrançois Tigeot CONNECTOR_OBJECT_ID_HDMI_TYPE_A 3356c59a5c48SFrançois Tigeot CONNECTOR_OBJECT_ID_DISPLAYPORT 3357c59a5c48SFrançois Tigeot CONNECTOR_OBJECT_ID_eDP 3358c59a5c48SFrançois Tigeot [31:24]- Reserved 3359c59a5c48SFrançois Tigeot 3360c59a5c48SFrançois Tigeot ulDDISlot2Config: Same as Slot1. 3361c59a5c48SFrançois Tigeot ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 3362c59a5c48SFrançois Tigeot For IGP, Hypermemory is the only memory type showed in CCC. 3363c59a5c48SFrançois Tigeot 3364c59a5c48SFrançois Tigeot ucUMAChannelNumber: how many channels for the UMA; 3365c59a5c48SFrançois Tigeot 3366c59a5c48SFrançois Tigeot ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 3367c59a5c48SFrançois Tigeot ucDockingPinBit: which bit in this register to read the pin status; 3368c59a5c48SFrançois Tigeot ucDockingPinPolarity:Polarity of the pin when docked; 3369c59a5c48SFrançois Tigeot 3370c59a5c48SFrançois Tigeot ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3371c59a5c48SFrançois Tigeot 3372c59a5c48SFrançois Tigeot usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3373c59a5c48SFrançois Tigeot 3374c59a5c48SFrançois Tigeot usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3375c59a5c48SFrançois Tigeot usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3376c59a5c48SFrançois Tigeot GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3377c59a5c48SFrançois Tigeot PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3378c59a5c48SFrançois Tigeot GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3379c59a5c48SFrançois Tigeot 3380c59a5c48SFrançois Tigeot usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3381c59a5c48SFrançois Tigeot 3382c59a5c48SFrançois Tigeot 3383c59a5c48SFrançois Tigeot ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3384c59a5c48SFrançois Tigeot usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3385c59a5c48SFrançois Tigeot If CDLW enabled, both upstream and downstream width should be the same during bootup. 3386c59a5c48SFrançois Tigeot usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3387c59a5c48SFrançois Tigeot If CDLW enabled, both upstream and downstream width should be the same during bootup. 3388c59a5c48SFrançois Tigeot 3389c59a5c48SFrançois Tigeot usUMASyncStartDelay: Memory access latency, required for watermark calculation 3390c59a5c48SFrançois Tigeot usUMADataReturnTime: Memory access latency, required for watermark calculation 3391c59a5c48SFrançois Tigeot usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3392c59a5c48SFrançois Tigeot for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3393c59a5c48SFrançois Tigeot if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3394c59a5c48SFrançois Tigeot if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3395c59a5c48SFrançois Tigeot if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3396c59a5c48SFrançois Tigeot if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3397c59a5c48SFrançois Tigeot 3398c59a5c48SFrançois Tigeot ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3399c59a5c48SFrançois Tigeot This must be less than or equal to ulHTLinkFreq(bootup frequency). 3400c59a5c48SFrançois Tigeot ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3401c59a5c48SFrançois Tigeot This must be less than or equal to ulHighVoltageHTLinkFreq. 3402c59a5c48SFrançois Tigeot 3403c59a5c48SFrançois Tigeot usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3404c59a5c48SFrançois Tigeot usMaxDownStreamHTLinkWidth: same as above. 3405c59a5c48SFrançois Tigeot usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3406c59a5c48SFrançois Tigeot usMinDownStreamHTLinkWidth: same as above. 3407c59a5c48SFrançois Tigeot */ 3408c59a5c48SFrançois Tigeot 3409c59a5c48SFrançois Tigeot // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3410c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3411c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3412c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3413c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3414c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3415c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3416c59a5c48SFrançois Tigeot 3417c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3418c59a5c48SFrançois Tigeot 3419c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3420c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3421c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3422c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3423c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3424c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3425c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3426c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3427c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3428c59a5c48SFrançois Tigeot #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3429c59a5c48SFrançois Tigeot 3430c59a5c48SFrançois Tigeot #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3431c59a5c48SFrançois Tigeot 3432c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3433c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3434c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3435c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3436c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3437c59a5c48SFrançois Tigeot #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3438c59a5c48SFrançois Tigeot 3439c59a5c48SFrançois Tigeot #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3440c59a5c48SFrançois Tigeot #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3441c59a5c48SFrançois Tigeot #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3442c59a5c48SFrançois Tigeot 3443c59a5c48SFrançois Tigeot #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3444c59a5c48SFrançois Tigeot 3445c59a5c48SFrançois Tigeot // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3446c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3447c59a5c48SFrançois Tigeot { 3448c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3449c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; //in 10kHz unit 3450c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3451c59a5c48SFrançois Tigeot ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3452c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; //in 10kHz unit 3453c59a5c48SFrançois Tigeot ULONG ulReserved1[8]; //must be 0x0 for the reserved 3454c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 3455c59a5c48SFrançois Tigeot ULONG ulOtherDisplayMisc; 3456c59a5c48SFrançois Tigeot ULONG ulReserved2[4]; //must be 0x0 for the reserved 3457c59a5c48SFrançois Tigeot ULONG ulSystemConfig; //TBD 3458c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; //TBD 3459c59a5c48SFrançois Tigeot USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3460c59a5c48SFrançois Tigeot USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3461c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; //boot up NB voltage 3462c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3463c59a5c48SFrançois Tigeot UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3464c59a5c48SFrançois Tigeot ULONG ulReserved3[4]; //must be 0x0 for the reserved 3465c59a5c48SFrançois Tigeot ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3466c59a5c48SFrançois Tigeot ULONG ulDDISlot2Config; 3467c59a5c48SFrançois Tigeot ULONG ulDDISlot3Config; 3468c59a5c48SFrançois Tigeot ULONG ulDDISlot4Config; 3469c59a5c48SFrançois Tigeot ULONG ulReserved4[4]; //must be 0x0 for the reserved 3470c59a5c48SFrançois Tigeot UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3471c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 3472c59a5c48SFrançois Tigeot USHORT usReserved; 3473c59a5c48SFrançois Tigeot ULONG ulReserved5[4]; //must be 0x0 for the reserved 3474c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3475c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3476c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3477c59a5c48SFrançois Tigeot ULONG ulReserved6[61]; //must be 0x0 3478c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V5; 3479c59a5c48SFrançois Tigeot 3480c59a5c48SFrançois Tigeot 3481c59a5c48SFrançois Tigeot 3482c59a5c48SFrançois Tigeot /****************************************************************************/ 3483c59a5c48SFrançois Tigeot // Structure used in GPUVirtualizationInfoTable 3484c59a5c48SFrançois Tigeot /****************************************************************************/ 3485c59a5c48SFrançois Tigeot typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3486c59a5c48SFrançois Tigeot { 3487c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3488c59a5c48SFrançois Tigeot ULONG ulMCUcodeRomStartAddr; 3489c59a5c48SFrançois Tigeot ULONG ulMCUcodeLength; 3490c59a5c48SFrançois Tigeot ULONG ulSMCUcodeRomStartAddr; 3491c59a5c48SFrançois Tigeot ULONG ulSMCUcodeLength; 3492c59a5c48SFrançois Tigeot ULONG ulRLCVUcodeRomStartAddr; 3493c59a5c48SFrançois Tigeot ULONG ulRLCVUcodeLength; 3494c59a5c48SFrançois Tigeot ULONG ulTOCUcodeStartAddr; 3495c59a5c48SFrançois Tigeot ULONG ulTOCUcodeLength; 3496c59a5c48SFrançois Tigeot ULONG ulSMCPatchTableStartAddr; 3497c59a5c48SFrançois Tigeot ULONG ulSmcPatchTableLength; 3498c59a5c48SFrançois Tigeot ULONG ulSystemFlag; 3499c59a5c48SFrançois Tigeot }ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3500c59a5c48SFrançois Tigeot 3501c59a5c48SFrançois Tigeot 3502c59a5c48SFrançois Tigeot #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3503c59a5c48SFrançois Tigeot #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3504c59a5c48SFrançois Tigeot #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3505c59a5c48SFrançois Tigeot #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3506c59a5c48SFrançois Tigeot #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3507c59a5c48SFrançois Tigeot #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3508c59a5c48SFrançois Tigeot #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3509c59a5c48SFrançois Tigeot #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3510c59a5c48SFrançois Tigeot #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3511c59a5c48SFrançois Tigeot #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3512c59a5c48SFrançois Tigeot #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3513c59a5c48SFrançois Tigeot #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3514c59a5c48SFrançois Tigeot #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3515c59a5c48SFrançois Tigeot #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3516c59a5c48SFrançois Tigeot 3517c59a5c48SFrançois Tigeot // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3518c59a5c48SFrançois Tigeot #define ASIC_INT_DAC1_ENCODER_ID 0x00 3519c59a5c48SFrançois Tigeot #define ASIC_INT_TV_ENCODER_ID 0x02 3520c59a5c48SFrançois Tigeot #define ASIC_INT_DIG1_ENCODER_ID 0x03 3521c59a5c48SFrançois Tigeot #define ASIC_INT_DAC2_ENCODER_ID 0x04 3522c59a5c48SFrançois Tigeot #define ASIC_EXT_TV_ENCODER_ID 0x06 3523c59a5c48SFrançois Tigeot #define ASIC_INT_DVO_ENCODER_ID 0x07 3524c59a5c48SFrançois Tigeot #define ASIC_INT_DIG2_ENCODER_ID 0x09 3525c59a5c48SFrançois Tigeot #define ASIC_EXT_DIG_ENCODER_ID 0x05 3526c59a5c48SFrançois Tigeot #define ASIC_EXT_DIG2_ENCODER_ID 0x08 3527c59a5c48SFrançois Tigeot #define ASIC_INT_DIG3_ENCODER_ID 0x0a 3528c59a5c48SFrançois Tigeot #define ASIC_INT_DIG4_ENCODER_ID 0x0b 3529c59a5c48SFrançois Tigeot #define ASIC_INT_DIG5_ENCODER_ID 0x0c 3530c59a5c48SFrançois Tigeot #define ASIC_INT_DIG6_ENCODER_ID 0x0d 3531c59a5c48SFrançois Tigeot #define ASIC_INT_DIG7_ENCODER_ID 0x0e 3532c59a5c48SFrançois Tigeot 3533c59a5c48SFrançois Tigeot //define Encoder attribute 3534c59a5c48SFrançois Tigeot #define ATOM_ANALOG_ENCODER 0 3535c59a5c48SFrançois Tigeot #define ATOM_DIGITAL_ENCODER 1 3536c59a5c48SFrançois Tigeot #define ATOM_DP_ENCODER 2 3537c59a5c48SFrançois Tigeot 3538c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_MASK 0x70 3539c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID1 0x00 3540c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID2 0x10 3541c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID3 0x20 3542c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID4 0x30 3543c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID5 0x40 3544c59a5c48SFrançois Tigeot #define ATOM_ENCODER_ENUM_ID6 0x50 3545c59a5c48SFrançois Tigeot 3546c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3547c59a5c48SFrançois Tigeot #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3548c59a5c48SFrançois Tigeot #define ATOM_DEVICE_TV1_INDEX 0x00000002 3549c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3550c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3551c59a5c48SFrançois Tigeot #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3552c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3553c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3554c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CV_INDEX 0x00000008 3555c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3556c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3557c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3558c59a5c48SFrançois Tigeot 3559c59a5c48SFrançois Tigeot #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3560c59a5c48SFrançois Tigeot #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3561c59a5c48SFrançois Tigeot #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3562c59a5c48SFrançois Tigeot #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3563c59a5c48SFrançois Tigeot #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3564c59a5c48SFrançois Tigeot #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3565c59a5c48SFrançois Tigeot #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3566c59a5c48SFrançois Tigeot 3567c59a5c48SFrançois Tigeot #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3568c59a5c48SFrançois Tigeot 3569c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3570c59a5c48SFrançois Tigeot #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3571c59a5c48SFrançois Tigeot #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3572c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3573c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3574c59a5c48SFrançois Tigeot #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3575c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3576c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3577c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3578c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3579c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3580c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3581c59a5c48SFrançois Tigeot 3582c59a5c48SFrançois Tigeot 3583c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3584c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3585c59a5c48SFrançois Tigeot #define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3586c59a5c48SFrançois Tigeot #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3587c59a5c48SFrançois Tigeot 3588c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3589c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3590c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3591c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3592c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3593c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3594c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3595c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3596c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3597c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3598c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3599c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3600c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3601c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3602c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3603c59a5c48SFrançois Tigeot 3604c59a5c48SFrançois Tigeot 3605c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3606c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3607c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3608c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3609c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3610c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3611c59a5c48SFrançois Tigeot 3612c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3613c59a5c48SFrançois Tigeot 3614c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3615c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3616c59a5c48SFrançois Tigeot 3617c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3618c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3619c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3620c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3621c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3622c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3623c59a5c48SFrançois Tigeot 3624c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3625c59a5c48SFrançois Tigeot #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3626c59a5c48SFrançois Tigeot #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3627c59a5c48SFrançois Tigeot #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3628c59a5c48SFrançois Tigeot 3629c59a5c48SFrançois Tigeot // usDeviceSupport: 3630c59a5c48SFrançois Tigeot // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3631c59a5c48SFrançois Tigeot // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3632c59a5c48SFrançois Tigeot // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3633c59a5c48SFrançois Tigeot // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3634c59a5c48SFrançois Tigeot // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3635c59a5c48SFrançois Tigeot // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3636c59a5c48SFrançois Tigeot // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3637c59a5c48SFrançois Tigeot // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3638c59a5c48SFrançois Tigeot // Bit 8 = 0 - no CV support= 1- CV is supported 3639c59a5c48SFrançois Tigeot // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3640c59a5c48SFrançois Tigeot // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3641c59a5c48SFrançois Tigeot // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3642c59a5c48SFrançois Tigeot // 3643c59a5c48SFrançois Tigeot // 3644c59a5c48SFrançois Tigeot 3645c59a5c48SFrançois Tigeot /****************************************************************************/ 3646c59a5c48SFrançois Tigeot // Structure used in MclkSS_InfoTable 3647c59a5c48SFrançois Tigeot /****************************************************************************/ 3648c59a5c48SFrançois Tigeot // ucI2C_ConfigID 3649c59a5c48SFrançois Tigeot // [7:0] - I2C LINE Associate ID 3650c59a5c48SFrançois Tigeot // = 0 - no I2C 3651c59a5c48SFrançois Tigeot // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3652c59a5c48SFrançois Tigeot // = 0, [6:0]=SW assisted I2C ID 3653c59a5c48SFrançois Tigeot // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3654c59a5c48SFrançois Tigeot // = 2, HW engine for Multimedia use 3655c59a5c48SFrançois Tigeot // = 3-7 Reserved for future I2C engines 3656c59a5c48SFrançois Tigeot // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3657c59a5c48SFrançois Tigeot 3658c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_ID_CONFIG 3659c59a5c48SFrançois Tigeot { 3660c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 3661c59a5c48SFrançois Tigeot UCHAR bfHW_Capable:1; 3662c59a5c48SFrançois Tigeot UCHAR bfHW_EngineID:3; 3663c59a5c48SFrançois Tigeot UCHAR bfI2C_LineMux:4; 3664c59a5c48SFrançois Tigeot #else 3665c59a5c48SFrançois Tigeot UCHAR bfI2C_LineMux:4; 3666c59a5c48SFrançois Tigeot UCHAR bfHW_EngineID:3; 3667c59a5c48SFrançois Tigeot UCHAR bfHW_Capable:1; 3668c59a5c48SFrançois Tigeot #endif 3669c59a5c48SFrançois Tigeot }ATOM_I2C_ID_CONFIG; 3670c59a5c48SFrançois Tigeot 3671c59a5c48SFrançois Tigeot typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3672c59a5c48SFrançois Tigeot { 3673c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG sbfAccess; 3674c59a5c48SFrançois Tigeot UCHAR ucAccess; 3675c59a5c48SFrançois Tigeot }ATOM_I2C_ID_CONFIG_ACCESS; 3676c59a5c48SFrançois Tigeot 3677c59a5c48SFrançois Tigeot 3678c59a5c48SFrançois Tigeot /****************************************************************************/ 3679c59a5c48SFrançois Tigeot // Structure used in GPIO_I2C_InfoTable 3680c59a5c48SFrançois Tigeot /****************************************************************************/ 3681c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3682c59a5c48SFrançois Tigeot { 3683c59a5c48SFrançois Tigeot USHORT usClkMaskRegisterIndex; 3684c59a5c48SFrançois Tigeot USHORT usClkEnRegisterIndex; 3685c59a5c48SFrançois Tigeot USHORT usClkY_RegisterIndex; 3686c59a5c48SFrançois Tigeot USHORT usClkA_RegisterIndex; 3687c59a5c48SFrançois Tigeot USHORT usDataMaskRegisterIndex; 3688c59a5c48SFrançois Tigeot USHORT usDataEnRegisterIndex; 3689c59a5c48SFrançois Tigeot USHORT usDataY_RegisterIndex; 3690c59a5c48SFrançois Tigeot USHORT usDataA_RegisterIndex; 3691c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3692c59a5c48SFrançois Tigeot UCHAR ucClkMaskShift; 3693c59a5c48SFrançois Tigeot UCHAR ucClkEnShift; 3694c59a5c48SFrançois Tigeot UCHAR ucClkY_Shift; 3695c59a5c48SFrançois Tigeot UCHAR ucClkA_Shift; 3696c59a5c48SFrançois Tigeot UCHAR ucDataMaskShift; 3697c59a5c48SFrançois Tigeot UCHAR ucDataEnShift; 3698c59a5c48SFrançois Tigeot UCHAR ucDataY_Shift; 3699c59a5c48SFrançois Tigeot UCHAR ucDataA_Shift; 3700c59a5c48SFrançois Tigeot UCHAR ucReserved1; 3701c59a5c48SFrançois Tigeot UCHAR ucReserved2; 3702c59a5c48SFrançois Tigeot }ATOM_GPIO_I2C_ASSIGMENT; 3703c59a5c48SFrançois Tigeot 3704c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_I2C_INFO 3705c59a5c48SFrançois Tigeot { 3706c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3707c59a5c48SFrançois Tigeot ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3708c59a5c48SFrançois Tigeot }ATOM_GPIO_I2C_INFO; 3709c59a5c48SFrançois Tigeot 3710c59a5c48SFrançois Tigeot /****************************************************************************/ 3711c59a5c48SFrançois Tigeot // Common Structure used in other structures 3712c59a5c48SFrançois Tigeot /****************************************************************************/ 3713c59a5c48SFrançois Tigeot 3714c59a5c48SFrançois Tigeot #ifndef _H2INC 3715c59a5c48SFrançois Tigeot 3716c59a5c48SFrançois Tigeot //Please don't add or expand this bitfield structure below, this one will retire soon.! 3717c59a5c48SFrançois Tigeot typedef struct _ATOM_MODE_MISC_INFO 3718c59a5c48SFrançois Tigeot { 3719c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 3720c59a5c48SFrançois Tigeot USHORT Reserved:6; 3721c59a5c48SFrançois Tigeot USHORT RGB888:1; 3722c59a5c48SFrançois Tigeot USHORT DoubleClock:1; 3723c59a5c48SFrançois Tigeot USHORT Interlace:1; 3724c59a5c48SFrançois Tigeot USHORT CompositeSync:1; 3725c59a5c48SFrançois Tigeot USHORT V_ReplicationBy2:1; 3726c59a5c48SFrançois Tigeot USHORT H_ReplicationBy2:1; 3727c59a5c48SFrançois Tigeot USHORT VerticalCutOff:1; 3728c59a5c48SFrançois Tigeot USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3729c59a5c48SFrançois Tigeot USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3730c59a5c48SFrançois Tigeot USHORT HorizontalCutOff:1; 3731c59a5c48SFrançois Tigeot #else 3732c59a5c48SFrançois Tigeot USHORT HorizontalCutOff:1; 3733c59a5c48SFrançois Tigeot USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3734c59a5c48SFrançois Tigeot USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3735c59a5c48SFrançois Tigeot USHORT VerticalCutOff:1; 3736c59a5c48SFrançois Tigeot USHORT H_ReplicationBy2:1; 3737c59a5c48SFrançois Tigeot USHORT V_ReplicationBy2:1; 3738c59a5c48SFrançois Tigeot USHORT CompositeSync:1; 3739c59a5c48SFrançois Tigeot USHORT Interlace:1; 3740c59a5c48SFrançois Tigeot USHORT DoubleClock:1; 3741c59a5c48SFrançois Tigeot USHORT RGB888:1; 3742c59a5c48SFrançois Tigeot USHORT Reserved:6; 3743c59a5c48SFrançois Tigeot #endif 3744c59a5c48SFrançois Tigeot }ATOM_MODE_MISC_INFO; 3745c59a5c48SFrançois Tigeot 3746c59a5c48SFrançois Tigeot typedef union _ATOM_MODE_MISC_INFO_ACCESS 3747c59a5c48SFrançois Tigeot { 3748c59a5c48SFrançois Tigeot ATOM_MODE_MISC_INFO sbfAccess; 3749c59a5c48SFrançois Tigeot USHORT usAccess; 3750c59a5c48SFrançois Tigeot }ATOM_MODE_MISC_INFO_ACCESS; 3751c59a5c48SFrançois Tigeot 3752c59a5c48SFrançois Tigeot #else 3753c59a5c48SFrançois Tigeot 3754c59a5c48SFrançois Tigeot typedef union _ATOM_MODE_MISC_INFO_ACCESS 3755c59a5c48SFrançois Tigeot { 3756c59a5c48SFrançois Tigeot USHORT usAccess; 3757c59a5c48SFrançois Tigeot }ATOM_MODE_MISC_INFO_ACCESS; 3758c59a5c48SFrançois Tigeot 3759c59a5c48SFrançois Tigeot #endif 3760c59a5c48SFrançois Tigeot 3761c59a5c48SFrançois Tigeot // usModeMiscInfo- 3762c59a5c48SFrançois Tigeot #define ATOM_H_CUTOFF 0x01 3763c59a5c48SFrançois Tigeot #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3764c59a5c48SFrançois Tigeot #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3765c59a5c48SFrançois Tigeot #define ATOM_V_CUTOFF 0x08 3766c59a5c48SFrançois Tigeot #define ATOM_H_REPLICATIONBY2 0x10 3767c59a5c48SFrançois Tigeot #define ATOM_V_REPLICATIONBY2 0x20 3768c59a5c48SFrançois Tigeot #define ATOM_COMPOSITESYNC 0x40 3769c59a5c48SFrançois Tigeot #define ATOM_INTERLACE 0x80 3770c59a5c48SFrançois Tigeot #define ATOM_DOUBLE_CLOCK_MODE 0x100 3771c59a5c48SFrançois Tigeot #define ATOM_RGB888_MODE 0x200 3772c59a5c48SFrançois Tigeot 3773c59a5c48SFrançois Tigeot //usRefreshRate- 3774c59a5c48SFrançois Tigeot #define ATOM_REFRESH_43 43 3775c59a5c48SFrançois Tigeot #define ATOM_REFRESH_47 47 3776c59a5c48SFrançois Tigeot #define ATOM_REFRESH_56 56 3777c59a5c48SFrançois Tigeot #define ATOM_REFRESH_60 60 3778c59a5c48SFrançois Tigeot #define ATOM_REFRESH_65 65 3779c59a5c48SFrançois Tigeot #define ATOM_REFRESH_70 70 3780c59a5c48SFrançois Tigeot #define ATOM_REFRESH_72 72 3781c59a5c48SFrançois Tigeot #define ATOM_REFRESH_75 75 3782c59a5c48SFrançois Tigeot #define ATOM_REFRESH_85 85 3783c59a5c48SFrançois Tigeot 3784c59a5c48SFrançois Tigeot // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3785c59a5c48SFrançois Tigeot // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3786c59a5c48SFrançois Tigeot // 3787c59a5c48SFrançois Tigeot // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3788c59a5c48SFrançois Tigeot // = EDID_HA + EDID_HBL 3789c59a5c48SFrançois Tigeot // VESA_HDISP = VESA_ACTIVE = EDID_HA 3790c59a5c48SFrançois Tigeot // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3791c59a5c48SFrançois Tigeot // = EDID_HA + EDID_HSO 3792c59a5c48SFrançois Tigeot // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3793c59a5c48SFrançois Tigeot // VESA_BORDER = EDID_BORDER 3794c59a5c48SFrançois Tigeot 3795c59a5c48SFrançois Tigeot 3796c59a5c48SFrançois Tigeot /****************************************************************************/ 3797c59a5c48SFrançois Tigeot // Structure used in SetCRTC_UsingDTDTimingTable 3798c59a5c48SFrançois Tigeot /****************************************************************************/ 3799c59a5c48SFrançois Tigeot typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3800c59a5c48SFrançois Tigeot { 3801c59a5c48SFrançois Tigeot USHORT usH_Size; 3802c59a5c48SFrançois Tigeot USHORT usH_Blanking_Time; 3803c59a5c48SFrançois Tigeot USHORT usV_Size; 3804c59a5c48SFrançois Tigeot USHORT usV_Blanking_Time; 3805c59a5c48SFrançois Tigeot USHORT usH_SyncOffset; 3806c59a5c48SFrançois Tigeot USHORT usH_SyncWidth; 3807c59a5c48SFrançois Tigeot USHORT usV_SyncOffset; 3808c59a5c48SFrançois Tigeot USHORT usV_SyncWidth; 3809c59a5c48SFrançois Tigeot ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3810c59a5c48SFrançois Tigeot UCHAR ucH_Border; // From DFP EDID 3811c59a5c48SFrançois Tigeot UCHAR ucV_Border; 3812c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3813c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 3814c59a5c48SFrançois Tigeot }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3815c59a5c48SFrançois Tigeot 3816c59a5c48SFrançois Tigeot /****************************************************************************/ 3817c59a5c48SFrançois Tigeot // Structure used in SetCRTC_TimingTable 3818c59a5c48SFrançois Tigeot /****************************************************************************/ 3819c59a5c48SFrançois Tigeot typedef struct _SET_CRTC_TIMING_PARAMETERS 3820c59a5c48SFrançois Tigeot { 3821c59a5c48SFrançois Tigeot USHORT usH_Total; // horizontal total 3822c59a5c48SFrançois Tigeot USHORT usH_Disp; // horizontal display 3823c59a5c48SFrançois Tigeot USHORT usH_SyncStart; // horozontal Sync start 3824c59a5c48SFrançois Tigeot USHORT usH_SyncWidth; // horizontal Sync width 3825c59a5c48SFrançois Tigeot USHORT usV_Total; // vertical total 3826c59a5c48SFrançois Tigeot USHORT usV_Disp; // vertical display 3827c59a5c48SFrançois Tigeot USHORT usV_SyncStart; // vertical Sync start 3828c59a5c48SFrançois Tigeot USHORT usV_SyncWidth; // vertical Sync width 3829c59a5c48SFrançois Tigeot ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3830c59a5c48SFrançois Tigeot UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3831c59a5c48SFrançois Tigeot UCHAR ucOverscanRight; // right 3832c59a5c48SFrançois Tigeot UCHAR ucOverscanLeft; // left 3833c59a5c48SFrançois Tigeot UCHAR ucOverscanBottom; // bottom 3834c59a5c48SFrançois Tigeot UCHAR ucOverscanTop; // top 3835c59a5c48SFrançois Tigeot UCHAR ucReserved; 3836c59a5c48SFrançois Tigeot }SET_CRTC_TIMING_PARAMETERS; 3837c59a5c48SFrançois Tigeot #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3838c59a5c48SFrançois Tigeot 3839c59a5c48SFrançois Tigeot 3840c59a5c48SFrançois Tigeot /****************************************************************************/ 3841c59a5c48SFrançois Tigeot // Structure used in StandardVESA_TimingTable 3842c59a5c48SFrançois Tigeot // AnalogTV_InfoTable 3843c59a5c48SFrançois Tigeot // ComponentVideoInfoTable 3844c59a5c48SFrançois Tigeot /****************************************************************************/ 3845c59a5c48SFrançois Tigeot typedef struct _ATOM_MODE_TIMING 3846c59a5c48SFrançois Tigeot { 3847c59a5c48SFrançois Tigeot USHORT usCRTC_H_Total; 3848c59a5c48SFrançois Tigeot USHORT usCRTC_H_Disp; 3849c59a5c48SFrançois Tigeot USHORT usCRTC_H_SyncStart; 3850c59a5c48SFrançois Tigeot USHORT usCRTC_H_SyncWidth; 3851c59a5c48SFrançois Tigeot USHORT usCRTC_V_Total; 3852c59a5c48SFrançois Tigeot USHORT usCRTC_V_Disp; 3853c59a5c48SFrançois Tigeot USHORT usCRTC_V_SyncStart; 3854c59a5c48SFrançois Tigeot USHORT usCRTC_V_SyncWidth; 3855c59a5c48SFrançois Tigeot USHORT usPixelClock; //in 10Khz unit 3856c59a5c48SFrançois Tigeot ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3857c59a5c48SFrançois Tigeot USHORT usCRTC_OverscanRight; 3858c59a5c48SFrançois Tigeot USHORT usCRTC_OverscanLeft; 3859c59a5c48SFrançois Tigeot USHORT usCRTC_OverscanBottom; 3860c59a5c48SFrançois Tigeot USHORT usCRTC_OverscanTop; 3861c59a5c48SFrançois Tigeot USHORT usReserve; 3862c59a5c48SFrançois Tigeot UCHAR ucInternalModeNumber; 3863c59a5c48SFrançois Tigeot UCHAR ucRefreshRate; 3864c59a5c48SFrançois Tigeot }ATOM_MODE_TIMING; 3865c59a5c48SFrançois Tigeot 3866c59a5c48SFrançois Tigeot typedef struct _ATOM_DTD_FORMAT 3867c59a5c48SFrançois Tigeot { 3868c59a5c48SFrançois Tigeot USHORT usPixClk; 3869c59a5c48SFrançois Tigeot USHORT usHActive; 3870c59a5c48SFrançois Tigeot USHORT usHBlanking_Time; 3871c59a5c48SFrançois Tigeot USHORT usVActive; 3872c59a5c48SFrançois Tigeot USHORT usVBlanking_Time; 3873c59a5c48SFrançois Tigeot USHORT usHSyncOffset; 3874c59a5c48SFrançois Tigeot USHORT usHSyncWidth; 3875c59a5c48SFrançois Tigeot USHORT usVSyncOffset; 3876c59a5c48SFrançois Tigeot USHORT usVSyncWidth; 3877c59a5c48SFrançois Tigeot USHORT usImageHSize; 3878c59a5c48SFrançois Tigeot USHORT usImageVSize; 3879c59a5c48SFrançois Tigeot UCHAR ucHBorder; 3880c59a5c48SFrançois Tigeot UCHAR ucVBorder; 3881c59a5c48SFrançois Tigeot ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3882c59a5c48SFrançois Tigeot UCHAR ucInternalModeNumber; 3883c59a5c48SFrançois Tigeot UCHAR ucRefreshRate; 3884c59a5c48SFrançois Tigeot }ATOM_DTD_FORMAT; 3885c59a5c48SFrançois Tigeot 3886c59a5c48SFrançois Tigeot /****************************************************************************/ 3887c59a5c48SFrançois Tigeot // Structure used in LVDS_InfoTable 3888c59a5c48SFrançois Tigeot // * Need a document to describe this table 3889c59a5c48SFrançois Tigeot /****************************************************************************/ 3890c59a5c48SFrançois Tigeot #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3891c59a5c48SFrançois Tigeot #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3892c59a5c48SFrançois Tigeot #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3893c59a5c48SFrançois Tigeot #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3894c59a5c48SFrançois Tigeot #define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3895c59a5c48SFrançois Tigeot 3896c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 3897c59a5c48SFrançois Tigeot //ucTableContentRevision=1 3898c59a5c48SFrançois Tigeot typedef struct _ATOM_LVDS_INFO 3899c59a5c48SFrançois Tigeot { 3900c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3901c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT sLCDTiming; 3902c59a5c48SFrançois Tigeot USHORT usModePatchTableOffset; 3903c59a5c48SFrançois Tigeot USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3904c59a5c48SFrançois Tigeot USHORT usOffDelayInMs; 3905c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDigOntoDEin10Ms; 3906c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3907c59a5c48SFrançois Tigeot UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3908c59a5c48SFrançois Tigeot // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3909c59a5c48SFrançois Tigeot // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3910c59a5c48SFrançois Tigeot // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3911c59a5c48SFrançois Tigeot UCHAR ucPanelDefaultRefreshRate; 3912c59a5c48SFrançois Tigeot UCHAR ucPanelIdentification; 3913c59a5c48SFrançois Tigeot UCHAR ucSS_Id; 3914c59a5c48SFrançois Tigeot }ATOM_LVDS_INFO; 3915c59a5c48SFrançois Tigeot 3916c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 3917c59a5c48SFrançois Tigeot //ucTableContentRevision=2 3918c59a5c48SFrançois Tigeot typedef struct _ATOM_LVDS_INFO_V12 3919c59a5c48SFrançois Tigeot { 3920c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3921c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT sLCDTiming; 3922c59a5c48SFrançois Tigeot USHORT usExtInfoTableOffset; 3923c59a5c48SFrançois Tigeot USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3924c59a5c48SFrançois Tigeot USHORT usOffDelayInMs; 3925c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDigOntoDEin10Ms; 3926c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3927c59a5c48SFrançois Tigeot UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3928c59a5c48SFrançois Tigeot // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3929c59a5c48SFrançois Tigeot // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3930c59a5c48SFrançois Tigeot // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3931c59a5c48SFrançois Tigeot UCHAR ucPanelDefaultRefreshRate; 3932c59a5c48SFrançois Tigeot UCHAR ucPanelIdentification; 3933c59a5c48SFrançois Tigeot UCHAR ucSS_Id; 3934c59a5c48SFrançois Tigeot USHORT usLCDVenderID; 3935c59a5c48SFrançois Tigeot USHORT usLCDProductID; 3936c59a5c48SFrançois Tigeot UCHAR ucLCDPanel_SpecialHandlingCap; 3937c59a5c48SFrançois Tigeot UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3938c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 3939c59a5c48SFrançois Tigeot }ATOM_LVDS_INFO_V12; 3940c59a5c48SFrançois Tigeot 3941c59a5c48SFrançois Tigeot //Definitions for ucLCDPanel_SpecialHandlingCap: 3942c59a5c48SFrançois Tigeot 3943c59a5c48SFrançois Tigeot //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3944c59a5c48SFrançois Tigeot //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3945c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_READ_EDID 0x1 3946c59a5c48SFrançois Tigeot 3947c59a5c48SFrançois Tigeot //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3948c59a5c48SFrançois Tigeot //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3949c59a5c48SFrançois Tigeot //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3950c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3951c59a5c48SFrançois Tigeot 3952c59a5c48SFrançois Tigeot //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3953c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_eDP 0x4 3954c59a5c48SFrançois Tigeot 3955c59a5c48SFrançois Tigeot 3956c59a5c48SFrançois Tigeot //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3957c59a5c48SFrançois Tigeot //Bit 6 5 4 3958c59a5c48SFrançois Tigeot // 0 0 0 - Color bit depth is undefined 3959c59a5c48SFrançois Tigeot // 0 0 1 - 6 Bits per Primary Color 3960c59a5c48SFrançois Tigeot // 0 1 0 - 8 Bits per Primary Color 3961c59a5c48SFrançois Tigeot // 0 1 1 - 10 Bits per Primary Color 3962c59a5c48SFrançois Tigeot // 1 0 0 - 12 Bits per Primary Color 3963c59a5c48SFrançois Tigeot // 1 0 1 - 14 Bits per Primary Color 3964c59a5c48SFrançois Tigeot // 1 1 0 - 16 Bits per Primary Color 3965c59a5c48SFrançois Tigeot // 1 1 1 - Reserved 3966c59a5c48SFrançois Tigeot 3967c59a5c48SFrançois Tigeot #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3968c59a5c48SFrançois Tigeot 3969c59a5c48SFrançois Tigeot // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3970c59a5c48SFrançois Tigeot #define PANEL_RANDOM_DITHER 0x80 3971c59a5c48SFrançois Tigeot #define PANEL_RANDOM_DITHER_MASK 0x80 3972c59a5c48SFrançois Tigeot 3973c59a5c48SFrançois Tigeot #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3974c59a5c48SFrançois Tigeot 3975c59a5c48SFrançois Tigeot 3976c59a5c48SFrançois Tigeot typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3977c59a5c48SFrançois Tigeot { 3978c59a5c48SFrançois Tigeot UCHAR ucSupportedRefreshRate; 3979c59a5c48SFrançois Tigeot UCHAR ucMinRefreshRateForDRR; 3980c59a5c48SFrançois Tigeot }ATOM_LCD_REFRESH_RATE_SUPPORT; 3981c59a5c48SFrançois Tigeot 3982c59a5c48SFrançois Tigeot /****************************************************************************/ 3983c59a5c48SFrançois Tigeot // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3984c59a5c48SFrançois Tigeot // ASIC Families: NI 3985c59a5c48SFrançois Tigeot // ucTableFormatRevision=1 3986c59a5c48SFrançois Tigeot // ucTableContentRevision=3 3987c59a5c48SFrançois Tigeot /****************************************************************************/ 3988c59a5c48SFrançois Tigeot typedef struct _ATOM_LCD_INFO_V13 3989c59a5c48SFrançois Tigeot { 3990c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 3991c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT sLCDTiming; 3992c59a5c48SFrançois Tigeot USHORT usExtInfoTableOffset; 3993c59a5c48SFrançois Tigeot union 3994c59a5c48SFrançois Tigeot { 3995c59a5c48SFrançois Tigeot USHORT usSupportedRefreshRate; 3996c59a5c48SFrançois Tigeot ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 3997c59a5c48SFrançois Tigeot }; 3998c59a5c48SFrançois Tigeot ULONG ulReserved0; 3999c59a5c48SFrançois Tigeot UCHAR ucLCD_Misc; // Reorganized in V13 4000c59a5c48SFrançois Tigeot // Bit0: {=0:single, =1:dual}, 4001c59a5c48SFrançois Tigeot // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 4002c59a5c48SFrançois Tigeot // Bit3:2: {Grey level} 4003c59a5c48SFrançois Tigeot // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 4004c59a5c48SFrançois Tigeot // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 4005c59a5c48SFrançois Tigeot UCHAR ucPanelDefaultRefreshRate; 4006c59a5c48SFrançois Tigeot UCHAR ucPanelIdentification; 4007c59a5c48SFrançois Tigeot UCHAR ucSS_Id; 4008c59a5c48SFrançois Tigeot USHORT usLCDVenderID; 4009c59a5c48SFrançois Tigeot USHORT usLCDProductID; 4010c59a5c48SFrançois Tigeot UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 4011c59a5c48SFrançois Tigeot // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 4012c59a5c48SFrançois Tigeot // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 4013c59a5c48SFrançois Tigeot // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 4014c59a5c48SFrançois Tigeot // Bit7-3: Reserved 4015c59a5c48SFrançois Tigeot UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 4016c59a5c48SFrançois Tigeot USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 4017c59a5c48SFrançois Tigeot 4018c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 4019c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 4020c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 4021c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 4022c59a5c48SFrançois Tigeot 4023c59a5c48SFrançois Tigeot UCHAR ucOffDelay_in4Ms; 4024c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 4025c59a5c48SFrançois Tigeot UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 4026c59a5c48SFrançois Tigeot UCHAR ucReserved1; 4027c59a5c48SFrançois Tigeot 4028c59a5c48SFrançois Tigeot UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 4029c59a5c48SFrançois Tigeot UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 4030c59a5c48SFrançois Tigeot UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 4031c59a5c48SFrançois Tigeot UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 4032c59a5c48SFrançois Tigeot 4033c59a5c48SFrançois Tigeot USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 4034c59a5c48SFrançois Tigeot UCHAR uceDPToLVDSRxId; 4035c59a5c48SFrançois Tigeot UCHAR ucLcdReservd; 4036c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 4037c59a5c48SFrançois Tigeot }ATOM_LCD_INFO_V13; 4038c59a5c48SFrançois Tigeot 4039c59a5c48SFrançois Tigeot #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 4040c59a5c48SFrançois Tigeot 4041c59a5c48SFrançois Tigeot //Definitions for ucLCD_Misc 4042c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 4043c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 4044c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 4045c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 4046c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 4047c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 4048c59a5c48SFrançois Tigeot #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 4049c59a5c48SFrançois Tigeot 4050c59a5c48SFrançois Tigeot //Color Bit Depth definition in EDID V1.4 @BYTE 14h 4051c59a5c48SFrançois Tigeot //Bit 6 5 4 4052c59a5c48SFrançois Tigeot // 0 0 0 - Color bit depth is undefined 4053c59a5c48SFrançois Tigeot // 0 0 1 - 6 Bits per Primary Color 4054c59a5c48SFrançois Tigeot // 0 1 0 - 8 Bits per Primary Color 4055c59a5c48SFrançois Tigeot // 0 1 1 - 10 Bits per Primary Color 4056c59a5c48SFrançois Tigeot // 1 0 0 - 12 Bits per Primary Color 4057c59a5c48SFrançois Tigeot // 1 0 1 - 14 Bits per Primary Color 4058c59a5c48SFrançois Tigeot // 1 1 0 - 16 Bits per Primary Color 4059c59a5c48SFrançois Tigeot // 1 1 1 - Reserved 4060c59a5c48SFrançois Tigeot 4061c59a5c48SFrançois Tigeot //Definitions for ucLCDPanel_SpecialHandlingCap: 4062c59a5c48SFrançois Tigeot 4063c59a5c48SFrançois Tigeot //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 4064c59a5c48SFrançois Tigeot //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 4065c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 4066c59a5c48SFrançois Tigeot 4067c59a5c48SFrançois Tigeot //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 4068c59a5c48SFrançois Tigeot //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 4069c59a5c48SFrançois Tigeot //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 4070c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 4071c59a5c48SFrançois Tigeot 4072c59a5c48SFrançois Tigeot //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 4073c59a5c48SFrançois Tigeot #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 4074c59a5c48SFrançois Tigeot 4075c59a5c48SFrançois Tigeot //uceDPToLVDSRxId 4076c59a5c48SFrançois Tigeot #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 4077c59a5c48SFrançois Tigeot #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 4078c59a5c48SFrançois Tigeot #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 4079c59a5c48SFrançois Tigeot 4080c59a5c48SFrançois Tigeot typedef struct _ATOM_PATCH_RECORD_MODE 4081c59a5c48SFrançois Tigeot { 4082c59a5c48SFrançois Tigeot UCHAR ucRecordType; 4083c59a5c48SFrançois Tigeot USHORT usHDisp; 4084c59a5c48SFrançois Tigeot USHORT usVDisp; 4085c59a5c48SFrançois Tigeot }ATOM_PATCH_RECORD_MODE; 4086c59a5c48SFrançois Tigeot 4087c59a5c48SFrançois Tigeot typedef struct _ATOM_LCD_RTS_RECORD 4088c59a5c48SFrançois Tigeot { 4089c59a5c48SFrançois Tigeot UCHAR ucRecordType; 4090c59a5c48SFrançois Tigeot UCHAR ucRTSValue; 4091c59a5c48SFrançois Tigeot }ATOM_LCD_RTS_RECORD; 4092c59a5c48SFrançois Tigeot 4093c59a5c48SFrançois Tigeot //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 4094c59a5c48SFrançois Tigeot // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 4095c59a5c48SFrançois Tigeot typedef struct _ATOM_LCD_MODE_CONTROL_CAP 4096c59a5c48SFrançois Tigeot { 4097c59a5c48SFrançois Tigeot UCHAR ucRecordType; 4098c59a5c48SFrançois Tigeot USHORT usLCDCap; 4099c59a5c48SFrançois Tigeot }ATOM_LCD_MODE_CONTROL_CAP; 4100c59a5c48SFrançois Tigeot 4101c59a5c48SFrançois Tigeot #define LCD_MODE_CAP_BL_OFF 1 4102c59a5c48SFrançois Tigeot #define LCD_MODE_CAP_CRTC_OFF 2 4103c59a5c48SFrançois Tigeot #define LCD_MODE_CAP_PANEL_OFF 4 4104c59a5c48SFrançois Tigeot 4105c59a5c48SFrançois Tigeot 4106c59a5c48SFrançois Tigeot typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 4107c59a5c48SFrançois Tigeot { 4108c59a5c48SFrançois Tigeot UCHAR ucRecordType; 4109c59a5c48SFrançois Tigeot UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 4110c59a5c48SFrançois Tigeot UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 4111c59a5c48SFrançois Tigeot } ATOM_FAKE_EDID_PATCH_RECORD; 4112c59a5c48SFrançois Tigeot 4113c59a5c48SFrançois Tigeot typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 4114c59a5c48SFrançois Tigeot { 4115c59a5c48SFrançois Tigeot UCHAR ucRecordType; 4116c59a5c48SFrançois Tigeot USHORT usHSize; 4117c59a5c48SFrançois Tigeot USHORT usVSize; 4118c59a5c48SFrançois Tigeot }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 4119c59a5c48SFrançois Tigeot 4120c59a5c48SFrançois Tigeot #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 4121c59a5c48SFrançois Tigeot #define LCD_RTS_RECORD_TYPE 2 4122c59a5c48SFrançois Tigeot #define LCD_CAP_RECORD_TYPE 3 4123c59a5c48SFrançois Tigeot #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 4124c59a5c48SFrançois Tigeot #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 4125c59a5c48SFrançois Tigeot #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 4126c59a5c48SFrançois Tigeot #define ATOM_RECORD_END_TYPE 0xFF 4127c59a5c48SFrançois Tigeot 4128c59a5c48SFrançois Tigeot /****************************Spread Spectrum Info Table Definitions **********************/ 4129c59a5c48SFrançois Tigeot 4130c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 4131c59a5c48SFrançois Tigeot //ucTableContentRevision=2 4132c59a5c48SFrançois Tigeot typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 4133c59a5c48SFrançois Tigeot { 4134c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; 4135c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 4136c59a5c48SFrançois Tigeot UCHAR ucSS_Step; 4137c59a5c48SFrançois Tigeot UCHAR ucSS_Delay; 4138c59a5c48SFrançois Tigeot UCHAR ucSS_Id; 4139c59a5c48SFrançois Tigeot UCHAR ucRecommendedRef_Div; 4140c59a5c48SFrançois Tigeot UCHAR ucSS_Range; //it was reserved for V11 4141c59a5c48SFrançois Tigeot }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 4142c59a5c48SFrançois Tigeot 4143c59a5c48SFrançois Tigeot #define ATOM_MAX_SS_ENTRY 16 4144c59a5c48SFrançois Tigeot #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 4145c59a5c48SFrançois Tigeot #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 4146c59a5c48SFrançois Tigeot #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 4147c59a5c48SFrançois Tigeot #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 4148c59a5c48SFrançois Tigeot 4149c59a5c48SFrançois Tigeot 4150c59a5c48SFrançois Tigeot 4151c59a5c48SFrançois Tigeot #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 4152c59a5c48SFrançois Tigeot #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 4153c59a5c48SFrançois Tigeot #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 4154c59a5c48SFrançois Tigeot #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 4155c59a5c48SFrançois Tigeot #define ATOM_INTERNAL_SS_MASK 0x00000000 4156c59a5c48SFrançois Tigeot #define ATOM_EXTERNAL_SS_MASK 0x00000002 4157c59a5c48SFrançois Tigeot #define EXEC_SS_STEP_SIZE_SHIFT 2 4158c59a5c48SFrançois Tigeot #define EXEC_SS_DELAY_SHIFT 4 4159c59a5c48SFrançois Tigeot #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 4160c59a5c48SFrançois Tigeot 4161c59a5c48SFrançois Tigeot typedef struct _ATOM_SPREAD_SPECTRUM_INFO 4162c59a5c48SFrançois Tigeot { 4163c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4164c59a5c48SFrançois Tigeot ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 4165c59a5c48SFrançois Tigeot }ATOM_SPREAD_SPECTRUM_INFO; 4166c59a5c48SFrançois Tigeot 4167c59a5c48SFrançois Tigeot 4168c59a5c48SFrançois Tigeot /****************************************************************************/ 4169c59a5c48SFrançois Tigeot // Structure used in AnalogTV_InfoTable (Top level) 4170c59a5c48SFrançois Tigeot /****************************************************************************/ 4171c59a5c48SFrançois Tigeot //ucTVBootUpDefaultStd definiton: 4172c59a5c48SFrançois Tigeot 4173c59a5c48SFrançois Tigeot //ATOM_TV_NTSC 1 4174c59a5c48SFrançois Tigeot //ATOM_TV_NTSCJ 2 4175c59a5c48SFrançois Tigeot //ATOM_TV_PAL 3 4176c59a5c48SFrançois Tigeot //ATOM_TV_PALM 4 4177c59a5c48SFrançois Tigeot //ATOM_TV_PALCN 5 4178c59a5c48SFrançois Tigeot //ATOM_TV_PALN 6 4179c59a5c48SFrançois Tigeot //ATOM_TV_PAL60 7 4180c59a5c48SFrançois Tigeot //ATOM_TV_SECAM 8 4181c59a5c48SFrançois Tigeot 4182c59a5c48SFrançois Tigeot //ucTVSuppportedStd definition: 4183c59a5c48SFrançois Tigeot #define NTSC_SUPPORT 0x1 4184c59a5c48SFrançois Tigeot #define NTSCJ_SUPPORT 0x2 4185c59a5c48SFrançois Tigeot 4186c59a5c48SFrançois Tigeot #define PAL_SUPPORT 0x4 4187c59a5c48SFrançois Tigeot #define PALM_SUPPORT 0x8 4188c59a5c48SFrançois Tigeot #define PALCN_SUPPORT 0x10 4189c59a5c48SFrançois Tigeot #define PALN_SUPPORT 0x20 4190c59a5c48SFrançois Tigeot #define PAL60_SUPPORT 0x40 4191c59a5c48SFrançois Tigeot #define SECAM_SUPPORT 0x80 4192c59a5c48SFrançois Tigeot 4193c59a5c48SFrançois Tigeot #define MAX_SUPPORTED_TV_TIMING 2 4194c59a5c48SFrançois Tigeot 4195c59a5c48SFrançois Tigeot typedef struct _ATOM_ANALOG_TV_INFO 4196c59a5c48SFrançois Tigeot { 4197c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4198c59a5c48SFrançois Tigeot UCHAR ucTV_SuppportedStandard; 4199c59a5c48SFrançois Tigeot UCHAR ucTV_BootUpDefaultStandard; 4200c59a5c48SFrançois Tigeot UCHAR ucExt_TV_ASIC_ID; 4201c59a5c48SFrançois Tigeot UCHAR ucExt_TV_ASIC_SlaveAddr; 4202c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 4203c59a5c48SFrançois Tigeot }ATOM_ANALOG_TV_INFO; 4204c59a5c48SFrançois Tigeot 4205c59a5c48SFrançois Tigeot typedef struct _ATOM_DPCD_INFO 4206c59a5c48SFrançois Tigeot { 4207c59a5c48SFrançois Tigeot UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 4208c59a5c48SFrançois Tigeot UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 4209c59a5c48SFrançois Tigeot UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 4210c59a5c48SFrançois Tigeot UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 4211c59a5c48SFrançois Tigeot }ATOM_DPCD_INFO; 4212c59a5c48SFrançois Tigeot 4213c59a5c48SFrançois Tigeot #define ATOM_DPCD_MAX_LANE_MASK 0x1F 4214c59a5c48SFrançois Tigeot 4215c59a5c48SFrançois Tigeot /**************************************************************************/ 4216c59a5c48SFrançois Tigeot // VRAM usage and their defintions 4217c59a5c48SFrançois Tigeot 4218c59a5c48SFrançois Tigeot // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 4219c59a5c48SFrançois Tigeot // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 4220c59a5c48SFrançois Tigeot // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 4221c59a5c48SFrançois Tigeot // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 4222c59a5c48SFrançois Tigeot // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 4223c59a5c48SFrançois Tigeot 4224c59a5c48SFrançois Tigeot // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 4225c59a5c48SFrançois Tigeot //#ifndef VESA_MEMORY_IN_64K_BLOCK 4226c59a5c48SFrançois Tigeot //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 4227c59a5c48SFrançois Tigeot //#endif 4228c59a5c48SFrançois Tigeot 4229c59a5c48SFrançois Tigeot #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 4230c59a5c48SFrançois Tigeot #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 4231c59a5c48SFrançois Tigeot #define ATOM_HWICON_INFOTABLE_SIZE 32 4232c59a5c48SFrançois Tigeot #define MAX_DTD_MODE_IN_VRAM 6 4233c59a5c48SFrançois Tigeot #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 4234c59a5c48SFrançois Tigeot #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 4235c59a5c48SFrançois Tigeot //20 bytes for Encoder Type and DPCD in STD EDID area 4236c59a5c48SFrançois Tigeot #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 4237c59a5c48SFrançois Tigeot #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 4238c59a5c48SFrançois Tigeot 4239c59a5c48SFrançois Tigeot #define ATOM_HWICON1_SURFACE_ADDR 0 4240c59a5c48SFrançois Tigeot #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4241c59a5c48SFrançois Tigeot #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4242c59a5c48SFrançois Tigeot #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 4243c59a5c48SFrançois Tigeot #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4244c59a5c48SFrançois Tigeot #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4245c59a5c48SFrançois Tigeot 4246c59a5c48SFrançois Tigeot #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4247c59a5c48SFrançois Tigeot #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4248c59a5c48SFrançois Tigeot #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4249c59a5c48SFrançois Tigeot 4250c59a5c48SFrançois Tigeot #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4251c59a5c48SFrançois Tigeot 4252c59a5c48SFrançois Tigeot #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4253c59a5c48SFrançois Tigeot #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4254c59a5c48SFrançois Tigeot #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4255c59a5c48SFrançois Tigeot 4256c59a5c48SFrançois Tigeot #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4257c59a5c48SFrançois Tigeot #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4258c59a5c48SFrançois Tigeot #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4259c59a5c48SFrançois Tigeot 4260c59a5c48SFrançois Tigeot #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4261c59a5c48SFrançois Tigeot #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4262c59a5c48SFrançois Tigeot #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4263c59a5c48SFrançois Tigeot 4264c59a5c48SFrançois Tigeot #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4265c59a5c48SFrançois Tigeot #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4266c59a5c48SFrançois Tigeot #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4267c59a5c48SFrançois Tigeot 4268c59a5c48SFrançois Tigeot #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4269c59a5c48SFrançois Tigeot #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4270c59a5c48SFrançois Tigeot #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4271c59a5c48SFrançois Tigeot 4272c59a5c48SFrançois Tigeot #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4273c59a5c48SFrançois Tigeot #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4274c59a5c48SFrançois Tigeot #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4275c59a5c48SFrançois Tigeot 4276c59a5c48SFrançois Tigeot #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4277c59a5c48SFrançois Tigeot #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4278c59a5c48SFrançois Tigeot #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4279c59a5c48SFrançois Tigeot 4280c59a5c48SFrançois Tigeot #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4281c59a5c48SFrançois Tigeot #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4282c59a5c48SFrançois Tigeot #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4283c59a5c48SFrançois Tigeot 4284c59a5c48SFrançois Tigeot #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4285c59a5c48SFrançois Tigeot #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4286c59a5c48SFrançois Tigeot #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4287c59a5c48SFrançois Tigeot 4288c59a5c48SFrançois Tigeot #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4289c59a5c48SFrançois Tigeot 4290c59a5c48SFrançois Tigeot #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 4291c59a5c48SFrançois Tigeot #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 4292c59a5c48SFrançois Tigeot 4293c59a5c48SFrançois Tigeot //The size below is in Kb! 4294c59a5c48SFrançois Tigeot #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 4295c59a5c48SFrançois Tigeot 4296c59a5c48SFrançois Tigeot #define ATOM_VRAM_RESERVE_V2_SIZE 32 4297c59a5c48SFrançois Tigeot 4298c59a5c48SFrançois Tigeot #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 4299c59a5c48SFrançois Tigeot #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 4300c59a5c48SFrançois Tigeot #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 4301c59a5c48SFrançois Tigeot #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 4302*b843c749SSergey Zigachev #define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2 4303c59a5c48SFrançois Tigeot 4304c59a5c48SFrançois Tigeot /***********************************************************************************/ 4305c59a5c48SFrançois Tigeot // Structure used in VRAM_UsageByFirmwareTable 4306c59a5c48SFrançois Tigeot // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 4307c59a5c48SFrançois Tigeot // at running time. 4308c59a5c48SFrançois Tigeot // note2: From RV770, the memory is more than 32bit addressable, so we will change 4309c59a5c48SFrançois Tigeot // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 4310c59a5c48SFrançois Tigeot // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 4311c59a5c48SFrançois Tigeot // (in offset to start of memory address) is KB aligned instead of byte aligend. 4312c59a5c48SFrançois Tigeot // Note3: 4313c59a5c48SFrançois Tigeot /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 4314c59a5c48SFrançois Tigeot constant across VGA or non VGA adapter, 4315c59a5c48SFrançois Tigeot for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 4316c59a5c48SFrançois Tigeot 4317c59a5c48SFrançois Tigeot If (ulStartAddrUsedByFirmware!=0) 4318c59a5c48SFrançois Tigeot FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 4319c59a5c48SFrançois Tigeot Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 4320c59a5c48SFrançois Tigeot else //Non VGA case 4321c59a5c48SFrançois Tigeot if (FB_Size<=2Gb) 4322c59a5c48SFrançois Tigeot FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 4323c59a5c48SFrançois Tigeot else 4324c59a5c48SFrançois Tigeot FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 4325c59a5c48SFrançois Tigeot 4326c59a5c48SFrançois Tigeot CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 4327c59a5c48SFrançois Tigeot 4328c59a5c48SFrançois Tigeot /***********************************************************************************/ 4329c59a5c48SFrançois Tigeot #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 4330c59a5c48SFrançois Tigeot 4331c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 4332c59a5c48SFrançois Tigeot { 4333c59a5c48SFrançois Tigeot ULONG ulStartAddrUsedByFirmware; 4334c59a5c48SFrançois Tigeot USHORT usFirmwareUseInKb; 4335c59a5c48SFrançois Tigeot USHORT usReserved; 4336c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 4337c59a5c48SFrançois Tigeot 4338c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 4339c59a5c48SFrançois Tigeot { 4340c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4341c59a5c48SFrançois Tigeot ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4342c59a5c48SFrançois Tigeot }ATOM_VRAM_USAGE_BY_FIRMWARE; 4343c59a5c48SFrançois Tigeot 4344c59a5c48SFrançois Tigeot // change verion to 1.5, when allow driver to allocate the vram area for command table access. 4345c59a5c48SFrançois Tigeot typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 4346c59a5c48SFrançois Tigeot { 4347c59a5c48SFrançois Tigeot ULONG ulStartAddrUsedByFirmware; 4348c59a5c48SFrançois Tigeot USHORT usFirmwareUseInKb; 4349c59a5c48SFrançois Tigeot USHORT usFBUsedByDrvInKb; 4350c59a5c48SFrançois Tigeot }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 4351c59a5c48SFrançois Tigeot 4352c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 4353c59a5c48SFrançois Tigeot { 4354c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4355c59a5c48SFrançois Tigeot ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4356c59a5c48SFrançois Tigeot }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 4357c59a5c48SFrançois Tigeot 4358c59a5c48SFrançois Tigeot /****************************************************************************/ 4359c59a5c48SFrançois Tigeot // Structure used in GPIO_Pin_LUTTable 4360c59a5c48SFrançois Tigeot /****************************************************************************/ 4361c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 4362c59a5c48SFrançois Tigeot { 4363c59a5c48SFrançois Tigeot USHORT usGpioPin_AIndex; 4364c59a5c48SFrançois Tigeot UCHAR ucGpioPinBitShift; 4365c59a5c48SFrançois Tigeot UCHAR ucGPIO_ID; 4366c59a5c48SFrançois Tigeot }ATOM_GPIO_PIN_ASSIGNMENT; 4367c59a5c48SFrançois Tigeot 4368c59a5c48SFrançois Tigeot //ucGPIO_ID pre-define id for multiple usage 4369c59a5c48SFrançois Tigeot // GPIO use to control PCIE_VDDC in certain SLT board 4370c59a5c48SFrançois Tigeot #define PCIE_VDDC_CONTROL_GPIO_PINID 56 4371c59a5c48SFrançois Tigeot 4372*b843c749SSergey Zigachev //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 4373c59a5c48SFrançois Tigeot #define PP_AC_DC_SWITCH_GPIO_PINID 60 4374c59a5c48SFrançois Tigeot //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4375c59a5c48SFrançois Tigeot #define VDDC_VRHOT_GPIO_PINID 61 4376c59a5c48SFrançois Tigeot //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4377c59a5c48SFrançois Tigeot #define VDDC_PCC_GPIO_PINID 62 4378c59a5c48SFrançois Tigeot // Only used on certain SLT/PA board to allow utility to cut Efuse. 4379c59a5c48SFrançois Tigeot #define EFUSE_CUT_ENABLE_GPIO_PINID 63 4380c59a5c48SFrançois Tigeot // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4381c59a5c48SFrançois Tigeot #define DRAM_SELF_REFRESH_GPIO_PINID 64 4382c59a5c48SFrançois Tigeot // Thermal interrupt output->system thermal chip GPIO pin 4383c59a5c48SFrançois Tigeot #define THERMAL_INT_OUTPUT_GPIO_PINID 65 4384c59a5c48SFrançois Tigeot 4385c59a5c48SFrançois Tigeot 4386c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_PIN_LUT 4387c59a5c48SFrançois Tigeot { 4388c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4389c59a5c48SFrançois Tigeot ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 4390c59a5c48SFrançois Tigeot }ATOM_GPIO_PIN_LUT; 4391c59a5c48SFrançois Tigeot 4392c59a5c48SFrançois Tigeot /****************************************************************************/ 4393c59a5c48SFrançois Tigeot // Structure used in ComponentVideoInfoTable 4394c59a5c48SFrançois Tigeot /****************************************************************************/ 4395c59a5c48SFrançois Tigeot #define GPIO_PIN_ACTIVE_HIGH 0x1 4396c59a5c48SFrançois Tigeot #define MAX_SUPPORTED_CV_STANDARDS 5 4397c59a5c48SFrançois Tigeot 4398c59a5c48SFrançois Tigeot // definitions for ATOM_D_INFO.ucSettings 4399c59a5c48SFrançois Tigeot #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4400c59a5c48SFrançois Tigeot #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4401c59a5c48SFrançois Tigeot #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4402c59a5c48SFrançois Tigeot 4403c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_INFO 4404c59a5c48SFrançois Tigeot { 4405c59a5c48SFrançois Tigeot USHORT usAOffset; 4406c59a5c48SFrançois Tigeot UCHAR ucSettings; 4407c59a5c48SFrançois Tigeot UCHAR ucReserved; 4408c59a5c48SFrançois Tigeot }ATOM_GPIO_INFO; 4409c59a5c48SFrançois Tigeot 4410c59a5c48SFrançois Tigeot // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4411c59a5c48SFrançois Tigeot #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4412c59a5c48SFrançois Tigeot 4413c59a5c48SFrançois Tigeot // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4414c59a5c48SFrançois Tigeot #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4415c59a5c48SFrançois Tigeot #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4416c59a5c48SFrançois Tigeot 4417c59a5c48SFrançois Tigeot // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4418c59a5c48SFrançois Tigeot //Line 3 out put 5V. 4419c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4420c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4421c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4422c59a5c48SFrançois Tigeot 4423c59a5c48SFrançois Tigeot //Line 3 out put 2.2V 4424c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4425c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4426c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4427c59a5c48SFrançois Tigeot 4428c59a5c48SFrançois Tigeot //Line 3 out put 0V 4429c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4430c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4431c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4432c59a5c48SFrançois Tigeot 4433c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4434c59a5c48SFrançois Tigeot 4435c59a5c48SFrançois Tigeot #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4436c59a5c48SFrançois Tigeot 4437c59a5c48SFrançois Tigeot //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4438c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4439c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4440c59a5c48SFrançois Tigeot 4441c59a5c48SFrançois Tigeot 4442c59a5c48SFrançois Tigeot typedef struct _ATOM_COMPONENT_VIDEO_INFO 4443c59a5c48SFrançois Tigeot { 4444c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4445c59a5c48SFrançois Tigeot USHORT usMask_PinRegisterIndex; 4446c59a5c48SFrançois Tigeot USHORT usEN_PinRegisterIndex; 4447c59a5c48SFrançois Tigeot USHORT usY_PinRegisterIndex; 4448c59a5c48SFrançois Tigeot USHORT usA_PinRegisterIndex; 4449c59a5c48SFrançois Tigeot UCHAR ucBitShift; 4450c59a5c48SFrançois Tigeot UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4451c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT sReserved; // must be zeroed out 4452c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; 4453c59a5c48SFrançois Tigeot UCHAR uc480i; 4454c59a5c48SFrançois Tigeot UCHAR uc480p; 4455c59a5c48SFrançois Tigeot UCHAR uc720p; 4456c59a5c48SFrançois Tigeot UCHAR uc1080i; 4457c59a5c48SFrançois Tigeot UCHAR ucLetterBoxMode; 4458c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 4459c59a5c48SFrançois Tigeot UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4460c59a5c48SFrançois Tigeot ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4461c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4462c59a5c48SFrançois Tigeot }ATOM_COMPONENT_VIDEO_INFO; 4463c59a5c48SFrançois Tigeot 4464c59a5c48SFrançois Tigeot //ucTableFormatRevision=2 4465c59a5c48SFrançois Tigeot //ucTableContentRevision=1 4466c59a5c48SFrançois Tigeot typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4467c59a5c48SFrançois Tigeot { 4468c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4469c59a5c48SFrançois Tigeot UCHAR ucMiscInfo; 4470c59a5c48SFrançois Tigeot UCHAR uc480i; 4471c59a5c48SFrançois Tigeot UCHAR uc480p; 4472c59a5c48SFrançois Tigeot UCHAR uc720p; 4473c59a5c48SFrançois Tigeot UCHAR uc1080i; 4474c59a5c48SFrançois Tigeot UCHAR ucReserved; 4475c59a5c48SFrançois Tigeot UCHAR ucLetterBoxMode; 4476c59a5c48SFrançois Tigeot UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4477c59a5c48SFrançois Tigeot ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4478c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4479c59a5c48SFrançois Tigeot }ATOM_COMPONENT_VIDEO_INFO_V21; 4480c59a5c48SFrançois Tigeot 4481c59a5c48SFrançois Tigeot #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4482c59a5c48SFrançois Tigeot 4483c59a5c48SFrançois Tigeot /****************************************************************************/ 4484c59a5c48SFrançois Tigeot // Structure used in object_InfoTable 4485c59a5c48SFrançois Tigeot /****************************************************************************/ 4486c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT_HEADER 4487c59a5c48SFrançois Tigeot { 4488c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4489c59a5c48SFrançois Tigeot USHORT usDeviceSupport; 4490c59a5c48SFrançois Tigeot USHORT usConnectorObjectTableOffset; 4491c59a5c48SFrançois Tigeot USHORT usRouterObjectTableOffset; 4492c59a5c48SFrançois Tigeot USHORT usEncoderObjectTableOffset; 4493c59a5c48SFrançois Tigeot USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4494c59a5c48SFrançois Tigeot USHORT usDisplayPathTableOffset; 4495c59a5c48SFrançois Tigeot }ATOM_OBJECT_HEADER; 4496c59a5c48SFrançois Tigeot 4497c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT_HEADER_V3 4498c59a5c48SFrançois Tigeot { 4499c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4500c59a5c48SFrançois Tigeot USHORT usDeviceSupport; 4501c59a5c48SFrançois Tigeot USHORT usConnectorObjectTableOffset; 4502c59a5c48SFrançois Tigeot USHORT usRouterObjectTableOffset; 4503c59a5c48SFrançois Tigeot USHORT usEncoderObjectTableOffset; 4504c59a5c48SFrançois Tigeot USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4505c59a5c48SFrançois Tigeot USHORT usDisplayPathTableOffset; 4506c59a5c48SFrançois Tigeot USHORT usMiscObjectTableOffset; 4507c59a5c48SFrançois Tigeot }ATOM_OBJECT_HEADER_V3; 4508c59a5c48SFrançois Tigeot 4509c59a5c48SFrançois Tigeot 4510c59a5c48SFrançois Tigeot typedef struct _ATOM_DISPLAY_OBJECT_PATH 4511c59a5c48SFrançois Tigeot { 4512c59a5c48SFrançois Tigeot USHORT usDeviceTag; //supported device 4513c59a5c48SFrançois Tigeot USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4514c59a5c48SFrançois Tigeot USHORT usConnObjectId; //Connector Object ID 4515c59a5c48SFrançois Tigeot USHORT usGPUObjectId; //GPU ID 4516c59a5c48SFrançois Tigeot USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4517c59a5c48SFrançois Tigeot }ATOM_DISPLAY_OBJECT_PATH; 4518c59a5c48SFrançois Tigeot 4519c59a5c48SFrançois Tigeot typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4520c59a5c48SFrançois Tigeot { 4521c59a5c48SFrançois Tigeot USHORT usDeviceTag; //supported device 4522c59a5c48SFrançois Tigeot USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4523c59a5c48SFrançois Tigeot USHORT usConnObjectId; //Connector Object ID 4524c59a5c48SFrançois Tigeot USHORT usGPUObjectId; //GPU ID 4525c59a5c48SFrançois Tigeot USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4526c59a5c48SFrançois Tigeot }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4527c59a5c48SFrançois Tigeot 4528c59a5c48SFrançois Tigeot typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4529c59a5c48SFrançois Tigeot { 4530c59a5c48SFrançois Tigeot UCHAR ucNumOfDispPath; 4531c59a5c48SFrançois Tigeot UCHAR ucVersion; 4532c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 4533c59a5c48SFrançois Tigeot ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4534c59a5c48SFrançois Tigeot }ATOM_DISPLAY_OBJECT_PATH_TABLE; 4535c59a5c48SFrançois Tigeot 4536c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT //each object has this structure 4537c59a5c48SFrançois Tigeot { 4538c59a5c48SFrançois Tigeot USHORT usObjectID; 4539c59a5c48SFrançois Tigeot USHORT usSrcDstTableOffset; 4540c59a5c48SFrançois Tigeot USHORT usRecordOffset; //this pointing to a bunch of records defined below 4541c59a5c48SFrançois Tigeot USHORT usReserved; 4542c59a5c48SFrançois Tigeot }ATOM_OBJECT; 4543c59a5c48SFrançois Tigeot 4544c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4545c59a5c48SFrançois Tigeot { 4546c59a5c48SFrançois Tigeot UCHAR ucNumberOfObjects; 4547c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 4548c59a5c48SFrançois Tigeot ATOM_OBJECT asObjects[1]; 4549c59a5c48SFrançois Tigeot }ATOM_OBJECT_TABLE; 4550c59a5c48SFrançois Tigeot 4551c59a5c48SFrançois Tigeot typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4552c59a5c48SFrançois Tigeot { 4553c59a5c48SFrançois Tigeot UCHAR ucNumberOfSrc; 4554c59a5c48SFrançois Tigeot USHORT usSrcObjectID[1]; 4555c59a5c48SFrançois Tigeot UCHAR ucNumberOfDst; 4556c59a5c48SFrançois Tigeot USHORT usDstObjectID[1]; 4557c59a5c48SFrançois Tigeot }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4558c59a5c48SFrançois Tigeot 4559c59a5c48SFrançois Tigeot 4560c59a5c48SFrançois Tigeot //Two definitions below are for OPM on MXM module designs 4561c59a5c48SFrançois Tigeot 4562c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_0 0 4563c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_1 1 4564c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_2 2 4565c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_3 3 4566c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_4 4 4567c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_5 5 4568c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_6 6 4569c59a5c48SFrançois Tigeot #define EXT_HPDPIN_LUTINDEX_7 7 4570c59a5c48SFrançois Tigeot #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4571c59a5c48SFrançois Tigeot 4572c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_0 0 4573c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_1 1 4574c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_2 2 4575c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_3 3 4576c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_4 4 4577c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_5 5 4578c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_6 6 4579c59a5c48SFrançois Tigeot #define EXT_AUXDDC_LUTINDEX_7 7 4580c59a5c48SFrançois Tigeot #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4581c59a5c48SFrançois Tigeot 4582c59a5c48SFrançois Tigeot //ucChannelMapping are defined as following 4583c59a5c48SFrançois Tigeot //for DP connector, eDP, DP to VGA/LVDS 4584c59a5c48SFrançois Tigeot //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4585c59a5c48SFrançois Tigeot //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4586c59a5c48SFrançois Tigeot //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4587c59a5c48SFrançois Tigeot //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4588c59a5c48SFrançois Tigeot typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4589c59a5c48SFrançois Tigeot { 4590c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 4591c59a5c48SFrançois Tigeot UCHAR ucDP_Lane3_Source:2; 4592c59a5c48SFrançois Tigeot UCHAR ucDP_Lane2_Source:2; 4593c59a5c48SFrançois Tigeot UCHAR ucDP_Lane1_Source:2; 4594c59a5c48SFrançois Tigeot UCHAR ucDP_Lane0_Source:2; 4595c59a5c48SFrançois Tigeot #else 4596c59a5c48SFrançois Tigeot UCHAR ucDP_Lane0_Source:2; 4597c59a5c48SFrançois Tigeot UCHAR ucDP_Lane1_Source:2; 4598c59a5c48SFrançois Tigeot UCHAR ucDP_Lane2_Source:2; 4599c59a5c48SFrançois Tigeot UCHAR ucDP_Lane3_Source:2; 4600c59a5c48SFrançois Tigeot #endif 4601c59a5c48SFrançois Tigeot }ATOM_DP_CONN_CHANNEL_MAPPING; 4602c59a5c48SFrançois Tigeot 4603c59a5c48SFrançois Tigeot //for DVI/HDMI, in dual link case, both links have to have same mapping. 4604c59a5c48SFrançois Tigeot //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4605c59a5c48SFrançois Tigeot //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4606c59a5c48SFrançois Tigeot //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4607c59a5c48SFrançois Tigeot //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4608c59a5c48SFrançois Tigeot typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4609c59a5c48SFrançois Tigeot { 4610c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 4611c59a5c48SFrançois Tigeot UCHAR ucDVI_CLK_Source:2; 4612c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA0_Source:2; 4613c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA1_Source:2; 4614c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA2_Source:2; 4615c59a5c48SFrançois Tigeot #else 4616c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA2_Source:2; 4617c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA1_Source:2; 4618c59a5c48SFrançois Tigeot UCHAR ucDVI_DATA0_Source:2; 4619c59a5c48SFrançois Tigeot UCHAR ucDVI_CLK_Source:2; 4620c59a5c48SFrançois Tigeot #endif 4621c59a5c48SFrançois Tigeot }ATOM_DVI_CONN_CHANNEL_MAPPING; 4622c59a5c48SFrançois Tigeot 4623c59a5c48SFrançois Tigeot typedef struct _EXT_DISPLAY_PATH 4624c59a5c48SFrançois Tigeot { 4625c59a5c48SFrançois Tigeot USHORT usDeviceTag; //A bit vector to show what devices are supported 4626c59a5c48SFrançois Tigeot USHORT usDeviceACPIEnum; //16bit device ACPI id. 4627c59a5c48SFrançois Tigeot USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4628c59a5c48SFrançois Tigeot UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4629c59a5c48SFrançois Tigeot UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4630c59a5c48SFrançois Tigeot USHORT usExtEncoderObjId; //external encoder object id 4631c59a5c48SFrançois Tigeot union{ 4632c59a5c48SFrançois Tigeot UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4633c59a5c48SFrançois Tigeot ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4634c59a5c48SFrançois Tigeot ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4635c59a5c48SFrançois Tigeot }; 4636c59a5c48SFrançois Tigeot UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4637c59a5c48SFrançois Tigeot USHORT usCaps; 4638c59a5c48SFrançois Tigeot USHORT usReserved; 4639c59a5c48SFrançois Tigeot }EXT_DISPLAY_PATH; 4640c59a5c48SFrançois Tigeot 4641c59a5c48SFrançois Tigeot #define NUMBER_OF_UCHAR_FOR_GUID 16 4642c59a5c48SFrançois Tigeot #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4643c59a5c48SFrançois Tigeot 4644c59a5c48SFrançois Tigeot //usCaps 4645d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001 4646d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002 4647d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C 4648d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip 4649d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip 4650d78d3a22SFrançois Tigeot #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip 4651d78d3a22SFrançois Tigeot 4652d78d3a22SFrançois Tigeot 4653d78d3a22SFrançois Tigeot 4654c59a5c48SFrançois Tigeot 4655c59a5c48SFrançois Tigeot typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4656c59a5c48SFrançois Tigeot { 4657c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 4658c59a5c48SFrançois Tigeot UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4659c59a5c48SFrançois Tigeot EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4660c59a5c48SFrançois Tigeot UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4661c59a5c48SFrançois Tigeot UCHAR uc3DStereoPinId; // use for eDP panel 4662c59a5c48SFrançois Tigeot UCHAR ucRemoteDisplayConfig; 4663c59a5c48SFrançois Tigeot UCHAR uceDPToLVDSRxId; 4664c59a5c48SFrançois Tigeot UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4665c59a5c48SFrançois Tigeot UCHAR Reserved[3]; // for potential expansion 4666c59a5c48SFrançois Tigeot }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4667c59a5c48SFrançois Tigeot 4668c59a5c48SFrançois Tigeot //Related definitions, all records are differnt but they have a commond header 4669c59a5c48SFrançois Tigeot typedef struct _ATOM_COMMON_RECORD_HEADER 4670c59a5c48SFrançois Tigeot { 4671c59a5c48SFrançois Tigeot UCHAR ucRecordType; //An emun to indicate the record type 4672c59a5c48SFrançois Tigeot UCHAR ucRecordSize; //The size of the whole record in byte 4673c59a5c48SFrançois Tigeot }ATOM_COMMON_RECORD_HEADER; 4674c59a5c48SFrançois Tigeot 4675c59a5c48SFrançois Tigeot 4676c59a5c48SFrançois Tigeot #define ATOM_I2C_RECORD_TYPE 1 4677c59a5c48SFrançois Tigeot #define ATOM_HPD_INT_RECORD_TYPE 2 4678c59a5c48SFrançois Tigeot #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4679c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4680c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4681c59a5c48SFrançois Tigeot #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4682c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4683c59a5c48SFrançois Tigeot #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4684c59a5c48SFrançois Tigeot #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4685c59a5c48SFrançois Tigeot #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4686c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4687c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4688c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4689c59a5c48SFrançois Tigeot #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4690c59a5c48SFrançois Tigeot #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4691c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4692c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4693c59a5c48SFrançois Tigeot #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4694c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4695c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4696c59a5c48SFrançois Tigeot #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4697d78d3a22SFrançois Tigeot #define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22 4698c59a5c48SFrançois Tigeot 4699c59a5c48SFrançois Tigeot //Must be updated when new record type is added,equal to that record definition! 4700d78d3a22SFrançois Tigeot #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 4701c59a5c48SFrançois Tigeot 4702c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_RECORD 4703c59a5c48SFrançois Tigeot { 4704c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4705c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG sucI2cId; 4706c59a5c48SFrançois Tigeot UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4707c59a5c48SFrançois Tigeot }ATOM_I2C_RECORD; 4708c59a5c48SFrançois Tigeot 4709c59a5c48SFrançois Tigeot typedef struct _ATOM_HPD_INT_RECORD 4710c59a5c48SFrançois Tigeot { 4711c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4712c59a5c48SFrançois Tigeot UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4713c59a5c48SFrançois Tigeot UCHAR ucPlugged_PinState; 4714c59a5c48SFrançois Tigeot }ATOM_HPD_INT_RECORD; 4715c59a5c48SFrançois Tigeot 4716c59a5c48SFrançois Tigeot 4717c59a5c48SFrançois Tigeot typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4718c59a5c48SFrançois Tigeot { 4719c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4720c59a5c48SFrançois Tigeot UCHAR ucProtectionFlag; 4721c59a5c48SFrançois Tigeot UCHAR ucReserved; 4722c59a5c48SFrançois Tigeot }ATOM_OUTPUT_PROTECTION_RECORD; 4723c59a5c48SFrançois Tigeot 4724c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4725c59a5c48SFrançois Tigeot { 4726c59a5c48SFrançois Tigeot ULONG ulACPIDeviceEnum; //Reserved for now 4727c59a5c48SFrançois Tigeot USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4728c59a5c48SFrançois Tigeot USHORT usPadding; 4729c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_DEVICE_TAG; 4730c59a5c48SFrançois Tigeot 4731c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4732c59a5c48SFrançois Tigeot { 4733c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4734c59a5c48SFrançois Tigeot UCHAR ucNumberOfDevice; 4735c59a5c48SFrançois Tigeot UCHAR ucReserved; 4736c59a5c48SFrançois Tigeot ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4737c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4738c59a5c48SFrançois Tigeot 4739c59a5c48SFrançois Tigeot 4740c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4741c59a5c48SFrançois Tigeot { 4742c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4743c59a5c48SFrançois Tigeot UCHAR ucConfigGPIOID; 4744c59a5c48SFrançois Tigeot UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4745c59a5c48SFrançois Tigeot UCHAR ucFlowinGPIPID; 4746c59a5c48SFrançois Tigeot UCHAR ucExtInGPIPID; 4747c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4748c59a5c48SFrançois Tigeot 4749c59a5c48SFrançois Tigeot typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4750c59a5c48SFrançois Tigeot { 4751c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4752c59a5c48SFrançois Tigeot UCHAR ucCTL1GPIO_ID; 4753c59a5c48SFrançois Tigeot UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4754c59a5c48SFrançois Tigeot UCHAR ucCTL2GPIO_ID; 4755c59a5c48SFrançois Tigeot UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4756c59a5c48SFrançois Tigeot UCHAR ucCTL3GPIO_ID; 4757c59a5c48SFrançois Tigeot UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4758c59a5c48SFrançois Tigeot UCHAR ucCTLFPGA_IN_ID; 4759c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 4760c59a5c48SFrançois Tigeot }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4761c59a5c48SFrançois Tigeot 4762c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4763c59a5c48SFrançois Tigeot { 4764c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4765c59a5c48SFrançois Tigeot UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4766c59a5c48SFrançois Tigeot UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4767c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4768c59a5c48SFrançois Tigeot 4769c59a5c48SFrançois Tigeot typedef struct _ATOM_JTAG_RECORD 4770c59a5c48SFrançois Tigeot { 4771c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4772c59a5c48SFrançois Tigeot UCHAR ucTMSGPIO_ID; 4773c59a5c48SFrançois Tigeot UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4774c59a5c48SFrançois Tigeot UCHAR ucTCKGPIO_ID; 4775c59a5c48SFrançois Tigeot UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4776c59a5c48SFrançois Tigeot UCHAR ucTDOGPIO_ID; 4777c59a5c48SFrançois Tigeot UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4778c59a5c48SFrançois Tigeot UCHAR ucTDIGPIO_ID; 4779c59a5c48SFrançois Tigeot UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4780c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 4781c59a5c48SFrançois Tigeot }ATOM_JTAG_RECORD; 4782c59a5c48SFrançois Tigeot 4783c59a5c48SFrançois Tigeot 4784c59a5c48SFrançois Tigeot //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4785c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4786c59a5c48SFrançois Tigeot { 4787c59a5c48SFrançois Tigeot UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4788c59a5c48SFrançois Tigeot UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4789c59a5c48SFrançois Tigeot }ATOM_GPIO_PIN_CONTROL_PAIR; 4790c59a5c48SFrançois Tigeot 4791c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4792c59a5c48SFrançois Tigeot { 4793c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4794c59a5c48SFrançois Tigeot UCHAR ucFlags; // Future expnadibility 4795c59a5c48SFrançois Tigeot UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4796c59a5c48SFrançois Tigeot ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4797c59a5c48SFrançois Tigeot }ATOM_OBJECT_GPIO_CNTL_RECORD; 4798c59a5c48SFrançois Tigeot 4799c59a5c48SFrançois Tigeot //Definitions for GPIO pin state 4800c59a5c48SFrançois Tigeot #define GPIO_PIN_TYPE_INPUT 0x00 4801c59a5c48SFrançois Tigeot #define GPIO_PIN_TYPE_OUTPUT 0x10 4802c59a5c48SFrançois Tigeot #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4803c59a5c48SFrançois Tigeot 4804c59a5c48SFrançois Tigeot //For GPIO_PIN_TYPE_OUTPUT the following is defined 4805c59a5c48SFrançois Tigeot #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4806c59a5c48SFrançois Tigeot #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4807c59a5c48SFrançois Tigeot #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4808c59a5c48SFrançois Tigeot #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4809c59a5c48SFrançois Tigeot 4810c59a5c48SFrançois Tigeot // Indexes to GPIO array in GLSync record 4811c59a5c48SFrançois Tigeot // GLSync record is for Frame Lock/Gen Lock feature. 4812c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4813c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4814c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4815c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4816c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4817c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4818c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4819c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4820c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4821c59a5c48SFrançois Tigeot #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4822c59a5c48SFrançois Tigeot 4823c59a5c48SFrançois Tigeot typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4824c59a5c48SFrançois Tigeot { 4825c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4826c59a5c48SFrançois Tigeot ULONG ulStrengthControl; // DVOA strength control for CF 4827c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 4828c59a5c48SFrançois Tigeot }ATOM_ENCODER_DVO_CF_RECORD; 4829c59a5c48SFrançois Tigeot 4830d78d3a22SFrançois Tigeot // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 4831d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 4832d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. 4833c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4834c59a5c48SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4835d78d3a22SFrançois Tigeot #define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board. 4836c59a5c48SFrançois Tigeot 4837c59a5c48SFrançois Tigeot typedef struct _ATOM_ENCODER_CAP_RECORD 4838c59a5c48SFrançois Tigeot { 4839c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4840c59a5c48SFrançois Tigeot union { 4841c59a5c48SFrançois Tigeot USHORT usEncoderCap; 4842c59a5c48SFrançois Tigeot struct { 4843c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 4844c59a5c48SFrançois Tigeot USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4845c59a5c48SFrançois Tigeot USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4846c59a5c48SFrançois Tigeot USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4847c59a5c48SFrançois Tigeot #else 4848c59a5c48SFrançois Tigeot USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4849c59a5c48SFrançois Tigeot USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4850c59a5c48SFrançois Tigeot USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4851c59a5c48SFrançois Tigeot #endif 4852c59a5c48SFrançois Tigeot }; 4853c59a5c48SFrançois Tigeot }; 4854c59a5c48SFrançois Tigeot }ATOM_ENCODER_CAP_RECORD; 4855c59a5c48SFrançois Tigeot 4856d78d3a22SFrançois Tigeot // Used after SI 4857d78d3a22SFrançois Tigeot typedef struct _ATOM_ENCODER_CAP_RECORD_V2 4858d78d3a22SFrançois Tigeot { 4859d78d3a22SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4860d78d3a22SFrançois Tigeot union { 4861d78d3a22SFrançois Tigeot USHORT usEncoderCap; 4862d78d3a22SFrançois Tigeot struct { 4863d78d3a22SFrançois Tigeot #if ATOM_BIG_ENDIAN 4864d78d3a22SFrançois Tigeot USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4865d78d3a22SFrançois Tigeot USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4866d78d3a22SFrançois Tigeot USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4867d78d3a22SFrançois Tigeot USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4868d78d3a22SFrançois Tigeot USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4869d78d3a22SFrançois Tigeot #else 4870d78d3a22SFrançois Tigeot USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4871d78d3a22SFrançois Tigeot USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4872d78d3a22SFrançois Tigeot USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4873d78d3a22SFrançois Tigeot USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4874d78d3a22SFrançois Tigeot USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4875d78d3a22SFrançois Tigeot #endif 4876d78d3a22SFrançois Tigeot }; 4877d78d3a22SFrançois Tigeot }; 4878d78d3a22SFrançois Tigeot }ATOM_ENCODER_CAP_RECORD_V2; 4879d78d3a22SFrançois Tigeot 4880d78d3a22SFrançois Tigeot 4881c59a5c48SFrançois Tigeot // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4882c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4883c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4884c59a5c48SFrançois Tigeot 4885c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_CF_RECORD 4886c59a5c48SFrançois Tigeot { 4887c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4888c59a5c48SFrançois Tigeot USHORT usMaxPixClk; 4889c59a5c48SFrançois Tigeot UCHAR ucFlowCntlGpioId; 4890c59a5c48SFrançois Tigeot UCHAR ucSwapCntlGpioId; 4891c59a5c48SFrançois Tigeot UCHAR ucConnectedDvoBundle; 4892c59a5c48SFrançois Tigeot UCHAR ucPadding; 4893c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_CF_RECORD; 4894c59a5c48SFrançois Tigeot 4895c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4896c59a5c48SFrançois Tigeot { 4897c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4898c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT asTiming; 4899c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4900c59a5c48SFrançois Tigeot 4901c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4902c59a5c48SFrançois Tigeot { 4903c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4904c59a5c48SFrançois Tigeot UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4905c59a5c48SFrançois Tigeot UCHAR ucReserved; 4906c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4907c59a5c48SFrançois Tigeot 4908c59a5c48SFrançois Tigeot 4909c59a5c48SFrançois Tigeot typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4910c59a5c48SFrançois Tigeot { 4911c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4912c59a5c48SFrançois Tigeot UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4913c59a5c48SFrançois Tigeot UCHAR ucMuxControlPin; 4914c59a5c48SFrançois Tigeot UCHAR ucMuxState[2]; //for alligment purpose 4915c59a5c48SFrançois Tigeot }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4916c59a5c48SFrançois Tigeot 4917c59a5c48SFrançois Tigeot typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4918c59a5c48SFrançois Tigeot { 4919c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4920c59a5c48SFrançois Tigeot UCHAR ucMuxType; 4921c59a5c48SFrançois Tigeot UCHAR ucMuxControlPin; 4922c59a5c48SFrançois Tigeot UCHAR ucMuxState[2]; //for alligment purpose 4923c59a5c48SFrançois Tigeot }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4924c59a5c48SFrançois Tigeot 4925c59a5c48SFrançois Tigeot // define ucMuxType 4926c59a5c48SFrançois Tigeot #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4927c59a5c48SFrançois Tigeot #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4928c59a5c48SFrançois Tigeot 4929c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4930c59a5c48SFrançois Tigeot { 4931c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4932c59a5c48SFrançois Tigeot UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4933c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4934c59a5c48SFrançois Tigeot 4935c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4936c59a5c48SFrançois Tigeot { 4937c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4938c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4939c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4940c59a5c48SFrançois Tigeot 4941c59a5c48SFrançois Tigeot typedef struct _ATOM_OBJECT_LINK_RECORD 4942c59a5c48SFrançois Tigeot { 4943c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4944c59a5c48SFrançois Tigeot USHORT usObjectID; //could be connector, encorder or other object in object.h 4945c59a5c48SFrançois Tigeot }ATOM_OBJECT_LINK_RECORD; 4946c59a5c48SFrançois Tigeot 4947c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4948c59a5c48SFrançois Tigeot { 4949c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4950c59a5c48SFrançois Tigeot USHORT usReserved; 4951c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4952c59a5c48SFrançois Tigeot 4953d78d3a22SFrançois Tigeot 4954d78d3a22SFrançois Tigeot typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD 4955d78d3a22SFrançois Tigeot { 4956d78d3a22SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4957d78d3a22SFrançois Tigeot // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 4958d78d3a22SFrançois Tigeot UCHAR ucMaxTmdsClkRateIn2_5Mhz; 4959d78d3a22SFrançois Tigeot UCHAR ucReserved; 4960d78d3a22SFrançois Tigeot } ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; 4961d78d3a22SFrançois Tigeot 4962d78d3a22SFrançois Tigeot 4963c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4964c59a5c48SFrançois Tigeot { 4965c59a5c48SFrançois Tigeot USHORT usConnectorObjectId; 4966c59a5c48SFrançois Tigeot UCHAR ucConnectorType; 4967c59a5c48SFrançois Tigeot UCHAR ucPosition; 4968c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_LAYOUT_INFO; 4969c59a5c48SFrançois Tigeot 4970c59a5c48SFrançois Tigeot // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4971c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_DVI_D 1 4972c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_DVI_I 2 4973c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_VGA 3 4974c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_HDMI 4 4975c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_DISPLAY_PORT 5 4976c59a5c48SFrançois Tigeot #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4977c59a5c48SFrançois Tigeot 4978c59a5c48SFrançois Tigeot typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4979c59a5c48SFrançois Tigeot { 4980c59a5c48SFrançois Tigeot ATOM_COMMON_RECORD_HEADER sheader; 4981c59a5c48SFrançois Tigeot UCHAR ucLength; 4982c59a5c48SFrançois Tigeot UCHAR ucWidth; 4983c59a5c48SFrançois Tigeot UCHAR ucConnNum; 4984c59a5c48SFrançois Tigeot UCHAR ucReserved; 4985c59a5c48SFrançois Tigeot ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4986c59a5c48SFrançois Tigeot }ATOM_BRACKET_LAYOUT_RECORD; 4987c59a5c48SFrançois Tigeot 4988c59a5c48SFrançois Tigeot 4989c59a5c48SFrançois Tigeot /****************************************************************************/ 4990c59a5c48SFrançois Tigeot // Structure used in XXXX 4991c59a5c48SFrançois Tigeot /****************************************************************************/ 4992c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_INFO_HEADER 4993c59a5c48SFrançois Tigeot { 4994c59a5c48SFrançois Tigeot USHORT usVDDCBaseLevel; //In number of 50mv unit 4995c59a5c48SFrançois Tigeot USHORT usReserved; //For possible extension table offset 4996c59a5c48SFrançois Tigeot UCHAR ucNumOfVoltageEntries; 4997c59a5c48SFrançois Tigeot UCHAR ucBytesPerVoltageEntry; 4998c59a5c48SFrançois Tigeot UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4999c59a5c48SFrançois Tigeot UCHAR ucDefaultVoltageEntry; 5000c59a5c48SFrançois Tigeot UCHAR ucVoltageControlI2cLine; 5001c59a5c48SFrançois Tigeot UCHAR ucVoltageControlAddress; 5002c59a5c48SFrançois Tigeot UCHAR ucVoltageControlOffset; 5003c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_INFO_HEADER; 5004c59a5c48SFrançois Tigeot 5005c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_INFO 5006c59a5c48SFrançois Tigeot { 5007c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5008c59a5c48SFrançois Tigeot ATOM_VOLTAGE_INFO_HEADER viHeader; 5009c59a5c48SFrançois Tigeot UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 5010c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_INFO; 5011c59a5c48SFrançois Tigeot 5012c59a5c48SFrançois Tigeot 5013c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_FORMULA 5014c59a5c48SFrançois Tigeot { 5015c59a5c48SFrançois Tigeot USHORT usVoltageBaseLevel; // In number of 1mv unit 5016c59a5c48SFrançois Tigeot USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 5017c59a5c48SFrançois Tigeot UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5018c59a5c48SFrançois Tigeot UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 5019c59a5c48SFrançois Tigeot UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 5020c59a5c48SFrançois Tigeot UCHAR ucReserved; 5021c59a5c48SFrançois Tigeot UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 5022c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_FORMULA; 5023c59a5c48SFrançois Tigeot 5024c59a5c48SFrançois Tigeot typedef struct _VOLTAGE_LUT_ENTRY 5025c59a5c48SFrançois Tigeot { 5026c59a5c48SFrançois Tigeot USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 5027c59a5c48SFrançois Tigeot USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5028c59a5c48SFrançois Tigeot }VOLTAGE_LUT_ENTRY; 5029c59a5c48SFrançois Tigeot 5030c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_FORMULA_V2 5031c59a5c48SFrançois Tigeot { 5032c59a5c48SFrançois Tigeot UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5033c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 5034c59a5c48SFrançois Tigeot VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 5035c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_FORMULA_V2; 5036c59a5c48SFrançois Tigeot 5037c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_CONTROL 5038c59a5c48SFrançois Tigeot { 5039c59a5c48SFrançois Tigeot UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 5040c59a5c48SFrançois Tigeot UCHAR ucVoltageControlI2cLine; 5041c59a5c48SFrançois Tigeot UCHAR ucVoltageControlAddress; 5042c59a5c48SFrançois Tigeot UCHAR ucVoltageControlOffset; 5043c59a5c48SFrançois Tigeot USHORT usGpioPin_AIndex; //GPIO_PAD register index 5044c59a5c48SFrançois Tigeot UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 5045c59a5c48SFrançois Tigeot UCHAR ucReserved; 5046c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_CONTROL; 5047c59a5c48SFrançois Tigeot 5048c59a5c48SFrançois Tigeot // Define ucVoltageControlId 5049c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROLLED_BY_HW 0x00 5050c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 5051c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 5052c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 5053c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 5054c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 5055c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_DS4402 0x04 5056c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_UP6266 0x05 5057c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 5058c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_VT1556M 0x07 5059c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_CHL822x 0x08 5060c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_VT1586M 0x09 5061c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_UP1637 0x0A 5062c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_CHL8214 0x0B 5063c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_UP1801 0x0C 5064c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_ST6788A 0x0D 5065c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 5066c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_AD527x 0x0F 5067c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_NCP81022 0x10 5068c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_LTC2635 0x11 5069c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_NCP4208 0x12 5070c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_IR35xx 0x13 5071c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_RT9403 0x14 5072c59a5c48SFrançois Tigeot 5073c59a5c48SFrançois Tigeot #define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 5074c59a5c48SFrançois Tigeot 5075c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT 5076c59a5c48SFrançois Tigeot { 5077c59a5c48SFrançois Tigeot UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5078c59a5c48SFrançois Tigeot UCHAR ucSize; //Size of Object 5079c59a5c48SFrançois Tigeot ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5080c59a5c48SFrançois Tigeot ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 5081c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT; 5082c59a5c48SFrançois Tigeot 5083c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT_V2 5084c59a5c48SFrançois Tigeot { 5085c59a5c48SFrançois Tigeot UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5086c59a5c48SFrançois Tigeot UCHAR ucSize; //Size of Object 5087c59a5c48SFrançois Tigeot ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5088c59a5c48SFrançois Tigeot ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 5089c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_V2; 5090c59a5c48SFrançois Tigeot 5091c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT_INFO 5092c59a5c48SFrançois Tigeot { 5093c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5094c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 5095c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_INFO; 5096c59a5c48SFrançois Tigeot 5097c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 5098c59a5c48SFrançois Tigeot { 5099c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5100c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 5101c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_INFO_V2; 5102c59a5c48SFrançois Tigeot 5103c59a5c48SFrançois Tigeot typedef struct _ATOM_LEAKID_VOLTAGE 5104c59a5c48SFrançois Tigeot { 5105c59a5c48SFrançois Tigeot UCHAR ucLeakageId; 5106c59a5c48SFrançois Tigeot UCHAR ucReserved; 5107c59a5c48SFrançois Tigeot USHORT usVoltage; 5108c59a5c48SFrançois Tigeot }ATOM_LEAKID_VOLTAGE; 5109c59a5c48SFrançois Tigeot 5110c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 5111c59a5c48SFrançois Tigeot UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5112c59a5c48SFrançois Tigeot UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 5113c59a5c48SFrançois Tigeot USHORT usSize; //Size of Object 5114c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_HEADER_V3; 5115c59a5c48SFrançois Tigeot 5116c59a5c48SFrançois Tigeot // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 5117c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5118c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 5119c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5120c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 5121c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_EVV 8 5122c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5123c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5124c59a5c48SFrançois Tigeot #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5125c59a5c48SFrançois Tigeot 5126c59a5c48SFrançois Tigeot typedef struct _VOLTAGE_LUT_ENTRY_V2 5127c59a5c48SFrançois Tigeot { 5128c59a5c48SFrançois Tigeot ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 5129c59a5c48SFrançois Tigeot USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5130c59a5c48SFrançois Tigeot }VOLTAGE_LUT_ENTRY_V2; 5131c59a5c48SFrançois Tigeot 5132c59a5c48SFrançois Tigeot typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 5133c59a5c48SFrançois Tigeot { 5134c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 5135c59a5c48SFrançois Tigeot USHORT usVoltageId; 5136c59a5c48SFrançois Tigeot USHORT usLeakageId; // The corresponding Voltage Value, in mV 5137c59a5c48SFrançois Tigeot }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 5138c59a5c48SFrançois Tigeot 5139c59a5c48SFrançois Tigeot 5140c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 5141c59a5c48SFrançois Tigeot { 5142c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 5143c59a5c48SFrançois Tigeot UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 5144c59a5c48SFrançois Tigeot UCHAR ucVoltageControlI2cLine; 5145c59a5c48SFrançois Tigeot UCHAR ucVoltageControlAddress; 5146c59a5c48SFrançois Tigeot UCHAR ucVoltageControlOffset; 5147c59a5c48SFrançois Tigeot UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 5148c59a5c48SFrançois Tigeot UCHAR ulReserved[3]; 5149c59a5c48SFrançois Tigeot VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 5150c59a5c48SFrançois Tigeot }ATOM_I2C_VOLTAGE_OBJECT_V3; 5151c59a5c48SFrançois Tigeot 5152c59a5c48SFrançois Tigeot // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 5153c59a5c48SFrançois Tigeot #define VOLTAGE_DATA_ONE_BYTE 0 5154c59a5c48SFrançois Tigeot #define VOLTAGE_DATA_TWO_BYTE 1 5155c59a5c48SFrançois Tigeot 5156c59a5c48SFrançois Tigeot typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 5157c59a5c48SFrançois Tigeot { 5158c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 5159c59a5c48SFrançois Tigeot UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 5160c59a5c48SFrançois Tigeot UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 5161c59a5c48SFrançois Tigeot UCHAR ucPhaseDelay; // phase delay in unit of micro second 5162c59a5c48SFrançois Tigeot UCHAR ucReserved; 5163c59a5c48SFrançois Tigeot ULONG ulGpioMaskVal; // GPIO Mask value 5164c59a5c48SFrançois Tigeot VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 5165c59a5c48SFrançois Tigeot }ATOM_GPIO_VOLTAGE_OBJECT_V3; 5166c59a5c48SFrançois Tigeot 5167c59a5c48SFrançois Tigeot typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5168c59a5c48SFrançois Tigeot { 5169c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 5170c59a5c48SFrançois Tigeot UCHAR ucLeakageCntlId; // default is 0 5171c59a5c48SFrançois Tigeot UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 5172c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 5173c59a5c48SFrançois Tigeot ULONG ulMaxVoltageLevel; 5174c59a5c48SFrançois Tigeot LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 5175c59a5c48SFrançois Tigeot }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 5176c59a5c48SFrançois Tigeot 5177c59a5c48SFrançois Tigeot 5178c59a5c48SFrançois Tigeot typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 5179c59a5c48SFrançois Tigeot { 5180c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5181c59a5c48SFrançois Tigeot // 14:7 � PSI0_VID 5182c59a5c48SFrançois Tigeot // 6 � PSI0_EN 5183c59a5c48SFrançois Tigeot // 5 � PSI1 5184c59a5c48SFrançois Tigeot // 4:2 � load line slope trim. 5185c59a5c48SFrançois Tigeot // 1:0 � offset trim, 5186c59a5c48SFrançois Tigeot USHORT usLoadLine_PSI; 5187c59a5c48SFrançois Tigeot // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 5188c59a5c48SFrançois Tigeot UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 5189c59a5c48SFrançois Tigeot UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 5190c59a5c48SFrançois Tigeot ULONG ulReserved; 5191c59a5c48SFrançois Tigeot }ATOM_SVID2_VOLTAGE_OBJECT_V3; 5192c59a5c48SFrançois Tigeot 5193d78d3a22SFrançois Tigeot 5194d78d3a22SFrançois Tigeot 5195d78d3a22SFrançois Tigeot typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3 5196d78d3a22SFrançois Tigeot { 5197d78d3a22SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 5198d78d3a22SFrançois Tigeot UCHAR ucMergedVType; // VDDC/VDCCI/.... 5199d78d3a22SFrançois Tigeot UCHAR ucReserved[3]; 5200d78d3a22SFrançois Tigeot }ATOM_MERGED_VOLTAGE_OBJECT_V3; 5201d78d3a22SFrançois Tigeot 5202d78d3a22SFrançois Tigeot 5203d78d3a22SFrançois Tigeot typedef struct _ATOM_EVV_DPM_INFO 5204d78d3a22SFrançois Tigeot { 5205d78d3a22SFrançois Tigeot ULONG ulDPMSclk; // DPM state SCLK 5206d78d3a22SFrançois Tigeot USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv 5207d78d3a22SFrançois Tigeot UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable 5208d78d3a22SFrançois Tigeot UCHAR ucDPMState; // DPMState0~7 5209d78d3a22SFrançois Tigeot } ATOM_EVV_DPM_INFO; 5210d78d3a22SFrançois Tigeot 5211d78d3a22SFrançois Tigeot // ucVoltageMode = VOLTAGE_OBJ_EVV 5212d78d3a22SFrançois Tigeot typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3 5213d78d3a22SFrançois Tigeot { 5214d78d3a22SFrançois Tigeot ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5215d78d3a22SFrançois Tigeot ATOM_EVV_DPM_INFO asEvvDpmList[8]; 5216d78d3a22SFrançois Tigeot }ATOM_EVV_VOLTAGE_OBJECT_V3; 5217d78d3a22SFrançois Tigeot 5218d78d3a22SFrançois Tigeot 5219c59a5c48SFrançois Tigeot typedef union _ATOM_VOLTAGE_OBJECT_V3{ 5220c59a5c48SFrançois Tigeot ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 5221c59a5c48SFrançois Tigeot ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 5222c59a5c48SFrançois Tigeot ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 5223c59a5c48SFrançois Tigeot ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 5224d78d3a22SFrançois Tigeot ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj; 5225c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_V3; 5226c59a5c48SFrançois Tigeot 5227c59a5c48SFrançois Tigeot typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 5228c59a5c48SFrançois Tigeot { 5229c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5230c59a5c48SFrançois Tigeot ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 5231c59a5c48SFrançois Tigeot }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 5232c59a5c48SFrançois Tigeot 5233c59a5c48SFrançois Tigeot 5234c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 5235c59a5c48SFrançois Tigeot { 5236c59a5c48SFrançois Tigeot UCHAR ucProfileId; 5237c59a5c48SFrançois Tigeot UCHAR ucReserved; 5238c59a5c48SFrançois Tigeot USHORT usSize; 5239c59a5c48SFrançois Tigeot USHORT usEfuseSpareStartAddr; 5240c59a5c48SFrançois Tigeot USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 5241c59a5c48SFrançois Tigeot ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 5242c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILE_VOLTAGE; 5243c59a5c48SFrançois Tigeot 5244c59a5c48SFrançois Tigeot //ucProfileId 5245c59a5c48SFrançois Tigeot #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 5246c59a5c48SFrançois Tigeot #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 5247c59a5c48SFrançois Tigeot #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 5248c59a5c48SFrançois Tigeot 5249c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO 5250c59a5c48SFrançois Tigeot { 5251c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5252c59a5c48SFrançois Tigeot ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 5253c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO; 5254c59a5c48SFrançois Tigeot 5255c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 5256c59a5c48SFrançois Tigeot { 5257c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5258c59a5c48SFrançois Tigeot UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 5259c59a5c48SFrançois Tigeot USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 5260c59a5c48SFrançois Tigeot 5261c59a5c48SFrançois Tigeot UCHAR ucElbVDDC_Num; 5262c59a5c48SFrançois Tigeot USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 5263c59a5c48SFrançois Tigeot USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5264c59a5c48SFrançois Tigeot 5265c59a5c48SFrançois Tigeot UCHAR ucElbVDDCI_Num; 5266c59a5c48SFrançois Tigeot USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 5267c59a5c48SFrançois Tigeot USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5268c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V2_1; 5269c59a5c48SFrançois Tigeot 5270c59a5c48SFrançois Tigeot 5271c59a5c48SFrançois Tigeot //Here is parameter to convert Efuse value to Measure value 5272c59a5c48SFrançois Tigeot //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 5273c59a5c48SFrançois Tigeot typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 5274c59a5c48SFrançois Tigeot { 5275c59a5c48SFrançois Tigeot USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5276c59a5c48SFrançois Tigeot UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5277c59a5c48SFrançois Tigeot UCHAR ucEfuseLength; // Efuse bits length, 5278c59a5c48SFrançois Tigeot ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5279c59a5c48SFrançois Tigeot ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 5280c59a5c48SFrançois Tigeot }EFUSE_LOGISTIC_FUNC_PARAM; 5281c59a5c48SFrançois Tigeot 5282c59a5c48SFrançois Tigeot //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 5283c59a5c48SFrançois Tigeot typedef struct _EFUSE_LINEAR_FUNC_PARAM 5284c59a5c48SFrançois Tigeot { 5285c59a5c48SFrançois Tigeot USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5286c59a5c48SFrançois Tigeot UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5287c59a5c48SFrançois Tigeot UCHAR ucEfuseLength; // Efuse bits length, 5288c59a5c48SFrançois Tigeot ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5289c59a5c48SFrançois Tigeot ULONG ulEfuseMin; // Min 5290c59a5c48SFrançois Tigeot }EFUSE_LINEAR_FUNC_PARAM; 5291c59a5c48SFrançois Tigeot 5292c59a5c48SFrançois Tigeot 5293c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 5294c59a5c48SFrançois Tigeot { 5295c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5296c59a5c48SFrançois Tigeot ULONG ulEvvDerateTdp; 5297c59a5c48SFrançois Tigeot ULONG ulEvvDerateTdc; 5298c59a5c48SFrançois Tigeot ULONG ulBoardCoreTemp; 5299c59a5c48SFrançois Tigeot ULONG ulMaxVddc; 5300c59a5c48SFrançois Tigeot ULONG ulMinVddc; 5301c59a5c48SFrançois Tigeot ULONG ulLoadLineSlop; 5302c59a5c48SFrançois Tigeot ULONG ulLeakageTemp; 5303c59a5c48SFrançois Tigeot ULONG ulLeakageVoltage; 5304c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACm; 5305c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACb; 5306c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5307c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5308c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5309c59a5c48SFrançois Tigeot USHORT usLkgEuseIndex; 5310c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; 5311c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseLength; 5312c59a5c48SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; 5313c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMax; 5314c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMin; 5315c59a5c48SFrançois Tigeot ULONG ulEfuseLogisticAlpha; 5316c59a5c48SFrançois Tigeot USHORT usPowerDpm0; 5317c59a5c48SFrançois Tigeot USHORT usCurrentDpm0; 5318c59a5c48SFrançois Tigeot USHORT usPowerDpm1; 5319c59a5c48SFrançois Tigeot USHORT usCurrentDpm1; 5320c59a5c48SFrançois Tigeot USHORT usPowerDpm2; 5321c59a5c48SFrançois Tigeot USHORT usCurrentDpm2; 5322c59a5c48SFrançois Tigeot USHORT usPowerDpm3; 5323c59a5c48SFrançois Tigeot USHORT usCurrentDpm3; 5324c59a5c48SFrançois Tigeot USHORT usPowerDpm4; 5325c59a5c48SFrançois Tigeot USHORT usCurrentDpm4; 5326c59a5c48SFrançois Tigeot USHORT usPowerDpm5; 5327c59a5c48SFrançois Tigeot USHORT usCurrentDpm5; 5328c59a5c48SFrançois Tigeot USHORT usPowerDpm6; 5329c59a5c48SFrançois Tigeot USHORT usCurrentDpm6; 5330c59a5c48SFrançois Tigeot USHORT usPowerDpm7; 5331c59a5c48SFrançois Tigeot USHORT usCurrentDpm7; 5332c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_1; 5333c59a5c48SFrançois Tigeot 5334c59a5c48SFrançois Tigeot 5335c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 5336c59a5c48SFrançois Tigeot { 5337c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5338c59a5c48SFrançois Tigeot ULONG ulEvvLkgFactor; 5339c59a5c48SFrançois Tigeot ULONG ulBoardCoreTemp; 5340c59a5c48SFrançois Tigeot ULONG ulMaxVddc; 5341c59a5c48SFrançois Tigeot ULONG ulMinVddc; 5342c59a5c48SFrançois Tigeot ULONG ulLoadLineSlop; 5343c59a5c48SFrançois Tigeot ULONG ulLeakageTemp; 5344c59a5c48SFrançois Tigeot ULONG ulLeakageVoltage; 5345c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACm; 5346c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACb; 5347c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5348c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5349c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5350c59a5c48SFrançois Tigeot USHORT usLkgEuseIndex; 5351c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; 5352c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseLength; 5353c59a5c48SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; 5354c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMax; 5355c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMin; 5356c59a5c48SFrançois Tigeot ULONG ulEfuseLogisticAlpha; 5357c59a5c48SFrançois Tigeot USHORT usPowerDpm0; 5358c59a5c48SFrançois Tigeot USHORT usPowerDpm1; 5359c59a5c48SFrançois Tigeot USHORT usPowerDpm2; 5360c59a5c48SFrançois Tigeot USHORT usPowerDpm3; 5361c59a5c48SFrançois Tigeot USHORT usPowerDpm4; 5362c59a5c48SFrançois Tigeot USHORT usPowerDpm5; 5363c59a5c48SFrançois Tigeot USHORT usPowerDpm6; 5364c59a5c48SFrançois Tigeot USHORT usPowerDpm7; 5365c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM0; 5366c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM1; 5367c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM2; 5368c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM3; 5369c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM4; 5370c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM5; 5371c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM6; 5372c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM7; 5373c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_2; 5374c59a5c48SFrançois Tigeot 5375c59a5c48SFrançois Tigeot 5376c59a5c48SFrançois Tigeot // for Tonga/Fiji speed EVV algorithm 5377c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 5378c59a5c48SFrançois Tigeot { 5379c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5380c59a5c48SFrançois Tigeot ULONG ulEvvLkgFactor; 5381c59a5c48SFrançois Tigeot ULONG ulBoardCoreTemp; 5382c59a5c48SFrançois Tigeot ULONG ulMaxVddc; 5383c59a5c48SFrançois Tigeot ULONG ulMinVddc; 5384c59a5c48SFrançois Tigeot ULONG ulLoadLineSlop; 5385c59a5c48SFrançois Tigeot ULONG ulLeakageTemp; 5386c59a5c48SFrançois Tigeot ULONG ulLeakageVoltage; 5387c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACm; 5388c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACb; 5389c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5390c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5391c59a5c48SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5392c59a5c48SFrançois Tigeot USHORT usLkgEuseIndex; 5393c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; 5394c59a5c48SFrançois Tigeot UCHAR ucLkgEfuseLength; 5395c59a5c48SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; 5396c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMax; 5397c59a5c48SFrançois Tigeot ULONG ulLkgEncodeMin; 5398c59a5c48SFrançois Tigeot ULONG ulEfuseLogisticAlpha; 5399d78d3a22SFrançois Tigeot 5400d78d3a22SFrançois Tigeot union{ 5401c59a5c48SFrançois Tigeot USHORT usPowerDpm0; 5402d78d3a22SFrançois Tigeot USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive 5403d78d3a22SFrançois Tigeot }; 5404c59a5c48SFrançois Tigeot USHORT usPowerDpm1; 5405c59a5c48SFrançois Tigeot USHORT usPowerDpm2; 5406c59a5c48SFrançois Tigeot USHORT usPowerDpm3; 5407c59a5c48SFrançois Tigeot USHORT usPowerDpm4; 5408c59a5c48SFrançois Tigeot USHORT usPowerDpm5; 5409c59a5c48SFrançois Tigeot USHORT usPowerDpm6; 5410c59a5c48SFrançois Tigeot USHORT usPowerDpm7; 5411c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM0; 5412c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM1; 5413c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM2; 5414c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM3; 5415c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM4; 5416c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM5; 5417c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM6; 5418c59a5c48SFrançois Tigeot ULONG ulTdpDerateDPM7; 5419c59a5c48SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5420c59a5c48SFrançois Tigeot ULONG ulRoAlpha; 5421c59a5c48SFrançois Tigeot ULONG ulRoBeta; 5422c59a5c48SFrançois Tigeot ULONG ulRoGamma; 5423c59a5c48SFrançois Tigeot ULONG ulRoEpsilon; 5424c59a5c48SFrançois Tigeot ULONG ulATermRo; 5425c59a5c48SFrançois Tigeot ULONG ulBTermRo; 5426c59a5c48SFrançois Tigeot ULONG ulCTermRo; 5427c59a5c48SFrançois Tigeot ULONG ulSclkMargin; 5428c59a5c48SFrançois Tigeot ULONG ulFmaxPercent; 5429c59a5c48SFrançois Tigeot ULONG ulCRPercent; 5430c59a5c48SFrançois Tigeot ULONG ulSFmaxPercent; 5431c59a5c48SFrançois Tigeot ULONG ulSCRPercent; 5432c59a5c48SFrançois Tigeot ULONG ulSDCMargine; 5433c59a5c48SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_3; 5434c59a5c48SFrançois Tigeot 5435d78d3a22SFrançois Tigeot // for Fiji speed EVV algorithm 5436d78d3a22SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 5437d78d3a22SFrançois Tigeot { 5438d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5439d78d3a22SFrançois Tigeot ULONG ulEvvLkgFactor; 5440d78d3a22SFrançois Tigeot ULONG ulBoardCoreTemp; 5441d78d3a22SFrançois Tigeot ULONG ulMaxVddc; 5442d78d3a22SFrançois Tigeot ULONG ulMinVddc; 5443d78d3a22SFrançois Tigeot ULONG ulLoadLineSlop; 5444d78d3a22SFrançois Tigeot ULONG ulLeakageTemp; 5445d78d3a22SFrançois Tigeot ULONG ulLeakageVoltage; 5446d78d3a22SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACm; 5447d78d3a22SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sCACb; 5448d78d3a22SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5449d78d3a22SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5450d78d3a22SFrançois Tigeot EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5451d78d3a22SFrançois Tigeot USHORT usLkgEuseIndex; 5452d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; 5453d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseLength; 5454d78d3a22SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; 5455d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMax; 5456d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMin; 5457d78d3a22SFrançois Tigeot ULONG ulEfuseLogisticAlpha; 5458d78d3a22SFrançois Tigeot USHORT usPowerDpm0; 5459d78d3a22SFrançois Tigeot USHORT usPowerDpm1; 5460d78d3a22SFrançois Tigeot USHORT usPowerDpm2; 5461d78d3a22SFrançois Tigeot USHORT usPowerDpm3; 5462d78d3a22SFrançois Tigeot USHORT usPowerDpm4; 5463d78d3a22SFrançois Tigeot USHORT usPowerDpm5; 5464d78d3a22SFrançois Tigeot USHORT usPowerDpm6; 5465d78d3a22SFrançois Tigeot USHORT usPowerDpm7; 5466d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM0; 5467d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM1; 5468d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM2; 5469d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM3; 5470d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM4; 5471d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM5; 5472d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM6; 5473d78d3a22SFrançois Tigeot ULONG ulTdpDerateDPM7; 5474d78d3a22SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5475d78d3a22SFrançois Tigeot ULONG ulEvvDefaultVddc; 5476d78d3a22SFrançois Tigeot ULONG ulEvvNoCalcVddc; 5477d78d3a22SFrançois Tigeot USHORT usParamNegFlag; 5478d78d3a22SFrançois Tigeot USHORT usSpeed_Model; 5479d78d3a22SFrançois Tigeot ULONG ulSM_A0; 5480d78d3a22SFrançois Tigeot ULONG ulSM_A1; 5481d78d3a22SFrançois Tigeot ULONG ulSM_A2; 5482d78d3a22SFrançois Tigeot ULONG ulSM_A3; 5483d78d3a22SFrançois Tigeot ULONG ulSM_A4; 5484d78d3a22SFrançois Tigeot ULONG ulSM_A5; 5485d78d3a22SFrançois Tigeot ULONG ulSM_A6; 5486d78d3a22SFrançois Tigeot ULONG ulSM_A7; 5487d78d3a22SFrançois Tigeot UCHAR ucSM_A0_sign; 5488d78d3a22SFrançois Tigeot UCHAR ucSM_A1_sign; 5489d78d3a22SFrançois Tigeot UCHAR ucSM_A2_sign; 5490d78d3a22SFrançois Tigeot UCHAR ucSM_A3_sign; 5491d78d3a22SFrançois Tigeot UCHAR ucSM_A4_sign; 5492d78d3a22SFrançois Tigeot UCHAR ucSM_A5_sign; 5493d78d3a22SFrançois Tigeot UCHAR ucSM_A6_sign; 5494d78d3a22SFrançois Tigeot UCHAR ucSM_A7_sign; 5495d78d3a22SFrançois Tigeot ULONG ulMargin_RO_a; 5496d78d3a22SFrançois Tigeot ULONG ulMargin_RO_b; 5497d78d3a22SFrançois Tigeot ULONG ulMargin_RO_c; 5498d78d3a22SFrançois Tigeot ULONG ulMargin_fixed; 5499d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_mean; 5500d78d3a22SFrançois Tigeot ULONG ulMargin_plat_mean; 5501d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_sigma; 5502d78d3a22SFrançois Tigeot ULONG ulMargin_plat_sigma; 5503d78d3a22SFrançois Tigeot ULONG ulMargin_DC_sigma; 5504d78d3a22SFrançois Tigeot ULONG ulReserved[8]; // Reserved for future ASIC 5505d78d3a22SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_4; 5506d78d3a22SFrançois Tigeot 5507d78d3a22SFrançois Tigeot // for Polaris10/Polaris11 speed EVV algorithm 5508d78d3a22SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 5509d78d3a22SFrançois Tigeot { 5510d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5511d78d3a22SFrançois Tigeot ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv 5512d78d3a22SFrançois Tigeot ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv 5513d78d3a22SFrançois Tigeot USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address ) 5514d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD 5515d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length 5516d78d3a22SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 ) 5517d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5518d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5519d78d3a22SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1. 5520d78d3a22SFrançois Tigeot ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/> 5521d78d3a22SFrançois Tigeot ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/> 5522d78d3a22SFrançois Tigeot ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/> 5523d78d3a22SFrançois Tigeot ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/> 5524d78d3a22SFrançois Tigeot ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/> 5525d78d3a22SFrançois Tigeot ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/> 5526d78d3a22SFrançois Tigeot ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/> 5527d78d3a22SFrançois Tigeot ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/> 5528d78d3a22SFrançois Tigeot ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/> 5529d78d3a22SFrançois Tigeot ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/> 5530d78d3a22SFrançois Tigeot ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/> 5531d78d3a22SFrançois Tigeot UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/> 5532d78d3a22SFrançois Tigeot UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/> 5533d78d3a22SFrançois Tigeot UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/> 5534d78d3a22SFrançois Tigeot UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/> 5535d78d3a22SFrançois Tigeot UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/> 5536d78d3a22SFrançois Tigeot UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/> 5537d78d3a22SFrançois Tigeot UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/> 5538d78d3a22SFrançois Tigeot UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/> 5539d78d3a22SFrançois Tigeot ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1" 5540d78d3a22SFrançois Tigeot ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1" 5541d78d3a22SFrançois Tigeot ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1" 5542d78d3a22SFrançois Tigeot ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/> 5543d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/> 5544d78d3a22SFrançois Tigeot ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/> 5545d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/> 5546d78d3a22SFrançois Tigeot ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/> 5547d78d3a22SFrançois Tigeot ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/> 5548d78d3a22SFrançois Tigeot ULONG ulReserved[12]; 5549d78d3a22SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_5; 5550d78d3a22SFrançois Tigeot 5551d78d3a22SFrançois Tigeot /* for Polars10/11 AVFS parameters */ 5552d78d3a22SFrançois Tigeot typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6 5553d78d3a22SFrançois Tigeot { 5554d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5555d78d3a22SFrançois Tigeot ULONG ulMaxVddc; 5556d78d3a22SFrançois Tigeot ULONG ulMinVddc; 5557d78d3a22SFrançois Tigeot USHORT usLkgEuseIndex; 5558d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseBitLSB; 5559d78d3a22SFrançois Tigeot UCHAR ucLkgEfuseLength; 5560d78d3a22SFrançois Tigeot ULONG ulLkgEncodeLn_MaxDivMin; 5561d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMax; 5562d78d3a22SFrançois Tigeot ULONG ulLkgEncodeMin; 5563d78d3a22SFrançois Tigeot EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5564d78d3a22SFrançois Tigeot ULONG ulEvvDefaultVddc; 5565d78d3a22SFrançois Tigeot ULONG ulEvvNoCalcVddc; 5566d78d3a22SFrançois Tigeot ULONG ulSpeed_Model; 5567d78d3a22SFrançois Tigeot ULONG ulSM_A0; 5568d78d3a22SFrançois Tigeot ULONG ulSM_A1; 5569d78d3a22SFrançois Tigeot ULONG ulSM_A2; 5570d78d3a22SFrançois Tigeot ULONG ulSM_A3; 5571d78d3a22SFrançois Tigeot ULONG ulSM_A4; 5572d78d3a22SFrançois Tigeot ULONG ulSM_A5; 5573d78d3a22SFrançois Tigeot ULONG ulSM_A6; 5574d78d3a22SFrançois Tigeot ULONG ulSM_A7; 5575d78d3a22SFrançois Tigeot UCHAR ucSM_A0_sign; 5576d78d3a22SFrançois Tigeot UCHAR ucSM_A1_sign; 5577d78d3a22SFrançois Tigeot UCHAR ucSM_A2_sign; 5578d78d3a22SFrançois Tigeot UCHAR ucSM_A3_sign; 5579d78d3a22SFrançois Tigeot UCHAR ucSM_A4_sign; 5580d78d3a22SFrançois Tigeot UCHAR ucSM_A5_sign; 5581d78d3a22SFrançois Tigeot UCHAR ucSM_A6_sign; 5582d78d3a22SFrançois Tigeot UCHAR ucSM_A7_sign; 5583d78d3a22SFrançois Tigeot ULONG ulMargin_RO_a; 5584d78d3a22SFrançois Tigeot ULONG ulMargin_RO_b; 5585d78d3a22SFrançois Tigeot ULONG ulMargin_RO_c; 5586d78d3a22SFrançois Tigeot ULONG ulMargin_fixed; 5587d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_mean; 5588d78d3a22SFrançois Tigeot ULONG ulMargin_plat_mean; 5589d78d3a22SFrançois Tigeot ULONG ulMargin_Fmax_sigma; 5590d78d3a22SFrançois Tigeot ULONG ulMargin_plat_sigma; 5591d78d3a22SFrançois Tigeot ULONG ulMargin_DC_sigma; 5592d78d3a22SFrançois Tigeot ULONG ulLoadLineSlop; 5593d78d3a22SFrançois Tigeot ULONG ulaTDClimitPerDPM[8]; 5594d78d3a22SFrançois Tigeot ULONG ulaNoCalcVddcPerDPM[8]; 5595d78d3a22SFrançois Tigeot ULONG ulAVFS_meanNsigma_Acontant0; 5596d78d3a22SFrançois Tigeot ULONG ulAVFS_meanNsigma_Acontant1; 5597d78d3a22SFrançois Tigeot ULONG ulAVFS_meanNsigma_Acontant2; 5598d78d3a22SFrançois Tigeot USHORT usAVFS_meanNsigma_DC_tol_sigma; 5599d78d3a22SFrançois Tigeot USHORT usAVFS_meanNsigma_Platform_mean; 5600d78d3a22SFrançois Tigeot USHORT usAVFS_meanNsigma_Platform_sigma; 5601d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSOFF_a0; 5602d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSOFF_a1; 5603d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSOFF_a2; 5604d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSON_a0; 5605d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSON_a1; 5606d78d3a22SFrançois Tigeot ULONG ulGB_VDROOP_TABLE_CKSON_a2; 5607d78d3a22SFrançois Tigeot ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 5608d78d3a22SFrançois Tigeot USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2; 5609d78d3a22SFrançois Tigeot ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b; 5610d78d3a22SFrançois Tigeot ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1; 5611d78d3a22SFrançois Tigeot USHORT usAVFSGB_FUSE_TABLE_CKSON_m2; 5612d78d3a22SFrançois Tigeot ULONG ulAVFSGB_FUSE_TABLE_CKSON_b; 5613d78d3a22SFrançois Tigeot USHORT usMaxVoltage_0_25mv; 5614d78d3a22SFrançois Tigeot UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF; 5615d78d3a22SFrançois Tigeot UCHAR ucEnableGB_VDROOP_TABLE_CKSON; 5616d78d3a22SFrançois Tigeot UCHAR ucEnableGB_FUSE_TABLE_CKSOFF; 5617d78d3a22SFrançois Tigeot UCHAR ucEnableGB_FUSE_TABLE_CKSON; 5618d78d3a22SFrançois Tigeot USHORT usPSM_Age_ComFactor; 5619d78d3a22SFrançois Tigeot UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage; 5620d78d3a22SFrançois Tigeot UCHAR ucReserved; 5621d78d3a22SFrançois Tigeot }ATOM_ASIC_PROFILING_INFO_V3_6; 5622d78d3a22SFrançois Tigeot 5623d78d3a22SFrançois Tigeot 5624d78d3a22SFrançois Tigeot typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ 5625d78d3a22SFrançois Tigeot ULONG ulMaxSclkFreq; 5626d78d3a22SFrançois Tigeot UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz 5627d78d3a22SFrançois Tigeot UCHAR ucPostdiv; // divide by 2^n 5628d78d3a22SFrançois Tigeot USHORT ucFcw_pcc; 5629d78d3a22SFrançois Tigeot USHORT ucFcw_trans_upper; 5630d78d3a22SFrançois Tigeot USHORT ucRcw_trans_lower; 5631d78d3a22SFrançois Tigeot }ATOM_SCLK_FCW_RANGE_ENTRY_V1; 5632d78d3a22SFrançois Tigeot 5633d78d3a22SFrançois Tigeot 5634d78d3a22SFrançois Tigeot // SMU_InfoTable for Polaris10/Polaris11 5635d78d3a22SFrançois Tigeot typedef struct _ATOM_SMU_INFO_V2_1 5636d78d3a22SFrançois Tigeot { 5637d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5638d78d3a22SFrançois Tigeot UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1 5639d78d3a22SFrançois Tigeot UCHAR ucReserved[3]; 5640d78d3a22SFrançois Tigeot ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8]; 5641d78d3a22SFrançois Tigeot }ATOM_SMU_INFO_V2_1; 5642d78d3a22SFrançois Tigeot 5643d78d3a22SFrançois Tigeot 5644d78d3a22SFrançois Tigeot // GFX_InfoTable for Polaris10/Polaris11 5645d78d3a22SFrançois Tigeot typedef struct _ATOM_GFX_INFO_V2_1 5646d78d3a22SFrançois Tigeot { 5647d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5648d78d3a22SFrançois Tigeot UCHAR GfxIpMinVer; 5649d78d3a22SFrançois Tigeot UCHAR GfxIpMajVer; 5650d78d3a22SFrançois Tigeot UCHAR max_shader_engines; 5651d78d3a22SFrançois Tigeot UCHAR max_tile_pipes; 5652d78d3a22SFrançois Tigeot UCHAR max_cu_per_sh; 5653d78d3a22SFrançois Tigeot UCHAR max_sh_per_se; 5654d78d3a22SFrançois Tigeot UCHAR max_backends_per_se; 5655d78d3a22SFrançois Tigeot UCHAR max_texture_channel_caches; 5656d78d3a22SFrançois Tigeot }ATOM_GFX_INFO_V2_1; 5657d78d3a22SFrançois Tigeot 5658d78d3a22SFrançois Tigeot 5659c59a5c48SFrançois Tigeot typedef struct _ATOM_POWER_SOURCE_OBJECT 5660c59a5c48SFrançois Tigeot { 5661c59a5c48SFrançois Tigeot UCHAR ucPwrSrcId; // Power source 5662c59a5c48SFrançois Tigeot UCHAR ucPwrSensorType; // GPIO, I2C or none 5663c59a5c48SFrançois Tigeot UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 5664c59a5c48SFrançois Tigeot UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 5665c59a5c48SFrançois Tigeot UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5666c59a5c48SFrançois Tigeot UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5667c59a5c48SFrançois Tigeot UCHAR ucPwrSensActiveState; // high active or low active 5668c59a5c48SFrançois Tigeot UCHAR ucReserve[3]; // reserve 5669c59a5c48SFrançois Tigeot USHORT usSensPwr; // in unit of watt 5670c59a5c48SFrançois Tigeot }ATOM_POWER_SOURCE_OBJECT; 5671c59a5c48SFrançois Tigeot 5672c59a5c48SFrançois Tigeot typedef struct _ATOM_POWER_SOURCE_INFO 5673c59a5c48SFrançois Tigeot { 5674c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 5675c59a5c48SFrançois Tigeot UCHAR asPwrbehave[16]; 5676c59a5c48SFrançois Tigeot ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5677c59a5c48SFrançois Tigeot }ATOM_POWER_SOURCE_INFO; 5678c59a5c48SFrançois Tigeot 5679c59a5c48SFrançois Tigeot 5680c59a5c48SFrançois Tigeot //Define ucPwrSrcId 5681c59a5c48SFrançois Tigeot #define POWERSOURCE_PCIE_ID1 0x00 5682c59a5c48SFrançois Tigeot #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5683c59a5c48SFrançois Tigeot #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5684c59a5c48SFrançois Tigeot #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5685c59a5c48SFrançois Tigeot #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5686c59a5c48SFrançois Tigeot 5687c59a5c48SFrançois Tigeot //define ucPwrSensorId 5688c59a5c48SFrançois Tigeot #define POWER_SENSOR_ALWAYS 0x00 5689c59a5c48SFrançois Tigeot #define POWER_SENSOR_GPIO 0x01 5690c59a5c48SFrançois Tigeot #define POWER_SENSOR_I2C 0x02 5691c59a5c48SFrançois Tigeot 5692c59a5c48SFrançois Tigeot typedef struct _ATOM_CLK_VOLT_CAPABILITY 5693c59a5c48SFrançois Tigeot { 5694c59a5c48SFrançois Tigeot ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5695c59a5c48SFrançois Tigeot ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5696c59a5c48SFrançois Tigeot }ATOM_CLK_VOLT_CAPABILITY; 5697c59a5c48SFrançois Tigeot 5698c59a5c48SFrançois Tigeot 5699c59a5c48SFrançois Tigeot typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5700c59a5c48SFrançois Tigeot { 5701c59a5c48SFrançois Tigeot USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5702c59a5c48SFrançois Tigeot ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5703c59a5c48SFrançois Tigeot }ATOM_CLK_VOLT_CAPABILITY_V2; 5704c59a5c48SFrançois Tigeot 5705c59a5c48SFrançois Tigeot typedef struct _ATOM_AVAILABLE_SCLK_LIST 5706c59a5c48SFrançois Tigeot { 5707c59a5c48SFrançois Tigeot ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5708c59a5c48SFrançois Tigeot USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5709c59a5c48SFrançois Tigeot USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5710c59a5c48SFrançois Tigeot }ATOM_AVAILABLE_SCLK_LIST; 5711c59a5c48SFrançois Tigeot 5712c59a5c48SFrançois Tigeot // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5713c59a5c48SFrançois Tigeot #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5714c59a5c48SFrançois Tigeot 5715c59a5c48SFrançois Tigeot // this IntegrateSystemInfoTable is used for Liano/Ontario APU 5716c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5717c59a5c48SFrançois Tigeot { 5718c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5719c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; 5720c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; 5721c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; 5722c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5723c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 5724c59a5c48SFrançois Tigeot ULONG ulOtherDisplayMisc; 5725c59a5c48SFrançois Tigeot ULONG ulGPUCapInfo; 5726c59a5c48SFrançois Tigeot ULONG ulSB_MMIO_Base_Addr; 5727c59a5c48SFrançois Tigeot USHORT usRequestedPWMFreqInHz; 5728c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; 5729c59a5c48SFrançois Tigeot UCHAR ucHtcHystLmt; 5730c59a5c48SFrançois Tigeot ULONG ulMinEngineClock; 5731c59a5c48SFrançois Tigeot ULONG ulSystemConfig; 5732c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 5733c59a5c48SFrançois Tigeot USHORT usNBP0Voltage; 5734c59a5c48SFrançois Tigeot USHORT usNBP1Voltage; 5735c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 5736c59a5c48SFrançois Tigeot USHORT usExtDispConnInfoOffset; 5737c59a5c48SFrançois Tigeot USHORT usPanelRefreshRateRange; 5738c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 5739c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 5740c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5741c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5742c59a5c48SFrançois Tigeot ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5743c59a5c48SFrançois Tigeot ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5744c59a5c48SFrançois Tigeot ULONG ulGMCRestoreResetTime; 5745c59a5c48SFrançois Tigeot ULONG ulMinimumNClk; 5746c59a5c48SFrançois Tigeot ULONG ulIdleNClk; 5747c59a5c48SFrançois Tigeot ULONG ulDDR_DLL_PowerUpTime; 5748c59a5c48SFrançois Tigeot ULONG ulDDR_PLL_PowerUpTime; 5749c59a5c48SFrançois Tigeot USHORT usPCIEClkSSPercentage; 5750c59a5c48SFrançois Tigeot USHORT usPCIEClkSSType; 5751c59a5c48SFrançois Tigeot USHORT usLvdsSSPercentage; 5752c59a5c48SFrançois Tigeot USHORT usLvdsSSpreadRateIn10Hz; 5753c59a5c48SFrançois Tigeot USHORT usHDMISSPercentage; 5754c59a5c48SFrançois Tigeot USHORT usHDMISSpreadRateIn10Hz; 5755c59a5c48SFrançois Tigeot USHORT usDVISSPercentage; 5756c59a5c48SFrançois Tigeot USHORT usDVISSpreadRateIn10Hz; 5757c59a5c48SFrançois Tigeot ULONG SclkDpmBoostMargin; 5758c59a5c48SFrançois Tigeot ULONG SclkDpmThrottleMargin; 5759c59a5c48SFrançois Tigeot USHORT SclkDpmTdpLimitPG; 5760c59a5c48SFrançois Tigeot USHORT SclkDpmTdpLimitBoost; 5761c59a5c48SFrançois Tigeot ULONG ulBoostEngineCLock; 5762c59a5c48SFrançois Tigeot UCHAR ulBoostVid_2bit; 5763c59a5c48SFrançois Tigeot UCHAR EnableBoost; 5764c59a5c48SFrançois Tigeot USHORT GnbTdpLimit; 5765c59a5c48SFrançois Tigeot USHORT usMaxLVDSPclkFreqInSingleLink; 5766c59a5c48SFrançois Tigeot UCHAR ucLvdsMisc; 5767c59a5c48SFrançois Tigeot UCHAR ucLVDSReserved; 5768c59a5c48SFrançois Tigeot ULONG ulReserved3[15]; 5769c59a5c48SFrançois Tigeot ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5770c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V6; 5771c59a5c48SFrançois Tigeot 5772c59a5c48SFrançois Tigeot // ulGPUCapInfo 5773c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5774c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5775c59a5c48SFrançois Tigeot 5776c59a5c48SFrançois Tigeot //ucLVDSMisc: 5777c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5778c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5779c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__888_BPC 0x04 5780c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5781c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5782c59a5c48SFrançois Tigeot // new since Trinity 5783c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5784c59a5c48SFrançois Tigeot 5785c59a5c48SFrançois Tigeot // not used any more 5786c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5787c59a5c48SFrançois Tigeot #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5788c59a5c48SFrançois Tigeot 5789c59a5c48SFrançois Tigeot /********************************************************************************************************************** 5790c59a5c48SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5791c59a5c48SFrançois Tigeot ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5792c59a5c48SFrançois Tigeot ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5793c59a5c48SFrançois Tigeot ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5794c59a5c48SFrançois Tigeot sDISPCLK_Voltage: Report Display clock voltage requirement. 5795c59a5c48SFrançois Tigeot 5796c59a5c48SFrançois Tigeot ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5797c59a5c48SFrançois Tigeot ATOM_DEVICE_CRT1_SUPPORT 0x0001 5798c59a5c48SFrançois Tigeot ATOM_DEVICE_CRT2_SUPPORT 0x0010 5799c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP1_SUPPORT 0x0008 5800c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP6_SUPPORT 0x0040 5801c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP2_SUPPORT 0x0080 5802c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP3_SUPPORT 0x0200 5803c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP4_SUPPORT 0x0400 5804c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP5_SUPPORT 0x0800 5805c59a5c48SFrançois Tigeot ATOM_DEVICE_LCD1_SUPPORT 0x0002 5806c59a5c48SFrançois Tigeot ulOtherDisplayMisc: Other display related flags, not defined yet. 5807c59a5c48SFrançois Tigeot ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5808c59a5c48SFrançois Tigeot =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5809c59a5c48SFrançois Tigeot bit[3]=0: Enable HW AUX mode detection logic 5810c59a5c48SFrançois Tigeot =1: Disable HW AUX mode dettion logic 5811c59a5c48SFrançois Tigeot ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5812c59a5c48SFrançois Tigeot 5813c59a5c48SFrançois Tigeot usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5814c59a5c48SFrançois Tigeot Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5815c59a5c48SFrançois Tigeot 5816c59a5c48SFrançois Tigeot When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5817c59a5c48SFrançois Tigeot 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5818c59a5c48SFrançois Tigeot VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5819c59a5c48SFrançois Tigeot Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5820c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 5821c59a5c48SFrançois Tigeot 5822c59a5c48SFrançois Tigeot 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5823c59a5c48SFrançois Tigeot that BL control from GPU is expected. 5824c59a5c48SFrançois Tigeot VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5825c59a5c48SFrançois Tigeot Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5826c59a5c48SFrançois Tigeot it's per platform 5827c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 5828c59a5c48SFrançois Tigeot 5829c59a5c48SFrançois Tigeot ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5830c59a5c48SFrançois Tigeot Threshold on value to enter HTC_active state. 5831c59a5c48SFrançois Tigeot ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5832c59a5c48SFrançois Tigeot To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5833c59a5c48SFrançois Tigeot ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5834c59a5c48SFrançois Tigeot ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5835c59a5c48SFrançois Tigeot =1: PCIE Power Gating Enabled 5836c59a5c48SFrançois Tigeot Bit[1]=0: DDR-DLL shut-down feature disabled. 5837c59a5c48SFrançois Tigeot 1: DDR-DLL shut-down feature enabled. 5838c59a5c48SFrançois Tigeot Bit[2]=0: DDR-PLL Power down feature disabled. 5839c59a5c48SFrançois Tigeot 1: DDR-PLL Power down feature enabled. 5840c59a5c48SFrançois Tigeot ulCPUCapInfo: TBD 5841c59a5c48SFrançois Tigeot usNBP0Voltage: VID for voltage on NB P0 State 5842c59a5c48SFrançois Tigeot usNBP1Voltage: VID for voltage on NB P1 State 5843c59a5c48SFrançois Tigeot usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5844c59a5c48SFrançois Tigeot usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5845c59a5c48SFrançois Tigeot usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5846c59a5c48SFrançois Tigeot to indicate a range. 5847c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5848c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5849c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5850c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5851c59a5c48SFrançois Tigeot ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5852c59a5c48SFrançois Tigeot ucUMAChannelNumber: System memory channel numbers. 5853c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5854c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5855c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5856c59a5c48SFrançois Tigeot sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5857c59a5c48SFrançois Tigeot ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5858c59a5c48SFrançois Tigeot ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5859c59a5c48SFrançois Tigeot ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5860c59a5c48SFrançois Tigeot ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5861c59a5c48SFrançois Tigeot ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5862c59a5c48SFrançois Tigeot usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5863c59a5c48SFrançois Tigeot usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5864c59a5c48SFrançois Tigeot usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5865c59a5c48SFrançois Tigeot usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5866c59a5c48SFrançois Tigeot usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5867c59a5c48SFrançois Tigeot usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5868c59a5c48SFrançois Tigeot usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5869c59a5c48SFrançois Tigeot usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5870c59a5c48SFrançois Tigeot usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5871c59a5c48SFrançois Tigeot ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5872c59a5c48SFrançois Tigeot [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5873c59a5c48SFrançois Tigeot [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5874c59a5c48SFrançois Tigeot [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5875c59a5c48SFrançois Tigeot [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5876c59a5c48SFrançois Tigeot **********************************************************************************************************************/ 5877c59a5c48SFrançois Tigeot 5878c59a5c48SFrançois Tigeot // this Table is used for Liano/Ontario APU 5879c59a5c48SFrançois Tigeot typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5880c59a5c48SFrançois Tigeot { 5881c59a5c48SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5882c59a5c48SFrançois Tigeot ULONG ulPowerplayTable[128]; 5883c59a5c48SFrançois Tigeot }ATOM_FUSION_SYSTEM_INFO_V1; 5884c59a5c48SFrançois Tigeot 5885c59a5c48SFrançois Tigeot 5886c59a5c48SFrançois Tigeot typedef struct _ATOM_TDP_CONFIG_BITS 5887c59a5c48SFrançois Tigeot { 5888c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 5889c59a5c48SFrançois Tigeot ULONG uReserved:2; 5890c59a5c48SFrançois Tigeot ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5891c59a5c48SFrançois Tigeot ULONG uCTDP_Value:14; // Override value in tens of milli watts 5892c59a5c48SFrançois Tigeot ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5893c59a5c48SFrançois Tigeot #else 5894c59a5c48SFrançois Tigeot ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5895c59a5c48SFrançois Tigeot ULONG uCTDP_Value:14; // Override value in tens of milli watts 5896c59a5c48SFrançois Tigeot ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5897c59a5c48SFrançois Tigeot ULONG uReserved:2; 5898c59a5c48SFrançois Tigeot #endif 5899c59a5c48SFrançois Tigeot }ATOM_TDP_CONFIG_BITS; 5900c59a5c48SFrançois Tigeot 5901c59a5c48SFrançois Tigeot typedef union _ATOM_TDP_CONFIG 5902c59a5c48SFrançois Tigeot { 5903c59a5c48SFrançois Tigeot ATOM_TDP_CONFIG_BITS TDP_config; 5904c59a5c48SFrançois Tigeot ULONG TDP_config_all; 5905c59a5c48SFrançois Tigeot }ATOM_TDP_CONFIG; 5906c59a5c48SFrançois Tigeot 5907c59a5c48SFrançois Tigeot /********************************************************************************************************************** 5908c59a5c48SFrançois Tigeot ATOM_FUSION_SYSTEM_INFO_V1 Description 5909c59a5c48SFrançois Tigeot sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5910c59a5c48SFrançois Tigeot ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5911c59a5c48SFrançois Tigeot **********************************************************************************************************************/ 5912c59a5c48SFrançois Tigeot 5913c59a5c48SFrançois Tigeot // this IntegrateSystemInfoTable is used for Trinity APU 5914c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5915c59a5c48SFrançois Tigeot { 5916c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 5917c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; 5918c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; 5919c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; 5920c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5921c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 5922c59a5c48SFrançois Tigeot ULONG ulOtherDisplayMisc; 5923c59a5c48SFrançois Tigeot ULONG ulGPUCapInfo; 5924c59a5c48SFrançois Tigeot ULONG ulSB_MMIO_Base_Addr; 5925c59a5c48SFrançois Tigeot USHORT usRequestedPWMFreqInHz; 5926c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; 5927c59a5c48SFrançois Tigeot UCHAR ucHtcHystLmt; 5928c59a5c48SFrançois Tigeot ULONG ulMinEngineClock; 5929c59a5c48SFrançois Tigeot ULONG ulSystemConfig; 5930c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 5931c59a5c48SFrançois Tigeot USHORT usNBP0Voltage; 5932c59a5c48SFrançois Tigeot USHORT usNBP1Voltage; 5933c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 5934c59a5c48SFrançois Tigeot USHORT usExtDispConnInfoOffset; 5935c59a5c48SFrançois Tigeot USHORT usPanelRefreshRateRange; 5936c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 5937c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 5938c59a5c48SFrançois Tigeot UCHAR strVBIOSMsg[40]; 5939c59a5c48SFrançois Tigeot ATOM_TDP_CONFIG asTdpConfig; 5940c59a5c48SFrançois Tigeot ULONG ulReserved[19]; 5941c59a5c48SFrançois Tigeot ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5942c59a5c48SFrançois Tigeot ULONG ulGMCRestoreResetTime; 5943c59a5c48SFrançois Tigeot ULONG ulMinimumNClk; 5944c59a5c48SFrançois Tigeot ULONG ulIdleNClk; 5945c59a5c48SFrançois Tigeot ULONG ulDDR_DLL_PowerUpTime; 5946c59a5c48SFrançois Tigeot ULONG ulDDR_PLL_PowerUpTime; 5947c59a5c48SFrançois Tigeot USHORT usPCIEClkSSPercentage; 5948c59a5c48SFrançois Tigeot USHORT usPCIEClkSSType; 5949c59a5c48SFrançois Tigeot USHORT usLvdsSSPercentage; 5950c59a5c48SFrançois Tigeot USHORT usLvdsSSpreadRateIn10Hz; 5951c59a5c48SFrançois Tigeot USHORT usHDMISSPercentage; 5952c59a5c48SFrançois Tigeot USHORT usHDMISSpreadRateIn10Hz; 5953c59a5c48SFrançois Tigeot USHORT usDVISSPercentage; 5954c59a5c48SFrançois Tigeot USHORT usDVISSpreadRateIn10Hz; 5955c59a5c48SFrançois Tigeot ULONG SclkDpmBoostMargin; 5956c59a5c48SFrançois Tigeot ULONG SclkDpmThrottleMargin; 5957c59a5c48SFrançois Tigeot USHORT SclkDpmTdpLimitPG; 5958c59a5c48SFrançois Tigeot USHORT SclkDpmTdpLimitBoost; 5959c59a5c48SFrançois Tigeot ULONG ulBoostEngineCLock; 5960c59a5c48SFrançois Tigeot UCHAR ulBoostVid_2bit; 5961c59a5c48SFrançois Tigeot UCHAR EnableBoost; 5962c59a5c48SFrançois Tigeot USHORT GnbTdpLimit; 5963c59a5c48SFrançois Tigeot USHORT usMaxLVDSPclkFreqInSingleLink; 5964c59a5c48SFrançois Tigeot UCHAR ucLvdsMisc; 5965c59a5c48SFrançois Tigeot UCHAR ucTravisLVDSVolAdjust; 5966c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5967c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5968c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5969c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5970c59a5c48SFrançois Tigeot UCHAR ucLVDSOffToOnDelay_in4Ms; 5971c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5972c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5973c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 5974c59a5c48SFrançois Tigeot ULONG ulLCDBitDepthControlVal; 5975c59a5c48SFrançois Tigeot ULONG ulNbpStateMemclkFreq[4]; 5976c59a5c48SFrançois Tigeot USHORT usNBP2Voltage; 5977c59a5c48SFrançois Tigeot USHORT usNBP3Voltage; 5978c59a5c48SFrançois Tigeot ULONG ulNbpStateNClkFreq[4]; 5979c59a5c48SFrançois Tigeot UCHAR ucNBDPMEnable; 5980c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 5981c59a5c48SFrançois Tigeot UCHAR ucDPMState0VclkFid; 5982c59a5c48SFrançois Tigeot UCHAR ucDPMState0DclkFid; 5983c59a5c48SFrançois Tigeot UCHAR ucDPMState1VclkFid; 5984c59a5c48SFrançois Tigeot UCHAR ucDPMState1DclkFid; 5985c59a5c48SFrançois Tigeot UCHAR ucDPMState2VclkFid; 5986c59a5c48SFrançois Tigeot UCHAR ucDPMState2DclkFid; 5987c59a5c48SFrançois Tigeot UCHAR ucDPMState3VclkFid; 5988c59a5c48SFrançois Tigeot UCHAR ucDPMState3DclkFid; 5989c59a5c48SFrançois Tigeot ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5990c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5991c59a5c48SFrançois Tigeot 5992c59a5c48SFrançois Tigeot // ulOtherDisplayMisc 5993c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5994c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5995c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5996c59a5c48SFrançois Tigeot #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5997c59a5c48SFrançois Tigeot 5998c59a5c48SFrançois Tigeot // ulGPUCapInfo 5999c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 6000c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 6001c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 6002c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 6003c59a5c48SFrançois Tigeot //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6004c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 6005c59a5c48SFrançois Tigeot 6006c59a5c48SFrançois Tigeot //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 6007c59a5c48SFrançois Tigeot #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 6008c59a5c48SFrançois Tigeot 6009c59a5c48SFrançois Tigeot /********************************************************************************************************************** 6010c59a5c48SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 6011c59a5c48SFrançois Tigeot ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6012c59a5c48SFrançois Tigeot ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6013c59a5c48SFrançois Tigeot ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6014c59a5c48SFrançois Tigeot sDISPCLK_Voltage: Report Display clock voltage requirement. 6015c59a5c48SFrançois Tigeot 6016c59a5c48SFrançois Tigeot ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6017c59a5c48SFrançois Tigeot ATOM_DEVICE_CRT1_SUPPORT 0x0001 6018c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP1_SUPPORT 0x0008 6019c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP6_SUPPORT 0x0040 6020c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP2_SUPPORT 0x0080 6021c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP3_SUPPORT 0x0200 6022c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP4_SUPPORT 0x0400 6023c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP5_SUPPORT 0x0800 6024c59a5c48SFrançois Tigeot ATOM_DEVICE_LCD1_SUPPORT 0x0002 6025c59a5c48SFrançois Tigeot ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6026c59a5c48SFrançois Tigeot =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6027c59a5c48SFrançois Tigeot bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6028c59a5c48SFrançois Tigeot =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6029c59a5c48SFrançois Tigeot bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6030c59a5c48SFrançois Tigeot =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6031c59a5c48SFrançois Tigeot bit[3]=0: VBIOS fast boot is disable 6032c59a5c48SFrançois Tigeot =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6033c59a5c48SFrançois Tigeot ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 6034c59a5c48SFrançois Tigeot =1: TMDS/HDMI Coherent Mode use signel PLL mode. 6035c59a5c48SFrançois Tigeot bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 6036c59a5c48SFrançois Tigeot =1: DP mode use single PLL mode 6037c59a5c48SFrançois Tigeot bit[3]=0: Enable AUX HW mode detection logic 6038c59a5c48SFrançois Tigeot =1: Disable AUX HW mode detection logic 6039c59a5c48SFrançois Tigeot 6040c59a5c48SFrançois Tigeot ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 6041c59a5c48SFrançois Tigeot 6042c59a5c48SFrançois Tigeot usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6043c59a5c48SFrançois Tigeot Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6044c59a5c48SFrançois Tigeot 6045c59a5c48SFrançois Tigeot When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6046c59a5c48SFrançois Tigeot 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6047c59a5c48SFrançois Tigeot VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6048c59a5c48SFrançois Tigeot Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6049c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 6050c59a5c48SFrançois Tigeot 6051c59a5c48SFrançois Tigeot 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6052c59a5c48SFrançois Tigeot that BL control from GPU is expected. 6053c59a5c48SFrançois Tigeot VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6054c59a5c48SFrançois Tigeot Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6055c59a5c48SFrançois Tigeot it's per platform 6056c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 6057c59a5c48SFrançois Tigeot 6058c59a5c48SFrançois Tigeot ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 6059c59a5c48SFrançois Tigeot Threshold on value to enter HTC_active state. 6060c59a5c48SFrançois Tigeot ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6061c59a5c48SFrançois Tigeot To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6062c59a5c48SFrançois Tigeot ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 6063c59a5c48SFrançois Tigeot ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6064c59a5c48SFrançois Tigeot =1: PCIE Power Gating Enabled 6065c59a5c48SFrançois Tigeot Bit[1]=0: DDR-DLL shut-down feature disabled. 6066c59a5c48SFrançois Tigeot 1: DDR-DLL shut-down feature enabled. 6067c59a5c48SFrançois Tigeot Bit[2]=0: DDR-PLL Power down feature disabled. 6068c59a5c48SFrançois Tigeot 1: DDR-PLL Power down feature enabled. 6069c59a5c48SFrançois Tigeot ulCPUCapInfo: TBD 6070c59a5c48SFrançois Tigeot usNBP0Voltage: VID for voltage on NB P0 State 6071c59a5c48SFrançois Tigeot usNBP1Voltage: VID for voltage on NB P1 State 6072c59a5c48SFrançois Tigeot usNBP2Voltage: VID for voltage on NB P2 State 6073c59a5c48SFrançois Tigeot usNBP3Voltage: VID for voltage on NB P3 State 6074c59a5c48SFrançois Tigeot usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 6075c59a5c48SFrançois Tigeot usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6076c59a5c48SFrançois Tigeot usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6077c59a5c48SFrançois Tigeot to indicate a range. 6078c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6079c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6080c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6081c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6082c59a5c48SFrançois Tigeot ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 6083c59a5c48SFrançois Tigeot ucUMAChannelNumber: System memory channel numbers. 6084c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 6085c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 6086c59a5c48SFrançois Tigeot ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 6087c59a5c48SFrançois Tigeot sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6088c59a5c48SFrançois Tigeot ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6089c59a5c48SFrançois Tigeot ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 6090c59a5c48SFrançois Tigeot ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 6091c59a5c48SFrançois Tigeot ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6092c59a5c48SFrançois Tigeot ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6093c59a5c48SFrançois Tigeot usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6094c59a5c48SFrançois Tigeot usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6095c59a5c48SFrançois Tigeot usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6096c59a5c48SFrançois Tigeot usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6097c59a5c48SFrançois Tigeot usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6098c59a5c48SFrançois Tigeot usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6099c59a5c48SFrançois Tigeot usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6100c59a5c48SFrançois Tigeot usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6101c59a5c48SFrançois Tigeot usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6102c59a5c48SFrançois Tigeot ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6103c59a5c48SFrançois Tigeot [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6104c59a5c48SFrançois Tigeot [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6105c59a5c48SFrançois Tigeot [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6106c59a5c48SFrançois Tigeot [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6107c59a5c48SFrançois Tigeot [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6108c59a5c48SFrançois Tigeot ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6109c59a5c48SFrançois Tigeot value to program Travis register LVDS_CTRL_4 6110c59a5c48SFrançois Tigeot ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6111c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6112c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6113c59a5c48SFrançois Tigeot ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6114c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6115c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6116c59a5c48SFrançois Tigeot 6117c59a5c48SFrançois Tigeot ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6118c59a5c48SFrançois Tigeot =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6119c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6120c59a5c48SFrançois Tigeot 6121c59a5c48SFrançois Tigeot ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6122c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6123c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6124c59a5c48SFrançois Tigeot 6125c59a5c48SFrançois Tigeot ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6126c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 125 ( 500ms ). 6127c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6128c59a5c48SFrançois Tigeot 6129c59a5c48SFrançois Tigeot ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6130c59a5c48SFrançois Tigeot LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6131c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 0 ( 0ms ). 6132c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6133c59a5c48SFrançois Tigeot 6134c59a5c48SFrançois Tigeot ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6135c59a5c48SFrançois Tigeot LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6136c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 0 ( 0ms ). 6137c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6138c59a5c48SFrançois Tigeot 6139c59a5c48SFrançois Tigeot ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6140c59a5c48SFrançois Tigeot 6141c59a5c48SFrançois Tigeot ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 6142c59a5c48SFrançois Tigeot 6143c59a5c48SFrançois Tigeot **********************************************************************************************************************/ 6144c59a5c48SFrançois Tigeot 6145c59a5c48SFrançois Tigeot // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 6146c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 6147c59a5c48SFrançois Tigeot { 6148c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6149c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; 6150c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; 6151c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; 6152c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 6153c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 6154c59a5c48SFrançois Tigeot ULONG ulVBIOSMisc; 6155c59a5c48SFrançois Tigeot ULONG ulGPUCapInfo; 6156c59a5c48SFrançois Tigeot ULONG ulDISP_CLK2Freq; 6157c59a5c48SFrançois Tigeot USHORT usRequestedPWMFreqInHz; 6158c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; 6159c59a5c48SFrançois Tigeot UCHAR ucHtcHystLmt; 6160c59a5c48SFrançois Tigeot ULONG ulReserved2; 6161c59a5c48SFrançois Tigeot ULONG ulSystemConfig; 6162c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 6163c59a5c48SFrançois Tigeot ULONG ulReserved3; 6164c59a5c48SFrançois Tigeot USHORT usGPUReservedSysMemSize; 6165c59a5c48SFrançois Tigeot USHORT usExtDispConnInfoOffset; 6166c59a5c48SFrançois Tigeot USHORT usPanelRefreshRateRange; 6167c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 6168c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 6169c59a5c48SFrançois Tigeot UCHAR strVBIOSMsg[40]; 6170c59a5c48SFrançois Tigeot ATOM_TDP_CONFIG asTdpConfig; 6171c59a5c48SFrançois Tigeot ULONG ulReserved[19]; 6172c59a5c48SFrançois Tigeot ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 6173c59a5c48SFrançois Tigeot ULONG ulGMCRestoreResetTime; 6174c59a5c48SFrançois Tigeot ULONG ulReserved4; 6175c59a5c48SFrançois Tigeot ULONG ulIdleNClk; 6176c59a5c48SFrançois Tigeot ULONG ulDDR_DLL_PowerUpTime; 6177c59a5c48SFrançois Tigeot ULONG ulDDR_PLL_PowerUpTime; 6178c59a5c48SFrançois Tigeot USHORT usPCIEClkSSPercentage; 6179c59a5c48SFrançois Tigeot USHORT usPCIEClkSSType; 6180c59a5c48SFrançois Tigeot USHORT usLvdsSSPercentage; 6181c59a5c48SFrançois Tigeot USHORT usLvdsSSpreadRateIn10Hz; 6182c59a5c48SFrançois Tigeot USHORT usHDMISSPercentage; 6183c59a5c48SFrançois Tigeot USHORT usHDMISSpreadRateIn10Hz; 6184c59a5c48SFrançois Tigeot USHORT usDVISSPercentage; 6185c59a5c48SFrançois Tigeot USHORT usDVISSpreadRateIn10Hz; 6186c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrLo; 6187c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrHi; 6188c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 6189c59a5c48SFrançois Tigeot ULONG ulReserved5; 6190c59a5c48SFrançois Tigeot USHORT usMaxLVDSPclkFreqInSingleLink; 6191c59a5c48SFrançois Tigeot UCHAR ucLvdsMisc; 6192c59a5c48SFrançois Tigeot UCHAR ucTravisLVDSVolAdjust; 6193c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6194c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6195c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6196c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6197c59a5c48SFrançois Tigeot UCHAR ucLVDSOffToOnDelay_in4Ms; 6198c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6199c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6200c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 6201c59a5c48SFrançois Tigeot ULONG ulLCDBitDepthControlVal; 6202c59a5c48SFrançois Tigeot ULONG ulNbpStateMemclkFreq[4]; 6203c59a5c48SFrançois Tigeot ULONG ulPSPVersion; 6204c59a5c48SFrançois Tigeot ULONG ulNbpStateNClkFreq[4]; 6205c59a5c48SFrançois Tigeot USHORT usNBPStateVoltage[4]; 6206c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 6207c59a5c48SFrançois Tigeot USHORT usReserved2; 6208c59a5c48SFrançois Tigeot ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6209c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 6210c59a5c48SFrançois Tigeot 6211c59a5c48SFrançois Tigeot /********************************************************************************************************************** 6212c59a5c48SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 6213c59a5c48SFrançois Tigeot ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6214c59a5c48SFrançois Tigeot ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6215c59a5c48SFrançois Tigeot ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6216c59a5c48SFrançois Tigeot sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 6217c59a5c48SFrançois Tigeot 6218c59a5c48SFrançois Tigeot ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6219c59a5c48SFrançois Tigeot ATOM_DEVICE_CRT1_SUPPORT 0x0001 6220c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP1_SUPPORT 0x0008 6221c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP6_SUPPORT 0x0040 6222c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP2_SUPPORT 0x0080 6223c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP3_SUPPORT 0x0200 6224c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP4_SUPPORT 0x0400 6225c59a5c48SFrançois Tigeot ATOM_DEVICE_DFP5_SUPPORT 0x0800 6226c59a5c48SFrançois Tigeot ATOM_DEVICE_LCD1_SUPPORT 0x0002 6227c59a5c48SFrançois Tigeot 6228c59a5c48SFrançois Tigeot ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 6229c59a5c48SFrançois Tigeot bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6230c59a5c48SFrançois Tigeot =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6231c59a5c48SFrançois Tigeot bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6232c59a5c48SFrançois Tigeot =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6233c59a5c48SFrançois Tigeot bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6234c59a5c48SFrançois Tigeot =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6235c59a5c48SFrançois Tigeot bit[3]=0: VBIOS fast boot is disable 6236c59a5c48SFrançois Tigeot =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6237c59a5c48SFrançois Tigeot 6238c59a5c48SFrançois Tigeot ulGPUCapInfo: bit[0~2]= Reserved 6239c59a5c48SFrançois Tigeot bit[3]=0: Enable AUX HW mode detection logic 6240c59a5c48SFrançois Tigeot =1: Disable AUX HW mode detection logic 6241c59a5c48SFrançois Tigeot bit[4]=0: Disable DFS bypass feature 6242c59a5c48SFrançois Tigeot =1: Enable DFS bypass feature 6243c59a5c48SFrançois Tigeot 6244c59a5c48SFrançois Tigeot usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6245c59a5c48SFrançois Tigeot Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6246c59a5c48SFrançois Tigeot 6247c59a5c48SFrançois Tigeot When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6248c59a5c48SFrançois Tigeot 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6249c59a5c48SFrançois Tigeot VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6250c59a5c48SFrançois Tigeot Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6251c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 6252c59a5c48SFrançois Tigeot 6253c59a5c48SFrançois Tigeot 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6254c59a5c48SFrançois Tigeot that BL control from GPU is expected. 6255c59a5c48SFrançois Tigeot VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6256c59a5c48SFrançois Tigeot Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6257c59a5c48SFrançois Tigeot it's per platform 6258c59a5c48SFrançois Tigeot and enabling VariBri under the driver environment from PP table is optional. 6259c59a5c48SFrançois Tigeot 6260c59a5c48SFrançois Tigeot ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 6261c59a5c48SFrançois Tigeot ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6262c59a5c48SFrançois Tigeot To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6263c59a5c48SFrançois Tigeot 6264c59a5c48SFrançois Tigeot ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6265c59a5c48SFrançois Tigeot =1: PCIE Power Gating Enabled 6266c59a5c48SFrançois Tigeot Bit[1]=0: DDR-DLL shut-down feature disabled. 6267c59a5c48SFrançois Tigeot 1: DDR-DLL shut-down feature enabled. 6268c59a5c48SFrançois Tigeot Bit[2]=0: DDR-PLL Power down feature disabled. 6269c59a5c48SFrançois Tigeot 1: DDR-PLL Power down feature enabled. 6270c59a5c48SFrançois Tigeot Bit[3]=0: GNB DPM is disabled 6271c59a5c48SFrançois Tigeot =1: GNB DPM is enabled 6272c59a5c48SFrançois Tigeot ulCPUCapInfo: TBD 6273c59a5c48SFrançois Tigeot 6274c59a5c48SFrançois Tigeot usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6275c59a5c48SFrançois Tigeot usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6276c59a5c48SFrançois Tigeot to indicate a range. 6277c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6278c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6279c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6280c59a5c48SFrançois Tigeot SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6281c59a5c48SFrançois Tigeot 6282c59a5c48SFrançois Tigeot ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 6283c59a5c48SFrançois Tigeot ucUMAChannelNumber: System memory channel numbers. 6284c59a5c48SFrançois Tigeot 6285c59a5c48SFrançois Tigeot strVBIOSMsg[40]: VBIOS boot up customized message string 6286c59a5c48SFrançois Tigeot 6287c59a5c48SFrançois Tigeot sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6288c59a5c48SFrançois Tigeot 6289c59a5c48SFrançois Tigeot ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6290c59a5c48SFrançois Tigeot ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 6291c59a5c48SFrançois Tigeot ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6292c59a5c48SFrançois Tigeot ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6293c59a5c48SFrançois Tigeot 6294c59a5c48SFrançois Tigeot usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6295c59a5c48SFrançois Tigeot usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6296c59a5c48SFrançois Tigeot usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6297c59a5c48SFrançois Tigeot usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6298c59a5c48SFrançois Tigeot usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6299c59a5c48SFrançois Tigeot usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6300c59a5c48SFrançois Tigeot usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6301c59a5c48SFrançois Tigeot usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6302c59a5c48SFrançois Tigeot 6303c59a5c48SFrançois Tigeot usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 6304c59a5c48SFrançois Tigeot ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 6305c59a5c48SFrançois Tigeot ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 6306c59a5c48SFrançois Tigeot 6307c59a5c48SFrançois Tigeot usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6308c59a5c48SFrançois Tigeot ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6309c59a5c48SFrançois Tigeot [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6310c59a5c48SFrançois Tigeot [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6311c59a5c48SFrançois Tigeot [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6312c59a5c48SFrançois Tigeot [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6313c59a5c48SFrançois Tigeot [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6314c59a5c48SFrançois Tigeot ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6315c59a5c48SFrançois Tigeot value to program Travis register LVDS_CTRL_4 6316c59a5c48SFrançois Tigeot ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 6317c59a5c48SFrançois Tigeot LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6318c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6319c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6320c59a5c48SFrançois Tigeot ucLVDSPwrOnDEtoVARY_BL_in4Ms: 6321c59a5c48SFrançois Tigeot LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6322c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6323c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6324c59a5c48SFrançois Tigeot ucLVDSPwrOffVARY_BLtoDE_in4Ms: 6325c59a5c48SFrançois Tigeot LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6326c59a5c48SFrançois Tigeot =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6327c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6328c59a5c48SFrançois Tigeot ucLVDSPwrOffDEtoDIGON_in4Ms: 6329c59a5c48SFrançois Tigeot LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6330c59a5c48SFrançois Tigeot =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6331c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6332c59a5c48SFrançois Tigeot ucLVDSOffToOnDelay_in4Ms: 6333c59a5c48SFrançois Tigeot LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6334c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 125 ( 500ms ). 6335c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6336c59a5c48SFrançois Tigeot ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6337c59a5c48SFrançois Tigeot LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6338c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 0 ( 0ms ). 6339c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6340c59a5c48SFrançois Tigeot 6341c59a5c48SFrançois Tigeot ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6342c59a5c48SFrançois Tigeot LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6343c59a5c48SFrançois Tigeot =0 means to use VBIOS default delay which is 0 ( 0ms ). 6344c59a5c48SFrançois Tigeot This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6345c59a5c48SFrançois Tigeot ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6346c59a5c48SFrançois Tigeot 6347c59a5c48SFrançois Tigeot ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 6348c59a5c48SFrançois Tigeot 6349c59a5c48SFrançois Tigeot ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 6350c59a5c48SFrançois Tigeot ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 6351c59a5c48SFrançois Tigeot usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 6352c59a5c48SFrançois Tigeot usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 6353c59a5c48SFrançois Tigeot sExtDispConnInfo: Display connector information table provided to VBIOS 6354c59a5c48SFrançois Tigeot 6355c59a5c48SFrançois Tigeot **********************************************************************************************************************/ 6356c59a5c48SFrançois Tigeot 6357c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_REG_INFO 6358c59a5c48SFrançois Tigeot { 6359c59a5c48SFrançois Tigeot UCHAR ucI2cRegIndex; 6360c59a5c48SFrançois Tigeot UCHAR ucI2cRegVal; 6361c59a5c48SFrançois Tigeot }ATOM_I2C_REG_INFO; 6362c59a5c48SFrançois Tigeot 6363c59a5c48SFrançois Tigeot // this IntegrateSystemInfoTable is used for Carrizo 6364c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 6365c59a5c48SFrançois Tigeot { 6366c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6367c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; 6368c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; 6369c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; 6370c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 6371c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 6372c59a5c48SFrançois Tigeot ULONG ulVBIOSMisc; 6373c59a5c48SFrançois Tigeot ULONG ulGPUCapInfo; 6374c59a5c48SFrançois Tigeot ULONG ulDISP_CLK2Freq; 6375c59a5c48SFrançois Tigeot USHORT usRequestedPWMFreqInHz; 6376c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; 6377c59a5c48SFrançois Tigeot UCHAR ucHtcHystLmt; 6378c59a5c48SFrançois Tigeot ULONG ulReserved2; 6379c59a5c48SFrançois Tigeot ULONG ulSystemConfig; 6380c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 6381c59a5c48SFrançois Tigeot ULONG ulReserved3; 6382c59a5c48SFrançois Tigeot USHORT usGPUReservedSysMemSize; 6383c59a5c48SFrançois Tigeot USHORT usExtDispConnInfoOffset; 6384c59a5c48SFrançois Tigeot USHORT usPanelRefreshRateRange; 6385c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 6386c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 6387c59a5c48SFrançois Tigeot UCHAR strVBIOSMsg[40]; 6388c59a5c48SFrançois Tigeot ATOM_TDP_CONFIG asTdpConfig; 6389c59a5c48SFrançois Tigeot UCHAR ucExtHDMIReDrvSlvAddr; 6390c59a5c48SFrançois Tigeot UCHAR ucExtHDMIReDrvRegNum; 6391c59a5c48SFrançois Tigeot ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 6392c59a5c48SFrançois Tigeot ULONG ulReserved[2]; 6393c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6394c59a5c48SFrançois Tigeot ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 6395c59a5c48SFrançois Tigeot ULONG ulGMCRestoreResetTime; 6396c59a5c48SFrançois Tigeot ULONG ulReserved4; 6397c59a5c48SFrançois Tigeot ULONG ulIdleNClk; 6398c59a5c48SFrançois Tigeot ULONG ulDDR_DLL_PowerUpTime; 6399c59a5c48SFrançois Tigeot ULONG ulDDR_PLL_PowerUpTime; 6400c59a5c48SFrançois Tigeot USHORT usPCIEClkSSPercentage; 6401c59a5c48SFrançois Tigeot USHORT usPCIEClkSSType; 6402c59a5c48SFrançois Tigeot USHORT usLvdsSSPercentage; 6403c59a5c48SFrançois Tigeot USHORT usLvdsSSpreadRateIn10Hz; 6404c59a5c48SFrançois Tigeot USHORT usHDMISSPercentage; 6405c59a5c48SFrançois Tigeot USHORT usHDMISSpreadRateIn10Hz; 6406c59a5c48SFrançois Tigeot USHORT usDVISSPercentage; 6407c59a5c48SFrançois Tigeot USHORT usDVISSpreadRateIn10Hz; 6408c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrLo; 6409c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrHi; 6410c59a5c48SFrançois Tigeot ULONG ulReserved5[3]; 6411c59a5c48SFrançois Tigeot USHORT usMaxLVDSPclkFreqInSingleLink; 6412c59a5c48SFrançois Tigeot UCHAR ucLvdsMisc; 6413c59a5c48SFrançois Tigeot UCHAR ucTravisLVDSVolAdjust; 6414c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6415c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6416c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6417c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6418c59a5c48SFrançois Tigeot UCHAR ucLVDSOffToOnDelay_in4Ms; 6419c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6420c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6421c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 6422c59a5c48SFrançois Tigeot ULONG ulLCDBitDepthControlVal; 6423c59a5c48SFrançois Tigeot ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 6424c59a5c48SFrançois Tigeot ULONG ulPSPVersion; 6425c59a5c48SFrançois Tigeot ULONG ulNbpStateNClkFreq[4]; 6426c59a5c48SFrançois Tigeot USHORT usNBPStateVoltage[4]; 6427c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 6428c59a5c48SFrançois Tigeot UCHAR ucEDPv1_4VSMode; 6429c59a5c48SFrançois Tigeot UCHAR ucReserved2; 6430c59a5c48SFrançois Tigeot ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6431c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 6432c59a5c48SFrançois Tigeot 6433c59a5c48SFrançois Tigeot 6434c59a5c48SFrançois Tigeot // definition for ucEDPv1_4VSMode 6435c59a5c48SFrançois Tigeot #define EDP_VS_LEGACY_MODE 0 6436c59a5c48SFrançois Tigeot #define EDP_VS_LOW_VDIFF_MODE 1 6437c59a5c48SFrançois Tigeot #define EDP_VS_HIGH_VDIFF_MODE 2 6438c59a5c48SFrançois Tigeot #define EDP_VS_STRETCH_MODE 3 6439c59a5c48SFrançois Tigeot #define EDP_VS_SINGLE_VDIFF_MODE 4 6440c59a5c48SFrançois Tigeot #define EDP_VS_VARIABLE_PREM_MODE 5 6441c59a5c48SFrançois Tigeot 6442c59a5c48SFrançois Tigeot 6443d78d3a22SFrançois Tigeot // ulGPUCapInfo 6444d78d3a22SFrançois Tigeot #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 6445d78d3a22SFrançois Tigeot #define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10 6446d78d3a22SFrançois Tigeot //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6447d78d3a22SFrançois Tigeot #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 6448d78d3a22SFrançois Tigeot //ulGPUCapInfo[18]=1 indicate the IOMMU is not available 6449d78d3a22SFrançois Tigeot #define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 6450d78d3a22SFrançois Tigeot //ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. 6451d78d3a22SFrançois Tigeot #define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000 6452d78d3a22SFrançois Tigeot 6453d78d3a22SFrançois Tigeot 6454d78d3a22SFrançois Tigeot typedef struct _DPHY_TIMING_PARA 6455d78d3a22SFrançois Tigeot { 6456d78d3a22SFrançois Tigeot UCHAR ucProfileID; // SENSOR_PROFILES 6457d78d3a22SFrançois Tigeot ULONG ucPara; 6458d78d3a22SFrançois Tigeot } DPHY_TIMING_PARA; 6459d78d3a22SFrançois Tigeot 6460d78d3a22SFrançois Tigeot typedef struct _DPHY_ELEC_PARA 6461d78d3a22SFrançois Tigeot { 6462d78d3a22SFrançois Tigeot USHORT usPara[3]; 6463d78d3a22SFrançois Tigeot } DPHY_ELEC_PARA; 6464d78d3a22SFrançois Tigeot 6465d78d3a22SFrançois Tigeot typedef struct _CAMERA_MODULE_INFO 6466d78d3a22SFrançois Tigeot { 6467d78d3a22SFrançois Tigeot UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user 6468d78d3a22SFrançois Tigeot UCHAR strModuleName[8]; 6469d78d3a22SFrançois Tigeot DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor 6470d78d3a22SFrançois Tigeot } CAMERA_MODULE_INFO; 6471d78d3a22SFrançois Tigeot 6472d78d3a22SFrançois Tigeot typedef struct _FLASHLIGHT_INFO 6473d78d3a22SFrançois Tigeot { 6474d78d3a22SFrançois Tigeot UCHAR ucID; // 0: Rear, 1: Front 6475d78d3a22SFrançois Tigeot UCHAR strName[8]; 6476d78d3a22SFrançois Tigeot } FLASHLIGHT_INFO; 6477d78d3a22SFrançois Tigeot 6478d78d3a22SFrançois Tigeot typedef struct _CAMERA_DATA 6479d78d3a22SFrançois Tigeot { 6480d78d3a22SFrançois Tigeot ULONG ulVersionCode; 6481d78d3a22SFrançois Tigeot CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max 6482d78d3a22SFrançois Tigeot FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max 6483d78d3a22SFrançois Tigeot DPHY_ELEC_PARA asDphyElecPara; 6484d78d3a22SFrançois Tigeot ULONG ulCrcVal; // CRC 6485d78d3a22SFrançois Tigeot }CAMERA_DATA; 6486d78d3a22SFrançois Tigeot 6487c59a5c48SFrançois Tigeot typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 6488c59a5c48SFrançois Tigeot { 6489c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6490c59a5c48SFrançois Tigeot ULONG ulBootUpEngineClock; 6491c59a5c48SFrançois Tigeot ULONG ulDentistVCOFreq; 6492c59a5c48SFrançois Tigeot ULONG ulBootUpUMAClock; 6493c59a5c48SFrançois Tigeot ULONG ulReserved0[8]; 6494c59a5c48SFrançois Tigeot ULONG ulBootUpReqDisplayVector; 6495c59a5c48SFrançois Tigeot ULONG ulVBIOSMisc; 6496c59a5c48SFrançois Tigeot ULONG ulGPUCapInfo; 6497c59a5c48SFrançois Tigeot ULONG ulReserved1; 6498c59a5c48SFrançois Tigeot USHORT usRequestedPWMFreqInHz; 6499c59a5c48SFrançois Tigeot UCHAR ucHtcTmpLmt; 6500c59a5c48SFrançois Tigeot UCHAR ucHtcHystLmt; 6501c59a5c48SFrançois Tigeot ULONG ulReserved2; 6502c59a5c48SFrançois Tigeot ULONG ulSystemConfig; 6503c59a5c48SFrançois Tigeot ULONG ulCPUCapInfo; 6504c59a5c48SFrançois Tigeot ULONG ulReserved3; 6505c59a5c48SFrançois Tigeot USHORT usGPUReservedSysMemSize; 6506c59a5c48SFrançois Tigeot USHORT usExtDispConnInfoOffset; 6507c59a5c48SFrançois Tigeot USHORT usPanelRefreshRateRange; 6508c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 6509c59a5c48SFrançois Tigeot UCHAR ucUMAChannelNumber; 6510d78d3a22SFrançois Tigeot ULONG ulMsgReserved[10]; 6511c59a5c48SFrançois Tigeot ATOM_TDP_CONFIG asTdpConfig; 6512c59a5c48SFrançois Tigeot ULONG ulReserved[7]; 6513c59a5c48SFrançois Tigeot ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6514c59a5c48SFrançois Tigeot ULONG ulReserved6[10]; 6515c59a5c48SFrançois Tigeot ULONG ulGMCRestoreResetTime; 6516c59a5c48SFrançois Tigeot ULONG ulReserved4; 6517c59a5c48SFrançois Tigeot ULONG ulIdleNClk; 6518c59a5c48SFrançois Tigeot ULONG ulDDR_DLL_PowerUpTime; 6519c59a5c48SFrançois Tigeot ULONG ulDDR_PLL_PowerUpTime; 6520c59a5c48SFrançois Tigeot USHORT usPCIEClkSSPercentage; 6521c59a5c48SFrançois Tigeot USHORT usPCIEClkSSType; 6522c59a5c48SFrançois Tigeot USHORT usLvdsSSPercentage; 6523c59a5c48SFrançois Tigeot USHORT usLvdsSSpreadRateIn10Hz; 6524c59a5c48SFrançois Tigeot USHORT usHDMISSPercentage; 6525c59a5c48SFrançois Tigeot USHORT usHDMISSpreadRateIn10Hz; 6526c59a5c48SFrançois Tigeot USHORT usDVISSPercentage; 6527c59a5c48SFrançois Tigeot USHORT usDVISSpreadRateIn10Hz; 6528c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrLo; 6529c59a5c48SFrançois Tigeot ULONG ulGPUReservedSysMemBaseAddrHi; 6530c59a5c48SFrançois Tigeot ULONG ulReserved5[3]; 6531c59a5c48SFrançois Tigeot USHORT usMaxLVDSPclkFreqInSingleLink; 6532c59a5c48SFrançois Tigeot UCHAR ucLvdsMisc; 6533c59a5c48SFrançois Tigeot UCHAR ucTravisLVDSVolAdjust; 6534c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6535c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6536c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6537c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6538c59a5c48SFrançois Tigeot UCHAR ucLVDSOffToOnDelay_in4Ms; 6539c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6540c59a5c48SFrançois Tigeot UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6541c59a5c48SFrançois Tigeot UCHAR ucMinAllowedBL_Level; 6542c59a5c48SFrançois Tigeot ULONG ulLCDBitDepthControlVal; 6543c59a5c48SFrançois Tigeot ULONG ulNbpStateMemclkFreq[2]; 6544c59a5c48SFrançois Tigeot ULONG ulReserved7[2]; 6545c59a5c48SFrançois Tigeot ULONG ulPSPVersion; 6546c59a5c48SFrançois Tigeot ULONG ulNbpStateNClkFreq[4]; 6547c59a5c48SFrançois Tigeot USHORT usNBPStateVoltage[4]; 6548c59a5c48SFrançois Tigeot USHORT usBootUpNBVoltage; 6549c59a5c48SFrançois Tigeot UCHAR ucEDPv1_4VSMode; 6550c59a5c48SFrançois Tigeot UCHAR ucReserved2; 6551c59a5c48SFrançois Tigeot ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6552d78d3a22SFrançois Tigeot CAMERA_DATA asCameraInfo; 6553d78d3a22SFrançois Tigeot ULONG ulReserved8[29]; 6554c59a5c48SFrançois Tigeot }ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 6555c59a5c48SFrançois Tigeot 6556d78d3a22SFrançois Tigeot 6557d78d3a22SFrançois Tigeot // this Table is used for Kaveri/Kabini APU 6558d78d3a22SFrançois Tigeot typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 6559d78d3a22SFrançois Tigeot { 6560d78d3a22SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6561d78d3a22SFrançois Tigeot ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 6562d78d3a22SFrançois Tigeot }ATOM_FUSION_SYSTEM_INFO_V2; 6563d78d3a22SFrançois Tigeot 6564d78d3a22SFrançois Tigeot 6565d78d3a22SFrançois Tigeot typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 6566d78d3a22SFrançois Tigeot { 6567d78d3a22SFrançois Tigeot ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6568d78d3a22SFrançois Tigeot ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable 6569d78d3a22SFrançois Tigeot }ATOM_FUSION_SYSTEM_INFO_V3; 6570d78d3a22SFrançois Tigeot 6571d78d3a22SFrançois Tigeot #define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800 6572d78d3a22SFrançois Tigeot 6573c59a5c48SFrançois Tigeot /**************************************************************************/ 6574c59a5c48SFrançois Tigeot // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 6575c59a5c48SFrançois Tigeot //Memory SS Info Table 6576c59a5c48SFrançois Tigeot //Define Memory Clock SS chip ID 6577c59a5c48SFrançois Tigeot #define ICS91719 1 6578c59a5c48SFrançois Tigeot #define ICS91720 2 6579c59a5c48SFrançois Tigeot 6580c59a5c48SFrançois Tigeot //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 6581c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_DATA_RECORD 6582c59a5c48SFrançois Tigeot { 6583c59a5c48SFrançois Tigeot UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 6584c59a5c48SFrançois Tigeot UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 6585c59a5c48SFrançois Tigeot }ATOM_I2C_DATA_RECORD; 6586c59a5c48SFrançois Tigeot 6587c59a5c48SFrançois Tigeot 6588c59a5c48SFrançois Tigeot //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 6589c59a5c48SFrançois Tigeot typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 6590c59a5c48SFrançois Tigeot { 6591c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 6592c59a5c48SFrançois Tigeot UCHAR ucSSChipID; //SS chip being used 6593c59a5c48SFrançois Tigeot UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 6594c59a5c48SFrançois Tigeot UCHAR ucNumOfI2CDataRecords; //number of data block 6595c59a5c48SFrançois Tigeot ATOM_I2C_DATA_RECORD asI2CData[1]; 6596c59a5c48SFrançois Tigeot }ATOM_I2C_DEVICE_SETUP_INFO; 6597c59a5c48SFrançois Tigeot 6598c59a5c48SFrançois Tigeot //========================================================================================== 6599c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_MVDD_INFO 6600c59a5c48SFrançois Tigeot { 6601c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6602c59a5c48SFrançois Tigeot ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 6603c59a5c48SFrançois Tigeot }ATOM_ASIC_MVDD_INFO; 6604c59a5c48SFrançois Tigeot 6605c59a5c48SFrançois Tigeot //========================================================================================== 6606c59a5c48SFrançois Tigeot #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 6607c59a5c48SFrançois Tigeot 6608c59a5c48SFrançois Tigeot //========================================================================================== 6609c59a5c48SFrançois Tigeot /**************************************************************************/ 6610c59a5c48SFrançois Tigeot 6611c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_SS_ASSIGNMENT 6612c59a5c48SFrançois Tigeot { 6613c59a5c48SFrançois Tigeot ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 6614c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6615c59a5c48SFrançois Tigeot USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 6616c59a5c48SFrançois Tigeot UCHAR ucClockIndication; //Indicate which clock source needs SS 6617c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 6618c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 6619c59a5c48SFrançois Tigeot }ATOM_ASIC_SS_ASSIGNMENT; 6620c59a5c48SFrançois Tigeot 6621c59a5c48SFrançois Tigeot //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 6622c59a5c48SFrançois Tigeot //SS is not required or enabled if a match is not found. 6623c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_MEMORY_SS 1 6624c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_ENGINE_SS 2 6625c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_UVD_SS 3 6626c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_SS_ON_TMDS 4 6627c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_SS_ON_HDMI 5 6628c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_SS_ON_LVDS 6 6629c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_SS_ON_DP 7 6630c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_SS_ON_DCPLL 8 6631c59a5c48SFrançois Tigeot #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 6632c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_VCE_SS 10 6633c59a5c48SFrançois Tigeot #define ASIC_INTERNAL_GPUPLL_SS 11 6634c59a5c48SFrançois Tigeot 6635c59a5c48SFrançois Tigeot 6636c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 6637c59a5c48SFrançois Tigeot { 6638c59a5c48SFrançois Tigeot ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6639c59a5c48SFrançois Tigeot //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6640c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6641c59a5c48SFrançois Tigeot USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6642c59a5c48SFrançois Tigeot UCHAR ucClockIndication; //Indicate which clock source needs SS 6643c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6644c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 6645c59a5c48SFrançois Tigeot }ATOM_ASIC_SS_ASSIGNMENT_V2; 6646c59a5c48SFrançois Tigeot 6647c59a5c48SFrançois Tigeot //ucSpreadSpectrumMode 6648c59a5c48SFrançois Tigeot //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 6649c59a5c48SFrançois Tigeot //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 6650c59a5c48SFrançois Tigeot //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 6651c59a5c48SFrançois Tigeot //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 6652c59a5c48SFrançois Tigeot //#define ATOM_INTERNAL_SS_MASK 0x00000000 6653c59a5c48SFrançois Tigeot //#define ATOM_EXTERNAL_SS_MASK 0x00000002 6654c59a5c48SFrançois Tigeot 6655c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 6656c59a5c48SFrançois Tigeot { 6657c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6658c59a5c48SFrançois Tigeot ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 6659c59a5c48SFrançois Tigeot }ATOM_ASIC_INTERNAL_SS_INFO; 6660c59a5c48SFrançois Tigeot 6661c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 6662c59a5c48SFrançois Tigeot { 6663c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6664c59a5c48SFrançois Tigeot ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 6665c59a5c48SFrançois Tigeot }ATOM_ASIC_INTERNAL_SS_INFO_V2; 6666c59a5c48SFrançois Tigeot 6667c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 6668c59a5c48SFrançois Tigeot { 6669c59a5c48SFrançois Tigeot ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6670c59a5c48SFrançois Tigeot //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6671c59a5c48SFrançois Tigeot USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 6672c59a5c48SFrançois Tigeot USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6673c59a5c48SFrançois Tigeot UCHAR ucClockIndication; //Indicate which clock source needs SS 6674c59a5c48SFrançois Tigeot UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6675c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 6676c59a5c48SFrançois Tigeot }ATOM_ASIC_SS_ASSIGNMENT_V3; 6677c59a5c48SFrançois Tigeot 6678c59a5c48SFrançois Tigeot //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 6679c59a5c48SFrançois Tigeot #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 6680c59a5c48SFrançois Tigeot #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 6681c59a5c48SFrançois Tigeot #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 6682c59a5c48SFrançois Tigeot 6683c59a5c48SFrançois Tigeot typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 6684c59a5c48SFrançois Tigeot { 6685c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 6686c59a5c48SFrançois Tigeot ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 6687c59a5c48SFrançois Tigeot }ATOM_ASIC_INTERNAL_SS_INFO_V3; 6688c59a5c48SFrançois Tigeot 6689c59a5c48SFrançois Tigeot 6690c59a5c48SFrançois Tigeot //==============================Scratch Pad Definition Portion=============================== 6691c59a5c48SFrançois Tigeot #define ATOM_DEVICE_CONNECT_INFO_DEF 0 6692c59a5c48SFrançois Tigeot #define ATOM_ROM_LOCATION_DEF 1 6693c59a5c48SFrançois Tigeot #define ATOM_TV_STANDARD_DEF 2 6694c59a5c48SFrançois Tigeot #define ATOM_ACTIVE_INFO_DEF 3 6695c59a5c48SFrançois Tigeot #define ATOM_LCD_INFO_DEF 4 6696c59a5c48SFrançois Tigeot #define ATOM_DOS_REQ_INFO_DEF 5 6697c59a5c48SFrançois Tigeot #define ATOM_ACC_CHANGE_INFO_DEF 6 6698c59a5c48SFrançois Tigeot #define ATOM_DOS_MODE_INFO_DEF 7 6699c59a5c48SFrançois Tigeot #define ATOM_I2C_CHANNEL_STATUS_DEF 8 6700c59a5c48SFrançois Tigeot #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 6701c59a5c48SFrançois Tigeot #define ATOM_INTERNAL_TIMER_DEF 10 6702c59a5c48SFrançois Tigeot 6703c59a5c48SFrançois Tigeot // BIOS_0_SCRATCH Definition 6704c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_MONO 0x00000001L 6705c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_COLOR 0x00000002L 6706c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 6707c59a5c48SFrançois Tigeot 6708c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 6709c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 6710c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 6711c59a5c48SFrançois Tigeot 6712c59a5c48SFrançois Tigeot #define ATOM_S0_CV_A 0x00000010L 6713c59a5c48SFrançois Tigeot #define ATOM_S0_CV_DIN_A 0x00000020L 6714c59a5c48SFrançois Tigeot #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 6715c59a5c48SFrançois Tigeot 6716c59a5c48SFrançois Tigeot 6717c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_MONO 0x00000100L 6718c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_COLOR 0x00000200L 6719c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6720c59a5c48SFrançois Tigeot 6721c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_COMPOSITE 0x00000400L 6722c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SVIDEO 0x00000800L 6723c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SCART 0x00004000L 6724c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6725c59a5c48SFrançois Tigeot 6726c59a5c48SFrançois Tigeot #define ATOM_S0_CV 0x00001000L 6727c59a5c48SFrançois Tigeot #define ATOM_S0_CV_DIN 0x00002000L 6728c59a5c48SFrançois Tigeot #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6729c59a5c48SFrançois Tigeot 6730c59a5c48SFrançois Tigeot #define ATOM_S0_DFP1 0x00010000L 6731c59a5c48SFrançois Tigeot #define ATOM_S0_DFP2 0x00020000L 6732c59a5c48SFrançois Tigeot #define ATOM_S0_LCD1 0x00040000L 6733c59a5c48SFrançois Tigeot #define ATOM_S0_LCD2 0x00080000L 6734c59a5c48SFrançois Tigeot #define ATOM_S0_DFP6 0x00100000L 6735c59a5c48SFrançois Tigeot #define ATOM_S0_DFP3 0x00200000L 6736c59a5c48SFrançois Tigeot #define ATOM_S0_DFP4 0x00400000L 6737c59a5c48SFrançois Tigeot #define ATOM_S0_DFP5 0x00800000L 6738c59a5c48SFrançois Tigeot 6739c59a5c48SFrançois Tigeot 6740c59a5c48SFrançois Tigeot #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6741c59a5c48SFrançois Tigeot 6742c59a5c48SFrançois Tigeot #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6743c59a5c48SFrançois Tigeot // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6744c59a5c48SFrançois Tigeot 6745c59a5c48SFrançois Tigeot #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6746c59a5c48SFrançois Tigeot #define ATOM_S0_THERMAL_STATE_SHIFT 26 6747c59a5c48SFrançois Tigeot 6748c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6749c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6750c59a5c48SFrançois Tigeot 6751c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6752c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6753c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6754c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6755c59a5c48SFrançois Tigeot 6756c59a5c48SFrançois Tigeot //Byte aligned defintion for BIOS usage 6757c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_MONOb0 0x01 6758c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_COLORb0 0x02 6759c59a5c48SFrançois Tigeot #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6760c59a5c48SFrançois Tigeot 6761c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_COMPOSITEb0 0x04 6762c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SVIDEOb0 0x08 6763c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6764c59a5c48SFrançois Tigeot 6765c59a5c48SFrançois Tigeot #define ATOM_S0_CVb0 0x10 6766c59a5c48SFrançois Tigeot #define ATOM_S0_CV_DINb0 0x20 6767c59a5c48SFrançois Tigeot #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6768c59a5c48SFrançois Tigeot 6769c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_MONOb1 0x01 6770c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_COLORb1 0x02 6771c59a5c48SFrançois Tigeot #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6772c59a5c48SFrançois Tigeot 6773c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_COMPOSITEb1 0x04 6774c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SVIDEOb1 0x08 6775c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_SCARTb1 0x40 6776c59a5c48SFrançois Tigeot #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6777c59a5c48SFrançois Tigeot 6778c59a5c48SFrançois Tigeot #define ATOM_S0_CVb1 0x10 6779c59a5c48SFrançois Tigeot #define ATOM_S0_CV_DINb1 0x20 6780c59a5c48SFrançois Tigeot #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6781c59a5c48SFrançois Tigeot 6782c59a5c48SFrançois Tigeot #define ATOM_S0_DFP1b2 0x01 6783c59a5c48SFrançois Tigeot #define ATOM_S0_DFP2b2 0x02 6784c59a5c48SFrançois Tigeot #define ATOM_S0_LCD1b2 0x04 6785c59a5c48SFrançois Tigeot #define ATOM_S0_LCD2b2 0x08 6786c59a5c48SFrançois Tigeot #define ATOM_S0_DFP6b2 0x10 6787c59a5c48SFrançois Tigeot #define ATOM_S0_DFP3b2 0x20 6788c59a5c48SFrançois Tigeot #define ATOM_S0_DFP4b2 0x40 6789c59a5c48SFrançois Tigeot #define ATOM_S0_DFP5b2 0x80 6790c59a5c48SFrançois Tigeot 6791c59a5c48SFrançois Tigeot 6792c59a5c48SFrançois Tigeot #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6793c59a5c48SFrançois Tigeot #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6794c59a5c48SFrançois Tigeot 6795c59a5c48SFrançois Tigeot #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6796c59a5c48SFrançois Tigeot #define ATOM_S0_LCD1_SHIFT 18 6797c59a5c48SFrançois Tigeot 6798c59a5c48SFrançois Tigeot // BIOS_1_SCRATCH Definition 6799c59a5c48SFrançois Tigeot #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6800c59a5c48SFrançois Tigeot #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6801c59a5c48SFrançois Tigeot 6802c59a5c48SFrançois Tigeot // BIOS_2_SCRATCH Definition 6803c59a5c48SFrançois Tigeot #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6804c59a5c48SFrançois Tigeot #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6805c59a5c48SFrançois Tigeot #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6806c59a5c48SFrançois Tigeot 6807c59a5c48SFrançois Tigeot #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6808c59a5c48SFrançois Tigeot #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6809c59a5c48SFrançois Tigeot #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6810c59a5c48SFrançois Tigeot 6811c59a5c48SFrançois Tigeot #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6812c59a5c48SFrançois Tigeot #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6813c59a5c48SFrançois Tigeot 6814c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6815c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6816c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6817c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6818c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6819c59a5c48SFrançois Tigeot #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6820c59a5c48SFrançois Tigeot 6821c59a5c48SFrançois Tigeot 6822c59a5c48SFrançois Tigeot //Byte aligned defintion for BIOS usage 6823c59a5c48SFrançois Tigeot #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6824c59a5c48SFrançois Tigeot #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6825c59a5c48SFrançois Tigeot #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6826c59a5c48SFrançois Tigeot 6827c59a5c48SFrançois Tigeot #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6828c59a5c48SFrançois Tigeot #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6829c59a5c48SFrançois Tigeot #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6830c59a5c48SFrançois Tigeot 6831c59a5c48SFrançois Tigeot 6832c59a5c48SFrançois Tigeot // BIOS_3_SCRATCH Definition 6833c59a5c48SFrançois Tigeot #define ATOM_S3_CRT1_ACTIVE 0x00000001L 6834c59a5c48SFrançois Tigeot #define ATOM_S3_LCD1_ACTIVE 0x00000002L 6835c59a5c48SFrançois Tigeot #define ATOM_S3_TV1_ACTIVE 0x00000004L 6836c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1_ACTIVE 0x00000008L 6837c59a5c48SFrançois Tigeot #define ATOM_S3_CRT2_ACTIVE 0x00000010L 6838c59a5c48SFrançois Tigeot #define ATOM_S3_LCD2_ACTIVE 0x00000020L 6839c59a5c48SFrançois Tigeot #define ATOM_S3_DFP6_ACTIVE 0x00000040L 6840c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2_ACTIVE 0x00000080L 6841c59a5c48SFrançois Tigeot #define ATOM_S3_CV_ACTIVE 0x00000100L 6842c59a5c48SFrançois Tigeot #define ATOM_S3_DFP3_ACTIVE 0x00000200L 6843c59a5c48SFrançois Tigeot #define ATOM_S3_DFP4_ACTIVE 0x00000400L 6844c59a5c48SFrançois Tigeot #define ATOM_S3_DFP5_ACTIVE 0x00000800L 6845c59a5c48SFrançois Tigeot 6846c59a5c48SFrançois Tigeot 6847c59a5c48SFrançois Tigeot #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6848c59a5c48SFrançois Tigeot 6849c59a5c48SFrançois Tigeot #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6850c59a5c48SFrançois Tigeot #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6851c59a5c48SFrançois Tigeot 6852c59a5c48SFrançois Tigeot #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6853c59a5c48SFrançois Tigeot #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6854c59a5c48SFrançois Tigeot #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6855c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6856c59a5c48SFrançois Tigeot #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6857c59a5c48SFrançois Tigeot #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6858c59a5c48SFrançois Tigeot #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6859c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6860c59a5c48SFrançois Tigeot #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6861c59a5c48SFrançois Tigeot #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6862c59a5c48SFrançois Tigeot #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6863c59a5c48SFrançois Tigeot #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6864c59a5c48SFrançois Tigeot 6865c59a5c48SFrançois Tigeot 6866c59a5c48SFrançois Tigeot #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6867c59a5c48SFrançois Tigeot #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6868c59a5c48SFrançois Tigeot //Below two definitions are not supported in pplib, but in the old powerplay in DAL 6869c59a5c48SFrançois Tigeot #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6870c59a5c48SFrançois Tigeot #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6871c59a5c48SFrançois Tigeot 6872c59a5c48SFrançois Tigeot 6873c59a5c48SFrançois Tigeot 6874c59a5c48SFrançois Tigeot //Byte aligned defintion for BIOS usage 6875c59a5c48SFrançois Tigeot #define ATOM_S3_CRT1_ACTIVEb0 0x01 6876c59a5c48SFrançois Tigeot #define ATOM_S3_LCD1_ACTIVEb0 0x02 6877c59a5c48SFrançois Tigeot #define ATOM_S3_TV1_ACTIVEb0 0x04 6878c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1_ACTIVEb0 0x08 6879c59a5c48SFrançois Tigeot #define ATOM_S3_CRT2_ACTIVEb0 0x10 6880c59a5c48SFrançois Tigeot #define ATOM_S3_LCD2_ACTIVEb0 0x20 6881c59a5c48SFrançois Tigeot #define ATOM_S3_DFP6_ACTIVEb0 0x40 6882c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2_ACTIVEb0 0x80 6883c59a5c48SFrançois Tigeot #define ATOM_S3_CV_ACTIVEb1 0x01 6884c59a5c48SFrançois Tigeot #define ATOM_S3_DFP3_ACTIVEb1 0x02 6885c59a5c48SFrançois Tigeot #define ATOM_S3_DFP4_ACTIVEb1 0x04 6886c59a5c48SFrançois Tigeot #define ATOM_S3_DFP5_ACTIVEb1 0x08 6887c59a5c48SFrançois Tigeot 6888c59a5c48SFrançois Tigeot 6889c59a5c48SFrançois Tigeot #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6890c59a5c48SFrançois Tigeot 6891c59a5c48SFrançois Tigeot #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6892c59a5c48SFrançois Tigeot #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6893c59a5c48SFrançois Tigeot #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6894c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6895c59a5c48SFrançois Tigeot #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6896c59a5c48SFrançois Tigeot #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6897c59a5c48SFrançois Tigeot #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6898c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6899c59a5c48SFrançois Tigeot #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6900c59a5c48SFrançois Tigeot #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6901c59a5c48SFrançois Tigeot #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6902c59a5c48SFrançois Tigeot #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6903c59a5c48SFrançois Tigeot 6904c59a5c48SFrançois Tigeot 6905c59a5c48SFrançois Tigeot #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6906c59a5c48SFrançois Tigeot 6907c59a5c48SFrançois Tigeot 6908c59a5c48SFrançois Tigeot // BIOS_4_SCRATCH Definition 6909c59a5c48SFrançois Tigeot #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6910c59a5c48SFrançois Tigeot #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6911c59a5c48SFrançois Tigeot #define ATOM_S4_LCD1_REFRESH_SHIFT 8 6912c59a5c48SFrançois Tigeot 6913c59a5c48SFrançois Tigeot //Byte aligned defintion for BIOS usage 6914c59a5c48SFrançois Tigeot #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6915c59a5c48SFrançois Tigeot #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6916c59a5c48SFrançois Tigeot #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6917c59a5c48SFrançois Tigeot 6918c59a5c48SFrançois Tigeot // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6919c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CRT1b0 0x01 6920c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_LCD1b0 0x02 6921c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_TV1b0 0x04 6922c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP1b0 0x08 6923c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CRT2b0 0x10 6924c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_LCD2b0 0x20 6925c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP6b0 0x40 6926c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP2b0 0x80 6927c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CVb1 0x01 6928c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP3b1 0x02 6929c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP4b1 0x04 6930c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP5b1 0x08 6931c59a5c48SFrançois Tigeot 6932c59a5c48SFrançois Tigeot 6933c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6934c59a5c48SFrançois Tigeot 6935c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CRT1 0x0001 6936c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_LCD1 0x0002 6937c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_TV1 0x0004 6938c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP1 0x0008 6939c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CRT2 0x0010 6940c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_LCD2 0x0020 6941c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP6 0x0040 6942c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP2 0x0080 6943c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_CV 0x0100 6944c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP3 0x0200 6945c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP4 0x0400 6946c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP5 0x0800 6947c59a5c48SFrançois Tigeot 6948c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6949c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6950c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6951c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6952c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6953c59a5c48SFrançois Tigeot (ATOM_S5_DOS_FORCE_CVb3<<8)) 6954c59a5c48SFrançois Tigeot // BIOS_6_SCRATCH Definition 6955c59a5c48SFrançois Tigeot #define ATOM_S6_DEVICE_CHANGE 0x00000001L 6956c59a5c48SFrançois Tigeot #define ATOM_S6_SCALER_CHANGE 0x00000002L 6957c59a5c48SFrançois Tigeot #define ATOM_S6_LID_CHANGE 0x00000004L 6958c59a5c48SFrançois Tigeot #define ATOM_S6_DOCKING_CHANGE 0x00000008L 6959c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_MODE 0x00000010L 6960c59a5c48SFrançois Tigeot #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6961c59a5c48SFrançois Tigeot #define ATOM_S6_LID_STATE 0x00000040L 6962c59a5c48SFrançois Tigeot #define ATOM_S6_DOCK_STATE 0x00000080L 6963c59a5c48SFrançois Tigeot #define ATOM_S6_CRITICAL_STATE 0x00000100L 6964c59a5c48SFrançois Tigeot #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6965c59a5c48SFrançois Tigeot #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6966c59a5c48SFrançois Tigeot #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6967c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6968c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6969c59a5c48SFrançois Tigeot 6970c59a5c48SFrançois Tigeot #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6971c59a5c48SFrançois Tigeot #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6972c59a5c48SFrançois Tigeot 6973c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6974c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6975c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_TV1 0x00040000L 6976c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6977c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6978c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 6979c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 6980c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 6981c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CV 0x01000000L 6982c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 6983c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 6984c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 6985c59a5c48SFrançois Tigeot 6986c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 6987c59a5c48SFrançois Tigeot #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 6988c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 6989c59a5c48SFrançois Tigeot #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 6990c59a5c48SFrançois Tigeot #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 6991c59a5c48SFrançois Tigeot 6992c59a5c48SFrançois Tigeot //Byte aligned defintion for BIOS usage 6993c59a5c48SFrançois Tigeot #define ATOM_S6_DEVICE_CHANGEb0 0x01 6994c59a5c48SFrançois Tigeot #define ATOM_S6_SCALER_CHANGEb0 0x02 6995c59a5c48SFrançois Tigeot #define ATOM_S6_LID_CHANGEb0 0x04 6996c59a5c48SFrançois Tigeot #define ATOM_S6_DOCKING_CHANGEb0 0x08 6997c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_MODEb0 0x10 6998c59a5c48SFrançois Tigeot #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 6999c59a5c48SFrançois Tigeot #define ATOM_S6_LID_STATEb0 0x40 7000c59a5c48SFrançois Tigeot #define ATOM_S6_DOCK_STATEb0 0x80 7001c59a5c48SFrançois Tigeot #define ATOM_S6_CRITICAL_STATEb1 0x01 7002c59a5c48SFrançois Tigeot #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 7003c59a5c48SFrançois Tigeot #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 7004c59a5c48SFrançois Tigeot #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 7005c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 7006c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 7007c59a5c48SFrançois Tigeot 7008c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CRT1b2 0x01 7009c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_LCD1b2 0x02 7010c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_TV1b2 0x04 7011c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP1b2 0x08 7012c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CRT2b2 0x10 7013c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_LCD2b2 0x20 7014c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP6b2 0x40 7015c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP2b2 0x80 7016c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_CVb3 0x01 7017c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP3b3 0x02 7018c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP4b3 0x04 7019c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP5b3 0x08 7020c59a5c48SFrançois Tigeot 7021c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 7022c59a5c48SFrançois Tigeot #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 7023c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 7024c59a5c48SFrançois Tigeot #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 7025c59a5c48SFrançois Tigeot #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 7026c59a5c48SFrançois Tigeot 7027c59a5c48SFrançois Tigeot #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 7028c59a5c48SFrançois Tigeot #define ATOM_S6_SCALER_CHANGE_SHIFT 1 7029c59a5c48SFrançois Tigeot #define ATOM_S6_LID_CHANGE_SHIFT 2 7030c59a5c48SFrançois Tigeot #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 7031c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_MODE_SHIFT 4 7032c59a5c48SFrançois Tigeot #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 7033c59a5c48SFrançois Tigeot #define ATOM_S6_LID_STATE_SHIFT 6 7034c59a5c48SFrançois Tigeot #define ATOM_S6_DOCK_STATE_SHIFT 7 7035c59a5c48SFrançois Tigeot #define ATOM_S6_CRITICAL_STATE_SHIFT 8 7036c59a5c48SFrançois Tigeot #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 7037c59a5c48SFrançois Tigeot #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 7038c59a5c48SFrançois Tigeot #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 7039c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_SCALER_SHIFT 12 7040c59a5c48SFrançois Tigeot #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 7041c59a5c48SFrançois Tigeot #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 7042c59a5c48SFrançois Tigeot #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 7043c59a5c48SFrançois Tigeot #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 7044c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 7045c59a5c48SFrançois Tigeot #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 7046c59a5c48SFrançois Tigeot #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 7047c59a5c48SFrançois Tigeot 7048c59a5c48SFrançois Tigeot // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 7049c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_TYPEb0 0x03 7050c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_VGAb0 0x00 7051c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_VESAb0 0x01 7052c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_EXTb0 0x02 7053c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 7054c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 7055c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 7056c59a5c48SFrançois Tigeot #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 7057c59a5c48SFrançois Tigeot #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 7058c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 7059c59a5c48SFrançois Tigeot 7060c59a5c48SFrançois Tigeot #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 7061c59a5c48SFrançois Tigeot 7062c59a5c48SFrançois Tigeot // BIOS_8_SCRATCH Definition 7063c59a5c48SFrançois Tigeot #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 7064c59a5c48SFrançois Tigeot #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 7065c59a5c48SFrançois Tigeot 7066c59a5c48SFrançois Tigeot #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 7067c59a5c48SFrançois Tigeot #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 7068c59a5c48SFrançois Tigeot 7069c59a5c48SFrançois Tigeot // BIOS_9_SCRATCH Definition 7070c59a5c48SFrançois Tigeot #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 7071c59a5c48SFrançois Tigeot #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 7072c59a5c48SFrançois Tigeot #endif 7073c59a5c48SFrançois Tigeot #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 7074c59a5c48SFrançois Tigeot #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 7075c59a5c48SFrançois Tigeot #endif 7076c59a5c48SFrançois Tigeot #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 7077c59a5c48SFrançois Tigeot #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 7078c59a5c48SFrançois Tigeot #endif 7079c59a5c48SFrançois Tigeot #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 7080c59a5c48SFrançois Tigeot #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 7081c59a5c48SFrançois Tigeot #endif 7082c59a5c48SFrançois Tigeot 7083c59a5c48SFrançois Tigeot 7084c59a5c48SFrançois Tigeot #define ATOM_FLAG_SET 0x20 7085c59a5c48SFrançois Tigeot #define ATOM_FLAG_CLEAR 0 7086c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 7087c59a5c48SFrançois Tigeot #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 7088c59a5c48SFrançois Tigeot #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 7089c59a5c48SFrançois Tigeot #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 7090c59a5c48SFrançois Tigeot #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 7091c59a5c48SFrançois Tigeot 7092c59a5c48SFrançois Tigeot #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 7093c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 7094c59a5c48SFrançois Tigeot 7095c59a5c48SFrançois Tigeot #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 7096c59a5c48SFrançois Tigeot #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 7097c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 7098c59a5c48SFrançois Tigeot 7099c59a5c48SFrançois Tigeot #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 7100c59a5c48SFrançois Tigeot #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 7101c59a5c48SFrançois Tigeot #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 7102c59a5c48SFrançois Tigeot 7103c59a5c48SFrançois Tigeot #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 7104c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 7105c59a5c48SFrançois Tigeot 7106c59a5c48SFrançois Tigeot #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 7107c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 7108c59a5c48SFrançois Tigeot 7109c59a5c48SFrançois Tigeot #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 7110c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 7111c59a5c48SFrançois Tigeot 7112c59a5c48SFrançois Tigeot #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7113c59a5c48SFrançois Tigeot 7114c59a5c48SFrançois Tigeot #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7115c59a5c48SFrançois Tigeot 7116c59a5c48SFrançois Tigeot #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 7117c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 7118c59a5c48SFrançois Tigeot #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 7119c59a5c48SFrançois Tigeot #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 7120c59a5c48SFrançois Tigeot 7121c59a5c48SFrançois Tigeot /****************************************************************************/ 7122c59a5c48SFrançois Tigeot //Portion II: Definitinos only used in Driver 7123c59a5c48SFrançois Tigeot /****************************************************************************/ 7124c59a5c48SFrançois Tigeot 7125c59a5c48SFrançois Tigeot // Macros used by driver 7126c59a5c48SFrançois Tigeot 7127c59a5c48SFrançois Tigeot #ifdef __cplusplus 7128c59a5c48SFrançois Tigeot #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 7129c59a5c48SFrançois Tigeot 7130c59a5c48SFrançois Tigeot #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 7131c59a5c48SFrançois Tigeot #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 7132c59a5c48SFrançois Tigeot #else // not __cplusplus 7133c59a5c48SFrançois Tigeot #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 7134c59a5c48SFrançois Tigeot 7135c59a5c48SFrançois Tigeot #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 7136c59a5c48SFrançois Tigeot #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 7137c59a5c48SFrançois Tigeot #endif // __cplusplus 7138c59a5c48SFrançois Tigeot 7139c59a5c48SFrançois Tigeot #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 7140c59a5c48SFrançois Tigeot #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 7141c59a5c48SFrançois Tigeot 7142c59a5c48SFrançois Tigeot /****************************************************************************/ 7143c59a5c48SFrançois Tigeot //Portion III: Definitinos only used in VBIOS 7144c59a5c48SFrançois Tigeot /****************************************************************************/ 7145c59a5c48SFrançois Tigeot #define ATOM_DAC_SRC 0x80 7146c59a5c48SFrançois Tigeot #define ATOM_SRC_DAC1 0 7147c59a5c48SFrançois Tigeot #define ATOM_SRC_DAC2 0x80 7148c59a5c48SFrançois Tigeot 7149c59a5c48SFrançois Tigeot 7150c59a5c48SFrançois Tigeot 7151c59a5c48SFrançois Tigeot typedef struct _MEMORY_PLLINIT_PARAMETERS 7152c59a5c48SFrançois Tigeot { 7153c59a5c48SFrançois Tigeot ULONG ulTargetMemoryClock; //In 10Khz unit 7154c59a5c48SFrançois Tigeot UCHAR ucAction; //not define yet 7155c59a5c48SFrançois Tigeot UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 7156c59a5c48SFrançois Tigeot UCHAR ucFbDiv; //FB value 7157c59a5c48SFrançois Tigeot UCHAR ucPostDiv; //Post div 7158c59a5c48SFrançois Tigeot }MEMORY_PLLINIT_PARAMETERS; 7159c59a5c48SFrançois Tigeot 7160c59a5c48SFrançois Tigeot #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 7161c59a5c48SFrançois Tigeot 7162c59a5c48SFrançois Tigeot 7163c59a5c48SFrançois Tigeot #define GPIO_PIN_WRITE 0x01 7164c59a5c48SFrançois Tigeot #define GPIO_PIN_READ 0x00 7165c59a5c48SFrançois Tigeot 7166c59a5c48SFrançois Tigeot typedef struct _GPIO_PIN_CONTROL_PARAMETERS 7167c59a5c48SFrançois Tigeot { 7168c59a5c48SFrançois Tigeot UCHAR ucGPIO_ID; //return value, read from GPIO pins 7169c59a5c48SFrançois Tigeot UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 7170c59a5c48SFrançois Tigeot UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 7171c59a5c48SFrançois Tigeot UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 7172c59a5c48SFrançois Tigeot }GPIO_PIN_CONTROL_PARAMETERS; 7173c59a5c48SFrançois Tigeot 7174c59a5c48SFrançois Tigeot typedef struct _ENABLE_SCALER_PARAMETERS 7175c59a5c48SFrançois Tigeot { 7176c59a5c48SFrançois Tigeot UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 7177c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 7178c59a5c48SFrançois Tigeot UCHAR ucTVStandard; // 7179c59a5c48SFrançois Tigeot UCHAR ucPadding[1]; 7180c59a5c48SFrançois Tigeot }ENABLE_SCALER_PARAMETERS; 7181c59a5c48SFrançois Tigeot #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 7182c59a5c48SFrançois Tigeot 7183c59a5c48SFrançois Tigeot //ucEnable: 7184c59a5c48SFrançois Tigeot #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 7185c59a5c48SFrançois Tigeot #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 7186c59a5c48SFrançois Tigeot #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 7187c59a5c48SFrançois Tigeot #define SCALER_ENABLE_MULTITAP_MODE 3 7188c59a5c48SFrançois Tigeot 7189c59a5c48SFrançois Tigeot typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 7190c59a5c48SFrançois Tigeot { 7191c59a5c48SFrançois Tigeot ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 7192c59a5c48SFrançois Tigeot UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 7193c59a5c48SFrançois Tigeot UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 7194c59a5c48SFrançois Tigeot UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 7195c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7196c59a5c48SFrançois Tigeot }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 7197c59a5c48SFrançois Tigeot 7198c59a5c48SFrançois Tigeot typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 7199c59a5c48SFrançois Tigeot { 7200c59a5c48SFrançois Tigeot ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 7201c59a5c48SFrançois Tigeot ENABLE_CRTC_PARAMETERS sReserved; 7202c59a5c48SFrançois Tigeot }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 7203c59a5c48SFrançois Tigeot 7204c59a5c48SFrançois Tigeot typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 7205c59a5c48SFrançois Tigeot { 7206c59a5c48SFrançois Tigeot USHORT usHight; // Image Hight 7207c59a5c48SFrançois Tigeot USHORT usWidth; // Image Width 7208c59a5c48SFrançois Tigeot UCHAR ucSurface; // Surface 1 or 2 7209c59a5c48SFrançois Tigeot UCHAR ucPadding[3]; 7210c59a5c48SFrançois Tigeot }ENABLE_GRAPH_SURFACE_PARAMETERS; 7211c59a5c48SFrançois Tigeot 7212c59a5c48SFrançois Tigeot typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 7213c59a5c48SFrançois Tigeot { 7214c59a5c48SFrançois Tigeot USHORT usHight; // Image Hight 7215c59a5c48SFrançois Tigeot USHORT usWidth; // Image Width 7216c59a5c48SFrançois Tigeot UCHAR ucSurface; // Surface 1 or 2 7217c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7218c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 7219c59a5c48SFrançois Tigeot }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 7220c59a5c48SFrançois Tigeot 7221c59a5c48SFrançois Tigeot typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 7222c59a5c48SFrançois Tigeot { 7223c59a5c48SFrançois Tigeot USHORT usHight; // Image Hight 7224c59a5c48SFrançois Tigeot USHORT usWidth; // Image Width 7225c59a5c48SFrançois Tigeot UCHAR ucSurface; // Surface 1 or 2 7226c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7227c59a5c48SFrançois Tigeot USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 7228c59a5c48SFrançois Tigeot }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 7229c59a5c48SFrançois Tigeot 7230c59a5c48SFrançois Tigeot typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 7231c59a5c48SFrançois Tigeot { 7232c59a5c48SFrançois Tigeot USHORT usHight; // Image Hight 7233c59a5c48SFrançois Tigeot USHORT usWidth; // Image Width 7234c59a5c48SFrançois Tigeot USHORT usGraphPitch; 7235c59a5c48SFrançois Tigeot UCHAR ucColorDepth; 7236c59a5c48SFrançois Tigeot UCHAR ucPixelFormat; 7237c59a5c48SFrançois Tigeot UCHAR ucSurface; // Surface 1 or 2 7238c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7239c59a5c48SFrançois Tigeot UCHAR ucModeType; 7240c59a5c48SFrançois Tigeot UCHAR ucReserved; 7241c59a5c48SFrançois Tigeot }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 7242c59a5c48SFrançois Tigeot 7243c59a5c48SFrançois Tigeot // ucEnable 7244c59a5c48SFrançois Tigeot #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 7245c59a5c48SFrançois Tigeot #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 7246c59a5c48SFrançois Tigeot 7247c59a5c48SFrançois Tigeot typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 7248c59a5c48SFrançois Tigeot { 7249c59a5c48SFrançois Tigeot ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 7250c59a5c48SFrançois Tigeot ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 7251c59a5c48SFrançois Tigeot }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 7252c59a5c48SFrançois Tigeot 7253c59a5c48SFrançois Tigeot typedef struct _MEMORY_CLEAN_UP_PARAMETERS 7254c59a5c48SFrançois Tigeot { 7255c59a5c48SFrançois Tigeot USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 7256c59a5c48SFrançois Tigeot USHORT usMemorySize; //8Kb blocks aligned 7257c59a5c48SFrançois Tigeot }MEMORY_CLEAN_UP_PARAMETERS; 7258c59a5c48SFrançois Tigeot 7259c59a5c48SFrançois Tigeot #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 7260c59a5c48SFrançois Tigeot 7261c59a5c48SFrançois Tigeot typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 7262c59a5c48SFrançois Tigeot { 7263c59a5c48SFrançois Tigeot USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7264c59a5c48SFrançois Tigeot USHORT usY_Size; 7265c59a5c48SFrançois Tigeot }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 7266c59a5c48SFrançois Tigeot 7267c59a5c48SFrançois Tigeot typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 7268c59a5c48SFrançois Tigeot { 7269c59a5c48SFrançois Tigeot union{ 7270c59a5c48SFrançois Tigeot USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7271c59a5c48SFrançois Tigeot USHORT usSurface; 7272c59a5c48SFrançois Tigeot }; 7273c59a5c48SFrançois Tigeot USHORT usY_Size; 7274c59a5c48SFrançois Tigeot USHORT usDispXStart; 7275c59a5c48SFrançois Tigeot USHORT usDispYStart; 7276c59a5c48SFrançois Tigeot }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 7277c59a5c48SFrançois Tigeot 7278c59a5c48SFrançois Tigeot 7279c59a5c48SFrançois Tigeot typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 7280c59a5c48SFrançois Tigeot { 7281c59a5c48SFrançois Tigeot UCHAR ucLutId; 7282c59a5c48SFrançois Tigeot UCHAR ucAction; 7283c59a5c48SFrançois Tigeot USHORT usLutStartIndex; 7284c59a5c48SFrançois Tigeot USHORT usLutLength; 7285c59a5c48SFrançois Tigeot USHORT usLutOffsetInVram; 7286c59a5c48SFrançois Tigeot }PALETTE_DATA_CONTROL_PARAMETERS_V3; 7287c59a5c48SFrançois Tigeot 7288c59a5c48SFrançois Tigeot // ucAction: 7289c59a5c48SFrançois Tigeot #define PALETTE_DATA_AUTO_FILL 1 7290c59a5c48SFrançois Tigeot #define PALETTE_DATA_READ 2 7291c59a5c48SFrançois Tigeot #define PALETTE_DATA_WRITE 3 7292c59a5c48SFrançois Tigeot 7293c59a5c48SFrançois Tigeot 7294c59a5c48SFrançois Tigeot typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 7295c59a5c48SFrançois Tigeot { 7296c59a5c48SFrançois Tigeot UCHAR ucInterruptId; 7297c59a5c48SFrançois Tigeot UCHAR ucServiceId; 7298c59a5c48SFrançois Tigeot UCHAR ucStatus; 7299c59a5c48SFrançois Tigeot UCHAR ucReserved; 7300c59a5c48SFrançois Tigeot }INTERRUPT_SERVICE_PARAMETER_V2; 7301c59a5c48SFrançois Tigeot 7302c59a5c48SFrançois Tigeot // ucInterruptId 7303c59a5c48SFrançois Tigeot #define HDP1_INTERRUPT_ID 1 7304c59a5c48SFrançois Tigeot #define HDP2_INTERRUPT_ID 2 7305c59a5c48SFrançois Tigeot #define HDP3_INTERRUPT_ID 3 7306c59a5c48SFrançois Tigeot #define HDP4_INTERRUPT_ID 4 7307c59a5c48SFrançois Tigeot #define HDP5_INTERRUPT_ID 5 7308c59a5c48SFrançois Tigeot #define HDP6_INTERRUPT_ID 6 7309c59a5c48SFrançois Tigeot #define SW_INTERRUPT_ID 11 7310c59a5c48SFrançois Tigeot 7311c59a5c48SFrançois Tigeot // ucAction 7312c59a5c48SFrançois Tigeot #define INTERRUPT_SERVICE_GEN_SW_INT 1 7313c59a5c48SFrançois Tigeot #define INTERRUPT_SERVICE_GET_STATUS 2 7314c59a5c48SFrançois Tigeot 7315c59a5c48SFrançois Tigeot // ucStatus 7316c59a5c48SFrançois Tigeot #define INTERRUPT_STATUS__INT_TRIGGER 1 7317c59a5c48SFrançois Tigeot #define INTERRUPT_STATUS__HPD_HIGH 2 7318c59a5c48SFrançois Tigeot 7319c59a5c48SFrançois Tigeot typedef struct _EFUSE_INPUT_PARAMETER 7320c59a5c48SFrançois Tigeot { 7321c59a5c48SFrançois Tigeot USHORT usEfuseIndex; 7322c59a5c48SFrançois Tigeot UCHAR ucBitShift; 7323c59a5c48SFrançois Tigeot UCHAR ucBitLength; 7324c59a5c48SFrançois Tigeot }EFUSE_INPUT_PARAMETER; 7325c59a5c48SFrançois Tigeot 7326c59a5c48SFrançois Tigeot // ReadEfuseValue command table input/output parameter 7327c59a5c48SFrançois Tigeot typedef union _READ_EFUSE_VALUE_PARAMETER 7328c59a5c48SFrançois Tigeot { 7329c59a5c48SFrançois Tigeot EFUSE_INPUT_PARAMETER sEfuse; 7330c59a5c48SFrançois Tigeot ULONG ulEfuseValue; 7331c59a5c48SFrançois Tigeot }READ_EFUSE_VALUE_PARAMETER; 7332c59a5c48SFrançois Tigeot 7333c59a5c48SFrançois Tigeot typedef struct _INDIRECT_IO_ACCESS 7334c59a5c48SFrançois Tigeot { 7335c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7336c59a5c48SFrançois Tigeot UCHAR IOAccessSequence[256]; 7337c59a5c48SFrançois Tigeot } INDIRECT_IO_ACCESS; 7338c59a5c48SFrançois Tigeot 7339c59a5c48SFrançois Tigeot #define INDIRECT_READ 0x00 7340c59a5c48SFrançois Tigeot #define INDIRECT_WRITE 0x80 7341c59a5c48SFrançois Tigeot 7342c59a5c48SFrançois Tigeot #define INDIRECT_IO_MM 0 7343c59a5c48SFrançois Tigeot #define INDIRECT_IO_PLL 1 7344c59a5c48SFrançois Tigeot #define INDIRECT_IO_MC 2 7345c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIE 3 7346c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIEP 4 7347c59a5c48SFrançois Tigeot #define INDIRECT_IO_NBMISC 5 7348c59a5c48SFrançois Tigeot #define INDIRECT_IO_SMU 5 7349c59a5c48SFrançois Tigeot 7350c59a5c48SFrançois Tigeot #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 7351c59a5c48SFrançois Tigeot #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 7352c59a5c48SFrançois Tigeot #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 7353c59a5c48SFrançois Tigeot #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 7354c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 7355c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 7356c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 7357c59a5c48SFrançois Tigeot #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 7358c59a5c48SFrançois Tigeot #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 7359c59a5c48SFrançois Tigeot #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 7360c59a5c48SFrançois Tigeot #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 7361c59a5c48SFrançois Tigeot #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 7362c59a5c48SFrançois Tigeot 7363c59a5c48SFrançois Tigeot 7364c59a5c48SFrançois Tigeot typedef struct _ATOM_OEM_INFO 7365c59a5c48SFrançois Tigeot { 7366c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7367c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7368c59a5c48SFrançois Tigeot }ATOM_OEM_INFO; 7369c59a5c48SFrançois Tigeot 7370c59a5c48SFrançois Tigeot typedef struct _ATOM_TV_MODE 7371c59a5c48SFrançois Tigeot { 7372c59a5c48SFrançois Tigeot UCHAR ucVMode_Num; //Video mode number 7373c59a5c48SFrançois Tigeot UCHAR ucTV_Mode_Num; //Internal TV mode number 7374c59a5c48SFrançois Tigeot }ATOM_TV_MODE; 7375c59a5c48SFrançois Tigeot 7376c59a5c48SFrançois Tigeot typedef struct _ATOM_BIOS_INT_TVSTD_MODE 7377c59a5c48SFrançois Tigeot { 7378c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7379c59a5c48SFrançois Tigeot USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 7380c59a5c48SFrançois Tigeot USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 7381c59a5c48SFrançois Tigeot USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 7382c59a5c48SFrançois Tigeot USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7383c59a5c48SFrançois Tigeot USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7384c59a5c48SFrançois Tigeot }ATOM_BIOS_INT_TVSTD_MODE; 7385c59a5c48SFrançois Tigeot 7386c59a5c48SFrançois Tigeot 7387c59a5c48SFrançois Tigeot typedef struct _ATOM_TV_MODE_SCALER_PTR 7388c59a5c48SFrançois Tigeot { 7389c59a5c48SFrançois Tigeot USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 7390c59a5c48SFrançois Tigeot USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 7391c59a5c48SFrançois Tigeot UCHAR ucTV_Mode_Num; 7392c59a5c48SFrançois Tigeot }ATOM_TV_MODE_SCALER_PTR; 7393c59a5c48SFrançois Tigeot 7394c59a5c48SFrançois Tigeot typedef struct _ATOM_STANDARD_VESA_TIMING 7395c59a5c48SFrançois Tigeot { 7396c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7397c59a5c48SFrançois Tigeot ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 7398c59a5c48SFrançois Tigeot }ATOM_STANDARD_VESA_TIMING; 7399c59a5c48SFrançois Tigeot 7400c59a5c48SFrançois Tigeot 7401c59a5c48SFrançois Tigeot typedef struct _ATOM_STD_FORMAT 7402c59a5c48SFrançois Tigeot { 7403c59a5c48SFrançois Tigeot USHORT usSTD_HDisp; 7404c59a5c48SFrançois Tigeot USHORT usSTD_VDisp; 7405c59a5c48SFrançois Tigeot USHORT usSTD_RefreshRate; 7406c59a5c48SFrançois Tigeot USHORT usReserved; 7407c59a5c48SFrançois Tigeot }ATOM_STD_FORMAT; 7408c59a5c48SFrançois Tigeot 7409c59a5c48SFrançois Tigeot typedef struct _ATOM_VESA_TO_EXTENDED_MODE 7410c59a5c48SFrançois Tigeot { 7411c59a5c48SFrançois Tigeot USHORT usVESA_ModeNumber; 7412c59a5c48SFrançois Tigeot USHORT usExtendedModeNumber; 7413c59a5c48SFrançois Tigeot }ATOM_VESA_TO_EXTENDED_MODE; 7414c59a5c48SFrançois Tigeot 7415c59a5c48SFrançois Tigeot typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 7416c59a5c48SFrançois Tigeot { 7417c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7418c59a5c48SFrançois Tigeot ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 7419c59a5c48SFrançois Tigeot }ATOM_VESA_TO_INTENAL_MODE_LUT; 7420c59a5c48SFrançois Tigeot 7421c59a5c48SFrançois Tigeot /*************** ATOM Memory Related Data Structure ***********************/ 7422c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 7423c59a5c48SFrançois Tigeot UCHAR ucMemoryType; 7424c59a5c48SFrançois Tigeot UCHAR ucMemoryVendor; 7425c59a5c48SFrançois Tigeot UCHAR ucAdjMCId; 7426c59a5c48SFrançois Tigeot UCHAR ucDynClkId; 7427c59a5c48SFrançois Tigeot ULONG ulDllResetClkRange; 7428c59a5c48SFrançois Tigeot }ATOM_MEMORY_VENDOR_BLOCK; 7429c59a5c48SFrançois Tigeot 7430c59a5c48SFrançois Tigeot 7431c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 7432c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 7433c59a5c48SFrançois Tigeot ULONG ucMemBlkId:8; 7434c59a5c48SFrançois Tigeot ULONG ulMemClockRange:24; 7435c59a5c48SFrançois Tigeot #else 7436c59a5c48SFrançois Tigeot ULONG ulMemClockRange:24; 7437c59a5c48SFrançois Tigeot ULONG ucMemBlkId:8; 7438c59a5c48SFrançois Tigeot #endif 7439c59a5c48SFrançois Tigeot }ATOM_MEMORY_SETTING_ID_CONFIG; 7440c59a5c48SFrançois Tigeot 7441c59a5c48SFrançois Tigeot typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 7442c59a5c48SFrançois Tigeot { 7443c59a5c48SFrançois Tigeot ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 7444c59a5c48SFrançois Tigeot ULONG ulAccess; 7445c59a5c48SFrançois Tigeot }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 7446c59a5c48SFrançois Tigeot 7447c59a5c48SFrançois Tigeot 7448c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 7449c59a5c48SFrançois Tigeot ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 7450c59a5c48SFrançois Tigeot ULONG aulMemData[1]; 7451c59a5c48SFrançois Tigeot }ATOM_MEMORY_SETTING_DATA_BLOCK; 7452c59a5c48SFrançois Tigeot 7453c59a5c48SFrançois Tigeot 7454c59a5c48SFrançois Tigeot typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 7455c59a5c48SFrançois Tigeot USHORT usRegIndex; // MC register index 7456c59a5c48SFrançois Tigeot UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 7457c59a5c48SFrançois Tigeot }ATOM_INIT_REG_INDEX_FORMAT; 7458c59a5c48SFrançois Tigeot 7459c59a5c48SFrançois Tigeot 7460c59a5c48SFrançois Tigeot typedef struct _ATOM_INIT_REG_BLOCK{ 7461c59a5c48SFrançois Tigeot USHORT usRegIndexTblSize; //size of asRegIndexBuf 7462c59a5c48SFrançois Tigeot USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 7463c59a5c48SFrançois Tigeot ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 7464c59a5c48SFrançois Tigeot ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 7465c59a5c48SFrançois Tigeot }ATOM_INIT_REG_BLOCK; 7466c59a5c48SFrançois Tigeot 7467c59a5c48SFrançois Tigeot #define END_OF_REG_INDEX_BLOCK 0x0ffff 7468c59a5c48SFrançois Tigeot #define END_OF_REG_DATA_BLOCK 0x00000000 7469c59a5c48SFrançois Tigeot #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 7470c59a5c48SFrançois Tigeot #define CLOCK_RANGE_HIGHEST 0x00ffffff 7471c59a5c48SFrançois Tigeot 7472c59a5c48SFrançois Tigeot #define VALUE_DWORD SIZEOF ULONG 7473c59a5c48SFrançois Tigeot #define VALUE_SAME_AS_ABOVE 0 7474c59a5c48SFrançois Tigeot #define VALUE_MASK_DWORD 0x84 7475c59a5c48SFrançois Tigeot 7476c59a5c48SFrançois Tigeot #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 7477c59a5c48SFrançois Tigeot #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 7478c59a5c48SFrançois Tigeot #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 7479c59a5c48SFrançois Tigeot //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 7480c59a5c48SFrançois Tigeot #define ACCESS_PLACEHOLDER 0x80 7481c59a5c48SFrançois Tigeot 7482c59a5c48SFrançois Tigeot 7483c59a5c48SFrançois Tigeot typedef struct _ATOM_MC_INIT_PARAM_TABLE 7484c59a5c48SFrançois Tigeot { 7485c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7486c59a5c48SFrançois Tigeot USHORT usAdjustARB_SEQDataOffset; 7487c59a5c48SFrançois Tigeot USHORT usMCInitMemTypeTblOffset; 7488c59a5c48SFrançois Tigeot USHORT usMCInitCommonTblOffset; 7489c59a5c48SFrançois Tigeot USHORT usMCInitPowerDownTblOffset; 7490c59a5c48SFrançois Tigeot ULONG ulARB_SEQDataBuf[32]; 7491c59a5c48SFrançois Tigeot ATOM_INIT_REG_BLOCK asMCInitMemType; 7492c59a5c48SFrançois Tigeot ATOM_INIT_REG_BLOCK asMCInitCommon; 7493c59a5c48SFrançois Tigeot }ATOM_MC_INIT_PARAM_TABLE; 7494c59a5c48SFrançois Tigeot 7495c59a5c48SFrançois Tigeot 7496c59a5c48SFrançois Tigeot typedef struct _ATOM_REG_INIT_SETTING 7497c59a5c48SFrançois Tigeot { 7498c59a5c48SFrançois Tigeot USHORT usRegIndex; 7499c59a5c48SFrançois Tigeot ULONG ulRegValue; 7500c59a5c48SFrançois Tigeot }ATOM_REG_INIT_SETTING; 7501c59a5c48SFrançois Tigeot 7502c59a5c48SFrançois Tigeot typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 7503c59a5c48SFrançois Tigeot { 7504c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7505c59a5c48SFrançois Tigeot ULONG ulMCUcodeVersion; 7506c59a5c48SFrançois Tigeot ULONG ulMCUcodeRomStartAddr; 7507c59a5c48SFrançois Tigeot ULONG ulMCUcodeLength; 7508c59a5c48SFrançois Tigeot USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 7509c59a5c48SFrançois Tigeot USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 7510c59a5c48SFrançois Tigeot }ATOM_MC_INIT_PARAM_TABLE_V2_1; 7511c59a5c48SFrançois Tigeot 7512c59a5c48SFrançois Tigeot 7513c59a5c48SFrançois Tigeot #define _4Mx16 0x2 7514c59a5c48SFrançois Tigeot #define _4Mx32 0x3 7515c59a5c48SFrançois Tigeot #define _8Mx16 0x12 7516c59a5c48SFrançois Tigeot #define _8Mx32 0x13 7517c59a5c48SFrançois Tigeot #define _8Mx128 0x15 7518c59a5c48SFrançois Tigeot #define _16Mx16 0x22 7519c59a5c48SFrançois Tigeot #define _16Mx32 0x23 7520c59a5c48SFrançois Tigeot #define _16Mx128 0x25 7521c59a5c48SFrançois Tigeot #define _32Mx16 0x32 7522c59a5c48SFrançois Tigeot #define _32Mx32 0x33 7523c59a5c48SFrançois Tigeot #define _32Mx128 0x35 7524c59a5c48SFrançois Tigeot #define _64Mx8 0x41 7525c59a5c48SFrançois Tigeot #define _64Mx16 0x42 7526d78d3a22SFrançois Tigeot #define _64Mx32 0x43 7527d78d3a22SFrançois Tigeot #define _64Mx128 0x45 7528c59a5c48SFrançois Tigeot #define _128Mx8 0x51 7529c59a5c48SFrançois Tigeot #define _128Mx16 0x52 7530c59a5c48SFrançois Tigeot #define _128Mx32 0x53 7531c59a5c48SFrançois Tigeot #define _256Mx8 0x61 7532c59a5c48SFrançois Tigeot #define _256Mx16 0x62 7533d78d3a22SFrançois Tigeot #define _256Mx32 0x63 7534c59a5c48SFrançois Tigeot #define _512Mx8 0x71 7535d78d3a22SFrançois Tigeot #define _512Mx16 0x72 7536c59a5c48SFrançois Tigeot 7537c59a5c48SFrançois Tigeot 7538c59a5c48SFrançois Tigeot #define SAMSUNG 0x1 7539c59a5c48SFrançois Tigeot #define INFINEON 0x2 7540c59a5c48SFrançois Tigeot #define ELPIDA 0x3 7541c59a5c48SFrançois Tigeot #define ETRON 0x4 7542c59a5c48SFrançois Tigeot #define NANYA 0x5 7543c59a5c48SFrançois Tigeot #define HYNIX 0x6 7544c59a5c48SFrançois Tigeot #define MOSEL 0x7 7545c59a5c48SFrançois Tigeot #define WINBOND 0x8 7546c59a5c48SFrançois Tigeot #define ESMT 0x9 7547c59a5c48SFrançois Tigeot #define MICRON 0xF 7548c59a5c48SFrançois Tigeot 7549c59a5c48SFrançois Tigeot #define QIMONDA INFINEON 7550c59a5c48SFrançois Tigeot #define PROMOS MOSEL 7551c59a5c48SFrançois Tigeot #define KRETON INFINEON 7552c59a5c48SFrançois Tigeot #define ELIXIR NANYA 7553c59a5c48SFrançois Tigeot #define MEZZA ELPIDA 7554c59a5c48SFrançois Tigeot 7555c59a5c48SFrançois Tigeot 7556c59a5c48SFrançois Tigeot /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 7557c59a5c48SFrançois Tigeot 7558c59a5c48SFrançois Tigeot #define UCODE_ROM_START_ADDRESS 0x1b800 7559c59a5c48SFrançois Tigeot #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 7560c59a5c48SFrançois Tigeot 7561c59a5c48SFrançois Tigeot //uCode block header for reference 7562c59a5c48SFrançois Tigeot 7563c59a5c48SFrançois Tigeot typedef struct _MCuCodeHeader 7564c59a5c48SFrançois Tigeot { 7565c59a5c48SFrançois Tigeot ULONG ulSignature; 7566c59a5c48SFrançois Tigeot UCHAR ucRevision; 7567c59a5c48SFrançois Tigeot UCHAR ucChecksum; 7568c59a5c48SFrançois Tigeot UCHAR ucReserved1; 7569c59a5c48SFrançois Tigeot UCHAR ucReserved2; 7570c59a5c48SFrançois Tigeot USHORT usParametersLength; 7571c59a5c48SFrançois Tigeot USHORT usUCodeLength; 7572c59a5c48SFrançois Tigeot USHORT usReserved1; 7573c59a5c48SFrançois Tigeot USHORT usReserved2; 7574c59a5c48SFrançois Tigeot } MCuCodeHeader; 7575c59a5c48SFrançois Tigeot 7576c59a5c48SFrançois Tigeot ////////////////////////////////////////////////////////////////////////////////// 7577c59a5c48SFrançois Tigeot 7578c59a5c48SFrançois Tigeot #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 7579c59a5c48SFrançois Tigeot 7580c59a5c48SFrançois Tigeot #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 7581c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V1 7582c59a5c48SFrançois Tigeot { 7583c59a5c48SFrançois Tigeot ULONG ulReserved; 7584c59a5c48SFrançois Tigeot USHORT usEMRSValue; 7585c59a5c48SFrançois Tigeot USHORT usMRSValue; 7586c59a5c48SFrançois Tigeot USHORT usReserved; 7587c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7588c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 7589c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 7590c59a5c48SFrançois Tigeot UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7591c59a5c48SFrançois Tigeot UCHAR ucRow; // Number of Row,in power of 2; 7592c59a5c48SFrançois Tigeot UCHAR ucColumn; // Number of Column,in power of 2; 7593c59a5c48SFrançois Tigeot UCHAR ucBank; // Nunber of Bank; 7594c59a5c48SFrançois Tigeot UCHAR ucRank; // Number of Rank, in power of 2 7595c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of channel; 7596c59a5c48SFrançois Tigeot UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7597c59a5c48SFrançois Tigeot UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7598c59a5c48SFrançois Tigeot UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7599c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 7600c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V1; 7601c59a5c48SFrançois Tigeot 7602c59a5c48SFrançois Tigeot 7603c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V2 7604c59a5c48SFrançois Tigeot { 7605c59a5c48SFrançois Tigeot ULONG ulReserved; 7606c59a5c48SFrançois Tigeot ULONG ulFlags; // To enable/disable functionalities based on memory type 7607c59a5c48SFrançois Tigeot ULONG ulEngineClock; // Override of default engine clock for particular memory type 7608c59a5c48SFrançois Tigeot ULONG ulMemoryClock; // Override of default memory clock for particular memory type 7609c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7610c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7611c59a5c48SFrançois Tigeot USHORT usEMRSValue; 7612c59a5c48SFrançois Tigeot USHORT usMRSValue; 7613c59a5c48SFrançois Tigeot USHORT usReserved; 7614c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7615c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7616c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7617c59a5c48SFrançois Tigeot UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7618c59a5c48SFrançois Tigeot UCHAR ucRow; // Number of Row,in power of 2; 7619c59a5c48SFrançois Tigeot UCHAR ucColumn; // Number of Column,in power of 2; 7620c59a5c48SFrançois Tigeot UCHAR ucBank; // Nunber of Bank; 7621c59a5c48SFrançois Tigeot UCHAR ucRank; // Number of Rank, in power of 2 7622c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of channel; 7623c59a5c48SFrançois Tigeot UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7624c59a5c48SFrançois Tigeot UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7625c59a5c48SFrançois Tigeot UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7626c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; 7627c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 7628c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V2; 7629c59a5c48SFrançois Tigeot 7630c59a5c48SFrançois Tigeot 7631c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_TIMING_FORMAT 7632c59a5c48SFrançois Tigeot { 7633c59a5c48SFrançois Tigeot ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7634c59a5c48SFrançois Tigeot union{ 7635c59a5c48SFrançois Tigeot USHORT usMRS; // mode register 7636c59a5c48SFrançois Tigeot USHORT usDDR3_MR0; 7637c59a5c48SFrançois Tigeot }; 7638c59a5c48SFrançois Tigeot union{ 7639c59a5c48SFrançois Tigeot USHORT usEMRS; // extended mode register 7640c59a5c48SFrançois Tigeot USHORT usDDR3_MR1; 7641c59a5c48SFrançois Tigeot }; 7642c59a5c48SFrançois Tigeot UCHAR ucCL; // CAS latency 7643c59a5c48SFrançois Tigeot UCHAR ucWL; // WRITE Latency 7644c59a5c48SFrançois Tigeot UCHAR uctRAS; // tRAS 7645c59a5c48SFrançois Tigeot UCHAR uctRC; // tRC 7646c59a5c48SFrançois Tigeot UCHAR uctRFC; // tRFC 7647c59a5c48SFrançois Tigeot UCHAR uctRCDR; // tRCDR 7648c59a5c48SFrançois Tigeot UCHAR uctRCDW; // tRCDW 7649c59a5c48SFrançois Tigeot UCHAR uctRP; // tRP 7650c59a5c48SFrançois Tigeot UCHAR uctRRD; // tRRD 7651c59a5c48SFrançois Tigeot UCHAR uctWR; // tWR 7652c59a5c48SFrançois Tigeot UCHAR uctWTR; // tWTR 7653c59a5c48SFrançois Tigeot UCHAR uctPDIX; // tPDIX 7654c59a5c48SFrançois Tigeot UCHAR uctFAW; // tFAW 7655c59a5c48SFrançois Tigeot UCHAR uctAOND; // tAOND 7656c59a5c48SFrançois Tigeot union 7657c59a5c48SFrançois Tigeot { 7658c59a5c48SFrançois Tigeot struct { 7659c59a5c48SFrançois Tigeot UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7660c59a5c48SFrançois Tigeot UCHAR ucReserved; 7661c59a5c48SFrançois Tigeot }; 7662c59a5c48SFrançois Tigeot USHORT usDDR3_MR2; 7663c59a5c48SFrançois Tigeot }; 7664c59a5c48SFrançois Tigeot }ATOM_MEMORY_TIMING_FORMAT; 7665c59a5c48SFrançois Tigeot 7666c59a5c48SFrançois Tigeot 7667c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 7668c59a5c48SFrançois Tigeot { 7669c59a5c48SFrançois Tigeot ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7670c59a5c48SFrançois Tigeot USHORT usMRS; // mode register 7671c59a5c48SFrançois Tigeot USHORT usEMRS; // extended mode register 7672c59a5c48SFrançois Tigeot UCHAR ucCL; // CAS latency 7673c59a5c48SFrançois Tigeot UCHAR ucWL; // WRITE Latency 7674c59a5c48SFrançois Tigeot UCHAR uctRAS; // tRAS 7675c59a5c48SFrançois Tigeot UCHAR uctRC; // tRC 7676c59a5c48SFrançois Tigeot UCHAR uctRFC; // tRFC 7677c59a5c48SFrançois Tigeot UCHAR uctRCDR; // tRCDR 7678c59a5c48SFrançois Tigeot UCHAR uctRCDW; // tRCDW 7679c59a5c48SFrançois Tigeot UCHAR uctRP; // tRP 7680c59a5c48SFrançois Tigeot UCHAR uctRRD; // tRRD 7681c59a5c48SFrançois Tigeot UCHAR uctWR; // tWR 7682c59a5c48SFrançois Tigeot UCHAR uctWTR; // tWTR 7683c59a5c48SFrançois Tigeot UCHAR uctPDIX; // tPDIX 7684c59a5c48SFrançois Tigeot UCHAR uctFAW; // tFAW 7685c59a5c48SFrançois Tigeot UCHAR uctAOND; // tAOND 7686c59a5c48SFrançois Tigeot UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7687c59a5c48SFrançois Tigeot ////////////////////////////////////GDDR parameters/////////////////////////////////// 7688c59a5c48SFrançois Tigeot UCHAR uctCCDL; // 7689c59a5c48SFrançois Tigeot UCHAR uctCRCRL; // 7690c59a5c48SFrançois Tigeot UCHAR uctCRCWL; // 7691c59a5c48SFrançois Tigeot UCHAR uctCKE; // 7692c59a5c48SFrançois Tigeot UCHAR uctCKRSE; // 7693c59a5c48SFrançois Tigeot UCHAR uctCKRSX; // 7694c59a5c48SFrançois Tigeot UCHAR uctFAW32; // 7695c59a5c48SFrançois Tigeot UCHAR ucMR5lo; // 7696c59a5c48SFrançois Tigeot UCHAR ucMR5hi; // 7697c59a5c48SFrançois Tigeot UCHAR ucTerminator; 7698c59a5c48SFrançois Tigeot }ATOM_MEMORY_TIMING_FORMAT_V1; 7699c59a5c48SFrançois Tigeot 7700c59a5c48SFrançois Tigeot 7701c59a5c48SFrançois Tigeot 7702c59a5c48SFrançois Tigeot 7703c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 7704c59a5c48SFrançois Tigeot { 7705c59a5c48SFrançois Tigeot ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7706c59a5c48SFrançois Tigeot USHORT usMRS; // mode register 7707c59a5c48SFrançois Tigeot USHORT usEMRS; // extended mode register 7708c59a5c48SFrançois Tigeot UCHAR ucCL; // CAS latency 7709c59a5c48SFrançois Tigeot UCHAR ucWL; // WRITE Latency 7710c59a5c48SFrançois Tigeot UCHAR uctRAS; // tRAS 7711c59a5c48SFrançois Tigeot UCHAR uctRC; // tRC 7712c59a5c48SFrançois Tigeot UCHAR uctRFC; // tRFC 7713c59a5c48SFrançois Tigeot UCHAR uctRCDR; // tRCDR 7714c59a5c48SFrançois Tigeot UCHAR uctRCDW; // tRCDW 7715c59a5c48SFrançois Tigeot UCHAR uctRP; // tRP 7716c59a5c48SFrançois Tigeot UCHAR uctRRD; // tRRD 7717c59a5c48SFrançois Tigeot UCHAR uctWR; // tWR 7718c59a5c48SFrançois Tigeot UCHAR uctWTR; // tWTR 7719c59a5c48SFrançois Tigeot UCHAR uctPDIX; // tPDIX 7720c59a5c48SFrançois Tigeot UCHAR uctFAW; // tFAW 7721c59a5c48SFrançois Tigeot UCHAR uctAOND; // tAOND 7722c59a5c48SFrançois Tigeot UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7723c59a5c48SFrançois Tigeot ////////////////////////////////////GDDR parameters/////////////////////////////////// 7724c59a5c48SFrançois Tigeot UCHAR uctCCDL; // 7725c59a5c48SFrançois Tigeot UCHAR uctCRCRL; // 7726c59a5c48SFrançois Tigeot UCHAR uctCRCWL; // 7727c59a5c48SFrançois Tigeot UCHAR uctCKE; // 7728c59a5c48SFrançois Tigeot UCHAR uctCKRSE; // 7729c59a5c48SFrançois Tigeot UCHAR uctCKRSX; // 7730c59a5c48SFrançois Tigeot UCHAR uctFAW32; // 7731c59a5c48SFrançois Tigeot UCHAR ucMR4lo; // 7732c59a5c48SFrançois Tigeot UCHAR ucMR4hi; // 7733c59a5c48SFrançois Tigeot UCHAR ucMR5lo; // 7734c59a5c48SFrançois Tigeot UCHAR ucMR5hi; // 7735c59a5c48SFrançois Tigeot UCHAR ucTerminator; 7736c59a5c48SFrançois Tigeot UCHAR ucReserved; 7737c59a5c48SFrançois Tigeot }ATOM_MEMORY_TIMING_FORMAT_V2; 7738c59a5c48SFrançois Tigeot 7739c59a5c48SFrançois Tigeot 7740c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_FORMAT 7741c59a5c48SFrançois Tigeot { 7742c59a5c48SFrançois Tigeot ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7743c59a5c48SFrançois Tigeot union{ 7744c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7745c59a5c48SFrançois Tigeot USHORT usDDR3_Reserved; // Not used for DDR3 memory 7746c59a5c48SFrançois Tigeot }; 7747c59a5c48SFrançois Tigeot union{ 7748c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7749c59a5c48SFrançois Tigeot USHORT usDDR3_MR3; // Used for DDR3 memory 7750c59a5c48SFrançois Tigeot }; 7751c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7752c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7753c59a5c48SFrançois Tigeot UCHAR ucRow; // Number of Row,in power of 2; 7754c59a5c48SFrançois Tigeot UCHAR ucColumn; // Number of Column,in power of 2; 7755c59a5c48SFrançois Tigeot UCHAR ucBank; // Nunber of Bank; 7756c59a5c48SFrançois Tigeot UCHAR ucRank; // Number of Rank, in power of 2 7757c59a5c48SFrançois Tigeot UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7758c59a5c48SFrançois Tigeot UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7759c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7760c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7761c59a5c48SFrançois Tigeot UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7762c59a5c48SFrançois Tigeot UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7763c59a5c48SFrançois Tigeot ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7764c59a5c48SFrançois Tigeot }ATOM_MEMORY_FORMAT; 7765c59a5c48SFrançois Tigeot 7766c59a5c48SFrançois Tigeot 7767c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V3 7768c59a5c48SFrançois Tigeot { 7769c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7770c59a5c48SFrançois Tigeot USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7771c59a5c48SFrançois Tigeot USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7772c59a5c48SFrançois Tigeot USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7773c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7774c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7775c59a5c48SFrançois Tigeot UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7776c59a5c48SFrançois Tigeot UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7777c59a5c48SFrançois Tigeot UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7778c59a5c48SFrançois Tigeot UCHAR ucFlag; // To enable/disable functionalities based on memory type 7779c59a5c48SFrançois Tigeot ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7780c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V3; 7781c59a5c48SFrançois Tigeot 7782c59a5c48SFrançois Tigeot 7783c59a5c48SFrançois Tigeot //ATOM_VRAM_MODULE_V3.ucNPL_RT 7784c59a5c48SFrançois Tigeot #define NPL_RT_MASK 0x0f 7785c59a5c48SFrançois Tigeot #define BATTERY_ODT_MASK 0xc0 7786c59a5c48SFrançois Tigeot 7787c59a5c48SFrançois Tigeot #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7788c59a5c48SFrançois Tigeot 7789c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V4 7790c59a5c48SFrançois Tigeot { 7791c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7792c59a5c48SFrançois Tigeot USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7793c59a5c48SFrançois Tigeot USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7794c59a5c48SFrançois Tigeot // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7795c59a5c48SFrançois Tigeot USHORT usReserved; 7796c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7797c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7798c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of channels present in this module config 7799c59a5c48SFrançois Tigeot UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7800c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7801c59a5c48SFrançois Tigeot UCHAR ucFlag; // To enable/disable functionalities based on memory type 7802c59a5c48SFrançois Tigeot UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7803c59a5c48SFrançois Tigeot UCHAR ucVREFI; // board dependent parameter 7804c59a5c48SFrançois Tigeot UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7805c59a5c48SFrançois Tigeot UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7806c59a5c48SFrançois Tigeot UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7807c59a5c48SFrançois Tigeot // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7808c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 7809c59a5c48SFrançois Tigeot 7810c59a5c48SFrançois Tigeot //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7811c59a5c48SFrançois Tigeot union{ 7812c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7813c59a5c48SFrançois Tigeot USHORT usDDR3_Reserved; 7814c59a5c48SFrançois Tigeot }; 7815c59a5c48SFrançois Tigeot union{ 7816c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7817c59a5c48SFrançois Tigeot USHORT usDDR3_MR3; // Used for DDR3 memory 7818c59a5c48SFrançois Tigeot }; 7819c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7820c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7821c59a5c48SFrançois Tigeot UCHAR ucReserved2[2]; 7822c59a5c48SFrançois Tigeot ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7823c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V4; 7824c59a5c48SFrançois Tigeot 7825c59a5c48SFrançois Tigeot #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7826c59a5c48SFrançois Tigeot #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7827c59a5c48SFrançois Tigeot #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7828c59a5c48SFrançois Tigeot #define VRAM_MODULE_V4_MISC_BL8 0x4 7829c59a5c48SFrançois Tigeot #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7830c59a5c48SFrançois Tigeot 7831c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V5 7832c59a5c48SFrançois Tigeot { 7833c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7834c59a5c48SFrançois Tigeot USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7835c59a5c48SFrançois Tigeot USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7836c59a5c48SFrançois Tigeot // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7837c59a5c48SFrançois Tigeot USHORT usReserved; 7838c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7839c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7840c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of channels present in this module config 7841c59a5c48SFrançois Tigeot UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7842c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7843c59a5c48SFrançois Tigeot UCHAR ucFlag; // To enable/disable functionalities based on memory type 7844c59a5c48SFrançois Tigeot UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7845c59a5c48SFrançois Tigeot UCHAR ucVREFI; // board dependent parameter 7846c59a5c48SFrançois Tigeot UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7847c59a5c48SFrançois Tigeot UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7848c59a5c48SFrançois Tigeot UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7849c59a5c48SFrançois Tigeot // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7850c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 7851c59a5c48SFrançois Tigeot 7852c59a5c48SFrançois Tigeot //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7853c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7854c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7855c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7856c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7857c59a5c48SFrançois Tigeot UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7858c59a5c48SFrançois Tigeot UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7859c59a5c48SFrançois Tigeot ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7860c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V5; 7861c59a5c48SFrançois Tigeot 7862c59a5c48SFrançois Tigeot 7863c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V6 7864c59a5c48SFrançois Tigeot { 7865c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7866c59a5c48SFrançois Tigeot USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7867c59a5c48SFrançois Tigeot USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7868c59a5c48SFrançois Tigeot // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7869c59a5c48SFrançois Tigeot USHORT usReserved; 7870c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7871c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7872c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of channels present in this module config 7873c59a5c48SFrançois Tigeot UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7874c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7875c59a5c48SFrançois Tigeot UCHAR ucFlag; // To enable/disable functionalities based on memory type 7876c59a5c48SFrançois Tigeot UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7877c59a5c48SFrançois Tigeot UCHAR ucVREFI; // board dependent parameter 7878c59a5c48SFrançois Tigeot UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7879c59a5c48SFrançois Tigeot UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7880c59a5c48SFrançois Tigeot UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7881c59a5c48SFrançois Tigeot // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7882c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 7883c59a5c48SFrançois Tigeot 7884c59a5c48SFrançois Tigeot //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7885c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7886c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7887c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7888c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7889c59a5c48SFrançois Tigeot UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7890c59a5c48SFrançois Tigeot UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7891c59a5c48SFrançois Tigeot ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7892c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V6; 7893c59a5c48SFrançois Tigeot 7894c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V7 7895c59a5c48SFrançois Tigeot { 7896c59a5c48SFrançois Tigeot // Design Specific Values 7897c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7898c59a5c48SFrançois Tigeot USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7899c59a5c48SFrançois Tigeot USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7900c59a5c48SFrançois Tigeot USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7901c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // Current memory module ID 7902c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7903c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of mem. channels supported in this module 7904c59a5c48SFrançois Tigeot UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7905c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7906c59a5c48SFrançois Tigeot UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7907c59a5c48SFrançois Tigeot UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7908c59a5c48SFrançois Tigeot UCHAR ucVREFI; // Not used. 7909c59a5c48SFrançois Tigeot UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7910c59a5c48SFrançois Tigeot UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7911c59a5c48SFrançois Tigeot UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7912c59a5c48SFrançois Tigeot USHORT usSEQSettingOffset; 7913c59a5c48SFrançois Tigeot UCHAR ucReserved; 7914c59a5c48SFrançois Tigeot // Memory Module specific values 7915c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2/MR2 Value. 7916c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3/MR3 Value. 7917c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7918c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7919c59a5c48SFrançois Tigeot UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7920c59a5c48SFrançois Tigeot UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7921c59a5c48SFrançois Tigeot char strMemPNString[20]; // part number end with '0'. 7922c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V7; 7923c59a5c48SFrançois Tigeot 7924c59a5c48SFrançois Tigeot 7925c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_MODULE_V8 7926c59a5c48SFrançois Tigeot { 7927c59a5c48SFrançois Tigeot // Design Specific Values 7928c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7929c59a5c48SFrançois Tigeot USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7930c59a5c48SFrançois Tigeot USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7931c59a5c48SFrançois Tigeot USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7932c59a5c48SFrançois Tigeot UCHAR ucExtMemoryID; // Current memory module ID 7933c59a5c48SFrançois Tigeot UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7934c59a5c48SFrançois Tigeot UCHAR ucChannelNum; // Number of mem. channels supported in this module 7935c59a5c48SFrançois Tigeot UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7936c59a5c48SFrançois Tigeot UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7937c59a5c48SFrançois Tigeot UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7938c59a5c48SFrançois Tigeot UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7939c59a5c48SFrançois Tigeot UCHAR ucVREFI; // Not used. 7940c59a5c48SFrançois Tigeot USHORT usReserved; // Not used 7941c59a5c48SFrançois Tigeot USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7942c59a5c48SFrançois Tigeot UCHAR ucMcTunningSetId; // MC phy registers set per. 7943c59a5c48SFrançois Tigeot UCHAR ucRowNum; 7944c59a5c48SFrançois Tigeot // Memory Module specific values 7945c59a5c48SFrançois Tigeot USHORT usEMRS2Value; // EMRS2/MR2 Value. 7946c59a5c48SFrançois Tigeot USHORT usEMRS3Value; // EMRS3/MR3 Value. 7947c59a5c48SFrançois Tigeot UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7948c59a5c48SFrançois Tigeot UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7949c59a5c48SFrançois Tigeot UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7950c59a5c48SFrançois Tigeot UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7951c59a5c48SFrançois Tigeot 7952c59a5c48SFrançois Tigeot ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7953c59a5c48SFrançois Tigeot ULONG ulBankMapCfg; 7954c59a5c48SFrançois Tigeot ULONG ulReserved; 7955c59a5c48SFrançois Tigeot char strMemPNString[20]; // part number end with '0'. 7956c59a5c48SFrançois Tigeot }ATOM_VRAM_MODULE_V8; 7957c59a5c48SFrançois Tigeot 7958c59a5c48SFrançois Tigeot 7959c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_INFO_V2 7960c59a5c48SFrançois Tigeot { 7961c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7962c59a5c48SFrançois Tigeot UCHAR ucNumOfVRAMModule; 7963c59a5c48SFrançois Tigeot ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7964c59a5c48SFrançois Tigeot }ATOM_VRAM_INFO_V2; 7965c59a5c48SFrançois Tigeot 7966c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_INFO_V3 7967c59a5c48SFrançois Tigeot { 7968c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7969c59a5c48SFrançois Tigeot USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7970c59a5c48SFrançois Tigeot USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7971c59a5c48SFrançois Tigeot USHORT usRerseved; 7972c59a5c48SFrançois Tigeot UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7973c59a5c48SFrançois Tigeot UCHAR ucNumOfVRAMModule; 7974c59a5c48SFrançois Tigeot ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7975c59a5c48SFrançois Tigeot ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7976c59a5c48SFrançois Tigeot 7977c59a5c48SFrançois Tigeot }ATOM_VRAM_INFO_V3; 7978c59a5c48SFrançois Tigeot 7979c59a5c48SFrançois Tigeot #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 7980c59a5c48SFrançois Tigeot 7981c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_INFO_V4 7982c59a5c48SFrançois Tigeot { 7983c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7984c59a5c48SFrançois Tigeot USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7985c59a5c48SFrançois Tigeot USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7986c59a5c48SFrançois Tigeot USHORT usRerseved; 7987c59a5c48SFrançois Tigeot UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 7988c59a5c48SFrançois Tigeot ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 7989c59a5c48SFrançois Tigeot UCHAR ucReservde[4]; 7990c59a5c48SFrançois Tigeot UCHAR ucNumOfVRAMModule; 7991c59a5c48SFrançois Tigeot ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7992c59a5c48SFrançois Tigeot ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7993c59a5c48SFrançois Tigeot }ATOM_VRAM_INFO_V4; 7994c59a5c48SFrançois Tigeot 7995c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 7996c59a5c48SFrançois Tigeot { 7997c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 7998c59a5c48SFrançois Tigeot USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7999c59a5c48SFrançois Tigeot USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8000c59a5c48SFrançois Tigeot USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8001c59a5c48SFrançois Tigeot USHORT usReserved[3]; 8002c59a5c48SFrançois Tigeot UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8003c59a5c48SFrançois Tigeot UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8004c59a5c48SFrançois Tigeot UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8005c59a5c48SFrançois Tigeot UCHAR ucReserved; 8006c59a5c48SFrançois Tigeot ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8007c59a5c48SFrançois Tigeot }ATOM_VRAM_INFO_HEADER_V2_1; 8008c59a5c48SFrançois Tigeot 8009c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 8010c59a5c48SFrançois Tigeot { 8011c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8012c59a5c48SFrançois Tigeot USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8013c59a5c48SFrançois Tigeot USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8014c59a5c48SFrançois Tigeot USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8015c59a5c48SFrançois Tigeot USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 8016c59a5c48SFrançois Tigeot USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 8017c59a5c48SFrançois Tigeot USHORT usReserved1; 8018c59a5c48SFrançois Tigeot UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8019c59a5c48SFrançois Tigeot UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8020c59a5c48SFrançois Tigeot UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8021c59a5c48SFrançois Tigeot UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 8022c59a5c48SFrançois Tigeot ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8023c59a5c48SFrançois Tigeot }ATOM_VRAM_INFO_HEADER_V2_2; 8024c59a5c48SFrançois Tigeot 8025c59a5c48SFrançois Tigeot 8026c59a5c48SFrançois Tigeot typedef struct _ATOM_DRAM_DATA_REMAP 8027c59a5c48SFrançois Tigeot { 8028c59a5c48SFrançois Tigeot UCHAR ucByteRemapCh0; 8029c59a5c48SFrançois Tigeot UCHAR ucByteRemapCh1; 8030c59a5c48SFrançois Tigeot ULONG ulByte0BitRemapCh0; 8031c59a5c48SFrançois Tigeot ULONG ulByte1BitRemapCh0; 8032c59a5c48SFrançois Tigeot ULONG ulByte2BitRemapCh0; 8033c59a5c48SFrançois Tigeot ULONG ulByte3BitRemapCh0; 8034c59a5c48SFrançois Tigeot ULONG ulByte0BitRemapCh1; 8035c59a5c48SFrançois Tigeot ULONG ulByte1BitRemapCh1; 8036c59a5c48SFrançois Tigeot ULONG ulByte2BitRemapCh1; 8037c59a5c48SFrançois Tigeot ULONG ulByte3BitRemapCh1; 8038c59a5c48SFrançois Tigeot }ATOM_DRAM_DATA_REMAP; 8039c59a5c48SFrançois Tigeot 8040c59a5c48SFrançois Tigeot typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 8041c59a5c48SFrançois Tigeot { 8042c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8043c59a5c48SFrançois Tigeot UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 8044c59a5c48SFrançois Tigeot }ATOM_VRAM_GPIO_DETECTION_INFO; 8045c59a5c48SFrançois Tigeot 8046c59a5c48SFrançois Tigeot 8047c59a5c48SFrançois Tigeot typedef struct _ATOM_MEMORY_TRAINING_INFO 8048c59a5c48SFrançois Tigeot { 8049c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8050c59a5c48SFrançois Tigeot UCHAR ucTrainingLoop; 8051c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 8052c59a5c48SFrançois Tigeot ATOM_INIT_REG_BLOCK asMemTrainingSetting; 8053c59a5c48SFrançois Tigeot }ATOM_MEMORY_TRAINING_INFO; 8054c59a5c48SFrançois Tigeot 8055c59a5c48SFrançois Tigeot 8056d78d3a22SFrançois Tigeot typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1 8057d78d3a22SFrançois Tigeot { 8058d78d3a22SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8059d78d3a22SFrançois Tigeot ULONG ulMCUcodeVersion; 8060d78d3a22SFrançois Tigeot USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array 8061d78d3a22SFrançois Tigeot USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array 8062d78d3a22SFrançois Tigeot USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array 8063d78d3a22SFrançois Tigeot USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array. 8064d78d3a22SFrançois Tigeot }ATOM_MEMORY_TRAINING_INFO_V3_1; 8065d78d3a22SFrançois Tigeot 8066d78d3a22SFrançois Tigeot 8067c59a5c48SFrançois Tigeot typedef struct SW_I2C_CNTL_DATA_PARAMETERS 8068c59a5c48SFrançois Tigeot { 8069c59a5c48SFrançois Tigeot UCHAR ucControl; 8070c59a5c48SFrançois Tigeot UCHAR ucData; 8071c59a5c48SFrançois Tigeot UCHAR ucSatus; 8072c59a5c48SFrançois Tigeot UCHAR ucTemp; 8073c59a5c48SFrançois Tigeot } SW_I2C_CNTL_DATA_PARAMETERS; 8074c59a5c48SFrançois Tigeot 8075c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 8076c59a5c48SFrançois Tigeot 8077c59a5c48SFrançois Tigeot typedef struct _SW_I2C_IO_DATA_PARAMETERS 8078c59a5c48SFrançois Tigeot { 8079c59a5c48SFrançois Tigeot USHORT GPIO_Info; 8080c59a5c48SFrançois Tigeot UCHAR ucAct; 8081c59a5c48SFrançois Tigeot UCHAR ucData; 8082c59a5c48SFrançois Tigeot } SW_I2C_IO_DATA_PARAMETERS; 8083c59a5c48SFrançois Tigeot 8084c59a5c48SFrançois Tigeot #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 8085c59a5c48SFrançois Tigeot 8086c59a5c48SFrançois Tigeot /****************************SW I2C CNTL DEFINITIONS**********************/ 8087c59a5c48SFrançois Tigeot #define SW_I2C_IO_RESET 0 8088c59a5c48SFrançois Tigeot #define SW_I2C_IO_GET 1 8089c59a5c48SFrançois Tigeot #define SW_I2C_IO_DRIVE 2 8090c59a5c48SFrançois Tigeot #define SW_I2C_IO_SET 3 8091c59a5c48SFrançois Tigeot #define SW_I2C_IO_START 4 8092c59a5c48SFrançois Tigeot 8093c59a5c48SFrançois Tigeot #define SW_I2C_IO_CLOCK 0 8094c59a5c48SFrançois Tigeot #define SW_I2C_IO_DATA 0x80 8095c59a5c48SFrançois Tigeot 8096c59a5c48SFrançois Tigeot #define SW_I2C_IO_ZERO 0 8097c59a5c48SFrançois Tigeot #define SW_I2C_IO_ONE 0x100 8098c59a5c48SFrançois Tigeot 8099c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_READ 0 8100c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_WRITE 1 8101c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_START 2 8102c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_STOP 3 8103c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_OPEN 4 8104c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_CLOSE 5 8105c59a5c48SFrançois Tigeot #define SW_I2C_CNTL_WRITE1BIT 6 8106c59a5c48SFrançois Tigeot 8107c59a5c48SFrançois Tigeot //==============================VESA definition Portion=============================== 8108c59a5c48SFrançois Tigeot #define VESA_OEM_PRODUCT_REV '01.00' 8109c59a5c48SFrançois Tigeot #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 8110c59a5c48SFrançois Tigeot #define VESA_MODE_WIN_ATTRIBUTE 7 8111c59a5c48SFrançois Tigeot #define VESA_WIN_SIZE 64 8112c59a5c48SFrançois Tigeot 8113c59a5c48SFrançois Tigeot typedef struct _PTR_32_BIT_STRUCTURE 8114c59a5c48SFrançois Tigeot { 8115c59a5c48SFrançois Tigeot USHORT Offset16; 8116c59a5c48SFrançois Tigeot USHORT Segment16; 8117c59a5c48SFrançois Tigeot } PTR_32_BIT_STRUCTURE; 8118c59a5c48SFrançois Tigeot 8119c59a5c48SFrançois Tigeot typedef union _PTR_32_BIT_UNION 8120c59a5c48SFrançois Tigeot { 8121c59a5c48SFrançois Tigeot PTR_32_BIT_STRUCTURE SegmentOffset; 8122c59a5c48SFrançois Tigeot ULONG Ptr32_Bit; 8123c59a5c48SFrançois Tigeot } PTR_32_BIT_UNION; 8124c59a5c48SFrançois Tigeot 8125c59a5c48SFrançois Tigeot typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 8126c59a5c48SFrançois Tigeot { 8127c59a5c48SFrançois Tigeot UCHAR VbeSignature[4]; 8128c59a5c48SFrançois Tigeot USHORT VbeVersion; 8129c59a5c48SFrançois Tigeot PTR_32_BIT_UNION OemStringPtr; 8130c59a5c48SFrançois Tigeot UCHAR Capabilities[4]; 8131c59a5c48SFrançois Tigeot PTR_32_BIT_UNION VideoModePtr; 8132c59a5c48SFrançois Tigeot USHORT TotalMemory; 8133c59a5c48SFrançois Tigeot } VBE_1_2_INFO_BLOCK_UPDATABLE; 8134c59a5c48SFrançois Tigeot 8135c59a5c48SFrançois Tigeot 8136c59a5c48SFrançois Tigeot typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 8137c59a5c48SFrançois Tigeot { 8138c59a5c48SFrançois Tigeot VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 8139c59a5c48SFrançois Tigeot USHORT OemSoftRev; 8140c59a5c48SFrançois Tigeot PTR_32_BIT_UNION OemVendorNamePtr; 8141c59a5c48SFrançois Tigeot PTR_32_BIT_UNION OemProductNamePtr; 8142c59a5c48SFrançois Tigeot PTR_32_BIT_UNION OemProductRevPtr; 8143c59a5c48SFrançois Tigeot } VBE_2_0_INFO_BLOCK_UPDATABLE; 8144c59a5c48SFrançois Tigeot 8145c59a5c48SFrançois Tigeot typedef union _VBE_VERSION_UNION 8146c59a5c48SFrançois Tigeot { 8147c59a5c48SFrançois Tigeot VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 8148c59a5c48SFrançois Tigeot VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 8149c59a5c48SFrançois Tigeot } VBE_VERSION_UNION; 8150c59a5c48SFrançois Tigeot 8151c59a5c48SFrançois Tigeot typedef struct _VBE_INFO_BLOCK 8152c59a5c48SFrançois Tigeot { 8153c59a5c48SFrançois Tigeot VBE_VERSION_UNION UpdatableVBE_Info; 8154c59a5c48SFrançois Tigeot UCHAR Reserved[222]; 8155c59a5c48SFrançois Tigeot UCHAR OemData[256]; 8156c59a5c48SFrançois Tigeot } VBE_INFO_BLOCK; 8157c59a5c48SFrançois Tigeot 8158c59a5c48SFrançois Tigeot typedef struct _VBE_FP_INFO 8159c59a5c48SFrançois Tigeot { 8160c59a5c48SFrançois Tigeot USHORT HSize; 8161c59a5c48SFrançois Tigeot USHORT VSize; 8162c59a5c48SFrançois Tigeot USHORT FPType; 8163c59a5c48SFrançois Tigeot UCHAR RedBPP; 8164c59a5c48SFrançois Tigeot UCHAR GreenBPP; 8165c59a5c48SFrançois Tigeot UCHAR BlueBPP; 8166c59a5c48SFrançois Tigeot UCHAR ReservedBPP; 8167c59a5c48SFrançois Tigeot ULONG RsvdOffScrnMemSize; 8168c59a5c48SFrançois Tigeot ULONG RsvdOffScrnMEmPtr; 8169c59a5c48SFrançois Tigeot UCHAR Reserved[14]; 8170c59a5c48SFrançois Tigeot } VBE_FP_INFO; 8171c59a5c48SFrançois Tigeot 8172c59a5c48SFrançois Tigeot typedef struct _VESA_MODE_INFO_BLOCK 8173c59a5c48SFrançois Tigeot { 8174c59a5c48SFrançois Tigeot // Mandatory information for all VBE revisions 8175c59a5c48SFrançois Tigeot USHORT ModeAttributes; // dw ? ; mode attributes 8176c59a5c48SFrançois Tigeot UCHAR WinAAttributes; // db ? ; window A attributes 8177c59a5c48SFrançois Tigeot UCHAR WinBAttributes; // db ? ; window B attributes 8178c59a5c48SFrançois Tigeot USHORT WinGranularity; // dw ? ; window granularity 8179c59a5c48SFrançois Tigeot USHORT WinSize; // dw ? ; window size 8180c59a5c48SFrançois Tigeot USHORT WinASegment; // dw ? ; window A start segment 8181c59a5c48SFrançois Tigeot USHORT WinBSegment; // dw ? ; window B start segment 8182c59a5c48SFrançois Tigeot ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 8183c59a5c48SFrançois Tigeot USHORT BytesPerScanLine;// dw ? ; bytes per scan line 8184c59a5c48SFrançois Tigeot 8185c59a5c48SFrançois Tigeot //; Mandatory information for VBE 1.2 and above 8186c59a5c48SFrançois Tigeot USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 8187c59a5c48SFrançois Tigeot USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 8188c59a5c48SFrançois Tigeot UCHAR XCharSize; // db ? ; character cell width in pixels 8189c59a5c48SFrançois Tigeot UCHAR YCharSize; // db ? ; character cell height in pixels 8190c59a5c48SFrançois Tigeot UCHAR NumberOfPlanes; // db ? ; number of memory planes 8191c59a5c48SFrançois Tigeot UCHAR BitsPerPixel; // db ? ; bits per pixel 8192c59a5c48SFrançois Tigeot UCHAR NumberOfBanks; // db ? ; number of banks 8193c59a5c48SFrançois Tigeot UCHAR MemoryModel; // db ? ; memory model type 8194c59a5c48SFrançois Tigeot UCHAR BankSize; // db ? ; bank size in KB 8195c59a5c48SFrançois Tigeot UCHAR NumberOfImagePages;// db ? ; number of images 8196c59a5c48SFrançois Tigeot UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 8197c59a5c48SFrançois Tigeot 8198c59a5c48SFrançois Tigeot //; Direct Color fields(required for direct/6 and YUV/7 memory models) 8199c59a5c48SFrançois Tigeot UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 8200c59a5c48SFrançois Tigeot UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 8201c59a5c48SFrançois Tigeot UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 8202c59a5c48SFrançois Tigeot UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 8203c59a5c48SFrançois Tigeot UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 8204c59a5c48SFrançois Tigeot UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 8205c59a5c48SFrançois Tigeot UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 8206c59a5c48SFrançois Tigeot UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 8207c59a5c48SFrançois Tigeot UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 8208c59a5c48SFrançois Tigeot 8209c59a5c48SFrançois Tigeot //; Mandatory information for VBE 2.0 and above 8210c59a5c48SFrançois Tigeot ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 8211c59a5c48SFrançois Tigeot ULONG Reserved_1; // dd 0 ; reserved - always set to 0 8212c59a5c48SFrançois Tigeot USHORT Reserved_2; // dw 0 ; reserved - always set to 0 8213c59a5c48SFrançois Tigeot 8214c59a5c48SFrançois Tigeot //; Mandatory information for VBE 3.0 and above 8215c59a5c48SFrançois Tigeot USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 8216c59a5c48SFrançois Tigeot UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 8217c59a5c48SFrançois Tigeot UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 8218c59a5c48SFrançois Tigeot UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 8219c59a5c48SFrançois Tigeot UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 8220c59a5c48SFrançois Tigeot UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 8221c59a5c48SFrançois Tigeot UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 8222c59a5c48SFrançois Tigeot UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 8223c59a5c48SFrançois Tigeot UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 8224c59a5c48SFrançois Tigeot UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 8225c59a5c48SFrançois Tigeot UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 8226c59a5c48SFrançois Tigeot ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 8227c59a5c48SFrançois Tigeot UCHAR Reserved; // db 190 dup (0) 8228c59a5c48SFrançois Tigeot } VESA_MODE_INFO_BLOCK; 8229c59a5c48SFrançois Tigeot 8230c59a5c48SFrançois Tigeot // BIOS function CALLS 8231c59a5c48SFrançois Tigeot #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 8232c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 8233c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 8234c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 8235c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 8236c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 8237c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 8238c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 8239c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_STV_STD 0x16 8240c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 8241c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 8242c59a5c48SFrançois Tigeot 8243c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 8244c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 8245c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 8246c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 8247c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 8248c59a5c48SFrançois Tigeot #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 8249c59a5c48SFrançois Tigeot #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 8250c59a5c48SFrançois Tigeot 8251c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 8252c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 8253c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 8254c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 8255c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 8256c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 8257c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 8258c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 8259c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 8260c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 8261c59a5c48SFrançois Tigeot 8262c59a5c48SFrançois Tigeot 8263c59a5c48SFrançois Tigeot #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 8264c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 8265c59a5c48SFrançois Tigeot #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 8266c59a5c48SFrançois Tigeot #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 8267c59a5c48SFrançois Tigeot #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 8268c59a5c48SFrançois Tigeot #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 8269c59a5c48SFrançois Tigeot #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 8270c59a5c48SFrançois Tigeot #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 8271c59a5c48SFrançois Tigeot 8272c59a5c48SFrançois Tigeot #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 8273c59a5c48SFrançois Tigeot #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 8274c59a5c48SFrançois Tigeot #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 8275c59a5c48SFrançois Tigeot 8276c59a5c48SFrançois Tigeot // structure used for VBIOS only 8277c59a5c48SFrançois Tigeot 8278c59a5c48SFrançois Tigeot //DispOutInfoTable 8279c59a5c48SFrançois Tigeot typedef struct _ASIC_TRANSMITTER_INFO 8280c59a5c48SFrançois Tigeot { 8281c59a5c48SFrançois Tigeot USHORT usTransmitterObjId; 8282c59a5c48SFrançois Tigeot USHORT usSupportDevice; 8283c59a5c48SFrançois Tigeot UCHAR ucTransmitterCmdTblId; 8284c59a5c48SFrançois Tigeot UCHAR ucConfig; 8285c59a5c48SFrançois Tigeot UCHAR ucEncoderID; //available 1st encoder ( default ) 8286c59a5c48SFrançois Tigeot UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 8287c59a5c48SFrançois Tigeot UCHAR uc2ndEncoderID; 8288c59a5c48SFrançois Tigeot UCHAR ucReserved; 8289c59a5c48SFrançois Tigeot }ASIC_TRANSMITTER_INFO; 8290c59a5c48SFrançois Tigeot 8291c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 8292c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 8293c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 8294c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 8295c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 8296c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 8297c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 8298c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 8299c59a5c48SFrançois Tigeot #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 8300c59a5c48SFrançois Tigeot 8301c59a5c48SFrançois Tigeot typedef struct _ASIC_ENCODER_INFO 8302c59a5c48SFrançois Tigeot { 8303c59a5c48SFrançois Tigeot UCHAR ucEncoderID; 8304c59a5c48SFrançois Tigeot UCHAR ucEncoderConfig; 8305c59a5c48SFrançois Tigeot USHORT usEncoderCmdTblId; 8306c59a5c48SFrançois Tigeot }ASIC_ENCODER_INFO; 8307c59a5c48SFrançois Tigeot 8308c59a5c48SFrançois Tigeot typedef struct _ATOM_DISP_OUT_INFO 8309c59a5c48SFrançois Tigeot { 8310c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8311c59a5c48SFrançois Tigeot USHORT ptrTransmitterInfo; 8312c59a5c48SFrançois Tigeot USHORT ptrEncoderInfo; 8313c59a5c48SFrançois Tigeot ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8314c59a5c48SFrançois Tigeot ASIC_ENCODER_INFO asEncoderInfo[1]; 8315c59a5c48SFrançois Tigeot }ATOM_DISP_OUT_INFO; 8316c59a5c48SFrançois Tigeot 8317c59a5c48SFrançois Tigeot 8318c59a5c48SFrançois Tigeot typedef struct _ATOM_DISP_OUT_INFO_V2 8319c59a5c48SFrançois Tigeot { 8320c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8321c59a5c48SFrançois Tigeot USHORT ptrTransmitterInfo; 8322c59a5c48SFrançois Tigeot USHORT ptrEncoderInfo; 8323c59a5c48SFrançois Tigeot USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8324c59a5c48SFrançois Tigeot ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8325c59a5c48SFrançois Tigeot ASIC_ENCODER_INFO asEncoderInfo[1]; 8326c59a5c48SFrançois Tigeot }ATOM_DISP_OUT_INFO_V2; 8327c59a5c48SFrançois Tigeot 8328c59a5c48SFrançois Tigeot 8329c59a5c48SFrançois Tigeot typedef struct _ATOM_DISP_CLOCK_ID { 8330c59a5c48SFrançois Tigeot UCHAR ucPpllId; 8331c59a5c48SFrançois Tigeot UCHAR ucPpllAttribute; 8332c59a5c48SFrançois Tigeot }ATOM_DISP_CLOCK_ID; 8333c59a5c48SFrançois Tigeot 8334c59a5c48SFrançois Tigeot // ucPpllAttribute 8335c59a5c48SFrançois Tigeot #define CLOCK_SOURCE_SHAREABLE 0x01 8336c59a5c48SFrançois Tigeot #define CLOCK_SOURCE_DP_MODE 0x02 8337c59a5c48SFrançois Tigeot #define CLOCK_SOURCE_NONE_DP_MODE 0x04 8338c59a5c48SFrançois Tigeot 8339c59a5c48SFrançois Tigeot //DispOutInfoTable 8340c59a5c48SFrançois Tigeot typedef struct _ASIC_TRANSMITTER_INFO_V2 8341c59a5c48SFrançois Tigeot { 8342c59a5c48SFrançois Tigeot USHORT usTransmitterObjId; 8343c59a5c48SFrançois Tigeot USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 8344c59a5c48SFrançois Tigeot UCHAR ucTransmitterCmdTblId; 8345c59a5c48SFrançois Tigeot UCHAR ucConfig; 8346c59a5c48SFrançois Tigeot UCHAR ucEncoderID; // available 1st encoder ( default ) 8347c59a5c48SFrançois Tigeot UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 8348c59a5c48SFrançois Tigeot UCHAR uc2ndEncoderID; 8349c59a5c48SFrançois Tigeot UCHAR ucReserved; 8350c59a5c48SFrançois Tigeot }ASIC_TRANSMITTER_INFO_V2; 8351c59a5c48SFrançois Tigeot 8352c59a5c48SFrançois Tigeot typedef struct _ATOM_DISP_OUT_INFO_V3 8353c59a5c48SFrançois Tigeot { 8354c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8355c59a5c48SFrançois Tigeot USHORT ptrTransmitterInfo; 8356c59a5c48SFrançois Tigeot USHORT ptrEncoderInfo; 8357c59a5c48SFrançois Tigeot USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8358c59a5c48SFrançois Tigeot USHORT usReserved; 8359c59a5c48SFrançois Tigeot UCHAR ucDCERevision; 8360c59a5c48SFrançois Tigeot UCHAR ucMaxDispEngineNum; 8361c59a5c48SFrançois Tigeot UCHAR ucMaxActiveDispEngineNum; 8362c59a5c48SFrançois Tigeot UCHAR ucMaxPPLLNum; 8363c59a5c48SFrançois Tigeot UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 8364c59a5c48SFrançois Tigeot UCHAR ucDispCaps; 8365c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 8366c59a5c48SFrançois Tigeot ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 8367c59a5c48SFrançois Tigeot }ATOM_DISP_OUT_INFO_V3; 8368c59a5c48SFrançois Tigeot 8369c59a5c48SFrançois Tigeot //ucDispCaps 8370c59a5c48SFrançois Tigeot #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 8371c59a5c48SFrançois Tigeot #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 8372c59a5c48SFrançois Tigeot 8373c59a5c48SFrançois Tigeot typedef enum CORE_REF_CLK_SOURCE{ 8374c59a5c48SFrançois Tigeot CLOCK_SRC_XTALIN=0, 8375c59a5c48SFrançois Tigeot CLOCK_SRC_XO_IN=1, 8376c59a5c48SFrançois Tigeot CLOCK_SRC_XO_IN2=2, 8377c59a5c48SFrançois Tigeot }CORE_REF_CLK_SOURCE; 8378c59a5c48SFrançois Tigeot 8379c59a5c48SFrançois Tigeot // DispDevicePriorityInfo 8380c59a5c48SFrançois Tigeot typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 8381c59a5c48SFrançois Tigeot { 8382c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8383c59a5c48SFrançois Tigeot USHORT asDevicePriority[16]; 8384c59a5c48SFrançois Tigeot }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 8385c59a5c48SFrançois Tigeot 8386c59a5c48SFrançois Tigeot //ProcessAuxChannelTransactionTable 8387c59a5c48SFrançois Tigeot typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8388c59a5c48SFrançois Tigeot { 8389c59a5c48SFrançois Tigeot USHORT lpAuxRequest; 8390c59a5c48SFrançois Tigeot USHORT lpDataOut; 8391c59a5c48SFrançois Tigeot UCHAR ucChannelID; 8392c59a5c48SFrançois Tigeot union 8393c59a5c48SFrançois Tigeot { 8394c59a5c48SFrançois Tigeot UCHAR ucReplyStatus; 8395c59a5c48SFrançois Tigeot UCHAR ucDelay; 8396c59a5c48SFrançois Tigeot }; 8397c59a5c48SFrançois Tigeot UCHAR ucDataOutLen; 8398c59a5c48SFrançois Tigeot UCHAR ucReserved; 8399c59a5c48SFrançois Tigeot }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 8400c59a5c48SFrançois Tigeot 8401c59a5c48SFrançois Tigeot //ProcessAuxChannelTransactionTable 8402c59a5c48SFrançois Tigeot typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 8403c59a5c48SFrançois Tigeot { 8404c59a5c48SFrançois Tigeot USHORT lpAuxRequest; 8405c59a5c48SFrançois Tigeot USHORT lpDataOut; 8406c59a5c48SFrançois Tigeot UCHAR ucChannelID; 8407c59a5c48SFrançois Tigeot union 8408c59a5c48SFrançois Tigeot { 8409c59a5c48SFrançois Tigeot UCHAR ucReplyStatus; 8410c59a5c48SFrançois Tigeot UCHAR ucDelay; 8411c59a5c48SFrançois Tigeot }; 8412c59a5c48SFrançois Tigeot UCHAR ucDataOutLen; 8413c59a5c48SFrançois Tigeot UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 8414c59a5c48SFrançois Tigeot }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 8415c59a5c48SFrançois Tigeot 8416c59a5c48SFrançois Tigeot #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8417c59a5c48SFrançois Tigeot 8418c59a5c48SFrançois Tigeot //GetSinkType 8419c59a5c48SFrançois Tigeot 8420c59a5c48SFrançois Tigeot typedef struct _DP_ENCODER_SERVICE_PARAMETERS 8421c59a5c48SFrançois Tigeot { 8422c59a5c48SFrançois Tigeot USHORT ucLinkClock; 8423c59a5c48SFrançois Tigeot union 8424c59a5c48SFrançois Tigeot { 8425c59a5c48SFrançois Tigeot UCHAR ucConfig; // for DP training command 8426c59a5c48SFrançois Tigeot UCHAR ucI2cId; // use for GET_SINK_TYPE command 8427c59a5c48SFrançois Tigeot }; 8428c59a5c48SFrançois Tigeot UCHAR ucAction; 8429c59a5c48SFrançois Tigeot UCHAR ucStatus; 8430c59a5c48SFrançois Tigeot UCHAR ucLaneNum; 8431c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 8432c59a5c48SFrançois Tigeot }DP_ENCODER_SERVICE_PARAMETERS; 8433c59a5c48SFrançois Tigeot 8434c59a5c48SFrançois Tigeot // ucAction 8435c59a5c48SFrançois Tigeot #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 8436c59a5c48SFrançois Tigeot 8437c59a5c48SFrançois Tigeot #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 8438c59a5c48SFrançois Tigeot 8439c59a5c48SFrançois Tigeot 8440c59a5c48SFrançois Tigeot typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 8441c59a5c48SFrançois Tigeot { 8442c59a5c48SFrançois Tigeot USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8443c59a5c48SFrançois Tigeot UCHAR ucAuxId; 8444c59a5c48SFrançois Tigeot UCHAR ucAction; 8445c59a5c48SFrançois Tigeot UCHAR ucSinkType; // Iput and Output parameters. 8446c59a5c48SFrançois Tigeot UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8447c59a5c48SFrançois Tigeot UCHAR ucReserved[2]; 8448c59a5c48SFrançois Tigeot }DP_ENCODER_SERVICE_PARAMETERS_V2; 8449c59a5c48SFrançois Tigeot 8450c59a5c48SFrançois Tigeot typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 8451c59a5c48SFrançois Tigeot { 8452c59a5c48SFrançois Tigeot DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 8453c59a5c48SFrançois Tigeot PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 8454c59a5c48SFrançois Tigeot }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 8455c59a5c48SFrançois Tigeot 8456c59a5c48SFrançois Tigeot // ucAction 8457c59a5c48SFrançois Tigeot #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 8458c59a5c48SFrançois Tigeot #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 8459c59a5c48SFrançois Tigeot 8460c59a5c48SFrançois Tigeot 8461c59a5c48SFrançois Tigeot // DP_TRAINING_TABLE 8462c59a5c48SFrançois Tigeot #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 8463c59a5c48SFrançois Tigeot #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 8464c59a5c48SFrançois Tigeot #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 8465c59a5c48SFrançois Tigeot #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 8466c59a5c48SFrançois Tigeot #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 8467c59a5c48SFrançois Tigeot #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 8468c59a5c48SFrançois Tigeot #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 8469c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 8470c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 8471c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 8472c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 8473c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 8474c59a5c48SFrançois Tigeot #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 8475c59a5c48SFrançois Tigeot 8476c59a5c48SFrançois Tigeot 8477c59a5c48SFrançois Tigeot typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8478c59a5c48SFrançois Tigeot { 8479c59a5c48SFrançois Tigeot UCHAR ucI2CSpeed; 8480c59a5c48SFrançois Tigeot union 8481c59a5c48SFrançois Tigeot { 8482c59a5c48SFrançois Tigeot UCHAR ucRegIndex; 8483c59a5c48SFrançois Tigeot UCHAR ucStatus; 8484c59a5c48SFrançois Tigeot }; 8485c59a5c48SFrançois Tigeot USHORT lpI2CDataOut; 8486c59a5c48SFrançois Tigeot UCHAR ucFlag; 8487c59a5c48SFrançois Tigeot UCHAR ucTransBytes; 8488c59a5c48SFrançois Tigeot UCHAR ucSlaveAddr; 8489c59a5c48SFrançois Tigeot UCHAR ucLineNumber; 8490c59a5c48SFrançois Tigeot }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 8491c59a5c48SFrançois Tigeot 8492c59a5c48SFrançois Tigeot #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8493c59a5c48SFrançois Tigeot 8494c59a5c48SFrançois Tigeot //ucFlag 8495c59a5c48SFrançois Tigeot #define HW_I2C_WRITE 1 8496c59a5c48SFrançois Tigeot #define HW_I2C_READ 0 8497c59a5c48SFrançois Tigeot #define I2C_2BYTE_ADDR 0x02 8498c59a5c48SFrançois Tigeot 8499c59a5c48SFrançois Tigeot /****************************************************************************/ 8500c59a5c48SFrançois Tigeot // Structures used by HW_Misc_OperationTable 8501c59a5c48SFrançois Tigeot /****************************************************************************/ 8502c59a5c48SFrançois Tigeot typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 8503c59a5c48SFrançois Tigeot { 8504c59a5c48SFrançois Tigeot UCHAR ucCmd; // Input: To tell which action to take 8505c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 8506c59a5c48SFrançois Tigeot ULONG ulReserved; 8507c59a5c48SFrançois Tigeot }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 8508c59a5c48SFrançois Tigeot 8509c59a5c48SFrançois Tigeot typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 8510c59a5c48SFrançois Tigeot { 8511c59a5c48SFrançois Tigeot UCHAR ucReturnCode; // Output: Return value base on action was taken 8512c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 8513c59a5c48SFrançois Tigeot ULONG ulReserved; 8514c59a5c48SFrançois Tigeot }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 8515c59a5c48SFrançois Tigeot 8516c59a5c48SFrançois Tigeot // Actions code 8517c59a5c48SFrançois Tigeot #define ATOM_GET_SDI_SUPPORT 0xF0 8518c59a5c48SFrançois Tigeot 8519c59a5c48SFrançois Tigeot // Return code 8520c59a5c48SFrançois Tigeot #define ATOM_UNKNOWN_CMD 0 8521c59a5c48SFrançois Tigeot #define ATOM_FEATURE_NOT_SUPPORTED 1 8522c59a5c48SFrançois Tigeot #define ATOM_FEATURE_SUPPORTED 2 8523c59a5c48SFrançois Tigeot 8524c59a5c48SFrançois Tigeot typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 8525c59a5c48SFrançois Tigeot { 8526c59a5c48SFrançois Tigeot ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 8527c59a5c48SFrançois Tigeot PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 8528c59a5c48SFrançois Tigeot }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 8529c59a5c48SFrançois Tigeot 8530c59a5c48SFrançois Tigeot /****************************************************************************/ 8531c59a5c48SFrançois Tigeot 8532c59a5c48SFrançois Tigeot typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 8533c59a5c48SFrançois Tigeot { 8534c59a5c48SFrançois Tigeot UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 8535c59a5c48SFrançois Tigeot UCHAR ucReserved[3]; 8536c59a5c48SFrançois Tigeot }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 8537c59a5c48SFrançois Tigeot 8538c59a5c48SFrançois Tigeot #define HWBLKINST_INSTANCE_MASK 0x07 8539c59a5c48SFrançois Tigeot #define HWBLKINST_HWBLK_MASK 0xF0 8540c59a5c48SFrançois Tigeot #define HWBLKINST_HWBLK_SHIFT 0x04 8541c59a5c48SFrançois Tigeot 8542c59a5c48SFrançois Tigeot //ucHWBlock 8543c59a5c48SFrançois Tigeot #define SELECT_DISP_ENGINE 0 8544c59a5c48SFrançois Tigeot #define SELECT_DISP_PLL 1 8545c59a5c48SFrançois Tigeot #define SELECT_DCIO_UNIPHY_LINK0 2 8546c59a5c48SFrançois Tigeot #define SELECT_DCIO_UNIPHY_LINK1 3 8547c59a5c48SFrançois Tigeot #define SELECT_DCIO_IMPCAL 4 8548c59a5c48SFrançois Tigeot #define SELECT_DCIO_DIG 6 8549c59a5c48SFrançois Tigeot #define SELECT_CRTC_PIXEL_RATE 7 8550c59a5c48SFrançois Tigeot #define SELECT_VGA_BLK 8 8551c59a5c48SFrançois Tigeot 8552c59a5c48SFrançois Tigeot // DIGTransmitterInfoTable structure used to program UNIPHY settings 8553c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 8554c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8555c59a5c48SFrançois Tigeot USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8556c59a5c48SFrançois Tigeot USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8557c59a5c48SFrançois Tigeot USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8558c59a5c48SFrançois Tigeot USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8559c59a5c48SFrançois Tigeot USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8560c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_INFO_HEADER_V3_1; 8561c59a5c48SFrançois Tigeot 8562c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 8563c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8564c59a5c48SFrançois Tigeot USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8565c59a5c48SFrançois Tigeot USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8566c59a5c48SFrançois Tigeot USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8567c59a5c48SFrançois Tigeot USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8568c59a5c48SFrançois Tigeot USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8569c59a5c48SFrançois Tigeot USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8570c59a5c48SFrançois Tigeot USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8571c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_INFO_HEADER_V3_2; 8572c59a5c48SFrançois Tigeot 8573c59a5c48SFrançois Tigeot 8574c59a5c48SFrançois Tigeot typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 8575c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8576c59a5c48SFrançois Tigeot USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8577c59a5c48SFrançois Tigeot USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8578c59a5c48SFrançois Tigeot USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8579c59a5c48SFrançois Tigeot USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8580c59a5c48SFrançois Tigeot USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8581c59a5c48SFrançois Tigeot USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8582c59a5c48SFrançois Tigeot USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8583c59a5c48SFrançois Tigeot USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 8584c59a5c48SFrançois Tigeot USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8585c59a5c48SFrançois Tigeot USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8586c59a5c48SFrançois Tigeot USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 8587c59a5c48SFrançois Tigeot USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8588c59a5c48SFrançois Tigeot USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 8589c59a5c48SFrançois Tigeot }DIG_TRANSMITTER_INFO_HEADER_V3_3; 8590c59a5c48SFrançois Tigeot 8591c59a5c48SFrançois Tigeot 8592c59a5c48SFrançois Tigeot typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 8593c59a5c48SFrançois Tigeot USHORT usRegisterIndex; 8594c59a5c48SFrançois Tigeot UCHAR ucStartBit; 8595c59a5c48SFrançois Tigeot UCHAR ucEndBit; 8596c59a5c48SFrançois Tigeot }CLOCK_CONDITION_REGESTER_INFO; 8597c59a5c48SFrançois Tigeot 8598c59a5c48SFrançois Tigeot typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 8599c59a5c48SFrançois Tigeot USHORT usMaxClockFreq; 8600c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; 8601c59a5c48SFrançois Tigeot UCHAR ucPhySel; 8602c59a5c48SFrançois Tigeot ULONG ulAnalogSetting[1]; 8603c59a5c48SFrançois Tigeot }CLOCK_CONDITION_SETTING_ENTRY; 8604c59a5c48SFrançois Tigeot 8605c59a5c48SFrançois Tigeot typedef struct _CLOCK_CONDITION_SETTING_INFO{ 8606c59a5c48SFrançois Tigeot USHORT usEntrySize; 8607c59a5c48SFrançois Tigeot CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 8608c59a5c48SFrançois Tigeot }CLOCK_CONDITION_SETTING_INFO; 8609c59a5c48SFrançois Tigeot 8610c59a5c48SFrançois Tigeot typedef struct _PHY_CONDITION_REG_VAL{ 8611c59a5c48SFrançois Tigeot ULONG ulCondition; 8612c59a5c48SFrançois Tigeot ULONG ulRegVal; 8613c59a5c48SFrançois Tigeot }PHY_CONDITION_REG_VAL; 8614c59a5c48SFrançois Tigeot 8615c59a5c48SFrançois Tigeot typedef struct _PHY_CONDITION_REG_VAL_V2{ 8616c59a5c48SFrançois Tigeot ULONG ulCondition; 8617c59a5c48SFrançois Tigeot UCHAR ucCondition2; 8618c59a5c48SFrançois Tigeot ULONG ulRegVal; 8619c59a5c48SFrançois Tigeot }PHY_CONDITION_REG_VAL_V2; 8620c59a5c48SFrançois Tigeot 8621c59a5c48SFrançois Tigeot typedef struct _PHY_CONDITION_REG_INFO{ 8622c59a5c48SFrançois Tigeot USHORT usRegIndex; 8623c59a5c48SFrançois Tigeot USHORT usSize; 8624c59a5c48SFrançois Tigeot PHY_CONDITION_REG_VAL asRegVal[1]; 8625c59a5c48SFrançois Tigeot }PHY_CONDITION_REG_INFO; 8626c59a5c48SFrançois Tigeot 8627c59a5c48SFrançois Tigeot typedef struct _PHY_CONDITION_REG_INFO_V2{ 8628c59a5c48SFrançois Tigeot USHORT usRegIndex; 8629c59a5c48SFrançois Tigeot USHORT usSize; 8630c59a5c48SFrançois Tigeot PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 8631c59a5c48SFrançois Tigeot }PHY_CONDITION_REG_INFO_V2; 8632c59a5c48SFrançois Tigeot 8633c59a5c48SFrançois Tigeot typedef struct _PHY_ANALOG_SETTING_INFO{ 8634c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; 8635c59a5c48SFrançois Tigeot UCHAR ucPhySel; 8636c59a5c48SFrançois Tigeot USHORT usSize; 8637c59a5c48SFrançois Tigeot PHY_CONDITION_REG_INFO asAnalogSetting[1]; 8638c59a5c48SFrançois Tigeot }PHY_ANALOG_SETTING_INFO; 8639c59a5c48SFrançois Tigeot 8640c59a5c48SFrançois Tigeot typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 8641c59a5c48SFrançois Tigeot UCHAR ucEncodeMode; 8642c59a5c48SFrançois Tigeot UCHAR ucPhySel; 8643c59a5c48SFrançois Tigeot USHORT usSize; 8644c59a5c48SFrançois Tigeot PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 8645c59a5c48SFrançois Tigeot }PHY_ANALOG_SETTING_INFO_V2; 8646c59a5c48SFrançois Tigeot 8647c59a5c48SFrançois Tigeot 8648c59a5c48SFrançois Tigeot typedef struct _GFX_HAVESTING_PARAMETERS { 8649c59a5c48SFrançois Tigeot UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 8650c59a5c48SFrançois Tigeot UCHAR ucReserved; //reserved 8651c59a5c48SFrançois Tigeot UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 8652c59a5c48SFrançois Tigeot UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 8653c59a5c48SFrançois Tigeot } GFX_HAVESTING_PARAMETERS; 8654c59a5c48SFrançois Tigeot 8655c59a5c48SFrançois Tigeot //ucGfxBlkId 8656c59a5c48SFrançois Tigeot #define GFX_HARVESTING_CU_ID 0 8657c59a5c48SFrançois Tigeot #define GFX_HARVESTING_RB_ID 1 8658c59a5c48SFrançois Tigeot #define GFX_HARVESTING_PRIM_ID 2 8659c59a5c48SFrançois Tigeot 8660c59a5c48SFrançois Tigeot 8661c59a5c48SFrançois Tigeot typedef struct _VBIOS_ROM_HEADER{ 8662c59a5c48SFrançois Tigeot UCHAR PciRomSignature[2]; 8663c59a5c48SFrançois Tigeot UCHAR ucPciRomSizeIn512bytes; 8664c59a5c48SFrançois Tigeot UCHAR ucJumpCoreMainInitBIOS; 8665c59a5c48SFrançois Tigeot USHORT usLabelCoreMainInitBIOS; 8666c59a5c48SFrançois Tigeot UCHAR PciReservedSpace[18]; 8667c59a5c48SFrançois Tigeot USHORT usPciDataStructureOffset; 8668c59a5c48SFrançois Tigeot UCHAR Rsvd1d_1a[4]; 8669c59a5c48SFrançois Tigeot char strIbm[3]; 8670c59a5c48SFrançois Tigeot UCHAR CheckSum[14]; 8671c59a5c48SFrançois Tigeot UCHAR ucBiosMsgNumber; 8672c59a5c48SFrançois Tigeot char str761295520[16]; 8673c59a5c48SFrançois Tigeot USHORT usLabelCoreVPOSTNoMode; 8674c59a5c48SFrançois Tigeot USHORT usSpecialPostOffset; 8675c59a5c48SFrançois Tigeot UCHAR ucSpeicalPostImageSizeIn512Bytes; 8676c59a5c48SFrançois Tigeot UCHAR Rsved47_45[3]; 8677c59a5c48SFrançois Tigeot USHORT usROM_HeaderInformationTableOffset; 8678c59a5c48SFrançois Tigeot UCHAR Rsved4f_4a[6]; 8679c59a5c48SFrançois Tigeot char strBuildTimeStamp[20]; 8680c59a5c48SFrançois Tigeot UCHAR ucJumpCoreXFuncFarHandler; 8681c59a5c48SFrançois Tigeot USHORT usCoreXFuncFarHandlerOffset; 8682c59a5c48SFrançois Tigeot UCHAR ucRsved67; 8683c59a5c48SFrançois Tigeot UCHAR ucJumpCoreVFuncFarHandler; 8684c59a5c48SFrançois Tigeot USHORT usCoreVFuncFarHandlerOffset; 8685c59a5c48SFrançois Tigeot UCHAR Rsved6d_6b[3]; 8686c59a5c48SFrançois Tigeot USHORT usATOM_BIOS_MESSAGE_Offset; 8687c59a5c48SFrançois Tigeot }VBIOS_ROM_HEADER; 8688c59a5c48SFrançois Tigeot 8689c59a5c48SFrançois Tigeot /****************************************************************************/ 8690c59a5c48SFrançois Tigeot //Portion VI: Definitinos for vbios MC scratch registers that driver used 8691c59a5c48SFrançois Tigeot /****************************************************************************/ 8692c59a5c48SFrançois Tigeot 8693c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 8694c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 8695c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 8696c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 8697c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 8698c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 8699c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 8700c59a5c48SFrançois Tigeot #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 8701c59a5c48SFrançois Tigeot 8702c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_DDR_STRING "DDR" 8703c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 8704c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 8705c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 8706c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 8707c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_HBM_STRING "HBM" 8708c59a5c48SFrançois Tigeot #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 8709c59a5c48SFrançois Tigeot 8710c59a5c48SFrançois Tigeot /****************************************************************************/ 8711c59a5c48SFrançois Tigeot //Portion VII: Definitinos being oboselete 8712c59a5c48SFrançois Tigeot /****************************************************************************/ 8713c59a5c48SFrançois Tigeot 8714c59a5c48SFrançois Tigeot //========================================================================================== 8715c59a5c48SFrançois Tigeot //Remove the definitions below when driver is ready! 8716c59a5c48SFrançois Tigeot typedef struct _ATOM_DAC_INFO 8717c59a5c48SFrançois Tigeot { 8718c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8719c59a5c48SFrançois Tigeot USHORT usMaxFrequency; // in 10kHz unit 8720c59a5c48SFrançois Tigeot USHORT usReserved; 8721c59a5c48SFrançois Tigeot }ATOM_DAC_INFO; 8722c59a5c48SFrançois Tigeot 8723c59a5c48SFrançois Tigeot 8724c59a5c48SFrançois Tigeot typedef struct _COMPASSIONATE_DATA 8725c59a5c48SFrançois Tigeot { 8726c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8727c59a5c48SFrançois Tigeot 8728c59a5c48SFrançois Tigeot //============================== DAC1 portion 8729c59a5c48SFrançois Tigeot UCHAR ucDAC1_BG_Adjustment; 8730c59a5c48SFrançois Tigeot UCHAR ucDAC1_DAC_Adjustment; 8731c59a5c48SFrançois Tigeot USHORT usDAC1_FORCE_Data; 8732c59a5c48SFrançois Tigeot //============================== DAC2 portion 8733c59a5c48SFrançois Tigeot UCHAR ucDAC2_CRT2_BG_Adjustment; 8734c59a5c48SFrançois Tigeot UCHAR ucDAC2_CRT2_DAC_Adjustment; 8735c59a5c48SFrançois Tigeot USHORT usDAC2_CRT2_FORCE_Data; 8736c59a5c48SFrançois Tigeot USHORT usDAC2_CRT2_MUX_RegisterIndex; 8737c59a5c48SFrançois Tigeot UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8738c59a5c48SFrançois Tigeot UCHAR ucDAC2_NTSC_BG_Adjustment; 8739c59a5c48SFrançois Tigeot UCHAR ucDAC2_NTSC_DAC_Adjustment; 8740c59a5c48SFrançois Tigeot USHORT usDAC2_TV1_FORCE_Data; 8741c59a5c48SFrançois Tigeot USHORT usDAC2_TV1_MUX_RegisterIndex; 8742c59a5c48SFrançois Tigeot UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8743c59a5c48SFrançois Tigeot UCHAR ucDAC2_CV_BG_Adjustment; 8744c59a5c48SFrançois Tigeot UCHAR ucDAC2_CV_DAC_Adjustment; 8745c59a5c48SFrançois Tigeot USHORT usDAC2_CV_FORCE_Data; 8746c59a5c48SFrançois Tigeot USHORT usDAC2_CV_MUX_RegisterIndex; 8747c59a5c48SFrançois Tigeot UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8748c59a5c48SFrançois Tigeot UCHAR ucDAC2_PAL_BG_Adjustment; 8749c59a5c48SFrançois Tigeot UCHAR ucDAC2_PAL_DAC_Adjustment; 8750c59a5c48SFrançois Tigeot USHORT usDAC2_TV2_FORCE_Data; 8751c59a5c48SFrançois Tigeot }COMPASSIONATE_DATA; 8752c59a5c48SFrançois Tigeot 8753c59a5c48SFrançois Tigeot /****************************Supported Device Info Table Definitions**********************/ 8754c59a5c48SFrançois Tigeot // ucConnectInfo: 8755c59a5c48SFrançois Tigeot // [7:4] - connector type 8756c59a5c48SFrançois Tigeot // = 1 - VGA connector 8757c59a5c48SFrançois Tigeot // = 2 - DVI-I 8758c59a5c48SFrançois Tigeot // = 3 - DVI-D 8759c59a5c48SFrançois Tigeot // = 4 - DVI-A 8760c59a5c48SFrançois Tigeot // = 5 - SVIDEO 8761c59a5c48SFrançois Tigeot // = 6 - COMPOSITE 8762c59a5c48SFrançois Tigeot // = 7 - LVDS 8763c59a5c48SFrançois Tigeot // = 8 - DIGITAL LINK 8764c59a5c48SFrançois Tigeot // = 9 - SCART 8765c59a5c48SFrançois Tigeot // = 0xA - HDMI_type A 8766c59a5c48SFrançois Tigeot // = 0xB - HDMI_type B 8767c59a5c48SFrançois Tigeot // = 0xE - Special case1 (DVI+DIN) 8768c59a5c48SFrançois Tigeot // Others=TBD 8769c59a5c48SFrançois Tigeot // [3:0] - DAC Associated 8770c59a5c48SFrançois Tigeot // = 0 - no DAC 8771c59a5c48SFrançois Tigeot // = 1 - DACA 8772c59a5c48SFrançois Tigeot // = 2 - DACB 8773c59a5c48SFrançois Tigeot // = 3 - External DAC 8774c59a5c48SFrançois Tigeot // Others=TBD 8775c59a5c48SFrançois Tigeot // 8776c59a5c48SFrançois Tigeot 8777c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_INFO 8778c59a5c48SFrançois Tigeot { 8779c59a5c48SFrançois Tigeot #if ATOM_BIG_ENDIAN 8780c59a5c48SFrançois Tigeot UCHAR bfConnectorType:4; 8781c59a5c48SFrançois Tigeot UCHAR bfAssociatedDAC:4; 8782c59a5c48SFrançois Tigeot #else 8783c59a5c48SFrançois Tigeot UCHAR bfAssociatedDAC:4; 8784c59a5c48SFrançois Tigeot UCHAR bfConnectorType:4; 8785c59a5c48SFrançois Tigeot #endif 8786c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_INFO; 8787c59a5c48SFrançois Tigeot 8788c59a5c48SFrançois Tigeot typedef union _ATOM_CONNECTOR_INFO_ACCESS 8789c59a5c48SFrançois Tigeot { 8790c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INFO sbfAccess; 8791c59a5c48SFrançois Tigeot UCHAR ucAccess; 8792c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_INFO_ACCESS; 8793c59a5c48SFrançois Tigeot 8794c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_INFO_I2C 8795c59a5c48SFrançois Tigeot { 8796c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8797c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8798c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_INFO_I2C; 8799c59a5c48SFrançois Tigeot 8800c59a5c48SFrançois Tigeot 8801c59a5c48SFrançois Tigeot typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8802c59a5c48SFrançois Tigeot { 8803c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8804c59a5c48SFrançois Tigeot USHORT usDeviceSupport; 8805c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8806c59a5c48SFrançois Tigeot }ATOM_SUPPORTED_DEVICES_INFO; 8807c59a5c48SFrançois Tigeot 8808c59a5c48SFrançois Tigeot #define NO_INT_SRC_MAPPED 0xFF 8809c59a5c48SFrançois Tigeot 8810c59a5c48SFrançois Tigeot typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8811c59a5c48SFrançois Tigeot { 8812c59a5c48SFrançois Tigeot UCHAR ucIntSrcBitmap; 8813c59a5c48SFrançois Tigeot }ATOM_CONNECTOR_INC_SRC_BITMAP; 8814c59a5c48SFrançois Tigeot 8815c59a5c48SFrançois Tigeot typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8816c59a5c48SFrançois Tigeot { 8817c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8818c59a5c48SFrançois Tigeot USHORT usDeviceSupport; 8819c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8820c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8821c59a5c48SFrançois Tigeot }ATOM_SUPPORTED_DEVICES_INFO_2; 8822c59a5c48SFrançois Tigeot 8823c59a5c48SFrançois Tigeot typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8824c59a5c48SFrançois Tigeot { 8825c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8826c59a5c48SFrançois Tigeot USHORT usDeviceSupport; 8827c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8828c59a5c48SFrançois Tigeot ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8829c59a5c48SFrançois Tigeot }ATOM_SUPPORTED_DEVICES_INFO_2d1; 8830c59a5c48SFrançois Tigeot 8831c59a5c48SFrançois Tigeot #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8832c59a5c48SFrançois Tigeot 8833c59a5c48SFrançois Tigeot 8834c59a5c48SFrançois Tigeot 8835c59a5c48SFrançois Tigeot typedef struct _ATOM_MISC_CONTROL_INFO 8836c59a5c48SFrançois Tigeot { 8837c59a5c48SFrançois Tigeot USHORT usFrequency; 8838c59a5c48SFrançois Tigeot UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8839c59a5c48SFrançois Tigeot UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8840c59a5c48SFrançois Tigeot UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8841c59a5c48SFrançois Tigeot UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8842c59a5c48SFrançois Tigeot }ATOM_MISC_CONTROL_INFO; 8843c59a5c48SFrançois Tigeot 8844c59a5c48SFrançois Tigeot 8845c59a5c48SFrançois Tigeot #define ATOM_MAX_MISC_INFO 4 8846c59a5c48SFrançois Tigeot 8847c59a5c48SFrançois Tigeot typedef struct _ATOM_TMDS_INFO 8848c59a5c48SFrançois Tigeot { 8849c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8850c59a5c48SFrançois Tigeot USHORT usMaxFrequency; // in 10Khz 8851c59a5c48SFrançois Tigeot ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8852c59a5c48SFrançois Tigeot }ATOM_TMDS_INFO; 8853c59a5c48SFrançois Tigeot 8854c59a5c48SFrançois Tigeot 8855c59a5c48SFrançois Tigeot typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8856c59a5c48SFrançois Tigeot { 8857c59a5c48SFrançois Tigeot UCHAR ucTVStandard; //Same as TV standards defined above, 8858c59a5c48SFrançois Tigeot UCHAR ucPadding[1]; 8859c59a5c48SFrançois Tigeot }ATOM_ENCODER_ANALOG_ATTRIBUTE; 8860c59a5c48SFrançois Tigeot 8861c59a5c48SFrançois Tigeot typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8862c59a5c48SFrançois Tigeot { 8863c59a5c48SFrançois Tigeot UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8864c59a5c48SFrançois Tigeot UCHAR ucPadding[1]; 8865c59a5c48SFrançois Tigeot }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8866c59a5c48SFrançois Tigeot 8867c59a5c48SFrançois Tigeot typedef union _ATOM_ENCODER_ATTRIBUTE 8868c59a5c48SFrançois Tigeot { 8869c59a5c48SFrançois Tigeot ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8870c59a5c48SFrançois Tigeot ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8871c59a5c48SFrançois Tigeot }ATOM_ENCODER_ATTRIBUTE; 8872c59a5c48SFrançois Tigeot 8873c59a5c48SFrançois Tigeot 8874c59a5c48SFrançois Tigeot typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8875c59a5c48SFrançois Tigeot { 8876c59a5c48SFrançois Tigeot USHORT usPixelClock; 8877c59a5c48SFrançois Tigeot USHORT usEncoderID; 8878c59a5c48SFrançois Tigeot UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8879c59a5c48SFrançois Tigeot UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8880c59a5c48SFrançois Tigeot ATOM_ENCODER_ATTRIBUTE usDevAttr; 8881c59a5c48SFrançois Tigeot }DVO_ENCODER_CONTROL_PARAMETERS; 8882c59a5c48SFrançois Tigeot 8883c59a5c48SFrançois Tigeot typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8884c59a5c48SFrançois Tigeot { 8885c59a5c48SFrançois Tigeot DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8886c59a5c48SFrançois Tigeot WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8887c59a5c48SFrançois Tigeot }DVO_ENCODER_CONTROL_PS_ALLOCATION; 8888c59a5c48SFrançois Tigeot 8889c59a5c48SFrançois Tigeot 8890c59a5c48SFrançois Tigeot #define ATOM_XTMDS_ASIC_SI164_ID 1 8891c59a5c48SFrançois Tigeot #define ATOM_XTMDS_ASIC_SI178_ID 2 8892c59a5c48SFrançois Tigeot #define ATOM_XTMDS_ASIC_TFP513_ID 3 8893c59a5c48SFrançois Tigeot #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8894c59a5c48SFrançois Tigeot #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8895c59a5c48SFrançois Tigeot #define ATOM_XTMDS_MVPU_FPGA 0x00000004 8896c59a5c48SFrançois Tigeot 8897c59a5c48SFrançois Tigeot 8898c59a5c48SFrançois Tigeot typedef struct _ATOM_XTMDS_INFO 8899c59a5c48SFrançois Tigeot { 8900c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 8901c59a5c48SFrançois Tigeot USHORT usSingleLinkMaxFrequency; 8902c59a5c48SFrançois Tigeot ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8903c59a5c48SFrançois Tigeot UCHAR ucXtransimitterID; 8904c59a5c48SFrançois Tigeot UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8905c59a5c48SFrançois Tigeot UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8906c59a5c48SFrançois Tigeot // due to design. This ID is used to alert driver that the sequence is not "standard"! 8907c59a5c48SFrançois Tigeot UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8908c59a5c48SFrançois Tigeot UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8909c59a5c48SFrançois Tigeot }ATOM_XTMDS_INFO; 8910c59a5c48SFrançois Tigeot 8911c59a5c48SFrançois Tigeot typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8912c59a5c48SFrançois Tigeot { 8913c59a5c48SFrançois Tigeot UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8914c59a5c48SFrançois Tigeot UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8915c59a5c48SFrançois Tigeot UCHAR ucPadding[2]; 8916c59a5c48SFrançois Tigeot }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8917c59a5c48SFrançois Tigeot 8918c59a5c48SFrançois Tigeot /****************************Legacy Power Play Table Definitions **********************/ 8919c59a5c48SFrançois Tigeot 8920c59a5c48SFrançois Tigeot //Definitions for ulPowerPlayMiscInfo 8921c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8922c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8923c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8924c59a5c48SFrançois Tigeot 8925c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8926c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8927c59a5c48SFrançois Tigeot 8928c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8929c59a5c48SFrançois Tigeot 8930c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8931c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8932c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8933c59a5c48SFrançois Tigeot 8934c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8935c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8936c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8937c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8938c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8939c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8940c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8941c59a5c48SFrançois Tigeot 8942c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8943c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8944c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8945c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8946c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8947c59a5c48SFrançois Tigeot 8948c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8949c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8950c59a5c48SFrançois Tigeot 8951c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8952c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8953c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8954c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8955c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8956c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8957c59a5c48SFrançois Tigeot 8958c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8959c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8960c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8961c59a5c48SFrançois Tigeot 8962c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8963c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8964c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8965c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8966c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8967c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8968c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8969c59a5c48SFrançois Tigeot //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8970c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8971c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8972c59a5c48SFrançois Tigeot #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8973c59a5c48SFrançois Tigeot 8974c59a5c48SFrançois Tigeot //ucTableFormatRevision=1 8975c59a5c48SFrançois Tigeot //ucTableContentRevision=1 8976c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERMODE_INFO 8977c59a5c48SFrançois Tigeot { 8978c59a5c48SFrançois Tigeot ULONG ulMiscInfo; //The power level should be arranged in ascending order 8979c59a5c48SFrançois Tigeot ULONG ulReserved1; // must set to 0 8980c59a5c48SFrançois Tigeot ULONG ulReserved2; // must set to 0 8981c59a5c48SFrançois Tigeot USHORT usEngineClock; 8982c59a5c48SFrançois Tigeot USHORT usMemoryClock; 8983c59a5c48SFrançois Tigeot UCHAR ucVoltageDropIndex; // index to GPIO table 8984c59a5c48SFrançois Tigeot UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8985c59a5c48SFrançois Tigeot UCHAR ucMinTemperature; 8986c59a5c48SFrançois Tigeot UCHAR ucMaxTemperature; 8987c59a5c48SFrançois Tigeot UCHAR ucNumPciELanes; // number of PCIE lanes 8988c59a5c48SFrançois Tigeot }ATOM_POWERMODE_INFO; 8989c59a5c48SFrançois Tigeot 8990c59a5c48SFrançois Tigeot //ucTableFormatRevision=2 8991c59a5c48SFrançois Tigeot //ucTableContentRevision=1 8992c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERMODE_INFO_V2 8993c59a5c48SFrançois Tigeot { 8994c59a5c48SFrançois Tigeot ULONG ulMiscInfo; //The power level should be arranged in ascending order 8995c59a5c48SFrançois Tigeot ULONG ulMiscInfo2; 8996c59a5c48SFrançois Tigeot ULONG ulEngineClock; 8997c59a5c48SFrançois Tigeot ULONG ulMemoryClock; 8998c59a5c48SFrançois Tigeot UCHAR ucVoltageDropIndex; // index to GPIO table 8999c59a5c48SFrançois Tigeot UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9000c59a5c48SFrançois Tigeot UCHAR ucMinTemperature; 9001c59a5c48SFrançois Tigeot UCHAR ucMaxTemperature; 9002c59a5c48SFrançois Tigeot UCHAR ucNumPciELanes; // number of PCIE lanes 9003c59a5c48SFrançois Tigeot }ATOM_POWERMODE_INFO_V2; 9004c59a5c48SFrançois Tigeot 9005c59a5c48SFrançois Tigeot //ucTableFormatRevision=2 9006c59a5c48SFrançois Tigeot //ucTableContentRevision=2 9007c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERMODE_INFO_V3 9008c59a5c48SFrançois Tigeot { 9009c59a5c48SFrançois Tigeot ULONG ulMiscInfo; //The power level should be arranged in ascending order 9010c59a5c48SFrançois Tigeot ULONG ulMiscInfo2; 9011c59a5c48SFrançois Tigeot ULONG ulEngineClock; 9012c59a5c48SFrançois Tigeot ULONG ulMemoryClock; 9013c59a5c48SFrançois Tigeot UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 9014c59a5c48SFrançois Tigeot UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9015c59a5c48SFrançois Tigeot UCHAR ucMinTemperature; 9016c59a5c48SFrançois Tigeot UCHAR ucMaxTemperature; 9017c59a5c48SFrançois Tigeot UCHAR ucNumPciELanes; // number of PCIE lanes 9018c59a5c48SFrançois Tigeot UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 9019c59a5c48SFrançois Tigeot }ATOM_POWERMODE_INFO_V3; 9020c59a5c48SFrançois Tigeot 9021c59a5c48SFrançois Tigeot 9022c59a5c48SFrançois Tigeot #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 9023c59a5c48SFrançois Tigeot 9024c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 9025c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 9026c59a5c48SFrançois Tigeot 9027c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 9028c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 9029c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 9030c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 9031c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 9032c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 9033c59a5c48SFrançois Tigeot #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 9034c59a5c48SFrançois Tigeot 9035c59a5c48SFrançois Tigeot 9036c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERPLAY_INFO 9037c59a5c48SFrançois Tigeot { 9038c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 9039c59a5c48SFrançois Tigeot UCHAR ucOverdriveThermalController; 9040c59a5c48SFrançois Tigeot UCHAR ucOverdriveI2cLine; 9041c59a5c48SFrançois Tigeot UCHAR ucOverdriveIntBitmap; 9042c59a5c48SFrançois Tigeot UCHAR ucOverdriveControllerAddress; 9043c59a5c48SFrançois Tigeot UCHAR ucSizeOfPowerModeEntry; 9044c59a5c48SFrançois Tigeot UCHAR ucNumOfPowerModeEntries; 9045c59a5c48SFrançois Tigeot ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9046c59a5c48SFrançois Tigeot }ATOM_POWERPLAY_INFO; 9047c59a5c48SFrançois Tigeot 9048c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERPLAY_INFO_V2 9049c59a5c48SFrançois Tigeot { 9050c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 9051c59a5c48SFrançois Tigeot UCHAR ucOverdriveThermalController; 9052c59a5c48SFrançois Tigeot UCHAR ucOverdriveI2cLine; 9053c59a5c48SFrançois Tigeot UCHAR ucOverdriveIntBitmap; 9054c59a5c48SFrançois Tigeot UCHAR ucOverdriveControllerAddress; 9055c59a5c48SFrançois Tigeot UCHAR ucSizeOfPowerModeEntry; 9056c59a5c48SFrançois Tigeot UCHAR ucNumOfPowerModeEntries; 9057c59a5c48SFrançois Tigeot ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9058c59a5c48SFrançois Tigeot }ATOM_POWERPLAY_INFO_V2; 9059c59a5c48SFrançois Tigeot 9060c59a5c48SFrançois Tigeot typedef struct _ATOM_POWERPLAY_INFO_V3 9061c59a5c48SFrançois Tigeot { 9062c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER sHeader; 9063c59a5c48SFrançois Tigeot UCHAR ucOverdriveThermalController; 9064c59a5c48SFrançois Tigeot UCHAR ucOverdriveI2cLine; 9065c59a5c48SFrançois Tigeot UCHAR ucOverdriveIntBitmap; 9066c59a5c48SFrançois Tigeot UCHAR ucOverdriveControllerAddress; 9067c59a5c48SFrançois Tigeot UCHAR ucSizeOfPowerModeEntry; 9068c59a5c48SFrançois Tigeot UCHAR ucNumOfPowerModeEntries; 9069c59a5c48SFrançois Tigeot ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9070c59a5c48SFrançois Tigeot }ATOM_POWERPLAY_INFO_V3; 9071c59a5c48SFrançois Tigeot 9072c59a5c48SFrançois Tigeot 9073c59a5c48SFrançois Tigeot 9074c59a5c48SFrançois Tigeot /**************************************************************************/ 9075c59a5c48SFrançois Tigeot 9076c59a5c48SFrançois Tigeot 9077c59a5c48SFrançois Tigeot // Following definitions are for compatiblity issue in different SW components. 9078c59a5c48SFrançois Tigeot #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 9079c59a5c48SFrançois Tigeot #define Object_Info Object_Header 9080c59a5c48SFrançois Tigeot #define AdjustARB_SEQ MC_InitParameter 9081c59a5c48SFrançois Tigeot #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 9082c59a5c48SFrançois Tigeot #define ASIC_VDDCI_Info ASIC_ProfilingInfo 9083c59a5c48SFrançois Tigeot #define ASIC_MVDDQ_Info MemoryTrainingInfo 9084c59a5c48SFrançois Tigeot #define SS_Info PPLL_SS_Info 9085c59a5c48SFrançois Tigeot #define ASIC_MVDDC_Info ASIC_InternalSS_Info 9086c59a5c48SFrançois Tigeot #define DispDevicePriorityInfo SaveRestoreInfo 9087c59a5c48SFrançois Tigeot #define DispOutInfo TV_VideoMode 9088c59a5c48SFrançois Tigeot 9089c59a5c48SFrançois Tigeot 9090c59a5c48SFrançois Tigeot #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 9091c59a5c48SFrançois Tigeot #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 9092c59a5c48SFrançois Tigeot 9093c59a5c48SFrançois Tigeot //New device naming, remove them when both DAL/VBIOS is ready 9094c59a5c48SFrançois Tigeot #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9095c59a5c48SFrançois Tigeot #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 9096c59a5c48SFrançois Tigeot 9097c59a5c48SFrançois Tigeot #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9098c59a5c48SFrançois Tigeot #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 9099c59a5c48SFrançois Tigeot 9100c59a5c48SFrançois Tigeot #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 9101c59a5c48SFrançois Tigeot #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 9102c59a5c48SFrançois Tigeot 9103c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 9104c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 9105c59a5c48SFrançois Tigeot 9106c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 9107c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 9108c59a5c48SFrançois Tigeot 9109c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 9110c59a5c48SFrançois Tigeot #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 9111c59a5c48SFrançois Tigeot 9112c59a5c48SFrançois Tigeot #define ATOM_S0_DFP1I ATOM_S0_DFP1 9113c59a5c48SFrançois Tigeot #define ATOM_S0_DFP1X ATOM_S0_DFP2 9114c59a5c48SFrançois Tigeot 9115c59a5c48SFrançois Tigeot #define ATOM_S0_DFP2I 0x00200000L 9116c59a5c48SFrançois Tigeot #define ATOM_S0_DFP2Ib2 0x20 9117c59a5c48SFrançois Tigeot 9118c59a5c48SFrançois Tigeot #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 9119c59a5c48SFrançois Tigeot #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 9120c59a5c48SFrançois Tigeot 9121c59a5c48SFrançois Tigeot #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 9122c59a5c48SFrançois Tigeot #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 9123c59a5c48SFrançois Tigeot 9124c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2I_ACTIVEb1 0x02 9125c59a5c48SFrançois Tigeot 9126c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 9127c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 9128c59a5c48SFrançois Tigeot 9129c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 9130c59a5c48SFrançois Tigeot 9131c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 9132c59a5c48SFrançois Tigeot #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 9133c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 9134c59a5c48SFrançois Tigeot 9135c59a5c48SFrançois Tigeot 9136c59a5c48SFrançois Tigeot #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 9137c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 9138c59a5c48SFrançois Tigeot 9139c59a5c48SFrançois Tigeot #define ATOM_S5_DOS_REQ_DFP2I 0x0200 9140c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 9141c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 9142c59a5c48SFrançois Tigeot 9143c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 9144c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 9145c59a5c48SFrançois Tigeot 9146c59a5c48SFrançois Tigeot #define TMDS1XEncoderControl DVOEncoderControl 9147c59a5c48SFrançois Tigeot #define DFP1XOutputControl DVOOutputControl 9148c59a5c48SFrançois Tigeot 9149c59a5c48SFrançois Tigeot #define ExternalDFPOutputControl DFP1XOutputControl 9150c59a5c48SFrançois Tigeot #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 9151c59a5c48SFrançois Tigeot 9152c59a5c48SFrançois Tigeot #define DFP1IOutputControl TMDSAOutputControl 9153c59a5c48SFrançois Tigeot #define DFP2IOutputControl LVTMAOutputControl 9154c59a5c48SFrançois Tigeot 9155c59a5c48SFrançois Tigeot #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9156c59a5c48SFrançois Tigeot #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9157c59a5c48SFrançois Tigeot 9158c59a5c48SFrançois Tigeot #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9159c59a5c48SFrançois Tigeot #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9160c59a5c48SFrançois Tigeot 9161c59a5c48SFrançois Tigeot #define ucDac1Standard ucDacStandard 9162c59a5c48SFrançois Tigeot #define ucDac2Standard ucDacStandard 9163c59a5c48SFrançois Tigeot 9164c59a5c48SFrançois Tigeot #define TMDS1EncoderControl TMDSAEncoderControl 9165c59a5c48SFrançois Tigeot #define TMDS2EncoderControl LVTMAEncoderControl 9166c59a5c48SFrançois Tigeot 9167c59a5c48SFrançois Tigeot #define DFP1OutputControl TMDSAOutputControl 9168c59a5c48SFrançois Tigeot #define DFP2OutputControl LVTMAOutputControl 9169c59a5c48SFrançois Tigeot #define CRT1OutputControl DAC1OutputControl 9170c59a5c48SFrançois Tigeot #define CRT2OutputControl DAC2OutputControl 9171c59a5c48SFrançois Tigeot 9172c59a5c48SFrançois Tigeot //These two lines will be removed for sure in a few days, will follow up with Michael V. 9173c59a5c48SFrançois Tigeot #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 9174c59a5c48SFrançois Tigeot #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 9175c59a5c48SFrançois Tigeot 9176c59a5c48SFrançois Tigeot #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 9177c59a5c48SFrançois Tigeot #define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9178c59a5c48SFrançois Tigeot #define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9179c59a5c48SFrançois Tigeot #define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9180c59a5c48SFrançois Tigeot #define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9181c59a5c48SFrançois Tigeot 9182c59a5c48SFrançois Tigeot #define ATOM_S6_ACC_REQ_TV2 0x00400000L 9183c59a5c48SFrançois Tigeot #define ATOM_DEVICE_TV2_INDEX 0x00000006 9184c59a5c48SFrançois Tigeot #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 9185c59a5c48SFrançois Tigeot #define ATOM_S0_TV2 0x00100000L 9186c59a5c48SFrançois Tigeot #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 9187c59a5c48SFrançois Tigeot #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 9188c59a5c48SFrançois Tigeot 9189c59a5c48SFrançois Tigeot /*********************************************************************************/ 9190c59a5c48SFrançois Tigeot 9191*b843c749SSergey Zigachev #pragma pack() // BIOS data must use byte alignment 9192c59a5c48SFrançois Tigeot 9193c59a5c48SFrançois Tigeot #pragma pack(1) 9194c59a5c48SFrançois Tigeot 9195c59a5c48SFrançois Tigeot typedef struct _ATOM_HOLE_INFO 9196c59a5c48SFrançois Tigeot { 9197c59a5c48SFrançois Tigeot USHORT usOffset; // offset of the hole ( from the start of the binary ) 9198c59a5c48SFrançois Tigeot USHORT usLength; // length of the hole ( in bytes ) 9199c59a5c48SFrançois Tigeot }ATOM_HOLE_INFO; 9200c59a5c48SFrançois Tigeot 9201c59a5c48SFrançois Tigeot typedef struct _ATOM_SERVICE_DESCRIPTION 9202c59a5c48SFrançois Tigeot { 9203c59a5c48SFrançois Tigeot UCHAR ucRevision; // Holes set revision 9204c59a5c48SFrançois Tigeot UCHAR ucAlgorithm; // Hash algorithm 9205c59a5c48SFrançois Tigeot UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 9206c59a5c48SFrançois Tigeot UCHAR ucReserved; 9207c59a5c48SFrançois Tigeot USHORT usSigOffset; // Signature offset ( from the start of the binary ) 9208c59a5c48SFrançois Tigeot USHORT usSigLength; // Signature length 9209c59a5c48SFrançois Tigeot }ATOM_SERVICE_DESCRIPTION; 9210c59a5c48SFrançois Tigeot 9211c59a5c48SFrançois Tigeot 9212c59a5c48SFrançois Tigeot typedef struct _ATOM_SERVICE_INFO 9213c59a5c48SFrançois Tigeot { 9214c59a5c48SFrançois Tigeot ATOM_COMMON_TABLE_HEADER asHeader; 9215c59a5c48SFrançois Tigeot ATOM_SERVICE_DESCRIPTION asDescr; 9216c59a5c48SFrançois Tigeot UCHAR ucholesNo; // number of holes that follow 9217c59a5c48SFrançois Tigeot ATOM_HOLE_INFO holes[1]; // array of hole descriptions 9218c59a5c48SFrançois Tigeot }ATOM_SERVICE_INFO; 9219c59a5c48SFrançois Tigeot 9220c59a5c48SFrançois Tigeot 9221c59a5c48SFrançois Tigeot 9222*b843c749SSergey Zigachev #pragma pack() // BIOS data must use byte alignment 9223c59a5c48SFrançois Tigeot 9224c59a5c48SFrançois Tigeot // 9225c59a5c48SFrançois Tigeot // AMD ACPI Table 9226c59a5c48SFrançois Tigeot // 9227c59a5c48SFrançois Tigeot #pragma pack(1) 9228c59a5c48SFrançois Tigeot 9229c59a5c48SFrançois Tigeot typedef struct { 9230c59a5c48SFrançois Tigeot ULONG Signature; 9231c59a5c48SFrançois Tigeot ULONG TableLength; //Length 9232c59a5c48SFrançois Tigeot UCHAR Revision; 9233c59a5c48SFrançois Tigeot UCHAR Checksum; 9234c59a5c48SFrançois Tigeot UCHAR OemId[6]; 9235c59a5c48SFrançois Tigeot UCHAR OemTableId[8]; //UINT64 OemTableId; 9236c59a5c48SFrançois Tigeot ULONG OemRevision; 9237c59a5c48SFrançois Tigeot ULONG CreatorId; 9238c59a5c48SFrançois Tigeot ULONG CreatorRevision; 9239c59a5c48SFrançois Tigeot } AMD_ACPI_DESCRIPTION_HEADER; 9240c59a5c48SFrançois Tigeot /* 9241c59a5c48SFrançois Tigeot //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 9242c59a5c48SFrançois Tigeot typedef struct { 9243c59a5c48SFrançois Tigeot UINT32 Signature; //0x0 9244c59a5c48SFrançois Tigeot UINT32 Length; //0x4 9245c59a5c48SFrançois Tigeot UINT8 Revision; //0x8 9246c59a5c48SFrançois Tigeot UINT8 Checksum; //0x9 9247c59a5c48SFrançois Tigeot UINT8 OemId[6]; //0xA 9248c59a5c48SFrançois Tigeot UINT64 OemTableId; //0x10 9249c59a5c48SFrançois Tigeot UINT32 OemRevision; //0x18 9250c59a5c48SFrançois Tigeot UINT32 CreatorId; //0x1C 9251c59a5c48SFrançois Tigeot UINT32 CreatorRevision; //0x20 9252c59a5c48SFrançois Tigeot }EFI_ACPI_DESCRIPTION_HEADER; 9253c59a5c48SFrançois Tigeot */ 9254c59a5c48SFrançois Tigeot typedef struct { 9255c59a5c48SFrançois Tigeot AMD_ACPI_DESCRIPTION_HEADER SHeader; 9256c59a5c48SFrançois Tigeot UCHAR TableUUID[16]; //0x24 9257c59a5c48SFrançois Tigeot ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 9258c59a5c48SFrançois Tigeot ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 9259c59a5c48SFrançois Tigeot ULONG Reserved[4]; //0x3C 9260c59a5c48SFrançois Tigeot }UEFI_ACPI_VFCT; 9261c59a5c48SFrançois Tigeot 9262c59a5c48SFrançois Tigeot typedef struct { 9263c59a5c48SFrançois Tigeot ULONG PCIBus; //0x4C 9264c59a5c48SFrançois Tigeot ULONG PCIDevice; //0x50 9265c59a5c48SFrançois Tigeot ULONG PCIFunction; //0x54 9266c59a5c48SFrançois Tigeot USHORT VendorID; //0x58 9267c59a5c48SFrançois Tigeot USHORT DeviceID; //0x5A 9268c59a5c48SFrançois Tigeot USHORT SSVID; //0x5C 9269c59a5c48SFrançois Tigeot USHORT SSID; //0x5E 9270c59a5c48SFrançois Tigeot ULONG Revision; //0x60 9271c59a5c48SFrançois Tigeot ULONG ImageLength; //0x64 9272c59a5c48SFrançois Tigeot }VFCT_IMAGE_HEADER; 9273c59a5c48SFrançois Tigeot 9274c59a5c48SFrançois Tigeot 9275c59a5c48SFrançois Tigeot typedef struct { 9276c59a5c48SFrançois Tigeot VFCT_IMAGE_HEADER VbiosHeader; 9277c59a5c48SFrançois Tigeot UCHAR VbiosContent[1]; 9278c59a5c48SFrançois Tigeot }GOP_VBIOS_CONTENT; 9279c59a5c48SFrançois Tigeot 9280c59a5c48SFrançois Tigeot typedef struct { 9281c59a5c48SFrançois Tigeot VFCT_IMAGE_HEADER Lib1Header; 9282c59a5c48SFrançois Tigeot UCHAR Lib1Content[1]; 9283c59a5c48SFrançois Tigeot }GOP_LIB1_CONTENT; 9284c59a5c48SFrançois Tigeot 9285c59a5c48SFrançois Tigeot #pragma pack() 9286c59a5c48SFrançois Tigeot 9287c59a5c48SFrançois Tigeot 9288c59a5c48SFrançois Tigeot #endif /* _ATOMBIOS_H */ 9289c59a5c48SFrançois Tigeot 9290c59a5c48SFrançois Tigeot #include "pptable.h" 9291c59a5c48SFrançois Tigeot 9292