17dcf36dcSFrançois Tigeot /* 27dcf36dcSFrançois Tigeot * Copyright 2014 Advanced Micro Devices, Inc. 37dcf36dcSFrançois Tigeot * 47dcf36dcSFrançois Tigeot * Permission is hereby granted, free of charge, to any person obtaining a 57dcf36dcSFrançois Tigeot * copy of this software and associated documentation files (the "Software"), 67dcf36dcSFrançois Tigeot * to deal in the Software without restriction, including without limitation 77dcf36dcSFrançois Tigeot * the rights to use, copy, modify, merge, publish, distribute, sublicense, 87dcf36dcSFrançois Tigeot * and/or sell copies of the Software, and to permit persons to whom the 97dcf36dcSFrançois Tigeot * Software is furnished to do so, subject to the following conditions: 107dcf36dcSFrançois Tigeot * 117dcf36dcSFrançois Tigeot * The above copyright notice and this permission notice shall be included in 127dcf36dcSFrançois Tigeot * all copies or substantial portions of the Software. 137dcf36dcSFrançois Tigeot * 147dcf36dcSFrançois Tigeot * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 157dcf36dcSFrançois Tigeot * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 167dcf36dcSFrançois Tigeot * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 177dcf36dcSFrançois Tigeot * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 187dcf36dcSFrançois Tigeot * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 197dcf36dcSFrançois Tigeot * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 207dcf36dcSFrançois Tigeot * OTHER DEALINGS IN THE SOFTWARE. 217dcf36dcSFrançois Tigeot */ 227dcf36dcSFrançois Tigeot 237dcf36dcSFrançois Tigeot /* 247dcf36dcSFrançois Tigeot * This file defines the private interface between the 257dcf36dcSFrançois Tigeot * AMD kernel graphics drivers and the AMD KFD. 267dcf36dcSFrançois Tigeot */ 277dcf36dcSFrançois Tigeot 287dcf36dcSFrançois Tigeot #ifndef KGD_KFD_INTERFACE_H_INCLUDED 297dcf36dcSFrançois Tigeot #define KGD_KFD_INTERFACE_H_INCLUDED 307dcf36dcSFrançois Tigeot 317dcf36dcSFrançois Tigeot #include <linux/types.h> 323f2dd94aSFrançois Tigeot #include <linux/bitmap.h> 33*b843c749SSergey Zigachev #include <linux/dma-fence.h> 347dcf36dcSFrançois Tigeot 357dcf36dcSFrançois Tigeot struct pci_dev; 367dcf36dcSFrançois Tigeot 373f2dd94aSFrançois Tigeot #define KFD_INTERFACE_VERSION 2 383f2dd94aSFrançois Tigeot #define KGD_MAX_QUEUES 128 397dcf36dcSFrançois Tigeot 407dcf36dcSFrançois Tigeot struct kfd_dev; 417dcf36dcSFrançois Tigeot struct kgd_dev; 427dcf36dcSFrançois Tigeot 437dcf36dcSFrançois Tigeot struct kgd_mem; 447dcf36dcSFrançois Tigeot 453f2dd94aSFrançois Tigeot enum kfd_preempt_type { 463f2dd94aSFrançois Tigeot KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0, 473f2dd94aSFrançois Tigeot KFD_PREEMPT_TYPE_WAVEFRONT_RESET, 483f2dd94aSFrançois Tigeot }; 493f2dd94aSFrançois Tigeot 50*b843c749SSergey Zigachev struct kfd_vm_fault_info { 51*b843c749SSergey Zigachev uint64_t page_addr; 52*b843c749SSergey Zigachev uint32_t vmid; 53*b843c749SSergey Zigachev uint32_t mc_id; 54*b843c749SSergey Zigachev uint32_t status; 55*b843c749SSergey Zigachev bool prot_valid; 56*b843c749SSergey Zigachev bool prot_read; 57*b843c749SSergey Zigachev bool prot_write; 58*b843c749SSergey Zigachev bool prot_exec; 59*b843c749SSergey Zigachev }; 60*b843c749SSergey Zigachev 61*b843c749SSergey Zigachev struct kfd_cu_info { 62*b843c749SSergey Zigachev uint32_t num_shader_engines; 63*b843c749SSergey Zigachev uint32_t num_shader_arrays_per_engine; 64*b843c749SSergey Zigachev uint32_t num_cu_per_sh; 65*b843c749SSergey Zigachev uint32_t cu_active_number; 66*b843c749SSergey Zigachev uint32_t cu_ao_mask; 67*b843c749SSergey Zigachev uint32_t simd_per_cu; 68*b843c749SSergey Zigachev uint32_t max_waves_per_simd; 69*b843c749SSergey Zigachev uint32_t wave_front_size; 70*b843c749SSergey Zigachev uint32_t max_scratch_slots_per_cu; 71*b843c749SSergey Zigachev uint32_t lds_size; 72*b843c749SSergey Zigachev uint32_t cu_bitmap[4][4]; 73*b843c749SSergey Zigachev }; 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev /* For getting GPU local memory information from KGD */ 76*b843c749SSergey Zigachev struct kfd_local_mem_info { 77*b843c749SSergey Zigachev uint64_t local_mem_size_private; 78*b843c749SSergey Zigachev uint64_t local_mem_size_public; 79*b843c749SSergey Zigachev uint32_t vram_width; 80*b843c749SSergey Zigachev uint32_t mem_clk_max; 81*b843c749SSergey Zigachev }; 82*b843c749SSergey Zigachev 837dcf36dcSFrançois Tigeot enum kgd_memory_pool { 847dcf36dcSFrançois Tigeot KGD_POOL_SYSTEM_CACHEABLE = 1, 857dcf36dcSFrançois Tigeot KGD_POOL_SYSTEM_WRITECOMBINE = 2, 867dcf36dcSFrançois Tigeot KGD_POOL_FRAMEBUFFER = 3, 877dcf36dcSFrançois Tigeot }; 887dcf36dcSFrançois Tigeot 897dcf36dcSFrançois Tigeot enum kgd_engine_type { 907dcf36dcSFrançois Tigeot KGD_ENGINE_PFP = 1, 917dcf36dcSFrançois Tigeot KGD_ENGINE_ME, 927dcf36dcSFrançois Tigeot KGD_ENGINE_CE, 937dcf36dcSFrançois Tigeot KGD_ENGINE_MEC1, 947dcf36dcSFrançois Tigeot KGD_ENGINE_MEC2, 957dcf36dcSFrançois Tigeot KGD_ENGINE_RLC, 96c59a5c48SFrançois Tigeot KGD_ENGINE_SDMA1, 97c59a5c48SFrançois Tigeot KGD_ENGINE_SDMA2, 987dcf36dcSFrançois Tigeot KGD_ENGINE_MAX 997dcf36dcSFrançois Tigeot }; 1007dcf36dcSFrançois Tigeot 1017dcf36dcSFrançois Tigeot struct kgd2kfd_shared_resources { 1027dcf36dcSFrançois Tigeot /* Bit n == 1 means VMID n is available for KFD. */ 1037dcf36dcSFrançois Tigeot unsigned int compute_vmid_bitmap; 1047dcf36dcSFrançois Tigeot 1053f2dd94aSFrançois Tigeot /* number of pipes per mec */ 1063f2dd94aSFrançois Tigeot uint32_t num_pipe_per_mec; 1077dcf36dcSFrançois Tigeot 1083f2dd94aSFrançois Tigeot /* number of queues per pipe */ 1093f2dd94aSFrançois Tigeot uint32_t num_queue_per_pipe; 1103f2dd94aSFrançois Tigeot 1113f2dd94aSFrançois Tigeot /* Bit n == 1 means Queue n is available for KFD */ 1123f2dd94aSFrançois Tigeot DECLARE_BITMAP(queue_bitmap, KGD_MAX_QUEUES); 1137dcf36dcSFrançois Tigeot 114*b843c749SSergey Zigachev /* Doorbell assignments (SOC15 and later chips only). Only 115*b843c749SSergey Zigachev * specific doorbells are routed to each SDMA engine. Others 116*b843c749SSergey Zigachev * are routed to IH and VCN. They are not usable by the CP. 117*b843c749SSergey Zigachev * 118*b843c749SSergey Zigachev * Any doorbell number D that satisfies the following condition 119*b843c749SSergey Zigachev * is reserved: (D & reserved_doorbell_mask) == reserved_doorbell_val 120*b843c749SSergey Zigachev * 121*b843c749SSergey Zigachev * KFD currently uses 1024 (= 0x3ff) doorbells per process. If 122*b843c749SSergey Zigachev * doorbells 0x0f0-0x0f7 and 0x2f-0x2f7 are reserved, that means 123*b843c749SSergey Zigachev * mask would be set to 0x1f8 and val set to 0x0f0. 124*b843c749SSergey Zigachev */ 125*b843c749SSergey Zigachev unsigned int sdma_doorbell[2][2]; 126*b843c749SSergey Zigachev unsigned int reserved_doorbell_mask; 127*b843c749SSergey Zigachev unsigned int reserved_doorbell_val; 128*b843c749SSergey Zigachev 1297dcf36dcSFrançois Tigeot /* Base address of doorbell aperture. */ 1307dcf36dcSFrançois Tigeot phys_addr_t doorbell_physical_address; 1317dcf36dcSFrançois Tigeot 1327dcf36dcSFrançois Tigeot /* Size in bytes of doorbell aperture. */ 1337dcf36dcSFrançois Tigeot size_t doorbell_aperture_size; 1347dcf36dcSFrançois Tigeot 1357dcf36dcSFrançois Tigeot /* Number of bytes at start of aperture reserved for KGD. */ 1367dcf36dcSFrançois Tigeot size_t doorbell_start_offset; 137*b843c749SSergey Zigachev 138*b843c749SSergey Zigachev /* GPUVM address space size in bytes */ 139*b843c749SSergey Zigachev uint64_t gpuvm_size; 140*b843c749SSergey Zigachev 141*b843c749SSergey Zigachev /* Minor device number of the render node */ 142*b843c749SSergey Zigachev int drm_render_minor; 1437dcf36dcSFrançois Tigeot }; 1447dcf36dcSFrançois Tigeot 1453f2dd94aSFrançois Tigeot struct tile_config { 1463f2dd94aSFrançois Tigeot uint32_t *tile_config_ptr; 1473f2dd94aSFrançois Tigeot uint32_t *macro_tile_config_ptr; 1483f2dd94aSFrançois Tigeot uint32_t num_tile_configs; 1493f2dd94aSFrançois Tigeot uint32_t num_macro_tile_configs; 1503f2dd94aSFrançois Tigeot 1513f2dd94aSFrançois Tigeot uint32_t gb_addr_config; 1523f2dd94aSFrançois Tigeot uint32_t num_banks; 1533f2dd94aSFrançois Tigeot uint32_t num_ranks; 1543f2dd94aSFrançois Tigeot }; 1553f2dd94aSFrançois Tigeot 156*b843c749SSergey Zigachev 157*b843c749SSergey Zigachev /* 158*b843c749SSergey Zigachev * Allocation flag domains 159*b843c749SSergey Zigachev * NOTE: This must match the corresponding definitions in kfd_ioctl.h. 160*b843c749SSergey Zigachev */ 161*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_VRAM (1 << 0) 162*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_GTT (1 << 1) 163*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_USERPTR (1 << 2) /* TODO */ 164*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_DOORBELL (1 << 3) /* TODO */ 165*b843c749SSergey Zigachev 166*b843c749SSergey Zigachev /* 167*b843c749SSergey Zigachev * Allocation flags attributes/access options. 168*b843c749SSergey Zigachev * NOTE: This must match the corresponding definitions in kfd_ioctl.h. 169*b843c749SSergey Zigachev */ 170*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 171*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 172*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 173*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) /* TODO */ 174*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 175*b843c749SSergey Zigachev #define ALLOC_MEM_FLAGS_COHERENT (1 << 26) /* For GFXv9 or later */ 176*b843c749SSergey Zigachev 1777dcf36dcSFrançois Tigeot /** 178c59a5c48SFrançois Tigeot * struct kfd2kgd_calls 179c59a5c48SFrançois Tigeot * 180c59a5c48SFrançois Tigeot * @init_gtt_mem_allocation: Allocate a buffer on the gart aperture. 181c59a5c48SFrançois Tigeot * The buffer can be used for mqds, hpds, kernel queue, fence and runlists 182c59a5c48SFrançois Tigeot * 183c59a5c48SFrançois Tigeot * @free_gtt_mem: Frees a buffer that was allocated on the gart aperture 184c59a5c48SFrançois Tigeot * 185*b843c749SSergey Zigachev * @get_local_mem_info: Retrieves information about GPU local memory 186c59a5c48SFrançois Tigeot * 187c59a5c48SFrançois Tigeot * @get_gpu_clock_counter: Retrieves GPU clock counter 188c59a5c48SFrançois Tigeot * 189c59a5c48SFrançois Tigeot * @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz 190c59a5c48SFrançois Tigeot * 1913f2dd94aSFrançois Tigeot * @alloc_pasid: Allocate a PASID 1923f2dd94aSFrançois Tigeot * @free_pasid: Free a PASID 1933f2dd94aSFrançois Tigeot * 194c59a5c48SFrançois Tigeot * @program_sh_mem_settings: A function that should initiate the memory 195c59a5c48SFrançois Tigeot * properties such as main aperture memory type (cache / non cached) and 196c59a5c48SFrançois Tigeot * secondary aperture base address, size and memory type. 197c59a5c48SFrançois Tigeot * This function is used only for no cp scheduling mode. 198c59a5c48SFrançois Tigeot * 199c59a5c48SFrançois Tigeot * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp 200c59a5c48SFrançois Tigeot * scheduling mode. Only used for no cp scheduling mode. 201c59a5c48SFrançois Tigeot * 202c59a5c48SFrançois Tigeot * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp 203c59a5c48SFrançois Tigeot * sceduling mode. 204c59a5c48SFrançois Tigeot * 205c59a5c48SFrançois Tigeot * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot. 206c59a5c48SFrançois Tigeot * used only for no HWS mode. 207c59a5c48SFrançois Tigeot * 208*b843c749SSergey Zigachev * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs. 209*b843c749SSergey Zigachev * Array is allocated with kmalloc, needs to be freed with kfree by caller. 210*b843c749SSergey Zigachev * 211*b843c749SSergey Zigachev * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs. 212*b843c749SSergey Zigachev * Array is allocated with kmalloc, needs to be freed with kfree by caller. 213*b843c749SSergey Zigachev * 214c59a5c48SFrançois Tigeot * @hqd_is_occupies: Checks if a hqd slot is occupied. 215c59a5c48SFrançois Tigeot * 216c59a5c48SFrançois Tigeot * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot. 217c59a5c48SFrançois Tigeot * 218c59a5c48SFrançois Tigeot * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied. 219c59a5c48SFrançois Tigeot * 220c59a5c48SFrançois Tigeot * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that 221c59a5c48SFrançois Tigeot * SDMA hqd slot. 222c59a5c48SFrançois Tigeot * 223c59a5c48SFrançois Tigeot * @get_fw_version: Returns FW versions from the header 224c59a5c48SFrançois Tigeot * 2253f2dd94aSFrançois Tigeot * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID. 2263f2dd94aSFrançois Tigeot * Only used for no cp scheduling mode 2273f2dd94aSFrançois Tigeot * 2283f2dd94aSFrançois Tigeot * @get_tile_config: Returns GPU-specific tiling mode information 2293f2dd94aSFrançois Tigeot * 230*b843c749SSergey Zigachev * @get_cu_info: Retrieves activated cu info 231*b843c749SSergey Zigachev * 232*b843c749SSergey Zigachev * @get_vram_usage: Returns current VRAM usage 233*b843c749SSergey Zigachev * 234*b843c749SSergey Zigachev * @create_process_vm: Create a VM address space for a given process and GPU 235*b843c749SSergey Zigachev * 236*b843c749SSergey Zigachev * @destroy_process_vm: Destroy a VM 237*b843c749SSergey Zigachev * 238*b843c749SSergey Zigachev * @get_process_page_dir: Get physical address of a VM page directory 239*b843c749SSergey Zigachev * 240*b843c749SSergey Zigachev * @set_vm_context_page_table_base: Program page table base for a VMID 241*b843c749SSergey Zigachev * 242*b843c749SSergey Zigachev * @alloc_memory_of_gpu: Allocate GPUVM memory 243*b843c749SSergey Zigachev * 244*b843c749SSergey Zigachev * @free_memory_of_gpu: Free GPUVM memory 245*b843c749SSergey Zigachev * 246*b843c749SSergey Zigachev * @map_memory_to_gpu: Map GPUVM memory into a specific VM address 247*b843c749SSergey Zigachev * space. Allocates and updates page tables and page directories as 248*b843c749SSergey Zigachev * needed. This function may return before all page table updates have 249*b843c749SSergey Zigachev * completed. This allows multiple map operations (on multiple GPUs) 250*b843c749SSergey Zigachev * to happen concurrently. Use sync_memory to synchronize with all 251*b843c749SSergey Zigachev * pending updates. 252*b843c749SSergey Zigachev * 253*b843c749SSergey Zigachev * @unmap_memor_to_gpu: Unmap GPUVM memory from a specific VM address space 254*b843c749SSergey Zigachev * 255*b843c749SSergey Zigachev * @sync_memory: Wait for pending page table updates to complete 256*b843c749SSergey Zigachev * 257*b843c749SSergey Zigachev * @map_gtt_bo_to_kernel: Map a GTT BO for kernel access 258*b843c749SSergey Zigachev * Pins the BO, maps it to kernel address space. Such BOs are never evicted. 259*b843c749SSergey Zigachev * The kernel virtual address remains valid until the BO is freed. 260*b843c749SSergey Zigachev * 261*b843c749SSergey Zigachev * @restore_process_bos: Restore all BOs that belong to the 262*b843c749SSergey Zigachev * process. This is intended for restoring memory mappings after a TTM 263*b843c749SSergey Zigachev * eviction. 264*b843c749SSergey Zigachev * 265*b843c749SSergey Zigachev * @invalidate_tlbs: Invalidate TLBs for a specific PASID 266*b843c749SSergey Zigachev * 267*b843c749SSergey Zigachev * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID 268*b843c749SSergey Zigachev * 269*b843c749SSergey Zigachev * @submit_ib: Submits an IB to the engine specified by inserting the 270*b843c749SSergey Zigachev * IB to the corresponding ring (ring type). The IB is executed with the 271*b843c749SSergey Zigachev * specified VMID in a user mode context. 272*b843c749SSergey Zigachev * 273*b843c749SSergey Zigachev * @get_vm_fault_info: Return information about a recent VM fault on 274*b843c749SSergey Zigachev * GFXv7 and v8. If multiple VM faults occurred since the last call of 275*b843c749SSergey Zigachev * this function, it will return information about the first of those 276*b843c749SSergey Zigachev * faults. On GFXv9 VM fault information is fully contained in the IH 277*b843c749SSergey Zigachev * packet and this function is not needed. 278*b843c749SSergey Zigachev * 279*b843c749SSergey Zigachev * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the 280*b843c749SSergey Zigachev * IH ring entry. This function allows the KFD ISR to get the VMID 281*b843c749SSergey Zigachev * from the fault status register as early as possible. 282*b843c749SSergey Zigachev * 283*b843c749SSergey Zigachev * @gpu_recover: let kgd reset gpu after kfd detect CPC hang 284*b843c749SSergey Zigachev * 285*b843c749SSergey Zigachev * @set_compute_idle: Indicates that compute is idle on a device. This 286*b843c749SSergey Zigachev * can be used to change power profiles depending on compute activity. 287*b843c749SSergey Zigachev * 288c59a5c48SFrançois Tigeot * This structure contains function pointers to services that the kgd driver 289c59a5c48SFrançois Tigeot * provides to amdkfd driver. 290c59a5c48SFrançois Tigeot * 291c59a5c48SFrançois Tigeot */ 292c59a5c48SFrançois Tigeot struct kfd2kgd_calls { 293c59a5c48SFrançois Tigeot int (*init_gtt_mem_allocation)(struct kgd_dev *kgd, size_t size, 294c59a5c48SFrançois Tigeot void **mem_obj, uint64_t *gpu_addr, 295*b843c749SSergey Zigachev void **cpu_ptr, bool mqd_gfx9); 296c59a5c48SFrançois Tigeot 297c59a5c48SFrançois Tigeot void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj); 298c59a5c48SFrançois Tigeot 299*b843c749SSergey Zigachev void (*get_local_mem_info)(struct kgd_dev *kgd, 300*b843c749SSergey Zigachev struct kfd_local_mem_info *mem_info); 301c59a5c48SFrançois Tigeot uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd); 302c59a5c48SFrançois Tigeot 303c59a5c48SFrançois Tigeot uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd); 304c59a5c48SFrançois Tigeot 3053f2dd94aSFrançois Tigeot int (*alloc_pasid)(unsigned int bits); 3063f2dd94aSFrançois Tigeot void (*free_pasid)(unsigned int pasid); 3073f2dd94aSFrançois Tigeot 308c59a5c48SFrançois Tigeot /* Register access functions */ 309c59a5c48SFrançois Tigeot void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid, 310c59a5c48SFrançois Tigeot uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, 311c59a5c48SFrançois Tigeot uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); 312c59a5c48SFrançois Tigeot 313c59a5c48SFrançois Tigeot int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid, 314c59a5c48SFrançois Tigeot unsigned int vmid); 315c59a5c48SFrançois Tigeot 316c59a5c48SFrançois Tigeot int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id); 317c59a5c48SFrançois Tigeot 318c59a5c48SFrançois Tigeot int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 3193f2dd94aSFrançois Tigeot uint32_t queue_id, uint32_t __user *wptr, 3203f2dd94aSFrançois Tigeot uint32_t wptr_shift, uint32_t wptr_mask, 3213f2dd94aSFrançois Tigeot struct mm_struct *mm); 322c59a5c48SFrançois Tigeot 323*b843c749SSergey Zigachev int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd, 324*b843c749SSergey Zigachev uint32_t __user *wptr, struct mm_struct *mm); 325*b843c749SSergey Zigachev 326*b843c749SSergey Zigachev int (*hqd_dump)(struct kgd_dev *kgd, 327*b843c749SSergey Zigachev uint32_t pipe_id, uint32_t queue_id, 328*b843c749SSergey Zigachev uint32_t (**dump)[2], uint32_t *n_regs); 329*b843c749SSergey Zigachev 330*b843c749SSergey Zigachev int (*hqd_sdma_dump)(struct kgd_dev *kgd, 331*b843c749SSergey Zigachev uint32_t engine_id, uint32_t queue_id, 332*b843c749SSergey Zigachev uint32_t (**dump)[2], uint32_t *n_regs); 333c59a5c48SFrançois Tigeot 334c59a5c48SFrançois Tigeot bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address, 335c59a5c48SFrançois Tigeot uint32_t pipe_id, uint32_t queue_id); 336c59a5c48SFrançois Tigeot 3373f2dd94aSFrançois Tigeot int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type, 338c59a5c48SFrançois Tigeot unsigned int timeout, uint32_t pipe_id, 339c59a5c48SFrançois Tigeot uint32_t queue_id); 340c59a5c48SFrançois Tigeot 341c59a5c48SFrançois Tigeot bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd); 342c59a5c48SFrançois Tigeot 343c59a5c48SFrançois Tigeot int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd, 344c59a5c48SFrançois Tigeot unsigned int timeout); 345c59a5c48SFrançois Tigeot 346c59a5c48SFrançois Tigeot int (*address_watch_disable)(struct kgd_dev *kgd); 347c59a5c48SFrançois Tigeot int (*address_watch_execute)(struct kgd_dev *kgd, 348c59a5c48SFrançois Tigeot unsigned int watch_point_id, 349c59a5c48SFrançois Tigeot uint32_t cntl_val, 350c59a5c48SFrançois Tigeot uint32_t addr_hi, 351c59a5c48SFrançois Tigeot uint32_t addr_lo); 352c59a5c48SFrançois Tigeot int (*wave_control_execute)(struct kgd_dev *kgd, 353c59a5c48SFrançois Tigeot uint32_t gfx_index_val, 354c59a5c48SFrançois Tigeot uint32_t sq_cmd); 355c59a5c48SFrançois Tigeot uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd, 356c59a5c48SFrançois Tigeot unsigned int watch_point_id, 357c59a5c48SFrançois Tigeot unsigned int reg_offset); 358c59a5c48SFrançois Tigeot bool (*get_atc_vmid_pasid_mapping_valid)( 359c59a5c48SFrançois Tigeot struct kgd_dev *kgd, 360c59a5c48SFrançois Tigeot uint8_t vmid); 361c59a5c48SFrançois Tigeot uint16_t (*get_atc_vmid_pasid_mapping_pasid)( 362c59a5c48SFrançois Tigeot struct kgd_dev *kgd, 363c59a5c48SFrançois Tigeot uint8_t vmid); 364c59a5c48SFrançois Tigeot 365c59a5c48SFrançois Tigeot uint16_t (*get_fw_version)(struct kgd_dev *kgd, 366c59a5c48SFrançois Tigeot enum kgd_engine_type type); 3673f2dd94aSFrançois Tigeot void (*set_scratch_backing_va)(struct kgd_dev *kgd, 3683f2dd94aSFrançois Tigeot uint64_t va, uint32_t vmid); 3693f2dd94aSFrançois Tigeot int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config); 370*b843c749SSergey Zigachev 371*b843c749SSergey Zigachev void (*get_cu_info)(struct kgd_dev *kgd, 372*b843c749SSergey Zigachev struct kfd_cu_info *cu_info); 373*b843c749SSergey Zigachev uint64_t (*get_vram_usage)(struct kgd_dev *kgd); 374*b843c749SSergey Zigachev 375*b843c749SSergey Zigachev int (*create_process_vm)(struct kgd_dev *kgd, void **vm, 376*b843c749SSergey Zigachev void **process_info, struct dma_fence **ef); 377*b843c749SSergey Zigachev int (*acquire_process_vm)(struct kgd_dev *kgd, struct file *filp, 378*b843c749SSergey Zigachev void **vm, void **process_info, struct dma_fence **ef); 379*b843c749SSergey Zigachev void (*destroy_process_vm)(struct kgd_dev *kgd, void *vm); 380*b843c749SSergey Zigachev uint32_t (*get_process_page_dir)(void *vm); 381*b843c749SSergey Zigachev void (*set_vm_context_page_table_base)(struct kgd_dev *kgd, 382*b843c749SSergey Zigachev uint32_t vmid, uint32_t page_table_base); 383*b843c749SSergey Zigachev int (*alloc_memory_of_gpu)(struct kgd_dev *kgd, uint64_t va, 384*b843c749SSergey Zigachev uint64_t size, void *vm, 385*b843c749SSergey Zigachev struct kgd_mem **mem, uint64_t *offset, 386*b843c749SSergey Zigachev uint32_t flags); 387*b843c749SSergey Zigachev int (*free_memory_of_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem); 388*b843c749SSergey Zigachev int (*map_memory_to_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem, 389*b843c749SSergey Zigachev void *vm); 390*b843c749SSergey Zigachev int (*unmap_memory_to_gpu)(struct kgd_dev *kgd, struct kgd_mem *mem, 391*b843c749SSergey Zigachev void *vm); 392*b843c749SSergey Zigachev int (*sync_memory)(struct kgd_dev *kgd, struct kgd_mem *mem, bool intr); 393*b843c749SSergey Zigachev int (*map_gtt_bo_to_kernel)(struct kgd_dev *kgd, struct kgd_mem *mem, 394*b843c749SSergey Zigachev void **kptr, uint64_t *size); 395*b843c749SSergey Zigachev int (*restore_process_bos)(void *process_info, struct dma_fence **ef); 396*b843c749SSergey Zigachev 397*b843c749SSergey Zigachev int (*invalidate_tlbs)(struct kgd_dev *kgd, uint16_t pasid); 398*b843c749SSergey Zigachev int (*invalidate_tlbs_vmid)(struct kgd_dev *kgd, uint16_t vmid); 399*b843c749SSergey Zigachev 400*b843c749SSergey Zigachev int (*submit_ib)(struct kgd_dev *kgd, enum kgd_engine_type engine, 401*b843c749SSergey Zigachev uint32_t vmid, uint64_t gpu_addr, 402*b843c749SSergey Zigachev uint32_t *ib_cmd, uint32_t ib_len); 403*b843c749SSergey Zigachev 404*b843c749SSergey Zigachev int (*get_vm_fault_info)(struct kgd_dev *kgd, 405*b843c749SSergey Zigachev struct kfd_vm_fault_info *info); 406*b843c749SSergey Zigachev uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd); 407*b843c749SSergey Zigachev 408*b843c749SSergey Zigachev void (*gpu_recover)(struct kgd_dev *kgd); 409*b843c749SSergey Zigachev 410*b843c749SSergey Zigachev void (*set_compute_idle)(struct kgd_dev *kgd, bool idle); 411c59a5c48SFrançois Tigeot }; 412c59a5c48SFrançois Tigeot 413c59a5c48SFrançois Tigeot /** 4147dcf36dcSFrançois Tigeot * struct kgd2kfd_calls 4157dcf36dcSFrançois Tigeot * 4167dcf36dcSFrançois Tigeot * @exit: Notifies amdkfd that kgd module is unloaded 4177dcf36dcSFrançois Tigeot * 4187dcf36dcSFrançois Tigeot * @probe: Notifies amdkfd about a probe done on a device in the kgd driver. 4197dcf36dcSFrançois Tigeot * 4207dcf36dcSFrançois Tigeot * @device_init: Initialize the newly probed device (if it is a device that 4217dcf36dcSFrançois Tigeot * amdkfd supports) 4227dcf36dcSFrançois Tigeot * 4237dcf36dcSFrançois Tigeot * @device_exit: Notifies amdkfd about a removal of a kgd device 4247dcf36dcSFrançois Tigeot * 4257dcf36dcSFrançois Tigeot * @suspend: Notifies amdkfd about a suspend action done to a kgd device 4267dcf36dcSFrançois Tigeot * 4277dcf36dcSFrançois Tigeot * @resume: Notifies amdkfd about a resume action done to a kgd device 4287dcf36dcSFrançois Tigeot * 429*b843c749SSergey Zigachev * @quiesce_mm: Quiesce all user queue access to specified MM address space 430*b843c749SSergey Zigachev * 431*b843c749SSergey Zigachev * @resume_mm: Resume user queue access to specified MM address space 432*b843c749SSergey Zigachev * 433*b843c749SSergey Zigachev * @schedule_evict_and_restore_process: Schedules work queue that will prepare 434*b843c749SSergey Zigachev * for safe eviction of KFD BOs that belong to the specified process. 435*b843c749SSergey Zigachev * 436*b843c749SSergey Zigachev * @pre_reset: Notifies amdkfd that amdgpu about to reset the gpu 437*b843c749SSergey Zigachev * 438*b843c749SSergey Zigachev * @post_reset: Notify amdkfd that amgpu successfully reseted the gpu 439*b843c749SSergey Zigachev * 4407dcf36dcSFrançois Tigeot * This structure contains function callback pointers so the kgd driver 4417dcf36dcSFrançois Tigeot * will notify to the amdkfd about certain status changes. 4427dcf36dcSFrançois Tigeot * 4437dcf36dcSFrançois Tigeot */ 4447dcf36dcSFrançois Tigeot struct kgd2kfd_calls { 4457dcf36dcSFrançois Tigeot void (*exit)(void); 446c59a5c48SFrançois Tigeot struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev, 447c59a5c48SFrançois Tigeot const struct kfd2kgd_calls *f2g); 4487dcf36dcSFrançois Tigeot bool (*device_init)(struct kfd_dev *kfd, 4497dcf36dcSFrançois Tigeot const struct kgd2kfd_shared_resources *gpu_resources); 4507dcf36dcSFrançois Tigeot void (*device_exit)(struct kfd_dev *kfd); 4517dcf36dcSFrançois Tigeot void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry); 4527dcf36dcSFrançois Tigeot void (*suspend)(struct kfd_dev *kfd); 4537dcf36dcSFrançois Tigeot int (*resume)(struct kfd_dev *kfd); 454*b843c749SSergey Zigachev int (*quiesce_mm)(struct mm_struct *mm); 455*b843c749SSergey Zigachev int (*resume_mm)(struct mm_struct *mm); 456*b843c749SSergey Zigachev int (*schedule_evict_and_restore_process)(struct mm_struct *mm, 457*b843c749SSergey Zigachev struct dma_fence *fence); 458*b843c749SSergey Zigachev int (*pre_reset)(struct kfd_dev *kfd); 459*b843c749SSergey Zigachev int (*post_reset)(struct kfd_dev *kfd); 4607dcf36dcSFrançois Tigeot }; 4617dcf36dcSFrançois Tigeot 462d78d3a22SFrançois Tigeot int kgd2kfd_init(unsigned interface_version, 4637dcf36dcSFrançois Tigeot const struct kgd2kfd_calls **g2f); 4647dcf36dcSFrançois Tigeot 4657dcf36dcSFrançois Tigeot #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ 466