1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef PP_ATOMVOLTAGECTRL_H 25*b843c749SSergey Zigachev #define PP_ATOMVOLTAGECTRL_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "hwmgr.h" 28*b843c749SSergey Zigachev 29*b843c749SSergey Zigachev #define MEM_TYPE_GDDR5 0x50 30*b843c749SSergey Zigachev #define MEM_TYPE_GDDR4 0x40 31*b843c749SSergey Zigachev #define MEM_TYPE_GDDR3 0x30 32*b843c749SSergey Zigachev #define MEM_TYPE_DDR2 0x20 33*b843c749SSergey Zigachev #define MEM_TYPE_GDDR1 0x10 34*b843c749SSergey Zigachev #define MEM_TYPE_DDR3 0xb0 35*b843c749SSergey Zigachev #define MEM_TYPE_MASK 0xF0 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev 38*b843c749SSergey Zigachev /* As returned from PowerConnectorDetectionTable. */ 39*b843c749SSergey Zigachev #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80 40*b843c749SSergey Zigachev #define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40 41*b843c749SSergey Zigachev #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20 42*b843c749SSergey Zigachev #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev /* New functions for Evergreen and beyond. */ 45*b843c749SSergey Zigachev #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32 46*b843c749SSergey Zigachev 47*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers { 48*b843c749SSergey Zigachev uint32_t pll_post_divider; 49*b843c749SSergey Zigachev uint32_t pll_feedback_divider; 50*b843c749SSergey Zigachev uint32_t pll_ref_divider; 51*b843c749SSergey Zigachev bool enable_post_divider; 52*b843c749SSergey Zigachev }; 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers; 55*b843c749SSergey Zigachev 56*b843c749SSergey Zigachev union pp_atomctrl_tcipll_fb_divider { 57*b843c749SSergey Zigachev struct { 58*b843c749SSergey Zigachev uint32_t ul_fb_div_frac : 14; 59*b843c749SSergey Zigachev uint32_t ul_fb_div : 12; 60*b843c749SSergey Zigachev uint32_t un_used : 6; 61*b843c749SSergey Zigachev }; 62*b843c749SSergey Zigachev uint32_t ul_fb_divider; 63*b843c749SSergey Zigachev }; 64*b843c749SSergey Zigachev 65*b843c749SSergey Zigachev typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider; 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_rv730 { 68*b843c749SSergey Zigachev uint32_t pll_post_divider; 69*b843c749SSergey Zigachev pp_atomctrl_tcipll_fb_divider mpll_feedback_divider; 70*b843c749SSergey Zigachev uint32_t pll_ref_divider; 71*b843c749SSergey Zigachev bool enable_post_divider; 72*b843c749SSergey Zigachev bool enable_dithen; 73*b843c749SSergey Zigachev uint32_t vco_mode; 74*b843c749SSergey Zigachev }; 75*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730; 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev 78*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_kong { 79*b843c749SSergey Zigachev uint32_t pll_post_divider; 80*b843c749SSergey Zigachev uint32_t real_clock; 81*b843c749SSergey Zigachev }; 82*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong; 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_ci { 85*b843c749SSergey Zigachev uint32_t pll_post_divider; /* post divider value */ 86*b843c749SSergey Zigachev uint32_t real_clock; 87*b843c749SSergey Zigachev pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */ 88*b843c749SSergey Zigachev uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */ 89*b843c749SSergey Zigachev uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */ 90*b843c749SSergey Zigachev uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 91*b843c749SSergey Zigachev }; 92*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci; 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_vi { 95*b843c749SSergey Zigachev uint32_t pll_post_divider; /* post divider value */ 96*b843c749SSergey Zigachev uint32_t real_clock; 97*b843c749SSergey Zigachev pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */ 98*b843c749SSergey Zigachev uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */ 99*b843c749SSergey Zigachev uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */ 100*b843c749SSergey Zigachev uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 101*b843c749SSergey Zigachev }; 102*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi; 103*b843c749SSergey Zigachev 104*b843c749SSergey Zigachev struct pp_atomctrl_clock_dividers_ai { 105*b843c749SSergey Zigachev u16 usSclk_fcw_frac; 106*b843c749SSergey Zigachev u16 usSclk_fcw_int; 107*b843c749SSergey Zigachev u8 ucSclkPostDiv; 108*b843c749SSergey Zigachev u8 ucSclkVcoMode; 109*b843c749SSergey Zigachev u8 ucSclkPllRange; 110*b843c749SSergey Zigachev u8 ucSscEnable; 111*b843c749SSergey Zigachev u16 usSsc_fcw1_frac; 112*b843c749SSergey Zigachev u16 usSsc_fcw1_int; 113*b843c749SSergey Zigachev u16 usReserved; 114*b843c749SSergey Zigachev u16 usPcc_fcw_int; 115*b843c749SSergey Zigachev u16 usSsc_fcw_slew_frac; 116*b843c749SSergey Zigachev u16 usPcc_fcw_slew_frac; 117*b843c749SSergey Zigachev }; 118*b843c749SSergey Zigachev typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai; 119*b843c749SSergey Zigachev 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev union pp_atomctrl_s_mpll_fb_divider { 122*b843c749SSergey Zigachev struct { 123*b843c749SSergey Zigachev uint32_t cl_kf : 12; 124*b843c749SSergey Zigachev uint32_t clk_frac : 12; 125*b843c749SSergey Zigachev uint32_t un_used : 8; 126*b843c749SSergey Zigachev }; 127*b843c749SSergey Zigachev uint32_t ul_fb_divider; 128*b843c749SSergey Zigachev }; 129*b843c749SSergey Zigachev typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider; 130*b843c749SSergey Zigachev 131*b843c749SSergey Zigachev enum pp_atomctrl_spread_spectrum_mode { 132*b843c749SSergey Zigachev pp_atomctrl_spread_spectrum_mode_down = 0, 133*b843c749SSergey Zigachev pp_atomctrl_spread_spectrum_mode_center 134*b843c749SSergey Zigachev }; 135*b843c749SSergey Zigachev typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode; 136*b843c749SSergey Zigachev 137*b843c749SSergey Zigachev struct pp_atomctrl_memory_clock_param { 138*b843c749SSergey Zigachev pp_atomctrl_s_mpll_fb_divider mpll_fb_divider; 139*b843c749SSergey Zigachev uint32_t mpll_post_divider; 140*b843c749SSergey Zigachev uint32_t bw_ctrl; 141*b843c749SSergey Zigachev uint32_t dll_speed; 142*b843c749SSergey Zigachev uint32_t vco_mode; 143*b843c749SSergey Zigachev uint32_t yclk_sel; 144*b843c749SSergey Zigachev uint32_t qdr; 145*b843c749SSergey Zigachev uint32_t half_rate; 146*b843c749SSergey Zigachev }; 147*b843c749SSergey Zigachev typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param; 148*b843c749SSergey Zigachev 149*b843c749SSergey Zigachev struct pp_atomctrl_memory_clock_param_ai { 150*b843c749SSergey Zigachev uint32_t ulClock; 151*b843c749SSergey Zigachev uint32_t ulPostDiv; 152*b843c749SSergey Zigachev uint16_t ulMclk_fcw_frac; 153*b843c749SSergey Zigachev uint16_t ulMclk_fcw_int; 154*b843c749SSergey Zigachev }; 155*b843c749SSergey Zigachev typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai; 156*b843c749SSergey Zigachev 157*b843c749SSergey Zigachev struct pp_atomctrl_internal_ss_info { 158*b843c749SSergey Zigachev uint32_t speed_spectrum_percentage; /* in 1/100 percentage */ 159*b843c749SSergey Zigachev uint32_t speed_spectrum_rate; /* in KHz */ 160*b843c749SSergey Zigachev pp_atomctrl_spread_spectrum_mode speed_spectrum_mode; 161*b843c749SSergey Zigachev }; 162*b843c749SSergey Zigachev typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info; 163*b843c749SSergey Zigachev 164*b843c749SSergey Zigachev #ifndef NUMBER_OF_M3ARB_PARAMS 165*b843c749SSergey Zigachev #define NUMBER_OF_M3ARB_PARAMS 3 166*b843c749SSergey Zigachev #endif 167*b843c749SSergey Zigachev 168*b843c749SSergey Zigachev #ifndef NUMBER_OF_M3ARB_PARAM_SETS 169*b843c749SSergey Zigachev #define NUMBER_OF_M3ARB_PARAM_SETS 10 170*b843c749SSergey Zigachev #endif 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev struct pp_atomctrl_kong_system_info { 173*b843c749SSergey Zigachev uint32_t ul_bootup_uma_clock; /* in 10kHz unit */ 174*b843c749SSergey Zigachev uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 175*b843c749SSergey Zigachev uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 176*b843c749SSergey Zigachev uint16_t us_bootup_nb_voltage; /* boot up NB voltage */ 177*b843c749SSergey Zigachev uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */ 178*b843c749SSergey Zigachev uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */ 179*b843c749SSergey Zigachev /* 0: default 1: uvd 2: fs-3d */ 180*b843c749SSergey Zigachev uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */ 181*b843c749SSergey Zigachev }; 182*b843c749SSergey Zigachev typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info; 183*b843c749SSergey Zigachev 184*b843c749SSergey Zigachev struct pp_atomctrl_memory_info { 185*b843c749SSergey Zigachev uint8_t memory_vendor; 186*b843c749SSergey Zigachev uint8_t memory_type; 187*b843c749SSergey Zigachev }; 188*b843c749SSergey Zigachev typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info; 189*b843c749SSergey Zigachev 190*b843c749SSergey Zigachev #define MAX_AC_TIMING_ENTRIES 16 191*b843c749SSergey Zigachev 192*b843c749SSergey Zigachev struct pp_atomctrl_memory_clock_range_table { 193*b843c749SSergey Zigachev uint8_t num_entries; 194*b843c749SSergey Zigachev uint8_t rsv[3]; 195*b843c749SSergey Zigachev 196*b843c749SSergey Zigachev uint32_t mclk[MAX_AC_TIMING_ENTRIES]; 197*b843c749SSergey Zigachev }; 198*b843c749SSergey Zigachev typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table; 199*b843c749SSergey Zigachev 200*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table_entry { 201*b843c749SSergey Zigachev uint16_t value; 202*b843c749SSergey Zigachev uint32_t smio_low; 203*b843c749SSergey Zigachev }; 204*b843c749SSergey Zigachev 205*b843c749SSergey Zigachev typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry; 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table { 208*b843c749SSergey Zigachev uint32_t count; 209*b843c749SSergey Zigachev uint32_t mask_low; 210*b843c749SSergey Zigachev uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */ 211*b843c749SSergey Zigachev pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES]; 212*b843c749SSergey Zigachev }; 213*b843c749SSergey Zigachev 214*b843c749SSergey Zigachev typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table; 215*b843c749SSergey Zigachev 216*b843c749SSergey Zigachev #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 217*b843c749SSergey Zigachev #define VBIOS_MAX_AC_TIMING_ENTRIES 20 218*b843c749SSergey Zigachev 219*b843c749SSergey Zigachev struct pp_atomctrl_mc_reg_entry { 220*b843c749SSergey Zigachev uint32_t mclk_max; 221*b843c749SSergey Zigachev uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 222*b843c749SSergey Zigachev }; 223*b843c749SSergey Zigachev typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry; 224*b843c749SSergey Zigachev 225*b843c749SSergey Zigachev struct pp_atomctrl_mc_register_address { 226*b843c749SSergey Zigachev uint16_t s1; 227*b843c749SSergey Zigachev uint8_t uc_pre_reg_data; 228*b843c749SSergey Zigachev }; 229*b843c749SSergey Zigachev 230*b843c749SSergey Zigachev typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address; 231*b843c749SSergey Zigachev 232*b843c749SSergey Zigachev #define MAX_SCLK_RANGE 8 233*b843c749SSergey Zigachev 234*b843c749SSergey Zigachev struct pp_atom_ctrl_sclk_range_table_entry{ 235*b843c749SSergey Zigachev uint8_t ucVco_setting; 236*b843c749SSergey Zigachev uint8_t ucPostdiv; 237*b843c749SSergey Zigachev uint16_t usFcw_pcc; 238*b843c749SSergey Zigachev uint16_t usFcw_trans_upper; 239*b843c749SSergey Zigachev uint16_t usRcw_trans_lower; 240*b843c749SSergey Zigachev }; 241*b843c749SSergey Zigachev 242*b843c749SSergey Zigachev 243*b843c749SSergey Zigachev struct pp_atom_ctrl_sclk_range_table{ 244*b843c749SSergey Zigachev struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE]; 245*b843c749SSergey Zigachev }; 246*b843c749SSergey Zigachev 247*b843c749SSergey Zigachev struct pp_atomctrl_mc_reg_table { 248*b843c749SSergey Zigachev uint8_t last; /* number of registers */ 249*b843c749SSergey Zigachev uint8_t num_entries; /* number of AC timing entries */ 250*b843c749SSergey Zigachev pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 251*b843c749SSergey Zigachev pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 252*b843c749SSergey Zigachev }; 253*b843c749SSergey Zigachev typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table; 254*b843c749SSergey Zigachev 255*b843c749SSergey Zigachev struct pp_atomctrl_gpio_pin_assignment { 256*b843c749SSergey Zigachev uint16_t us_gpio_pin_aindex; 257*b843c749SSergey Zigachev uint8_t uc_gpio_pin_bit_shift; 258*b843c749SSergey Zigachev }; 259*b843c749SSergey Zigachev typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment; 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev struct pp_atom_ctrl__avfs_parameters { 262*b843c749SSergey Zigachev uint32_t ulAVFS_meanNsigma_Acontant0; 263*b843c749SSergey Zigachev uint32_t ulAVFS_meanNsigma_Acontant1; 264*b843c749SSergey Zigachev uint32_t ulAVFS_meanNsigma_Acontant2; 265*b843c749SSergey Zigachev uint16_t usAVFS_meanNsigma_DC_tol_sigma; 266*b843c749SSergey Zigachev uint16_t usAVFS_meanNsigma_Platform_mean; 267*b843c749SSergey Zigachev uint16_t usAVFS_meanNsigma_Platform_sigma; 268*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0; 269*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1; 270*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2; 271*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSON_a0; 272*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSON_a1; 273*b843c749SSergey Zigachev uint32_t ulGB_VDROOP_TABLE_CKSON_a2; 274*b843c749SSergey Zigachev uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 275*b843c749SSergey Zigachev uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2; 276*b843c749SSergey Zigachev uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b; 277*b843c749SSergey Zigachev uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1; 278*b843c749SSergey Zigachev uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2; 279*b843c749SSergey Zigachev uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b; 280*b843c749SSergey Zigachev uint16_t usMaxVoltage_0_25mv; 281*b843c749SSergey Zigachev uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF; 282*b843c749SSergey Zigachev uint8_t ucEnableGB_VDROOP_TABLE_CKSON; 283*b843c749SSergey Zigachev uint8_t ucEnableGB_FUSE_TABLE_CKSOFF; 284*b843c749SSergey Zigachev uint8_t ucEnableGB_FUSE_TABLE_CKSON; 285*b843c749SSergey Zigachev uint16_t usPSM_Age_ComFactor; 286*b843c749SSergey Zigachev uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage; 287*b843c749SSergey Zigachev uint8_t ucReserved; 288*b843c749SSergey Zigachev }; 289*b843c749SSergey Zigachev 290*b843c749SSergey Zigachev extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); 291*b843c749SSergey Zigachev extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 292*b843c749SSergey Zigachev extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); 293*b843c749SSergey Zigachev extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); 294*b843c749SSergey Zigachev extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); 295*b843c749SSergey Zigachev extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); 296*b843c749SSergey Zigachev extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); 297*b843c749SSergey Zigachev extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); 298*b843c749SSergey Zigachev extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); 299*b843c749SSergey Zigachev extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); 300*b843c749SSergey Zigachev extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 301*b843c749SSergey Zigachev extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 302*b843c749SSergey Zigachev extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); 303*b843c749SSergey Zigachev extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); 304*b843c749SSergey Zigachev extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, 305*b843c749SSergey Zigachev uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); 306*b843c749SSergey Zigachev extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, 307*b843c749SSergey Zigachev uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); 308*b843c749SSergey Zigachev extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, 309*b843c749SSergey Zigachev uint32_t clock_value, 310*b843c749SSergey Zigachev pp_atomctrl_clock_dividers_kong *dividers); 311*b843c749SSergey Zigachev extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, 312*b843c749SSergey Zigachev uint16_t end_index, uint32_t mask, uint32_t *efuse); 313*b843c749SSergey Zigachev extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 314*b843c749SSergey Zigachev uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); 315*b843c749SSergey Zigachev extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); 316*b843c749SSergey Zigachev extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, 317*b843c749SSergey Zigachev uint8_t level); 318*b843c749SSergey Zigachev extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 319*b843c749SSergey Zigachev uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); 320*b843c749SSergey Zigachev extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); 321*b843c749SSergey Zigachev 322*b843c749SSergey Zigachev extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); 323*b843c749SSergey Zigachev 324*b843c749SSergey Zigachev extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 325*b843c749SSergey Zigachev uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, 326*b843c749SSergey Zigachev uint16_t *load_line); 327*b843c749SSergey Zigachev 328*b843c749SSergey Zigachev extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, 329*b843c749SSergey Zigachev uint16_t *vddc, uint16_t *vddci, 330*b843c749SSergey Zigachev uint16_t virtual_voltage_id, 331*b843c749SSergey Zigachev uint16_t efuse_voltage_id); 332*b843c749SSergey Zigachev extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); 333*b843c749SSergey Zigachev 334*b843c749SSergey Zigachev extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, 335*b843c749SSergey Zigachev uint32_t *min_vddc); 336*b843c749SSergey Zigachev #endif 337*b843c749SSergey Zigachev 338