1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef PP_ATOMVOLTAGECTRL_H 25 #define PP_ATOMVOLTAGECTRL_H 26 27 #include "hwmgr.h" 28 29 #define MEM_TYPE_GDDR5 0x50 30 #define MEM_TYPE_GDDR4 0x40 31 #define MEM_TYPE_GDDR3 0x30 32 #define MEM_TYPE_DDR2 0x20 33 #define MEM_TYPE_GDDR1 0x10 34 #define MEM_TYPE_DDR3 0xb0 35 #define MEM_TYPE_MASK 0xF0 36 37 38 /* As returned from PowerConnectorDetectionTable. */ 39 #define PP_ATOM_POWER_BUDGET_DISABLE_OVERDRIVE 0x80 40 #define PP_ATOM_POWER_BUDGET_SHOW_WARNING 0x40 41 #define PP_ATOM_POWER_BUDGET_SHOW_WAIVER 0x20 42 #define PP_ATOM_POWER_POWER_BUDGET_BEHAVIOUR 0x0F 43 44 /* New functions for Evergreen and beyond. */ 45 #define PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES 32 46 47 struct pp_atomctrl_clock_dividers { 48 uint32_t pll_post_divider; 49 uint32_t pll_feedback_divider; 50 uint32_t pll_ref_divider; 51 bool enable_post_divider; 52 }; 53 54 typedef struct pp_atomctrl_clock_dividers pp_atomctrl_clock_dividers; 55 56 union pp_atomctrl_tcipll_fb_divider { 57 struct { 58 uint32_t ul_fb_div_frac : 14; 59 uint32_t ul_fb_div : 12; 60 uint32_t un_used : 6; 61 }; 62 uint32_t ul_fb_divider; 63 }; 64 65 typedef union pp_atomctrl_tcipll_fb_divider pp_atomctrl_tcipll_fb_divider; 66 67 struct pp_atomctrl_clock_dividers_rv730 { 68 uint32_t pll_post_divider; 69 pp_atomctrl_tcipll_fb_divider mpll_feedback_divider; 70 uint32_t pll_ref_divider; 71 bool enable_post_divider; 72 bool enable_dithen; 73 uint32_t vco_mode; 74 }; 75 typedef struct pp_atomctrl_clock_dividers_rv730 pp_atomctrl_clock_dividers_rv730; 76 77 78 struct pp_atomctrl_clock_dividers_kong { 79 uint32_t pll_post_divider; 80 uint32_t real_clock; 81 }; 82 typedef struct pp_atomctrl_clock_dividers_kong pp_atomctrl_clock_dividers_kong; 83 84 struct pp_atomctrl_clock_dividers_ci { 85 uint32_t pll_post_divider; /* post divider value */ 86 uint32_t real_clock; 87 pp_atomctrl_tcipll_fb_divider ul_fb_div; /* Output Parameter: PLL FB divider */ 88 uint8_t uc_pll_ref_div; /* Output Parameter: PLL ref divider */ 89 uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */ 90 uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 91 }; 92 typedef struct pp_atomctrl_clock_dividers_ci pp_atomctrl_clock_dividers_ci; 93 94 struct pp_atomctrl_clock_dividers_vi { 95 uint32_t pll_post_divider; /* post divider value */ 96 uint32_t real_clock; 97 pp_atomctrl_tcipll_fb_divider ul_fb_div; /*Output Parameter: PLL FB divider */ 98 uint8_t uc_pll_ref_div; /*Output Parameter: PLL ref divider */ 99 uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */ 100 uint8_t uc_pll_cntl_flag; /*Output Flags: control flag */ 101 }; 102 typedef struct pp_atomctrl_clock_dividers_vi pp_atomctrl_clock_dividers_vi; 103 104 struct pp_atomctrl_clock_dividers_ai { 105 u16 usSclk_fcw_frac; 106 u16 usSclk_fcw_int; 107 u8 ucSclkPostDiv; 108 u8 ucSclkVcoMode; 109 u8 ucSclkPllRange; 110 u8 ucSscEnable; 111 u16 usSsc_fcw1_frac; 112 u16 usSsc_fcw1_int; 113 u16 usReserved; 114 u16 usPcc_fcw_int; 115 u16 usSsc_fcw_slew_frac; 116 u16 usPcc_fcw_slew_frac; 117 }; 118 typedef struct pp_atomctrl_clock_dividers_ai pp_atomctrl_clock_dividers_ai; 119 120 121 union pp_atomctrl_s_mpll_fb_divider { 122 struct { 123 uint32_t cl_kf : 12; 124 uint32_t clk_frac : 12; 125 uint32_t un_used : 8; 126 }; 127 uint32_t ul_fb_divider; 128 }; 129 typedef union pp_atomctrl_s_mpll_fb_divider pp_atomctrl_s_mpll_fb_divider; 130 131 enum pp_atomctrl_spread_spectrum_mode { 132 pp_atomctrl_spread_spectrum_mode_down = 0, 133 pp_atomctrl_spread_spectrum_mode_center 134 }; 135 typedef enum pp_atomctrl_spread_spectrum_mode pp_atomctrl_spread_spectrum_mode; 136 137 struct pp_atomctrl_memory_clock_param { 138 pp_atomctrl_s_mpll_fb_divider mpll_fb_divider; 139 uint32_t mpll_post_divider; 140 uint32_t bw_ctrl; 141 uint32_t dll_speed; 142 uint32_t vco_mode; 143 uint32_t yclk_sel; 144 uint32_t qdr; 145 uint32_t half_rate; 146 }; 147 typedef struct pp_atomctrl_memory_clock_param pp_atomctrl_memory_clock_param; 148 149 struct pp_atomctrl_memory_clock_param_ai { 150 uint32_t ulClock; 151 uint32_t ulPostDiv; 152 uint16_t ulMclk_fcw_frac; 153 uint16_t ulMclk_fcw_int; 154 }; 155 typedef struct pp_atomctrl_memory_clock_param_ai pp_atomctrl_memory_clock_param_ai; 156 157 struct pp_atomctrl_internal_ss_info { 158 uint32_t speed_spectrum_percentage; /* in 1/100 percentage */ 159 uint32_t speed_spectrum_rate; /* in KHz */ 160 pp_atomctrl_spread_spectrum_mode speed_spectrum_mode; 161 }; 162 typedef struct pp_atomctrl_internal_ss_info pp_atomctrl_internal_ss_info; 163 164 #ifndef NUMBER_OF_M3ARB_PARAMS 165 #define NUMBER_OF_M3ARB_PARAMS 3 166 #endif 167 168 #ifndef NUMBER_OF_M3ARB_PARAM_SETS 169 #define NUMBER_OF_M3ARB_PARAM_SETS 10 170 #endif 171 172 struct pp_atomctrl_kong_system_info { 173 uint32_t ul_bootup_uma_clock; /* in 10kHz unit */ 174 uint16_t us_max_nb_voltage; /* high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 175 uint16_t us_min_nb_voltage; /* low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; */ 176 uint16_t us_bootup_nb_voltage; /* boot up NB voltage */ 177 uint8_t uc_htc_tmp_lmt; /* bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD */ 178 uint8_t uc_tj_offset; /* bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD */ 179 /* 0: default 1: uvd 2: fs-3d */ 180 uint32_t ul_csr_m3_srb_cntl[NUMBER_OF_M3ARB_PARAM_SETS][NUMBER_OF_M3ARB_PARAMS];/* arrays with values for CSR M3 arbiter for default */ 181 }; 182 typedef struct pp_atomctrl_kong_system_info pp_atomctrl_kong_system_info; 183 184 struct pp_atomctrl_memory_info { 185 uint8_t memory_vendor; 186 uint8_t memory_type; 187 }; 188 typedef struct pp_atomctrl_memory_info pp_atomctrl_memory_info; 189 190 #define MAX_AC_TIMING_ENTRIES 16 191 192 struct pp_atomctrl_memory_clock_range_table { 193 uint8_t num_entries; 194 uint8_t rsv[3]; 195 196 uint32_t mclk[MAX_AC_TIMING_ENTRIES]; 197 }; 198 typedef struct pp_atomctrl_memory_clock_range_table pp_atomctrl_memory_clock_range_table; 199 200 struct pp_atomctrl_voltage_table_entry { 201 uint16_t value; 202 uint32_t smio_low; 203 }; 204 205 typedef struct pp_atomctrl_voltage_table_entry pp_atomctrl_voltage_table_entry; 206 207 struct pp_atomctrl_voltage_table { 208 uint32_t count; 209 uint32_t mask_low; 210 uint32_t phase_delay; /* Used for ATOM_GPIO_VOLTAGE_OBJECT_V3 and later */ 211 pp_atomctrl_voltage_table_entry entries[PP_ATOMCTRL_MAX_VOLTAGE_ENTRIES]; 212 }; 213 214 typedef struct pp_atomctrl_voltage_table pp_atomctrl_voltage_table; 215 216 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32 217 #define VBIOS_MAX_AC_TIMING_ENTRIES 20 218 219 struct pp_atomctrl_mc_reg_entry { 220 uint32_t mclk_max; 221 uint32_t mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE]; 222 }; 223 typedef struct pp_atomctrl_mc_reg_entry pp_atomctrl_mc_reg_entry; 224 225 struct pp_atomctrl_mc_register_address { 226 uint16_t s1; 227 uint8_t uc_pre_reg_data; 228 }; 229 230 typedef struct pp_atomctrl_mc_register_address pp_atomctrl_mc_register_address; 231 232 #define MAX_SCLK_RANGE 8 233 234 struct pp_atom_ctrl_sclk_range_table_entry{ 235 uint8_t ucVco_setting; 236 uint8_t ucPostdiv; 237 uint16_t usFcw_pcc; 238 uint16_t usFcw_trans_upper; 239 uint16_t usRcw_trans_lower; 240 }; 241 242 243 struct pp_atom_ctrl_sclk_range_table{ 244 struct pp_atom_ctrl_sclk_range_table_entry entry[MAX_SCLK_RANGE]; 245 }; 246 247 struct pp_atomctrl_mc_reg_table { 248 uint8_t last; /* number of registers */ 249 uint8_t num_entries; /* number of AC timing entries */ 250 pp_atomctrl_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES]; 251 pp_atomctrl_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE]; 252 }; 253 typedef struct pp_atomctrl_mc_reg_table pp_atomctrl_mc_reg_table; 254 255 struct pp_atomctrl_gpio_pin_assignment { 256 uint16_t us_gpio_pin_aindex; 257 uint8_t uc_gpio_pin_bit_shift; 258 }; 259 typedef struct pp_atomctrl_gpio_pin_assignment pp_atomctrl_gpio_pin_assignment; 260 261 struct pp_atom_ctrl__avfs_parameters { 262 uint32_t ulAVFS_meanNsigma_Acontant0; 263 uint32_t ulAVFS_meanNsigma_Acontant1; 264 uint32_t ulAVFS_meanNsigma_Acontant2; 265 uint16_t usAVFS_meanNsigma_DC_tol_sigma; 266 uint16_t usAVFS_meanNsigma_Platform_mean; 267 uint16_t usAVFS_meanNsigma_Platform_sigma; 268 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a0; 269 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a1; 270 uint32_t ulGB_VDROOP_TABLE_CKSOFF_a2; 271 uint32_t ulGB_VDROOP_TABLE_CKSON_a0; 272 uint32_t ulGB_VDROOP_TABLE_CKSON_a1; 273 uint32_t ulGB_VDROOP_TABLE_CKSON_a2; 274 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 275 uint16_t usAVFSGB_FUSE_TABLE_CKSOFF_m2; 276 uint32_t ulAVFSGB_FUSE_TABLE_CKSOFF_b; 277 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_m1; 278 uint16_t usAVFSGB_FUSE_TABLE_CKSON_m2; 279 uint32_t ulAVFSGB_FUSE_TABLE_CKSON_b; 280 uint16_t usMaxVoltage_0_25mv; 281 uint8_t ucEnableGB_VDROOP_TABLE_CKSOFF; 282 uint8_t ucEnableGB_VDROOP_TABLE_CKSON; 283 uint8_t ucEnableGB_FUSE_TABLE_CKSOFF; 284 uint8_t ucEnableGB_FUSE_TABLE_CKSON; 285 uint16_t usPSM_Age_ComFactor; 286 uint8_t ucEnableApplyAVFS_CKS_OFF_Voltage; 287 uint8_t ucReserved; 288 }; 289 290 extern bool atomctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pinId, pp_atomctrl_gpio_pin_assignment *gpio_pin_assignment); 291 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage); 292 extern int atomctrl_get_voltage_evv(struct pp_hwmgr *hwmgr, uint16_t virtual_voltage_id, uint16_t *voltage); 293 extern uint32_t atomctrl_get_mpll_reference_clock(struct pp_hwmgr *hwmgr); 294 extern int atomctrl_get_memory_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t memory_clock, pp_atomctrl_internal_ss_info *ssInfo); 295 extern int atomctrl_get_engine_clock_spread_spectrum(struct pp_hwmgr *hwmgr, const uint32_t engine_clock, pp_atomctrl_internal_ss_info *ssInfo); 296 extern int atomctrl_initialize_mc_reg_table(struct pp_hwmgr *hwmgr, uint8_t module_index, pp_atomctrl_mc_reg_table *table); 297 extern int atomctrl_set_engine_dram_timings_rv770(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint32_t memory_clock); 298 extern uint32_t atomctrl_get_reference_clock(struct pp_hwmgr *hwmgr); 299 extern int atomctrl_get_memory_pll_dividers_si(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param, bool strobe_mode); 300 extern int atomctrl_get_engine_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 301 extern int atomctrl_get_dfs_pll_dividers_vi(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_vi *dividers); 302 extern bool atomctrl_is_voltage_controlled_by_gpio_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode); 303 extern int atomctrl_get_voltage_table_v3(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint8_t voltage_mode, pp_atomctrl_voltage_table *voltage_table); 304 extern int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, 305 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param); 306 extern int atomctrl_get_memory_pll_dividers_ai(struct pp_hwmgr *hwmgr, 307 uint32_t clock_value, pp_atomctrl_memory_clock_param_ai *mpll_param); 308 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, 309 uint32_t clock_value, 310 pp_atomctrl_clock_dividers_kong *dividers); 311 extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, 312 uint16_t end_index, uint32_t mask, uint32_t *efuse); 313 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 314 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug); 315 extern int atomctrl_get_engine_pll_dividers_ai(struct pp_hwmgr *hwmgr, uint32_t clock_value, pp_atomctrl_clock_dividers_ai *dividers); 316 extern int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, 317 uint8_t level); 318 extern int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 319 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage); 320 extern int atomctrl_get_smc_sclk_range_table(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl_sclk_range_table *table); 321 322 extern int atomctrl_get_avfs_information(struct pp_hwmgr *hwmgr, struct pp_atom_ctrl__avfs_parameters *param); 323 324 extern int atomctrl_get_svi2_info(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 325 uint8_t *svd_gpio_id, uint8_t *svc_gpio_id, 326 uint16_t *load_line); 327 328 extern int atomctrl_get_leakage_vddc_base_on_leakage(struct pp_hwmgr *hwmgr, 329 uint16_t *vddc, uint16_t *vddci, 330 uint16_t virtual_voltage_id, 331 uint16_t efuse_voltage_id); 332 extern int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id); 333 334 extern void atomctrl_get_voltage_range(struct pp_hwmgr *hwmgr, uint32_t *max_vddc, 335 uint32_t *min_vddc); 336 #endif 337 338