1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "pp_debug.h" 24 #include <linux/delay.h> 25 #include <linux/fb.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 #include <asm/div64.h> 29 #include <drm/amdgpu_drm.h> 30 #include "ppatomctrl.h" 31 #include "atombios.h" 32 #include "pptable_v1_0.h" 33 #include "pppcielanes.h" 34 #include "amd_pcie_helpers.h" 35 #include "hardwaremanager.h" 36 #include "process_pptables_v1_0.h" 37 #include "cgs_common.h" 38 39 #include "smu7_common.h" 40 41 #include "hwmgr.h" 42 #include "smu7_hwmgr.h" 43 #include "smu_ucode_xfer_vi.h" 44 #include "smu7_powertune.h" 45 #include "smu7_dyn_defaults.h" 46 #include "smu7_thermal.h" 47 #include "smu7_clockpowergating.h" 48 #include "processpptables.h" 49 #include "pp_thermal.h" 50 51 #include "ivsrcid/ivsrcid_vislands30.h" 52 53 #define MC_CG_ARB_FREQ_F0 0x0a 54 #define MC_CG_ARB_FREQ_F1 0x0b 55 #define MC_CG_ARB_FREQ_F2 0x0c 56 #define MC_CG_ARB_FREQ_F3 0x0d 57 58 #define MC_CG_SEQ_DRAMCONF_S0 0x05 59 #define MC_CG_SEQ_DRAMCONF_S1 0x06 60 #define MC_CG_SEQ_YCLK_SUSPEND 0x04 61 #define MC_CG_SEQ_YCLK_RESUME 0x0a 62 63 #define SMC_CG_IND_START 0xc0030000 64 #define SMC_CG_IND_END 0xc0040000 65 66 #define MEM_FREQ_LOW_LATENCY 25000 67 #define MEM_FREQ_HIGH_LATENCY 80000 68 69 #define MEM_LATENCY_HIGH 45 70 #define MEM_LATENCY_LOW 35 71 #define MEM_LATENCY_ERR 0xFFFF 72 73 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 74 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 75 #define MC_SEQ_MISC0_GDDR5_VALUE 5 76 77 #define PCIE_BUS_CLK 10000 78 #define TCLK (PCIE_BUS_CLK / 10) 79 80 static const struct profile_mode_setting smu7_profiling[6] = 81 {{1, 0, 100, 30, 1, 0, 100, 10}, 82 {1, 10, 0, 30, 0, 0, 0, 0}, 83 {0, 0, 0, 0, 1, 10, 16, 31}, 84 {1, 0, 11, 50, 1, 0, 100, 10}, 85 {1, 0, 5, 30, 0, 0, 0, 0}, 86 {0, 0, 0, 0, 0, 0, 0, 0}, 87 }; 88 89 #define PPSMC_MSG_SetVBITimeout_VEGAM ((uint16_t) 0x310) 90 91 #define ixPWR_SVI2_PLANE1_LOAD 0xC0200280 92 #define PWR_SVI2_PLANE1_LOAD__PSI1_MASK 0x00000020L 93 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN_MASK 0x00000040L 94 #define PWR_SVI2_PLANE1_LOAD__PSI1__SHIFT 0x00000005 95 #define PWR_SVI2_PLANE1_LOAD__PSI0_EN__SHIFT 0x00000006 96 97 /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ 98 enum DPM_EVENT_SRC { 99 DPM_EVENT_SRC_ANALOG = 0, 100 DPM_EVENT_SRC_EXTERNAL = 1, 101 DPM_EVENT_SRC_DIGITAL = 2, 102 DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 103 DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 104 }; 105 106 static const unsigned long PhwVIslands_Magic = (unsigned long)(PHM_VIslands_Magic); 107 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 108 enum pp_clock_type type, uint32_t mask); 109 110 static struct smu7_power_state *cast_phw_smu7_power_state( 111 struct pp_hw_power_state *hw_ps) 112 { 113 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 114 "Invalid Powerstate Type!", 115 return NULL); 116 117 return (struct smu7_power_state *)hw_ps; 118 } 119 120 static const struct smu7_power_state *cast_const_phw_smu7_power_state( 121 const struct pp_hw_power_state *hw_ps) 122 { 123 PP_ASSERT_WITH_CODE((PhwVIslands_Magic == hw_ps->magic), 124 "Invalid Powerstate Type!", 125 return NULL); 126 127 return (const struct smu7_power_state *)hw_ps; 128 } 129 130 /** 131 * Find the MC microcode version and store it in the HwMgr struct 132 * 133 * @param hwmgr the address of the powerplay hardware manager. 134 * @return always 0 135 */ 136 static int smu7_get_mc_microcode_version(struct pp_hwmgr *hwmgr) 137 { 138 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 0x9F); 139 140 hwmgr->microcode_version_info.MC = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 141 142 return 0; 143 } 144 145 static uint16_t smu7_get_current_pcie_speed(struct pp_hwmgr *hwmgr) 146 { 147 uint32_t speedCntl = 0; 148 149 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 150 speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, 151 ixPCIE_LC_SPEED_CNTL); 152 return((uint16_t)PHM_GET_FIELD(speedCntl, 153 PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); 154 } 155 156 static int smu7_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr) 157 { 158 uint32_t link_width; 159 160 /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ 161 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 162 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD); 163 164 PP_ASSERT_WITH_CODE((7 >= link_width), 165 "Invalid PCIe lane width!", return 0); 166 167 return decode_pcie_lane_width(link_width); 168 } 169 170 /** 171 * Enable voltage control 172 * 173 * @param pHwMgr the address of the powerplay hardware manager. 174 * @return always PP_Result_OK 175 */ 176 static int smu7_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) 177 { 178 if (hwmgr->chip_id == CHIP_VEGAM) { 179 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 180 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI1, 0); 181 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, 182 CGS_IND_REG__SMC, PWR_SVI2_PLANE1_LOAD, PSI0_EN, 0); 183 } 184 185 if (hwmgr->feature_mask & PP_SMC_VOLTAGE_CONTROL_MASK) 186 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Enable); 187 188 return 0; 189 } 190 191 /** 192 * Checks if we want to support voltage control 193 * 194 * @param hwmgr the address of the powerplay hardware manager. 195 */ 196 static bool smu7_voltage_control(const struct pp_hwmgr *hwmgr) 197 { 198 const struct smu7_hwmgr *data = 199 (const struct smu7_hwmgr *)(hwmgr->backend); 200 201 return (SMU7_VOLTAGE_CONTROL_NONE != data->voltage_control); 202 } 203 204 /** 205 * Enable voltage control 206 * 207 * @param hwmgr the address of the powerplay hardware manager. 208 * @return always 0 209 */ 210 static int smu7_enable_voltage_control(struct pp_hwmgr *hwmgr) 211 { 212 /* enable voltage control */ 213 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 214 GENERAL_PWRMGT, VOLT_PWRMGT_EN, 1); 215 216 return 0; 217 } 218 219 static int phm_get_svi2_voltage_table_v0(pp_atomctrl_voltage_table *voltage_table, 220 struct phm_clock_voltage_dependency_table *voltage_dependency_table 221 ) 222 { 223 uint32_t i; 224 225 PP_ASSERT_WITH_CODE((NULL != voltage_table), 226 "Voltage Dependency Table empty.", return -EINVAL;); 227 228 voltage_table->mask_low = 0; 229 voltage_table->phase_delay = 0; 230 voltage_table->count = voltage_dependency_table->count; 231 232 for (i = 0; i < voltage_dependency_table->count; i++) { 233 voltage_table->entries[i].value = 234 voltage_dependency_table->entries[i].v; 235 voltage_table->entries[i].smio_low = 0; 236 } 237 238 return 0; 239 } 240 241 242 /** 243 * Create Voltage Tables. 244 * 245 * @param hwmgr the address of the powerplay hardware manager. 246 * @return always 0 247 */ 248 static int smu7_construct_voltage_tables(struct pp_hwmgr *hwmgr) 249 { 250 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 251 struct phm_ppt_v1_information *table_info = 252 (struct phm_ppt_v1_information *)hwmgr->pptable; 253 int result = 0; 254 uint32_t tmp; 255 256 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { 257 result = atomctrl_get_voltage_table_v3(hwmgr, 258 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, 259 &(data->mvdd_voltage_table)); 260 PP_ASSERT_WITH_CODE((0 == result), 261 "Failed to retrieve MVDD table.", 262 return result); 263 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { 264 if (hwmgr->pp_table_version == PP_TABLE_V1) 265 result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), 266 table_info->vdd_dep_on_mclk); 267 else if (hwmgr->pp_table_version == PP_TABLE_V0) 268 result = phm_get_svi2_voltage_table_v0(&(data->mvdd_voltage_table), 269 hwmgr->dyn_state.mvdd_dependency_on_mclk); 270 271 PP_ASSERT_WITH_CODE((0 == result), 272 "Failed to retrieve SVI2 MVDD table from dependancy table.", 273 return result;); 274 } 275 276 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { 277 result = atomctrl_get_voltage_table_v3(hwmgr, 278 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, 279 &(data->vddci_voltage_table)); 280 PP_ASSERT_WITH_CODE((0 == result), 281 "Failed to retrieve VDDCI table.", 282 return result); 283 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { 284 if (hwmgr->pp_table_version == PP_TABLE_V1) 285 result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), 286 table_info->vdd_dep_on_mclk); 287 else if (hwmgr->pp_table_version == PP_TABLE_V0) 288 result = phm_get_svi2_voltage_table_v0(&(data->vddci_voltage_table), 289 hwmgr->dyn_state.vddci_dependency_on_mclk); 290 PP_ASSERT_WITH_CODE((0 == result), 291 "Failed to retrieve SVI2 VDDCI table from dependancy table.", 292 return result); 293 } 294 295 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) { 296 /* VDDGFX has only SVI2 voltage control */ 297 result = phm_get_svi2_vdd_voltage_table(&(data->vddgfx_voltage_table), 298 table_info->vddgfx_lookup_table); 299 PP_ASSERT_WITH_CODE((0 == result), 300 "Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;); 301 } 302 303 304 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) { 305 result = atomctrl_get_voltage_table_v3(hwmgr, 306 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT, 307 &data->vddc_voltage_table); 308 PP_ASSERT_WITH_CODE((0 == result), 309 "Failed to retrieve VDDC table.", return result;); 310 } else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { 311 312 if (hwmgr->pp_table_version == PP_TABLE_V0) 313 result = phm_get_svi2_voltage_table_v0(&data->vddc_voltage_table, 314 hwmgr->dyn_state.vddc_dependency_on_mclk); 315 else if (hwmgr->pp_table_version == PP_TABLE_V1) 316 result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), 317 table_info->vddc_lookup_table); 318 319 PP_ASSERT_WITH_CODE((0 == result), 320 "Failed to retrieve SVI2 VDDC table from dependancy table.", return result;); 321 } 322 323 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDC); 324 PP_ASSERT_WITH_CODE( 325 (data->vddc_voltage_table.count <= tmp), 326 "Too many voltage values for VDDC. Trimming to fit state table.", 327 phm_trim_voltage_table_to_fit_state_table(tmp, 328 &(data->vddc_voltage_table))); 329 330 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 331 PP_ASSERT_WITH_CODE( 332 (data->vddgfx_voltage_table.count <= tmp), 333 "Too many voltage values for VDDC. Trimming to fit state table.", 334 phm_trim_voltage_table_to_fit_state_table(tmp, 335 &(data->vddgfx_voltage_table))); 336 337 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDCI); 338 PP_ASSERT_WITH_CODE( 339 (data->vddci_voltage_table.count <= tmp), 340 "Too many voltage values for VDDCI. Trimming to fit state table.", 341 phm_trim_voltage_table_to_fit_state_table(tmp, 342 &(data->vddci_voltage_table))); 343 344 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_MVDD); 345 PP_ASSERT_WITH_CODE( 346 (data->mvdd_voltage_table.count <= tmp), 347 "Too many voltage values for MVDD. Trimming to fit state table.", 348 phm_trim_voltage_table_to_fit_state_table(tmp, 349 &(data->mvdd_voltage_table))); 350 351 return 0; 352 } 353 354 /** 355 * Programs static screed detection parameters 356 * 357 * @param hwmgr the address of the powerplay hardware manager. 358 * @return always 0 359 */ 360 static int smu7_program_static_screen_threshold_parameters( 361 struct pp_hwmgr *hwmgr) 362 { 363 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 364 365 /* Set static screen threshold unit */ 366 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 367 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD_UNIT, 368 data->static_screen_threshold_unit); 369 /* Set static screen threshold */ 370 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 371 CG_STATIC_SCREEN_PARAMETER, STATIC_SCREEN_THRESHOLD, 372 data->static_screen_threshold); 373 374 return 0; 375 } 376 377 /** 378 * Setup display gap for glitch free memory clock switching. 379 * 380 * @param hwmgr the address of the powerplay hardware manager. 381 * @return always 0 382 */ 383 static int smu7_enable_display_gap(struct pp_hwmgr *hwmgr) 384 { 385 uint32_t display_gap = 386 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 387 ixCG_DISPLAY_GAP_CNTL); 388 389 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 390 DISP_GAP, DISPLAY_GAP_IGNORE); 391 392 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, 393 DISP_GAP_MCHG, DISPLAY_GAP_VBLANK); 394 395 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 396 ixCG_DISPLAY_GAP_CNTL, display_gap); 397 398 return 0; 399 } 400 401 /** 402 * Programs activity state transition voting clients 403 * 404 * @param hwmgr the address of the powerplay hardware manager. 405 * @return always 0 406 */ 407 static int smu7_program_voting_clients(struct pp_hwmgr *hwmgr) 408 { 409 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 410 int i; 411 412 /* Clear reset for voting clients before enabling DPM */ 413 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 414 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 0); 415 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 416 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 0); 417 418 for (i = 0; i < 8; i++) 419 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 420 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 421 data->voting_rights_clients[i]); 422 return 0; 423 } 424 425 static int smu7_clear_voting_clients(struct pp_hwmgr *hwmgr) 426 { 427 int i; 428 429 /* Reset voting clients before disabling DPM */ 430 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 431 SCLK_PWRMGT_CNTL, RESET_SCLK_CNT, 1); 432 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 433 SCLK_PWRMGT_CNTL, RESET_BUSY_CNT, 1); 434 435 for (i = 0; i < 8; i++) 436 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 437 ixCG_FREQ_TRAN_VOTING_0 + i * 4, 0); 438 439 return 0; 440 } 441 442 /* Copy one arb setting to another and then switch the active set. 443 * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. 444 */ 445 static int smu7_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, 446 uint32_t arb_src, uint32_t arb_dest) 447 { 448 uint32_t mc_arb_dram_timing; 449 uint32_t mc_arb_dram_timing2; 450 uint32_t burst_time; 451 uint32_t mc_cg_config; 452 453 switch (arb_src) { 454 case MC_CG_ARB_FREQ_F0: 455 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING); 456 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2); 457 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0); 458 break; 459 case MC_CG_ARB_FREQ_F1: 460 mc_arb_dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1); 461 mc_arb_dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1); 462 burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1); 463 break; 464 default: 465 return -EINVAL; 466 } 467 468 switch (arb_dest) { 469 case MC_CG_ARB_FREQ_F0: 470 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING, mc_arb_dram_timing); 471 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2, mc_arb_dram_timing2); 472 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0, burst_time); 473 break; 474 case MC_CG_ARB_FREQ_F1: 475 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING_1, mc_arb_dram_timing); 476 cgs_write_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2); 477 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE1, burst_time); 478 break; 479 default: 480 return -EINVAL; 481 } 482 483 mc_cg_config = cgs_read_register(hwmgr->device, mmMC_CG_CONFIG); 484 mc_cg_config |= 0x0000000F; 485 cgs_write_register(hwmgr->device, mmMC_CG_CONFIG, mc_cg_config); 486 PHM_WRITE_FIELD(hwmgr->device, MC_ARB_CG, CG_ARB_REQ, arb_dest); 487 488 return 0; 489 } 490 491 static int smu7_reset_to_default(struct pp_hwmgr *hwmgr) 492 { 493 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ResetToDefaults); 494 } 495 496 /** 497 * Initial switch from ARB F0->F1 498 * 499 * @param hwmgr the address of the powerplay hardware manager. 500 * @return always 0 501 * This function is to be called from the SetPowerState table. 502 */ 503 static int smu7_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) 504 { 505 return smu7_copy_and_switch_arb_sets(hwmgr, 506 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 507 } 508 509 static int smu7_force_switch_to_arbf0(struct pp_hwmgr *hwmgr) 510 { 511 uint32_t tmp; 512 513 tmp = (cgs_read_ind_register(hwmgr->device, 514 CGS_IND_REG__SMC, ixSMC_SCRATCH9) & 515 0x0000ff00) >> 8; 516 517 if (tmp == MC_CG_ARB_FREQ_F0) 518 return 0; 519 520 return smu7_copy_and_switch_arb_sets(hwmgr, 521 tmp, MC_CG_ARB_FREQ_F0); 522 } 523 524 static int smu7_setup_default_pcie_table(struct pp_hwmgr *hwmgr) 525 { 526 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 527 528 struct phm_ppt_v1_information *table_info = 529 (struct phm_ppt_v1_information *)(hwmgr->pptable); 530 struct phm_ppt_v1_pcie_table *pcie_table = NULL; 531 532 uint32_t i, max_entry; 533 uint32_t tmp; 534 535 PP_ASSERT_WITH_CODE((data->use_pcie_performance_levels || 536 data->use_pcie_power_saving_levels), "No pcie performance levels!", 537 return -EINVAL); 538 539 if (table_info != NULL) 540 pcie_table = table_info->pcie_table; 541 542 if (data->use_pcie_performance_levels && 543 !data->use_pcie_power_saving_levels) { 544 data->pcie_gen_power_saving = data->pcie_gen_performance; 545 data->pcie_lane_power_saving = data->pcie_lane_performance; 546 } else if (!data->use_pcie_performance_levels && 547 data->use_pcie_power_saving_levels) { 548 data->pcie_gen_performance = data->pcie_gen_power_saving; 549 data->pcie_lane_performance = data->pcie_lane_power_saving; 550 } 551 tmp = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_LINK); 552 phm_reset_single_dpm_table(&data->dpm_table.pcie_speed_table, 553 tmp, 554 MAX_REGULAR_DPM_NUMBER); 555 556 if (pcie_table != NULL) { 557 /* max_entry is used to make sure we reserve one PCIE level 558 * for boot level (fix for A+A PSPP issue). 559 * If PCIE table from PPTable have ULV entry + 8 entries, 560 * then ignore the last entry.*/ 561 max_entry = (tmp < pcie_table->count) ? tmp : pcie_table->count; 562 for (i = 1; i < max_entry; i++) { 563 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i - 1, 564 get_pcie_gen_support(data->pcie_gen_cap, 565 pcie_table->entries[i].gen_speed), 566 get_pcie_lane_support(data->pcie_lane_cap, 567 pcie_table->entries[i].lane_width)); 568 } 569 data->dpm_table.pcie_speed_table.count = max_entry - 1; 570 smum_update_smc_table(hwmgr, SMU_BIF_TABLE); 571 } else { 572 /* Hardcode Pcie Table */ 573 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 0, 574 get_pcie_gen_support(data->pcie_gen_cap, 575 PP_Min_PCIEGen), 576 get_pcie_lane_support(data->pcie_lane_cap, 577 PP_Max_PCIELane)); 578 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 1, 579 get_pcie_gen_support(data->pcie_gen_cap, 580 PP_Min_PCIEGen), 581 get_pcie_lane_support(data->pcie_lane_cap, 582 PP_Max_PCIELane)); 583 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 2, 584 get_pcie_gen_support(data->pcie_gen_cap, 585 PP_Max_PCIEGen), 586 get_pcie_lane_support(data->pcie_lane_cap, 587 PP_Max_PCIELane)); 588 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 3, 589 get_pcie_gen_support(data->pcie_gen_cap, 590 PP_Max_PCIEGen), 591 get_pcie_lane_support(data->pcie_lane_cap, 592 PP_Max_PCIELane)); 593 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 4, 594 get_pcie_gen_support(data->pcie_gen_cap, 595 PP_Max_PCIEGen), 596 get_pcie_lane_support(data->pcie_lane_cap, 597 PP_Max_PCIELane)); 598 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 5, 599 get_pcie_gen_support(data->pcie_gen_cap, 600 PP_Max_PCIEGen), 601 get_pcie_lane_support(data->pcie_lane_cap, 602 PP_Max_PCIELane)); 603 604 data->dpm_table.pcie_speed_table.count = 6; 605 } 606 /* Populate last level for boot PCIE level, but do not increment count. */ 607 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 608 for (i = 0; i <= data->dpm_table.pcie_speed_table.count; i++) 609 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, i, 610 get_pcie_gen_support(data->pcie_gen_cap, 611 PP_Max_PCIEGen), 612 data->vbios_boot_state.pcie_lane_bootup_value); 613 } else { 614 phm_setup_pcie_table_entry(&data->dpm_table.pcie_speed_table, 615 data->dpm_table.pcie_speed_table.count, 616 get_pcie_gen_support(data->pcie_gen_cap, 617 PP_Min_PCIEGen), 618 get_pcie_lane_support(data->pcie_lane_cap, 619 PP_Max_PCIELane)); 620 } 621 return 0; 622 } 623 624 static int smu7_reset_dpm_tables(struct pp_hwmgr *hwmgr) 625 { 626 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 627 628 memset(&(data->dpm_table), 0x00, sizeof(data->dpm_table)); 629 630 phm_reset_single_dpm_table( 631 &data->dpm_table.sclk_table, 632 smum_get_mac_definition(hwmgr, 633 SMU_MAX_LEVELS_GRAPHICS), 634 MAX_REGULAR_DPM_NUMBER); 635 phm_reset_single_dpm_table( 636 &data->dpm_table.mclk_table, 637 smum_get_mac_definition(hwmgr, 638 SMU_MAX_LEVELS_MEMORY), MAX_REGULAR_DPM_NUMBER); 639 640 phm_reset_single_dpm_table( 641 &data->dpm_table.vddc_table, 642 smum_get_mac_definition(hwmgr, 643 SMU_MAX_LEVELS_VDDC), 644 MAX_REGULAR_DPM_NUMBER); 645 phm_reset_single_dpm_table( 646 &data->dpm_table.vddci_table, 647 smum_get_mac_definition(hwmgr, 648 SMU_MAX_LEVELS_VDDCI), MAX_REGULAR_DPM_NUMBER); 649 650 phm_reset_single_dpm_table( 651 &data->dpm_table.mvdd_table, 652 smum_get_mac_definition(hwmgr, 653 SMU_MAX_LEVELS_MVDD), 654 MAX_REGULAR_DPM_NUMBER); 655 return 0; 656 } 657 /* 658 * This function is to initialize all DPM state tables 659 * for SMU7 based on the dependency table. 660 * Dynamic state patching function will then trim these 661 * state tables to the allowed range based 662 * on the power policy or external client requests, 663 * such as UVD request, etc. 664 */ 665 666 static int smu7_setup_dpm_tables_v0(struct pp_hwmgr *hwmgr) 667 { 668 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 669 struct phm_clock_voltage_dependency_table *allowed_vdd_sclk_table = 670 hwmgr->dyn_state.vddc_dependency_on_sclk; 671 struct phm_clock_voltage_dependency_table *allowed_vdd_mclk_table = 672 hwmgr->dyn_state.vddc_dependency_on_mclk; 673 struct phm_cac_leakage_table *std_voltage_table = 674 hwmgr->dyn_state.cac_leakage_table; 675 uint32_t i; 676 677 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table != NULL, 678 "SCLK dependency table is missing. This table is mandatory", return -EINVAL); 679 PP_ASSERT_WITH_CODE(allowed_vdd_sclk_table->count >= 1, 680 "SCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 681 682 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 683 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 684 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table->count >= 1, 685 "VMCLK dependency table has to have is missing. This table is mandatory", return -EINVAL); 686 687 688 /* Initialize Sclk DPM table based on allow Sclk values*/ 689 data->dpm_table.sclk_table.count = 0; 690 691 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 692 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != 693 allowed_vdd_sclk_table->entries[i].clk) { 694 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 695 allowed_vdd_sclk_table->entries[i].clk; 696 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; 697 data->dpm_table.sclk_table.count++; 698 } 699 } 700 701 PP_ASSERT_WITH_CODE(allowed_vdd_mclk_table != NULL, 702 "MCLK dependency table is missing. This table is mandatory", return -EINVAL); 703 /* Initialize Mclk DPM table based on allow Mclk values */ 704 data->dpm_table.mclk_table.count = 0; 705 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 706 if (i == 0 || data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count-1].value != 707 allowed_vdd_mclk_table->entries[i].clk) { 708 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 709 allowed_vdd_mclk_table->entries[i].clk; 710 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = (i == 0) ? 1 : 0; 711 data->dpm_table.mclk_table.count++; 712 } 713 } 714 715 /* Initialize Vddc DPM table based on allow Vddc values. And populate corresponding std values. */ 716 for (i = 0; i < allowed_vdd_sclk_table->count; i++) { 717 data->dpm_table.vddc_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 718 data->dpm_table.vddc_table.dpm_levels[i].param1 = std_voltage_table->entries[i].Leakage; 719 /* param1 is for corresponding std voltage */ 720 data->dpm_table.vddc_table.dpm_levels[i].enabled = 1; 721 } 722 723 data->dpm_table.vddc_table.count = allowed_vdd_sclk_table->count; 724 allowed_vdd_mclk_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 725 726 if (NULL != allowed_vdd_mclk_table) { 727 /* Initialize Vddci DPM table based on allow Mclk values */ 728 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 729 data->dpm_table.vddci_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 730 data->dpm_table.vddci_table.dpm_levels[i].enabled = 1; 731 } 732 data->dpm_table.vddci_table.count = allowed_vdd_mclk_table->count; 733 } 734 735 allowed_vdd_mclk_table = hwmgr->dyn_state.mvdd_dependency_on_mclk; 736 737 if (NULL != allowed_vdd_mclk_table) { 738 /* 739 * Initialize MVDD DPM table based on allow Mclk 740 * values 741 */ 742 for (i = 0; i < allowed_vdd_mclk_table->count; i++) { 743 data->dpm_table.mvdd_table.dpm_levels[i].value = allowed_vdd_mclk_table->entries[i].v; 744 data->dpm_table.mvdd_table.dpm_levels[i].enabled = 1; 745 } 746 data->dpm_table.mvdd_table.count = allowed_vdd_mclk_table->count; 747 } 748 749 return 0; 750 } 751 752 static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr) 753 { 754 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 755 struct phm_ppt_v1_information *table_info = 756 (struct phm_ppt_v1_information *)(hwmgr->pptable); 757 uint32_t i; 758 759 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 760 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 761 762 if (table_info == NULL) 763 return -EINVAL; 764 765 dep_sclk_table = table_info->vdd_dep_on_sclk; 766 dep_mclk_table = table_info->vdd_dep_on_mclk; 767 768 PP_ASSERT_WITH_CODE(dep_sclk_table != NULL, 769 "SCLK dependency table is missing.", 770 return -EINVAL); 771 PP_ASSERT_WITH_CODE(dep_sclk_table->count >= 1, 772 "SCLK dependency table count is 0.", 773 return -EINVAL); 774 775 PP_ASSERT_WITH_CODE(dep_mclk_table != NULL, 776 "MCLK dependency table is missing.", 777 return -EINVAL); 778 PP_ASSERT_WITH_CODE(dep_mclk_table->count >= 1, 779 "MCLK dependency table count is 0", 780 return -EINVAL); 781 782 /* Initialize Sclk DPM table based on allow Sclk values */ 783 data->dpm_table.sclk_table.count = 0; 784 for (i = 0; i < dep_sclk_table->count; i++) { 785 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != 786 dep_sclk_table->entries[i].clk) { 787 788 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = 789 dep_sclk_table->entries[i].clk; 790 791 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 792 (i == 0) ? true : false; 793 data->dpm_table.sclk_table.count++; 794 } 795 } 796 if (hwmgr->platform_descriptor.overdriveLimit.engineClock == 0) 797 hwmgr->platform_descriptor.overdriveLimit.engineClock = dep_sclk_table->entries[i-1].clk; 798 /* Initialize Mclk DPM table based on allow Mclk values */ 799 data->dpm_table.mclk_table.count = 0; 800 for (i = 0; i < dep_mclk_table->count; i++) { 801 if (i == 0 || data->dpm_table.mclk_table.dpm_levels 802 [data->dpm_table.mclk_table.count - 1].value != 803 dep_mclk_table->entries[i].clk) { 804 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value = 805 dep_mclk_table->entries[i].clk; 806 data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 807 (i == 0) ? true : false; 808 data->dpm_table.mclk_table.count++; 809 } 810 } 811 812 if (hwmgr->platform_descriptor.overdriveLimit.memoryClock == 0) 813 hwmgr->platform_descriptor.overdriveLimit.memoryClock = dep_mclk_table->entries[i-1].clk; 814 return 0; 815 } 816 817 static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr) 818 { 819 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 820 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 821 struct phm_ppt_v1_information *table_info = 822 (struct phm_ppt_v1_information *)(hwmgr->pptable); 823 uint32_t i; 824 825 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 826 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 827 struct phm_odn_performance_level *entries; 828 829 if (table_info == NULL) 830 return -EINVAL; 831 832 dep_sclk_table = table_info->vdd_dep_on_sclk; 833 dep_mclk_table = table_info->vdd_dep_on_mclk; 834 835 odn_table->odn_core_clock_dpm_levels.num_of_pl = 836 data->golden_dpm_table.sclk_table.count; 837 entries = odn_table->odn_core_clock_dpm_levels.entries; 838 for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) { 839 entries[i].clock = data->golden_dpm_table.sclk_table.dpm_levels[i].value; 840 entries[i].enabled = true; 841 entries[i].vddc = dep_sclk_table->entries[i].vddc; 842 } 843 844 smu_get_voltage_dependency_table_ppt_v1(dep_sclk_table, 845 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk)); 846 847 odn_table->odn_memory_clock_dpm_levels.num_of_pl = 848 data->golden_dpm_table.mclk_table.count; 849 entries = odn_table->odn_memory_clock_dpm_levels.entries; 850 for (i=0; i<data->golden_dpm_table.mclk_table.count; i++) { 851 entries[i].clock = data->golden_dpm_table.mclk_table.dpm_levels[i].value; 852 entries[i].enabled = true; 853 entries[i].vddc = dep_mclk_table->entries[i].vddc; 854 } 855 856 smu_get_voltage_dependency_table_ppt_v1(dep_mclk_table, 857 (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk)); 858 859 return 0; 860 } 861 862 static void smu7_setup_voltage_range_from_vbios(struct pp_hwmgr *hwmgr) 863 { 864 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 865 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table; 866 struct phm_ppt_v1_information *table_info = 867 (struct phm_ppt_v1_information *)(hwmgr->pptable); 868 uint32_t min_vddc = 0; 869 uint32_t max_vddc = 0; 870 871 if (!table_info) 872 return; 873 874 dep_sclk_table = table_info->vdd_dep_on_sclk; 875 876 atomctrl_get_voltage_range(hwmgr, &max_vddc, &min_vddc); 877 878 if (min_vddc == 0 || min_vddc > 2000 879 || min_vddc > dep_sclk_table->entries[0].vddc) 880 min_vddc = dep_sclk_table->entries[0].vddc; 881 882 if (max_vddc == 0 || max_vddc > 2000 883 || max_vddc < dep_sclk_table->entries[dep_sclk_table->count-1].vddc) 884 max_vddc = dep_sclk_table->entries[dep_sclk_table->count-1].vddc; 885 886 data->odn_dpm_table.min_vddc = min_vddc; 887 data->odn_dpm_table.max_vddc = max_vddc; 888 } 889 890 static void smu7_check_dpm_table_updated(struct pp_hwmgr *hwmgr) 891 { 892 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 893 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 894 struct phm_ppt_v1_information *table_info = 895 (struct phm_ppt_v1_information *)(hwmgr->pptable); 896 uint32_t i; 897 898 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table; 899 struct phm_ppt_v1_clock_voltage_dependency_table *odn_dep_table; 900 901 if (table_info == NULL) 902 return; 903 904 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { 905 if (odn_table->odn_core_clock_dpm_levels.entries[i].clock != 906 data->dpm_table.sclk_table.dpm_levels[i].value) { 907 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 908 break; 909 } 910 } 911 912 for (i = 0; i < data->dpm_table.mclk_table.count; i++) { 913 if (odn_table->odn_memory_clock_dpm_levels.entries[i].clock != 914 data->dpm_table.mclk_table.dpm_levels[i].value) { 915 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 916 break; 917 } 918 } 919 920 dep_table = table_info->vdd_dep_on_mclk; 921 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk); 922 923 for (i = 0; i < dep_table->count; i++) { 924 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 925 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_MCLK; 926 return; 927 } 928 } 929 930 dep_table = table_info->vdd_dep_on_sclk; 931 odn_dep_table = (struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk); 932 for (i = 0; i < dep_table->count; i++) { 933 if (dep_table->entries[i].vddc != odn_dep_table->entries[i].vddc) { 934 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; 935 return; 936 } 937 } 938 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 939 data->need_update_smu7_dpm_table &= ~DPMTABLE_OD_UPDATE_VDDC; 940 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; 941 } 942 } 943 944 static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 945 { 946 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 947 948 smu7_reset_dpm_tables(hwmgr); 949 950 if (hwmgr->pp_table_version == PP_TABLE_V1) 951 smu7_setup_dpm_tables_v1(hwmgr); 952 else if (hwmgr->pp_table_version == PP_TABLE_V0) 953 smu7_setup_dpm_tables_v0(hwmgr); 954 955 smu7_setup_default_pcie_table(hwmgr); 956 957 /* save a copy of the default DPM table */ 958 memcpy(&(data->golden_dpm_table), &(data->dpm_table), 959 sizeof(struct smu7_dpm_table)); 960 961 /* initialize ODN table */ 962 if (hwmgr->od_enabled) { 963 if (data->odn_dpm_table.max_vddc) { 964 smu7_check_dpm_table_updated(hwmgr); 965 } else { 966 smu7_setup_voltage_range_from_vbios(hwmgr); 967 smu7_odn_initial_default_setting(hwmgr); 968 } 969 } 970 return 0; 971 } 972 973 static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) 974 { 975 976 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 977 PHM_PlatformCaps_RegulatorHot)) 978 return smum_send_msg_to_smc(hwmgr, 979 PPSMC_MSG_EnableVRHotGPIOInterrupt); 980 981 return 0; 982 } 983 984 static int smu7_enable_sclk_control(struct pp_hwmgr *hwmgr) 985 { 986 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 987 SCLK_PWRMGT_OFF, 0); 988 return 0; 989 } 990 991 static int smu7_enable_ulv(struct pp_hwmgr *hwmgr) 992 { 993 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 994 995 if (data->ulv_supported) 996 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableULV); 997 998 return 0; 999 } 1000 1001 static int smu7_disable_ulv(struct pp_hwmgr *hwmgr) 1002 { 1003 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1004 1005 if (data->ulv_supported) 1006 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableULV); 1007 1008 return 0; 1009 } 1010 1011 static int smu7_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1012 { 1013 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1014 PHM_PlatformCaps_SclkDeepSleep)) { 1015 if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MASTER_DeepSleep_ON)) 1016 PP_ASSERT_WITH_CODE(false, 1017 "Attempt to enable Master Deep Sleep switch failed!", 1018 return -EINVAL); 1019 } else { 1020 if (smum_send_msg_to_smc(hwmgr, 1021 PPSMC_MSG_MASTER_DeepSleep_OFF)) { 1022 PP_ASSERT_WITH_CODE(false, 1023 "Attempt to disable Master Deep Sleep switch failed!", 1024 return -EINVAL); 1025 } 1026 } 1027 1028 return 0; 1029 } 1030 1031 static int smu7_disable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) 1032 { 1033 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1034 PHM_PlatformCaps_SclkDeepSleep)) { 1035 if (smum_send_msg_to_smc(hwmgr, 1036 PPSMC_MSG_MASTER_DeepSleep_OFF)) { 1037 PP_ASSERT_WITH_CODE(false, 1038 "Attempt to disable Master Deep Sleep switch failed!", 1039 return -EINVAL); 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static int smu7_disable_sclk_vce_handshake(struct pp_hwmgr *hwmgr) 1047 { 1048 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1049 uint32_t soft_register_value = 0; 1050 uint32_t handshake_disables_offset = data->soft_regs_start 1051 + smum_get_offsetof(hwmgr, 1052 SMU_SoftRegisters, HandshakeDisables); 1053 1054 soft_register_value = cgs_read_ind_register(hwmgr->device, 1055 CGS_IND_REG__SMC, handshake_disables_offset); 1056 soft_register_value |= SMU7_VCE_SCLK_HANDSHAKE_DISABLE; 1057 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1058 handshake_disables_offset, soft_register_value); 1059 return 0; 1060 } 1061 1062 static int smu7_disable_handshake_uvd(struct pp_hwmgr *hwmgr) 1063 { 1064 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1065 uint32_t soft_register_value = 0; 1066 uint32_t handshake_disables_offset = data->soft_regs_start 1067 + smum_get_offsetof(hwmgr, 1068 SMU_SoftRegisters, HandshakeDisables); 1069 1070 soft_register_value = cgs_read_ind_register(hwmgr->device, 1071 CGS_IND_REG__SMC, handshake_disables_offset); 1072 soft_register_value |= smum_get_mac_definition(hwmgr, 1073 SMU_UVD_MCLK_HANDSHAKE_DISABLE); 1074 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1075 handshake_disables_offset, soft_register_value); 1076 return 0; 1077 } 1078 1079 static int smu7_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1080 { 1081 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1082 1083 /* enable SCLK dpm */ 1084 if (!data->sclk_dpm_key_disabled) { 1085 if (hwmgr->chip_id == CHIP_VEGAM) 1086 smu7_disable_sclk_vce_handshake(hwmgr); 1087 1088 PP_ASSERT_WITH_CODE( 1089 (0 == smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Enable)), 1090 "Failed to enable SCLK DPM during DPM Start Function!", 1091 return -EINVAL); 1092 } 1093 1094 /* enable MCLK dpm */ 1095 if (0 == data->mclk_dpm_key_disabled) { 1096 if (!(hwmgr->feature_mask & PP_UVD_HANDSHAKE_MASK)) 1097 smu7_disable_handshake_uvd(hwmgr); 1098 1099 PP_ASSERT_WITH_CODE( 1100 (0 == smum_send_msg_to_smc(hwmgr, 1101 PPSMC_MSG_MCLKDPM_Enable)), 1102 "Failed to enable MCLK DPM during DPM Start Function!", 1103 return -EINVAL); 1104 1105 if (hwmgr->chip_family != CHIP_VEGAM) 1106 PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1); 1107 1108 1109 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1110 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x5); 1111 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x5); 1112 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x100005); 1113 udelay(10); 1114 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d30, 0x400005); 1115 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d3c, 0x400005); 1116 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 0xc0400d80, 0x500005); 1117 } else { 1118 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x5); 1119 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x5); 1120 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x100005); 1121 udelay(10); 1122 if (hwmgr->chip_id == CHIP_VEGAM) { 1123 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400009); 1124 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400009); 1125 } else { 1126 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC0_CNTL, 0x400005); 1127 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_MC1_CNTL, 0x400005); 1128 } 1129 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixLCAC_CPL_CNTL, 0x500005); 1130 } 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int smu7_start_dpm(struct pp_hwmgr *hwmgr) 1137 { 1138 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1139 1140 /*enable general power management */ 1141 1142 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1143 GLOBAL_PWRMGT_EN, 1); 1144 1145 /* enable sclk deep sleep */ 1146 1147 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1148 DYNAMIC_PM_EN, 1); 1149 1150 /* prepare for PCIE DPM */ 1151 1152 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 1153 data->soft_regs_start + 1154 smum_get_offsetof(hwmgr, SMU_SoftRegisters, 1155 VoltageChangeTimeout), 0x1000); 1156 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, 1157 SWRST_COMMAND_1, RESETLC, 0x0); 1158 1159 if (hwmgr->chip_family == AMDGPU_FAMILY_CI) 1160 cgs_write_register(hwmgr->device, 0x1488, 1161 (cgs_read_register(hwmgr->device, 0x1488) & ~0x1)); 1162 1163 if (smu7_enable_sclk_mclk_dpm(hwmgr)) { 1164 pr_err("Failed to enable Sclk DPM and Mclk DPM!"); 1165 return -EINVAL; 1166 } 1167 1168 /* enable PCIE dpm */ 1169 if (0 == data->pcie_dpm_key_disabled) { 1170 PP_ASSERT_WITH_CODE( 1171 (0 == smum_send_msg_to_smc(hwmgr, 1172 PPSMC_MSG_PCIeDPM_Enable)), 1173 "Failed to enable pcie DPM during DPM Start Function!", 1174 return -EINVAL); 1175 } 1176 1177 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1178 PHM_PlatformCaps_Falcon_QuickTransition)) { 1179 PP_ASSERT_WITH_CODE((0 == smum_send_msg_to_smc(hwmgr, 1180 PPSMC_MSG_EnableACDCGPIOInterrupt)), 1181 "Failed to enable AC DC GPIO Interrupt!", 1182 ); 1183 } 1184 1185 return 0; 1186 } 1187 1188 static int smu7_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 1189 { 1190 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1191 1192 /* disable SCLK dpm */ 1193 if (!data->sclk_dpm_key_disabled) { 1194 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1195 "Trying to disable SCLK DPM when DPM is disabled", 1196 return 0); 1197 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DPM_Disable); 1198 } 1199 1200 /* disable MCLK dpm */ 1201 if (!data->mclk_dpm_key_disabled) { 1202 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1203 "Trying to disable MCLK DPM when DPM is disabled", 1204 return 0); 1205 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_Disable); 1206 } 1207 1208 return 0; 1209 } 1210 1211 static int smu7_stop_dpm(struct pp_hwmgr *hwmgr) 1212 { 1213 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1214 1215 /* disable general power management */ 1216 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1217 GLOBAL_PWRMGT_EN, 0); 1218 /* disable sclk deep sleep */ 1219 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, 1220 DYNAMIC_PM_EN, 0); 1221 1222 /* disable PCIE dpm */ 1223 if (!data->pcie_dpm_key_disabled) { 1224 PP_ASSERT_WITH_CODE( 1225 (smum_send_msg_to_smc(hwmgr, 1226 PPSMC_MSG_PCIeDPM_Disable) == 0), 1227 "Failed to disable pcie DPM during DPM Stop Function!", 1228 return -EINVAL); 1229 } 1230 1231 smu7_disable_sclk_mclk_dpm(hwmgr); 1232 1233 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 1234 "Trying to disable voltage DPM when DPM is disabled", 1235 return 0); 1236 1237 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_Voltage_Cntl_Disable); 1238 1239 return 0; 1240 } 1241 1242 static void smu7_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) 1243 { 1244 bool protection; 1245 enum DPM_EVENT_SRC src; 1246 1247 switch (sources) { 1248 default: 1249 pr_err("Unknown throttling event sources."); 1250 /* fall through */ 1251 case 0: 1252 protection = false; 1253 /* src is unused */ 1254 break; 1255 case (1 << PHM_AutoThrottleSource_Thermal): 1256 protection = true; 1257 src = DPM_EVENT_SRC_DIGITAL; 1258 break; 1259 case (1 << PHM_AutoThrottleSource_External): 1260 protection = true; 1261 src = DPM_EVENT_SRC_EXTERNAL; 1262 break; 1263 case (1 << PHM_AutoThrottleSource_External) | 1264 (1 << PHM_AutoThrottleSource_Thermal): 1265 protection = true; 1266 src = DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL; 1267 break; 1268 } 1269 /* Order matters - don't enable thermal protection for the wrong source. */ 1270 if (protection) { 1271 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_CTRL, 1272 DPM_EVENT_SRC, src); 1273 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1274 THERMAL_PROTECTION_DIS, 1275 !phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1276 PHM_PlatformCaps_ThermalController)); 1277 } else 1278 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, 1279 THERMAL_PROTECTION_DIS, 1); 1280 } 1281 1282 static int smu7_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1283 PHM_AutoThrottleSource source) 1284 { 1285 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1286 1287 if (!(data->active_auto_throttle_sources & (1 << source))) { 1288 data->active_auto_throttle_sources |= 1 << source; 1289 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1290 } 1291 return 0; 1292 } 1293 1294 static int smu7_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1295 { 1296 return smu7_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1297 } 1298 1299 static int smu7_disable_auto_throttle_source(struct pp_hwmgr *hwmgr, 1300 PHM_AutoThrottleSource source) 1301 { 1302 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1303 1304 if (data->active_auto_throttle_sources & (1 << source)) { 1305 data->active_auto_throttle_sources &= ~(1 << source); 1306 smu7_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); 1307 } 1308 return 0; 1309 } 1310 1311 static int smu7_disable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) 1312 { 1313 return smu7_disable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); 1314 } 1315 1316 static int smu7_pcie_performance_request(struct pp_hwmgr *hwmgr) 1317 { 1318 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1319 data->pcie_performance_request = true; 1320 1321 return 0; 1322 } 1323 1324 static int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr) 1325 { 1326 int tmp_result = 0; 1327 int result = 0; 1328 1329 if (smu7_voltage_control(hwmgr)) { 1330 tmp_result = smu7_enable_voltage_control(hwmgr); 1331 PP_ASSERT_WITH_CODE(tmp_result == 0, 1332 "Failed to enable voltage control!", 1333 result = tmp_result); 1334 1335 tmp_result = smu7_construct_voltage_tables(hwmgr); 1336 PP_ASSERT_WITH_CODE((0 == tmp_result), 1337 "Failed to construct voltage tables!", 1338 result = tmp_result); 1339 } 1340 smum_initialize_mc_reg_table(hwmgr); 1341 1342 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1343 PHM_PlatformCaps_EngineSpreadSpectrumSupport)) 1344 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1345 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 1); 1346 1347 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1348 PHM_PlatformCaps_ThermalController)) 1349 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1350 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); 1351 1352 tmp_result = smu7_program_static_screen_threshold_parameters(hwmgr); 1353 PP_ASSERT_WITH_CODE((0 == tmp_result), 1354 "Failed to program static screen threshold parameters!", 1355 result = tmp_result); 1356 1357 tmp_result = smu7_enable_display_gap(hwmgr); 1358 PP_ASSERT_WITH_CODE((0 == tmp_result), 1359 "Failed to enable display gap!", result = tmp_result); 1360 1361 tmp_result = smu7_program_voting_clients(hwmgr); 1362 PP_ASSERT_WITH_CODE((0 == tmp_result), 1363 "Failed to program voting clients!", result = tmp_result); 1364 1365 tmp_result = smum_process_firmware_header(hwmgr); 1366 PP_ASSERT_WITH_CODE((0 == tmp_result), 1367 "Failed to process firmware header!", result = tmp_result); 1368 1369 if (hwmgr->chip_id != CHIP_VEGAM) { 1370 tmp_result = smu7_initial_switch_from_arbf0_to_f1(hwmgr); 1371 PP_ASSERT_WITH_CODE((0 == tmp_result), 1372 "Failed to initialize switch from ArbF0 to F1!", 1373 result = tmp_result); 1374 } 1375 1376 result = smu7_setup_default_dpm_tables(hwmgr); 1377 PP_ASSERT_WITH_CODE(0 == result, 1378 "Failed to setup default DPM tables!", return result); 1379 1380 tmp_result = smum_init_smc_table(hwmgr); 1381 PP_ASSERT_WITH_CODE((0 == tmp_result), 1382 "Failed to initialize SMC table!", result = tmp_result); 1383 1384 tmp_result = smu7_enable_vrhot_gpio_interrupt(hwmgr); 1385 PP_ASSERT_WITH_CODE((0 == tmp_result), 1386 "Failed to enable VR hot GPIO interrupt!", result = tmp_result); 1387 1388 smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_NoDisplay); 1389 1390 tmp_result = smu7_enable_sclk_control(hwmgr); 1391 PP_ASSERT_WITH_CODE((0 == tmp_result), 1392 "Failed to enable SCLK control!", result = tmp_result); 1393 1394 tmp_result = smu7_enable_smc_voltage_controller(hwmgr); 1395 PP_ASSERT_WITH_CODE((0 == tmp_result), 1396 "Failed to enable voltage control!", result = tmp_result); 1397 1398 tmp_result = smu7_enable_ulv(hwmgr); 1399 PP_ASSERT_WITH_CODE((0 == tmp_result), 1400 "Failed to enable ULV!", result = tmp_result); 1401 1402 tmp_result = smu7_enable_deep_sleep_master_switch(hwmgr); 1403 PP_ASSERT_WITH_CODE((0 == tmp_result), 1404 "Failed to enable deep sleep master switch!", result = tmp_result); 1405 1406 tmp_result = smu7_enable_didt_config(hwmgr); 1407 PP_ASSERT_WITH_CODE((tmp_result == 0), 1408 "Failed to enable deep sleep master switch!", result = tmp_result); 1409 1410 tmp_result = smu7_start_dpm(hwmgr); 1411 PP_ASSERT_WITH_CODE((0 == tmp_result), 1412 "Failed to start DPM!", result = tmp_result); 1413 1414 tmp_result = smu7_enable_smc_cac(hwmgr); 1415 PP_ASSERT_WITH_CODE((0 == tmp_result), 1416 "Failed to enable SMC CAC!", result = tmp_result); 1417 1418 tmp_result = smu7_enable_power_containment(hwmgr); 1419 PP_ASSERT_WITH_CODE((0 == tmp_result), 1420 "Failed to enable power containment!", result = tmp_result); 1421 1422 tmp_result = smu7_power_control_set_level(hwmgr); 1423 PP_ASSERT_WITH_CODE((0 == tmp_result), 1424 "Failed to power control set level!", result = tmp_result); 1425 1426 tmp_result = smu7_enable_thermal_auto_throttle(hwmgr); 1427 PP_ASSERT_WITH_CODE((0 == tmp_result), 1428 "Failed to enable thermal auto throttle!", result = tmp_result); 1429 1430 tmp_result = smu7_pcie_performance_request(hwmgr); 1431 PP_ASSERT_WITH_CODE((0 == tmp_result), 1432 "pcie performance request failed!", result = tmp_result); 1433 1434 return 0; 1435 } 1436 1437 static int smu7_avfs_control(struct pp_hwmgr *hwmgr, bool enable) 1438 { 1439 if (!hwmgr->avfs_supported) 1440 return 0; 1441 1442 if (enable) { 1443 if (!PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1444 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1445 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1446 hwmgr, PPSMC_MSG_EnableAvfs), 1447 "Failed to enable AVFS!", 1448 return -EINVAL); 1449 } 1450 } else if (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, 1451 CGS_IND_REG__SMC, FEATURE_STATUS, AVS_ON)) { 1452 PP_ASSERT_WITH_CODE(!smum_send_msg_to_smc( 1453 hwmgr, PPSMC_MSG_DisableAvfs), 1454 "Failed to disable AVFS!", 1455 return -EINVAL); 1456 } 1457 1458 return 0; 1459 } 1460 1461 static int smu7_update_avfs(struct pp_hwmgr *hwmgr) 1462 { 1463 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1464 1465 if (!hwmgr->avfs_supported) 1466 return 0; 1467 1468 if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_VDDC) { 1469 smu7_avfs_control(hwmgr, false); 1470 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 1471 smu7_avfs_control(hwmgr, false); 1472 smu7_avfs_control(hwmgr, true); 1473 } else { 1474 smu7_avfs_control(hwmgr, true); 1475 } 1476 1477 return 0; 1478 } 1479 1480 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr); 1481 int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr) 1482 { 1483 int tmp_result, result = 0; 1484 1485 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1486 PHM_PlatformCaps_ThermalController)) 1487 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1488 GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 1); 1489 1490 tmp_result = smu7_disable_power_containment(hwmgr); 1491 PP_ASSERT_WITH_CODE((tmp_result == 0), 1492 "Failed to disable power containment!", result = tmp_result); 1493 1494 tmp_result = smu7_disable_smc_cac(hwmgr); 1495 PP_ASSERT_WITH_CODE((tmp_result == 0), 1496 "Failed to disable SMC CAC!", result = tmp_result); 1497 1498 tmp_result = smu7_disable_didt_config(hwmgr); 1499 PP_ASSERT_WITH_CODE((tmp_result == 0), 1500 "Failed to disable DIDT!", result = tmp_result); 1501 1502 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1503 CG_SPLL_SPREAD_SPECTRUM, SSEN, 0); 1504 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 1505 GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, 0); 1506 1507 tmp_result = smu7_disable_thermal_auto_throttle(hwmgr); 1508 PP_ASSERT_WITH_CODE((tmp_result == 0), 1509 "Failed to disable thermal auto throttle!", result = tmp_result); 1510 1511 tmp_result = smu7_avfs_control(hwmgr, false); 1512 PP_ASSERT_WITH_CODE((tmp_result == 0), 1513 "Failed to disable AVFS!", result = tmp_result); 1514 1515 tmp_result = smu7_stop_dpm(hwmgr); 1516 PP_ASSERT_WITH_CODE((tmp_result == 0), 1517 "Failed to stop DPM!", result = tmp_result); 1518 1519 tmp_result = smu7_disable_deep_sleep_master_switch(hwmgr); 1520 PP_ASSERT_WITH_CODE((tmp_result == 0), 1521 "Failed to disable deep sleep master switch!", result = tmp_result); 1522 1523 tmp_result = smu7_disable_ulv(hwmgr); 1524 PP_ASSERT_WITH_CODE((tmp_result == 0), 1525 "Failed to disable ULV!", result = tmp_result); 1526 1527 tmp_result = smu7_clear_voting_clients(hwmgr); 1528 PP_ASSERT_WITH_CODE((tmp_result == 0), 1529 "Failed to clear voting clients!", result = tmp_result); 1530 1531 tmp_result = smu7_reset_to_default(hwmgr); 1532 PP_ASSERT_WITH_CODE((tmp_result == 0), 1533 "Failed to reset to default!", result = tmp_result); 1534 1535 tmp_result = smum_stop_smc(hwmgr); 1536 PP_ASSERT_WITH_CODE((tmp_result == 0), 1537 "Failed to stop smc!", result = tmp_result); 1538 1539 tmp_result = smu7_force_switch_to_arbf0(hwmgr); 1540 PP_ASSERT_WITH_CODE((tmp_result == 0), 1541 "Failed to force to switch arbf0!", result = tmp_result); 1542 1543 return result; 1544 } 1545 1546 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr); 1547 int smu7_reset_asic_tasks(struct pp_hwmgr *hwmgr) 1548 { 1549 1550 return 0; 1551 } 1552 1553 static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr) 1554 { 1555 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1556 struct phm_ppt_v1_information *table_info = 1557 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1558 struct amdgpu_device *adev = hwmgr->adev; 1559 1560 data->dll_default_on = false; 1561 data->mclk_dpm0_activity_target = 0xa; 1562 data->vddc_vddgfx_delta = 300; 1563 data->static_screen_threshold = SMU7_STATICSCREENTHRESHOLD_DFLT; 1564 data->static_screen_threshold_unit = SMU7_STATICSCREENTHRESHOLDUNIT_DFLT; 1565 data->voting_rights_clients[0] = SMU7_VOTINGRIGHTSCLIENTS_DFLT0; 1566 data->voting_rights_clients[1]= SMU7_VOTINGRIGHTSCLIENTS_DFLT1; 1567 data->voting_rights_clients[2] = SMU7_VOTINGRIGHTSCLIENTS_DFLT2; 1568 data->voting_rights_clients[3]= SMU7_VOTINGRIGHTSCLIENTS_DFLT3; 1569 data->voting_rights_clients[4]= SMU7_VOTINGRIGHTSCLIENTS_DFLT4; 1570 data->voting_rights_clients[5]= SMU7_VOTINGRIGHTSCLIENTS_DFLT5; 1571 data->voting_rights_clients[6]= SMU7_VOTINGRIGHTSCLIENTS_DFLT6; 1572 data->voting_rights_clients[7]= SMU7_VOTINGRIGHTSCLIENTS_DFLT7; 1573 1574 data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; 1575 data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; 1576 data->pcie_dpm_key_disabled = hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; 1577 /* need to set voltage control types before EVV patching */ 1578 data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE; 1579 data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE; 1580 data->mvdd_control = SMU7_VOLTAGE_CONTROL_NONE; 1581 data->enable_tdc_limit_feature = true; 1582 data->enable_pkg_pwr_tracking_feature = true; 1583 data->force_pcie_gen = PP_PCIEGenInvalid; 1584 data->ulv_supported = hwmgr->feature_mask & PP_ULV_MASK ? true : false; 1585 data->current_profile_setting.bupdate_sclk = 1; 1586 data->current_profile_setting.sclk_up_hyst = 0; 1587 data->current_profile_setting.sclk_down_hyst = 100; 1588 data->current_profile_setting.sclk_activity = SMU7_SCLK_TARGETACTIVITY_DFLT; 1589 data->current_profile_setting.bupdate_mclk = 1; 1590 data->current_profile_setting.mclk_up_hyst = 0; 1591 data->current_profile_setting.mclk_down_hyst = 100; 1592 data->current_profile_setting.mclk_activity = SMU7_MCLK_TARGETACTIVITY_DFLT; 1593 hwmgr->workload_mask = 1 << hwmgr->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D]; 1594 hwmgr->power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1595 hwmgr->default_power_profile_mode = PP_SMC_POWER_PROFILE_FULLSCREEN3D; 1596 1597 if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker) { 1598 uint8_t tmp1, tmp2; 1599 uint16_t tmp3 = 0; 1600 atomctrl_get_svi2_info(hwmgr, VOLTAGE_TYPE_VDDC, &tmp1, &tmp2, 1601 &tmp3); 1602 tmp3 = (tmp3 >> 5) & 0x3; 1603 data->vddc_phase_shed_control = ((tmp3 << 1) | (tmp3 >> 1)) & 0x3; 1604 } else if (hwmgr->chip_family == AMDGPU_FAMILY_CI) { 1605 data->vddc_phase_shed_control = 1; 1606 } else { 1607 data->vddc_phase_shed_control = 0; 1608 } 1609 1610 if (hwmgr->chip_id == CHIP_HAWAII) { 1611 data->thermal_temp_setting.temperature_low = 94500; 1612 data->thermal_temp_setting.temperature_high = 95000; 1613 data->thermal_temp_setting.temperature_shutdown = 104000; 1614 } else { 1615 data->thermal_temp_setting.temperature_low = 99500; 1616 data->thermal_temp_setting.temperature_high = 100000; 1617 data->thermal_temp_setting.temperature_shutdown = 104000; 1618 } 1619 1620 data->fast_watermark_threshold = 100; 1621 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1622 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) 1623 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1624 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1625 VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT)) 1626 data->voltage_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1627 1628 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1629 PHM_PlatformCaps_ControlVDDGFX)) { 1630 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1631 VOLTAGE_TYPE_VDDGFX, VOLTAGE_OBJ_SVID2)) { 1632 data->vdd_gfx_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1633 } 1634 } 1635 1636 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1637 PHM_PlatformCaps_EnableMVDDControl)) { 1638 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1639 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) 1640 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1641 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1642 VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) 1643 data->mvdd_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1644 } 1645 1646 if (SMU7_VOLTAGE_CONTROL_NONE == data->vdd_gfx_control) 1647 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1648 PHM_PlatformCaps_ControlVDDGFX); 1649 1650 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1651 PHM_PlatformCaps_ControlVDDCI)) { 1652 if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1653 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) 1654 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_GPIO; 1655 else if (atomctrl_is_voltage_controlled_by_gpio_v3(hwmgr, 1656 VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) 1657 data->vddci_control = SMU7_VOLTAGE_CONTROL_BY_SVID2; 1658 } 1659 1660 if (data->mvdd_control == SMU7_VOLTAGE_CONTROL_NONE) 1661 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1662 PHM_PlatformCaps_EnableMVDDControl); 1663 1664 if (data->vddci_control == SMU7_VOLTAGE_CONTROL_NONE) 1665 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, 1666 PHM_PlatformCaps_ControlVDDCI); 1667 1668 if ((hwmgr->pp_table_version != PP_TABLE_V0) && (hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK) 1669 && (table_info->cac_dtp_table->usClockStretchAmount != 0)) 1670 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1671 PHM_PlatformCaps_ClockStretcher); 1672 1673 data->pcie_gen_performance.max = PP_PCIEGen1; 1674 data->pcie_gen_performance.min = PP_PCIEGen3; 1675 data->pcie_gen_power_saving.max = PP_PCIEGen1; 1676 data->pcie_gen_power_saving.min = PP_PCIEGen3; 1677 data->pcie_lane_performance.max = 0; 1678 data->pcie_lane_performance.min = 16; 1679 data->pcie_lane_power_saving.max = 0; 1680 data->pcie_lane_power_saving.min = 16; 1681 1682 1683 if (adev->pg_flags & AMD_PG_SUPPORT_UVD) 1684 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1685 PHM_PlatformCaps_UVDPowerGating); 1686 if (adev->pg_flags & AMD_PG_SUPPORT_VCE) 1687 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 1688 PHM_PlatformCaps_VCEPowerGating); 1689 } 1690 1691 /** 1692 * Get Leakage VDDC based on leakage ID. 1693 * 1694 * @param hwmgr the address of the powerplay hardware manager. 1695 * @return always 0 1696 */ 1697 static int smu7_get_evv_voltages(struct pp_hwmgr *hwmgr) 1698 { 1699 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1700 uint16_t vv_id; 1701 uint16_t vddc = 0; 1702 uint16_t vddgfx = 0; 1703 uint16_t i, j; 1704 uint32_t sclk = 0; 1705 struct phm_ppt_v1_information *table_info = 1706 (struct phm_ppt_v1_information *)hwmgr->pptable; 1707 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = NULL; 1708 1709 1710 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 1711 vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 1712 1713 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1714 if ((hwmgr->pp_table_version == PP_TABLE_V1) 1715 && !phm_get_sclk_for_voltage_evv(hwmgr, 1716 table_info->vddgfx_lookup_table, vv_id, &sclk)) { 1717 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1718 PHM_PlatformCaps_ClockStretcher)) { 1719 sclk_table = table_info->vdd_dep_on_sclk; 1720 1721 for (j = 1; j < sclk_table->count; j++) { 1722 if (sclk_table->entries[j].clk == sclk && 1723 sclk_table->entries[j].cks_enable == 0) { 1724 sclk += 5000; 1725 break; 1726 } 1727 } 1728 } 1729 if (0 == atomctrl_get_voltage_evv_on_sclk 1730 (hwmgr, VOLTAGE_TYPE_VDDGFX, sclk, 1731 vv_id, &vddgfx)) { 1732 /* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */ 1733 PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -EINVAL); 1734 1735 /* the voltage should not be zero nor equal to leakage ID */ 1736 if (vddgfx != 0 && vddgfx != vv_id) { 1737 data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx; 1738 data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = vv_id; 1739 data->vddcgfx_leakage.count++; 1740 } 1741 } else { 1742 pr_info("Error retrieving EVV voltage value!\n"); 1743 } 1744 } 1745 } else { 1746 if ((hwmgr->pp_table_version == PP_TABLE_V0) 1747 || !phm_get_sclk_for_voltage_evv(hwmgr, 1748 table_info->vddc_lookup_table, vv_id, &sclk)) { 1749 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 1750 PHM_PlatformCaps_ClockStretcher)) { 1751 if (table_info == NULL) 1752 return -EINVAL; 1753 sclk_table = table_info->vdd_dep_on_sclk; 1754 1755 for (j = 1; j < sclk_table->count; j++) { 1756 if (sclk_table->entries[j].clk == sclk && 1757 sclk_table->entries[j].cks_enable == 0) { 1758 sclk += 5000; 1759 break; 1760 } 1761 } 1762 } 1763 1764 if (phm_get_voltage_evv_on_sclk(hwmgr, 1765 VOLTAGE_TYPE_VDDC, 1766 sclk, vv_id, &vddc) == 0) { 1767 if (vddc >= 2000 || vddc == 0) 1768 return -EINVAL; 1769 } else { 1770 pr_debug("failed to retrieving EVV voltage!\n"); 1771 continue; 1772 } 1773 1774 /* the voltage should not be zero nor equal to leakage ID */ 1775 if (vddc != 0 && vddc != vv_id) { 1776 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = (uint16_t)(vddc); 1777 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = vv_id; 1778 data->vddc_leakage.count++; 1779 } 1780 } 1781 } 1782 } 1783 1784 return 0; 1785 } 1786 1787 /** 1788 * Change virtual leakage voltage to actual value. 1789 * 1790 * @param hwmgr the address of the powerplay hardware manager. 1791 * @param pointer to changing voltage 1792 * @param pointer to leakage table 1793 */ 1794 static void smu7_patch_ppt_v1_with_vdd_leakage(struct pp_hwmgr *hwmgr, 1795 uint16_t *voltage, struct smu7_leakage_voltage *leakage_table) 1796 { 1797 uint32_t index; 1798 1799 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 1800 for (index = 0; index < leakage_table->count; index++) { 1801 /* if this voltage matches a leakage voltage ID */ 1802 /* patch with actual leakage voltage */ 1803 if (leakage_table->leakage_id[index] == *voltage) { 1804 *voltage = leakage_table->actual_voltage[index]; 1805 break; 1806 } 1807 } 1808 1809 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 1810 pr_err("Voltage value looks like a Leakage ID but it's not patched \n"); 1811 } 1812 1813 /** 1814 * Patch voltage lookup table by EVV leakages. 1815 * 1816 * @param hwmgr the address of the powerplay hardware manager. 1817 * @param pointer to voltage lookup table 1818 * @param pointer to leakage table 1819 * @return always 0 1820 */ 1821 static int smu7_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, 1822 phm_ppt_v1_voltage_lookup_table *lookup_table, 1823 struct smu7_leakage_voltage *leakage_table) 1824 { 1825 uint32_t i; 1826 1827 for (i = 0; i < lookup_table->count; i++) 1828 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 1829 &lookup_table->entries[i].us_vdd, leakage_table); 1830 1831 return 0; 1832 } 1833 1834 static int smu7_patch_clock_voltage_limits_with_vddc_leakage( 1835 struct pp_hwmgr *hwmgr, struct smu7_leakage_voltage *leakage_table, 1836 uint16_t *vddc) 1837 { 1838 struct phm_ppt_v1_information *table_info = 1839 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1840 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); 1841 hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = 1842 table_info->max_clock_voltage_on_dc.vddc; 1843 return 0; 1844 } 1845 1846 static int smu7_patch_voltage_dependency_tables_with_lookup_table( 1847 struct pp_hwmgr *hwmgr) 1848 { 1849 uint8_t entry_id; 1850 uint8_t voltage_id; 1851 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1852 struct phm_ppt_v1_information *table_info = 1853 (struct phm_ppt_v1_information *)(hwmgr->pptable); 1854 1855 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = 1856 table_info->vdd_dep_on_sclk; 1857 struct phm_ppt_v1_clock_voltage_dependency_table *mclk_table = 1858 table_info->vdd_dep_on_mclk; 1859 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = 1860 table_info->mm_dep_table; 1861 1862 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1863 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 1864 voltage_id = sclk_table->entries[entry_id].vddInd; 1865 sclk_table->entries[entry_id].vddgfx = 1866 table_info->vddgfx_lookup_table->entries[voltage_id].us_vdd; 1867 } 1868 } else { 1869 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 1870 voltage_id = sclk_table->entries[entry_id].vddInd; 1871 sclk_table->entries[entry_id].vddc = 1872 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 1873 } 1874 } 1875 1876 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 1877 voltage_id = mclk_table->entries[entry_id].vddInd; 1878 mclk_table->entries[entry_id].vddc = 1879 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 1880 } 1881 1882 for (entry_id = 0; entry_id < mm_table->count; ++entry_id) { 1883 voltage_id = mm_table->entries[entry_id].vddcInd; 1884 mm_table->entries[entry_id].vddc = 1885 table_info->vddc_lookup_table->entries[voltage_id].us_vdd; 1886 } 1887 1888 return 0; 1889 1890 } 1891 1892 static int phm_add_voltage(struct pp_hwmgr *hwmgr, 1893 phm_ppt_v1_voltage_lookup_table *look_up_table, 1894 phm_ppt_v1_voltage_lookup_record *record) 1895 { 1896 uint32_t i; 1897 1898 PP_ASSERT_WITH_CODE((NULL != look_up_table), 1899 "Lookup Table empty.", return -EINVAL); 1900 PP_ASSERT_WITH_CODE((0 != look_up_table->count), 1901 "Lookup Table empty.", return -EINVAL); 1902 1903 i = smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_VDDGFX); 1904 PP_ASSERT_WITH_CODE((i >= look_up_table->count), 1905 "Lookup Table is full.", return -EINVAL); 1906 1907 /* This is to avoid entering duplicate calculated records. */ 1908 for (i = 0; i < look_up_table->count; i++) { 1909 if (look_up_table->entries[i].us_vdd == record->us_vdd) { 1910 if (look_up_table->entries[i].us_calculated == 1) 1911 return 0; 1912 break; 1913 } 1914 } 1915 1916 look_up_table->entries[i].us_calculated = 1; 1917 look_up_table->entries[i].us_vdd = record->us_vdd; 1918 look_up_table->entries[i].us_cac_low = record->us_cac_low; 1919 look_up_table->entries[i].us_cac_mid = record->us_cac_mid; 1920 look_up_table->entries[i].us_cac_high = record->us_cac_high; 1921 /* Only increment the count when we're appending, not replacing duplicate entry. */ 1922 if (i == look_up_table->count) 1923 look_up_table->count++; 1924 1925 return 0; 1926 } 1927 1928 1929 static int smu7_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) 1930 { 1931 uint8_t entry_id; 1932 struct phm_ppt_v1_voltage_lookup_record v_record; 1933 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1934 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 1935 1936 phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk; 1937 phm_ppt_v1_clock_voltage_dependency_table *mclk_table = pptable_info->vdd_dep_on_mclk; 1938 1939 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1940 for (entry_id = 0; entry_id < sclk_table->count; ++entry_id) { 1941 if (sclk_table->entries[entry_id].vdd_offset & (1 << 15)) 1942 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 1943 sclk_table->entries[entry_id].vdd_offset - 0xFFFF; 1944 else 1945 v_record.us_vdd = sclk_table->entries[entry_id].vddgfx + 1946 sclk_table->entries[entry_id].vdd_offset; 1947 1948 sclk_table->entries[entry_id].vddc = 1949 v_record.us_cac_low = v_record.us_cac_mid = 1950 v_record.us_cac_high = v_record.us_vdd; 1951 1952 phm_add_voltage(hwmgr, pptable_info->vddc_lookup_table, &v_record); 1953 } 1954 1955 for (entry_id = 0; entry_id < mclk_table->count; ++entry_id) { 1956 if (mclk_table->entries[entry_id].vdd_offset & (1 << 15)) 1957 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 1958 mclk_table->entries[entry_id].vdd_offset - 0xFFFF; 1959 else 1960 v_record.us_vdd = mclk_table->entries[entry_id].vddc + 1961 mclk_table->entries[entry_id].vdd_offset; 1962 1963 mclk_table->entries[entry_id].vddgfx = v_record.us_cac_low = 1964 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 1965 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 1966 } 1967 } 1968 return 0; 1969 } 1970 1971 static int smu7_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) 1972 { 1973 uint8_t entry_id; 1974 struct phm_ppt_v1_voltage_lookup_record v_record; 1975 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 1976 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); 1977 phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table; 1978 1979 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 1980 for (entry_id = 0; entry_id < mm_table->count; entry_id++) { 1981 if (mm_table->entries[entry_id].vddgfx_offset & (1 << 15)) 1982 v_record.us_vdd = mm_table->entries[entry_id].vddc + 1983 mm_table->entries[entry_id].vddgfx_offset - 0xFFFF; 1984 else 1985 v_record.us_vdd = mm_table->entries[entry_id].vddc + 1986 mm_table->entries[entry_id].vddgfx_offset; 1987 1988 /* Add the calculated VDDGFX to the VDDGFX lookup table */ 1989 mm_table->entries[entry_id].vddgfx = v_record.us_cac_low = 1990 v_record.us_cac_mid = v_record.us_cac_high = v_record.us_vdd; 1991 phm_add_voltage(hwmgr, pptable_info->vddgfx_lookup_table, &v_record); 1992 } 1993 } 1994 return 0; 1995 } 1996 1997 static int smu7_sort_lookup_table(struct pp_hwmgr *hwmgr, 1998 struct phm_ppt_v1_voltage_lookup_table *lookup_table) 1999 { 2000 uint32_t table_size, i, j; 2001 struct phm_ppt_v1_voltage_lookup_record tmp_voltage_lookup_record; 2002 table_size = lookup_table->count; 2003 2004 PP_ASSERT_WITH_CODE(0 != lookup_table->count, 2005 "Lookup table is empty", return -EINVAL); 2006 2007 /* Sorting voltages */ 2008 for (i = 0; i < table_size - 1; i++) { 2009 for (j = i + 1; j > 0; j--) { 2010 if (lookup_table->entries[j].us_vdd < 2011 lookup_table->entries[j - 1].us_vdd) { 2012 tmp_voltage_lookup_record = lookup_table->entries[j - 1]; 2013 lookup_table->entries[j - 1] = lookup_table->entries[j]; 2014 lookup_table->entries[j] = tmp_voltage_lookup_record; 2015 } 2016 } 2017 } 2018 2019 return 0; 2020 } 2021 2022 static int smu7_complete_dependency_tables(struct pp_hwmgr *hwmgr) 2023 { 2024 int result = 0; 2025 int tmp_result; 2026 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2027 struct phm_ppt_v1_information *table_info = 2028 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2029 2030 if (data->vdd_gfx_control == SMU7_VOLTAGE_CONTROL_BY_SVID2) { 2031 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2032 table_info->vddgfx_lookup_table, &(data->vddcgfx_leakage)); 2033 if (tmp_result != 0) 2034 result = tmp_result; 2035 2036 smu7_patch_ppt_v1_with_vdd_leakage(hwmgr, 2037 &table_info->max_clock_voltage_on_dc.vddgfx, &(data->vddcgfx_leakage)); 2038 } else { 2039 2040 tmp_result = smu7_patch_lookup_table_with_leakage(hwmgr, 2041 table_info->vddc_lookup_table, &(data->vddc_leakage)); 2042 if (tmp_result) 2043 result = tmp_result; 2044 2045 tmp_result = smu7_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, 2046 &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); 2047 if (tmp_result) 2048 result = tmp_result; 2049 } 2050 2051 tmp_result = smu7_patch_voltage_dependency_tables_with_lookup_table(hwmgr); 2052 if (tmp_result) 2053 result = tmp_result; 2054 2055 tmp_result = smu7_calc_voltage_dependency_tables(hwmgr); 2056 if (tmp_result) 2057 result = tmp_result; 2058 2059 tmp_result = smu7_calc_mm_voltage_dependency_table(hwmgr); 2060 if (tmp_result) 2061 result = tmp_result; 2062 2063 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddgfx_lookup_table); 2064 if (tmp_result) 2065 result = tmp_result; 2066 2067 tmp_result = smu7_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); 2068 if (tmp_result) 2069 result = tmp_result; 2070 2071 return result; 2072 } 2073 2074 static int smu7_set_private_data_based_on_pptable_v1(struct pp_hwmgr *hwmgr) 2075 { 2076 struct phm_ppt_v1_information *table_info = 2077 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2078 2079 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_sclk_vdd_table = 2080 table_info->vdd_dep_on_sclk; 2081 struct phm_ppt_v1_clock_voltage_dependency_table *allowed_mclk_vdd_table = 2082 table_info->vdd_dep_on_mclk; 2083 2084 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table != NULL, 2085 "VDD dependency on SCLK table is missing.", 2086 return -EINVAL); 2087 PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1, 2088 "VDD dependency on SCLK table has to have is missing.", 2089 return -EINVAL); 2090 2091 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table != NULL, 2092 "VDD dependency on MCLK table is missing", 2093 return -EINVAL); 2094 PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1, 2095 "VDD dependency on MCLK table has to have is missing.", 2096 return -EINVAL); 2097 2098 table_info->max_clock_voltage_on_ac.sclk = 2099 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk; 2100 table_info->max_clock_voltage_on_ac.mclk = 2101 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].clk; 2102 table_info->max_clock_voltage_on_ac.vddc = 2103 allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].vddc; 2104 table_info->max_clock_voltage_on_ac.vddci = 2105 allowed_mclk_vdd_table->entries[allowed_mclk_vdd_table->count - 1].vddci; 2106 2107 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = table_info->max_clock_voltage_on_ac.sclk; 2108 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = table_info->max_clock_voltage_on_ac.mclk; 2109 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = table_info->max_clock_voltage_on_ac.vddc; 2110 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = table_info->max_clock_voltage_on_ac.vddci; 2111 2112 return 0; 2113 } 2114 2115 static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr) 2116 { 2117 struct phm_ppt_v1_information *table_info = 2118 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2119 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 2120 struct phm_ppt_v1_voltage_lookup_table *lookup_table; 2121 uint32_t i; 2122 uint32_t hw_revision, sub_vendor_id, sub_sys_id; 2123 struct amdgpu_device *adev = hwmgr->adev; 2124 2125 if (table_info != NULL) { 2126 dep_mclk_table = table_info->vdd_dep_on_mclk; 2127 lookup_table = table_info->vddc_lookup_table; 2128 } else 2129 return 0; 2130 2131 hw_revision = adev->pdev->revision; 2132 sub_sys_id = adev->pdev->subsystem_device; 2133 sub_vendor_id = adev->pdev->subsystem_vendor; 2134 2135 if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 && 2136 ((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) || 2137 (sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) || 2138 (sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) { 2139 if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000) 2140 return 0; 2141 2142 for (i = 0; i < lookup_table->count; i++) { 2143 if (lookup_table->entries[i].us_vdd < 0xff01 && lookup_table->entries[i].us_vdd >= 1000) { 2144 dep_mclk_table->entries[dep_mclk_table->count-1].vddInd = (uint8_t) i; 2145 return 0; 2146 } 2147 } 2148 } 2149 return 0; 2150 } 2151 2152 static int smu7_thermal_parameter_init(struct pp_hwmgr *hwmgr) 2153 { 2154 struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; 2155 uint32_t temp_reg; 2156 struct phm_ppt_v1_information *table_info = 2157 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2158 2159 2160 if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_PCC_GPIO_PINID, &gpio_pin_assignment)) { 2161 temp_reg = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL); 2162 switch (gpio_pin_assignment.uc_gpio_pin_bit_shift) { 2163 case 0: 2164 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x1); 2165 break; 2166 case 1: 2167 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW_MODE, 0x2); 2168 break; 2169 case 2: 2170 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, GNB_SLOW, 0x1); 2171 break; 2172 case 3: 2173 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, FORCE_NB_PS1, 0x1); 2174 break; 2175 case 4: 2176 temp_reg = PHM_SET_FIELD(temp_reg, CNB_PWRMGT_CNTL, DPM_ENABLED, 0x1); 2177 break; 2178 default: 2179 break; 2180 } 2181 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCNB_PWRMGT_CNTL, temp_reg); 2182 } 2183 2184 if (table_info == NULL) 2185 return 0; 2186 2187 if (table_info->cac_dtp_table->usDefaultTargetOperatingTemp != 0 && 2188 hwmgr->thermal_controller.advanceFanControlParameters.ucFanControlMode) { 2189 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit = 2190 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2191 2192 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMaxLimit = 2193 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2194 2195 hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMStep = 1; 2196 2197 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMaxLimit = 100; 2198 2199 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMMinLimit = 2200 (uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucMinimumPWMLimit; 2201 2202 hwmgr->thermal_controller.advanceFanControlParameters.usFanRPMStep = 1; 2203 2204 table_info->cac_dtp_table->usDefaultTargetOperatingTemp = (table_info->cac_dtp_table->usDefaultTargetOperatingTemp >= 50) ? 2205 (table_info->cac_dtp_table->usDefaultTargetOperatingTemp - 50) : 0; 2206 2207 table_info->cac_dtp_table->usOperatingTempMaxLimit = table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2208 table_info->cac_dtp_table->usOperatingTempStep = 1; 2209 table_info->cac_dtp_table->usOperatingTempHyst = 1; 2210 2211 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM = 2212 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanPWM; 2213 2214 hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM = 2215 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultMaxFanRPM; 2216 2217 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMinLimit = 2218 table_info->cac_dtp_table->usOperatingTempMinLimit; 2219 2220 hwmgr->dyn_state.cac_dtp_table->usOperatingTempMaxLimit = 2221 table_info->cac_dtp_table->usOperatingTempMaxLimit; 2222 2223 hwmgr->dyn_state.cac_dtp_table->usDefaultTargetOperatingTemp = 2224 table_info->cac_dtp_table->usDefaultTargetOperatingTemp; 2225 2226 hwmgr->dyn_state.cac_dtp_table->usOperatingTempStep = 2227 table_info->cac_dtp_table->usOperatingTempStep; 2228 2229 hwmgr->dyn_state.cac_dtp_table->usTargetOperatingTemp = 2230 table_info->cac_dtp_table->usTargetOperatingTemp; 2231 if (hwmgr->feature_mask & PP_OD_FUZZY_FAN_CONTROL_MASK) 2232 phm_cap_set(hwmgr->platform_descriptor.platformCaps, 2233 PHM_PlatformCaps_ODFuzzyFanControlSupport); 2234 } 2235 2236 return 0; 2237 } 2238 2239 /** 2240 * Change virtual leakage voltage to actual value. 2241 * 2242 * @param hwmgr the address of the powerplay hardware manager. 2243 * @param pointer to changing voltage 2244 * @param pointer to leakage table 2245 */ 2246 static void smu7_patch_ppt_v0_with_vdd_leakage(struct pp_hwmgr *hwmgr, 2247 uint32_t *voltage, struct smu7_leakage_voltage *leakage_table) 2248 { 2249 uint32_t index; 2250 2251 /* search for leakage voltage ID 0xff01 ~ 0xff08 */ 2252 for (index = 0; index < leakage_table->count; index++) { 2253 /* if this voltage matches a leakage voltage ID */ 2254 /* patch with actual leakage voltage */ 2255 if (leakage_table->leakage_id[index] == *voltage) { 2256 *voltage = leakage_table->actual_voltage[index]; 2257 break; 2258 } 2259 } 2260 2261 if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0) 2262 pr_err("Voltage value looks like a Leakage ID but it's not patched \n"); 2263 } 2264 2265 2266 static int smu7_patch_vddc(struct pp_hwmgr *hwmgr, 2267 struct phm_clock_voltage_dependency_table *tab) 2268 { 2269 uint16_t i; 2270 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2271 2272 if (tab) 2273 for (i = 0; i < tab->count; i++) 2274 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2275 &data->vddc_leakage); 2276 2277 return 0; 2278 } 2279 2280 static int smu7_patch_vddci(struct pp_hwmgr *hwmgr, 2281 struct phm_clock_voltage_dependency_table *tab) 2282 { 2283 uint16_t i; 2284 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2285 2286 if (tab) 2287 for (i = 0; i < tab->count; i++) 2288 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2289 &data->vddci_leakage); 2290 2291 return 0; 2292 } 2293 2294 static int smu7_patch_vce_vddc(struct pp_hwmgr *hwmgr, 2295 struct phm_vce_clock_voltage_dependency_table *tab) 2296 { 2297 uint16_t i; 2298 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2299 2300 if (tab) 2301 for (i = 0; i < tab->count; i++) 2302 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2303 &data->vddc_leakage); 2304 2305 return 0; 2306 } 2307 2308 2309 static int smu7_patch_uvd_vddc(struct pp_hwmgr *hwmgr, 2310 struct phm_uvd_clock_voltage_dependency_table *tab) 2311 { 2312 uint16_t i; 2313 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2314 2315 if (tab) 2316 for (i = 0; i < tab->count; i++) 2317 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2318 &data->vddc_leakage); 2319 2320 return 0; 2321 } 2322 2323 static int smu7_patch_vddc_shed_limit(struct pp_hwmgr *hwmgr, 2324 struct phm_phase_shedding_limits_table *tab) 2325 { 2326 uint16_t i; 2327 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2328 2329 if (tab) 2330 for (i = 0; i < tab->count; i++) 2331 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].Voltage, 2332 &data->vddc_leakage); 2333 2334 return 0; 2335 } 2336 2337 static int smu7_patch_samu_vddc(struct pp_hwmgr *hwmgr, 2338 struct phm_samu_clock_voltage_dependency_table *tab) 2339 { 2340 uint16_t i; 2341 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2342 2343 if (tab) 2344 for (i = 0; i < tab->count; i++) 2345 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2346 &data->vddc_leakage); 2347 2348 return 0; 2349 } 2350 2351 static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr, 2352 struct phm_acp_clock_voltage_dependency_table *tab) 2353 { 2354 uint16_t i; 2355 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2356 2357 if (tab) 2358 for (i = 0; i < tab->count; i++) 2359 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &tab->entries[i].v, 2360 &data->vddc_leakage); 2361 2362 return 0; 2363 } 2364 2365 static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr, 2366 struct phm_clock_and_voltage_limits *tab) 2367 { 2368 uint32_t vddc, vddci; 2369 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2370 2371 if (tab) { 2372 vddc = tab->vddc; 2373 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, 2374 &data->vddc_leakage); 2375 tab->vddc = vddc; 2376 vddci = tab->vddci; 2377 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci, 2378 &data->vddci_leakage); 2379 tab->vddci = vddci; 2380 } 2381 2382 return 0; 2383 } 2384 2385 static int smu7_patch_cac_vddc(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *tab) 2386 { 2387 uint32_t i; 2388 uint32_t vddc; 2389 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2390 2391 if (tab) { 2392 for (i = 0; i < tab->count; i++) { 2393 vddc = (uint32_t)(tab->entries[i].Vddc); 2394 smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc, &data->vddc_leakage); 2395 tab->entries[i].Vddc = (uint16_t)vddc; 2396 } 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int smu7_patch_dependency_tables_with_leakage(struct pp_hwmgr *hwmgr) 2403 { 2404 int tmp; 2405 2406 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_sclk); 2407 if (tmp) 2408 return -EINVAL; 2409 2410 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dependency_on_mclk); 2411 if (tmp) 2412 return -EINVAL; 2413 2414 tmp = smu7_patch_vddc(hwmgr, hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2415 if (tmp) 2416 return -EINVAL; 2417 2418 tmp = smu7_patch_vddci(hwmgr, hwmgr->dyn_state.vddci_dependency_on_mclk); 2419 if (tmp) 2420 return -EINVAL; 2421 2422 tmp = smu7_patch_vce_vddc(hwmgr, hwmgr->dyn_state.vce_clock_voltage_dependency_table); 2423 if (tmp) 2424 return -EINVAL; 2425 2426 tmp = smu7_patch_uvd_vddc(hwmgr, hwmgr->dyn_state.uvd_clock_voltage_dependency_table); 2427 if (tmp) 2428 return -EINVAL; 2429 2430 tmp = smu7_patch_samu_vddc(hwmgr, hwmgr->dyn_state.samu_clock_voltage_dependency_table); 2431 if (tmp) 2432 return -EINVAL; 2433 2434 tmp = smu7_patch_acp_vddc(hwmgr, hwmgr->dyn_state.acp_clock_voltage_dependency_table); 2435 if (tmp) 2436 return -EINVAL; 2437 2438 tmp = smu7_patch_vddc_shed_limit(hwmgr, hwmgr->dyn_state.vddc_phase_shed_limits_table); 2439 if (tmp) 2440 return -EINVAL; 2441 2442 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_ac); 2443 if (tmp) 2444 return -EINVAL; 2445 2446 tmp = smu7_patch_limits_vddc(hwmgr, &hwmgr->dyn_state.max_clock_voltage_on_dc); 2447 if (tmp) 2448 return -EINVAL; 2449 2450 tmp = smu7_patch_cac_vddc(hwmgr, hwmgr->dyn_state.cac_leakage_table); 2451 if (tmp) 2452 return -EINVAL; 2453 2454 return 0; 2455 } 2456 2457 2458 static int smu7_set_private_data_based_on_pptable_v0(struct pp_hwmgr *hwmgr) 2459 { 2460 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2461 2462 struct phm_clock_voltage_dependency_table *allowed_sclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 2463 struct phm_clock_voltage_dependency_table *allowed_mclk_vddc_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 2464 struct phm_clock_voltage_dependency_table *allowed_mclk_vddci_table = hwmgr->dyn_state.vddci_dependency_on_mclk; 2465 2466 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table != NULL, 2467 "VDDC dependency on SCLK table is missing. This table is mandatory", 2468 return -EINVAL); 2469 PP_ASSERT_WITH_CODE(allowed_sclk_vddc_table->count >= 1, 2470 "VDDC dependency on SCLK table has to have is missing. This table is mandatory", 2471 return -EINVAL); 2472 2473 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table != NULL, 2474 "VDDC dependency on MCLK table is missing. This table is mandatory", 2475 return -EINVAL); 2476 PP_ASSERT_WITH_CODE(allowed_mclk_vddc_table->count >= 1, 2477 "VDD dependency on MCLK table has to have is missing. This table is mandatory", 2478 return -EINVAL); 2479 2480 data->min_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[0].v; 2481 data->max_vddc_in_pptable = (uint16_t)allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2482 2483 hwmgr->dyn_state.max_clock_voltage_on_ac.sclk = 2484 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk; 2485 hwmgr->dyn_state.max_clock_voltage_on_ac.mclk = 2486 allowed_mclk_vddc_table->entries[allowed_mclk_vddc_table->count - 1].clk; 2487 hwmgr->dyn_state.max_clock_voltage_on_ac.vddc = 2488 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v; 2489 2490 if (allowed_mclk_vddci_table != NULL && allowed_mclk_vddci_table->count >= 1) { 2491 data->min_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[0].v; 2492 data->max_vddci_in_pptable = (uint16_t)allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v; 2493 } 2494 2495 if (hwmgr->dyn_state.vddci_dependency_on_mclk != NULL && hwmgr->dyn_state.vddci_dependency_on_mclk->count >= 1) 2496 hwmgr->dyn_state.max_clock_voltage_on_ac.vddci = hwmgr->dyn_state.vddci_dependency_on_mclk->entries[hwmgr->dyn_state.vddci_dependency_on_mclk->count - 1].v; 2497 2498 return 0; 2499 } 2500 2501 static int smu7_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) 2502 { 2503 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl); 2504 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL; 2505 kfree(hwmgr->backend); 2506 hwmgr->backend = NULL; 2507 2508 return 0; 2509 } 2510 2511 static int smu7_get_elb_voltages(struct pp_hwmgr *hwmgr) 2512 { 2513 uint16_t virtual_voltage_id, vddc, vddci, efuse_voltage_id; 2514 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2515 int i; 2516 2517 if (atomctrl_get_leakage_id_from_efuse(hwmgr, &efuse_voltage_id) == 0) { 2518 for (i = 0; i < SMU7_MAX_LEAKAGE_COUNT; i++) { 2519 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; 2520 if (atomctrl_get_leakage_vddc_base_on_leakage(hwmgr, &vddc, &vddci, 2521 virtual_voltage_id, 2522 efuse_voltage_id) == 0) { 2523 if (vddc != 0 && vddc != virtual_voltage_id) { 2524 data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc; 2525 data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id; 2526 data->vddc_leakage.count++; 2527 } 2528 if (vddci != 0 && vddci != virtual_voltage_id) { 2529 data->vddci_leakage.actual_voltage[data->vddci_leakage.count] = vddci; 2530 data->vddci_leakage.leakage_id[data->vddci_leakage.count] = virtual_voltage_id; 2531 data->vddci_leakage.count++; 2532 } 2533 } 2534 } 2535 } 2536 return 0; 2537 } 2538 2539 static int smu7_hwmgr_backend_init(struct pp_hwmgr *hwmgr) 2540 { 2541 struct smu7_hwmgr *data; 2542 int result = 0; 2543 2544 data = kzalloc(sizeof(struct smu7_hwmgr), GFP_KERNEL); 2545 if (data == NULL) 2546 return -ENOMEM; 2547 2548 hwmgr->backend = data; 2549 smu7_patch_voltage_workaround(hwmgr); 2550 smu7_init_dpm_defaults(hwmgr); 2551 2552 /* Get leakage voltage based on leakage ID. */ 2553 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2554 PHM_PlatformCaps_EVV)) { 2555 result = smu7_get_evv_voltages(hwmgr); 2556 if (result) { 2557 pr_info("Get EVV Voltage Failed. Abort Driver loading!\n"); 2558 return -EINVAL; 2559 } 2560 } else { 2561 smu7_get_elb_voltages(hwmgr); 2562 } 2563 2564 if (hwmgr->pp_table_version == PP_TABLE_V1) { 2565 smu7_complete_dependency_tables(hwmgr); 2566 smu7_set_private_data_based_on_pptable_v1(hwmgr); 2567 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 2568 smu7_patch_dependency_tables_with_leakage(hwmgr); 2569 smu7_set_private_data_based_on_pptable_v0(hwmgr); 2570 } 2571 2572 /* Initalize Dynamic State Adjustment Rule Settings */ 2573 result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); 2574 2575 if (0 == result) { 2576 struct amdgpu_device *adev = hwmgr->adev; 2577 2578 data->is_tlu_enabled = false; 2579 2580 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = 2581 SMU7_MAX_HARDWARE_POWERLEVELS; 2582 hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; 2583 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; 2584 2585 data->pcie_gen_cap = adev->pm.pcie_gen_mask; 2586 if (data->pcie_gen_cap & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 2587 data->pcie_spc_cap = 20; 2588 data->pcie_lane_cap = adev->pm.pcie_mlw_mask; 2589 2590 hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ 2591 /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */ 2592 hwmgr->platform_descriptor.clockStep.engineClock = 500; 2593 hwmgr->platform_descriptor.clockStep.memoryClock = 500; 2594 smu7_thermal_parameter_init(hwmgr); 2595 } else { 2596 /* Ignore return value in here, we are cleaning up a mess. */ 2597 smu7_hwmgr_backend_fini(hwmgr); 2598 } 2599 2600 return 0; 2601 } 2602 2603 static int smu7_force_dpm_highest(struct pp_hwmgr *hwmgr) 2604 { 2605 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2606 uint32_t level, tmp; 2607 2608 if (!data->pcie_dpm_key_disabled) { 2609 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 2610 level = 0; 2611 tmp = data->dpm_level_enable_mask.pcie_dpm_enable_mask; 2612 while (tmp >>= 1) 2613 level++; 2614 2615 if (level) 2616 smum_send_msg_to_smc_with_parameter(hwmgr, 2617 PPSMC_MSG_PCIeDPM_ForceLevel, level); 2618 } 2619 } 2620 2621 if (!data->sclk_dpm_key_disabled) { 2622 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 2623 level = 0; 2624 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 2625 while (tmp >>= 1) 2626 level++; 2627 2628 if (level) 2629 smum_send_msg_to_smc_with_parameter(hwmgr, 2630 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2631 (1 << level)); 2632 } 2633 } 2634 2635 if (!data->mclk_dpm_key_disabled) { 2636 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 2637 level = 0; 2638 tmp = data->dpm_level_enable_mask.mclk_dpm_enable_mask; 2639 while (tmp >>= 1) 2640 level++; 2641 2642 if (level) 2643 smum_send_msg_to_smc_with_parameter(hwmgr, 2644 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2645 (1 << level)); 2646 } 2647 } 2648 2649 return 0; 2650 } 2651 2652 static int smu7_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) 2653 { 2654 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2655 2656 if (hwmgr->pp_table_version == PP_TABLE_V1) 2657 phm_apply_dal_min_voltage_request(hwmgr); 2658 /* TO DO for v0 iceland and Ci*/ 2659 2660 if (!data->sclk_dpm_key_disabled) { 2661 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) 2662 smum_send_msg_to_smc_with_parameter(hwmgr, 2663 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2664 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 2665 } 2666 2667 if (!data->mclk_dpm_key_disabled) { 2668 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) 2669 smum_send_msg_to_smc_with_parameter(hwmgr, 2670 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2671 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 2672 } 2673 2674 return 0; 2675 } 2676 2677 static int smu7_unforce_dpm_levels(struct pp_hwmgr *hwmgr) 2678 { 2679 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2680 2681 if (!smum_is_dpm_running(hwmgr)) 2682 return -EINVAL; 2683 2684 if (!data->pcie_dpm_key_disabled) { 2685 smum_send_msg_to_smc(hwmgr, 2686 PPSMC_MSG_PCIeDPM_UnForceLevel); 2687 } 2688 2689 return smu7_upload_dpm_level_enable_mask(hwmgr); 2690 } 2691 2692 static int smu7_force_dpm_lowest(struct pp_hwmgr *hwmgr) 2693 { 2694 struct smu7_hwmgr *data = 2695 (struct smu7_hwmgr *)(hwmgr->backend); 2696 uint32_t level; 2697 2698 if (!data->sclk_dpm_key_disabled) 2699 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 2700 level = phm_get_lowest_enabled_level(hwmgr, 2701 data->dpm_level_enable_mask.sclk_dpm_enable_mask); 2702 smum_send_msg_to_smc_with_parameter(hwmgr, 2703 PPSMC_MSG_SCLKDPM_SetEnabledMask, 2704 (1 << level)); 2705 2706 } 2707 2708 if (!data->mclk_dpm_key_disabled) { 2709 if (data->dpm_level_enable_mask.mclk_dpm_enable_mask) { 2710 level = phm_get_lowest_enabled_level(hwmgr, 2711 data->dpm_level_enable_mask.mclk_dpm_enable_mask); 2712 smum_send_msg_to_smc_with_parameter(hwmgr, 2713 PPSMC_MSG_MCLKDPM_SetEnabledMask, 2714 (1 << level)); 2715 } 2716 } 2717 2718 if (!data->pcie_dpm_key_disabled) { 2719 if (data->dpm_level_enable_mask.pcie_dpm_enable_mask) { 2720 level = phm_get_lowest_enabled_level(hwmgr, 2721 data->dpm_level_enable_mask.pcie_dpm_enable_mask); 2722 smum_send_msg_to_smc_with_parameter(hwmgr, 2723 PPSMC_MSG_PCIeDPM_ForceLevel, 2724 (level)); 2725 } 2726 } 2727 2728 return 0; 2729 } 2730 2731 static int smu7_get_profiling_clk(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level, 2732 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *pcie_mask) 2733 { 2734 uint32_t percentage; 2735 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2736 struct smu7_dpm_table *golden_dpm_table = &data->golden_dpm_table; 2737 int32_t tmp_mclk; 2738 int32_t tmp_sclk; 2739 int32_t count; 2740 2741 if (golden_dpm_table->mclk_table.count < 1) 2742 return -EINVAL; 2743 2744 percentage = 100 * golden_dpm_table->sclk_table.dpm_levels[golden_dpm_table->sclk_table.count - 1].value / 2745 golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 2746 2747 if (golden_dpm_table->mclk_table.count == 1) { 2748 percentage = 70; 2749 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 1].value; 2750 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 2751 } else { 2752 tmp_mclk = golden_dpm_table->mclk_table.dpm_levels[golden_dpm_table->mclk_table.count - 2].value; 2753 *mclk_mask = golden_dpm_table->mclk_table.count - 2; 2754 } 2755 2756 tmp_sclk = tmp_mclk * percentage / 100; 2757 2758 if (hwmgr->pp_table_version == PP_TABLE_V0) { 2759 for (count = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 2760 count >= 0; count--) { 2761 if (tmp_sclk >= hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk) { 2762 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[count].clk; 2763 *sclk_mask = count; 2764 break; 2765 } 2766 } 2767 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2768 *sclk_mask = 0; 2769 tmp_sclk = hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].clk; 2770 } 2771 2772 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 2773 *sclk_mask = hwmgr->dyn_state.vddc_dependency_on_sclk->count-1; 2774 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 2775 struct phm_ppt_v1_information *table_info = 2776 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2777 2778 for (count = table_info->vdd_dep_on_sclk->count-1; count >= 0; count--) { 2779 if (tmp_sclk >= table_info->vdd_dep_on_sclk->entries[count].clk) { 2780 tmp_sclk = table_info->vdd_dep_on_sclk->entries[count].clk; 2781 *sclk_mask = count; 2782 break; 2783 } 2784 } 2785 if (count < 0 || level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) { 2786 *sclk_mask = 0; 2787 tmp_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 2788 } 2789 2790 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 2791 *sclk_mask = table_info->vdd_dep_on_sclk->count - 1; 2792 } 2793 2794 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) 2795 *mclk_mask = 0; 2796 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 2797 *mclk_mask = golden_dpm_table->mclk_table.count - 1; 2798 2799 *pcie_mask = data->dpm_table.pcie_speed_table.count - 1; 2800 hwmgr->pstate_sclk = tmp_sclk; 2801 hwmgr->pstate_mclk = tmp_mclk; 2802 2803 return 0; 2804 } 2805 2806 static int smu7_force_dpm_level(struct pp_hwmgr *hwmgr, 2807 enum amd_dpm_forced_level level) 2808 { 2809 int ret = 0; 2810 uint32_t sclk_mask = 0; 2811 uint32_t mclk_mask = 0; 2812 uint32_t pcie_mask = 0; 2813 2814 if (hwmgr->pstate_sclk == 0) 2815 smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 2816 2817 switch (level) { 2818 case AMD_DPM_FORCED_LEVEL_HIGH: 2819 ret = smu7_force_dpm_highest(hwmgr); 2820 break; 2821 case AMD_DPM_FORCED_LEVEL_LOW: 2822 ret = smu7_force_dpm_lowest(hwmgr); 2823 break; 2824 case AMD_DPM_FORCED_LEVEL_AUTO: 2825 ret = smu7_unforce_dpm_levels(hwmgr); 2826 break; 2827 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD: 2828 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK: 2829 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK: 2830 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK: 2831 ret = smu7_get_profiling_clk(hwmgr, level, &sclk_mask, &mclk_mask, &pcie_mask); 2832 if (ret) 2833 return ret; 2834 smu7_force_clock_level(hwmgr, PP_SCLK, 1<<sclk_mask); 2835 smu7_force_clock_level(hwmgr, PP_MCLK, 1<<mclk_mask); 2836 smu7_force_clock_level(hwmgr, PP_PCIE, 1<<pcie_mask); 2837 break; 2838 case AMD_DPM_FORCED_LEVEL_MANUAL: 2839 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT: 2840 default: 2841 break; 2842 } 2843 2844 if (!ret) { 2845 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 2846 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); 2847 else if (level != AMD_DPM_FORCED_LEVEL_PROFILE_PEAK && hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) 2848 smu7_fan_ctrl_reset_fan_speed_to_default(hwmgr); 2849 } 2850 return ret; 2851 } 2852 2853 static int smu7_get_power_state_size(struct pp_hwmgr *hwmgr) 2854 { 2855 return sizeof(struct smu7_power_state); 2856 } 2857 2858 static int smu7_vblank_too_short(struct pp_hwmgr *hwmgr, 2859 uint32_t vblank_time_us) 2860 { 2861 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2862 uint32_t switch_limit_us; 2863 2864 switch (hwmgr->chip_id) { 2865 case CHIP_POLARIS10: 2866 case CHIP_POLARIS11: 2867 case CHIP_POLARIS12: 2868 switch_limit_us = data->is_memory_gddr5 ? 190 : 150; 2869 break; 2870 case CHIP_VEGAM: 2871 switch_limit_us = 30; 2872 break; 2873 default: 2874 switch_limit_us = data->is_memory_gddr5 ? 450 : 150; 2875 break; 2876 } 2877 2878 if (vblank_time_us < switch_limit_us) 2879 return true; 2880 else 2881 return false; 2882 } 2883 2884 static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, 2885 struct pp_power_state *request_ps, 2886 const struct pp_power_state *current_ps) 2887 { 2888 struct amdgpu_device *adev = hwmgr->adev; 2889 struct smu7_power_state *smu7_ps = 2890 cast_phw_smu7_power_state(&request_ps->hardware); 2891 uint32_t sclk; 2892 uint32_t mclk; 2893 struct PP_Clocks minimum_clocks = {0}; 2894 bool disable_mclk_switching; 2895 bool disable_mclk_switching_for_frame_lock; 2896 const struct phm_clock_and_voltage_limits *max_limits; 2897 uint32_t i; 2898 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 2899 struct phm_ppt_v1_information *table_info = 2900 (struct phm_ppt_v1_information *)(hwmgr->pptable); 2901 int32_t count; 2902 int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; 2903 2904 data->battery_state = (PP_StateUILabel_Battery == 2905 request_ps->classification.ui_label); 2906 2907 PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, 2908 "VI should always have 2 performance levels", 2909 ); 2910 2911 max_limits = adev->pm.ac_power ? 2912 &(hwmgr->dyn_state.max_clock_voltage_on_ac) : 2913 &(hwmgr->dyn_state.max_clock_voltage_on_dc); 2914 2915 /* Cap clock DPM tables at DC MAX if it is in DC. */ 2916 if (!adev->pm.ac_power) { 2917 for (i = 0; i < smu7_ps->performance_level_count; i++) { 2918 if (smu7_ps->performance_levels[i].memory_clock > max_limits->mclk) 2919 smu7_ps->performance_levels[i].memory_clock = max_limits->mclk; 2920 if (smu7_ps->performance_levels[i].engine_clock > max_limits->sclk) 2921 smu7_ps->performance_levels[i].engine_clock = max_limits->sclk; 2922 } 2923 } 2924 2925 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; 2926 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; 2927 2928 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2929 PHM_PlatformCaps_StablePState)) { 2930 max_limits = &(hwmgr->dyn_state.max_clock_voltage_on_ac); 2931 stable_pstate_sclk = (max_limits->sclk * 75) / 100; 2932 2933 for (count = table_info->vdd_dep_on_sclk->count - 1; 2934 count >= 0; count--) { 2935 if (stable_pstate_sclk >= 2936 table_info->vdd_dep_on_sclk->entries[count].clk) { 2937 stable_pstate_sclk = 2938 table_info->vdd_dep_on_sclk->entries[count].clk; 2939 break; 2940 } 2941 } 2942 2943 if (count < 0) 2944 stable_pstate_sclk = table_info->vdd_dep_on_sclk->entries[0].clk; 2945 2946 stable_pstate_mclk = max_limits->mclk; 2947 2948 minimum_clocks.engineClock = stable_pstate_sclk; 2949 minimum_clocks.memoryClock = stable_pstate_mclk; 2950 } 2951 2952 disable_mclk_switching_for_frame_lock = phm_cap_enabled( 2953 hwmgr->platform_descriptor.platformCaps, 2954 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock); 2955 2956 2957 if (hwmgr->display_config->num_display == 0) 2958 disable_mclk_switching = false; 2959 else 2960 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) || 2961 disable_mclk_switching_for_frame_lock || 2962 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); 2963 2964 sclk = smu7_ps->performance_levels[0].engine_clock; 2965 mclk = smu7_ps->performance_levels[0].memory_clock; 2966 2967 if (disable_mclk_switching) 2968 mclk = smu7_ps->performance_levels 2969 [smu7_ps->performance_level_count - 1].memory_clock; 2970 2971 if (sclk < minimum_clocks.engineClock) 2972 sclk = (minimum_clocks.engineClock > max_limits->sclk) ? 2973 max_limits->sclk : minimum_clocks.engineClock; 2974 2975 if (mclk < minimum_clocks.memoryClock) 2976 mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? 2977 max_limits->mclk : minimum_clocks.memoryClock; 2978 2979 smu7_ps->performance_levels[0].engine_clock = sclk; 2980 smu7_ps->performance_levels[0].memory_clock = mclk; 2981 2982 smu7_ps->performance_levels[1].engine_clock = 2983 (smu7_ps->performance_levels[1].engine_clock >= 2984 smu7_ps->performance_levels[0].engine_clock) ? 2985 smu7_ps->performance_levels[1].engine_clock : 2986 smu7_ps->performance_levels[0].engine_clock; 2987 2988 if (disable_mclk_switching) { 2989 if (mclk < smu7_ps->performance_levels[1].memory_clock) 2990 mclk = smu7_ps->performance_levels[1].memory_clock; 2991 2992 smu7_ps->performance_levels[0].memory_clock = mclk; 2993 smu7_ps->performance_levels[1].memory_clock = mclk; 2994 } else { 2995 if (smu7_ps->performance_levels[1].memory_clock < 2996 smu7_ps->performance_levels[0].memory_clock) 2997 smu7_ps->performance_levels[1].memory_clock = 2998 smu7_ps->performance_levels[0].memory_clock; 2999 } 3000 3001 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3002 PHM_PlatformCaps_StablePState)) { 3003 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3004 smu7_ps->performance_levels[i].engine_clock = stable_pstate_sclk; 3005 smu7_ps->performance_levels[i].memory_clock = stable_pstate_mclk; 3006 smu7_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; 3007 smu7_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; 3008 } 3009 } 3010 return 0; 3011 } 3012 3013 3014 static uint32_t smu7_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) 3015 { 3016 struct pp_power_state *ps; 3017 struct smu7_power_state *smu7_ps; 3018 3019 if (hwmgr == NULL) 3020 return -EINVAL; 3021 3022 ps = hwmgr->request_ps; 3023 3024 if (ps == NULL) 3025 return -EINVAL; 3026 3027 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3028 3029 if (low) 3030 return smu7_ps->performance_levels[0].memory_clock; 3031 else 3032 return smu7_ps->performance_levels 3033 [smu7_ps->performance_level_count-1].memory_clock; 3034 } 3035 3036 static uint32_t smu7_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) 3037 { 3038 struct pp_power_state *ps; 3039 struct smu7_power_state *smu7_ps; 3040 3041 if (hwmgr == NULL) 3042 return -EINVAL; 3043 3044 ps = hwmgr->request_ps; 3045 3046 if (ps == NULL) 3047 return -EINVAL; 3048 3049 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 3050 3051 if (low) 3052 return smu7_ps->performance_levels[0].engine_clock; 3053 else 3054 return smu7_ps->performance_levels 3055 [smu7_ps->performance_level_count-1].engine_clock; 3056 } 3057 3058 static int smu7_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, 3059 struct pp_hw_power_state *hw_ps) 3060 { 3061 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3062 struct smu7_power_state *ps = (struct smu7_power_state *)hw_ps; 3063 ATOM_FIRMWARE_INFO_V2_2 *fw_info; 3064 uint16_t size; 3065 uint8_t frev, crev; 3066 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 3067 3068 /* First retrieve the Boot clocks and VDDC from the firmware info table. 3069 * We assume here that fw_info is unchanged if this call fails. 3070 */ 3071 fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, 3072 &size, &frev, &crev); 3073 if (!fw_info) 3074 /* During a test, there is no firmware info table. */ 3075 return 0; 3076 3077 /* Patch the state. */ 3078 data->vbios_boot_state.sclk_bootup_value = 3079 le32_to_cpu(fw_info->ulDefaultEngineClock); 3080 data->vbios_boot_state.mclk_bootup_value = 3081 le32_to_cpu(fw_info->ulDefaultMemoryClock); 3082 data->vbios_boot_state.mvdd_bootup_value = 3083 le16_to_cpu(fw_info->usBootUpMVDDCVoltage); 3084 data->vbios_boot_state.vddc_bootup_value = 3085 le16_to_cpu(fw_info->usBootUpVDDCVoltage); 3086 data->vbios_boot_state.vddci_bootup_value = 3087 le16_to_cpu(fw_info->usBootUpVDDCIVoltage); 3088 data->vbios_boot_state.pcie_gen_bootup_value = 3089 smu7_get_current_pcie_speed(hwmgr); 3090 3091 data->vbios_boot_state.pcie_lane_bootup_value = 3092 (uint16_t)smu7_get_current_pcie_lane_number(hwmgr); 3093 3094 /* set boot power state */ 3095 ps->performance_levels[0].memory_clock = data->vbios_boot_state.mclk_bootup_value; 3096 ps->performance_levels[0].engine_clock = data->vbios_boot_state.sclk_bootup_value; 3097 ps->performance_levels[0].pcie_gen = data->vbios_boot_state.pcie_gen_bootup_value; 3098 ps->performance_levels[0].pcie_lane = data->vbios_boot_state.pcie_lane_bootup_value; 3099 3100 return 0; 3101 } 3102 3103 static int smu7_get_number_of_powerplay_table_entries(struct pp_hwmgr *hwmgr) 3104 { 3105 int result; 3106 unsigned long ret = 0; 3107 3108 if (hwmgr->pp_table_version == PP_TABLE_V0) { 3109 result = pp_tables_get_num_of_entries(hwmgr, &ret); 3110 return result ? 0 : ret; 3111 } else if (hwmgr->pp_table_version == PP_TABLE_V1) { 3112 result = get_number_of_powerplay_table_entries_v1_0(hwmgr); 3113 return result; 3114 } 3115 return 0; 3116 } 3117 3118 static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr, 3119 void *state, struct pp_power_state *power_state, 3120 void *pp_table, uint32_t classification_flag) 3121 { 3122 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3123 struct smu7_power_state *smu7_power_state = 3124 (struct smu7_power_state *)(&(power_state->hardware)); 3125 struct smu7_performance_level *performance_level; 3126 ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; 3127 ATOM_Tonga_POWERPLAYTABLE *powerplay_table = 3128 (ATOM_Tonga_POWERPLAYTABLE *)pp_table; 3129 PPTable_Generic_SubTable_Header *sclk_dep_table = 3130 (PPTable_Generic_SubTable_Header *) 3131 (((unsigned long)powerplay_table) + 3132 le16_to_cpu(powerplay_table->usSclkDependencyTableOffset)); 3133 3134 ATOM_Tonga_MCLK_Dependency_Table *mclk_dep_table = 3135 (ATOM_Tonga_MCLK_Dependency_Table *) 3136 (((unsigned long)powerplay_table) + 3137 le16_to_cpu(powerplay_table->usMclkDependencyTableOffset)); 3138 3139 /* The following fields are not initialized here: id orderedList allStatesList */ 3140 power_state->classification.ui_label = 3141 (le16_to_cpu(state_entry->usClassification) & 3142 ATOM_PPLIB_CLASSIFICATION_UI_MASK) >> 3143 ATOM_PPLIB_CLASSIFICATION_UI_SHIFT; 3144 power_state->classification.flags = classification_flag; 3145 /* NOTE: There is a classification2 flag in BIOS that is not being used right now */ 3146 3147 power_state->classification.temporary_state = false; 3148 power_state->classification.to_be_deleted = false; 3149 3150 power_state->validation.disallowOnDC = 3151 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3152 ATOM_Tonga_DISALLOW_ON_DC)); 3153 3154 power_state->pcie.lanes = 0; 3155 3156 power_state->display.disableFrameModulation = false; 3157 power_state->display.limitRefreshrate = false; 3158 power_state->display.enableVariBright = 3159 (0 != (le32_to_cpu(state_entry->ulCapsAndSettings) & 3160 ATOM_Tonga_ENABLE_VARIBRIGHT)); 3161 3162 power_state->validation.supportedPowerLevels = 0; 3163 power_state->uvd_clocks.VCLK = 0; 3164 power_state->uvd_clocks.DCLK = 0; 3165 power_state->temperatures.min = 0; 3166 power_state->temperatures.max = 0; 3167 3168 performance_level = &(smu7_power_state->performance_levels 3169 [smu7_power_state->performance_level_count++]); 3170 3171 PP_ASSERT_WITH_CODE( 3172 (smu7_power_state->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3173 "Performance levels exceeds SMC limit!", 3174 return -EINVAL); 3175 3176 PP_ASSERT_WITH_CODE( 3177 (smu7_power_state->performance_level_count <= 3178 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3179 "Performance levels exceeds Driver limit!", 3180 return -EINVAL); 3181 3182 /* Performance levels are arranged from low to high. */ 3183 performance_level->memory_clock = mclk_dep_table->entries 3184 [state_entry->ucMemoryClockIndexLow].ulMclk; 3185 if (sclk_dep_table->ucRevId == 0) 3186 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3187 [state_entry->ucEngineClockIndexLow].ulSclk; 3188 else if (sclk_dep_table->ucRevId == 1) 3189 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3190 [state_entry->ucEngineClockIndexLow].ulSclk; 3191 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3192 state_entry->ucPCIEGenLow); 3193 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3194 state_entry->ucPCIELaneLow); 3195 3196 performance_level = &(smu7_power_state->performance_levels 3197 [smu7_power_state->performance_level_count++]); 3198 performance_level->memory_clock = mclk_dep_table->entries 3199 [state_entry->ucMemoryClockIndexHigh].ulMclk; 3200 3201 if (sclk_dep_table->ucRevId == 0) 3202 performance_level->engine_clock = ((ATOM_Tonga_SCLK_Dependency_Table *)sclk_dep_table)->entries 3203 [state_entry->ucEngineClockIndexHigh].ulSclk; 3204 else if (sclk_dep_table->ucRevId == 1) 3205 performance_level->engine_clock = ((ATOM_Polaris_SCLK_Dependency_Table *)sclk_dep_table)->entries 3206 [state_entry->ucEngineClockIndexHigh].ulSclk; 3207 3208 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, 3209 state_entry->ucPCIEGenHigh); 3210 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, 3211 state_entry->ucPCIELaneHigh); 3212 3213 return 0; 3214 } 3215 3216 static int smu7_get_pp_table_entry_v1(struct pp_hwmgr *hwmgr, 3217 unsigned long entry_index, struct pp_power_state *state) 3218 { 3219 int result; 3220 struct smu7_power_state *ps; 3221 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3222 struct phm_ppt_v1_information *table_info = 3223 (struct phm_ppt_v1_information *)(hwmgr->pptable); 3224 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = 3225 table_info->vdd_dep_on_mclk; 3226 3227 state->hardware.magic = PHM_VIslands_Magic; 3228 3229 ps = (struct smu7_power_state *)(&state->hardware); 3230 3231 result = get_powerplay_table_entry_v1_0(hwmgr, entry_index, state, 3232 smu7_get_pp_table_entry_callback_func_v1); 3233 3234 /* This is the earliest time we have all the dependency table and the VBIOS boot state 3235 * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state 3236 * if there is only one VDDCI/MCLK level, check if it's the same as VBIOS boot state 3237 */ 3238 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3239 if (dep_mclk_table->entries[0].clk != 3240 data->vbios_boot_state.mclk_bootup_value) 3241 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3242 "does not match VBIOS boot MCLK level"); 3243 if (dep_mclk_table->entries[0].vddci != 3244 data->vbios_boot_state.vddci_bootup_value) 3245 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3246 "does not match VBIOS boot VDDCI level"); 3247 } 3248 3249 /* set DC compatible flag if this state supports DC */ 3250 if (!state->validation.disallowOnDC) 3251 ps->dc_compatible = true; 3252 3253 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3254 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3255 3256 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3257 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3258 3259 if (!result) { 3260 uint32_t i; 3261 3262 switch (state->classification.ui_label) { 3263 case PP_StateUILabel_Performance: 3264 data->use_pcie_performance_levels = true; 3265 for (i = 0; i < ps->performance_level_count; i++) { 3266 if (data->pcie_gen_performance.max < 3267 ps->performance_levels[i].pcie_gen) 3268 data->pcie_gen_performance.max = 3269 ps->performance_levels[i].pcie_gen; 3270 3271 if (data->pcie_gen_performance.min > 3272 ps->performance_levels[i].pcie_gen) 3273 data->pcie_gen_performance.min = 3274 ps->performance_levels[i].pcie_gen; 3275 3276 if (data->pcie_lane_performance.max < 3277 ps->performance_levels[i].pcie_lane) 3278 data->pcie_lane_performance.max = 3279 ps->performance_levels[i].pcie_lane; 3280 if (data->pcie_lane_performance.min > 3281 ps->performance_levels[i].pcie_lane) 3282 data->pcie_lane_performance.min = 3283 ps->performance_levels[i].pcie_lane; 3284 } 3285 break; 3286 case PP_StateUILabel_Battery: 3287 data->use_pcie_power_saving_levels = true; 3288 3289 for (i = 0; i < ps->performance_level_count; i++) { 3290 if (data->pcie_gen_power_saving.max < 3291 ps->performance_levels[i].pcie_gen) 3292 data->pcie_gen_power_saving.max = 3293 ps->performance_levels[i].pcie_gen; 3294 3295 if (data->pcie_gen_power_saving.min > 3296 ps->performance_levels[i].pcie_gen) 3297 data->pcie_gen_power_saving.min = 3298 ps->performance_levels[i].pcie_gen; 3299 3300 if (data->pcie_lane_power_saving.max < 3301 ps->performance_levels[i].pcie_lane) 3302 data->pcie_lane_power_saving.max = 3303 ps->performance_levels[i].pcie_lane; 3304 3305 if (data->pcie_lane_power_saving.min > 3306 ps->performance_levels[i].pcie_lane) 3307 data->pcie_lane_power_saving.min = 3308 ps->performance_levels[i].pcie_lane; 3309 } 3310 break; 3311 default: 3312 break; 3313 } 3314 } 3315 return 0; 3316 } 3317 3318 static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr, 3319 struct pp_hw_power_state *power_state, 3320 unsigned int index, const void *clock_info) 3321 { 3322 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3323 struct smu7_power_state *ps = cast_phw_smu7_power_state(power_state); 3324 const ATOM_PPLIB_CI_CLOCK_INFO *visland_clk_info = clock_info; 3325 struct smu7_performance_level *performance_level; 3326 uint32_t engine_clock, memory_clock; 3327 uint16_t pcie_gen_from_bios; 3328 3329 engine_clock = visland_clk_info->ucEngineClockHigh << 16 | visland_clk_info->usEngineClockLow; 3330 memory_clock = visland_clk_info->ucMemoryClockHigh << 16 | visland_clk_info->usMemoryClockLow; 3331 3332 if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk) 3333 data->highest_mclk = memory_clock; 3334 3335 PP_ASSERT_WITH_CODE( 3336 (ps->performance_level_count < smum_get_mac_definition(hwmgr, SMU_MAX_LEVELS_GRAPHICS)), 3337 "Performance levels exceeds SMC limit!", 3338 return -EINVAL); 3339 3340 PP_ASSERT_WITH_CODE( 3341 (ps->performance_level_count < 3342 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), 3343 "Performance levels exceeds Driver limit, Skip!", 3344 return 0); 3345 3346 performance_level = &(ps->performance_levels 3347 [ps->performance_level_count++]); 3348 3349 /* Performance levels are arranged from low to high. */ 3350 performance_level->memory_clock = memory_clock; 3351 performance_level->engine_clock = engine_clock; 3352 3353 pcie_gen_from_bios = visland_clk_info->ucPCIEGen; 3354 3355 performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap, pcie_gen_from_bios); 3356 performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, visland_clk_info->usPCIELane); 3357 3358 return 0; 3359 } 3360 3361 static int smu7_get_pp_table_entry_v0(struct pp_hwmgr *hwmgr, 3362 unsigned long entry_index, struct pp_power_state *state) 3363 { 3364 int result; 3365 struct smu7_power_state *ps; 3366 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3367 struct phm_clock_voltage_dependency_table *dep_mclk_table = 3368 hwmgr->dyn_state.vddci_dependency_on_mclk; 3369 3370 memset(&state->hardware, 0x00, sizeof(struct pp_hw_power_state)); 3371 3372 state->hardware.magic = PHM_VIslands_Magic; 3373 3374 ps = (struct smu7_power_state *)(&state->hardware); 3375 3376 result = pp_tables_get_entry(hwmgr, entry_index, state, 3377 smu7_get_pp_table_entry_callback_func_v0); 3378 3379 /* 3380 * This is the earliest time we have all the dependency table 3381 * and the VBIOS boot state as 3382 * PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot 3383 * state if there is only one VDDCI/MCLK level, check if it's 3384 * the same as VBIOS boot state 3385 */ 3386 if (dep_mclk_table != NULL && dep_mclk_table->count == 1) { 3387 if (dep_mclk_table->entries[0].clk != 3388 data->vbios_boot_state.mclk_bootup_value) 3389 pr_debug("Single MCLK entry VDDCI/MCLK dependency table " 3390 "does not match VBIOS boot MCLK level"); 3391 if (dep_mclk_table->entries[0].v != 3392 data->vbios_boot_state.vddci_bootup_value) 3393 pr_debug("Single VDDCI entry VDDCI/MCLK dependency table " 3394 "does not match VBIOS boot VDDCI level"); 3395 } 3396 3397 /* set DC compatible flag if this state supports DC */ 3398 if (!state->validation.disallowOnDC) 3399 ps->dc_compatible = true; 3400 3401 if (state->classification.flags & PP_StateClassificationFlag_ACPI) 3402 data->acpi_pcie_gen = ps->performance_levels[0].pcie_gen; 3403 3404 ps->uvd_clks.vclk = state->uvd_clocks.VCLK; 3405 ps->uvd_clks.dclk = state->uvd_clocks.DCLK; 3406 3407 if (!result) { 3408 uint32_t i; 3409 3410 switch (state->classification.ui_label) { 3411 case PP_StateUILabel_Performance: 3412 data->use_pcie_performance_levels = true; 3413 3414 for (i = 0; i < ps->performance_level_count; i++) { 3415 if (data->pcie_gen_performance.max < 3416 ps->performance_levels[i].pcie_gen) 3417 data->pcie_gen_performance.max = 3418 ps->performance_levels[i].pcie_gen; 3419 3420 if (data->pcie_gen_performance.min > 3421 ps->performance_levels[i].pcie_gen) 3422 data->pcie_gen_performance.min = 3423 ps->performance_levels[i].pcie_gen; 3424 3425 if (data->pcie_lane_performance.max < 3426 ps->performance_levels[i].pcie_lane) 3427 data->pcie_lane_performance.max = 3428 ps->performance_levels[i].pcie_lane; 3429 3430 if (data->pcie_lane_performance.min > 3431 ps->performance_levels[i].pcie_lane) 3432 data->pcie_lane_performance.min = 3433 ps->performance_levels[i].pcie_lane; 3434 } 3435 break; 3436 case PP_StateUILabel_Battery: 3437 data->use_pcie_power_saving_levels = true; 3438 3439 for (i = 0; i < ps->performance_level_count; i++) { 3440 if (data->pcie_gen_power_saving.max < 3441 ps->performance_levels[i].pcie_gen) 3442 data->pcie_gen_power_saving.max = 3443 ps->performance_levels[i].pcie_gen; 3444 3445 if (data->pcie_gen_power_saving.min > 3446 ps->performance_levels[i].pcie_gen) 3447 data->pcie_gen_power_saving.min = 3448 ps->performance_levels[i].pcie_gen; 3449 3450 if (data->pcie_lane_power_saving.max < 3451 ps->performance_levels[i].pcie_lane) 3452 data->pcie_lane_power_saving.max = 3453 ps->performance_levels[i].pcie_lane; 3454 3455 if (data->pcie_lane_power_saving.min > 3456 ps->performance_levels[i].pcie_lane) 3457 data->pcie_lane_power_saving.min = 3458 ps->performance_levels[i].pcie_lane; 3459 } 3460 break; 3461 default: 3462 break; 3463 } 3464 } 3465 return 0; 3466 } 3467 3468 static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr, 3469 unsigned long entry_index, struct pp_power_state *state) 3470 { 3471 if (hwmgr->pp_table_version == PP_TABLE_V0) 3472 return smu7_get_pp_table_entry_v0(hwmgr, entry_index, state); 3473 else if (hwmgr->pp_table_version == PP_TABLE_V1) 3474 return smu7_get_pp_table_entry_v1(hwmgr, entry_index, state); 3475 3476 return 0; 3477 } 3478 3479 static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query) 3480 { 3481 struct amdgpu_device *adev = hwmgr->adev; 3482 int i; 3483 u32 tmp = 0; 3484 3485 if (!query) 3486 return -EINVAL; 3487 3488 /* 3489 * PPSMC_MSG_GetCurrPkgPwr is not supported on: 3490 * - Hawaii 3491 * - Bonaire 3492 * - Fiji 3493 * - Tonga 3494 */ 3495 if ((adev->asic_type != CHIP_HAWAII) && 3496 (adev->asic_type != CHIP_BONAIRE) && 3497 (adev->asic_type != CHIP_FIJI) && 3498 (adev->asic_type != CHIP_TONGA)) { 3499 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0); 3500 tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3501 *query = tmp; 3502 3503 if (tmp != 0) 3504 return 0; 3505 } 3506 3507 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart); 3508 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 3509 ixSMU_PM_STATUS_95, 0); 3510 3511 for (i = 0; i < 10; i++) { 3512 mdelay(500); 3513 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogSample); 3514 tmp = cgs_read_ind_register(hwmgr->device, 3515 CGS_IND_REG__SMC, 3516 ixSMU_PM_STATUS_95); 3517 if (tmp != 0) 3518 break; 3519 } 3520 *query = tmp; 3521 3522 return 0; 3523 } 3524 3525 static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx, 3526 void *value, int *size) 3527 { 3528 uint32_t sclk, mclk, activity_percent; 3529 uint32_t offset, val_vid; 3530 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3531 3532 /* size must be at least 4 bytes for all sensors */ 3533 if (*size < 4) 3534 return -EINVAL; 3535 3536 switch (idx) { 3537 case AMDGPU_PP_SENSOR_GFX_SCLK: 3538 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency); 3539 sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3540 *((uint32_t *)value) = sclk; 3541 *size = 4; 3542 return 0; 3543 case AMDGPU_PP_SENSOR_GFX_MCLK: 3544 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency); 3545 mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 3546 *((uint32_t *)value) = mclk; 3547 *size = 4; 3548 return 0; 3549 case AMDGPU_PP_SENSOR_GPU_LOAD: 3550 offset = data->soft_regs_start + smum_get_offsetof(hwmgr, 3551 SMU_SoftRegisters, 3552 AverageGraphicsActivity); 3553 3554 activity_percent = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset); 3555 activity_percent += 0x80; 3556 activity_percent >>= 8; 3557 *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent; 3558 *size = 4; 3559 return 0; 3560 case AMDGPU_PP_SENSOR_GPU_TEMP: 3561 *((uint32_t *)value) = smu7_thermal_get_temperature(hwmgr); 3562 *size = 4; 3563 return 0; 3564 case AMDGPU_PP_SENSOR_UVD_POWER: 3565 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1; 3566 *size = 4; 3567 return 0; 3568 case AMDGPU_PP_SENSOR_VCE_POWER: 3569 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1; 3570 *size = 4; 3571 return 0; 3572 case AMDGPU_PP_SENSOR_GPU_POWER: 3573 return smu7_get_gpu_power(hwmgr, (uint32_t *)value); 3574 case AMDGPU_PP_SENSOR_VDDGFX: 3575 if ((data->vr_config & VRCONF_VDDGFX_MASK) == 3576 (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT)) 3577 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 3578 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID); 3579 else 3580 val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device, 3581 CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE1_VID); 3582 3583 *((uint32_t *)value) = (uint32_t)convert_to_vddc(val_vid); 3584 return 0; 3585 default: 3586 return -EINVAL; 3587 } 3588 } 3589 3590 static int smu7_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) 3591 { 3592 const struct phm_set_power_state_input *states = 3593 (const struct phm_set_power_state_input *)input; 3594 const struct smu7_power_state *smu7_ps = 3595 cast_const_phw_smu7_power_state(states->pnew_state); 3596 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3597 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 3598 uint32_t sclk = smu7_ps->performance_levels 3599 [smu7_ps->performance_level_count - 1].engine_clock; 3600 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 3601 uint32_t mclk = smu7_ps->performance_levels 3602 [smu7_ps->performance_level_count - 1].memory_clock; 3603 struct PP_Clocks min_clocks = {0}; 3604 uint32_t i; 3605 3606 for (i = 0; i < sclk_table->count; i++) { 3607 if (sclk == sclk_table->dpm_levels[i].value) 3608 break; 3609 } 3610 3611 if (i >= sclk_table->count) 3612 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; 3613 else { 3614 /* TODO: Check SCLK in DAL's minimum clocks 3615 * in case DeepSleep divider update is required. 3616 */ 3617 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && 3618 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || 3619 data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 3620 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; 3621 } 3622 3623 for (i = 0; i < mclk_table->count; i++) { 3624 if (mclk == mclk_table->dpm_levels[i].value) 3625 break; 3626 } 3627 3628 if (i >= mclk_table->count) 3629 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; 3630 3631 3632 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 3633 data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; 3634 3635 return 0; 3636 } 3637 3638 static uint16_t smu7_get_maximum_link_speed(struct pp_hwmgr *hwmgr, 3639 const struct smu7_power_state *smu7_ps) 3640 { 3641 uint32_t i; 3642 uint32_t sclk, max_sclk = 0; 3643 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3644 struct smu7_dpm_table *dpm_table = &data->dpm_table; 3645 3646 for (i = 0; i < smu7_ps->performance_level_count; i++) { 3647 sclk = smu7_ps->performance_levels[i].engine_clock; 3648 if (max_sclk < sclk) 3649 max_sclk = sclk; 3650 } 3651 3652 for (i = 0; i < dpm_table->sclk_table.count; i++) { 3653 if (dpm_table->sclk_table.dpm_levels[i].value == max_sclk) 3654 return (uint16_t) ((i >= dpm_table->pcie_speed_table.count) ? 3655 dpm_table->pcie_speed_table.dpm_levels 3656 [dpm_table->pcie_speed_table.count - 1].value : 3657 dpm_table->pcie_speed_table.dpm_levels[i].value); 3658 } 3659 3660 return 0; 3661 } 3662 3663 static int smu7_request_link_speed_change_before_state_change( 3664 struct pp_hwmgr *hwmgr, const void *input) 3665 { 3666 const struct phm_set_power_state_input *states = 3667 (const struct phm_set_power_state_input *)input; 3668 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3669 const struct smu7_power_state *smu7_nps = 3670 cast_const_phw_smu7_power_state(states->pnew_state); 3671 const struct smu7_power_state *polaris10_cps = 3672 cast_const_phw_smu7_power_state(states->pcurrent_state); 3673 3674 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_nps); 3675 uint16_t current_link_speed; 3676 3677 if (data->force_pcie_gen == PP_PCIEGenInvalid) 3678 current_link_speed = smu7_get_maximum_link_speed(hwmgr, polaris10_cps); 3679 else 3680 current_link_speed = data->force_pcie_gen; 3681 3682 data->force_pcie_gen = PP_PCIEGenInvalid; 3683 data->pspp_notify_required = false; 3684 3685 if (target_link_speed > current_link_speed) { 3686 switch (target_link_speed) { 3687 #ifdef CONFIG_ACPI 3688 case PP_PCIEGen3: 3689 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN3, false)) 3690 break; 3691 data->force_pcie_gen = PP_PCIEGen2; 3692 if (current_link_speed == PP_PCIEGen2) 3693 break; 3694 case PP_PCIEGen2: 3695 if (0 == amdgpu_acpi_pcie_performance_request(hwmgr->adev, PCIE_PERF_REQ_GEN2, false)) 3696 break; 3697 #endif 3698 default: 3699 data->force_pcie_gen = smu7_get_current_pcie_speed(hwmgr); 3700 break; 3701 } 3702 } else { 3703 if (target_link_speed < current_link_speed) 3704 data->pspp_notify_required = true; 3705 } 3706 3707 return 0; 3708 } 3709 3710 static int smu7_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 3711 { 3712 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3713 3714 if (0 == data->need_update_smu7_dpm_table) 3715 return 0; 3716 3717 if ((0 == data->sclk_dpm_key_disabled) && 3718 (data->need_update_smu7_dpm_table & 3719 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 3720 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3721 "Trying to freeze SCLK DPM when DPM is disabled", 3722 ); 3723 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3724 PPSMC_MSG_SCLKDPM_FreezeLevel), 3725 "Failed to freeze SCLK DPM during FreezeSclkMclkDPM Function!", 3726 return -EINVAL); 3727 } 3728 3729 if ((0 == data->mclk_dpm_key_disabled) && 3730 (data->need_update_smu7_dpm_table & 3731 DPMTABLE_OD_UPDATE_MCLK)) { 3732 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3733 "Trying to freeze MCLK DPM when DPM is disabled", 3734 ); 3735 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3736 PPSMC_MSG_MCLKDPM_FreezeLevel), 3737 "Failed to freeze MCLK DPM during FreezeSclkMclkDPM Function!", 3738 return -EINVAL); 3739 } 3740 3741 return 0; 3742 } 3743 3744 static int smu7_populate_and_upload_sclk_mclk_dpm_levels( 3745 struct pp_hwmgr *hwmgr, const void *input) 3746 { 3747 int result = 0; 3748 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3749 struct smu7_dpm_table *dpm_table = &data->dpm_table; 3750 uint32_t count; 3751 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 3752 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 3753 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 3754 3755 if (0 == data->need_update_smu7_dpm_table) 3756 return 0; 3757 3758 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { 3759 for (count = 0; count < dpm_table->sclk_table.count; count++) { 3760 dpm_table->sclk_table.dpm_levels[count].enabled = odn_sclk_table->entries[count].enabled; 3761 dpm_table->sclk_table.dpm_levels[count].value = odn_sclk_table->entries[count].clock; 3762 } 3763 } 3764 3765 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) { 3766 for (count = 0; count < dpm_table->mclk_table.count; count++) { 3767 dpm_table->mclk_table.dpm_levels[count].enabled = odn_mclk_table->entries[count].enabled; 3768 dpm_table->mclk_table.dpm_levels[count].value = odn_mclk_table->entries[count].clock; 3769 } 3770 } 3771 3772 if (data->need_update_smu7_dpm_table & 3773 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { 3774 result = smum_populate_all_graphic_levels(hwmgr); 3775 PP_ASSERT_WITH_CODE((0 == result), 3776 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", 3777 return result); 3778 } 3779 3780 if (data->need_update_smu7_dpm_table & 3781 (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { 3782 /*populate MCLK dpm table to SMU7 */ 3783 result = smum_populate_all_memory_levels(hwmgr); 3784 PP_ASSERT_WITH_CODE((0 == result), 3785 "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", 3786 return result); 3787 } 3788 3789 return result; 3790 } 3791 3792 static int smu7_trim_single_dpm_states(struct pp_hwmgr *hwmgr, 3793 struct smu7_single_dpm_table *dpm_table, 3794 uint32_t low_limit, uint32_t high_limit) 3795 { 3796 uint32_t i; 3797 3798 /* force the trim if mclk_switching is disabled to prevent flicker */ 3799 bool force_trim = (low_limit == high_limit); 3800 for (i = 0; i < dpm_table->count; i++) { 3801 /*skip the trim if od is enabled*/ 3802 if ((!hwmgr->od_enabled || force_trim) 3803 && (dpm_table->dpm_levels[i].value < low_limit 3804 || dpm_table->dpm_levels[i].value > high_limit)) 3805 dpm_table->dpm_levels[i].enabled = false; 3806 else 3807 dpm_table->dpm_levels[i].enabled = true; 3808 } 3809 3810 return 0; 3811 } 3812 3813 static int smu7_trim_dpm_states(struct pp_hwmgr *hwmgr, 3814 const struct smu7_power_state *smu7_ps) 3815 { 3816 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3817 uint32_t high_limit_count; 3818 3819 PP_ASSERT_WITH_CODE((smu7_ps->performance_level_count >= 1), 3820 "power state did not have any performance level", 3821 return -EINVAL); 3822 3823 high_limit_count = (1 == smu7_ps->performance_level_count) ? 0 : 1; 3824 3825 smu7_trim_single_dpm_states(hwmgr, 3826 &(data->dpm_table.sclk_table), 3827 smu7_ps->performance_levels[0].engine_clock, 3828 smu7_ps->performance_levels[high_limit_count].engine_clock); 3829 3830 smu7_trim_single_dpm_states(hwmgr, 3831 &(data->dpm_table.mclk_table), 3832 smu7_ps->performance_levels[0].memory_clock, 3833 smu7_ps->performance_levels[high_limit_count].memory_clock); 3834 3835 return 0; 3836 } 3837 3838 static int smu7_generate_dpm_level_enable_mask( 3839 struct pp_hwmgr *hwmgr, const void *input) 3840 { 3841 int result = 0; 3842 const struct phm_set_power_state_input *states = 3843 (const struct phm_set_power_state_input *)input; 3844 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3845 const struct smu7_power_state *smu7_ps = 3846 cast_const_phw_smu7_power_state(states->pnew_state); 3847 3848 3849 result = smu7_trim_dpm_states(hwmgr, smu7_ps); 3850 if (result) 3851 return result; 3852 3853 data->dpm_level_enable_mask.sclk_dpm_enable_mask = 3854 phm_get_dpm_level_enable_mask_value(&data->dpm_table.sclk_table); 3855 data->dpm_level_enable_mask.mclk_dpm_enable_mask = 3856 phm_get_dpm_level_enable_mask_value(&data->dpm_table.mclk_table); 3857 data->dpm_level_enable_mask.pcie_dpm_enable_mask = 3858 phm_get_dpm_level_enable_mask_value(&data->dpm_table.pcie_speed_table); 3859 3860 return 0; 3861 } 3862 3863 static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) 3864 { 3865 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3866 3867 if (0 == data->need_update_smu7_dpm_table) 3868 return 0; 3869 3870 if ((0 == data->sclk_dpm_key_disabled) && 3871 (data->need_update_smu7_dpm_table & 3872 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { 3873 3874 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3875 "Trying to Unfreeze SCLK DPM when DPM is disabled", 3876 ); 3877 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3878 PPSMC_MSG_SCLKDPM_UnfreezeLevel), 3879 "Failed to unfreeze SCLK DPM during UnFreezeSclkMclkDPM Function!", 3880 return -EINVAL); 3881 } 3882 3883 if ((0 == data->mclk_dpm_key_disabled) && 3884 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { 3885 3886 PP_ASSERT_WITH_CODE(true == smum_is_dpm_running(hwmgr), 3887 "Trying to Unfreeze MCLK DPM when DPM is disabled", 3888 ); 3889 PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr, 3890 PPSMC_MSG_MCLKDPM_UnfreezeLevel), 3891 "Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM Function!", 3892 return -EINVAL); 3893 } 3894 3895 data->need_update_smu7_dpm_table &= DPMTABLE_OD_UPDATE_VDDC; 3896 3897 return 0; 3898 } 3899 3900 static int smu7_notify_link_speed_change_after_state_change( 3901 struct pp_hwmgr *hwmgr, const void *input) 3902 { 3903 const struct phm_set_power_state_input *states = 3904 (const struct phm_set_power_state_input *)input; 3905 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3906 const struct smu7_power_state *smu7_ps = 3907 cast_const_phw_smu7_power_state(states->pnew_state); 3908 uint16_t target_link_speed = smu7_get_maximum_link_speed(hwmgr, smu7_ps); 3909 uint8_t request; 3910 3911 if (data->pspp_notify_required) { 3912 if (target_link_speed == PP_PCIEGen3) 3913 request = PCIE_PERF_REQ_GEN3; 3914 else if (target_link_speed == PP_PCIEGen2) 3915 request = PCIE_PERF_REQ_GEN2; 3916 else 3917 request = PCIE_PERF_REQ_GEN1; 3918 3919 if (request == PCIE_PERF_REQ_GEN1 && 3920 smu7_get_current_pcie_speed(hwmgr) > 0) 3921 return 0; 3922 3923 #ifdef CONFIG_ACPI 3924 if (amdgpu_acpi_pcie_performance_request(hwmgr->adev, request, false)) { 3925 if (PP_PCIEGen2 == target_link_speed) 3926 pr_info("PSPP request to switch to Gen2 from Gen3 Failed!"); 3927 else 3928 pr_info("PSPP request to switch to Gen1 from Gen2 Failed!"); 3929 } 3930 #endif 3931 } 3932 3933 return 0; 3934 } 3935 3936 static int smu7_notify_smc_display(struct pp_hwmgr *hwmgr) 3937 { 3938 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3939 3940 if (hwmgr->feature_mask & PP_VBI_TIME_SUPPORT_MASK) { 3941 if (hwmgr->chip_id == CHIP_VEGAM) 3942 smum_send_msg_to_smc_with_parameter(hwmgr, 3943 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout_VEGAM, data->frame_time_x2); 3944 else 3945 smum_send_msg_to_smc_with_parameter(hwmgr, 3946 (PPSMC_Msg)PPSMC_MSG_SetVBITimeout, data->frame_time_x2); 3947 } 3948 return (smum_send_msg_to_smc(hwmgr, (PPSMC_Msg)PPSMC_HasDisplay) == 0) ? 0 : -EINVAL; 3949 } 3950 3951 static int smu7_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) 3952 { 3953 int tmp_result, result = 0; 3954 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 3955 3956 tmp_result = smu7_find_dpm_states_clocks_in_dpm_table(hwmgr, input); 3957 PP_ASSERT_WITH_CODE((0 == tmp_result), 3958 "Failed to find DPM states clocks in DPM table!", 3959 result = tmp_result); 3960 3961 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 3962 PHM_PlatformCaps_PCIEPerformanceRequest)) { 3963 tmp_result = 3964 smu7_request_link_speed_change_before_state_change(hwmgr, input); 3965 PP_ASSERT_WITH_CODE((0 == tmp_result), 3966 "Failed to request link speed change before state change!", 3967 result = tmp_result); 3968 } 3969 3970 tmp_result = smu7_freeze_sclk_mclk_dpm(hwmgr); 3971 PP_ASSERT_WITH_CODE((0 == tmp_result), 3972 "Failed to freeze SCLK MCLK DPM!", result = tmp_result); 3973 3974 tmp_result = smu7_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); 3975 PP_ASSERT_WITH_CODE((0 == tmp_result), 3976 "Failed to populate and upload SCLK MCLK DPM levels!", 3977 result = tmp_result); 3978 3979 /* 3980 * If a custom pp table is loaded, set DPMTABLE_OD_UPDATE_VDDC flag. 3981 * That effectively disables AVFS feature. 3982 */ 3983 if (hwmgr->hardcode_pp_table != NULL) 3984 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC; 3985 3986 tmp_result = smu7_update_avfs(hwmgr); 3987 PP_ASSERT_WITH_CODE((0 == tmp_result), 3988 "Failed to update avfs voltages!", 3989 result = tmp_result); 3990 3991 tmp_result = smu7_generate_dpm_level_enable_mask(hwmgr, input); 3992 PP_ASSERT_WITH_CODE((0 == tmp_result), 3993 "Failed to generate DPM level enabled mask!", 3994 result = tmp_result); 3995 3996 tmp_result = smum_update_sclk_threshold(hwmgr); 3997 PP_ASSERT_WITH_CODE((0 == tmp_result), 3998 "Failed to update SCLK threshold!", 3999 result = tmp_result); 4000 4001 tmp_result = smu7_notify_smc_display(hwmgr); 4002 PP_ASSERT_WITH_CODE((0 == tmp_result), 4003 "Failed to notify smc display settings!", 4004 result = tmp_result); 4005 4006 tmp_result = smu7_unfreeze_sclk_mclk_dpm(hwmgr); 4007 PP_ASSERT_WITH_CODE((0 == tmp_result), 4008 "Failed to unfreeze SCLK MCLK DPM!", 4009 result = tmp_result); 4010 4011 tmp_result = smu7_upload_dpm_level_enable_mask(hwmgr); 4012 PP_ASSERT_WITH_CODE((0 == tmp_result), 4013 "Failed to upload DPM level enabled mask!", 4014 result = tmp_result); 4015 4016 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4017 PHM_PlatformCaps_PCIEPerformanceRequest)) { 4018 tmp_result = 4019 smu7_notify_link_speed_change_after_state_change(hwmgr, input); 4020 PP_ASSERT_WITH_CODE((0 == tmp_result), 4021 "Failed to notify link speed change after state change!", 4022 result = tmp_result); 4023 } 4024 data->apply_optimized_settings = false; 4025 return result; 4026 } 4027 4028 static int smu7_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) 4029 { 4030 hwmgr->thermal_controller. 4031 advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; 4032 4033 return smum_send_msg_to_smc_with_parameter(hwmgr, 4034 PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); 4035 } 4036 4037 static int 4038 smu7_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) 4039 { 4040 PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; 4041 4042 return (smum_send_msg_to_smc(hwmgr, msg) == 0) ? 0 : -1; 4043 } 4044 4045 static int 4046 smu7_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) 4047 { 4048 if (hwmgr->display_config->num_display > 1 && 4049 !hwmgr->display_config->multi_monitor_in_sync) 4050 smu7_notify_smc_display_change(hwmgr, false); 4051 4052 return 0; 4053 } 4054 4055 /** 4056 * Programs the display gap 4057 * 4058 * @param hwmgr the address of the powerplay hardware manager. 4059 * @return always OK 4060 */ 4061 static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 4062 { 4063 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4064 uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); 4065 uint32_t display_gap2; 4066 uint32_t pre_vbi_time_in_us; 4067 uint32_t frame_time_in_us; 4068 uint32_t ref_clock, refresh_rate; 4069 4070 display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (hwmgr->display_config->num_display > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE); 4071 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap); 4072 4073 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev); 4074 refresh_rate = hwmgr->display_config->vrefresh; 4075 4076 if (0 == refresh_rate) 4077 refresh_rate = 60; 4078 4079 frame_time_in_us = 1000000 / refresh_rate; 4080 4081 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; 4082 4083 data->frame_time_x2 = frame_time_in_us * 2 / 100; 4084 4085 if (data->frame_time_x2 < 280) { 4086 pr_debug("%s: enforce minimal VBITimeout: %d -> 280\n", __func__, data->frame_time_x2); 4087 data->frame_time_x2 = 280; 4088 } 4089 4090 display_gap2 = pre_vbi_time_in_us * (ref_clock / 100); 4091 4092 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL2, display_gap2); 4093 4094 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4095 data->soft_regs_start + smum_get_offsetof(hwmgr, 4096 SMU_SoftRegisters, 4097 PreVBlankGap), 0x64); 4098 4099 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4100 data->soft_regs_start + smum_get_offsetof(hwmgr, 4101 SMU_SoftRegisters, 4102 VBlankTimeout), 4103 (frame_time_in_us - pre_vbi_time_in_us)); 4104 4105 return 0; 4106 } 4107 4108 static int smu7_display_configuration_changed_task(struct pp_hwmgr *hwmgr) 4109 { 4110 return smu7_program_display_gap(hwmgr); 4111 } 4112 4113 /** 4114 * Set maximum target operating fan output RPM 4115 * 4116 * @param hwmgr: the address of the powerplay hardware manager. 4117 * @param usMaxFanRpm: max operating fan RPM value. 4118 * @return The response that came from the SMC. 4119 */ 4120 static int smu7_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) 4121 { 4122 hwmgr->thermal_controller. 4123 advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; 4124 4125 return smum_send_msg_to_smc_with_parameter(hwmgr, 4126 PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); 4127 } 4128 4129 static const struct amdgpu_irq_src_funcs smu7_irq_funcs = { 4130 .process = phm_irq_process, 4131 }; 4132 4133 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) 4134 { 4135 struct amdgpu_irq_src *source = 4136 kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL); 4137 4138 if (!source) 4139 return -ENOMEM; 4140 4141 source->funcs = &smu7_irq_funcs; 4142 4143 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4144 AMDGPU_IH_CLIENTID_LEGACY, 4145 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, 4146 source); 4147 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4148 AMDGPU_IH_CLIENTID_LEGACY, 4149 VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, 4150 source); 4151 4152 /* Register CTF(GPIO_19) interrupt */ 4153 amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), 4154 AMDGPU_IH_CLIENTID_LEGACY, 4155 VISLANDS30_IV_SRCID_GPIO_19, 4156 source); 4157 4158 return 0; 4159 } 4160 4161 static bool 4162 smu7_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) 4163 { 4164 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4165 bool is_update_required = false; 4166 4167 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) 4168 is_update_required = true; 4169 4170 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { 4171 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr && 4172 (data->display_timing.min_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK || 4173 hwmgr->display_config->min_core_set_clock_in_sr >= SMU7_MINIMUM_ENGINE_CLOCK)) 4174 is_update_required = true; 4175 } 4176 return is_update_required; 4177 } 4178 4179 static inline bool smu7_are_power_levels_equal(const struct smu7_performance_level *pl1, 4180 const struct smu7_performance_level *pl2) 4181 { 4182 return ((pl1->memory_clock == pl2->memory_clock) && 4183 (pl1->engine_clock == pl2->engine_clock) && 4184 (pl1->pcie_gen == pl2->pcie_gen) && 4185 (pl1->pcie_lane == pl2->pcie_lane)); 4186 } 4187 4188 static int smu7_check_states_equal(struct pp_hwmgr *hwmgr, 4189 const struct pp_hw_power_state *pstate1, 4190 const struct pp_hw_power_state *pstate2, bool *equal) 4191 { 4192 const struct smu7_power_state *psa; 4193 const struct smu7_power_state *psb; 4194 int i; 4195 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4196 4197 if (pstate1 == NULL || pstate2 == NULL || equal == NULL) 4198 return -EINVAL; 4199 4200 psa = cast_const_phw_smu7_power_state(pstate1); 4201 psb = cast_const_phw_smu7_power_state(pstate2); 4202 /* If the two states don't even have the same number of performance levels they cannot be the same state. */ 4203 if (psa->performance_level_count != psb->performance_level_count) { 4204 *equal = false; 4205 return 0; 4206 } 4207 4208 for (i = 0; i < psa->performance_level_count; i++) { 4209 if (!smu7_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { 4210 /* If we have found even one performance level pair that is different the states are different. */ 4211 *equal = false; 4212 return 0; 4213 } 4214 } 4215 4216 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/ 4217 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk)); 4218 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk)); 4219 *equal &= (psa->sclk_threshold == psb->sclk_threshold); 4220 /* For OD call, set value based on flag */ 4221 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | 4222 DPMTABLE_OD_UPDATE_MCLK | 4223 DPMTABLE_OD_UPDATE_VDDC)); 4224 4225 return 0; 4226 } 4227 4228 static int smu7_check_mc_firmware(struct pp_hwmgr *hwmgr) 4229 { 4230 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4231 4232 uint32_t vbios_version; 4233 uint32_t tmp; 4234 4235 /* Read MC indirect register offset 0x9F bits [3:0] to see 4236 * if VBIOS has already loaded a full version of MC ucode 4237 * or not. 4238 */ 4239 4240 smu7_get_mc_microcode_version(hwmgr); 4241 vbios_version = hwmgr->microcode_version_info.MC & 0xf; 4242 4243 data->need_long_memory_training = false; 4244 4245 cgs_write_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_INDEX, 4246 ixMC_IO_DEBUG_UP_13); 4247 tmp = cgs_read_register(hwmgr->device, mmMC_SEQ_IO_DEBUG_DATA); 4248 4249 if (tmp & (1 << 23)) { 4250 data->mem_latency_high = MEM_LATENCY_HIGH; 4251 data->mem_latency_low = MEM_LATENCY_LOW; 4252 } else { 4253 data->mem_latency_high = 330; 4254 data->mem_latency_low = 330; 4255 } 4256 4257 return 0; 4258 } 4259 4260 static int smu7_read_clock_registers(struct pp_hwmgr *hwmgr) 4261 { 4262 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4263 4264 data->clock_registers.vCG_SPLL_FUNC_CNTL = 4265 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL); 4266 data->clock_registers.vCG_SPLL_FUNC_CNTL_2 = 4267 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2); 4268 data->clock_registers.vCG_SPLL_FUNC_CNTL_3 = 4269 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3); 4270 data->clock_registers.vCG_SPLL_FUNC_CNTL_4 = 4271 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4); 4272 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM = 4273 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM); 4274 data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 = 4275 cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2); 4276 data->clock_registers.vDLL_CNTL = 4277 cgs_read_register(hwmgr->device, mmDLL_CNTL); 4278 data->clock_registers.vMCLK_PWRMGT_CNTL = 4279 cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL); 4280 data->clock_registers.vMPLL_AD_FUNC_CNTL = 4281 cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL); 4282 data->clock_registers.vMPLL_DQ_FUNC_CNTL = 4283 cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL); 4284 data->clock_registers.vMPLL_FUNC_CNTL = 4285 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL); 4286 data->clock_registers.vMPLL_FUNC_CNTL_1 = 4287 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1); 4288 data->clock_registers.vMPLL_FUNC_CNTL_2 = 4289 cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2); 4290 data->clock_registers.vMPLL_SS1 = 4291 cgs_read_register(hwmgr->device, mmMPLL_SS1); 4292 data->clock_registers.vMPLL_SS2 = 4293 cgs_read_register(hwmgr->device, mmMPLL_SS2); 4294 return 0; 4295 4296 } 4297 4298 /** 4299 * Find out if memory is GDDR5. 4300 * 4301 * @param hwmgr the address of the powerplay hardware manager. 4302 * @return always 0 4303 */ 4304 static int smu7_get_memory_type(struct pp_hwmgr *hwmgr) 4305 { 4306 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4307 struct amdgpu_device *adev = hwmgr->adev; 4308 4309 data->is_memory_gddr5 = (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5); 4310 4311 return 0; 4312 } 4313 4314 /** 4315 * Enables Dynamic Power Management by SMC 4316 * 4317 * @param hwmgr the address of the powerplay hardware manager. 4318 * @return always 0 4319 */ 4320 static int smu7_enable_acpi_power_management(struct pp_hwmgr *hwmgr) 4321 { 4322 PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, 4323 GENERAL_PWRMGT, STATIC_PM_EN, 1); 4324 4325 return 0; 4326 } 4327 4328 /** 4329 * Initialize PowerGating States for different engines 4330 * 4331 * @param hwmgr the address of the powerplay hardware manager. 4332 * @return always 0 4333 */ 4334 static int smu7_init_power_gate_state(struct pp_hwmgr *hwmgr) 4335 { 4336 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4337 4338 data->uvd_power_gated = false; 4339 data->vce_power_gated = false; 4340 4341 return 0; 4342 } 4343 4344 static int smu7_init_sclk_threshold(struct pp_hwmgr *hwmgr) 4345 { 4346 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4347 4348 data->low_sclk_interrupt_threshold = 0; 4349 return 0; 4350 } 4351 4352 static int smu7_setup_asic_task(struct pp_hwmgr *hwmgr) 4353 { 4354 int tmp_result, result = 0; 4355 4356 smu7_check_mc_firmware(hwmgr); 4357 4358 tmp_result = smu7_read_clock_registers(hwmgr); 4359 PP_ASSERT_WITH_CODE((0 == tmp_result), 4360 "Failed to read clock registers!", result = tmp_result); 4361 4362 tmp_result = smu7_get_memory_type(hwmgr); 4363 PP_ASSERT_WITH_CODE((0 == tmp_result), 4364 "Failed to get memory type!", result = tmp_result); 4365 4366 tmp_result = smu7_enable_acpi_power_management(hwmgr); 4367 PP_ASSERT_WITH_CODE((0 == tmp_result), 4368 "Failed to enable ACPI power management!", result = tmp_result); 4369 4370 tmp_result = smu7_init_power_gate_state(hwmgr); 4371 PP_ASSERT_WITH_CODE((0 == tmp_result), 4372 "Failed to init power gate state!", result = tmp_result); 4373 4374 tmp_result = smu7_get_mc_microcode_version(hwmgr); 4375 PP_ASSERT_WITH_CODE((0 == tmp_result), 4376 "Failed to get MC microcode version!", result = tmp_result); 4377 4378 tmp_result = smu7_init_sclk_threshold(hwmgr); 4379 PP_ASSERT_WITH_CODE((0 == tmp_result), 4380 "Failed to init sclk threshold!", result = tmp_result); 4381 4382 return result; 4383 } 4384 4385 static int smu7_force_clock_level(struct pp_hwmgr *hwmgr, 4386 enum pp_clock_type type, uint32_t mask) 4387 { 4388 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4389 4390 if (mask == 0) 4391 return -EINVAL; 4392 4393 switch (type) { 4394 case PP_SCLK: 4395 if (!data->sclk_dpm_key_disabled) 4396 smum_send_msg_to_smc_with_parameter(hwmgr, 4397 PPSMC_MSG_SCLKDPM_SetEnabledMask, 4398 data->dpm_level_enable_mask.sclk_dpm_enable_mask & mask); 4399 break; 4400 case PP_MCLK: 4401 if (!data->mclk_dpm_key_disabled) 4402 smum_send_msg_to_smc_with_parameter(hwmgr, 4403 PPSMC_MSG_MCLKDPM_SetEnabledMask, 4404 data->dpm_level_enable_mask.mclk_dpm_enable_mask & mask); 4405 break; 4406 case PP_PCIE: 4407 { 4408 uint32_t tmp = mask & data->dpm_level_enable_mask.pcie_dpm_enable_mask; 4409 4410 if (!data->pcie_dpm_key_disabled) { 4411 if (fls(tmp) != ffs(tmp)) 4412 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PCIeDPM_UnForceLevel); 4413 else 4414 smum_send_msg_to_smc_with_parameter(hwmgr, 4415 PPSMC_MSG_PCIeDPM_ForceLevel, 4416 fls(tmp) - 1); 4417 } 4418 break; 4419 } 4420 default: 4421 break; 4422 } 4423 4424 return 0; 4425 } 4426 4427 static int smu7_print_clock_levels(struct pp_hwmgr *hwmgr, 4428 enum pp_clock_type type, char *buf) 4429 { 4430 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4431 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4432 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4433 struct smu7_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); 4434 struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table); 4435 struct phm_odn_clock_levels *odn_sclk_table = &(odn_table->odn_core_clock_dpm_levels); 4436 struct phm_odn_clock_levels *odn_mclk_table = &(odn_table->odn_memory_clock_dpm_levels); 4437 int i, now, size = 0; 4438 uint32_t clock, pcie_speed; 4439 4440 switch (type) { 4441 case PP_SCLK: 4442 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetSclkFrequency); 4443 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 4444 4445 for (i = 0; i < sclk_table->count; i++) { 4446 if (clock > sclk_table->dpm_levels[i].value) 4447 continue; 4448 break; 4449 } 4450 now = i; 4451 4452 for (i = 0; i < sclk_table->count; i++) 4453 size += sprintf(buf + size, "%d: %uMhz %s\n", 4454 i, sclk_table->dpm_levels[i].value / 100, 4455 (i == now) ? "*" : ""); 4456 break; 4457 case PP_MCLK: 4458 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_API_GetMclkFrequency); 4459 clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); 4460 4461 for (i = 0; i < mclk_table->count; i++) { 4462 if (clock > mclk_table->dpm_levels[i].value) 4463 continue; 4464 break; 4465 } 4466 now = i; 4467 4468 for (i = 0; i < mclk_table->count; i++) 4469 size += sprintf(buf + size, "%d: %uMhz %s\n", 4470 i, mclk_table->dpm_levels[i].value / 100, 4471 (i == now) ? "*" : ""); 4472 break; 4473 case PP_PCIE: 4474 pcie_speed = smu7_get_current_pcie_speed(hwmgr); 4475 for (i = 0; i < pcie_table->count; i++) { 4476 if (pcie_speed != pcie_table->dpm_levels[i].value) 4477 continue; 4478 break; 4479 } 4480 now = i; 4481 4482 for (i = 0; i < pcie_table->count; i++) 4483 size += sprintf(buf + size, "%d: %s %s\n", i, 4484 (pcie_table->dpm_levels[i].value == 0) ? "2.5GT/s, x8" : 4485 (pcie_table->dpm_levels[i].value == 1) ? "5.0GT/s, x16" : 4486 (pcie_table->dpm_levels[i].value == 2) ? "8.0GT/s, x16" : "", 4487 (i == now) ? "*" : ""); 4488 break; 4489 case OD_SCLK: 4490 if (hwmgr->od_enabled) { 4491 size = sprintf(buf, "%s:\n", "OD_SCLK"); 4492 for (i = 0; i < odn_sclk_table->num_of_pl; i++) 4493 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 4494 i, odn_sclk_table->entries[i].clock/100, 4495 odn_sclk_table->entries[i].vddc); 4496 } 4497 break; 4498 case OD_MCLK: 4499 if (hwmgr->od_enabled) { 4500 size = sprintf(buf, "%s:\n", "OD_MCLK"); 4501 for (i = 0; i < odn_mclk_table->num_of_pl; i++) 4502 size += sprintf(buf + size, "%d: %10uMHz %10umV\n", 4503 i, odn_mclk_table->entries[i].clock/100, 4504 odn_mclk_table->entries[i].vddc); 4505 } 4506 break; 4507 case OD_RANGE: 4508 if (hwmgr->od_enabled) { 4509 size = sprintf(buf, "%s:\n", "OD_RANGE"); 4510 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n", 4511 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 4512 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4513 size += sprintf(buf + size, "MCLK: %7uMHz %10uMHz\n", 4514 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 4515 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4516 size += sprintf(buf + size, "VDDC: %7umV %11umV\n", 4517 data->odn_dpm_table.min_vddc, 4518 data->odn_dpm_table.max_vddc); 4519 } 4520 break; 4521 default: 4522 break; 4523 } 4524 return size; 4525 } 4526 4527 static void smu7_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 4528 { 4529 switch (mode) { 4530 case AMD_FAN_CTRL_NONE: 4531 smu7_fan_ctrl_set_fan_speed_percent(hwmgr, 100); 4532 break; 4533 case AMD_FAN_CTRL_MANUAL: 4534 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 4535 PHM_PlatformCaps_MicrocodeFanControl)) 4536 smu7_fan_ctrl_stop_smc_fan_control(hwmgr); 4537 break; 4538 case AMD_FAN_CTRL_AUTO: 4539 if (!smu7_fan_ctrl_set_static_mode(hwmgr, mode)) 4540 smu7_fan_ctrl_start_smc_fan_control(hwmgr); 4541 break; 4542 default: 4543 break; 4544 } 4545 } 4546 4547 static uint32_t smu7_get_fan_control_mode(struct pp_hwmgr *hwmgr) 4548 { 4549 return hwmgr->fan_ctrl_enabled ? AMD_FAN_CTRL_AUTO : AMD_FAN_CTRL_MANUAL; 4550 } 4551 4552 static int smu7_get_sclk_od(struct pp_hwmgr *hwmgr) 4553 { 4554 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4555 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4556 struct smu7_single_dpm_table *golden_sclk_table = 4557 &(data->golden_dpm_table.sclk_table); 4558 int value; 4559 4560 value = (sclk_table->dpm_levels[sclk_table->count - 1].value - 4561 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value) * 4562 100 / 4563 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 4564 4565 return value; 4566 } 4567 4568 static int smu7_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 4569 { 4570 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4571 struct smu7_single_dpm_table *golden_sclk_table = 4572 &(data->golden_dpm_table.sclk_table); 4573 struct pp_power_state *ps; 4574 struct smu7_power_state *smu7_ps; 4575 4576 if (value > 20) 4577 value = 20; 4578 4579 ps = hwmgr->request_ps; 4580 4581 if (ps == NULL) 4582 return -EINVAL; 4583 4584 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 4585 4586 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].engine_clock = 4587 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value * 4588 value / 100 + 4589 golden_sclk_table->dpm_levels[golden_sclk_table->count - 1].value; 4590 4591 return 0; 4592 } 4593 4594 static int smu7_get_mclk_od(struct pp_hwmgr *hwmgr) 4595 { 4596 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4597 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4598 struct smu7_single_dpm_table *golden_mclk_table = 4599 &(data->golden_dpm_table.mclk_table); 4600 int value; 4601 4602 value = (mclk_table->dpm_levels[mclk_table->count - 1].value - 4603 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value) * 4604 100 / 4605 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 4606 4607 return value; 4608 } 4609 4610 static int smu7_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value) 4611 { 4612 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4613 struct smu7_single_dpm_table *golden_mclk_table = 4614 &(data->golden_dpm_table.mclk_table); 4615 struct pp_power_state *ps; 4616 struct smu7_power_state *smu7_ps; 4617 4618 if (value > 20) 4619 value = 20; 4620 4621 ps = hwmgr->request_ps; 4622 4623 if (ps == NULL) 4624 return -EINVAL; 4625 4626 smu7_ps = cast_phw_smu7_power_state(&ps->hardware); 4627 4628 smu7_ps->performance_levels[smu7_ps->performance_level_count - 1].memory_clock = 4629 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value * 4630 value / 100 + 4631 golden_mclk_table->dpm_levels[golden_mclk_table->count - 1].value; 4632 4633 return 0; 4634 } 4635 4636 4637 static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 4638 { 4639 struct phm_ppt_v1_information *table_info = 4640 (struct phm_ppt_v1_information *)hwmgr->pptable; 4641 struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL; 4642 struct phm_clock_voltage_dependency_table *sclk_table; 4643 int i; 4644 4645 if (hwmgr->pp_table_version == PP_TABLE_V1) { 4646 if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL) 4647 return -EINVAL; 4648 dep_sclk_table = table_info->vdd_dep_on_sclk; 4649 for (i = 0; i < dep_sclk_table->count; i++) 4650 clocks->clock[i] = dep_sclk_table->entries[i].clk * 10; 4651 clocks->count = dep_sclk_table->count; 4652 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4653 sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk; 4654 for (i = 0; i < sclk_table->count; i++) 4655 clocks->clock[i] = sclk_table->entries[i].clk * 10; 4656 clocks->count = sclk_table->count; 4657 } 4658 4659 return 0; 4660 } 4661 4662 static uint32_t smu7_get_mem_latency(struct pp_hwmgr *hwmgr, uint32_t clk) 4663 { 4664 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4665 4666 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) 4667 return data->mem_latency_high; 4668 else if (clk >= MEM_FREQ_HIGH_LATENCY) 4669 return data->mem_latency_low; 4670 else 4671 return MEM_LATENCY_ERR; 4672 } 4673 4674 static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 4675 { 4676 struct phm_ppt_v1_information *table_info = 4677 (struct phm_ppt_v1_information *)hwmgr->pptable; 4678 struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table; 4679 int i; 4680 struct phm_clock_voltage_dependency_table *mclk_table; 4681 4682 if (hwmgr->pp_table_version == PP_TABLE_V1) { 4683 if (table_info == NULL) 4684 return -EINVAL; 4685 dep_mclk_table = table_info->vdd_dep_on_mclk; 4686 for (i = 0; i < dep_mclk_table->count; i++) { 4687 clocks->clock[i] = dep_mclk_table->entries[i].clk * 10; 4688 clocks->latency[i] = smu7_get_mem_latency(hwmgr, 4689 dep_mclk_table->entries[i].clk); 4690 } 4691 clocks->count = dep_mclk_table->count; 4692 } else if (hwmgr->pp_table_version == PP_TABLE_V0) { 4693 mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk; 4694 for (i = 0; i < mclk_table->count; i++) 4695 clocks->clock[i] = mclk_table->entries[i].clk * 10; 4696 clocks->count = mclk_table->count; 4697 } 4698 return 0; 4699 } 4700 4701 static int smu7_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, 4702 struct amd_pp_clocks *clocks) 4703 { 4704 switch (type) { 4705 case amd_pp_sys_clock: 4706 smu7_get_sclks(hwmgr, clocks); 4707 break; 4708 case amd_pp_mem_clock: 4709 smu7_get_mclks(hwmgr, clocks); 4710 break; 4711 default: 4712 return -EINVAL; 4713 } 4714 4715 return 0; 4716 } 4717 4718 static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr, 4719 uint32_t virtual_addr_low, 4720 uint32_t virtual_addr_hi, 4721 uint32_t mc_addr_low, 4722 uint32_t mc_addr_hi, 4723 uint32_t size) 4724 { 4725 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4726 4727 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4728 data->soft_regs_start + 4729 smum_get_offsetof(hwmgr, 4730 SMU_SoftRegisters, DRAM_LOG_ADDR_H), 4731 mc_addr_hi); 4732 4733 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4734 data->soft_regs_start + 4735 smum_get_offsetof(hwmgr, 4736 SMU_SoftRegisters, DRAM_LOG_ADDR_L), 4737 mc_addr_low); 4738 4739 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4740 data->soft_regs_start + 4741 smum_get_offsetof(hwmgr, 4742 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_H), 4743 virtual_addr_hi); 4744 4745 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4746 data->soft_regs_start + 4747 smum_get_offsetof(hwmgr, 4748 SMU_SoftRegisters, DRAM_LOG_PHY_ADDR_L), 4749 virtual_addr_low); 4750 4751 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, 4752 data->soft_regs_start + 4753 smum_get_offsetof(hwmgr, 4754 SMU_SoftRegisters, DRAM_LOG_BUFF_SIZE), 4755 size); 4756 return 0; 4757 } 4758 4759 static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr, 4760 struct amd_pp_simple_clock_info *clocks) 4761 { 4762 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4763 struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); 4764 struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); 4765 4766 if (clocks == NULL) 4767 return -EINVAL; 4768 4769 clocks->memory_max_clock = mclk_table->count > 1 ? 4770 mclk_table->dpm_levels[mclk_table->count-1].value : 4771 mclk_table->dpm_levels[0].value; 4772 clocks->engine_max_clock = sclk_table->count > 1 ? 4773 sclk_table->dpm_levels[sclk_table->count-1].value : 4774 sclk_table->dpm_levels[0].value; 4775 return 0; 4776 } 4777 4778 static int smu7_get_thermal_temperature_range(struct pp_hwmgr *hwmgr, 4779 struct PP_TemperatureRange *thermal_data) 4780 { 4781 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4782 struct phm_ppt_v1_information *table_info = 4783 (struct phm_ppt_v1_information *)hwmgr->pptable; 4784 4785 memcpy(thermal_data, &SMU7ThermalPolicy[0], sizeof(struct PP_TemperatureRange)); 4786 4787 if (hwmgr->pp_table_version == PP_TABLE_V1) 4788 thermal_data->max = table_info->cac_dtp_table->usSoftwareShutdownTemp * 4789 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4790 else if (hwmgr->pp_table_version == PP_TABLE_V0) 4791 thermal_data->max = data->thermal_temp_setting.temperature_shutdown * 4792 PP_TEMPERATURE_UNITS_PER_CENTIGRADES; 4793 4794 return 0; 4795 } 4796 4797 static bool smu7_check_clk_voltage_valid(struct pp_hwmgr *hwmgr, 4798 enum PP_OD_DPM_TABLE_COMMAND type, 4799 uint32_t clk, 4800 uint32_t voltage) 4801 { 4802 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4803 4804 if (voltage < data->odn_dpm_table.min_vddc || voltage > data->odn_dpm_table.max_vddc) { 4805 pr_info("OD voltage is out of range [%d - %d] mV\n", 4806 data->odn_dpm_table.min_vddc, 4807 data->odn_dpm_table.max_vddc); 4808 return false; 4809 } 4810 4811 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) { 4812 if (data->golden_dpm_table.sclk_table.dpm_levels[0].value > clk || 4813 hwmgr->platform_descriptor.overdriveLimit.engineClock < clk) { 4814 pr_info("OD engine clock is out of range [%d - %d] MHz\n", 4815 data->golden_dpm_table.sclk_table.dpm_levels[0].value/100, 4816 hwmgr->platform_descriptor.overdriveLimit.engineClock/100); 4817 return false; 4818 } 4819 } else if (type == PP_OD_EDIT_MCLK_VDDC_TABLE) { 4820 if (data->golden_dpm_table.mclk_table.dpm_levels[0].value > clk || 4821 hwmgr->platform_descriptor.overdriveLimit.memoryClock < clk) { 4822 pr_info("OD memory clock is out of range [%d - %d] MHz\n", 4823 data->golden_dpm_table.mclk_table.dpm_levels[0].value/100, 4824 hwmgr->platform_descriptor.overdriveLimit.memoryClock/100); 4825 return false; 4826 } 4827 } else { 4828 return false; 4829 } 4830 4831 return true; 4832 } 4833 4834 static int smu7_odn_edit_dpm_table(struct pp_hwmgr *hwmgr, 4835 enum PP_OD_DPM_TABLE_COMMAND type, 4836 long *input, uint32_t size) 4837 { 4838 uint32_t i; 4839 struct phm_odn_clock_levels *podn_dpm_table_in_backend = NULL; 4840 struct smu7_odn_clock_voltage_dependency_table *podn_vdd_dep_in_backend = NULL; 4841 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4842 4843 uint32_t input_clk; 4844 uint32_t input_vol; 4845 uint32_t input_level; 4846 4847 PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage", 4848 return -EINVAL); 4849 4850 if (!hwmgr->od_enabled) { 4851 pr_info("OverDrive feature not enabled\n"); 4852 return -EINVAL; 4853 } 4854 4855 if (PP_OD_EDIT_SCLK_VDDC_TABLE == type) { 4856 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_core_clock_dpm_levels; 4857 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_sclk; 4858 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 4859 "Failed to get ODN SCLK and Voltage tables", 4860 return -EINVAL); 4861 } else if (PP_OD_EDIT_MCLK_VDDC_TABLE == type) { 4862 podn_dpm_table_in_backend = &data->odn_dpm_table.odn_memory_clock_dpm_levels; 4863 podn_vdd_dep_in_backend = &data->odn_dpm_table.vdd_dependency_on_mclk; 4864 4865 PP_ASSERT_WITH_CODE((podn_dpm_table_in_backend && podn_vdd_dep_in_backend), 4866 "Failed to get ODN MCLK and Voltage tables", 4867 return -EINVAL); 4868 } else if (PP_OD_RESTORE_DEFAULT_TABLE == type) { 4869 smu7_odn_initial_default_setting(hwmgr); 4870 return 0; 4871 } else if (PP_OD_COMMIT_DPM_TABLE == type) { 4872 smu7_check_dpm_table_updated(hwmgr); 4873 return 0; 4874 } else { 4875 return -EINVAL; 4876 } 4877 4878 for (i = 0; i < size; i += 3) { 4879 if (i + 3 > size || input[i] >= podn_dpm_table_in_backend->num_of_pl) { 4880 pr_info("invalid clock voltage input \n"); 4881 return 0; 4882 } 4883 input_level = input[i]; 4884 input_clk = input[i+1] * 100; 4885 input_vol = input[i+2]; 4886 4887 if (smu7_check_clk_voltage_valid(hwmgr, type, input_clk, input_vol)) { 4888 podn_dpm_table_in_backend->entries[input_level].clock = input_clk; 4889 podn_vdd_dep_in_backend->entries[input_level].clk = input_clk; 4890 podn_dpm_table_in_backend->entries[input_level].vddc = input_vol; 4891 podn_vdd_dep_in_backend->entries[input_level].vddc = input_vol; 4892 } else { 4893 return -EINVAL; 4894 } 4895 } 4896 4897 return 0; 4898 } 4899 4900 static int smu7_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf) 4901 { 4902 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4903 uint32_t i, size = 0; 4904 uint32_t len; 4905 4906 static const char *profile_name[6] = {"3D_FULL_SCREEN", 4907 "POWER_SAVING", 4908 "VIDEO", 4909 "VR", 4910 "COMPUTE", 4911 "CUSTOM"}; 4912 4913 static const char *title[8] = {"NUM", 4914 "MODE_NAME", 4915 "SCLK_UP_HYST", 4916 "SCLK_DOWN_HYST", 4917 "SCLK_ACTIVE_LEVEL", 4918 "MCLK_UP_HYST", 4919 "MCLK_DOWN_HYST", 4920 "MCLK_ACTIVE_LEVEL"}; 4921 4922 if (!buf) 4923 return -EINVAL; 4924 4925 size += sprintf(buf + size, "%s %16s %16s %16s %16s %16s %16s %16s\n", 4926 title[0], title[1], title[2], title[3], 4927 title[4], title[5], title[6], title[7]); 4928 4929 len = sizeof(smu7_profiling) / sizeof(struct profile_mode_setting); 4930 4931 for (i = 0; i < len; i++) { 4932 if (i == hwmgr->power_profile_mode) { 4933 size += sprintf(buf + size, "%3d %14s %s: %8d %16d %16d %16d %16d %16d\n", 4934 i, profile_name[i], "*", 4935 data->current_profile_setting.sclk_up_hyst, 4936 data->current_profile_setting.sclk_down_hyst, 4937 data->current_profile_setting.sclk_activity, 4938 data->current_profile_setting.mclk_up_hyst, 4939 data->current_profile_setting.mclk_down_hyst, 4940 data->current_profile_setting.mclk_activity); 4941 continue; 4942 } 4943 if (smu7_profiling[i].bupdate_sclk) 4944 size += sprintf(buf + size, "%3d %16s: %8d %16d %16d ", 4945 i, profile_name[i], smu7_profiling[i].sclk_up_hyst, 4946 smu7_profiling[i].sclk_down_hyst, 4947 smu7_profiling[i].sclk_activity); 4948 else 4949 size += sprintf(buf + size, "%3d %16s: %8s %16s %16s ", 4950 i, profile_name[i], "-", "-", "-"); 4951 4952 if (smu7_profiling[i].bupdate_mclk) 4953 size += sprintf(buf + size, "%16d %16d %16d\n", 4954 smu7_profiling[i].mclk_up_hyst, 4955 smu7_profiling[i].mclk_down_hyst, 4956 smu7_profiling[i].mclk_activity); 4957 else 4958 size += sprintf(buf + size, "%16s %16s %16s\n", 4959 "-", "-", "-"); 4960 } 4961 4962 return size; 4963 } 4964 4965 static void smu7_patch_compute_profile_mode(struct pp_hwmgr *hwmgr, 4966 enum PP_SMC_POWER_PROFILE requst) 4967 { 4968 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4969 uint32_t tmp, level; 4970 4971 if (requst == PP_SMC_POWER_PROFILE_COMPUTE) { 4972 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask) { 4973 level = 0; 4974 tmp = data->dpm_level_enable_mask.sclk_dpm_enable_mask; 4975 while (tmp >>= 1) 4976 level++; 4977 if (level > 0) 4978 smu7_force_clock_level(hwmgr, PP_SCLK, 3 << (level-1)); 4979 } 4980 } else if (hwmgr->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) { 4981 smu7_force_clock_level(hwmgr, PP_SCLK, data->dpm_level_enable_mask.sclk_dpm_enable_mask); 4982 } 4983 } 4984 4985 static int smu7_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size) 4986 { 4987 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend); 4988 struct profile_mode_setting tmp; 4989 enum PP_SMC_POWER_PROFILE mode; 4990 4991 if (input == NULL) 4992 return -EINVAL; 4993 4994 mode = input[size]; 4995 switch (mode) { 4996 case PP_SMC_POWER_PROFILE_CUSTOM: 4997 if (size < 8) 4998 return -EINVAL; 4999 5000 tmp.bupdate_sclk = input[0]; 5001 tmp.sclk_up_hyst = input[1]; 5002 tmp.sclk_down_hyst = input[2]; 5003 tmp.sclk_activity = input[3]; 5004 tmp.bupdate_mclk = input[4]; 5005 tmp.mclk_up_hyst = input[5]; 5006 tmp.mclk_down_hyst = input[6]; 5007 tmp.mclk_activity = input[7]; 5008 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5009 memcpy(&data->current_profile_setting, &tmp, sizeof(struct profile_mode_setting)); 5010 hwmgr->power_profile_mode = mode; 5011 } 5012 break; 5013 case PP_SMC_POWER_PROFILE_FULLSCREEN3D: 5014 case PP_SMC_POWER_PROFILE_POWERSAVING: 5015 case PP_SMC_POWER_PROFILE_VIDEO: 5016 case PP_SMC_POWER_PROFILE_VR: 5017 case PP_SMC_POWER_PROFILE_COMPUTE: 5018 if (mode == hwmgr->power_profile_mode) 5019 return 0; 5020 5021 memcpy(&tmp, &smu7_profiling[mode], sizeof(struct profile_mode_setting)); 5022 if (!smum_update_dpm_settings(hwmgr, &tmp)) { 5023 if (tmp.bupdate_sclk) { 5024 data->current_profile_setting.bupdate_sclk = tmp.bupdate_sclk; 5025 data->current_profile_setting.sclk_up_hyst = tmp.sclk_up_hyst; 5026 data->current_profile_setting.sclk_down_hyst = tmp.sclk_down_hyst; 5027 data->current_profile_setting.sclk_activity = tmp.sclk_activity; 5028 } 5029 if (tmp.bupdate_mclk) { 5030 data->current_profile_setting.bupdate_mclk = tmp.bupdate_mclk; 5031 data->current_profile_setting.mclk_up_hyst = tmp.mclk_up_hyst; 5032 data->current_profile_setting.mclk_down_hyst = tmp.mclk_down_hyst; 5033 data->current_profile_setting.mclk_activity = tmp.mclk_activity; 5034 } 5035 smu7_patch_compute_profile_mode(hwmgr, mode); 5036 hwmgr->power_profile_mode = mode; 5037 } 5038 break; 5039 default: 5040 return -EINVAL; 5041 } 5042 5043 return 0; 5044 } 5045 5046 static const struct pp_hwmgr_func smu7_hwmgr_funcs = { 5047 .backend_init = &smu7_hwmgr_backend_init, 5048 .backend_fini = &smu7_hwmgr_backend_fini, 5049 .asic_setup = &smu7_setup_asic_task, 5050 .dynamic_state_management_enable = &smu7_enable_dpm_tasks, 5051 .apply_state_adjust_rules = smu7_apply_state_adjust_rules, 5052 .force_dpm_level = &smu7_force_dpm_level, 5053 .power_state_set = smu7_set_power_state_tasks, 5054 .get_power_state_size = smu7_get_power_state_size, 5055 .get_mclk = smu7_dpm_get_mclk, 5056 .get_sclk = smu7_dpm_get_sclk, 5057 .patch_boot_state = smu7_dpm_patch_boot_state, 5058 .get_pp_table_entry = smu7_get_pp_table_entry, 5059 .get_num_of_pp_table_entries = smu7_get_number_of_powerplay_table_entries, 5060 .powerdown_uvd = smu7_powerdown_uvd, 5061 .powergate_uvd = smu7_powergate_uvd, 5062 .powergate_vce = smu7_powergate_vce, 5063 .disable_clock_power_gating = smu7_disable_clock_power_gating, 5064 .update_clock_gatings = smu7_update_clock_gatings, 5065 .notify_smc_display_config_after_ps_adjustment = smu7_notify_smc_display_config_after_ps_adjustment, 5066 .display_config_changed = smu7_display_configuration_changed_task, 5067 .set_max_fan_pwm_output = smu7_set_max_fan_pwm_output, 5068 .set_max_fan_rpm_output = smu7_set_max_fan_rpm_output, 5069 .stop_thermal_controller = smu7_thermal_stop_thermal_controller, 5070 .get_fan_speed_info = smu7_fan_ctrl_get_fan_speed_info, 5071 .get_fan_speed_percent = smu7_fan_ctrl_get_fan_speed_percent, 5072 .set_fan_speed_percent = smu7_fan_ctrl_set_fan_speed_percent, 5073 .reset_fan_speed_to_default = smu7_fan_ctrl_reset_fan_speed_to_default, 5074 .get_fan_speed_rpm = smu7_fan_ctrl_get_fan_speed_rpm, 5075 .set_fan_speed_rpm = smu7_fan_ctrl_set_fan_speed_rpm, 5076 .uninitialize_thermal_controller = smu7_thermal_ctrl_uninitialize_thermal_controller, 5077 .register_irq_handlers = smu7_register_irq_handlers, 5078 .check_smc_update_required_for_display_configuration = smu7_check_smc_update_required_for_display_configuration, 5079 .check_states_equal = smu7_check_states_equal, 5080 .set_fan_control_mode = smu7_set_fan_control_mode, 5081 .get_fan_control_mode = smu7_get_fan_control_mode, 5082 .force_clock_level = smu7_force_clock_level, 5083 .print_clock_levels = smu7_print_clock_levels, 5084 .powergate_gfx = smu7_powergate_gfx, 5085 .get_sclk_od = smu7_get_sclk_od, 5086 .set_sclk_od = smu7_set_sclk_od, 5087 .get_mclk_od = smu7_get_mclk_od, 5088 .set_mclk_od = smu7_set_mclk_od, 5089 .get_clock_by_type = smu7_get_clock_by_type, 5090 .read_sensor = smu7_read_sensor, 5091 .dynamic_state_management_disable = smu7_disable_dpm_tasks, 5092 .avfs_control = smu7_avfs_control, 5093 .disable_smc_firmware_ctf = smu7_thermal_disable_alert, 5094 .start_thermal_controller = smu7_start_thermal_controller, 5095 .notify_cac_buffer_info = smu7_notify_cac_buffer_info, 5096 .get_max_high_clocks = smu7_get_max_high_clocks, 5097 .get_thermal_temperature_range = smu7_get_thermal_temperature_range, 5098 .odn_edit_dpm_table = smu7_odn_edit_dpm_table, 5099 .set_power_limit = smu7_set_power_limit, 5100 .get_power_profile_mode = smu7_get_power_profile_mode, 5101 .set_power_profile_mode = smu7_set_power_profile_mode, 5102 }; 5103 5104 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 5105 uint32_t clock_insr) 5106 { 5107 uint8_t i; 5108 uint32_t temp; 5109 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK); 5110 5111 PP_ASSERT_WITH_CODE((clock >= min), "Engine clock can't satisfy stutter requirement!", return 0); 5112 for (i = SMU7_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { 5113 temp = clock >> i; 5114 5115 if (temp >= min || i == 0) 5116 break; 5117 } 5118 return i; 5119 } 5120 5121 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr); 5122 int smu7_init_function_pointers(struct pp_hwmgr *hwmgr) 5123 { 5124 int ret = 0; 5125 5126 hwmgr->hwmgr_func = &smu7_hwmgr_funcs; 5127 if (hwmgr->pp_table_version == PP_TABLE_V0) 5128 hwmgr->pptable_func = &pptable_funcs; 5129 else if (hwmgr->pp_table_version == PP_TABLE_V1) 5130 hwmgr->pptable_func = &pptable_v1_0_funcs; 5131 5132 return ret; 5133 } 5134