1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef _SMU7_HWMGR_H 25*b843c749SSergey Zigachev #define _SMU7_HWMGR_H 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "hwmgr.h" 28*b843c749SSergey Zigachev #include "ppatomctrl.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define SMU7_MAX_HARDWARE_POWERLEVELS 2 31*b843c749SSergey Zigachev 32*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROL_NONE 0x0 33*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 34*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 35*b843c749SSergey Zigachev #define SMU7_VOLTAGE_CONTROL_MERGED 0x3 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev enum gpu_pt_config_reg_type { 38*b843c749SSergey Zigachev GPU_CONFIGREG_MMR = 0, 39*b843c749SSergey Zigachev GPU_CONFIGREG_SMC_IND, 40*b843c749SSergey Zigachev GPU_CONFIGREG_DIDT_IND, 41*b843c749SSergey Zigachev GPU_CONFIGREG_GC_CAC_IND, 42*b843c749SSergey Zigachev GPU_CONFIGREG_CACHE, 43*b843c749SSergey Zigachev GPU_CONFIGREG_MAX 44*b843c749SSergey Zigachev }; 45*b843c749SSergey Zigachev 46*b843c749SSergey Zigachev struct gpu_pt_config_reg { 47*b843c749SSergey Zigachev uint32_t offset; 48*b843c749SSergey Zigachev uint32_t mask; 49*b843c749SSergey Zigachev uint32_t shift; 50*b843c749SSergey Zigachev uint32_t value; 51*b843c749SSergey Zigachev enum gpu_pt_config_reg_type type; 52*b843c749SSergey Zigachev }; 53*b843c749SSergey Zigachev 54*b843c749SSergey Zigachev struct smu7_performance_level { 55*b843c749SSergey Zigachev uint32_t memory_clock; 56*b843c749SSergey Zigachev uint32_t engine_clock; 57*b843c749SSergey Zigachev uint16_t pcie_gen; 58*b843c749SSergey Zigachev uint16_t pcie_lane; 59*b843c749SSergey Zigachev }; 60*b843c749SSergey Zigachev 61*b843c749SSergey Zigachev struct smu7_thermal_temperature_setting { 62*b843c749SSergey Zigachev long temperature_low; 63*b843c749SSergey Zigachev long temperature_high; 64*b843c749SSergey Zigachev long temperature_shutdown; 65*b843c749SSergey Zigachev }; 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev struct smu7_uvd_clocks { 68*b843c749SSergey Zigachev uint32_t vclk; 69*b843c749SSergey Zigachev uint32_t dclk; 70*b843c749SSergey Zigachev }; 71*b843c749SSergey Zigachev 72*b843c749SSergey Zigachev struct smu7_vce_clocks { 73*b843c749SSergey Zigachev uint32_t evclk; 74*b843c749SSergey Zigachev uint32_t ecclk; 75*b843c749SSergey Zigachev }; 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev struct smu7_power_state { 78*b843c749SSergey Zigachev uint32_t magic; 79*b843c749SSergey Zigachev struct smu7_uvd_clocks uvd_clks; 80*b843c749SSergey Zigachev struct smu7_vce_clocks vce_clks; 81*b843c749SSergey Zigachev uint32_t sam_clk; 82*b843c749SSergey Zigachev uint16_t performance_level_count; 83*b843c749SSergey Zigachev bool dc_compatible; 84*b843c749SSergey Zigachev uint32_t sclk_threshold; 85*b843c749SSergey Zigachev struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; 86*b843c749SSergey Zigachev }; 87*b843c749SSergey Zigachev 88*b843c749SSergey Zigachev struct smu7_dpm_level { 89*b843c749SSergey Zigachev bool enabled; 90*b843c749SSergey Zigachev uint32_t value; 91*b843c749SSergey Zigachev uint32_t param1; 92*b843c749SSergey Zigachev }; 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 95*b843c749SSergey Zigachev #define MAX_REGULAR_DPM_NUMBER 8 96*b843c749SSergey Zigachev #define SMU7_MINIMUM_ENGINE_CLOCK 2500 97*b843c749SSergey Zigachev 98*b843c749SSergey Zigachev struct smu7_single_dpm_table { 99*b843c749SSergey Zigachev uint32_t count; 100*b843c749SSergey Zigachev struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 101*b843c749SSergey Zigachev }; 102*b843c749SSergey Zigachev 103*b843c749SSergey Zigachev struct smu7_dpm_table { 104*b843c749SSergey Zigachev struct smu7_single_dpm_table sclk_table; 105*b843c749SSergey Zigachev struct smu7_single_dpm_table mclk_table; 106*b843c749SSergey Zigachev struct smu7_single_dpm_table pcie_speed_table; 107*b843c749SSergey Zigachev struct smu7_single_dpm_table vddc_table; 108*b843c749SSergey Zigachev struct smu7_single_dpm_table vddci_table; 109*b843c749SSergey Zigachev struct smu7_single_dpm_table mvdd_table; 110*b843c749SSergey Zigachev }; 111*b843c749SSergey Zigachev 112*b843c749SSergey Zigachev struct smu7_clock_registers { 113*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL; 114*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_2; 115*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_3; 116*b843c749SSergey Zigachev uint32_t vCG_SPLL_FUNC_CNTL_4; 117*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM; 118*b843c749SSergey Zigachev uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 119*b843c749SSergey Zigachev uint32_t vDLL_CNTL; 120*b843c749SSergey Zigachev uint32_t vMCLK_PWRMGT_CNTL; 121*b843c749SSergey Zigachev uint32_t vMPLL_AD_FUNC_CNTL; 122*b843c749SSergey Zigachev uint32_t vMPLL_DQ_FUNC_CNTL; 123*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL; 124*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_1; 125*b843c749SSergey Zigachev uint32_t vMPLL_FUNC_CNTL_2; 126*b843c749SSergey Zigachev uint32_t vMPLL_SS1; 127*b843c749SSergey Zigachev uint32_t vMPLL_SS2; 128*b843c749SSergey Zigachev }; 129*b843c749SSergey Zigachev 130*b843c749SSergey Zigachev #define DISABLE_MC_LOADMICROCODE 1 131*b843c749SSergey Zigachev #define DISABLE_MC_CFGPROGRAMMING 2 132*b843c749SSergey Zigachev 133*b843c749SSergey Zigachev struct smu7_voltage_smio_registers { 134*b843c749SSergey Zigachev uint32_t vS0_VID_LOWER_SMIO_CNTL; 135*b843c749SSergey Zigachev }; 136*b843c749SSergey Zigachev 137*b843c749SSergey Zigachev #define SMU7_MAX_LEAKAGE_COUNT 8 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev struct smu7_leakage_voltage { 140*b843c749SSergey Zigachev uint16_t count; 141*b843c749SSergey Zigachev uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; 142*b843c749SSergey Zigachev uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; 143*b843c749SSergey Zigachev }; 144*b843c749SSergey Zigachev 145*b843c749SSergey Zigachev struct smu7_vbios_boot_state { 146*b843c749SSergey Zigachev uint16_t mvdd_bootup_value; 147*b843c749SSergey Zigachev uint16_t vddc_bootup_value; 148*b843c749SSergey Zigachev uint16_t vddci_bootup_value; 149*b843c749SSergey Zigachev uint16_t vddgfx_bootup_value; 150*b843c749SSergey Zigachev uint32_t sclk_bootup_value; 151*b843c749SSergey Zigachev uint32_t mclk_bootup_value; 152*b843c749SSergey Zigachev uint16_t pcie_gen_bootup_value; 153*b843c749SSergey Zigachev uint16_t pcie_lane_bootup_value; 154*b843c749SSergey Zigachev }; 155*b843c749SSergey Zigachev 156*b843c749SSergey Zigachev struct smu7_display_timing { 157*b843c749SSergey Zigachev uint32_t min_clock_in_sr; 158*b843c749SSergey Zigachev uint32_t num_existing_displays; 159*b843c749SSergey Zigachev }; 160*b843c749SSergey Zigachev 161*b843c749SSergey Zigachev struct smu7_dpmlevel_enable_mask { 162*b843c749SSergey Zigachev uint32_t uvd_dpm_enable_mask; 163*b843c749SSergey Zigachev uint32_t vce_dpm_enable_mask; 164*b843c749SSergey Zigachev uint32_t acp_dpm_enable_mask; 165*b843c749SSergey Zigachev uint32_t samu_dpm_enable_mask; 166*b843c749SSergey Zigachev uint32_t sclk_dpm_enable_mask; 167*b843c749SSergey Zigachev uint32_t mclk_dpm_enable_mask; 168*b843c749SSergey Zigachev uint32_t pcie_dpm_enable_mask; 169*b843c749SSergey Zigachev }; 170*b843c749SSergey Zigachev 171*b843c749SSergey Zigachev struct smu7_pcie_perf_range { 172*b843c749SSergey Zigachev uint16_t max; 173*b843c749SSergey Zigachev uint16_t min; 174*b843c749SSergey Zigachev }; 175*b843c749SSergey Zigachev 176*b843c749SSergey Zigachev struct smu7_odn_clock_voltage_dependency_table { 177*b843c749SSergey Zigachev uint32_t count; 178*b843c749SSergey Zigachev phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 179*b843c749SSergey Zigachev }; 180*b843c749SSergey Zigachev 181*b843c749SSergey Zigachev struct smu7_odn_dpm_table { 182*b843c749SSergey Zigachev struct phm_odn_clock_levels odn_core_clock_dpm_levels; 183*b843c749SSergey Zigachev struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 184*b843c749SSergey Zigachev struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 185*b843c749SSergey Zigachev struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 186*b843c749SSergey Zigachev uint32_t odn_mclk_min_limit; 187*b843c749SSergey Zigachev uint32_t min_vddc; 188*b843c749SSergey Zigachev uint32_t max_vddc; 189*b843c749SSergey Zigachev }; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev struct profile_mode_setting { 192*b843c749SSergey Zigachev uint8_t bupdate_sclk; 193*b843c749SSergey Zigachev uint8_t sclk_up_hyst; 194*b843c749SSergey Zigachev uint8_t sclk_down_hyst; 195*b843c749SSergey Zigachev uint16_t sclk_activity; 196*b843c749SSergey Zigachev uint8_t bupdate_mclk; 197*b843c749SSergey Zigachev uint8_t mclk_up_hyst; 198*b843c749SSergey Zigachev uint8_t mclk_down_hyst; 199*b843c749SSergey Zigachev uint16_t mclk_activity; 200*b843c749SSergey Zigachev }; 201*b843c749SSergey Zigachev 202*b843c749SSergey Zigachev struct smu7_hwmgr { 203*b843c749SSergey Zigachev struct smu7_dpm_table dpm_table; 204*b843c749SSergey Zigachev struct smu7_dpm_table golden_dpm_table; 205*b843c749SSergey Zigachev struct smu7_odn_dpm_table odn_dpm_table; 206*b843c749SSergey Zigachev 207*b843c749SSergey Zigachev uint32_t voting_rights_clients[8]; 208*b843c749SSergey Zigachev uint32_t static_screen_threshold_unit; 209*b843c749SSergey Zigachev uint32_t static_screen_threshold; 210*b843c749SSergey Zigachev uint32_t voltage_control; 211*b843c749SSergey Zigachev uint32_t vdd_gfx_control; 212*b843c749SSergey Zigachev uint32_t vddc_vddgfx_delta; 213*b843c749SSergey Zigachev uint32_t active_auto_throttle_sources; 214*b843c749SSergey Zigachev 215*b843c749SSergey Zigachev struct smu7_clock_registers clock_registers; 216*b843c749SSergey Zigachev 217*b843c749SSergey Zigachev bool is_memory_gddr5; 218*b843c749SSergey Zigachev uint16_t acpi_vddc; 219*b843c749SSergey Zigachev bool pspp_notify_required; 220*b843c749SSergey Zigachev uint16_t force_pcie_gen; 221*b843c749SSergey Zigachev uint16_t acpi_pcie_gen; 222*b843c749SSergey Zigachev uint32_t pcie_gen_cap; 223*b843c749SSergey Zigachev uint32_t pcie_lane_cap; 224*b843c749SSergey Zigachev uint32_t pcie_spc_cap; 225*b843c749SSergey Zigachev struct smu7_leakage_voltage vddc_leakage; 226*b843c749SSergey Zigachev struct smu7_leakage_voltage vddci_leakage; 227*b843c749SSergey Zigachev struct smu7_leakage_voltage vddcgfx_leakage; 228*b843c749SSergey Zigachev 229*b843c749SSergey Zigachev uint32_t mvdd_control; 230*b843c749SSergey Zigachev uint32_t vddc_mask_low; 231*b843c749SSergey Zigachev uint32_t mvdd_mask_low; 232*b843c749SSergey Zigachev uint16_t max_vddc_in_pptable; 233*b843c749SSergey Zigachev uint16_t min_vddc_in_pptable; 234*b843c749SSergey Zigachev uint16_t max_vddci_in_pptable; 235*b843c749SSergey Zigachev uint16_t min_vddci_in_pptable; 236*b843c749SSergey Zigachev bool is_uvd_enabled; 237*b843c749SSergey Zigachev struct smu7_vbios_boot_state vbios_boot_state; 238*b843c749SSergey Zigachev 239*b843c749SSergey Zigachev bool pcie_performance_request; 240*b843c749SSergey Zigachev bool battery_state; 241*b843c749SSergey Zigachev bool is_tlu_enabled; 242*b843c749SSergey Zigachev bool disable_handshake; 243*b843c749SSergey Zigachev bool smc_voltage_control_enabled; 244*b843c749SSergey Zigachev bool vbi_time_out_support; 245*b843c749SSergey Zigachev 246*b843c749SSergey Zigachev uint32_t soft_regs_start; 247*b843c749SSergey Zigachev /* ---- Stuff originally coming from Evergreen ---- */ 248*b843c749SSergey Zigachev uint32_t vddci_control; 249*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table vddc_voltage_table; 250*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table vddci_voltage_table; 251*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table mvdd_voltage_table; 252*b843c749SSergey Zigachev struct pp_atomctrl_voltage_table vddgfx_voltage_table; 253*b843c749SSergey Zigachev 254*b843c749SSergey Zigachev uint32_t mgcg_cgtt_local2; 255*b843c749SSergey Zigachev uint32_t mgcg_cgtt_local3; 256*b843c749SSergey Zigachev uint32_t gpio_debug; 257*b843c749SSergey Zigachev uint32_t mc_micro_code_feature; 258*b843c749SSergey Zigachev uint32_t highest_mclk; 259*b843c749SSergey Zigachev uint16_t acpi_vddci; 260*b843c749SSergey Zigachev uint8_t mvdd_high_index; 261*b843c749SSergey Zigachev uint8_t mvdd_low_index; 262*b843c749SSergey Zigachev bool dll_default_on; 263*b843c749SSergey Zigachev bool performance_request_registered; 264*b843c749SSergey Zigachev 265*b843c749SSergey Zigachev /* ---- Low Power Features ---- */ 266*b843c749SSergey Zigachev bool ulv_supported; 267*b843c749SSergey Zigachev 268*b843c749SSergey Zigachev /* ---- CAC Stuff ---- */ 269*b843c749SSergey Zigachev uint32_t cac_table_start; 270*b843c749SSergey Zigachev bool cac_configuration_required; 271*b843c749SSergey Zigachev bool driver_calculate_cac_leakage; 272*b843c749SSergey Zigachev bool cac_enabled; 273*b843c749SSergey Zigachev 274*b843c749SSergey Zigachev /* ---- DPM2 Parameters ---- */ 275*b843c749SSergey Zigachev uint32_t power_containment_features; 276*b843c749SSergey Zigachev bool enable_dte_feature; 277*b843c749SSergey Zigachev bool enable_tdc_limit_feature; 278*b843c749SSergey Zigachev bool enable_pkg_pwr_tracking_feature; 279*b843c749SSergey Zigachev bool disable_uvd_power_tune_feature; 280*b843c749SSergey Zigachev 281*b843c749SSergey Zigachev 282*b843c749SSergey Zigachev uint32_t dte_tj_offset; 283*b843c749SSergey Zigachev uint32_t fast_watermark_threshold; 284*b843c749SSergey Zigachev 285*b843c749SSergey Zigachev /* ---- Phase Shedding ---- */ 286*b843c749SSergey Zigachev uint8_t vddc_phase_shed_control; 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev /* ---- DI/DT ---- */ 289*b843c749SSergey Zigachev struct smu7_display_timing display_timing; 290*b843c749SSergey Zigachev 291*b843c749SSergey Zigachev /* ---- Thermal Temperature Setting ---- */ 292*b843c749SSergey Zigachev struct smu7_thermal_temperature_setting thermal_temp_setting; 293*b843c749SSergey Zigachev struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; 294*b843c749SSergey Zigachev uint32_t need_update_smu7_dpm_table; 295*b843c749SSergey Zigachev uint32_t sclk_dpm_key_disabled; 296*b843c749SSergey Zigachev uint32_t mclk_dpm_key_disabled; 297*b843c749SSergey Zigachev uint32_t pcie_dpm_key_disabled; 298*b843c749SSergey Zigachev uint32_t min_engine_clocks; 299*b843c749SSergey Zigachev struct smu7_pcie_perf_range pcie_gen_performance; 300*b843c749SSergey Zigachev struct smu7_pcie_perf_range pcie_lane_performance; 301*b843c749SSergey Zigachev struct smu7_pcie_perf_range pcie_gen_power_saving; 302*b843c749SSergey Zigachev struct smu7_pcie_perf_range pcie_lane_power_saving; 303*b843c749SSergey Zigachev bool use_pcie_performance_levels; 304*b843c749SSergey Zigachev bool use_pcie_power_saving_levels; 305*b843c749SSergey Zigachev uint32_t mclk_dpm0_activity_target; 306*b843c749SSergey Zigachev uint32_t low_sclk_interrupt_threshold; 307*b843c749SSergey Zigachev uint32_t last_mclk_dpm_enable_mask; 308*b843c749SSergey Zigachev bool uvd_enabled; 309*b843c749SSergey Zigachev 310*b843c749SSergey Zigachev /* ---- Power Gating States ---- */ 311*b843c749SSergey Zigachev bool uvd_power_gated; 312*b843c749SSergey Zigachev bool vce_power_gated; 313*b843c749SSergey Zigachev bool need_long_memory_training; 314*b843c749SSergey Zigachev 315*b843c749SSergey Zigachev /* Application power optimization parameters */ 316*b843c749SSergey Zigachev bool update_up_hyst; 317*b843c749SSergey Zigachev bool update_down_hyst; 318*b843c749SSergey Zigachev uint32_t down_hyst; 319*b843c749SSergey Zigachev uint32_t up_hyst; 320*b843c749SSergey Zigachev uint32_t disable_dpm_mask; 321*b843c749SSergey Zigachev bool apply_optimized_settings; 322*b843c749SSergey Zigachev 323*b843c749SSergey Zigachev uint32_t avfs_vdroop_override_setting; 324*b843c749SSergey Zigachev bool apply_avfs_cks_off_voltage; 325*b843c749SSergey Zigachev uint32_t frame_time_x2; 326*b843c749SSergey Zigachev uint16_t mem_latency_high; 327*b843c749SSergey Zigachev uint16_t mem_latency_low; 328*b843c749SSergey Zigachev uint32_t vr_config; 329*b843c749SSergey Zigachev struct profile_mode_setting current_profile_setting; 330*b843c749SSergey Zigachev }; 331*b843c749SSergey Zigachev 332*b843c749SSergey Zigachev /* To convert to Q8.8 format for firmware */ 333*b843c749SSergey Zigachev #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 334*b843c749SSergey Zigachev 335*b843c749SSergey Zigachev enum SMU7_I2CLineID { 336*b843c749SSergey Zigachev SMU7_I2CLineID_DDC1 = 0x90, 337*b843c749SSergey Zigachev SMU7_I2CLineID_DDC2 = 0x91, 338*b843c749SSergey Zigachev SMU7_I2CLineID_DDC3 = 0x92, 339*b843c749SSergey Zigachev SMU7_I2CLineID_DDC4 = 0x93, 340*b843c749SSergey Zigachev SMU7_I2CLineID_DDC5 = 0x94, 341*b843c749SSergey Zigachev SMU7_I2CLineID_DDC6 = 0x95, 342*b843c749SSergey Zigachev SMU7_I2CLineID_SCLSDA = 0x96, 343*b843c749SSergey Zigachev SMU7_I2CLineID_DDCVGA = 0x97 344*b843c749SSergey Zigachev }; 345*b843c749SSergey Zigachev 346*b843c749SSergey Zigachev #define SMU7_I2C_DDC1DATA 0 347*b843c749SSergey Zigachev #define SMU7_I2C_DDC1CLK 1 348*b843c749SSergey Zigachev #define SMU7_I2C_DDC2DATA 2 349*b843c749SSergey Zigachev #define SMU7_I2C_DDC2CLK 3 350*b843c749SSergey Zigachev #define SMU7_I2C_DDC3DATA 4 351*b843c749SSergey Zigachev #define SMU7_I2C_DDC3CLK 5 352*b843c749SSergey Zigachev #define SMU7_I2C_SDA 40 353*b843c749SSergey Zigachev #define SMU7_I2C_SCL 41 354*b843c749SSergey Zigachev #define SMU7_I2C_DDC4DATA 65 355*b843c749SSergey Zigachev #define SMU7_I2C_DDC4CLK 66 356*b843c749SSergey Zigachev #define SMU7_I2C_DDC5DATA 0x48 357*b843c749SSergey Zigachev #define SMU7_I2C_DDC5CLK 0x49 358*b843c749SSergey Zigachev #define SMU7_I2C_DDC6DATA 0x4a 359*b843c749SSergey Zigachev #define SMU7_I2C_DDC6CLK 0x4b 360*b843c749SSergey Zigachev #define SMU7_I2C_DDCVGADATA 0x4c 361*b843c749SSergey Zigachev #define SMU7_I2C_DDCVGACLK 0x4d 362*b843c749SSergey Zigachev 363*b843c749SSergey Zigachev #define SMU7_UNUSED_GPIO_PIN 0x7F 364*b843c749SSergey Zigachev uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 365*b843c749SSergey Zigachev uint32_t clock_insr); 366*b843c749SSergey Zigachev #endif 367*b843c749SSergey Zigachev 368