1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2015 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef _SMU8_HWMGR_H_ 25*b843c749SSergey Zigachev #define _SMU8_HWMGR_H_ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "cgs_common.h" 28*b843c749SSergey Zigachev #include "ppatomctrl.h" 29*b843c749SSergey Zigachev 30*b843c749SSergey Zigachev #define SMU8_NUM_NBPSTATES 4 31*b843c749SSergey Zigachev #define SMU8_NUM_NBPMEMORYCLOCK 2 32*b843c749SSergey Zigachev #define MAX_DISPLAY_CLOCK_LEVEL 8 33*b843c749SSergey Zigachev #define SMU8_MAX_HARDWARE_POWERLEVELS 8 34*b843c749SSergey Zigachev #define SMU8_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 35*b843c749SSergey Zigachev #define SMU8_MIN_DEEP_SLEEP_SCLK 800 36*b843c749SSergey Zigachev 37*b843c749SSergey Zigachev /* Carrizo device IDs */ 38*b843c749SSergey Zigachev #define DEVICE_ID_CZ_9870 0x9870 39*b843c749SSergey Zigachev #define DEVICE_ID_CZ_9874 0x9874 40*b843c749SSergey Zigachev #define DEVICE_ID_CZ_9875 0x9875 41*b843c749SSergey Zigachev #define DEVICE_ID_CZ_9876 0x9876 42*b843c749SSergey Zigachev #define DEVICE_ID_CZ_9877 0x9877 43*b843c749SSergey Zigachev 44*b843c749SSergey Zigachev struct smu8_dpm_entry { 45*b843c749SSergey Zigachev uint32_t soft_min_clk; 46*b843c749SSergey Zigachev uint32_t hard_min_clk; 47*b843c749SSergey Zigachev uint32_t soft_max_clk; 48*b843c749SSergey Zigachev uint32_t hard_max_clk; 49*b843c749SSergey Zigachev }; 50*b843c749SSergey Zigachev 51*b843c749SSergey Zigachev struct smu8_sys_info { 52*b843c749SSergey Zigachev uint32_t bootup_uma_clock; 53*b843c749SSergey Zigachev uint32_t bootup_engine_clock; 54*b843c749SSergey Zigachev uint32_t dentist_vco_freq; 55*b843c749SSergey Zigachev uint32_t nb_dpm_enable; 56*b843c749SSergey Zigachev uint32_t nbp_memory_clock[SMU8_NUM_NBPMEMORYCLOCK]; 57*b843c749SSergey Zigachev uint32_t nbp_n_clock[SMU8_NUM_NBPSTATES]; 58*b843c749SSergey Zigachev uint16_t nbp_voltage_index[SMU8_NUM_NBPSTATES]; 59*b843c749SSergey Zigachev uint32_t display_clock[MAX_DISPLAY_CLOCK_LEVEL]; 60*b843c749SSergey Zigachev uint16_t bootup_nb_voltage_index; 61*b843c749SSergey Zigachev uint8_t htc_tmp_lmt; 62*b843c749SSergey Zigachev uint8_t htc_hyst_lmt; 63*b843c749SSergey Zigachev uint32_t system_config; 64*b843c749SSergey Zigachev uint32_t uma_channel_number; 65*b843c749SSergey Zigachev }; 66*b843c749SSergey Zigachev 67*b843c749SSergey Zigachev #define MAX_DISPLAYPHY_IDS 0x8 68*b843c749SSergey Zigachev #define DISPLAYPHY_LANEMASK 0xF 69*b843c749SSergey Zigachev #define UNKNOWN_TRANSMITTER_PHY_ID (-1) 70*b843c749SSergey Zigachev 71*b843c749SSergey Zigachev #define DISPLAYPHY_PHYID_SHIFT 24 72*b843c749SSergey Zigachev #define DISPLAYPHY_LANESELECT_SHIFT 16 73*b843c749SSergey Zigachev 74*b843c749SSergey Zigachev #define DISPLAYPHY_RX_SELECT 0x1 75*b843c749SSergey Zigachev #define DISPLAYPHY_TX_SELECT 0x2 76*b843c749SSergey Zigachev #define DISPLAYPHY_CORE_SELECT 0x4 77*b843c749SSergey Zigachev 78*b843c749SSergey Zigachev #define DDI_POWERGATING_ARG(phyID, lanemask, rx, tx, core) \ 79*b843c749SSergey Zigachev (((uint32_t)(phyID))<<DISPLAYPHY_PHYID_SHIFT | \ 80*b843c749SSergey Zigachev ((uint32_t)(lanemask))<<DISPLAYPHY_LANESELECT_SHIFT | \ 81*b843c749SSergey Zigachev ((rx) ? DISPLAYPHY_RX_SELECT : 0) | \ 82*b843c749SSergey Zigachev ((tx) ? DISPLAYPHY_TX_SELECT : 0) | \ 83*b843c749SSergey Zigachev ((core) ? DISPLAYPHY_CORE_SELECT : 0)) 84*b843c749SSergey Zigachev 85*b843c749SSergey Zigachev struct smu8_display_phy_info_entry { 86*b843c749SSergey Zigachev uint8_t phy_present; 87*b843c749SSergey Zigachev uint8_t active_lane_mapping; 88*b843c749SSergey Zigachev uint8_t display_config_type; 89*b843c749SSergey Zigachev uint8_t active_number_of_lanes; 90*b843c749SSergey Zigachev }; 91*b843c749SSergey Zigachev 92*b843c749SSergey Zigachev #define SMU8_MAX_DISPLAYPHY_IDS 10 93*b843c749SSergey Zigachev 94*b843c749SSergey Zigachev struct smu8_display_phy_info { 95*b843c749SSergey Zigachev bool display_phy_access_initialized; 96*b843c749SSergey Zigachev struct smu8_display_phy_info_entry entries[SMU8_MAX_DISPLAYPHY_IDS]; 97*b843c749SSergey Zigachev }; 98*b843c749SSergey Zigachev 99*b843c749SSergey Zigachev struct smu8_power_level { 100*b843c749SSergey Zigachev uint32_t engineClock; 101*b843c749SSergey Zigachev uint8_t vddcIndex; 102*b843c749SSergey Zigachev uint8_t dsDividerIndex; 103*b843c749SSergey Zigachev uint8_t ssDividerIndex; 104*b843c749SSergey Zigachev uint8_t allowGnbSlow; 105*b843c749SSergey Zigachev uint8_t forceNBPstate; 106*b843c749SSergey Zigachev uint8_t display_wm; 107*b843c749SSergey Zigachev uint8_t vce_wm; 108*b843c749SSergey Zigachev uint8_t numSIMDToPowerDown; 109*b843c749SSergey Zigachev uint8_t hysteresis_up; 110*b843c749SSergey Zigachev uint8_t rsv[3]; 111*b843c749SSergey Zigachev }; 112*b843c749SSergey Zigachev 113*b843c749SSergey Zigachev struct smu8_uvd_clocks { 114*b843c749SSergey Zigachev uint32_t vclk; 115*b843c749SSergey Zigachev uint32_t dclk; 116*b843c749SSergey Zigachev uint32_t vclk_low_divider; 117*b843c749SSergey Zigachev uint32_t vclk_high_divider; 118*b843c749SSergey Zigachev uint32_t dclk_low_divider; 119*b843c749SSergey Zigachev uint32_t dclk_high_divider; 120*b843c749SSergey Zigachev }; 121*b843c749SSergey Zigachev 122*b843c749SSergey Zigachev enum smu8_pstate_previous_action { 123*b843c749SSergey Zigachev DO_NOTHING = 1, 124*b843c749SSergey Zigachev FORCE_HIGH, 125*b843c749SSergey Zigachev CANCEL_FORCE_HIGH 126*b843c749SSergey Zigachev }; 127*b843c749SSergey Zigachev 128*b843c749SSergey Zigachev struct pp_disable_nb_ps_flags { 129*b843c749SSergey Zigachev union { 130*b843c749SSergey Zigachev struct { 131*b843c749SSergey Zigachev uint32_t entry : 1; 132*b843c749SSergey Zigachev uint32_t display : 1; 133*b843c749SSergey Zigachev uint32_t driver: 1; 134*b843c749SSergey Zigachev uint32_t vce : 1; 135*b843c749SSergey Zigachev uint32_t uvd : 1; 136*b843c749SSergey Zigachev uint32_t acp : 1; 137*b843c749SSergey Zigachev uint32_t reserved: 26; 138*b843c749SSergey Zigachev } bits; 139*b843c749SSergey Zigachev uint32_t u32All; 140*b843c749SSergey Zigachev }; 141*b843c749SSergey Zigachev }; 142*b843c749SSergey Zigachev 143*b843c749SSergey Zigachev struct smu8_power_state { 144*b843c749SSergey Zigachev unsigned int magic; 145*b843c749SSergey Zigachev uint32_t level; 146*b843c749SSergey Zigachev struct smu8_uvd_clocks uvd_clocks; 147*b843c749SSergey Zigachev uint32_t evclk; 148*b843c749SSergey Zigachev uint32_t ecclk; 149*b843c749SSergey Zigachev uint32_t samclk; 150*b843c749SSergey Zigachev uint32_t acpclk; 151*b843c749SSergey Zigachev bool need_dfs_bypass; 152*b843c749SSergey Zigachev uint32_t nbps_flags; 153*b843c749SSergey Zigachev uint32_t bapm_flags; 154*b843c749SSergey Zigachev uint8_t dpm_0_pg_nb_ps_low; 155*b843c749SSergey Zigachev uint8_t dpm_0_pg_nb_ps_high; 156*b843c749SSergey Zigachev uint8_t dpm_x_nb_ps_low; 157*b843c749SSergey Zigachev uint8_t dpm_x_nb_ps_high; 158*b843c749SSergey Zigachev enum smu8_pstate_previous_action action; 159*b843c749SSergey Zigachev struct smu8_power_level levels[SMU8_MAX_HARDWARE_POWERLEVELS]; 160*b843c749SSergey Zigachev struct pp_disable_nb_ps_flags disable_nb_ps_flag; 161*b843c749SSergey Zigachev }; 162*b843c749SSergey Zigachev 163*b843c749SSergey Zigachev #define DPMFlags_SCLK_Enabled 0x00000001 164*b843c749SSergey Zigachev #define DPMFlags_UVD_Enabled 0x00000002 165*b843c749SSergey Zigachev #define DPMFlags_VCE_Enabled 0x00000004 166*b843c749SSergey Zigachev #define DPMFlags_ACP_Enabled 0x00000008 167*b843c749SSergey Zigachev #define DPMFlags_ForceHighestValid 0x40000000 168*b843c749SSergey Zigachev #define DPMFlags_Debug 0x80000000 169*b843c749SSergey Zigachev 170*b843c749SSergey Zigachev #define SMU_EnabledFeatureScoreboard_AcpDpmOn 0x00000001 /* bit 0 */ 171*b843c749SSergey Zigachev #define SMU_EnabledFeatureScoreboard_UvdDpmOn 0x00800000 /* bit 23 */ 172*b843c749SSergey Zigachev #define SMU_EnabledFeatureScoreboard_VceDpmOn 0x01000000 /* bit 24 */ 173*b843c749SSergey Zigachev 174*b843c749SSergey Zigachev struct cc6_settings { 175*b843c749SSergey Zigachev bool cc6_setting_changed; 176*b843c749SSergey Zigachev bool nb_pstate_switch_disable;/* controls NB PState switch */ 177*b843c749SSergey Zigachev bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */ 178*b843c749SSergey Zigachev bool cpu_pstate_disable; 179*b843c749SSergey Zigachev uint32_t cpu_pstate_separation_time; 180*b843c749SSergey Zigachev }; 181*b843c749SSergey Zigachev 182*b843c749SSergey Zigachev struct smu8_hwmgr { 183*b843c749SSergey Zigachev uint32_t dpm_interval; 184*b843c749SSergey Zigachev 185*b843c749SSergey Zigachev uint32_t voltage_drop_threshold; 186*b843c749SSergey Zigachev 187*b843c749SSergey Zigachev uint32_t voting_rights_clients; 188*b843c749SSergey Zigachev 189*b843c749SSergey Zigachev uint32_t disable_driver_thermal_policy; 190*b843c749SSergey Zigachev 191*b843c749SSergey Zigachev uint32_t static_screen_threshold; 192*b843c749SSergey Zigachev 193*b843c749SSergey Zigachev uint32_t gfx_power_gating_threshold; 194*b843c749SSergey Zigachev 195*b843c749SSergey Zigachev uint32_t activity_hysteresis; 196*b843c749SSergey Zigachev uint32_t bootup_sclk_divider; 197*b843c749SSergey Zigachev uint32_t gfx_ramp_step; 198*b843c749SSergey Zigachev uint32_t gfx_ramp_delay; /* in micro-seconds */ 199*b843c749SSergey Zigachev 200*b843c749SSergey Zigachev uint32_t thermal_auto_throttling_treshold; 201*b843c749SSergey Zigachev 202*b843c749SSergey Zigachev struct smu8_sys_info sys_info; 203*b843c749SSergey Zigachev 204*b843c749SSergey Zigachev struct smu8_power_level boot_power_level; 205*b843c749SSergey Zigachev struct smu8_power_state *smu8_current_ps; 206*b843c749SSergey Zigachev struct smu8_power_state *smu8_requested_ps; 207*b843c749SSergey Zigachev 208*b843c749SSergey Zigachev uint32_t mgcg_cgtt_local0; 209*b843c749SSergey Zigachev uint32_t mgcg_cgtt_local1; 210*b843c749SSergey Zigachev 211*b843c749SSergey Zigachev uint32_t tdr_clock; /* in 10khz unit */ 212*b843c749SSergey Zigachev 213*b843c749SSergey Zigachev uint32_t ddi_power_gating_disabled; 214*b843c749SSergey Zigachev uint32_t disable_gfx_power_gating_in_uvd; 215*b843c749SSergey Zigachev uint32_t disable_nb_ps3_in_battery; 216*b843c749SSergey Zigachev 217*b843c749SSergey Zigachev uint32_t lock_nb_ps_in_uvd_play_back; 218*b843c749SSergey Zigachev 219*b843c749SSergey Zigachev struct smu8_display_phy_info display_phy_info; 220*b843c749SSergey Zigachev uint32_t vce_slow_sclk_threshold; /* default 200mhz */ 221*b843c749SSergey Zigachev uint32_t dce_slow_sclk_threshold; /* default 300mhz */ 222*b843c749SSergey Zigachev uint32_t min_sclk_did; /* minimum sclk divider */ 223*b843c749SSergey Zigachev 224*b843c749SSergey Zigachev bool disp_clk_bypass; 225*b843c749SSergey Zigachev bool disp_clk_bypass_pending; 226*b843c749SSergey Zigachev uint32_t bapm_enabled; 227*b843c749SSergey Zigachev uint32_t clock_slow_down_freq; 228*b843c749SSergey Zigachev uint32_t skip_clock_slow_down; 229*b843c749SSergey Zigachev uint32_t enable_nb_ps_policy; 230*b843c749SSergey Zigachev uint32_t voltage_drop_in_dce_power_gating; 231*b843c749SSergey Zigachev uint32_t uvd_dpm_interval; 232*b843c749SSergey Zigachev uint32_t override_dynamic_mgpg; 233*b843c749SSergey Zigachev uint32_t lclk_deep_enabled; 234*b843c749SSergey Zigachev 235*b843c749SSergey Zigachev uint32_t uvd_performance; 236*b843c749SSergey Zigachev 237*b843c749SSergey Zigachev bool video_start; 238*b843c749SSergey Zigachev bool battery_state; 239*b843c749SSergey Zigachev uint32_t lowest_valid; 240*b843c749SSergey Zigachev uint32_t highest_valid; 241*b843c749SSergey Zigachev uint32_t high_voltage_threshold; 242*b843c749SSergey Zigachev uint32_t is_nb_dpm_enabled; 243*b843c749SSergey Zigachev struct cc6_settings cc6_settings; 244*b843c749SSergey Zigachev uint32_t is_voltage_island_enabled; 245*b843c749SSergey Zigachev 246*b843c749SSergey Zigachev bool pgacpinit; 247*b843c749SSergey Zigachev 248*b843c749SSergey Zigachev uint8_t disp_config; 249*b843c749SSergey Zigachev 250*b843c749SSergey Zigachev /* PowerTune */ 251*b843c749SSergey Zigachev uint32_t power_containment_features; 252*b843c749SSergey Zigachev bool cac_enabled; 253*b843c749SSergey Zigachev bool disable_uvd_power_tune_feature; 254*b843c749SSergey Zigachev bool enable_ba_pm_feature; 255*b843c749SSergey Zigachev bool enable_tdc_limit_feature; 256*b843c749SSergey Zigachev 257*b843c749SSergey Zigachev uint32_t sram_end; 258*b843c749SSergey Zigachev uint32_t dpm_table_start; 259*b843c749SSergey Zigachev uint32_t soft_regs_start; 260*b843c749SSergey Zigachev 261*b843c749SSergey Zigachev uint8_t uvd_level_count; 262*b843c749SSergey Zigachev uint8_t vce_level_count; 263*b843c749SSergey Zigachev 264*b843c749SSergey Zigachev uint8_t acp_level_count; 265*b843c749SSergey Zigachev uint8_t samu_level_count; 266*b843c749SSergey Zigachev uint32_t fps_high_threshold; 267*b843c749SSergey Zigachev uint32_t fps_low_threshold; 268*b843c749SSergey Zigachev 269*b843c749SSergey Zigachev uint32_t dpm_flags; 270*b843c749SSergey Zigachev struct smu8_dpm_entry sclk_dpm; 271*b843c749SSergey Zigachev struct smu8_dpm_entry uvd_dpm; 272*b843c749SSergey Zigachev struct smu8_dpm_entry vce_dpm; 273*b843c749SSergey Zigachev struct smu8_dpm_entry acp_dpm; 274*b843c749SSergey Zigachev 275*b843c749SSergey Zigachev uint8_t uvd_boot_level; 276*b843c749SSergey Zigachev uint8_t vce_boot_level; 277*b843c749SSergey Zigachev uint8_t acp_boot_level; 278*b843c749SSergey Zigachev uint8_t samu_boot_level; 279*b843c749SSergey Zigachev uint8_t uvd_interval; 280*b843c749SSergey Zigachev uint8_t vce_interval; 281*b843c749SSergey Zigachev uint8_t acp_interval; 282*b843c749SSergey Zigachev uint8_t samu_interval; 283*b843c749SSergey Zigachev 284*b843c749SSergey Zigachev uint8_t graphics_interval; 285*b843c749SSergey Zigachev uint8_t graphics_therm_throttle_enable; 286*b843c749SSergey Zigachev uint8_t graphics_voltage_change_enable; 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev uint8_t graphics_clk_slow_enable; 289*b843c749SSergey Zigachev uint8_t graphics_clk_slow_divider; 290*b843c749SSergey Zigachev 291*b843c749SSergey Zigachev uint32_t display_cac; 292*b843c749SSergey Zigachev uint32_t low_sclk_interrupt_threshold; 293*b843c749SSergey Zigachev 294*b843c749SSergey Zigachev uint32_t dram_log_addr_h; 295*b843c749SSergey Zigachev uint32_t dram_log_addr_l; 296*b843c749SSergey Zigachev uint32_t dram_log_phy_addr_h; 297*b843c749SSergey Zigachev uint32_t dram_log_phy_addr_l; 298*b843c749SSergey Zigachev uint32_t dram_log_buff_size; 299*b843c749SSergey Zigachev 300*b843c749SSergey Zigachev bool uvd_power_gated; 301*b843c749SSergey Zigachev bool vce_power_gated; 302*b843c749SSergey Zigachev bool samu_power_gated; 303*b843c749SSergey Zigachev bool acp_power_gated; 304*b843c749SSergey Zigachev bool acp_power_up_no_dsp; 305*b843c749SSergey Zigachev uint32_t active_process_mask; 306*b843c749SSergey Zigachev 307*b843c749SSergey Zigachev uint32_t max_sclk_level; 308*b843c749SSergey Zigachev uint32_t num_of_clk_entries; 309*b843c749SSergey Zigachev }; 310*b843c749SSergey Zigachev 311*b843c749SSergey Zigachev #endif /* _SMU8_HWMGR_H_ */ 312