1*b843c749SSergey Zigachev /* 2*b843c749SSergey Zigachev * Copyright 2016 Advanced Micro Devices, Inc. 3*b843c749SSergey Zigachev * 4*b843c749SSergey Zigachev * Permission is hereby granted, free of charge, to any person obtaining a 5*b843c749SSergey Zigachev * copy of this software and associated documentation files (the "Software"), 6*b843c749SSergey Zigachev * to deal in the Software without restriction, including without limitation 7*b843c749SSergey Zigachev * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*b843c749SSergey Zigachev * and/or sell copies of the Software, and to permit persons to whom the 9*b843c749SSergey Zigachev * Software is furnished to do so, subject to the following conditions: 10*b843c749SSergey Zigachev * 11*b843c749SSergey Zigachev * The above copyright notice and this permission notice shall be included in 12*b843c749SSergey Zigachev * all copies or substantial portions of the Software. 13*b843c749SSergey Zigachev * 14*b843c749SSergey Zigachev * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*b843c749SSergey Zigachev * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*b843c749SSergey Zigachev * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*b843c749SSergey Zigachev * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*b843c749SSergey Zigachev * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*b843c749SSergey Zigachev * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*b843c749SSergey Zigachev * OTHER DEALINGS IN THE SOFTWARE. 21*b843c749SSergey Zigachev * 22*b843c749SSergey Zigachev */ 23*b843c749SSergey Zigachev 24*b843c749SSergey Zigachev #ifndef _VEGA10_HWMGR_H_ 25*b843c749SSergey Zigachev #define _VEGA10_HWMGR_H_ 26*b843c749SSergey Zigachev 27*b843c749SSergey Zigachev #include "hwmgr.h" 28*b843c749SSergey Zigachev #include "smu9_driver_if.h" 29*b843c749SSergey Zigachev #include "ppatomctrl.h" 30*b843c749SSergey Zigachev #include "ppatomfwctrl.h" 31*b843c749SSergey Zigachev #include "vega10_ppsmc.h" 32*b843c749SSergey Zigachev #include "vega10_powertune.h" 33*b843c749SSergey Zigachev 34*b843c749SSergey Zigachev #define VEGA10_MAX_HARDWARE_POWERLEVELS 2 35*b843c749SSergey Zigachev 36*b843c749SSergey Zigachev #define WaterMarksExist 1 37*b843c749SSergey Zigachev #define WaterMarksLoaded 2 38*b843c749SSergey Zigachev 39*b843c749SSergey Zigachev enum { 40*b843c749SSergey Zigachev GNLD_DPM_PREFETCHER = 0, 41*b843c749SSergey Zigachev GNLD_DPM_GFXCLK, 42*b843c749SSergey Zigachev GNLD_DPM_UCLK, 43*b843c749SSergey Zigachev GNLD_DPM_SOCCLK, 44*b843c749SSergey Zigachev GNLD_DPM_UVD, 45*b843c749SSergey Zigachev GNLD_DPM_VCE, 46*b843c749SSergey Zigachev GNLD_ULV, 47*b843c749SSergey Zigachev GNLD_DPM_MP0CLK, 48*b843c749SSergey Zigachev GNLD_DPM_LINK, 49*b843c749SSergey Zigachev GNLD_DPM_DCEFCLK, 50*b843c749SSergey Zigachev GNLD_AVFS, 51*b843c749SSergey Zigachev GNLD_DS_GFXCLK, 52*b843c749SSergey Zigachev GNLD_DS_SOCCLK, 53*b843c749SSergey Zigachev GNLD_DS_LCLK, 54*b843c749SSergey Zigachev GNLD_PPT, 55*b843c749SSergey Zigachev GNLD_TDC, 56*b843c749SSergey Zigachev GNLD_THERMAL, 57*b843c749SSergey Zigachev GNLD_GFX_PER_CU_CG, 58*b843c749SSergey Zigachev GNLD_RM, 59*b843c749SSergey Zigachev GNLD_DS_DCEFCLK, 60*b843c749SSergey Zigachev GNLD_ACDC, 61*b843c749SSergey Zigachev GNLD_VR0HOT, 62*b843c749SSergey Zigachev GNLD_VR1HOT, 63*b843c749SSergey Zigachev GNLD_FW_CTF, 64*b843c749SSergey Zigachev GNLD_LED_DISPLAY, 65*b843c749SSergey Zigachev GNLD_FAN_CONTROL, 66*b843c749SSergey Zigachev GNLD_FEATURE_FAST_PPT_BIT, 67*b843c749SSergey Zigachev GNLD_DIDT, 68*b843c749SSergey Zigachev GNLD_ACG, 69*b843c749SSergey Zigachev GNLD_PCC_LIMIT, 70*b843c749SSergey Zigachev GNLD_FEATURES_MAX 71*b843c749SSergey Zigachev }; 72*b843c749SSergey Zigachev 73*b843c749SSergey Zigachev #define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1) 74*b843c749SSergey Zigachev 75*b843c749SSergey Zigachev #define SMC_DPM_FEATURES 0x30F 76*b843c749SSergey Zigachev 77*b843c749SSergey Zigachev struct smu_features { 78*b843c749SSergey Zigachev bool supported; 79*b843c749SSergey Zigachev bool enabled; 80*b843c749SSergey Zigachev uint32_t smu_feature_id; 81*b843c749SSergey Zigachev uint32_t smu_feature_bitmap; 82*b843c749SSergey Zigachev }; 83*b843c749SSergey Zigachev 84*b843c749SSergey Zigachev struct vega10_performance_level { 85*b843c749SSergey Zigachev uint32_t soc_clock; 86*b843c749SSergey Zigachev uint32_t gfx_clock; 87*b843c749SSergey Zigachev uint32_t mem_clock; 88*b843c749SSergey Zigachev }; 89*b843c749SSergey Zigachev 90*b843c749SSergey Zigachev struct vega10_bacos { 91*b843c749SSergey Zigachev uint32_t baco_flags; 92*b843c749SSergey Zigachev /* struct vega10_performance_level performance_level; */ 93*b843c749SSergey Zigachev }; 94*b843c749SSergey Zigachev 95*b843c749SSergey Zigachev struct vega10_uvd_clocks { 96*b843c749SSergey Zigachev uint32_t vclk; 97*b843c749SSergey Zigachev uint32_t dclk; 98*b843c749SSergey Zigachev }; 99*b843c749SSergey Zigachev 100*b843c749SSergey Zigachev struct vega10_vce_clocks { 101*b843c749SSergey Zigachev uint32_t evclk; 102*b843c749SSergey Zigachev uint32_t ecclk; 103*b843c749SSergey Zigachev }; 104*b843c749SSergey Zigachev 105*b843c749SSergey Zigachev struct vega10_power_state { 106*b843c749SSergey Zigachev uint32_t magic; 107*b843c749SSergey Zigachev struct vega10_uvd_clocks uvd_clks; 108*b843c749SSergey Zigachev struct vega10_vce_clocks vce_clks; 109*b843c749SSergey Zigachev uint16_t performance_level_count; 110*b843c749SSergey Zigachev bool dc_compatible; 111*b843c749SSergey Zigachev uint32_t sclk_threshold; 112*b843c749SSergey Zigachev struct vega10_performance_level performance_levels[VEGA10_MAX_HARDWARE_POWERLEVELS]; 113*b843c749SSergey Zigachev }; 114*b843c749SSergey Zigachev 115*b843c749SSergey Zigachev struct vega10_dpm_level { 116*b843c749SSergey Zigachev bool enabled; 117*b843c749SSergey Zigachev uint32_t value; 118*b843c749SSergey Zigachev uint32_t param1; 119*b843c749SSergey Zigachev }; 120*b843c749SSergey Zigachev 121*b843c749SSergey Zigachev #define VEGA10_MAX_DEEPSLEEP_DIVIDER_ID 5 122*b843c749SSergey Zigachev #define MAX_REGULAR_DPM_NUMBER 8 123*b843c749SSergey Zigachev #define MAX_PCIE_CONF 2 124*b843c749SSergey Zigachev #define VEGA10_MINIMUM_ENGINE_CLOCK 2500 125*b843c749SSergey Zigachev 126*b843c749SSergey Zigachev struct vega10_dpm_state { 127*b843c749SSergey Zigachev uint32_t soft_min_level; 128*b843c749SSergey Zigachev uint32_t soft_max_level; 129*b843c749SSergey Zigachev uint32_t hard_min_level; 130*b843c749SSergey Zigachev uint32_t hard_max_level; 131*b843c749SSergey Zigachev }; 132*b843c749SSergey Zigachev 133*b843c749SSergey Zigachev struct vega10_single_dpm_table { 134*b843c749SSergey Zigachev uint32_t count; 135*b843c749SSergey Zigachev struct vega10_dpm_state dpm_state; 136*b843c749SSergey Zigachev struct vega10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 137*b843c749SSergey Zigachev }; 138*b843c749SSergey Zigachev 139*b843c749SSergey Zigachev struct vega10_pcie_table { 140*b843c749SSergey Zigachev uint16_t count; 141*b843c749SSergey Zigachev uint8_t pcie_gen[MAX_PCIE_CONF]; 142*b843c749SSergey Zigachev uint8_t pcie_lane[MAX_PCIE_CONF]; 143*b843c749SSergey Zigachev uint32_t lclk[MAX_PCIE_CONF]; 144*b843c749SSergey Zigachev }; 145*b843c749SSergey Zigachev 146*b843c749SSergey Zigachev struct vega10_dpm_table { 147*b843c749SSergey Zigachev struct vega10_single_dpm_table soc_table; 148*b843c749SSergey Zigachev struct vega10_single_dpm_table gfx_table; 149*b843c749SSergey Zigachev struct vega10_single_dpm_table mem_table; 150*b843c749SSergey Zigachev struct vega10_single_dpm_table eclk_table; 151*b843c749SSergey Zigachev struct vega10_single_dpm_table vclk_table; 152*b843c749SSergey Zigachev struct vega10_single_dpm_table dclk_table; 153*b843c749SSergey Zigachev struct vega10_single_dpm_table dcef_table; 154*b843c749SSergey Zigachev struct vega10_single_dpm_table pixel_table; 155*b843c749SSergey Zigachev struct vega10_single_dpm_table display_table; 156*b843c749SSergey Zigachev struct vega10_single_dpm_table phy_table; 157*b843c749SSergey Zigachev struct vega10_pcie_table pcie_table; 158*b843c749SSergey Zigachev }; 159*b843c749SSergey Zigachev 160*b843c749SSergey Zigachev #define VEGA10_MAX_LEAKAGE_COUNT 8 161*b843c749SSergey Zigachev struct vega10_leakage_voltage { 162*b843c749SSergey Zigachev uint16_t count; 163*b843c749SSergey Zigachev uint16_t leakage_id[VEGA10_MAX_LEAKAGE_COUNT]; 164*b843c749SSergey Zigachev uint16_t actual_voltage[VEGA10_MAX_LEAKAGE_COUNT]; 165*b843c749SSergey Zigachev }; 166*b843c749SSergey Zigachev 167*b843c749SSergey Zigachev struct vega10_display_timing { 168*b843c749SSergey Zigachev uint32_t min_clock_in_sr; 169*b843c749SSergey Zigachev uint32_t num_existing_displays; 170*b843c749SSergey Zigachev }; 171*b843c749SSergey Zigachev 172*b843c749SSergey Zigachev struct vega10_dpmlevel_enable_mask { 173*b843c749SSergey Zigachev uint32_t uvd_dpm_enable_mask; 174*b843c749SSergey Zigachev uint32_t vce_dpm_enable_mask; 175*b843c749SSergey Zigachev uint32_t acp_dpm_enable_mask; 176*b843c749SSergey Zigachev uint32_t samu_dpm_enable_mask; 177*b843c749SSergey Zigachev uint32_t sclk_dpm_enable_mask; 178*b843c749SSergey Zigachev uint32_t mclk_dpm_enable_mask; 179*b843c749SSergey Zigachev }; 180*b843c749SSergey Zigachev 181*b843c749SSergey Zigachev struct vega10_vbios_boot_state { 182*b843c749SSergey Zigachev bool bsoc_vddc_lock; 183*b843c749SSergey Zigachev uint16_t vddc; 184*b843c749SSergey Zigachev uint16_t vddci; 185*b843c749SSergey Zigachev uint16_t mvddc; 186*b843c749SSergey Zigachev uint16_t vdd_gfx; 187*b843c749SSergey Zigachev uint32_t gfx_clock; 188*b843c749SSergey Zigachev uint32_t mem_clock; 189*b843c749SSergey Zigachev uint32_t soc_clock; 190*b843c749SSergey Zigachev uint32_t dcef_clock; 191*b843c749SSergey Zigachev }; 192*b843c749SSergey Zigachev 193*b843c749SSergey Zigachev struct vega10_smc_state_table { 194*b843c749SSergey Zigachev uint32_t soc_boot_level; 195*b843c749SSergey Zigachev uint32_t gfx_boot_level; 196*b843c749SSergey Zigachev uint32_t dcef_boot_level; 197*b843c749SSergey Zigachev uint32_t mem_boot_level; 198*b843c749SSergey Zigachev uint32_t uvd_boot_level; 199*b843c749SSergey Zigachev uint32_t vce_boot_level; 200*b843c749SSergey Zigachev uint32_t gfx_max_level; 201*b843c749SSergey Zigachev uint32_t mem_max_level; 202*b843c749SSergey Zigachev uint8_t vr_hot_gpio; 203*b843c749SSergey Zigachev uint8_t ac_dc_gpio; 204*b843c749SSergey Zigachev uint8_t therm_out_gpio; 205*b843c749SSergey Zigachev uint8_t therm_out_polarity; 206*b843c749SSergey Zigachev uint8_t therm_out_mode; 207*b843c749SSergey Zigachev PPTable_t pp_table; 208*b843c749SSergey Zigachev Watermarks_t water_marks_table; 209*b843c749SSergey Zigachev AvfsTable_t avfs_table; 210*b843c749SSergey Zigachev AvfsFuseOverride_t avfs_fuse_override_table; 211*b843c749SSergey Zigachev }; 212*b843c749SSergey Zigachev 213*b843c749SSergey Zigachev struct vega10_mclk_latency_entries { 214*b843c749SSergey Zigachev uint32_t frequency; 215*b843c749SSergey Zigachev uint32_t latency; 216*b843c749SSergey Zigachev }; 217*b843c749SSergey Zigachev 218*b843c749SSergey Zigachev struct vega10_mclk_latency_table { 219*b843c749SSergey Zigachev uint32_t count; 220*b843c749SSergey Zigachev struct vega10_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER]; 221*b843c749SSergey Zigachev }; 222*b843c749SSergey Zigachev 223*b843c749SSergey Zigachev struct vega10_registry_data { 224*b843c749SSergey Zigachev uint8_t ac_dc_switch_gpio_support; 225*b843c749SSergey Zigachev uint8_t avfs_support; 226*b843c749SSergey Zigachev uint8_t cac_support; 227*b843c749SSergey Zigachev uint8_t clock_stretcher_support; 228*b843c749SSergey Zigachev uint8_t db_ramping_support; 229*b843c749SSergey Zigachev uint8_t didt_mode; 230*b843c749SSergey Zigachev uint8_t didt_support; 231*b843c749SSergey Zigachev uint8_t edc_didt_support; 232*b843c749SSergey Zigachev uint8_t dynamic_state_patching_support; 233*b843c749SSergey Zigachev uint8_t enable_pkg_pwr_tracking_feature; 234*b843c749SSergey Zigachev uint8_t enable_tdc_limit_feature; 235*b843c749SSergey Zigachev uint32_t fast_watermark_threshold; 236*b843c749SSergey Zigachev uint8_t force_dpm_high; 237*b843c749SSergey Zigachev uint8_t fuzzy_fan_control_support; 238*b843c749SSergey Zigachev uint8_t long_idle_baco_support; 239*b843c749SSergey Zigachev uint8_t mclk_dpm_key_disabled; 240*b843c749SSergey Zigachev uint8_t od_state_in_dc_support; 241*b843c749SSergey Zigachev uint8_t pcieLaneOverride; 242*b843c749SSergey Zigachev uint8_t pcieSpeedOverride; 243*b843c749SSergey Zigachev uint32_t pcieClockOverride; 244*b843c749SSergey Zigachev uint8_t pcie_dpm_key_disabled; 245*b843c749SSergey Zigachev uint8_t dcefclk_dpm_key_disabled; 246*b843c749SSergey Zigachev uint8_t power_containment_support; 247*b843c749SSergey Zigachev uint8_t ppt_support; 248*b843c749SSergey Zigachev uint8_t prefetcher_dpm_key_disabled; 249*b843c749SSergey Zigachev uint8_t quick_transition_support; 250*b843c749SSergey Zigachev uint8_t regulator_hot_gpio_support; 251*b843c749SSergey Zigachev uint8_t sclk_deep_sleep_support; 252*b843c749SSergey Zigachev uint8_t sclk_dpm_key_disabled; 253*b843c749SSergey Zigachev uint8_t sclk_from_vbios; 254*b843c749SSergey Zigachev uint8_t sclk_throttle_low_notification; 255*b843c749SSergey Zigachev uint8_t show_baco_dbg_info; 256*b843c749SSergey Zigachev uint8_t skip_baco_hardware; 257*b843c749SSergey Zigachev uint8_t socclk_dpm_key_disabled; 258*b843c749SSergey Zigachev uint8_t spll_shutdown_support; 259*b843c749SSergey Zigachev uint8_t sq_ramping_support; 260*b843c749SSergey Zigachev uint32_t stable_pstate_sclk_dpm_percentage; 261*b843c749SSergey Zigachev uint8_t tcp_ramping_support; 262*b843c749SSergey Zigachev uint8_t tdc_support; 263*b843c749SSergey Zigachev uint8_t td_ramping_support; 264*b843c749SSergey Zigachev uint8_t dbr_ramping_support; 265*b843c749SSergey Zigachev uint8_t gc_didt_support; 266*b843c749SSergey Zigachev uint8_t psm_didt_support; 267*b843c749SSergey Zigachev uint8_t thermal_out_gpio_support; 268*b843c749SSergey Zigachev uint8_t thermal_support; 269*b843c749SSergey Zigachev uint8_t fw_ctf_enabled; 270*b843c749SSergey Zigachev uint8_t fan_control_support; 271*b843c749SSergey Zigachev uint8_t ulps_support; 272*b843c749SSergey Zigachev uint8_t ulv_support; 273*b843c749SSergey Zigachev uint32_t vddc_vddci_delta; 274*b843c749SSergey Zigachev uint8_t odn_feature_enable; 275*b843c749SSergey Zigachev uint8_t disable_water_mark; 276*b843c749SSergey Zigachev uint8_t zrpm_stop_temp; 277*b843c749SSergey Zigachev uint8_t zrpm_start_temp; 278*b843c749SSergey Zigachev uint8_t led_dpm_enabled; 279*b843c749SSergey Zigachev uint8_t vr0hot_enabled; 280*b843c749SSergey Zigachev uint8_t vr1hot_enabled; 281*b843c749SSergey Zigachev }; 282*b843c749SSergey Zigachev 283*b843c749SSergey Zigachev struct vega10_odn_clock_voltage_dependency_table { 284*b843c749SSergey Zigachev uint32_t count; 285*b843c749SSergey Zigachev struct phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 286*b843c749SSergey Zigachev }; 287*b843c749SSergey Zigachev 288*b843c749SSergey Zigachev struct vega10_odn_vddc_lookup_table { 289*b843c749SSergey Zigachev uint32_t count; 290*b843c749SSergey Zigachev struct phm_ppt_v1_voltage_lookup_record entries[MAX_REGULAR_DPM_NUMBER]; 291*b843c749SSergey Zigachev }; 292*b843c749SSergey Zigachev 293*b843c749SSergey Zigachev struct vega10_odn_dpm_table { 294*b843c749SSergey Zigachev struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_sclk; 295*b843c749SSergey Zigachev struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_mclk; 296*b843c749SSergey Zigachev struct vega10_odn_clock_voltage_dependency_table vdd_dep_on_socclk; 297*b843c749SSergey Zigachev struct vega10_odn_vddc_lookup_table vddc_lookup_table; 298*b843c749SSergey Zigachev uint32_t max_vddc; 299*b843c749SSergey Zigachev uint32_t min_vddc; 300*b843c749SSergey Zigachev }; 301*b843c749SSergey Zigachev 302*b843c749SSergey Zigachev struct vega10_odn_fan_table { 303*b843c749SSergey Zigachev uint32_t target_fan_speed; 304*b843c749SSergey Zigachev uint32_t target_temperature; 305*b843c749SSergey Zigachev uint32_t min_performance_clock; 306*b843c749SSergey Zigachev uint32_t min_fan_limit; 307*b843c749SSergey Zigachev }; 308*b843c749SSergey Zigachev 309*b843c749SSergey Zigachev struct vega10_hwmgr { 310*b843c749SSergey Zigachev struct vega10_dpm_table dpm_table; 311*b843c749SSergey Zigachev struct vega10_dpm_table golden_dpm_table; 312*b843c749SSergey Zigachev struct vega10_registry_data registry_data; 313*b843c749SSergey Zigachev struct vega10_vbios_boot_state vbios_boot_state; 314*b843c749SSergey Zigachev struct vega10_mclk_latency_table mclk_latency_table; 315*b843c749SSergey Zigachev 316*b843c749SSergey Zigachev struct vega10_leakage_voltage vddc_leakage; 317*b843c749SSergey Zigachev 318*b843c749SSergey Zigachev uint32_t vddc_control; 319*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table vddc_voltage_table; 320*b843c749SSergey Zigachev uint32_t mvdd_control; 321*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table mvdd_voltage_table; 322*b843c749SSergey Zigachev uint32_t vddci_control; 323*b843c749SSergey Zigachev struct pp_atomfwctrl_voltage_table vddci_voltage_table; 324*b843c749SSergey Zigachev 325*b843c749SSergey Zigachev uint32_t active_auto_throttle_sources; 326*b843c749SSergey Zigachev uint32_t water_marks_bitmap; 327*b843c749SSergey Zigachev struct vega10_bacos bacos; 328*b843c749SSergey Zigachev 329*b843c749SSergey Zigachev struct vega10_odn_dpm_table odn_dpm_table; 330*b843c749SSergey Zigachev struct vega10_odn_fan_table odn_fan_table; 331*b843c749SSergey Zigachev 332*b843c749SSergey Zigachev /* ---- General data ---- */ 333*b843c749SSergey Zigachev uint8_t need_update_dpm_table; 334*b843c749SSergey Zigachev 335*b843c749SSergey Zigachev bool cac_enabled; 336*b843c749SSergey Zigachev bool battery_state; 337*b843c749SSergey Zigachev bool is_tlu_enabled; 338*b843c749SSergey Zigachev 339*b843c749SSergey Zigachev uint32_t low_sclk_interrupt_threshold; 340*b843c749SSergey Zigachev 341*b843c749SSergey Zigachev uint32_t total_active_cus; 342*b843c749SSergey Zigachev 343*b843c749SSergey Zigachev struct vega10_display_timing display_timing; 344*b843c749SSergey Zigachev 345*b843c749SSergey Zigachev /* ---- Vega10 Dyn Register Settings ---- */ 346*b843c749SSergey Zigachev 347*b843c749SSergey Zigachev uint32_t debug_settings; 348*b843c749SSergey Zigachev uint32_t lowest_uclk_reserved_for_ulv; 349*b843c749SSergey Zigachev uint32_t gfxclk_average_alpha; 350*b843c749SSergey Zigachev uint32_t socclk_average_alpha; 351*b843c749SSergey Zigachev uint32_t uclk_average_alpha; 352*b843c749SSergey Zigachev uint32_t gfx_activity_average_alpha; 353*b843c749SSergey Zigachev uint32_t display_voltage_mode; 354*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_a; 355*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_b; 356*b843c749SSergey Zigachev uint32_t dcef_clk_quad_eqn_c; 357*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_a; 358*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_b; 359*b843c749SSergey Zigachev uint32_t disp_clk_quad_eqn_c; 360*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_a; 361*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_b; 362*b843c749SSergey Zigachev uint32_t pixel_clk_quad_eqn_c; 363*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_a; 364*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_b; 365*b843c749SSergey Zigachev uint32_t phy_clk_quad_eqn_c; 366*b843c749SSergey Zigachev 367*b843c749SSergey Zigachev /* ---- Thermal Temperature Setting ---- */ 368*b843c749SSergey Zigachev struct vega10_dpmlevel_enable_mask dpm_level_enable_mask; 369*b843c749SSergey Zigachev 370*b843c749SSergey Zigachev /* ---- Power Gating States ---- */ 371*b843c749SSergey Zigachev bool uvd_power_gated; 372*b843c749SSergey Zigachev bool vce_power_gated; 373*b843c749SSergey Zigachev bool need_long_memory_training; 374*b843c749SSergey Zigachev 375*b843c749SSergey Zigachev /* Internal settings to apply the application power optimization parameters */ 376*b843c749SSergey Zigachev uint32_t disable_dpm_mask; 377*b843c749SSergey Zigachev 378*b843c749SSergey Zigachev /* ---- SMU9 ---- */ 379*b843c749SSergey Zigachev struct smu_features smu_features[GNLD_FEATURES_MAX]; 380*b843c749SSergey Zigachev struct vega10_smc_state_table smc_state_table; 381*b843c749SSergey Zigachev 382*b843c749SSergey Zigachev uint32_t config_telemetry; 383*b843c749SSergey Zigachev uint32_t acg_loop_state; 384*b843c749SSergey Zigachev uint32_t mem_channels; 385*b843c749SSergey Zigachev uint8_t custom_profile_mode[4]; 386*b843c749SSergey Zigachev }; 387*b843c749SSergey Zigachev 388*b843c749SSergey Zigachev #define VEGA10_DPM2_NEAR_TDP_DEC 10 389*b843c749SSergey Zigachev #define VEGA10_DPM2_ABOVE_SAFE_INC 5 390*b843c749SSergey Zigachev #define VEGA10_DPM2_BELOW_SAFE_INC 20 391*b843c749SSergey Zigachev 392*b843c749SSergey Zigachev #define VEGA10_DPM2_LTA_WINDOW_SIZE 7 393*b843c749SSergey Zigachev 394*b843c749SSergey Zigachev #define VEGA10_DPM2_LTS_TRUNCATE 0 395*b843c749SSergey Zigachev 396*b843c749SSergey Zigachev #define VEGA10_DPM2_TDP_SAFE_LIMIT_PERCENT 80 397*b843c749SSergey Zigachev 398*b843c749SSergey Zigachev #define VEGA10_DPM2_MAXPS_PERCENT_M 90 399*b843c749SSergey Zigachev #define VEGA10_DPM2_MAXPS_PERCENT_H 90 400*b843c749SSergey Zigachev 401*b843c749SSergey Zigachev #define VEGA10_DPM2_PWREFFICIENCYRATIO_MARGIN 50 402*b843c749SSergey Zigachev 403*b843c749SSergey Zigachev #define VEGA10_DPM2_SQ_RAMP_MAX_POWER 0x3FFF 404*b843c749SSergey Zigachev #define VEGA10_DPM2_SQ_RAMP_MIN_POWER 0x12 405*b843c749SSergey Zigachev #define VEGA10_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15 406*b843c749SSergey Zigachev #define VEGA10_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E 407*b843c749SSergey Zigachev #define VEGA10_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF 408*b843c749SSergey Zigachev 409*b843c749SSergey Zigachev #define VEGA10_VOLTAGE_CONTROL_NONE 0x0 410*b843c749SSergey Zigachev #define VEGA10_VOLTAGE_CONTROL_BY_GPIO 0x1 411*b843c749SSergey Zigachev #define VEGA10_VOLTAGE_CONTROL_BY_SVID2 0x2 412*b843c749SSergey Zigachev #define VEGA10_VOLTAGE_CONTROL_MERGED 0x3 413*b843c749SSergey Zigachev /* To convert to Q8.8 format for firmware */ 414*b843c749SSergey Zigachev #define VEGA10_Q88_FORMAT_CONVERSION_UNIT 256 415*b843c749SSergey Zigachev 416*b843c749SSergey Zigachev #define VEGA10_UNUSED_GPIO_PIN 0x7F 417*b843c749SSergey Zigachev 418*b843c749SSergey Zigachev #define VEGA10_THERM_OUT_MODE_DISABLE 0x0 419*b843c749SSergey Zigachev #define VEGA10_THERM_OUT_MODE_THERM_ONLY 0x1 420*b843c749SSergey Zigachev #define VEGA10_THERM_OUT_MODE_THERM_VRHOT 0x2 421*b843c749SSergey Zigachev 422*b843c749SSergey Zigachev #define PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT 0xffffffff 423*b843c749SSergey Zigachev #define PPREGKEY_VEGA10QUADRATICEQUATION_DFLT 0xffffffff 424*b843c749SSergey Zigachev 425*b843c749SSergey Zigachev #define PPVEGA10_VEGA10GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 426*b843c749SSergey Zigachev #define PPVEGA10_VEGA10SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 427*b843c749SSergey Zigachev #define PPVEGA10_VEGA10UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 428*b843c749SSergey Zigachev #define PPVEGA10_VEGA10GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */ 429*b843c749SSergey Zigachev 430*b843c749SSergey Zigachev #define VEGA10_UMD_PSTATE_GFXCLK_LEVEL 0x3 431*b843c749SSergey Zigachev #define VEGA10_UMD_PSTATE_SOCCLK_LEVEL 0x3 432*b843c749SSergey Zigachev #define VEGA10_UMD_PSTATE_MCLK_LEVEL 0x2 433*b843c749SSergey Zigachev 434*b843c749SSergey Zigachev extern int tonga_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr); 435*b843c749SSergey Zigachev extern int tonga_hwmgr_backend_fini(struct pp_hwmgr *hwmgr); 436*b843c749SSergey Zigachev extern int tonga_get_mc_microcode_version (struct pp_hwmgr *hwmgr); 437*b843c749SSergey Zigachev extern int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr); 438*b843c749SSergey Zigachev extern int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display); 439*b843c749SSergey Zigachev int vega10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input); 440*b843c749SSergey Zigachev int vega10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); 441*b843c749SSergey Zigachev int vega10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); 442*b843c749SSergey Zigachev int vega10_update_acp_dpm(struct pp_hwmgr *hwmgr, bool bgate); 443*b843c749SSergey Zigachev int vega10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); 444*b843c749SSergey Zigachev int vega10_enable_smc_features(struct pp_hwmgr *hwmgr, 445*b843c749SSergey Zigachev bool enable, uint32_t feature_mask); 446*b843c749SSergey Zigachev 447*b843c749SSergey Zigachev #endif /* _VEGA10_HWMGR_H_ */ 448